Silos – Verilog Simulator
Contents
1. SILVACO SILOS Verilog Simulator 64 Data Tips fl File View Project Code Coverage Debug State Machine Explorer Window Help x 1 i i lt Scan to Change gt Silos c silos examples rtl_spj vendtest v Scope stimulus Filter File Edit View Project Code Coverage Debug State Machine Explorer newspaper 1 enable Reports Options Window Help lej x Copy Scope Ctrl C E Select Scope i E 0 akse cc ss Command Instance Mame Filter P er timescale ins 1ns EIA module stimulus For Help press F1 j i reg click Select instance stimulus open reg clock Sti re st the context menu with the right J tel sete mouse button and then select radix hex time 0 740us 4 IF T1 0 740us Time 1 540us REZ Go to stimulus Data Tips display value scope radix and simulation time point for variable clock The time point can be set by the T1 timing marker in the Data Analyzer The Data Tips can be turned on off and the radix can be changed by using the context menu in the source window SILVACO T2 0 780us SILOS Verilog Simulator 65 Agenda Advanced Debugging Features Introduction Starting Silos Project Explorer and Analyzer Source Code Debugging State Machine Design Entry Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 66 cl2. Senet Display Iteration Data Go to Definition coin 1 nickel none Jj nickel j none Delete Grou newsp Insert Group NEXT_ Show Groups lA A cents j j Jj l cents PRES Hide Selected Group 4 cents J J cents info 96 Move Group Up Alt Up Arrow addingcons j j Move Group Down Alt Down Arrow gt Padia 1 f2 frdelta Num y Click with right mouse button in Signal list Box Selections for groups SILVACO SILOS Verilog Simulator 58 Conditional Search Specify Signal Expression x stimulus Cancel Silos c Nsiloskexamples Mil spj Data Analyzer Gi ES File Edi Wiew Project Code Coverage Debug Explorer Reports Options Window Help 2 x amp amp amp lt 2 lt i Scan to Change reo y D 555us 745us p 335us Signal or Expression Default 1 1 1 E LL 4 Se 1 X Y 1 1 X 4 1 2 clock amp amp coin 1 clock Ss Stl reset s t0 coin 1 0 S none none j jj none j j none j j clk news 1 OAT ONT OAT ONT KOAT 0 3 2 11 AONT KOKLO AI XOT XOKI newspaper sto S NEXT STATE I 0 Y Ocents cents JY5cents Y cents O PRES STATE 1 0 Y Ocents cents 5cents j 5 Qcents info 96 1 s ne faddingcoins adding coins stimulus clock amp amp coin 1 clk news 4 n For Help press F1 Ti 12 Tdelta Time 1 540us NUM 4 Expression clock amp amp coin 1 Notice that if you
3. Compliant to VERILOG 2001 Introduction Starting Silos Project Explorer and Analyzer Source Code Debugging State Machine Design Entry Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 2 What is Silos Es EIE Wh Me EU x i wt m3 Verilog IEEE 1364 Digital Logic Simulator Analysis and Debugging Environment Waveform Viewer Hierarchical Browser Text editor Code Coverage Finite State Machine Tool Single Step with Breakpoints Trace Gate and RTL events SILVACO SILOS Verilog Simulator 3 Digital Front End Simulation Control Verilog HDL Synthesis Netlist Scripting Control Processor Language Netlist Controls Gate level Options Simulation Logic bes Placement m Tiber Synthesis os d Tapeout Waveform RTL Viewer Simulation Timing Estimate C Timing Results Digital Cell Library gt Cell Synthesis Verilog Routing SA Verilog Test Scan Test Bench Libraries Libraries Tech Files LEF DEF Decks Models SILOS Verilog Simulator 4 Silos Platforms Silos supports Windows SUN Solaris Linux platforms SILVACO SILOS Verilog Simulator 5 Silos Markets Current FPGA Xilinx Altera QuickLogic Actel etc PLD General Digital Logic Future Analog Mixed Signal SILVACO SILOS Verilog Simulator 6 Agenda Starting Silos Proj
4. SILVACO SILOS Verilog Simulator 28 Explorer Context Menu F Silos c silos examples rtl spj Explorer olx id File View Project Code Coverage Debug State Machine Explorer Window Help 15 xl S La es 9 ES cc ss Command All Modules Scope stimulus vendY Filter E stimulus stimulu JE gt clock vendY vem L 1 0 coin Go to Definition Add Signals to Analyzer Name Filter Sort by Name 4 v Sort by Type For Help press F1 n T2 Tdelta Time 1 540us NUM LZ Context menu use right mouse button u SILVACO 29 Explorer Silos c silos examples rtl spi Explorer is File View Project Code Coverage Debug State Machine Explorer Window Help 18 x El s es KJ aksil cc ss Command All Modules Scope stimulus vendr Filter E stimulus stimulu JE gt clock wendY vem L 1 0 coim Click here to expand and contract hierarchy SILVACO SILOS Verilog Simulator 30 Explorer Silos c silos examples rtl sp Explorer Fe File View Project Code Coverage Debug State Machine Explorer Window Help 18 x bel El LJEd Ol ES cc ss Command All Modules Scope stimulus vendY Filter E stimulus stimulu E clock Use right mouse button to see the context menu SILVACO SILOS Verilog Simulator 31 Agenda Source Code Debugging fete c gt IA Bc 7 rej 4 ri HA 1 D m ma Po V
5. Reports Options Window Help OMARE xX EE stimulus Default clock reset coin 1 0 newspaper T1 0 151us IT2 Tdeka Time 1 450us NUM 7 The minimized Finite State Machine window shows the active state as you scan in the Data Analyzer SILVACO SILOS Verilog Simulator 92 Agenda Gate Level TENE Introduction Starting Silos Project Explorer and Analyzer Source Code Debugging State Machine Design Entry Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 93 Gate Level Debugging I AS A ESOS ERES A XI File Edit View Project Code Coverage Debug Explorer Reports Options Window Help El j amp m cc ss Command BN Data Analyzer Default clock stimulus coin 1 0 stimulus stimulus reset stimulus Output ajoj x For Help press F1 T1 D 021us T2 delta Time 1 540us NUM YW newspaper Highlight signal newspaper and click with the right mouse button in the Signal Name list box Select Trace Signal Inputs when the context menu opens At time 0 021us newspaper changes from Unknown to Low SILVACO SILOS Verilog Simulator 94 Gate Level Debugging Silos c silos examples gate spj Trace Signal Inputs File Edit View Project Code Coverage Debug Explorer Reports Options Window Help cC ajajaja Scan to Change 1 gt 2 n re e Ssp N
6. click on the expression a second time you can modify the expression SILVACO SILOS Verilog Simulator 59 Data Analyzer Scan Buttons Scan left buttons Scan Value Scan right buttons Silos c isilostexamplestril spj Data Analyzer O File Edit View Project Code Coverage Debug Explorer Reports Options Window Help x ajajaja oa gt e 11 12 20 Ssp Name 224us 244us A Default clock Stl reset Sl coin 1 0 nickel clk news 1 newspaper St NEXT STATE 1 0 15 cents PRES STATE 1 0 10 cents clock amp amp coin 1 St0 intAaIMC 11 AA a ja au i For Help press F1 T10 220us T20 240us Tdelta0 020us Time 1 460us ne ay SILVACO SILOS Verilog Simulator 60 SILOS Verilog Simulator Data Analyzer Timescale Silos c silos examples rtLspj Data Analyzer EJ File Edit View Project Code Coverage Debug Explorer Reports Options Window Help 8 ajajaja a TTTETESITTE d EXE n re o 55 EE NEN Scan to Change 0 224us 244us Default Enter Scan Value SE perse area ee rer eee eei clock Sul reset Std coin 1 0 nickel clk news 1 newspaper St0 mmm NEXT STATE I 0 15 cents PRES_STATE 1 0 10cents Scents TUcents clock amp amp coin 1 St i i a D la For Help press F1 T T1 0 220us fr T2 0 240us i delta 0 020us Time 1 460us E SILVACO 61 Data Analyzer Silos c silos examples rtLspj Tel F
7. clock stimulus reset coin 1 0 oe stimulus stimulus newspaper s reset reset m j 1 bx pad stimulus stimulus reset 1 b0 and choose Trace Signal Inputs from the context menu SILOS Verilog Simulator 47 E Trace Signal Inputs stimulus reset stimulus stimulus reset 1 bx stimulus stimulus reset Ei vendtest v always negedge reset if flag 6 begin reset 1 bx end initial 56 reset Ail The Trace Signal Inputs window shows that two statements assigned to register stimulus reset at T 0 055us The first assignment listed in the Trace Signal Inputs window is the last assignment to reset that executed at this time point The second statement listed is the next to last assignment to reset that executed Left mouse clicking on the first statement for reset shows line 27 of file vendtest v is the last line executed SILOS Verilog Simulator 48 Visual Debug E Silos c isilostexamplestrtl spj File Edit View Project Code Coverage Debug Explorer Reports Options Window Help E aja amp lt a lt i Scan to Change 1 a n re e se Reevaluate combinational logic each time a coin is put or the present state changes assign newspaper NEXT STATE fsm coin PRES STATE clock the state flipflops use synchronous reset always posedge clock begin ZO funca A hax Data Analyzer Default vend stimulus vendY clock e newspaper newspaper
8. more coins to vending mal ine Newspaper is dispensed B vendtest v ES For Help press F1 T1 0 080us T2 Tdelta Time 1 460us Double clicking on the text in the Output window will open the source file SILVACO SILOS Verilog Simulator 19 Output of a Simulation Silos c isilostexamplesirtl_ spj File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help i Li e Fe icc ss Command Output X vue 6 State changes on observable nets Simulation stopped at the end of time 8 888us Ready sim adding coins to vending machine Rdding more coins to vending mal ine Newspaper is dispensed v E vendtest v Af case coin1 6 begin info 1 begin adding coins display Adding more coins to uei newspaper coint 8 display Newspaper is di v E i gt For Help press F1 T1 0 080us T2 Tdelta Time 1 460us and highlight the display statement that caused the text to be printed SILVACO SILOS Verilog Simulator 20 Agenda Explorer and Analyzer Introduction Starting Silos Project Source Code Debugging State Machine Design Entry Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 21 Explorer and Analyzer amp Silos c silos examples rtl spi IDE x File View Project Code Coverage Debug State Machine Explo
9. nand stimulus vendY PRES STATE reg 0 n6 n6 0 Stl 03 St qq sto clr Stl Item is a wire T1 0 020us T2 0 020us Tdelta 0 000us Three input nand gate 1 Double click on the o3 2 input to the nand gate because the High to Low transition on this input caused the output to change u SILVACO 101 Gate Level Debugging Buffer Gate ck File Edit View Project Code Coverage Debug Explorer Reports Options Window Help amp amp amp amp e amp Scan to Change Dl n re O sd stimulus vendY PRES STATE reg 0 qqbar Stl nand stimulus vendY PRES STATE reg 0 n6 n6 0 Stl 03 St qq sto clr Stl Item is a wire T1 0 020us T2 0 020us Tdelta 0 000us Three input nand gate 1 Double click on the ck 2 input to the nand gate The Low to High change on ck caused the nano gate to change u SILVACO 102 Gate Level Debugging TENE A41 El O o fi File Edit View Project Code Coverage Debug Explorer Reports Options Window Help ajajaja Scan to Change 1 gt 2 gt T1 T2 3 Ssp MEA stimulus vendY PRES_STATE_reg 0 ck St buf stimulus vendY PRES STATE reg 0 B5 B5 0 sto sto Item is a wire T10 047us T2 0 020us Tdelta 0 027us Buffer gate 1 The original unknown to low transition has been traced back to signal clock in the testbench SILVACO SILOS Verilog Simulator 103 Silos c silos examples rtl err spj OF
10. stimulus Stl stimulus 0 A ees 1 0 coin 1 stimulus coin 0 stimulus newspaper stimulus SUX EXA NEXT STATE 1 0 stimulus vendY x xh O 3 142241 PRES STATE 1 0 stimulus vendY x xh Of 1 gt For Help press F1 T1 T2 Tdelta Time 1 540us NUM Z Double click on vector coin 1 0 to expand and hide the bits SILVACO SILOS Verilog Simulator 51 Agenda State Machine nt Entry Introduction Starting Silos Project Explorer and Analyzer Source Code Debugging Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 52 State Machine Values ORT s Silos c silos examples rtl spj Data Analyzer OF x E Eile Edit View Project Code Coverage Debug Explorer Reports Options Window Help a x a amp jajajal lt lt Scan to Change 1 gt e Trete Name SE ACI Default reset st Symbol T able v Cancel coin 1 0 St Symbol T able jnickelj newspaper st NEXT STATE 1 0 str TETTE Ru 141412711 PRES STATE 1 0 stimulus vendY x FT MH y 1 For Help press F1 T1 T2 Tdelta Time 1 540us NUM Y Select coin 1 07 Use the drop down arrows to display Right mouse click to see context Symbol Table and coin_values menu Then select Set Radix SILVACO SILOS Verilog Simulator 53 State Machine Values PELs I3 E UBER T4 Make sure you click on the File Edi
11. ES File Edit View Project Code Coverage Debug State Machine Explorer Reports Window Help S i f 3184 kA cc ss Command Reading venderr u C Silos Examples venderr v 8 error 3 229 expecting 3 Reading vend u TI n Oh ll error 2 188 errors are too seuere to simulate Ready sim 4 b A For Help press F1 T1 T2 Tdelta Time 0 NUM Y Double click on the error message to automatically open the source file and see the error SILVACO SILOS Verilog Simulator 104 missing from module header reg clock Silos Ill highlights the next line because the error could not be detected until that line is interpreted UD Error is caused by semicolon missing from the module header SILOS Verilog Simulator 105 Errors Silos c silos examples rtl_ernr spj BptA amp 043 THP File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help 18 x EA e se e ELLE css omes 4 error 3 229 line 8 file C XSilosXExamplesXuenderr v reg clock expecting A a or p error 2 188 sim to 6 errors are too severe to simulate For Help press F1 T1 T2 Tdelta Time 0 NUM A Error report for Silos Ill SILVACO SILOS Verilog Simulator 106 Analog Waveforms Silos c silos examples analog spj Data Analyzer OF x File Edit View Project Code Coverage Debug Explorer Reports Options Win
12. S of T Adding coins to vending machine fidding more coins to vending machine Newspaper is dispensed Start logic simulation T1 T2 Tdelta Time 1 460us NUM 4 Press Go button F5 SILVACO SILOS Verilog Simulator 16 Starting a Simulation Silos c silos examples rtl spj E o Of x File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help sju els e aleja c Command Adding coins to vending machine fidding more coins to vending machine Newspaper is dispensed Start logic simulation T1 T2 Tdelta Time 1 460us NUM 4 SS Button for Singe Stepping SILVACO SILOS Verilog Simulator 17 Starting a Simulation al BL xl File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help Sal ejfe e e E E cc ss Command Silos c silos examples rtl spj Adding coins to vending machine fidding more coins to vending machine Newspaper is dispensed Start logic simulation T1 T2 Tdelta Time 1 460us NUM Z Output Window SILVACO SILOS Verilog Simulator 18 Output of a Simulation Silos c isilostexamplestrtl_ spj Cel File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help S E a e Fl icc ss Command ala il A e a vue 6 State changes on observable nets Simulation stopped at the end of time 6 666us Adding
13. St ea AA PRES_STATE 1 0 0 reset Sto d PRES_STATE Q P coin 1 coin 1 0 Item is a register bit T1 0 020us T2 0 020us Tdelta 0 000us Tracing on newspaper in the Data Analyzer brings up the Trace Signal Inputs window which shows PRES_STATE 1 0 and coin 1 are the right hand side rhs variables that assign the value for newspaper Double clicking on PRES_STATE 1 will refresh the Trace Signal Inputs window put PRES STATE 1 at the top and display the rhs variables for PRES_STATE 1 SILVACO SILOS Verilog Simulator 49 Report Generation 1 2 gt amS D 000us 120us Default clock stimulus Std stimulus 0 e Sy E newspaper stimulus six EX reset stimulus stl NEXT_STATE 1 0 stimulus vendY x xi 0 1142 PRES_STATE 1 0 stimulus vendY x xi Of 41 IT Copy window image to clipboard T1 T2 Tdelta Time 1 540us NUM y Select the Edit Copy Image to Clipboard menu to copy the Data Analyzer so it can be pasted into MS Word You can use the Edit Copy menu or Ctrl C on the keyboard to copy the full path name for a signal to the clipboard SILVACO SILOS Verilog Simulator 50 Vector d Silos c silos examples rtl sp Data Analyzer IDE XI File Edit View Project Code Coverage Debug Explorer Reports Options Window Help Z 81 x Aa Jaja Sean to Change 1 gt 2 Tene e Default clock stimulus Sto reset
14. TATE to 3 SILVACO SILOS Verilog Simulator 70 Breakpoints Breakpoints Type Break at Location Y Break at Simulation Time Location Break at Location Break in Module Instance Expressiorr Break in Module Any Instance SUBE stimulus imenont Breakpoints cSsillos3vexamplessvendtest v 51 SILVACO SILOS Verilog Simulator 71 Put the cursor on this line and click on the Toggle Breakpoint button 1 to set the red breakpoint stop sign SILOS Verilog Simulator 72 Code Coverage button should be depressed Double click on the first line in the Operator report to open the source file at that line Lines not executed have a purple dot 2 Click on a column header to change the sort order SILOS Verilog Simulator 73 code covera ge always out H1 out2 out A large number of hits in the Code Coverage Line Report may indicate a looping problem in the user s design such as always out out out2 out1 SILOS Verilog Simulator 74 C ASilos E xamples code coverage c Export Code Coverage Data dialog box can use comma separated data files for importing into a spreadsheet program such as Microsoft Excel SILOS Verilog Simulator 75 E Qe testbench testbench CC select ABCD select 5 IV Save code coverage data for this entry In the Explorer the red circle with the slash through it means code coverage is disable
15. You can then left mouse click on the waveform for clock to see the statement that caused clock to toggle 3 SILOS Verilog Simulator 37 Visual Debug Time Point for Tracing Signal Silos c silos examples rtLspj File Edit View Project Code Coverage Debug Explorer Reports Options Window Help c amp Ole e EB cc ss Command ajajaja lt lt end AAA X Reevaluate combinational logic each time a coin is put or the present state changes paper NEXT STATE fsm coin PRES STATE clock the state flipflops use synchronous reset oes Minaradan n nnl d i m S Data Analyzer BAR E Trace Signal Inputs Bele J ES 4 me fe S A 4 LI 4 1 1 4 4 4 A 4 4 4 0 000us 4 j Default PKA ENEE OEEO EENE clock coin 1 0 ESC LIC RARAS Trace Signal Inputs A Display Iteration Dig Go to Definition Mew Group For Help press F1 T1 0 057us T2 Tdelta Setting the blue T1 marker 1 determines the time point for tracing a signal Right mouse clicking on the name newspaper brings up the context menu 2 SILVACO SILOS Verilog Simulator 38 Visual Debug Trace Signal Inputs 3 Silos c silostexamplesirtl spj File Edit View Project Code Coverage Debug Explorer Reports Options Window Help cii Of e Ejrjm ccfss Commana Q lalalal lt 2 ee endfunction Reevaluate combinational logic each time a coin is put or the present state changes assign newspap
16. bles in the assignment to newspaper are listed below it and indented one space SILOS Verilog Simulator 40 Visual Debug Status Window Silos c isilostexamplestril spj File Edit View Project Code Coverage Debug Explorer Reports Options Window Help aja amp amp Scan to Change 1 2 gt 11 12 20 Esp Data Analyzer Default clock coin 1 0 newspaper reset pad stimulus pad vend stimulus vendY pad pad enable enable1 clock clock stimulus stimulus a pad B vendtest v enable reg reset flag clock wire newspaper reg 96 1 info reg enable enable1 wire pad enable clock 1 bz ZZ bidirectional pad instantiate the vending state machine vend vendY coin clock reset newspaper pad enable1 lii MEE ST D e Re EE RE ieee T1 0 040us T2 0 040us Tdelta 0 000us Red flashing message in status window warns user of multiple drivers or assignments at a time point while Show Source is on SILVACO SILOS Verilog Simulator 41 Default clock coin 1 0 newspaper reset pad To find the cause of the Unknown level on pad right mouse click on the signal named pad SILOS Verilog Simulator 42 Default clock coin 1 0 E vend stimulus vendY stimulus pad newspaper s pad pad reset enable enable1 pad clock clock stimulus stimulus pad enable clock Ail and cho
17. by moving the mouse cursor tangentially across the transition line with the left mouse button held down SILVACO SILOS Verilog Simulator 86 The symbols are for positive edge clock and reset lines Click on the 4 sign to change it to a sign for a negative edge reset clock SILVACO SILOS Verilog Simulator 87 Notes can be used to document output signals on the diagram SILOS Verilog Simulator 88 FSM Debugging File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help 8 xj OTE xXx GG stimulus Itl Es El se 9 akse cc ss Command module stimulus reg clock reg 1 8 coin reg reset reg newspaper include vending v 4 For Help press F1 T1 T2 Tdelta Time 1 450us NUM Y The include vending v compiler directive is used to include the Verilog HDL source code for the newspaper vending FSM SILVACO SILOS Verilog Simulator 89 SILOS Verilog Simulator 90 Open Instance button As the T1 timing marker is dragged in the Data Analyzer the states change color as they become active FSM Scan button To select states for scanning click on the state with the left mouse button and hold down the Ctrl key SILOS Verilog Simulator 91 FSM pa Finite State Machine Window File Edit View Project Code Coverage Debug Explorer
18. chine FSM Entry State 1 of UnSay cata73s71 21 22 05 on Tuesday July 25 2000 SOK lt ADD YOUR CLOCK EXPRESSION HERE gt Use the left mouse button when the State Mode is active to create the two states SILVACO SILOS Verilog Simulator 82 FSM Entry Transition Mode is Transition Mode button SILVACO SILOS Verilog Simulator 83 FSM Entry Transition Mode Notice the small circle on state s1 for drawing the transition between s1 and s2 The circle will move along s1 as the mouse is moved SILVACO SILOS Verilog Simulator 84 FSM Entry Transition Mode id Ae R i EN df B SILOS c silos3 examples simple_fsm _spj Fsm Dx Transition between states 3 File Edit View Project State Machine Window Help s2 and s1 will change at mo MIX 4 the next positive clock edge CLOCK ADD YOUR CLOCK EXPRESSION HERE gt because the expression has been deleted Ch Notice a state symbol can be moved when there is a circle with cross hairs If instead you see a star on the state symbol this will change the shape of the state symbol instead of moving it SILVACO SILOS Verilog Simulator 85 FSM Entry Transition Mode SILOS c silos3 examples simple_fsm spj Fsm 3 File Edit View Project State Machine Window Help Col mNI5X amp 34 CLOCK ADD YOUR CLOCK EXPRESSION HERE gt The transition can be redrawn
19. d AN gt gt gt EI l vendtest v reg enable enable1 vire pad instantiate the vending state machine nand nondV frenin ciarb racat noancnanor _ reset NEXT_STATE 1 0 1 For Help press F1 T2 SILOS Verilog Simulator 35 Aaa 77 bidi Highlight expression enable clock 1 bz and drag and drop it into the Data Analyzer to see the waveform for the expression SILVACO Rearranging Signal Drag and Drop S TUS SEAN 7773 Lime Default clock stimulus St stimulus Stl EX coin 1 stimulus 0 newspaper stimulus SUX NEXT STATE 1 0 stimulus vendY x PRES STATE 1 0 stimulus vendY x Item is a register Rearrange the signal names by dragging and dropping them in the Signal Name list box SILVACO SILOS Verilog Simulator 36 Show Source Code ajaja 4 lt e lt 1 Scan to Change 1 25 Ti re e Data Analyzer DER El PRA Default i m always clock begin P f 26 clock clock coin 1 0 a newspaper reset All gt 2 Explorer All Modules Scope stimulus Filter TO 8 00 stimulus stimulus newspaper 1568 8 1566 8 finish in file C silos examples ve 736 State changes on obseruable n Simulation stopped at the end of For Help press F1 T1 0 048us T2 Tdelta If Show Source in inactive SSF button not depressed 1 holding down the Ctrl key will temporarily activate Show Source 2
20. d for this instance The green CC means code coverage is enabled SILOS Verilog Simulator 76 O if A gt B C lt D else if C gt D J Operator gt ki rover wt The and the operators failed to be true When expressions have more than one operator you can use separate lines to display the purple dot for each failed operator SILOS Verilog Simulator 77 Operator left operand never independently toggles result right operand never independently toggles result Deselecting the DEFAULT option and selecting the other options for the Operator report will show which operands did not affect their corresponding operator SILOS Verilog Simulator 78 code batch2 codecov Code coverage results can be merged from batch simulations that use different test benches for the same design SILOS Verilog Simulator 79 Agenda Finite State Machine Example fete c PC AES Bc pay 4 Ai dir Introduction Starting Silos Project Explorer and Analyzer Source Code Debugging State Machine Design Entry Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 80 Finite State Machine FSM Entry State 1 of UnSay cata73s71 21 22 05 on Tuesday July 25 2000 SOK lt ADD YOUR CLOCK EXPRESSION HERE gt FSM Toolbar State drawing button SILVACO SILOS Verilog Simulator 81 Finite State Ma
21. dow Help 8 x ajajaja lt e lt 1 ean to Change gt pue e I 000us 65 0 090us ETT i 72 1 Default clock top sto down_up top St top 0 000 Stepping function display of analog signal feedback top 0 000 X Piece wise linear l display of analog counter_value top 0 OOOO OU signal count 7 0 top xx ae IA IATA AAA aaa TATATA ATATA ATATA ATA C 0 MDC WMTRW08 VTWTEOM E a For Help press F1 T1 T2 Tdelta Time 180 000us NUM Z7 Double click to toggle between stepping function and piece wise linear SILVACO SILOS Verilog Simulator 107 Silos Advanced Features e Supports Industry Standard PLI 1 0 Interface Currently implementing PLI 2 0 Silos supports the SDF language as defined by the IEEE 1497 standard for SDF Silos also supports a commonly used extension used to specify the SDF file of delay values the sdf annotate system task e sdf annotate file name module instance Interface for SystemC SILVACO SILOS Verilog Simulator 108 Silos Future Analog Mixed Signal Solution Silos AMS beta release in May 2004 ntegrated power of SmartSpice Solver improvements for simulation speed Common Silos GUI on WINDOWS SUN and LINUX platforms STA Static Timing Analyzer capability September 2004 SILVACO SILOS Verilog Simulator 109 Analog and Mixed Signal Design Flow 3 PES gt SIIVACO Analog Library De
22. ect Introduction Starting Silos Project Explorer and Analyzer Source Code Debugging State Machine Design Entry Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 7 B Silos File View Project Code Coverage Debug State Machine Explorer Reports Window B365 mE amp e ss e lrg ccfss Command de Quick Start Guide New Features User s Manual Verilog LRM SDF Manual User Registration About Silos List Help topics T1 T2 Tdelta Contents will display the contents for the Silos User s Manual The New Features menu provides a short help file on the new features for the Silos release SILOS Verilog Simulator 8 B Silos File View Project Code Coverage Debug State Machine Explorer Reports Window B365 Saj 0 cc ss Command Contents Using Help Quick Start Guide New Features User s Manual Verilog LRM SDF Manual V is rs Registration About Silos T1 T2 Tdela User Registration will show the security block number SILOS Verilog Simulator B Silos File View Project Code Coverage Debug State Machine Explorer Reports Window B365 Saj 0 cc ss Command Contents Using Help Quick Start Guide New Features User s Manual Verilog LRM SDF Manual User Registration T1 T2 Tdelta About Silos will show the memory usage and version number SILOS Ve
23. er NEXT STATE fsm coin PRES STATE clock the state flipflops use synchronous reset Aem Minaradana nnn X Data Analyzer EIS COR asy Ive ERES 0 000us 1 1 1 4 1 1 82024 92 4 9 4 074 9 4 0 0 9 4 04 04 9 4 Default clock coin 1 0 een SASN SAINI NININA INTALNITA EE Trace Signal Inputs Display Iteration Di Go to Definition New Group For Help press F1 T1 0 057us Tdelta Selecting the Trace Signal Inputs menu selection opens the Trace Signal Inputs window 3 SILVACO SILOS Verilog Simulator 39 stimulus newspaper Sto vend stimulus vendY newspaper newspaper St0 PRES_STATE 1 0 0 coin 1 coin 1 0 The top signal stimulus newspaper is the signal being traced The next line is the module name vend and instance name stimulus vendY which drives the top signal The next line is the driver or assignment in the instance Subsequent lines indented with a space are the inputs or right hand side rhs variables to the driver assignment If the driver or rhs variable is a port of the instance it is shown using port name syntax If it is not a port then just the name of the variable is listed The signal name preceded by the period newspaper is the local port name in module vend The name in the parenthesis newspaper is the name in the module above stimulus vendY Signal names coin 1 and wire PRES_STATE 1 0 the rhs varia
24. ie Edit View Project Codecove 1 and T2 timing markers set by the left ajajaja ela EMG gown the shift key to snap to edge mure ne Default clock reset coin 1 0 clk news newspaper NEXT STATE 1 0 PRES_STATE 1 0 clock 2 coin 1 int In C1 ei or Help press F1 Value for the signal nickel EE dE d IT1 0 220us and right mouse buttons respectively Hold CLAUS caaus Enter Scan Value Stl St0 1 St0 15 cents 10 cents Std we n EA Tme1 460us Z T2 0 240us Tdelta 0 020us T1 T2 and delta time SILVACO SILOS Verilog Simulator Data Analyzer Scan to Value i Silos c silos examples rtl spj Data Analyzer ajajaja ejal El Default clock stimulus reset stimulus coin 1 0 stimulus clk_news newspaper stimulus stimulus ve 5 cents PRES_STATE 1 0 stimulus ve ls 5 cents info 96 1 stimulus adding coins newspaper clock amp amp coin 1 stimulus Scan to value does a character search so you can scan a signal that is a single bit a vector or that uses symbolic names SILVACO SILOS Verilog Simulator 63 Data Analyzer Pan Buttons Pan to T1 button Pan to T2 button Pan Last i Silos c silos examples rtl spj Data Analyzer ajajajaj ela fiscens gt Scope stimulus stimulus stimulus 15 cents oo cts stimulus adding coins newspaper clock amp amp coin 1
25. ilos examples rtl spi File Edi View Project Code Coverage Debug Explorer Reports Options Window Help gi eje 9 Ei ccfss Commana Default clock i d Toi clock i sn scope stimulus vendY reset 1 b1 radix hex time 0 020us stimulus clock always stimulus vendY reset 1 b1 begin 26 clock clock y 14 stimulus clock setup clock cycle time i Explorer aliai x Output aliai x For Help press F1 T1 D 711us T2 0 780us Tdelta 0 069us Time 0 020us NUM Lo Drag and drop expression reset 1 b1 1 into the Data Analyzer 2 and Watch Windows 3 SILVACO SILOS Verilog Simulator 69 Set and Force 41 Hae gt AM Silos c silos examples rtl spi Iof x File View Project Code Coverage Debug Explorer Window Help El et j alsm cc ss Command u e pena ren ak 15 cents fe ESA El vend v begin Default if reset 1 b1 nck gt Wisse else clock St0 i PRES STATE nora zin EEA E Register Value Cancel Note amd stimulus clock stimulus clock R dpt stimulus vendr reset 1 b1 Force wire Stae stimulus vendY PRES_STATE 3 Wie Foree SA m2g clock clock y A G Setwire State simulation step in Explorer For Help press F1 T1 D 711us T2 D 780us Tdelta 0 069us gt Time 0 020us NUM LZ Set the value for register PRES S
26. ine was stimulus newspaper St VAND stimulus vendY U118 0ut stimulus newspaper st0 nu h St Item is a wire T1 0 021us T20 020us Tdelta0 001us The top signal stimulus newspaper is the signal being traced The next line is the module name VAND and instance name stimulus vendY U118 which drives the top signal The next line is the driver in the instance Subsequent lines indented with a space are the inputs to the driver If the driver is a port of the instance it is shown using port name syntax If it is not a port then just the name of the net is listed The signal name preceded by the period out is the local port name in module VAND The name in the parenthesis stimulus newspaper is the wire name in the module above stimulus vendY U118 Signal name out is listed below it and indented one space SILVACO SILOS Verilog Simulator 95 To view the full signal name use the mouse to drag the vertical bars and increase the size of the Name column SILOS Verilog Simulator 96 and stimulus vendY U118 andS1 Two input and gate Gate instance name The 1 at the end of the name is an IEEE naming convention for gates that do not have instance names SILOS Verilog Simulator 97 inO PRES_STATE O inO is the local name for the input pin A PRES_STATE O is the wire name in the module above stimulus vendY U118 Since both inputs change from Unkn
27. ock cycle time 46 units always begin 26 clock clock E gt end ascii vector to explain stimulus always coin begin coind coin1 1 Step to next source statement T1 0 740us T2 0 780us Tdelta 0 040us Time 1 560us NUM Z Click on the Step button to open the source window to the line that is currently executing SILVACO SILOS Verilog Simulator 67 Single Stepping Leads I7 AL f a RAE y E Drag and drop expression clock from file vendtest v 1 to the Data Analyzer and Watch Window 2 Silos c silos examples rtl spj A x File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help Notice the Data Tip m S eje e Exg m cc ss emos shows the instantenous ZN Data Analyzer Output value for expression clock is 0 at the Default 8 clock current timestep n 8 State changes on observable nt sock However the Data E E stopped at the end Analyzer is not updated until the end of the timestep so its value for Name MIvse mode clock is 1 stimulus clod setup clock cycle time 0 always begin 26 clock C end clock 0 scope stimulus radix hex E Explorer amp ni x time 0 020us For Help press F1 110 71lus T20780us Tdelta 0 069us gt Time 0 020us NUM Z 75c0633 nantan ta SILVACO SILOS Verilog Simulator 68 c s
28. on lA e Introduction e Starting Silos Project e Explorer and Analyzer State Machine Design Entry Advanced Debugging Features Finite State Machine Example Gate Level Debugging SILVACO SILOS Verilog Simulator 32 Source Code Waveforms A Silos c isilostexamplestril spj Open File button to open File Edit View Project Code Coverage Debug State Machine Explorer Reports file vendtest yv Options Window Help dEl e 0 al el cel ss Command J Data Analyzer us 4b ddd reset NEXT_STATE 1 0 PRES_STATE 1 0 For Help press F1 SILVACO SILOS Verilog Simulator 33 Source Code Waveforms Silos c isilostexamplestril spj ma ES Double click on variable File Edit View Project Code Coverage Debug State Machine Explorer Reports pad and drag and drop E chee Het bad into the Name column 2 E ELS e Elm cc ss Command to see the waveform E vendtest y reg pees 21 info reg enable1 vire pad SSCA ly eked 77 bidi AS instantiate the vending state machine ond nondV frenin ciarb racat naoancnanar Al J Data Analyzer Er x EI reset NEXT STATE 1 0 PRES STATE 1 0 For Help press F1 m r2 rela SILVACO SILOS Verilog Simulator 34 Source Code Waveforms 5 Silos c isilostexamplestril spj File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help iul ui ole stl eos Comman
29. ose Trace Signal Inputs from the context menu SILOS Verilog Simulator 43 s E Trace Signal Inputs stimulus pad vend stimulus vendY pad pad enable enable1 clock clock stimulus stimulus Unknown level on stimulus pad is caused by both enables being low Left mouse clicking on either driver name pad will highlight the corresponding line of source for that driver SILOS Verilog Simulator 44 Visual Debug stimulus pad Silos c isilostexamplestril spj File Edit View Project Code Coverage Debug Explorer Reports Options Window Help amp amp ld amp Scan to Change 1 2 gt e Esp Z Data Analyzer Default stimulus reset coin 1 0 newspaper reset ae EA 1 bx pad a stimulus stimulus reset clock stimulus stimulus reset l vendtest v Tun always negedge reset if flag 6 begin reset 1 bx end initial 56 reset CERT UCL ule T10 055us T2 Tdelta Red flashing message in status window warns user of multiple drivers or assignments at a time point while Show Source is on SILVACO SILOS Verilog Simulator 45 Value 0 043us Default clock coin 1 0 newspaper reset pad lt To find the cause of the Unknown level on register reset right mouse click on the signal named reset SILOS Verilog Simulator 46 J Trace Signal Inputs Default
30. own to Low at time 0 020us for this example on input inO SILOS Verilog Simulator 98 File Edit View Project Code Coverage Debug Explorer Reports Options Window Help ajajaja Scan to Change 1 gt 11 12 09 5s stimulus vendY U118 in0 Sto buf stimulus vendY PRES STA qAPRES STATE 0 st0 qq Std Ttem is a wire l T1 0 020us T2 0 020us Tdelta 0 000us Buffer gate 1 Double click on the input to the buffer to continue tracing back through the topology SILVACO SILOS Verilog Simulator 99 Gate Level Debugging Buffer Gate qqbar 5 Silos c silos examples gate spj Trace Signal Inputs File Edit View Project Code Coverage Debug Explorer Reports Options Window Help ajajaja Scan to Change 1 gt 2 T1 T2 3 Esp LLLI 1 1 p 00us 1 1 000us stimulus vendY PRES STATE reg 0 qq St nand stimulus vendY PRES STATE reg 0 n5 n5 0 sto qqbar Stl 02 Stl pre Stl For Help press F1 T1 0 020us T2 0 020us Tdelta 0 000us Three input nand gate 1 Double click on the qqbar 2 input because the Unknown to High transition on this input caused the output to change SILVACO SILOS Verilog Simulator 100 Gate Level Debugging Buffer Gate o3 File Edit View Project Code Coverage Debug Explorer Reports Options Window Help amp amp amp amp e amp ScantoChange Dl n re O sd stimulus vendY PRES STATE reg 0 qqbar Stl
31. rer Window Help iz Explorer All Modules Scope stimulus Filter stimulus stimulu For Help press F1 m T2 delta Time 1 540us NUM 4 SILVACO SILOS Verilog Simulator 22 Explorer and Analyzer Silos c silos examples rtl spi OF XI Open Analyzer button File View Project Code Coverage Debug State Machine Explorer Window Help Scope stimulus Filter 1 0 coin TY 1 coin i 96 1 info Output For Help press F1 Ti T2 delta Time 1 540us NUM YW SILVACO SILOS Verilog Simulator 23 Explorer and Analyzer O I Select signal clock File View Project Code Coverage Debug State Machine Explorer Window Help Su e els Elm cc ss 2 Explorer All Modules stimulus stimulu Silos c silos examples rtl spj Command Output For Help press F1 Ti T2 Tdelta Time 1 540us NUM LZ l SILVACO SILOS Verilog Simulator Explorer and Analyzer amp Silos c silos examples rtl spi LE Hold down Ctrl or Shift keys File View Project Code Coverage Debug State Machine Explorer Window Help while using the mouse to E eje 0 alme cc ss E Explorer select additional signals Command All Modules Scope stimulus Filter stimulus stimulu ra Output For Help press F1 TI T2 Tdelta Time 1 540us NUM 4 SILVACO SILOS Verilog Simulator Explorer and Analyzer TL A Silos c silos e
32. rilog Simulator 10 B Silos Ele View Broject Code Coverage Debug State Machine Explorer Window Help ki Open N Create a nev Command FES risp Save As ose Save Project State Restore Project State L felgad and Ga AIEE T1 T2 Tdeta NUM 7 Highlight Project New and press and release the F1 key on the SILOS Verilog Simulator keyboard to see the on line help Create a Project a analog spj am rtl err spj a code coverage spj vcd input spj a code coverage2 spj an vending spj a fltsim spj a gate spj aa rtl spj Project name rtl File name rti Save as type sib cien spi Cancel Ai SILVACO SILOS Verilog Simulator 12 Project Files Project Files rtL spj is Double click on a file name to add Look in e examples ck E3 it to project abc 100 v testbench2 v a analog 2 testbench v code coverage v s vcd input v a design v s vend E Faulttst v 2 venderr v a stimulus s vending File name vendtest v Files of type Source xv Cancel File Group owes aa Files Directories in Group Remove Move Down Note You can edit paths to include defined constants that are defined in Project Settings e g topmyMfile SILVACO SILOS Verilog Simulator 13 Project Files Project Files rtl spj Lkn Oemd sje EB E abc 100 a
33. t View Project Code Coverage Debug minus sign to save the new ajaja a Bonn to Change radixes Default clock stimulus St reset stimulus stl coin 1 0 stimulus none newspaper stimulus SU NESARA stimulus vendY S MASSNEXEMISEIMUEstimulus vendY SX N For Help press F1 SILOS Verilog Simulator 54 a Silos c silos examples rtl spi Data Analyzer ajajaj lt el lt scm to change z ala lele stimulus stimulus newspaper stimulus six stimulus vendY StX stimulus vendY Stx Symbolic names for state values for vectors SILOS Verilog Simulator 55 Waveform Annotation f X m i TR CN a 3 Tz oT B fs MN jh 4i i i p File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help 18 x Command ascii vector to explain stimulus always coin begin coind coin1 1 Open File j info 0 1 info adding coins 2 info adding coins 3 begin info neuspaper coin1 8 end y endcase Open an existing file T1 T2 Tdelta Time 1 540us NUM Y Case statement for ASCII vector info SILVACO SILOS Verilog Simulator 56 newspaper NEXT STATE 1 0 Y PRES STATE 1 0 Y 5 cents i s addin ASCII text describes the simulation SILOS Verilog Simulator 57 Grouping Waveforms Sows P pU Trace Signal Inputs
34. testbench2 v a vending_testbench v 2 analog E testbench v s vendtest v a code coverage v E vcd input v a design B vend z Faulttst v x venderr E stimulus v a vending v File name vendtest v Files of type Source v Y Cancel TEREP E E File Group r E Source Files py dll Add Files Directories in Group Remove Move Up Move Down Note Y ou can edit paths to include defined constants that are defined in Project Settings e g top my file SILVACO SILOS Verilog Simulator 14 Project Files Project Files rtLspj Lookin exampes y e Ele EB E abc 100 v testbench2 v a vending testbench v a analog s testbench v a wendtest y E code coverage v vcd input v a design s vend a Faulttst v s venderr v s stimulus s vending File name vendtest v Files of type Library a Cancel File Group Source Fies Add Files Directories in Group Remove vendtest y vend y Move Up Move Down Note You can edit paths to include defined constants that are defined in Project Settings e g topmyMfile SILVACO SILOS Verilog Simulator 15 Starting a Simulation EON 71 Es 25228 wy p Tt Silos co silos examples rtl spj File Edit View Project Code Coverage Debug State Machine Explorer Reports Options Window Help zu HCOE Fl cc ss Command Output E A GO F
35. velopment SILOS Verilog Simulator Specifications Design Exploration Design Capture Verilog A Behavioral Schematic Capture SPICE Simulation 110 Pre layout AMS Post layout AMS a System Verification System Verification Analog Design Physical Design Custom Layout e Transistor level Netlist P p Celis Manual Place 4 Back Annotation Parasitic Extraction Verification SILVACO
36. xamples rtl spi A ES Click with the right mouse File View Project Code Coverage Debug State Machine Explorer Window Help button to open the context 5 4 e ee 0 Cc ss Command menu and select Sort by E Explorer Name Scope stimulus Filter stimulus stimulu Er Y 1 0 coin HEDE Go to Definition it 96 Add Signals to Analyzer jen 4 Name Filter Dutput For Help press F1 t T2 delta Time 1 540us NUM 4 SILVACO SILOS Verilog Simulator 26 Explorer and Analyzer B Silos c silos examples rtl spi PII E3 Drag and drop signals to File View Project Code Coverage Debug State Machine Explorer Window Help m Nam e list b OX in D ata Sul ej eje Eile cc ss Command Analyzer E Explorer All Modules Scope stimulus Filter stimulus stimulu lO x 120us 240us For Help press F1 T1 T2 Tdelta Time 1 540us NUM LZ SILVACO SILOS Verilog Simulator 27 Explorer Symbols ES T F ey AL Silos c silos examples rtl sp Ex E gt Input ports point right is File View Project Code Coverage D Help lt Output ports point left All Modules Scope stimulus vendy Non port variable symbols E stimulus stimulu gt clock Vendy vem L 1 0 coin l l dumbell symbol is a wire flop symbol is a register is a real variable is a parameter Aaa dl is an integer 4 gt _ For Help press F1 a Eres Dr
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