AN2148: Design Considerations for Interfacing SDRAM with
Contents
1. SDCTRL Ox FF FFFC04 SDRAM Control Register Table 7 8 SDPWDN Ox FF FFFCO6 SDRAM Power down Register Table 7 10 For certain registers only some of the fields are relevant to SDRAM operation Table 4 lists the relevant fields for each register Table 4 SDRAM Registers Relevant Fields Name Description Relevant Fields CSD Chip Select Register D COMB DRAM BSW WS3 1 SIZ EN CSCTRL1 Chip Select Control Register 1 DSIZ3 CSCTRL2 Chip Select Control Register 2 ECDD ECDT DRAMC DRAM Control Register EN RM CLK PGSZ LSP RST 3 1 Chip Select Registers When the DragonBall VZ is configured to use SDRAM chip select group D 1 0 is used for SDRAM chip selects At the same time chip select group C 1 0 becomes the SDCAS and SDRAS signals During this time all chip select group C registers are ignored 3 1 1 Chip Select Group D Base Address Register CSGBD This register holds the base address for SDRAM The value in this register represents A 28 14 of the address bus A value of 0x0800 puts the SDRAM at 0x01000000 SDRAM Control Registers For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chip Select Registers 0x00000000 CSGBD 0x0800 0x01000000 SDRAM Starting Address 0x01000000 64 Mbit 4M x 16 bit SDRAM 0x017FFFFF OxFFFFFFFF Figure 2 Chip Select Base Address Register 3 1 2 Chip Select Register D CSD and2. www freescale com DRAG GAS Register eescale Semiconductor Inc Figure 11 Power Down Mode Disabled SDRAM Control Registers For More Information On This Product Go to www freescale com Freescale Semiconductor 4 SDRAM Initialization Sequences NFM Controller Registers Code Listing 1 provides the initialization sequences used by the DragonBall VZ ADS board Code Listing 1 SDRAM Initialization Sequences RRR RRR ERR k k k k ER ERR ERE k k k KER k k k kk k ke k k ke k k SDRAM 64M bit Single Band Latency 2 3 FKK k k k k k k k k k k k k k k k k k k k k k k k k k ke k k k k k k k ke k k S0000 GRPBASED move move move move move move move WO WO WO zeae clr w delay addi Ww cmp w bne move nop nop nop nop nop nop nop nop nop nop WO S0281 CSD S0040 CSCR S0000 DRAMC SC03F SDCTRL 854020 DRAMMC 8000 DRAMC do 1 d0 SFFFF d0 delay SC83F SDCTRL move w SD03F SDCTRL nop nop nop nop nop nop nop nop nop nop move w SD43F SDCTRL nop nop nop nop nop nop nop nop nop nop Design Considerations for Interfacin More Information On This Product For Set SDRAM base address to 0x0 Chip Sel Control Reg Disable DRAM Controller Set CPM CL1 Singl le Bank Multiplexing for 64Mbyte SDRAM Enable DRAM Control ler Delay period for SDRAM Issue precharge comm Enable refresh Issu
3. BNKADDL 1 0 The controller supports 4 banks therefore there are two lines of bank addresses However bnkaddH and bnkaddL signals are used by the internal bank register and the page hit detection logic to track whether the current access is on the same page of the previous access in the same bank Each individual bank has its own logic SDCTRL BNKADDH 1 0 00 01 p gt bnkaddh 40 high bank address 11 SDCTRL BNKADDL 1 0 00 01 bnkaddL 40 low bank address 11 Figure 7 BNKADDH and BNKADDL Model For a 2 bank device only one mux from the pair is used The other mux is programmed to 11 output 0 This results in the appearance of only two possible bank registers present For a 4 bank device two muxes are used to form a two line bank address bnkaddH and bnkaddL therefore all four bank registers are used Users may want to treat a multibank device as a 1 bank device In this case the user should program both BNKADDH and BNKADDL to 11 output 0 The logic sees only a one bank register Table 7 9 in the DragonBall VZ user s manual provides information on how to set these bits Design Considerations for Interfacing SDRAM with MC68VZ328 9 For More Information On This Product Go to www freescale com DRAN Conto Register Feeseale Semiconductor Inc NOTE It is recommended that all BNKADDH L bits be set to 1 for SDRAM to appear as one single bank This is
4. Chip Select Control Register 1 CSCTRL1 The CSD register is used to determine three things e If chip select group C will be used as CAS and RAS e Bus width of the SDRAM e Size for each SDRAM chip select With the influence of CSCTRL 1 By default CSD register is set to use the CAS 1 0 and RAS 1 0 functions muxed to PB 5 4 and PB 3 2 respectively This is determined by the DRAM bit bit9 of the CSD register The BSW bit bit7 is O for 8 bit SDRAM and 1 for 16 bit SDRAM The size of each SDRAM chip select determines the SIZ field bits 3 1 The values represented by these bits need to be combined with the DSIZ3 bit of the CSCTRL 1 register to configure the chip select size Table 5 SDRAM Chip Select Size DSIZ3 SIZ 3 1 SDRAM Size 0 0 0 0 32 kbyte 0 0 0 1 64 kbyte 0 0 1 0 128 kbyte 0 0 1 1 256 kbyte 0 1 0 0 512 kbyte 0 1 0 1 1 Mbyte 0 1 1 0 2 Mbyte pesion one oro information Un This Product oi i Go to www freescale com Chip Select Registers Freescale Semiconductor Inc Table 5 SDRAM Chip Select Size Continued DSIZ3 SIZ 3 1 SDRAM Size 0 1 1 1 4 Mbyte 1 0 0 0 8 Mbyte 1 0 0 1 16 Mbyte 1 This bit resides in the CSCTRL1 register 2 Use this setting for 32 Mbyte SDRAM as well NOTE For 32 Mbyte SDRAM first set the chip select size to 16 Mbyte and then set the COMB bit bit10 of the CSD register
5. and self refresh modes See Section 7 3 2 in the DragonBall VZ user s manual for details on other options 3 2 3 SDRAM Control Register SDCTRL The SDRAM control register provides features specific to SDRAM operation This section discusses those features in detail SDRAM Control Registers For More Information On This Product Go to www freescale com Freescale Semiconductor Ince y Controller Habigtar The first register bit in the SDCTRL register is the SDEN bit bit 15 This bit must be set for SDRAM to be used and it must be set before the EN bit is set in the DRAMC to ensure SDRAM support after the controller is enabled In addition to the SDEN bit other settings must be checked as well These settings include the CAS latency or CL bit and the bank address line settings BNKADDH and BNKADDL The CAS latency of a SDRAM should always be set in the SDRAM s mode register before using the SDRAM The DragonBall VZ supports CAS latency of 1 or 2 cycles NOTE Although most SDRAM does not specify support for CAS latency below 2 clock counts testing shows that a number of those SDRAM have no problem running in CAS latency 1 mode The number of SDRAM banks is defined using the BNKADDH and BNKADDL bits This bank refers to the internal arrangement of the SDRAM chip Figure 7 depicts the internal structure of the logic Two multiplexors derive the bank address based on the setting of the SDCTRL register bits BNKADDH 1 0 and
6. usasscssecsssssassssscessosessssscssecessonesosssesecsessesecsossssscesssseseconsonsesessoseosesecosecesconesesocon Figure 4 Normal SDRAM Read Write D15_00 all 1 SEBA Pt srs SDCSO SDAS Sample Read Sample i Write Early ASB Early ASB E SDRAS SENE PreC Act PreC Act SDCLK SDA10 E Refer to Table 1 for signal description sesssssssssssscmmi imessssecsssesecssssssussescesscessonesecsssosscsssosesssscosessscseosecessosesoensssesocsscoseossesoseessosecsesoseses Figure 5 SDRAM Read Write with ECD Using the PK3 UDS signal as a reference as shown in Figure 4 and Figure 5 setting the ECDD bit can improve SDRAM operation during CPU access to the SDRAM by asserting SDCSx early LCDC DMA access is not affected by the ECD feature because the CPU is not involved during the access For more information on ECD settings see Section 6 3 6 in the DragonBall VZ user s manual 3 2 DRAM Controller Registers The DragonBall VZ DRAM controller is designed to support SDRAM up to 32 Mbytes Four registers are used for the configuration and operation of SDRAM 3 2 1 DRAM Memory Configuration Register DRAMMC The DRAM controller uses address multiplexing to support different types of SDRAM For recommendations on how address lines must be configured with the SDRAM use Tables 7 1 through 7 5 in the DragonBall VZ user s manual Design Considerations for Interfacing SDRAM with MC68VZ328 7 For More Information On This Product G
7. Act SDCLK SDA10 Refer to Table 1 on page 2 for signal descriptions Refer to Table 1 on page 2 for signal descriptions Figure 14 SDRAM Read CAS Latency 1 Page Hit Condition Design Considerations for Interfacing SDRAM with MC68VZ328 15 For More Information On This Product Go to www freescale com DAAN GA Ae Register eescale Semiconductor Inc WU a p 2928 6103 oosa so pl t3 EE a o SDCSO NENES Write Write SDCAS mu dd a SDRAS aaa l web sossssssssssscosmiumbsssssesscsssasssscessesesssssessesscosessssscesscessesesscosscesseseenesscesconessessescesecsssseosecosnsencesescos Figure 15 SDRAM Write CAS Latency 1 Page Hit Condition D15 00 all H sepa 9se0 6rss sera UDS SDCSO SDCAS Sample Sample e ASB PreC Act ASB SDRAS re C Frec Act i Write SDWE r SDCLK h SDA10 i Refer to Table 1 on page 2 for signal descriptions sossssssssos mimmin c5 sssssssssossesssesssesssessessosessssssseccsacssssescessaesecescconessossessssessceossconsecessecsseosscossocos Figure 16 SDRAM Read Write CAS Latency 2 Page Miss Condition SDRAM Logic Analyzer Screen Captures For More Information On This Product Go to www freescale com Freescale Semiconductor NG Controller Registers Figure 17 SDRAM Read CAS Latency 2 Page Hit Condition Figure 18 SDRAM Write CAS Latency 2 Page Hit Condition Design Consi
8. Freescale Semiconductor Inc AN2148 D Rev 1 6 2002 Design Considerations for Interfacing SDRAM with MC68VZ328 By Bryan C Chan The MC68VZ328 DragonBall VZ adds support for Synchronous DRAM SDRAM directly in its DRAM controller This application note provided information to setup and use the DragonBall VZ to access SDRAM This application note discusses all aspects of the DragonBall VZ operation as it relates to the SDRAM Contents 1 Introduction 1 2 Physical Interface Between SDRAM and MC68VZ328 2 3 SDRAM Control Registers 4 A 4 spraminiiaizetion 1 Introduction Sequences 13 5 SDRAM Power Control This application note provides information to users who are preparing to use Synchronous Features 14 6 SDRAM Logic Analyzer DRAM SDRAM with the MC68VZ328 Screen Captures 15 The following topics are discussed 1 Physical interface between SDRAM and MC68VZ328 2 Relevant control registers for SDRAM operation in the MC68VZ328 memory controller 3 SDRAM initialization sequences 4 SDRAM power control features 5 SDRAM logic analyzer screen captures It is assumed that users have a basic understanding of the DragonBall processors and SDRAM operation large amount of abbreviations are used throughout this application note Please refer to MC68VZ328 User s Manual order number MC68VZ328UM D for details if needed 1 1 Terminology Unless otherwise specified within the document the following terms a
9. SA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com AN2148 D Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the rig
10. because of a silicon bug documented in the DragonBall VZ design Multibank settings under CAS latency 2 can cause the DragonBall VZ to stop responding to commands if the LCD and the CPU are accessing separate banks The erratum is listed in an errata document available at www freescale com dragonball The continuous page mode or CPM bit in the SDCTRL register can also be enabled at this time The CPM feature can accelerate SDRAM read write cycles by eliminating unneeded precharge cycles With CPM enabled access to a page for the first time generates a page miss flag which sends a precharge and then a read write command Subsequent access to the page generates a page hit flag which is followed immediately by the read write command Setting CPM is another method in circumventing the multibank issue mentioned above 64Mbit SDRAM 64Mbit SDRAM I 1 Page H1 Page First Access Le Page Hit First Access 2 Page Miss Precharged Second Access Precharged Second Access Row Activated Read Command Row Activated Precharge Read Command Read Command Row Activate Read Command Figure 8 Continuous Page Mode Before the SDRAM is fully operational its has to go through the following initialization sequence 1 Initiate an all bank precharge with the IP bit IP 1 RE 0 MR 0 2 Start SDRAM refresh cycles using the RE bit in the SDCTRL register IP 0 RE 1 MR 0 3 Set the mode register of the SDRAM with t
11. ch 2 X No Connect These configurations apply to both 8 bit and 16 bit SDRAM the differences of which can be configured by setting the DRAM Memory Configuration Register DRAMMC Section 7 3 of the DragonBall VZ user s manual provides the details to configure this register For details on address bus signals see Section 2 4 of the DragonBall VZ user s manual 2 2 Data Lines The data bus for 8 bit SDRAMs must have the data signals connected to D 15 8 For details on data bus signals see Section 2 5 of the DragonBall VZ user s manual 2 3 Interface Lines For details on SDRAM interface signals see Section 2 15 of the DragonBall VZ user s manual Design Considerations for Interfacing SDRAM with MC68VZ328 3 For More Information On This Product Go to www freescale com Chip Select Registers Freescale Semiconductor Inc 3 SDRAM Control Registers This section discusses the relevant registers used in SDRAM operations The following registers have an effect on SDRAM operation Table 3 SDRAM Registers Name Address Description DragonBall VZ Manual CSGBD Ox FF FFF106 Chip Select Group D Base Address Table 6 5 CSD Ox FF FFF116 Chip Select Register D Table 6 10 CSCTRL1 Ox FF FFF10A Chip Select Control Register 1 Table 6 12 CSCTRL2 Ox FF FFF10C Chip Select Control Register 2 Table 6 13 DRAMMC Ox FF FFFCOO DRAM Memory Configuration Register Table 7 6 DRAMC Ox FF FFFCO2 DRAM Control Register Table 7 7
12. derations for Interfacing SDRAM with MC68VZ328 17 For More Information On This Product Go to www freescale com DRAMA E Register e eScale Semiconductor Inc D15 00 all T SEBA i655 SDCSO E SDCAS Sample Read Sample Write Early ASB i SDRAS Early ASB arly E DWE PreC Act PreC Act SDCLK Refer to Table 1 on page 2 for signal descriptions sossssssossssssmm i eesssssssscussusssscessaesecsssssessessosesssssesscossesecssossessuseenaessceseconecsesscescesessasecosecosnsencessoces Figure 19 SDRAM Read Write CAS Latency 1 Page Miss Condition with ECD Refer to Table 1 on page 2 for signal descriptions Figure 20 SDRAM Read CAS Latency 1 Page Hit Condition with ECD SDRAM Logic Analyzer Screen Captures For More Information On This Product Go to www freescale com Freescale Semiconductor Ing Canticle Reoite Figure 21 SDRAM Write CAS Latency 1 Page Hit Condition with ECD Refer to Table 1 on page 2 for signal descriptions sossssssssssssemili esscsssssscssssssssessesecsssscsssasssosesscsecesscessesconescessusscssossesecosesscsscessossosessescensonessceocen Figure 22 LCD DMA Read CAS Latency 2 Burst Length 4 Design Considerations for Interfacing SDRAM with MC68VZ328 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc How to Reach Us Home Page www freescale com E mail support freescale com U
13. e mode command Go to www freescale com SDRAM with MC68VZ328 13 AA AH AT Register eescale Semiconductor Inc 5 SDRAM Power Control Features The DRAM controller can initiate the following two types of power control features e Self refresh mode e Power down mode SDRAM self refresh mode is controlled by the RE bit in the DRAMC register By setting the RE bit to 1 the DRAM controller issues a self refresh mode command Refer to Table 1 on page 2 for signal descriptions kia poem zd CA el ud ne SDCAS a E EE E Esdscsseae aM 22 ee Rolorto Tao ton page 2 tor signal desoriptions Figure 12 Self Refresh Event The SDRAM draws the minimum amount of power when it is in self refresh mode The DRAM controller can also be disabled after the SDRAM enters self refresh mode Power down modes allows the SDRAM to be suspended when not in use It differs from self refresh mode in that it does not require a wake up period when access occurs See Section 3 2 4 of this document for details on power down modes SDRAM Power ontrol Features For More Information On This Product Go to www freescale com Freescale Semiconductor Ing Controler Habigiarg 6 SDRAM Logic Analyzer Screen Captures The logic analyzer screen captures in this section show the SDRAM read and write cycles generated by the DragonBall VZ ADS D15 00a 3580 prs UDS SDCSO SDCAS K naghit Read Sample rite SDRAS ASB pDWE PreC Act Prec
14. een SDRAM and MC68VZ328 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Lines The configuration shown in Figure 1 was derived from the DragonBall VZ Application Development System ADS which provides for two 64 Mbit SDRAM 4 M X 16 bit Each chip select line can address up to 16 Mbytes of memory Chip select DO can be configured to use the address space of chip select D1 for a total address space of 32 Mbytes See Section 3 1 2 Chip Select Register D CSD and Chip Select Control Register 1 CSCTRL 1 on page 5 for details on using 32 Mbyte SDRAM 2 1 Address Lines One of the more intricate steps in the MC68VZ328 to SDRAM interface is connecting the SDRAM to the address lines Most importantly the address line PM4 SDA10 must always be connected to A10 on the SDRAM memory chip to ensure proper SDRAM operation NOTE SDA10 can be kept high during the precharge command to direct the SDRAM to precharged all banks Table 2 provides examples of address line configurations for different sizes of SDRAM Table 2 Address Line Configurations 8 Bit or 16 Bit MC68VZ328 Pins SDRAM Pins 16 Mbit 64 Mbit 128 Mbit 256 Mbit A 0 9 A 1 10 A 1 10 A 1 10 A 1 10 A10 SDA10 SDA10 SDA10 SDA10 A11 A12 A12 A13 A12 A12 x X X A13 BSO X A13 A12 A15 BS1 xX A14 A15 A16 1 For 16Mbit SDRAM A11 is used for Bank Select and maybe labeled as su
15. he MR bit IP 0 RE 1 MR 1 The MR bit passes the CAS latency setting to the mode register of the SDRAM The load mode register command programs the SDRAM to CAS latency 1 or 2 depending on the CL bit The CL bit should be set to the proper latency period prior to setting the MR bit The steps above must be completed in sequence followed by a number of no ops to allow the SDRAM to initialize properly See the Section 4 SDRAM Initialization Sequences on page 13 for example code on SDRAM initialization SDRAM Control Registers For More Information On This Product Go to www freescale com Freescale Semiconductor Ing Controller Hablatara 3 2 4 SDRAM Power Down Register SDPWDN The SDPWDN register controls how the SDRAM enters power down mode The power down mode can reduce SDRAM power consumption by negating the SDCE signal when SDRAM is not being accessed During power down mode refresh cycles continue to be issued to the SDRAM by the DRAM controller 3 2 4 1 Active Power Down Mode When the APEN bit is set the SDCE is negated after every access to the SDRAM Figure 9 Active Power Down Mode 3 2 4 2 Precharge Power Down Mode When the PDEN bit is set the SDCE signal is negated when the SDRAM has been precharged and the PDTOUT time out condition has been met Figure 10 Precharge Power Down Mode Design Considerations for Interfacing SDRAM with MC68VZ328 11 For More Information On This Product Go to
16. ht to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harm
17. less against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e O 7 freescale semiconductor For More Information On This Product Go to www freescale com
18. nd abbreviation are as defined in Table 1 freescale semiconductor Freescale Semiconductor Inc 2004 All rights reserved Go to www freescale Freescale Semiconductor Inc Terminology Table1 Terminology Terms Description CPU The 68K core in the DragonBall processor LCDC LCD Controller module in the DragonBall processor UDS Upper Data Strobe signal from the 68K core muxed with Port K3 PK3 UDS SDCSO SDRAM Chip select 0 muxed with Port B4 PB4 CSD0 CAS0 SDCS0 SDCAS SDRAM CAS signal muxed with Port B3 PB3 CSC1 RAS1 SDCAS SDRAS SDRAM RAS signal muxed with Port B2 PB2 CSCO RASO SDRAS SDWE SDRAM Write Enable signal muxed with Port B1 PB1 CSB1 SDWE SDCLK SDRAM Clock signal muxed with Port MO PMO SDCLK SDCE SDRAM Clock Enable signal muxed with Port M1 PM1 SDCE SDA10 SDRAM Address Line 10 signal muxed with Port M4 PM4 SDA10 2 Physical Interface Between SDRAM and MC68VZ328 The recommended pin connections between the DragonBall VZ to SDRAM are shown Figure 1 vee VCC 1 i1 MC68VZ328 64 Mbit 4Meg x 16 Bit SDRAM PB5 CSD1 CAS1 SDCS1 CS SDRAM1 D 64 Mbit 4Meg x 16 Bit SDRAM PBA CSDO CASO SDCSO cs SDRAMO PM1 SDCE CKE PM0 SDCL CLK PB2 CSCO RASO SDRAS RAS PB3 CSC1 RAS1 SDCAS CAS PM2 DQMH UDQM PM3 DQML LDQM PB1 CSB1 SDWE D 0 15 A 1 10 Figure 1 Pin Connection from MC68VZ328 to SDRAM Physical Interface Betw
19. o to www freescale com NENG Register eescale Semiconductor Inc The DRAMMC register also controls the refresh cycle timing see Section 7 2 3 in the DragonBall VZ user s manual for details For typical applications the default value for the REF bits is sufficient 3 2 2 DRAM Control Register DRAMC The DRAMC contains the following features that apply to SDRAM operations e Master DRAM controller enable e Page size of SDRAM e SDRAM refresh mode e Light sleep option e Reset burst refresh option Of these features the first two options require consideration before the SDRAM is initialized After the DRAM controller is enabled through the EN bit bit15 of the DRAMC register the page size of the SDRAM should be set in the PGSZ field bits 9 8 The page size of a particular SDRAM can be found by the number of column addresses for each bank The amount of memory space covered by the column addresses is the page size For 8 bit SDRAM the number must be divided by two before applying it to the PGSZ field Example 64 Mbit SDRAM 64 Mbit SDRAM 12 Row 12 Row Address Address 8 bit E NO 8 Column 9 Column Address Address 8 column address 256 memory space 9 column address 512 memory space For 16 bit SDRAM PGSZ 00 256 words For 8 bit SDRAM PGSZ 00 256 words Figure 6 Calculating Page Size The RM bit controls the SDRAM refresh mode between auto refresh
20. to 1 The COMB bit effectively combines the memory space of CSD1 to that of CSDO allowing CSDO to address a full 32 Mbyte 0x00000000 0x00000000 0x01000000 0x01000000 CSDO 16Mbyte CSD Register Ox01FFFFFF ki COMB bit 1 0x02000000 CSDO0 32Mbyte CSD1 16Mbyte Ox02FFFFFF Ox02FFFFFF OxFFFFFFFF OxFFFFFFFF Figure 3 Combining CSDO and CSD1 for 32 Mbyte SDRAM The EN bit of the CSD register should be set to one to enable this chip select Also the WS3 1 bits can be used to introduce a number of wait states if required 3 1 3 Chip Select Control Register 2 CSCTRL2 The DragonBall VZ chip select module incorporates an Early Cycle Detect ECD feature for dynamic memory In a normal chip select scenario without ECD the chip select signal is proceeded by an internal address strobe ASB signal from the 68K core The ECD feature works from the fact that the ASB is itself proceeded by an early ASB signal from the 68K core By using the early ASB signal to derive the chip select signal both read and write cycles to SDRAM can be shortened by one clock cycle SDRAM Control Registers For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y Controle Habitat D15 00 all 7 1580 ee ee UDS SDCSO yDeAS Cae Read Sample rite ASB ASB SDRAS SDWE PreC Act Prec Act SDCLK SDA10 Refer to Table 1 for signal description sessssssossssoum9
Download Pdf Manuals
Related Search