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1. 22 BSYNC L MEME 1 SEL 0 2 4 6 L 5 TUE OUTHB L T I OUTLB L m T9 T10 BRPLY L T13 2 4 I Ry Cx H 115 116 TIME REQUIRED TO DISCHARGE FROM ANY CONDITION ASSERTED 150ns NOTE 11 4548 Times nanoseconds 5501 Figure 5 DC004 Timing Diagram Ve son 2800 FROM FROM FROM OUTPUT OUTPUT OUTPUT 5 15pF 200pF 1500F DIODE 20777 LOAD LOAD B LOAD C 11 4349 MA 5499 Figure 6 DC004 Loading Configurations 84 L 1 JA2 L 2 MATCH H 3 REC H 4 XMIT H 5 DAT3 H 6 DAT2 H 7 BUS3 L 8 BUS2 L 9 GND 10 BUS0 L JA1 L Js BUS2 L lS JA2 L BUS3 L dp JA3 L L XMIT H H Figure B 7 APPENDICES le 05 Simplified Logic Diagram 20 Vcc 19 JA3 L 18 DATOH 17 DAT1 H 16 JV3H 15 JV2 H 14 JV1H 13 MENB L 12 BUSOL 11 BUS1 L 7 dec cad JV1 H Man TP JV2 H DAT2 H JV3 H DAT3 H MATCH H IC DC005 MA 5498 APPENDICES 85 TRANSMIT DATA TO BUS XMIT H c MM REC H GROUND 5 5 30ns BUS L OUTPUT 5 25ns gt fe 5 25 DAT H INPUT RECEIVE DATA FROM BUS 5 INITIALLY HIGH XMIT H GROUND 30ns je TO DAT H OUTPUT 2 2 m je 8 TO 30ns BUS L
2. 2 1 2 DPMBO Detailed Functional Diagram 4 1 3 The ISV11 A DPM50 Subsystem 7 1 4 DPM50 Ax Cx Physical Layout 10 1 5 DPMBO Fx Hx Physical Layout 11 1 6 H7870 Power 11 1 7 M7958 Control Module 13 2 1 DECdataway Connector Mounting 19 2 2 Cabinet Heat vs Site Temperature 21 2 3 ISV11 A Physical Configuration 23 2 4 MB080 Board yy a x aw bu eed Wb 24 2 5 3290 Rare ena ae fr ec ce 25 2 6 DPMBO AA AB LSI 11 Module Placement 26 2 7 DPMBO FA LSI 11 Module Placement 26 2 8 DPMBO Serial Line Filter Configuration EIA RS232C 30 2 9 DPMBO Serial Line Filter Configuration 20 mA CurrentLoop 31 3 1 DPM50 Maintenance Software Firmware Hierarchy 34 3 2 ISV11 A Boards Edge On 40 CONTENTS 3 3 M8080 Board 222 bre BAe eae n u 42 3 4 3290 Board aars WES a DG E RS 43 3 5 Troubleshooting Flowcharts Chart 1 System Procedure 46 3 6 Troubleshooting Flowcharts Chart 2 Subsystem Procedure PICA n eee 47 3
3. 14 1 6 Documentation de 3 6 5 15 CHAPTER 2 INSTALLATION 2 1 gt sath oe ded oe dud T 17 2 2 339 Installation 17 2 2 1 General Considerations 17 2 2 2 DIGITAL Cabinet Installation 18 2 2 3 NEMA Installation 18 2 2 4 NEMA Power Dissipation Considerations 18 2 2 5 Other Enclosures 22 2 3 ISVIA A Config ratioN iac eee eed 22 2 4 LSI 11 Microcomputer Configuration 24 2 4 1 LSI 11 Bus Backplane Configuration 25 2 4 2 LSI 11 Module Configurations 27 2 4 3 Serial Line Interface Cable Filter Optional 28 2 5 Control Module D Bus Option Configuration 30 CHAPTER 3 MAINTENANCE 3 1 4 25 L Tayka bu a ua g Aa su maa bia he eee 33 3 2 DZKCH DECdataway Exerciser 34 3 3 CZKCIx ISV11 A ROM Resident Diagnostics 35 3 3 1 Hardcore Diagnostics uuu s ct ke ata 35 3 3 2 Softcore Diagnostics 35 3 4 CZKMPx Diagnostic 36 iv CONTENTS 3 4 1 H st Mode vitae orae E SEO 3
4. DISTRIBUTED PLANT MANAGEMENT DPM50 user guide INDUSTRIAL PRODUCTS EK DPM50 UG 002 DPM50 user guide digital equipment corporation maynard massachusetts 1st Edition September 1978 2nd Edition September 1980 Copyright 1980 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice Digital Equipment Corporation assumes no responsibility for any errors which may appear in this manual Printed in U S A This document was set on DIGITAL s DECset 8000 com puterized typesetting system The following are trademarks of Digital Equipment Corporation Maynard Massachusetts DIGITAL DEC PDP DECUS UNIBUS DECsystem 10 DECSYSTEM 20 DIBOL EDUSYSTEM VAX VMS MASSBUS OMNIBUS OS 8 RSTS RSX IAS CONTENTS CHAPTER 1 INTRODUCTION 1 1 SCOPE Set h p S Ey 1 1 2 Functional Description as euch 1 1 2 1 Distributed Plant Management Overview 2 1 2 2 The DPNMIBO wie Sebo Bae a U s 3 1 3 Physical Description 8 1 3 1 Standard Versions of the DPMBO 8 1 3 2 Controls Fuses Indicators 8 1 3 3 Hardware EE EN US 9 1 4 ca ae sea wawaka ee eee Se es 1 5 Specifications mo
5. 9 1 2 H7870 Switches and Indicators 12 1 3 ISV11 A Specifications 15 2 1 DPMBO AA LSI 11 Modules Jumper and Switch SettingS ROCA 28 2 2 DPM50 FA FB HA HB LSI 11 Modules Jumper u and Switch Settings Ex REPE becca ae ees ETE 29 2 3 7006 B Filter Assembly Kits 29 2 4 Available 12 V Current for Modules 32 3 1 Hardcore Feste mue vd 3 2 Softcore Tests sce cs er qu RR d eur ea aes 36 3 3 LSI 11 MAINDEC Diagnostics 39 4 1 Cock Characteristics sx usutakuy au 2 4212 CHAPTER 1 INTRODUCTION 1 1 SCOPE The 50 is an intelligent real time factory floor process 1 sub system with an intelligent interface to the DECdataway The DECdataway provides bidirectional multidrop communication between a central com puting facility and DPM50 subsystems scattered through an industrial vironment This arrangement constitutes a Distributed Plant Management DPM system This user guide provides functional and physical descriptions general software information installation instructions and maintenance cedures for the DPM50 It should be used with the following manuals I O Subsystem User Guide EK OPIOS UG DECdataway User s Guide 1 1 UG Micro
6. E F NULL MODEM 22 10 SYMBOLS E M EIA RS232 25 PIN MALE CONN M CONNECTOR E F EIA RS232 25 PIN FEMALE CONN F FEMALE CONNECTOR 6153 Figure 2 8 50 Serial Line Filter Configuration EIA RS232C Figures 2 8 and 2 9 show DPM50 serial line filter cabling for various EIA and 20 mA configurations respectively Refer to the H333 arrangement drawings in the H333 Maintenance Print Set for physical mounting and cable laying information and illustrations 2 5 CONTROL MODULE AND D BUS OPTION CONFIGURATION Procedures for configuring the I O control module IOCM 1 modules and placing them in the D Bus can be found in Chapters 3 and 4 of the O Subsystem User Guide However the following information may be useful in determining power limitations imposed the modules by 51 11 bus options in DPM50 Fx and Hx systems INSTALLATION 31 ae eed f H7006 A DLV11 DLV11 F BC05M XX FILTER REOUIRED H7004 B F BC06K 7K OPTIONAL TERMINAL CABLE BCO15 XX TERMINAL 7423332 00 FILTER PANEL j 0 1 BC05M XX TERMINAL BC06K 7K FILTER MIN DLV11 U70046 REQUIRED CABLE N N TERMINAL DLV11 F L L 40 PIN I 7423332 00 FILTER PANEL gt a EE mm DLV11 KA
7. Ground lug LTC switch ENA HALT switch DC ON indicator RUN light 5 V test point 12 V test point RTN test point Function Applies ac power to the H7870 and activates power control outlet Protects against ac line overload fuse rating is 6 25 A for 115 V operation or 3 A for 230 V operation When connected to power control bus ties ac power ON OFF control of all power controllers to ac ON OFF switch of the H333 chassis Provides safety ground connection to power supply chassis When on enables B EVNT L which is an LSI Bus compatible line frequency signal generated by the H7870 must be on for normal operation When on enables program execution by the LSI 11 when off it places the processor in halt mode must be in the ENA position for normal operation Lights to indicate that dc power is on should light when ac ON OFF switch is turned on Lights to indicate that LSI 11 processor is running Measures 5 Vdc output Measures 12 Vdc output Meter return for dc voltage measurement 2 4 3 of this manual provides H7006 A B Filter Panel configuration and in stallation information For information concerning the following options re fer to the Microcomputer Interfaces Handbook The following options are available for the DPM5O AA AB and CB versions Refer to Section 2 4 of this manual for option selection guide lines e DLV11 DLV11 F or DLV11 J Asynchronous Line Interface and asso ciated
8. H7006 8 8 015 4 MAX 5 1 OPTIONAL FILTER 4 M BC21A 03 Tee TERMINAL CABLE LERMINAL 8 PIN L 1 BC21A 03 M M FILTER DLV11 KB m H7005 TERMINAL CABLE TERMINAL L aPN 7017399 06 DLV11 J FIM S FILTER i file N TERMINAL CABLE S ERRAT 8 PIN BC21A 03 1 7399 H7005 8 PIN BCO15 XX FILTER PANEL EL ee es es us BC015 XX IS A OPTIONAL 20mA EXTENSION CABLE AVAILABLE IN THE FOLLOWING LENGTHS 3 6 10 15 25 50 100 FT SUBSTITUTE XX WITH DESIRED LENGTH WHEN ORDERING MNL MATE N LOCK 8 PIN CONNECTOR SYMBOLS M MALE CONNECTOR F FEMALE CONNECTOR MA6154 Figure 2 9 50 Serial Line Filter Configuration 20 mA Current Loop The DPM50 Fx and Hx have seven slots available for modules in the H333 Due to power limitations a close examination of power require ments for the modules must be made based on which LSI 11 bus op tions are being used The I O modules use only 12 V from the H7870 power supply The maximum current needed for each module is speci fied in the O Subsystem User Guide 32 INSTALLATION Table 2 4 Available 12 V Current for I O Modules LSI 11 Bus DLV11 F Console DLV11 J DLV11 KA Option Interface Console Interface No option or 2 63A 2 79 A minus 0 30 A console only DLV 11 K
9. T CLOCK H MA 2289 99 21901 W31SAS PCS1 J1 J2 SL6 DROPOUT L gt H OR RSA H INT H INTERRUPT INT RQ 7 H SL5 8080 LATCH amp E ack L ENCODER TEST 6 in PCS 2 RX ENA DRIVERS PORT USYNRT TEST 4 ADDRESS DECODER BUS BUS A03 07 SEL A0 L READ 8X L SEL 8X H ADR SEL 515 RSI RX CLK R DATA L TRANSITION DROPOUT H DETECTOR HISTORY ETC RAW DATA H SL1 Figure 4 6 Serial Line In TEST 5 RECEIVER CIRCUIT SL1 J1 MA 2290 21901 WALSAS L9 DMA ENB H PCS 5IO B L SACK L BUS L Pcs 5 PCS 5SO SACK L OH T Hj BUS A15 H BDMGI L DOUT L SACK H TIMER PCS 5 GRANT 440 H CONTROL B SYNC L 550 H B WTBT L PCS 6 PCS 5 BDMGO L T ADDR EN H BUS 00 14 H T 857 H BUS D3 H B BS7 L DRIVERS XMIT DAL 0 15 H DC005 PCS8 8 TRANSCEIVERS O FOR TEST ONLY LOADS OWN CSR S TESTS 7 AND 11 BUS D0 7 H PCS 4 BUS D gt DAL HB L IDRIVERS PCS8 8 B DAL O 15 L MA 2291 Figure 4 7 DMA Transfer Out 89 21901 WALSAS H BUS L B DIN L B SYNC L B SYNC L B RPLY L F RPLY H m ines 10 A00 H I ADDR EN H BUS A00 14
10. Decoding addresses of 8080 ports in the LSI 11 bus interface is accom plished by the logic at the top on PCS7 There address bits 0 2 are de coded to select the port on 1 function when bits 3 7 are all zero Only ports 1 and 2 the E39 and E36 registers below the decoder can be writ ten by the 8080 and for these the select lines also generate write signals on an I O write From these two ports the only bit the LSI 11 can read is boot status port 1 bit 1 through CSRO Setting and clearing port 1 bit 7 boots the LSI 11 by simulating a power up signal on the DCOK line of the LSI 11 bus To halt the LSI 11 port 1 bit 6 is handled by a separate flip flop so it can also be set by a power failure Port 2 bit 5 is not included in the register as it is used to clear the LSI interrupt request flip flop at the lower right Port 1 bit O and port 2 bit 4 do not show up here at all they are used to request interrupts at the LSI 11 as described in the following dis cussion The 8080 can read most of what it supplies to ports 1 and 2 along with a few other bits from interrupt and DMA control via the E38 and E40 multi plexers at the left Port O is not used and ports 3 4 and 5 correspond to the three bytes of the TCB address in CSR2 and CSR4 PCS3 4 4 2 LSI 11 Interrupt Control Interrupt requests from the 8080 to the LSI 11 are handled by the stand ard DCOO3 dual interrupt circuit at the upper right on PCS4 The 8080 ma
11. and each H332 screw terminal chassis has a ground strap on the right side Every one of these ground straps must be electrically well connected to the cabinet Although the RX01 2 floppy disk systems are standard options for the DPM50 DIGITAL does not supply hardware for mounting it in NEMA cabinet Customers must provide their own mounting bracket 2 2 4 NEMA Power Dissipation Considerations A circulating fan with minimurn capacity of 500 CFM must be mounted in INSTALLATION 19 7015928 03 gt SERIAL BUS CABLE T lt s gt p We 7421108 CONNECTOR BRACKET H333 A B MASTER CARD CAGE H7870 POWER SUPPLY MA 2265 Figure 2 1 DECdataway Connector Mounting the enclosure An appropriate model is the Caravel 115 Vac 550 CFM DEC P N 12 04826 A typical NEMA 12 enclosure with a fan 6 feet x 5 feet 1 foot can used to house an H333 and one H334 When there are two chassis in the enclosure the H333 should be at the bottom in the cooler circulating air Nothing else can be mounted in the box unless it is equipped with a heat exchanger or air conditioner both standard NEMA accessories Even then the remaining space should be used only for legitimate DPM50 op tions expansion chassis for modules or screw terminal chassis for field wiring No other equipment should be mounted in the box Power dis sipation of the enclosed units should never exceed 18 watts per square foot of u
12. reference is the 2 TTL clock supplied by the 8224 clock circuit associ ated with the 8080 microprocessor This clock drives the receiver directly For the transmitter the exclusive OR gate at A7 with the delay introduced by two inverters at one of its inputs acts as an edge detector to multiply the basic clock to 4 MHz From this the E28 counter produces the 8X clock by dividing by nine This is accomplished by loading 7 at the clock following the carry out produced by a count of 15 The 8X clock counts the E23 counter which runs on a continuous 16 count cycle so its two middle bits provide division by 4 and 8 The T IX clock drives the USYNRT transmitter and shifts out the data the 1X and 2X clocks togeth er are used for biphase encoding of data transmitted over the dataway Characteristics of the various clocks are as shown in Table 4 1 Table 4 1 Clock Characteristics Clock Period us Frequency 2TTL 0 5 2 MHz 8X CLK 2 25 444 444 KHz 2XCLK 9 111 111 KHz TCLOCK 18 55 555 KHz The modem is coupled to the DECdataway by transformer T1 its second ary winding connects the serial line at pins 9 and 10 of the internal data way connector The transformer is the 1 1 1 type That is a pulse train in from the line generates two output trains one positive and the other negative but both have the same amplitude as the input The transmitter uses only one primary coil each way so the output is a 5 V signal either positive or negative
13. the first 2 MHz clock produces the transition detected signal This is on for two clock periods during that time it turns off the detector to inhibit further sampling of the raw data This filters out noise near the modem comparator threshold preventing any noise surrounding a transi tion from being mistaken for another transition The second signal transi tion delayed has the same form as transition detected but it has opposite polarity and is offset by one clock period The difference in these two sig nals is that transition detected inhibits the detector resetting the phase counter and transition low actually represents the transition for process ing by the remaining logic The third signal from the detector produces the phase locked clock which occurs at the end of transition detected SYSTEM LOGIC 59 The phase counter is reset at every transition but in the absence of tran sitions it simulates the phase locked clock every time it reaches 30 The Ts and Ns in the timing diagram distinguish phase locked clocks produc ed by transitions 7 from those that are not N The timing diagram is drawn with the exact theoretical timing for a serial signal from the bus In a real situation transitions can be quite late without adversely affecting reception Each phase locked clock shifts the transition history Where the bit shifted into the register reflects transition low detection of a transition causes a zero to be entered After th
14. 3 4 1 of the O Subsystem User Guide indicates that supply voltages should be within three percent of their nominal values However because of the ISV11 A present in the DPM50 the 5 V supply output must be adjusted to 5 1 V To do this follow instructions in Section 7 4 1 of the O Subsystem User Guide Also for normal operation the LTC and HALT ENA switches on the front panel of the supply must be up ON and ENA respectively 2 2 2 DIGITAL Cabinet Installation When a system is ordered in DIGITAL cabinets all equipment is already configured as shown in several illustrations in Chapter 3 of the O Sub system User Guide The ISV11 A cable is not shown in that manual This cable passes through the top of the H333 chassis and its dataway con nector mounts on a bracket at the back of the cabinet Figure 2 1 2 2 3 NEMA Installation Directions for installing the H333 and similar chassis in a NEMA enclosure are given in Section 3 3 5 of the O Subsystem User Guide The bracket holding the dataway connector on the end of the ISV11 A cable must be on an enclosure wall within 75 cm 30 inches of the right side of the H333 Figure 2 1 Mounting requires a pair of holes for 10 32 hardware 0 554 cm diameter drilled 4 445 cm apart 0 218 inches diameter drilled 1 75 inches apart Bracket location is unimportant as long as there is enough clearance to connect the DECdataway port connector The H333 master chassis each H334 expander chassis
15. 53 and numbers along the edges The following three sections give a de tailed description of the hardware on the two boards Discussion is geared to the prints but readers should also refer to Figure 4 1 whenever necessary Some logic signals on the boards are available at test sockets shown in the lower left on SL6 and the upper right on PCS6 In some cases the lines to these test pins are not true logic signals at all but gate inputs tied to 5 V Therefore they play no real role in system operation but they can be pulled low to disable various parts of the logic for GR test pur poses These pseudosignals are identified on the prints by the word test 4 2 PROCESSING UNIT This unit occupies part of both boards and is shown on three prints PCS2 SL2 and SL3 The first of these shows the 8080 microprocessor with its clock and gating circuits The 8228 has bidirectional drivers for the 8 data lines in the 8080 bus the two 7452418 below it provide unidirectional driv ing for the 16 address lines The 8224 clock circuit at the left supplies the 1 2 clocks for the microprocessor chip and the 2 TTL clock for the serial line unit all clocks are 2 MHz At the beginning of every micro processor machine cycle the 8080 places status information identifying the use of the cycle on its D outputs and sends a sync signal to the 8224 This latter chip responds by sending a strobe to the 8228 causing it to load status into a set of latche
16. 7 Troubleshooting Flowcharts Chart 2 Subsystem Procedure Patt Su py pusaka ws wee eet 48 3 8 Troubleshooting Flowcharts Chart 3 Port Address CHECKOUL 1 Cu ee Maes oe A 4 1 ISV11 A Logical Organization 52 4 2 Transmitter TIMING 56 4 3 Receiver Simplified Block Diagram 57 4 4 Receiver TIMING se eet Baa tare uA rS eu 58 4 5 Serial LIMO muku ae cae 66 4 6 Seral LNG i tattoo ete DRE on S paren as 67 4 7 Transfer 68 4 8 DMA Transfer n ate ee Pr a ex e o e 69 4 9 ISV11 A Interrupt Request 5 11 70 4 10 LSI Interrupt Request 71 B 1 DCOO3 Simplified Logic Diagram 79 B 2 DCOO3 Interrupt Section Timing Diagram 80 B 3 DCOOS3 Interrupt Section Timing Diagram Sections A and Br es uu oet Casa goes eae 81 B 4 DC004 Simplified Logic Diagram 82 B 5 DGOO4 Timing Diagram 83 B 6 DCOO4 Loading Configurations 83 B 7 DCOO5 Simplified Logic Diagram 84 B 8 DCO05 Timing Diagram 85 TABLES 1 1 DPM50 XX System Configuration
17. CABLE INTERBOARD CONNECTOR CONNECTOR amp 5413290 M8080 BRACKET USYNRT 1 CHIP 213 87 mm SPACER 10 44 in __ 265 18 mm MA 2264 Figure 2 3 ISV11 A Physical Configuration the two boards joined together along details of the ISV11 A cable data way connector and mounting bracket As mounted in the chassis the M8080 mother board the one that plugs into the backplane is on the left This places the 54 13290 daughter board closer to the LSI 11 processor board The ISV11 A must always be plugged into slot five of the back plane Refer to Figures 2 6 and 2 7 in Section 2 4 1 All jumpers are set correctly at the factory However it is a good practice to verify the configuration at installation time An in depth technical de scription of the ISV11 A is presented in Chapter 4 of this manual Both ISV11 A boards have a number of jumpers that are factory installed for proper DPM50 operation The jumper configuration on both boards is as follows M8080 In W7 W8 W9 W10 W17 W18 W19 W20 Out All others Jumpers Use W1 8 W12 W13 LSI 11 bus address W9 11 W14 W15 Vector address W16 Hold B SACK L W17 W20 DMA timers W18 W19 Connect pins W2 1 23 Reserved 24 INSTALLATION w5 W13 W16 W20 W17 W15 W14 W23 w22 W21 Le Lc gt 0 1 I I C 2 E 5 MA 2267B Figure 2 4 M8080 Board 54 13290 In W1 W3 W5 W7 W9 Out All others Jumpers
18. CZKMP x DIAGNOSTIC 3 4 51 11 BUS CZKCI x RIDE PARAGRAPH 3 3 LSI 11 OR LSI 11 23 MEMORY PROCESSOR BUS OPTIONAL OPTIONAL INTERFACE INTERFACE SOFTWARE HARDWARE 10 LSI 11 BUS MAINDEC S PARAGRAPH 3 4 4 ow s s m TO xe VERSION DESIGNATION D BUS A INTERFACE Z MONITOR i 1 PARAGRAPH 3 4 5 l r 7 L N DIAGNOSTIC MA 5506 Figure 3 1 DPM50 Maintenance Software Firmware Hierarchy The North American NORAM industrial support team is chartered to pro vide all levels of support including Field Service training for NORAM per sonnel Support and training in European areas is provided by European Regional Support 3 2 DZKCH DECDATAWAY EXERCISER The ability of the host to communicate with DPM50 the DECdataway must be verified before a valid diagnosis of a DPM50 can be performed DZKCH is a task that runs under RSX11 M M 4 in the host This task ex MAINTENANCE 35 ercises the DECdataway and verifies integrity of the communications channel between the host and various devices on the dataway With a 50 DZKCH checks communication up to and including the 8 bit mi croprocessor in the ISV11 A It tests whether the 8 bit microprocessor can manage the DECdataway protocol and communicat
19. H T BS7 H S Pos 7 0 B BS7 L BS7 H DRIVERS DAL 0 15 H PCS8 8 TRANSCEIVERS PCS 4 DRIVERS PCS8 8 B DAL 0 15 L PCs 80 DAL LB gt BUS D L MA 2292 Figure4 8 DMA Transfer In 21901 WALSAS 69 ENA DAT BIRQ DAT BDIN BUS DOH BUS D4H DC003 DUAL INTERRUPT CIRCUIT ENA CLK VEC ROST 8080 PORT A rs ry n rr ADDRESS 2 H DECODER PCS 7 BUSI O W L VEC ROST BH TRANSCEIVERS VECIOR H ENB CLK VECTOR PCS 4 BUS A00 07 H JV BUS INPUTS TEST 12 0 004 VECTOR Figure 4 9 ISV11 A Interrupt Request LSI 11 MA 2293 0 21901 WALSAS B DAL 0 15 L DAT DC005 TRANSCEIVERS B BS7 L O B WTBT L O B DOUT L gt gt Figure 4 10 LSI Interrupt Request SRPLY H INTERRUPT LATCH amp PRIORITY ENCODER INT H G PCS 11 SL 6 2 N LSI INT REQ H BUS D0 7 H ADDRESS DECODER SL4 BUS 05 H PCS 4 JO BRPLY L 8080 PORT ADDRESS DECODER PCS 7 BUS A00 07 H 8080 PCS 2 MA 2294 21901 WALSAS LL APPENDIX A LOGICAL DISCONNECTION OF A DPM50 FROM THE HOST SYSTEM Before downloading and running diagnostics on a DPM50 it is necessary to sever any open channel between it
20. INPUT RECEIVE DATA FROM BUS BUS INITIALLY LOW XMIT H GROUND REC H gt 30ns TO 30ns DAT H OUTPUT HiZ Hiz 8 30ns BUS INPUT VECTOR TRANSFER TO BUS JV H lt 20ns MAX 20ns BUS L OUTPUT ADDRESS DECODING BUS INPUT X 10 40ns E lt 5 TO 40 ns 10 TO 40ns L acd ee NI RECEIVE MODE LOGIC DELAY XMIT H H 40 90ns DAT 3 0 H OUTPUT HZ 11 4892 MA 5600 Figure 8 005 Timing Diagram SIGNAL GLOSSARY This list identifies all signals that appear on the circuit schematics for the M8080 and 54 13290 boards and gives the print on which each appear Some bus sig nals are generated on several prints Many LSI 11 bus signals originate outside the ISV11 A as well as inside it A print designation in parentheses indicates a signal that appears on that print as an input but is never generated by the ISV 1 1 Signal 91 2 CLOCK H 2 TTL H 1X CLK H 2X CLK H 8X CLK H L OH 330 H 440 H 550 H AD 15 17 H BAD 16 171 BBS7L Print PCS2 PCS2 SL 1 SL 1 SL 1 PCS6 PCS7 PCS7 PCS7 Definition 2 MHz clocks generated by the 8224 for the 8080 2 MHz clocks generated by the 8224 for the USYNRT Equals T CLOCK H For biphase encoding this clock has twice the frequency of T CLOCK Intermediate signal in
21. LSI 11 23 Based Microcomputer The LSI 11 crocomputer directly controls the I O Subsystem as described in the pre vious paragraph The DPM50 LSI 11 microcomputer is based upon either LSI 11 KD11 H processor or an LSI 11 23 11 processor Fig ure 1 2 NOTE To avoid contusion the following conventions are followed in this user guide The term LSI 11 microcomputer refers to the entire microcomputer system regardless of its processor When a distinction is made between processors the option designa tion KDXXX X is always presented 6 INTRODUCTION The LSI 11 microcomputer exercises direct local control over the D bus by executing user programs stored in its local memory Within the DPM50 master chassis space is provided in the LSI 11 bus backplane for adding optional interface modules Figure 1 2 This allows local terminals and or floppy disk mass storage units to be added to the system Complete information regarding the LSI 11 Microcomputer family of prod ucts is presented in the Microcomputer Processor Handbook and the Mi crocomputer Interfaces Handbook 1 2 2 3 DECdataway Interface The ISV11 A is an intelligent DEC dataway interface It manages DPM50 communications with the host com puter over the DECdataway It performs the following functions 1 It facilitates downline loading of the RSX 11S operating system with built in tasks into the LSI 11 microcomputer memory Refer to Sec ti
22. Maximum heat produced inside the cabinet expressed in Btu hr Therefore a user considering NEMA 12 applications must calculate what temperature limits will allow reliable operations These power dissipation relationships were derived under laboratory conditions and should only be used as guides for most normal installations For NEMA cabinet appli cations in areas with an abnormal heat source these formulas should be modified to account for the specific environment The worst case dissipation for various chassis with all 1 slots filled is as follows H333 2493 Btu hr 713 W H334 with power supply 2319 Btu hr 680 W H334 without power supply 955 Btu hr 280 W To determine the exact figure for a particular configuration refer to the O Subsystem User Guide the ISV11 A dissipates about 17 watts 2 2 5 Other Enclosures Customers can use any enclosure they want to protect the equipment The mounting directions are the same as those given for a NEMA enclo sure at the beginning of Section 2 2 3 However when a non DIGITAL non NEMA cabinet is used the customer must maintain specified environ mental conditions such as the quality of the system ground In particular air circulating into the 51 11 area must not be higher than 60 C 2 3 ISV11 A CONFIGURATION Physically the ISV11 A is comprised of two quad height modules bolted together and connected by a 50 conductor ribbon cable Figure 2 3 shows INSTALLATION 23 ISV11 A
23. SUPPORT INTEGRITY OF REMOTE PROCESS WHILE 15 RUNNING DIAGNOSTICS CUSTOMER WILLING TO OPERATE NO CALL SUPPORT GO BACK TO START RUN DZKCH ON DEVICE COMBINATIONS RUN APPLICABLE DPM50 DIAGNOSTICS FROM HOST ANY PROBLEMS GO BACK A 2269 9 3ONVN3 LNIVIN LIST DEVICES ON SYSTEM CONSOLE HAVE CUSTOMER ARRANGE FOR INTEGRITY OF REMOTE PROCESS WHILE DPM50 IS RUNNING DIAGNOSTICS HAS AC POWER FAILED AT REMOTE IS DPM50 ON LINE AT PROTOCOL LEVEL NO YES START DIAGNOSTIC MONITOR RUN APPLICABLE DPM50 DIAGNOSTICS IN HOST MODE REQUEST HELP FROM CUSTOMER S ELECTRICIAN SUSPECT DRIVERS OR RECEIVERS NOT TESTED BY DIAGNOSTICS ANY NO ERRORS INTERPRET ERROR REPORTS TO DETERMINE FAULTY MODULE S SET UP MONITOR FOR LOCAL MODE TAKE SERVICE EQUIPMENT TO REMOTE SITE GO DPM50 Figure 3 6 Troubleshooting Flowcharts 5 CHECK 5V 12V LTC POWER DOWN 50 DIS CONNECT FIELD SIGNALS AS NECESSARY REPLACE KNOWN FAULTY MODULES INSTALL TERMINAL IF NECESSARY POWER UP 50 amp TERMINAL OBSERVE ISV 11A LED DISPLAY ANY NO ERRORS PART YES CALL SUPPORT YES HAVE YOU BEEN THRU HERE FREQUENTLY INTERPRET ERROR REPORTS TO DETERMINE FAULTY MODULE S H
24. also be put into a third logical state that disconnects that jumper from the ad dress match allowing for don t address bits In addition to the 77 78 APPENDICES three address jumper inputs a fourth high impedance input line is used to enable disable the MATCH output Three vector jumper inputs are used to generate a constant that can be passed to the computer bus The three inputs directly drive three of the bus lines overriding control line action Two control signals are decoded to give three operational states receive data transmit data and disable Maximum current required from the Vcc supply is 100 mA 5 RQSTA H VECTOR H N H ENADATA VECRQSTB H 17 H BDIN L ENAST H INITO L 15D ENADATA H ENACLK H R BINIT 1 95 ENACLK L 130 ENBCLK H BIAKI 12D ENBDATA H BIRQ 118 ENBST H GNOQ9 RQSTB H BIAKI L BIAKO L BINIT L BIRQ L BDIN L d gt ENBST H VECTOR H ENBDATA H ENBCLK H VECRQSTB H RQSTD H INITO L 0173 5505 Figure B 1 03 Simplified Logic Diagram tane SADIGNAddV 6 80 APPENDICES 1 CLK H 30 Fl 22 22052 ST H 7 30 RQSTA H Bed L 15 65 20 90 1 I rte ee LL EL BDIN L VAR ae NES L 35 MIN m 35 MIN I VECTOR H 10 45 lt o
25. function at both E11 and E3 The first clock after detection of the transition loads zero into E3 and shifts E11 without sampling the raw data That is pin 15 remains the same and the transition then lies between pins 14 and 13 With this change E9 6 supplies a low input to E15 DO and E2 J The sec ond clock loads again moving the transition between pins 13 and 11 This causes E9 8 to drop producing a phase locked clock which shifts E15 and loads zero into E15 RO since 9 6 is still low E9 11 also drops reen abling shifting and counting The third clock then counts E3 to one and shifts E11 resampling the raw data and shifting out the preceding transi tion This raises both E9 6 and E9 8 dropping the phase locked clock If a transition were detected E9 11 would again go high starting the whole sequence over Transmission over the serial line always begins with a few ones followed by at least two zeros The final one and the two zeros provide a string of five transitions a half bit time apart Following the just defined procedure we see that the first four transitions result in four zeros being shifted into E15 This enables the AND gates at the clear input to the dropout flip flop E2 At the fifth transition the phase locked clock clears E2 removing both the dropout signal to the USYNRT and the hold clear on flip flop E12 3 generating the R clock for the USYNRT receiver Once the system is syn chronized to the incoming serial signal a
26. line ASYNC MUX test part 2 DVDZCAO Cable and echo test RXV 11 DZRXAEO System reliability test M7946 DZRXBFO Interface DIAGS NEEDS diskette RXV21 ZRXDAO 2 floppy CVPCADO MDC 1 module test M7958 3 4 5 CVPCAx 1 0 Subsystem Diagnostic All information about the process modules the I O control module the LSI 11 bus and the H333 chassis power supply is provided in the O Subsystem User Guide CVPCAx is a complete diagnostic for testing the entire 1 subsystem The diagnostic and its use is described in the MAINDEC writeup AC A959D MC Its use is discussed briefly in Section 7 5 3 2 of the O Sub system User Guide The new version is automated process testing APT compatible and can therefore be run from the host However the only op tion that can be used when running from the host is the system test tion S This option maps modules connected to the IOCM on the D bus and runs the appropriate tests on them individually Of course the entire diagnostic is used to its full capability if downline loaded from the host and run in local mode from a terminal on the LSI 11 bus x designates current version 40 MAINTENANCE rj TU 70 9 z 666 J mum U d E m c LED S TP4 TEST POINTS TP6 2266 Figure 3 2 ISV11 A Boards 3 5 ISV11
27. logic on PCS5 and PCS6 A 124K memory would require that AD 16 and AD 17 be set up as well The 8080 must also set BS7 port 2 bit 3 if the address location lies in the I O bank Two timing diagrams TD ISV 11 0 5 and TD ISU 11A 0 6 show the relationships among the 5 quantities involved in output and input DMA transfers LSI 11 bus signals control signals for the 8080 the 8080 clocks and machine states An R or T in parentheses by a signal name means it is received or transmitted by the ISV11 A over the LSI 11 bus Movement of addresses and data between the two buses is through the 74LS367 drivers on PCS8 The signal T ADDR EN places the address on the LSI 11 bus through parts of the driver chips at the left However only 15 bits come from the 8080 bus address lines bit 15 A8 comes from port 2 instead Each data transfer is of a single byte with the low or high posi tion on the DAL lines selected by 00 Data is gated from 8080 bus to LSI 11 bus by T DATA EN with the low byte handled by E60 and part of E46 and the high byte by E59 and part of E51 Gating from LSI 11 bus to 8080 bus is controlled by a DMA signal derived directly from the 8080 memory read with low byte through E61 and part of E7 and high through E52 and part of E51 An 8080 memory reference in the 8000 FFFF range produces ENA DMA at the upper left on PCS5 This causes the 8080 to wait by pulling down the 8224 ready input on PCS2 On PCS5 it generates
28. outside edge of the M8080 and join them with three screws Make sure the short ribbon cable still connects them 5 Plug the M8080 into the module extender QUICK CHECK FOR MAJOR PROBLEMS These tests check the major functionality of ISV11 A modules They are particularly useful if the 8080 does not run all maintenance LEDs on Un less otherwise indicated all test points are on the outside edge of the 54 13290 Testing requires a voltmeter and an oscilloscope preferred or logic probe NOTE TP7 8 V and TP9 GND can be used to power the probe 44 MAINTENANCE 1 Using TP9 as a ground reference ensure that the following supply voltages are present 5 V 5 percent at TP7 12V 5 percent at 12 V 10 percent at TP6 5 VA 5 percent at TP8 5 VB 5 percent at TP5 2 Check that the modem transmitter clock T CLOCK H is present on TP 12 It is a square wave with period 18 This test also verifies that the 8080 clock generator is working 3 Check that 8080 memory read pulses BUS MEMR L are present on TP 1 This verifies that the 8080 is fetching instructions and running it is not verify on the M8080 that BPOK H E14 12 and READY H E70 23 are asserted Then replace the 8080 E70 4 The carrier detected LED should turn on dim or bright glow when a running dataway is connected and off when the dataway is removed If the LED stays on check that T ENA L TP4 is high If T ENA L is asser
29. prevents any wait during IN instruction but during an OUT it occurs later and the 8080 may enter the wait state for a single cycle The RAM and ROM that constitute local memory are SL2 and 513 spectively The RAM is made up of 8 X 1 chips each storing a single 54 SYSTEM LOGIC bit of each byte in the 1K Whereas the ROM is made up of 5 1K 8 chips with space for a sixth each storing the entire byte for 1K locations Log ic gates at the upper left on SL2 produce a memory select when the 8080 calls for a memory read or write with an address the range select in turn enables the decoding of address bit 10 12 at the lower left on SL3 to select a single ROM chip or the set of eight RAM chips The 10 least significant address bits are applied to the address inputs of all chips to select the individual location When the RAM is selected and the func tion is write bits from the eight data lines are written into the eight RAM chips The output of the selected ROM or set of RAMs is available on the SL3 memory bus During a read the data is placed on the 8080 bus via the multiplexer at the upper right on SL2 Drawing TD ISV11A 0 7 shows the timing of the signals involved in the 8080 reading and writing memory 4 3 SERIAL LINE UNIT The heart of this unit is the USYNRT synchronous communications chip at the left on 515 It is set up for byte operation by a high level at pin 22 connecting cor
30. transition that occurs before a count of 30 following a preceding transition produces a phase locked clock that loads a zero into E15 If there is no transition by clock 29 clock 30 counts to 15 and the carry out produces a phase locked clock that loads a one into E15 since E9 6 is high But subsequent detection of a transition before the next 29 count restarting the count with no transition detected ships the extra load generates a phase locked clock that loads a zero into E15 Therefore a zero data bit causes the loading of two suc cessive zeros into the first two stages of E15 A one results in a zero in RO and a one in R1 following a pair of shifts Thus at the end of each bit time the received data is represented by the state of R1 Since at this time RO is zero for either a zero or a one data bit the trailing edge of the phase locked clock sets E12 3 to start a cycle of the R clock Since the K input is held high the flip flop clears in the middle of the next bit time regard less of what the first phase locked clock brings into RO The first data bit the USYNRT actually reads is the second zero in the sync pair If no transition is detected through the 58th clock the 59th counts to 15 a second time producing a second nontransition phase locked clock With E9 6 still high and a one already in E15 this sets E2 indicating a modem dropout and disabling the receiver clock 4 3 1 3 Negative Voltage Converters The cir
31. 0 START e ANALYZE CUSTOMER COMPLAINT COLLECT FAULT INFO FROM CONSOLE ERROR LOG CUSTOMER COMPLAINT DPM50 ON LINE AT TASK LEVEL CHECK CONSOLE OUTPUT amp RUN ISBRPT TO DUMP ERROR LOG COMPARE INFO WITH PHYSICAL AN DU r can LATUYI run POSSIBLE DATAWAY PROBLEMS REPAIR OR REPLACE ne 0n i FAVLIT J ANY INFO RELEVANT TO DPM50 DEVICE SHOW MORE ERRORS THAN OTHERS YES CAN DPM50 BE RELEASED FOR DIAGNOSTICS CHART 2 ERRORS GROUPED INSPECT PAST SOME POINT DATAWAY FOR ON DATAWAY PHYSICAL DAMAGE IS FAULT TRACEABLE TO A SINGLE POINT SUPPLIED EQUIPMENT FAULTY SCHEDULE MAINTENANCE WHEN DPM50 CAN BE RELEASED DETERMINE ADVISE SPARE MODULE CUSTOMER OF AVAILABILITY PROBABLE CAUSE AND SCHEDULE OF FAULT REPLACEMENT lt o v J c INVESTIGATE ARE ALL POSSIBILITY ERRORS TIME OF PERIODIC RELATED ELECTRICAL INTERFERENCE RUN STAND ALONE ERRORS ASSOCIATED ISB 11 DIAGNOSTICS OR REPLACE ISB 11 SUSPECTED 158 11 ARE MOST MORE INFO IS REQUIRED FOR FAULT ISOLATION HAVE YOU BEEN THRU HERE BEFORE CUSTOMER WILLING TO OPERATE NO GO BACK TO START YES HAVE CUSTOMER CALL ARRANGE FOR
32. 0 register 2 and 8080 1 0 registers 3 5 that are common with LSI 11 control and status registers CSR2 and 4 Checks timeout feature of DMA logic for access to LSI 11 memory Checks LSI 11 interrupt circuit in ISV 11 A Table 3 2 Softcore Tests Test Module 12 151 11 13 MSV11 14 LSI 11 Description Loads a program into LSI 11 memory and then boots the LSI 11 this checks ability of ISV11 A to interrupt the LSI 11 and vice versa Runs address and data tests on 28K words of LSI 11 memory Runs LSI 11 instruction test by loading it into LSI 11 memory and booting LSI 11 to run it 3 4 CZKMPx DIAGNOSTIC MONITOR If the ISV11 A and its communications channel to the host are in working order DZKCHx 2 have run correctly service personnel can execute standalone LSI 11 and I O subsystem diagnostics in the DPMBO This is done with a diagnostic monitor that runs in the host com puter This monitor comes with every DPM system host It is accompanied x designates current version MAINTENANCE 37 by set of LSI 11 bus diagnostics image format file at the host Note that the file names for these are the same as under XXDP but with the extension IMG For information on these diagnostics refer to Sections 3 4 4 and 3 4 5 of this user guide CZKMPx allows service personnel to call various diagnostics for equip ment on the LSI 11 bus DPM50 system These diagnosti
33. 2 1 NAME REMOTE VCB 1 RECV AT 44560 STS 1502 VCB 2 SEND AT 44660 STS 0 DONE DLC CL 1 NO REMOTE CR 515 DONE In this ST5 report a DPM50 is shown with open channel at NODES SB numbers 1 and 2 temporary Logical Unit NumberS LUNS 2 and 1 node NAME REMOTE The Volume Control Block information is not important However if Status STS OFFLINE the DPM50 may be physically disconnected or powered down Use the command DE Vices to verify on line and off line status This DPM50 does not have an ACTIVE CONNECTION reported so it may be closed to allow diag nostics to attach to it The close command CL for DLC has as an argument the lower of the two sequential SB numbers in this case 1 The node name NO is the word following NAME in the first line of the ST5 report After the DLC command to close the channel finished executing the prompt character prints The close may take up to 30 seconds Type 575 again to verify that the operation was successful If so the DPM50 channel that was closed does not appear the new ST5 re port If an ACTIVE CONNECTION exists the ST5 report looks like this yST5 50 AT NODES 1 2 LUNS 2 1 NAME REMOTE VCB 1 RECV AT 44560 STS 1502 VCB 2 SEND AT 44660 STS 0 ACTIVE CONNECTION WB 44210 HOST TASK HEX1 REM TASK REX1 STS 200 DONE An active connection exists between a task in the host named HEX 1 and a task in the DPM50
34. 4 when BPOK H goes down Signal RESET H L RESET H L HALT RPOK L RRPLY H L RSA H RX ACT H SACK H SEL 0 2 4 L SEL 8X H SEL 90 L SEL A0 L SEL BOL SELECT 1 5 L SRPLY H STROBE SYNC L T ADDR EN H L TBMT H Print PCS2 SL6 PCS7 PCS5 PCS4 SL5 SL5 PCS5 PCS4 SL4 SL4 SL4 SL4 PCS7 PCS4 PCS2 PCS6 PCS6 SL5 GLOSSARY 93 Definition Equals RESET 1 5413290 reset from PCS2 RESET L Received B HALT Received BPOK Received BRPLY USYNRT output receiver status available USYNRT receiver active Send B SACK for DMA CSR address decoder outputs 8080 accessing l O register in address range 80 87 8080 reading 1 register 90 USYNRT status 8080 writing I O register AO USYNRT control 8080 reading 1 register BO port address Address decoder outputs for 8080 1 registers Q bus interface Send BRPLY Send 8224 to 8228 in response to CPU SYNC latches 8080 cycle status in 8228 Received B SYNC Transmit address on B DAL for DMA USYNRT transmit buffer empty 94 GLOSSARY Signal TBS7 H T CLOCK H TDATAH T DATA EN H L T DIN H T DOUT H T ENAH L TEST DISABLE 8080L TEST DISABLE TME H TMO H TMO ERR H TRANSITION DETECTED H TRANSITION DLYD L T RAW DATA H T SYNC H T WTBT H TX ACT H VEC RQST B H Print PCS7 SL1 SL5 PCS6 PCS6 PCS6 SL5 PCS6 PCS6 PCS7
35. 45 pu le I o n c V w TT BIAKO L 12 55 12 55 Times nanoseconds 11 4150 5503 Figure B 2 DCOOS3 Interrupt Section Timing Diagram APPENDICES 81 sur I INITO L 2614 2150 DATA H CLK H ENB ST H BIRQ L t RQSTB H 1 ENA CLK H 30 MIN c F ST H RQSTA H BDIN L BIAKI L 1 1 VECTOR 0 45 10 45 ss VECRQSTB H 15 65 4 i 15 65 Times are nanoseconds Figure B 3 03 Interrupt Section Timing Diagram Sections A andB 11 4151 MA 5502 82 APPENDICES ENB H BSYNC L BDAL2 L BOALI L BDALO L BWTBT L BDIN L Figure B 4 VECTOR H BDAL2 L 2 ENB H L RXCX H EDALO L G4 SEL6 L BWTBT L C5 SEL4 L BSYNC L SEL2 BOINL 7 SELO L BRPLY 58 OUTHBL BDOUT L G9 OUTLBL GND INWD L vec d O aa D 1 02 D 4 01 Sas D 1 LATCH DECODER BDOUT 1 TD gt gt 04 Simplified Logic Diagram SEL6 L SEL 4 L SEL 2 L SEL O L OUT HB L OUT LB L RXCX H BRPLY L VECTOR H INWD L 0174 5504 APPENDICES 83 BDAL 2 1001
36. 7 3 4 2 Local Mod vw xa a wer Ed AC 38 3 4 3 Communications Mode 38 3 4 4 LSI 11 MAINDEC Diagnostics 38 3 4 5 CUPCAx Subsystem Diagnostic 39 3 5 LON TESI fxd ha hd ot NC eR t BE Daya dhe act 40 3 5 1 LED mun katate Oe oa Seine 40 3 5 2 Test POINTS oum SSS Sua ed e Y Z a 41 3 5 3 Modules Troubleshooting 42 3 6 H7870 Power 45 3 7 DPMBO Troubleshooting Flowcharts 45 CHAPTER 4 SYSTEM LOGIC 4 1 tir ip iR s aut quA 51 4 2 Processing UNIT us es poet qq 53 4 3 Serial Eie nit 45 ma v xx d qe are e rto x cr eot d 54 4 3 1 Serial Transmitter Receiver 55 4 4 SHIT Bus div Pee Gattis Ss ire eRe RR 61 4 4 1 Port Transfers Coena dades nacio Se edo Ward ei 61 4 4 2 LSI 11 Interrupt Control LEE YS 62 4 4 3 DMA Transfers e rice d ora dox uo 63 4 5 FUNCTIONAL PIOWS x exe tA Ra h RO Y CEN 64 APPENDIX LOGICAL DISCONNECTION OF A DPM50 FROM THE HOST SYSTEM APPENDIX SPECIAL CIRCUITS SIGNAL GLOSSARY FIGURES 1 1 DPMBO Organization ir a Typical DPM System
37. 70 power supply Figure 1 6 Table 1 2 details their functions Figure 1 7 shows the five LED indicators on the M7958 IOCM For more information about these indicators refer to Chapter 3 of the O Sub system User Guide There are five LED indicators on the ISV11 A module Refer to Figure 3 2 and Section 3 5 1 of this manual for their location and function respective ly Table 1 1 DPM50 XX System Configuration Standard Equipment H333A master chassis 115 Vac H333B master chassis 230 Vac M7958 I O control module KD11 HLSI 11 microprocessor with KEV 11 KDF 1 1 A LSI 11 23 microprocessor MSV 11 DD 16 bit X 32 Kw MOS memory ISV11 A DECdataway to 51 11 bus Interface TEV 11 LSI 11 bus terminator NOTE 1 Originally shipped with two MSV11 CD 16 bit x 16K MOS Memory Modules AA CA X X Note 1 X INTRODUCTION 50 CB x Note 1 X X X X X X X X X X X Note 2 Note 2 9 NOTE 2 The ISV11 A must have ECO Rev 4 incorporated to operate in the DPMS50 Fx and Hx versions 1 3 3 Hardware Options The following hardware options are available for all current versions of the DPM50 Cabinetry The 50 is a cabinet or rack mountable device Typi cal cabinets used for DPM50 mounting are DEC H960 C cabinets and NEMA 12 cabinets O Modules A wide variety of analog and digital input and output modules
38. A DLV 11 J KA 1 9 A minus 0 3 A Only one supported per DLV 1 1 KA system RXV11 RXV21 1 87 2 02 A minus O 30 A DLV 1 1 KA DZV 11 B 1 49 A 1 64 A minus 0 30 A DLV11 KA MSV11 D 1 42 A 1 57 A minus 0 30 A second DLV 1 1 KA DLV 1 1 F 1 75 A 1 9 A minus 0 30 A DLV11 VA The 12 V current available for the modules varies depending which LSI 11 bus options are present in the H333 Table 2 4 shows the amount of 12 V current available to the I O modules for various LSI 1 1 bus configurations NOTE Due to Field Service requirements outlined in Section 2 4 1 all specifications in Table 2 3 are based on the assumption that a console terminal interface DLV11 F DLV11 J is present in the LSI 11 bus CHAPTER 3 MAINTENANCE 3 1 OVERVIEW WARNING Do not initiate any DPM50 diagnostic or maintenance soft ware before checking with local site personnel for any safety precautions to be performed and or any operating restrictions The DPM50 is a re mote process controller Its modules may control very perhaps dangerous industrial processes This chapter is divided into the following three main areas Sections 3 2 through 3 4 are devoted to DPM50 related maintena ce software and firmware Sections 3 5 and 3 6 contain information about the ISV11 A and the H7870 power supply respectively This is DPM50 specific monna tion not found in the O Subsystem User Guide Sect
39. A The maintenance philosophy for the ISV11 A is option replacement How ever careful analysis of faults using diagnostics and available test points should permit service personnel to isolate a problem to one of the two modules Section 3 5 3 of this user guide provides guidelines to aid in iso lating a problem to one module Note that the ISV11 A operates only as unit that is with the M8080 and 54 13290 boards connected together However they are not a matched set a single board can be replaced if necessary 3 5 1 LED Displays As seen in the edge on view of the boards Figure 3 2 there are four LEDs on the M8080 board and one on the 54 13290 The single LED on the latter board is lit whenever a message is being transmitted to or from any port on the dataway not just this ISV11 A The light goes out at the end of every message but goes right back on again as soon as the next MAINTENANCE 41 message is detected This is because the ISV11 A receiver picks up all transmissions on the dataway including its own transmission to the host The light can be off for a significant time only if the dataway is inactive out of order or if something is wrong with the receiver The LEDs on the M8080 board are all on at power up If they remain on the ISV11 A is broken so badly that the onboard 8080 microprocessor cannot even start its ROM resident diagnostics which run automatically following power up As the diagnostics run each displays its
40. ARDCORE TEST FAILURE REPLACE ISV 11A REPLACE LSI 11 OR MSV11 AS INDICATED ie CHART 3 gt CHART 3 SOFTCORE TEST FAILURE NO PROMPT gt ON TERMINAL TERMINAL IS ON LINE TO MONITOR RUN APPROPRIATE DIAGNOSTICS TO VERIFY REPAIR MA 2270 Chart 2 DPM50 Subsystem Procedure Part A LV 48 MAINTENANCE EXIT MONITOR POWER DOWN DPM50 REMOVE EQUIPMENT THAT IS NOT PART OF SYSTEM RECONNECT FIELD WIRING POWER UP DPM50 MAKE SURE ISV 11A ROM TESTS PASS RELEASE SYSTEM TO CUSTOMER FOR APPLICATION TEST ANY NO ERRORS YES IS FAULT TRACEABLE TO AN MODULE YES ANY MODULE FUSES BLOWN YES NO YES REPLACE MODULE Figure 3 7 PROBLEM YES STILL THERE INVESTIGATE POSSIBILITY THAT CUSTOMER HARDWARE IS CAUSING MODULE TO FAIL OR THAT SPARE MODULE 15 BAD IF PROBLEM PERSISTS CALL SUPPORT DONE CLOSE UP amp DO PAPERWORK IS FAULT TRACEABLE TO CUSTOMER HARDWARE CALL SUPPORT HELP CUSTOMER ISOLATE HIS PROBLEM REPLACE FUSES PROBLEM STILL THERE MA 2427 Troubleshooting Flowcharts Chart 2 DPM50 Subsystem Procedure Part B MAINTENANCE 49 IS DATAWAY CONNECTED NO YES COMPARE REPORTED TERMINAL REPORT ADDRESS 778 REPLACE YES ISV 11A CONNECT NO ADDRESS WITH EXPECTED ADDRESS amp ADDRESS WIRE
41. D IN INSPECT CONNECTOR amp CABLE FOR SHORTS OPENS LOOSE PINS DATAWAY amp POWER UP AGAIN PORT CONNECTOR OK NO CHART 2 PARTA ASK CUSTOMER TECHNICIAN TO REPAIR IT REPLACE ISV 11A CABLE POWER UP AGAIN WITH DATAWAY CONNECTED VERIFY OPERATION OF TERMINAL 2 VERIFY THAT MONITOR IS RUNNING AT HOST WITH SCOPE CHECK FOR DATAWAY SIGNAL AT CONNECTOR BEEN THRU HERE SEVERAL YES TIMES FINALLY GAINED YES YES SIGNAL NO NO COMMUNICATION PRESENT WITH J US NO CHART 2 CHART 2 CONSULT DATAWAY USER S GUIDE AND TM PART A PART A CALL SUPPORT Figure 3 8 Troubleshooting Flowcharts Chart 3 Port Address Checkout MA 2271 CHAPTER 4 SYSTEM LOGIC 4 1 OVERVIEW The ISV11 A is a dual quad height printed circuit board option It is built around two large scale monolithic integrated circuits an 8080 micro processor and LSI synchronous communications device USYNRT In order to understand how the hardware functions readers must be familiar with the operation of these two circuits as explained in the vendor man uals A signal name glossary has been provided at the end of this manual Figure 4 1 is a block diagram showing the logical organization of the hard ware on the M8080 ISV11 A microprocessor and the 54 13290 serial line unit Logically the system has three major subdivisions organized around two internal buses one of which is simply an e
42. DAL inter faces to the bidirectional LSI 11 bus data and address lines B DAL by the DCOOS5 transceivers at the left on PCS4 The XMIT input is enabled for driving the LSI 11 bus from its extension when one of two things is hap pening When the LSI 11 is reading a control status register CSR or when the ISV11 A is sending DMA address or data to the LSI 11 memory or I O bank At all other times the REC input is enabled driving the exten sion from the LSI 11 bus However enabling REC also allows high levels at the JAV inputs to drive the LSI 11 bus lines independently These in puts are connected for VECTOR to place an interrupt vector on the B DAL lines where a jumper in is a one When the 1 bank select signal BS7 is true at E23 13 the JA inputs are compared with levels on certain LSI 11 bus lines The lines are not c n nected to the chips in order this is so a comparison can be made be tween JA inputs and lines 3 12 The match output is true when BS7 is true and bus lines 3 12 contain the address of the ISV11 A CSRs set into the JA jumpers A jumper in is a one Type 8641 transceivers are used for interfacing to LSI 11 bus control sig nals usually bidirectional These transceivers appear on various prints at those parts of the logic with which they are associated 4 4 1 Port Transfers Programmed transfers are handled through what are regarded as 16 bit control status registers from the LSI 11 and 8 bit ports from the 8080
43. ED SLOT BETWEEN THE PROCESSOR AND THE ISV11 A RENT Figure 1 4 DPMS50 Ax Cx Physical Layout INTRODUCTION 11 CONNECTOR TO DECdataway ISV11 A CABLE OPTIONS INTERFACE INTERFACE 5 M7958 10CM LSI 11723 PROCESSOR 11 D BU darum 1 0 MODULES LSI 118US Aq 2 ET Wa cy LEE 2503 LSI 11 TERMINATOR __ r MODULE D BUS U EXPANSION _ _ I CONNECTOR DB8US SLOT NUMBERS 12V DC an ON R RUN ENA H7870 POWER SUPPLY O ES s O OFF HALT MASTER CHASSIS NOTE A G7272 CONTINUITY MODULE MUST BE INSTALLED INANY UNUSED SLOT BETWEEN THE PROCESSOR AND THE ISV11 A Figure 1 5 50 Hx Physical Layout LINE FUSE AC ON OFF CONTROL MA 3441 Figure 1 6 7870 Power Supply H332 Mounting Rack with Terminal Strips This provides a conven ient point for connections between 1 modules and field wiring of external processes H7006 A B Filter Panel This provides EMI filtering for serial inter face cabling 20 mA or EIA RS232C connecting the LSI 11 to modems or terminals outside the DPM50 cabinetry For information concerning the options listed previously except the H7006 A B Filter Panel refer to the O Subsystem User Guide Section 12 INTRODUCTION Table 1 2 H7870 Switches and Indicators Switches and indicators AC ON OFF switch Line fuse Power control outlet
44. EMR L BUS MEMW L B WTBT L CARRIED LED CPU SYNCH H DAL 0 15 H DAL LB BUS D L DIN L DIS 8X CLK L DIS Print PCS6 PCS7 PCS2 PCS2 3 7 SL2 4 PCS8 PCS2 PCS2 PCS2 SL2 PCS2 PCS2 PCS6 SL1 PCS2 PCS4 7 PCS8 PCS6 SL6 SL6 GLOSSARY 89 Definition LSl 11 bus master has placed address on bus From BUS A00 H 8080 bus address lines 8080 bus data lines 8080 data to LSI 11 bus high byte 8080 interrupt acknowledge 8080 reading an I O register port 8080 writing an 1 register port 8080 reading local memory or receiving interrupt RST 8080 reading memory or I O register addressed as memory 8080 writing memory or I O register addressed as memory LSI 11 bus write byte Controls carrier detected LED 8080 signal to 8224 to indicate first state in each machine cycle Data and address lines on LSI 11 bus extension LSI 11 bus data low byte to 8080 Received B WTBT GR test disable for 8X CLK GR test disable for 8080 I O address decoder 90 GLOSSARY Signal DIS MEM L DIS RAW DATA L DMA ACK H DMA MEMR H DMA MEMW H DMR DOUT L DROPOUT H L DROPOUT L H OR RSA H ENA DMA H EXT 8X CLK L EXT RAW DATA H EXT R CLOCK L EXT R DATAL FRPLY H L HALT LSI H INT H Print SL6 SL6 PCS6 PCS5 PCS5 PCS5 PCS6 SL1 SL5 PCS5 SL6 SL6 SL6 SL6 DCS6 PCS7 SL2 Definition GR tes
45. PCS7 PCS7 SL1 SL1 SL1 PCS6 PCS6 SL5 PCS4 Definition Transmit B BS7 Transmitter clock 55 556 KHz USYNRT serial data output Transmit data on B DAL for DMA Transmit B DIN for DMA Transmit B DOUT for DMA Enable modem transmitter when USYNRT transmitter active but not in maintenance mode GR test disable 8080 operation GR test disable 8080 I O register addressing Timeout enable for DMA DMA timeout Timeout error status bit 8080 to LSI 11 Receiver detected a zero crossing Transition detected inverted and delayed 500 ns Flip flop biphase encoded data signal applied to transmitter circuit Transmit B SYNC for DMA Transmit B WTBT for DMA USYNRT transmitter active Makes vector jumper address 304 when VECTOR is true Signal VECTORH WAIT L WRITE 1 2 H WTBT L Print PCS4 PCS2 PCS7 PCS6 GLOSSARY 95 Definition Places vector jumper address JAV on B DAL when the 8080 interrupts the LSI 11 Puts 8080 wait state until DMA acknowledged Select 8080 I O registers 1 and 2 for writing Received B WTBT DPM50 User Guide Reader s Comments EK DPM50 UG 002 Your comments and suggestions will heip us in our continuous effort to improve the quality and useful ness of our publications What is your general reaction to this manual In your judgement is it complete accurate well organized well written etc ls it easy to use What features are most
46. The two zener diodes back to back shown at the left of the connector draw no current until the potential reaches 9 V and then they draw a great deal This prevents a surge on the dataway from burn ing out the operational amplifiers During transmission the zeners limit output to 9 V even though the transmitter circuit output is about 12 V With the dataway connected there is an effective 100 ohm load This is due to 56 SYSTEM LOGIC T DATA H j T CLOCK H 1X CLK H J j L L E12 JK 12 9 2X CLK L SLL LJ Ul Ul T DATAH 1 I E12 5 Li Li Li Figure 4 2 Transmitter Timing either the 200 ohm terminating resistor in parallel with the cable or being mounted in the middle of the 200 ohm cable Therefore the line is actually driven at about 5 V The only control signal supplied by the to the modem is T ENA at D8 When this signal is true the T1 primary can be driven at one side or the other to drive the serial line When T ENA is false the transmitter is disabled and the receiver picks up any data coming from the DECdata way The disable and external inputs as well as various outputs of the circuit are available at the test socket on SL6 Test inputs allow for disabling the clock and the raw received data so external inputs can be substituted for them Conversely without the disables the external connections make the internal clock and raw data available a
47. Use W7 W8 PROM selection W1 W6 W9 W10 PROM power Figures 2 4 and 2 5 locate the jumpers for M8080 and 54 13290 respec tively 2 4 151 11 MICROCOMPUTER CONFIGURATION The LSI 11 modules must be configured correctly for proper DPM50 oper ation System configuration refers to the position of the LSI 11 modules within the LSI 11 backplane as well as switch and jumper settings on the modules themselves This section assumes a basic familiarity with the LSI 11 bus The reader who wants an in depth discussion of the 151 11 should refer to the Microcomputer Processor Handbook 15836 18 INSTALLATION 25 5 gt G um v 7 W1 W8 MA 2268A Figure 2 5 54 13290 Board 2 4 1 LSI 11 Bus Backplane Configuration The recommended placement of LSI 11 modules the LSI 11 backplane is shown in Figures 2 6 and 2 7 Figure 2 6 shows placement of these modules in the DPM50 AA AB CA or CB models Some earlier versions of these models were shipped with MSV11 CD MOS memory modules The early version is shown in Figure 2 6A The current version is shown jin Figure 2 6B Standard equipment for these models include the following features KD11 H M7264 YA YC LSI 11 CPU with the KEV11 A floating point option MSV11 DD M8044 D 32K x 16 bit MOS memory TEV11 9400 LSI 11 Bus Terminator 26 INSTALLATION lt
48. aded to the host for display f 3 3 1 Hardcore Diagnostics The first 9 1 11 octal ISV11 A ROM resident diagnostic tests are consid ered hardcore If a hardcore error is encountered CZKCIx fails and no er ror information is upline loaded to the host Table 3 1 describes the hardcore tests 3 3 2 Softcore Diagnostics Tests 12 13 and 14 of the ISV11 A ROM resident diagnostic tests are considered softcore For example this type of error does not hinder the ISV11 A ability to communicate with the host lf a softcore error is encoun tered while running under CZKCIx error information is upline loaded to the host and displayed at the operator s terminal Table 3 2 describes the softcore tests x designates current version 36 MAINTENANCE Table 3 1 Hardcore Tests Test Module Description 1 M8080 2 54 13290 3 54 13290 4 54 13290 5 54 13290 6 54 13290 7 M8080 10 M8080 11 Both Checks power up configuration of 8080 1 registers 1 2 and does basic 8080 instruction test Does individual cyclic redundancy check on each 8080 ROM Checks writing and reading in the 8080 RAM and checks out RAM addresses Checks transmission and reception in USYNRT communications chip using maintenance mode If dataway connector is unplugged i e address 77 is read this test checks transmission and reception in the USYNRT through the modem otherwise test is skipped Checks ISV 1 1 A interrupt system Checks 8080 1
49. ae Y WW Wai Ol S 5 A EARLY SHIPMENTS 401 141 421 dc 5 he i O i i MASTER CHASSIS 333 LSI 11 BUS RESERVED FOR 1 0 MODULES 2 A G7272 CONTINUITY MODULE MUST BE INSTALLED IN ANY UNUSED SLOT BETWEEN THE PROCESSOR AND THE ISVII A D BUS NI SW 1 1 I i 1 G7272 G7272 rg ue ha i G7272 B CURRENT SHIPMENTS r MSV11 DD KD11 H KEV11 A OPTION pm 8 7 6 5 MASTER CHASSIS 333 LSI 11 BUS RESERVED FOR 1 0 MODULES D BUS 07272 CONTINUITY MODULE MUST BE INSTALLED IN ANY UNUSED SLOT BETWEEN THE PROCESSOR AND THE ISVII A 02318 Figure 2 6 50 LSI 11 Module Placement 7272 67272 EST SN G7272 RD OPTION Si MSV 11 DD KDF11 AA 12 11 10 9 8 7 6 5 4 3 MASTER CHASSIS H333 LSI 11 BUS 7 2 RESERVED FOR 1 0 MODULES D BUS 2 A G7272 CONTINUITY MODULE MUST BE INSTALLED IN ANY UNUSED SLOT 3ETWEEN THE PROCESSOR AND THE ISVII A MA 0231A Figure 2 7 5 HB LSI 11 Module Placement INSTALLATION 27 The DPM50 AA CA and CB supported options from each egory are as follows DLV11 DLV11 F or DLV11 J Asynchronous Line Interfac
50. al origin They are also used in the text and the block diagrams for referencing individual prints In Figure 4 1 these labels appear in the lower left corners of each block to indicate which print contains the logic repre sented by the block Parts of a print are indicated by combining the letters 51 PROCESSING UNIT SERIAL LINE UNIT RESET 1 1 TER Au DECdataway CLOCK ADDRESS 2 TTL PCS 2 DECODER 814 ROM INTERRUPT 8080 SL3 5KX8 PRIORITY USYNRT o ed MODEM PCS 2 CONTROL amp Si ADDRESS 512 STROBE 513 so ne CONTROL DATAWAY eda e sas ms isi INTERRUPT is PORT BO DRIVERS 516 92 SL4 6 PORT AO SL5 PCS 2 812 1KX8 515 8 BUS 00 7 po 8080 ot ME qup ae LSI 35 INTERRUPT DMA DRIVERS CONTROL PCS 8 16 PCS 4 EN PORT 1 PORTS 142 mE PCS7 8 2X8 CSRO B c PCSB 4 PORT 5 CSR4 PCS3 4 PCS3 CSRO PCS7 DAL 0 3 151 1 0 ADDRESSES 160140 CSR NUMBER 8080 MEMORY ADDRESSES FOR PORTS 4000 PORT NUMBER DMA DRIVERS PCS 8 16 DMA DRIVERS PCS 8 16 8641 CONTROL TRANSCEIVERS PCS 4 7 CONTROL LINES LSI 11 INTERFACE DAL 0 3 BUS TRANSCEIVERS INTERNAL 151 11 BUS EXTENSION PCS4 16 MA 2285 Figure 4 1 ISV11 A Logical Organization ea 21901 WALSAS SYSTEM LOGIC
51. and the host system software A channel may be open in one of the two following ways 1 2 There may simply be an open channel established between an on line DPM50 and host system software with no task actually using the channel In this case the procedure detailed below is sufficient to disconnect the DPM50 so that a diagnostic task may be attached to it There may be an active connection between a task in the host and one in the remote DPM50 as indicated by the status reporting task ST5 detailed below WARNING If an active connection exists the channel should never be closed without permission from the system operator The 50 is cess control device and an untimely shutdown could cause a safety haz ard PROCEDURE 1 Determine the DECdataway port numbers and corresponding SB numbers of the DPM50 to be diagnosed The physical port addresses are associated with SB numbers in the operating system at SYSGEN time On line or off line status of the SB numbers can be determined by using the command DEVices In this example the DPM50 is at DECdataway port addresses 1 and 2 SB numbers 1 and 2 At an MCR terminal type the following entry ST5 CR 73 74 APPENDICES This prints a report of all open DPM50s If the desired DPM50 does not appear then it is not open and diagnostics can be run on it The ST5 report looks like this operator input is underlined ST5 CR DPM50 AT NODES 1 2 LUNS
52. as the signal paths and logic elements that enter into their execution All logic elements are labeled for the circuit schemat ics on which they appear The objective of a drawing is to identify all sig nificant elements that play a role in a given operational sequence to help pinpoint the trouble The investigator can then turn to the referenced schematics for details of circuit signals and pin connections These flows are meant to stand alone no written description accom panies them since the detailed description of the logic geared to sche matics has already been presented All lines are labeled with the actual signal names from the schematics and wherever possible the logic ele ments are represented by the symbols in the schematics It has however been necessary in some cases to employ ordinary blocks as logic ele ments These are easily identified because the signal lines entering them SYSTEM LOGIC 65 have arrowheads None of the diagrammed operations are comprised of only a single sequence of events Rather each is made up of several log ically distinct but interdependent sequences such as an 8080 instruction followed by an interrupt then another 8080 instruction Another sequence is an 8080 instruction followed by a response from the LSI 11 followed an action by the ISV11 A The numbers in circles indicate the order in which the hardware parts are employed for these sequences Sections of the hardware tested by power u
53. at produced by equipment in the cabinet must be calculated Then using the curve in Figure 2 2 the maximum allowable temperature where the cabinet is being installed can be determined For applications where the temperature outside the cabinet exceeds al lowable limits additional cooling is required NEMA cabinets available for the DPM50 are provided with pipe fittings to allow circulation of clean air for cooling The compressed air introduced into the cabinet also main tains a positive pressure inside the cabinet This protects the equipment from dirt dust or other corrosive material in the factory environment Air purging the NEMA cabinet is achieved by connecting an air source to a hole at the bottom of the cabinet and opening a hole at the top of the cabinet The air supply should be filtered and oil free It should also have a shutoff valve to facilitate service and a pressure relief valve in case the 22 INSTALLATION cabinet exit port becomes obstructed For a free standing NEMA 12 in stallation the following approximate relation between air flow air temper ature heat dissipated and ambient temperature holds true T2 T4 1 8 T4 Ta Pmax 90 Where To Maximum ambient temperature where the NEMA 12 cabinet is to be installed C Ty Maximum allowable temperature for the electronics for any member of the I O subsystem family 60 C AF Air flowin CFM TA Temperature of purge air C Pmax
54. ation Services NR2 M15 Customer Services Section For information concerning Microfiche Libraries contact the following group Digital Equipment Corporation Micropublishing Group BU D2 Bedford Mass 01730 CHAPTER 2 INSTALLATION 2 1 OVERVIEW The DPM50 process I O subsystem with the addition of an ISV11 A DEC dataway interface is similar to an IP300 process I O subsystem There fore most site preparation and installation information for the DPM50 is in the latest O Subsystem User Guide EK OPIOS UG Chapter 3 of that manual describes unpacking inspection installation configuration and checkout procedures for a complete process 1 subsystem However there are subtle differences between some versions of the 50 and the IP300 Therefore this chapter supplements the O Subsystem User Guide by providing configuration and installation information in the follow ing areas H333 Section 2 2 Cabinetry Section 2 2 2 ISV11 A Section 2 3 51 11 Bus Section 2 4 1 LSI 11 Bus Modules Section 2 4 2 D Bus Section 2 5 The port connector on the DECdataway is of special interest to someone installing the DPM50 The ISV11 A cable plugs into this connector The connector is wired with the lower of the two port addresses that the ISV11 A responds to For information on configuring the DECdataway port connector refer to Chapter of the DECdataway User s Guide EK ISB11 UG 2 2 H333 INSTALLATION The first part of this se
55. ces a register on the data lines READ 8X from the address decoder drives the 8080 bus from them The E30 gate below the decoder on SL4 prevents register selection at all if the 8080 should give a read function for a write port The remaining 2 ports are at the upper right on SL5 where address 90 reads status bits from the USYNRT and the modem the LSI 11 interrupt request through E22 Address AO loads a byte from the 8080 bus into the register in E27 The control bits supplied include enables for transmitter and receiver in the USYNRT maintenance mode and for various condi tions that can request interrupts through gates at the upper right Select ing maintenance mode inhibits generation of the transmit enable to the SYSTEM LOGIC 55 modem T ENA at Cl even if the USYNRT transmitter is active TX ACT The interrupt request levels are applied to the latch and priority network at the upper left on SL2 Any interrupt request produces the INT signal which goes to the 8080 Response by the 8080 with an acknowledgement latches the current request enables the multiplexer for the SL2 bus 8080 bus data lines and selects as multiplexer input an RST instruction en coded from the number of the highest priority request The 8080 then exe cutes the RST as a call to the corresponding location as listed in the table at the lower right on SL5 4 3 1 Serial Transmitter Receiver The modem for the serial line unit takes up most of SL1 The basic time
56. computer Processor Handbook EB 15836 18 Microcomputer Interfaces Handbook EB 17723 20 Chapter 1 provides functional physical and software descriptions speci fications and a list of related documentation Chapter 2 provides installation and configuration information This chap ter relies on information contained in the manuals listed above Chapter 3 provides maintenance procedures and troubleshooting flow charts Chapter 4 provides a detailed technical description of the ISV11 A DEC dataway Communications Interface 1 2 FUNCTIONAL DESCRIPTION DPM50 is an industrial 1 subsystem which uses LSI 11 LSI 11 23 based microcomputer an interface to the DECdataway This terface to the DECdataway makes the DPM50 a subsystem a DPM sys tem 2 INTRODUCTION DECdataway ISV11 A DECdataway TO LSI 11 INTERFACE SUBSYSTEM FIELD WIRING CONNECTION POINTS TERMINAL STRIPS 51 11 MICROCOMPUTER EXTERNAL PROCESS REMOTE ANY SUBSYTEM OR TERMINAL WHICH INTERFACES TO A DECdataway THE 50 IS AN EXAMPLE OF A REMOTE 5758 Figure 1 1 DPM50 Organization in a Typical DPM System 1 2 1 Distributed Plant Management Overview DPM is a concept that connects a PDP 11 host computer to remote sub systems or terminals scattered through an industrial environment DEC dataway is the communication channel that links the host computer to these remote subs
57. cs down line loaded into LSI 11 memory and executed by the LSI 11 Host mode local mode and communications mode are available for carrying out this procedure In host mode the operator remains at a host terminal and re ceives pass fail and pass count information via upline reporting Local mode allows operators to go to the remote site and run diagnostics from a terminal on the LSI 11 bus connecting a portable terminal if necessary This method allows operators to call and run diagnostics from the local terminal and receive complete error information Communication mode is similar to host mode with one major advantage The operator stays at the host terminal and receives not only pass fail and pass count information but also error messages generated by the diagnostic running in the DPM50 CZKMPx runs as a task under 5 11 To run it the operator ters RUN CZKMPx in response to the MCR prompt character gt In re sponse to further prompts the operator selects the mode gives the num ber of the DECdataway ISB1 1 A controller and gives the port address the DPM50 to be tested 3 4 1 Host Mode Host mode is used to verify from the host individual component oper ation in several DPM50s is not as comprehensive as the testing pro cess conducted in local mode at the DPM50 site However it provides an efficient method for service personnel to verify basic functionality of re mote subsystems scattered over a
58. cted LED after each step Effect LED 1 Power up ISV11 A with dataway Transmitter idle 2 Connect jumper 1 from TP4 Transmit 1s Off E ENA L to TP9 GND 3 Connect jumper 2 from TP2 Transmit Os On T DATA H to TP9 GND 4 Disconnect jumper 1 Transmit 1s On 5 Disconnect jumper 2 Transmitter idle Off If the test fails repeat it observing these points with the scope after each step Step CLOCK H TP 13 DATA H TP 11 1 Logic O Logic 1 2 Logic 0 Square wave 18 us 3 Square 18 Logic 0 4 Square wave 18 Square wave 18 us 5 Logic 0 Logic 1 3 6 H7870 POWER SUPPLY In a 50 the ISV11 A is mounted an H333 chassis which contains its own power supply The HALT ENA switch on this power supply must set to ENA Furthermore the 5 V output of the supply must be in the 5 1 V 0 15 V range Instructions for adjusting the supply are given in Section 7 4 1 of the O Subsystem User Guide 3 7 DPM50 TROUBLESHOOTING FLOWCHARTS WARNING Do not initiate any DPM50 diagnostic or maintenance ware before checking with local site personnel for any safety precautions to be performed and or any operating restrictions The 5 is a re mote process controller modules may control very sophisticated and perhaps dangerous industrial processes The rest of this chapter is a series of flowcharts Figures 3 5 through 3 8 that define a troubleshooting procedure for the DPM5
59. ction gives general information applicable to all in stallations The remaining three parts give specific information about sys tems delivered in DIGITAL cabinets or mounted in NEMA enclosures or other customer enclosures 2 2 1 General Considerations Every cabinet used for mounting any equipment in a system must be prop erly grounded The correct procedure is described in Section 1 Chapter 3 of the Digital Site Preparation Guide EK OCORP SP 18 INSTALLATION Any enclosure or free standing piece of equipment must be situated for easy access and maintenance by Field Service There must be good light ing and ample working space around the equipment Wall mounted enclo sures must be a reasonable height above solid safe and roomy walk ways The site must also provide service outlets for scopes and other maintenance equipment In the H333 there is a filter on the power line in the H7870 power supply In a standard DIGITAL installation additional filtering is provided by an 861 series power controller This controller has switched outlets that can be used for other system units terminal or disk provided they are always powered on and off with the H333 Other equipment scopes mainte nance gear or system units that can be turned on or off independently of the H333 should use independent outlets like the unswitched ones on the 861 Better yet such equipment should have its own separate filter The power checkout procedure in Section
60. cuit at the left 516 provides one 12 V and two 5 V supplies from 5 V Two separate 5 V supplies are necessary for handling the large power requirements of the PROMs SYSTEM LOGIC 61 Each 5 V converter is comprised of an inverter oscillator using a satu rable core transformer a negative rectifier a filter and a three terminal regulator chip that produces the regulated 5 V Oscillator frequency is about 40 KHz The transformer primary has a 9 V square wave centered at 5 V the secondary has an 18 V square wave centered at ground Filter output to the regulator is approximately 8 V The 12 V converter uses the 9 V square wave across the T3 primary to drive a charge pump C55 D10 D11 C56 The pump output is super imposed on the 8 V rectified secondary output to produce an unregu lated 17 V which is converted to a regulated 12 V by zener diode D12 To prevent large instantaneous switching currents in the oscillators from coupling into the main 4 5 V supply they have separate inner layer ground and planes The separate plane is decoupled from the main plane by an LC filter and the separate ground plane is connected to the main ground plane at a single point 4 4 LSI 11 BUS INTERFACE This unit handles all communication programmed transfers DMA trans fers and interrupts between the ISV11 A and the LSI 11 processor and memory The bidirectional LSI 11 internal bus extension PCS4
61. d The downline control task DLC is callable at the host through the monitor console routine MCR It allows the user to download a sys tem image to 50 and initialize host remote communication 2 Upline Crash Dump Another MCR callable task upline dump ULD allows the user to bring the DPM50 system image to a disk file at the host It is stored there for later analysis by the RSX 11M crash dump utility 3 Interactive Program to Program Communication An ancillary control processor ACP manages a single program to program connection between the host and each remote A host pro gram written in MACRO 11 QIO interface or FORTRAN IV CALL interface can communicate with a user program in a 50 using ACP 50 diagnostic and maintenance software is discussed in Chapter 3 Additional software for the LSI 11 microcomputer in the 50 includes the following e ISV11 A DECdataway driver Complete support for the complement of process I O modules Language support for MACRO 11 and FORTRAN ACP to support the program to program link to the host 1 5 SPECIFICATIONS Specifications for all LSI 11 microcomputer components in the 50 are provided in the Microcomputer Processor Handbook and the Micro computer Interfaces Handbook Specifications for the remaining DPM50 components except the ISV 11 A are provided in Section 1 4 of the O Subsystem User Guide Specifica tions for the ISV11 A are prov
62. e because of cabling requirements the DLV11 J can only be used with the DLV11 KA option Field Service requires this interface for terminal connection to run local diagnostics RXV11 or RXV21 Dual Drive Floppy Disk System When this option is selected the TEV11 can be replaced with a REV11 to provide local boot capability The recommended placement of LSI 11 modules in the DPM50 FA FB HA and HB models is shown in Figure 2 7 Standard equipment for these models include the following features KDF11 AA M8186 LSI 11 23 CPU This can be upgraded with the KEF11 A floating point chip hardware option MSV11 DD M8044 D 32K x 16 bit MOS Memory TEV11 9400 LSI 11 Bus Terminator DPM50 FA HB models support to two 2 of the op tions listed below However Field Service requires an asynchronous line unit to connect a terminal for diagnostic purposes Therefore if more than one option is desired one must be an asynchronous line unit Customers can choose from the following four supported options DLV11 F DLV11 J Asynchronous Line Unit Because of cabling requirements the DLV11 J can only be used with the DLV11 KA op tion DZV11 B Four Channel Asynchronous Multiplexer Interface MSV11 DD 32K 16 bit MOS Memory additional RXV11 RXV21 Dual Drive Floppy Disk System Because the LBI 11 23 KDF11 A and the REV11 are incompatible local boot of the floppy dis
63. e 330 turns on T SYNC and time 440 clears T ADDR EN For writing 440 also sets T DATA EN to gate the byte onto the LSI 11 bus and 550 turns on T DOUT to make the slave accept it But for reading 550 turns on T DIN to tell the slave to send data and the read level itself gates the DAL lines onto the 8080 bus with the trans fer time determined by the slave With SACK still asserted the reply from the slave produces the DMA ac knowledgement C7 that frees the 8080 The freed 8080 negates the memory signals negating DMR PCS5 DMR in turn cancels either DOUT or T DIN whichever is on Finally the trailing edge of RRPLY trig gers an identical reset timer based on shift register E10 Reset time R110 turns off T SYNC T DATA EN and T WTBT if on and it also sets E15 9 at the lower left on PCS5 to turn off SACK Each request triggers the 39 5 one shot in the timeout circuit at the bot tom on PCS6 Completion of a transfer clears it and prevents the clearing from affecting the E15 5 flip flop at the right However should the one shot time out indicating failure of the slave to reply in a reasonable time the flip flop sets to generate FRPLY This signal produces the DMA ACK to the 8080 When DMR subsequently goes off it clears FRPLY but also sets E19 9 triggering the reset time to clear the DMA logic 4 5 FUNCTIONAL FLOWS Figures 4 5 through 4 10 show the system s major operations in terms of functional flow that is
64. e line has been idle the phase lock ed clock that occurs at the fifth consecutive transition a one succeeded by two zeros clears the dropout flag turning on the LED From that point on the data represented by the bottom line in the diagram is made avail able to the USYNRT from the second bit position in the history shift regis ter The USYNRT samples incoming data at the R clock which is repre sented by arrows and occurs at the trailing edge of the phase locked clock The absence of two transitions in a row sets the dropout flag turn ing off the receiver clock The above discussion is sufficient for a basic understanding of what the receiver does and how the incoming data is supplied to the USYNRT But to understand in detail how the logic works readers should turn to the circuit schematic print SL1 and the complete timing diagram TD ISV11A 0 8 which show all associated signals Raw data synchronization is provided by flip flop E8 9 located at B3 on the print The transition de tector at the left is made up of a shift register and three exclusive OR gates When pin 9 of E11 is high each clock shifts the register sampling the raw data at the LSB When pin 9 is low each clock loads it from the data inputs but these are connected so the register still shifts ignoring the raw data Therefore each transition is shifted through the register giving a sequence of signals through the exclusive OR gates E9 11 and E9 6 are transition d
65. e with the host 3 3 CZKCIx AND ISV11 A ROM RESIDENT DIAGNOSTICS CZKCIx is also a task that runs under RSX11 M M 4 in the host When run it starts internal diagnostics on selected devices connected to data way ports It receives and displays information on all but catastrophic er rors With the DPM50 CZKCIx starts a series of ROM resident diagnostics in the ISV11 A These tests also start automatically when the DPM50 is powered up and can be used as a basic standalone confidence check for the DPM50 As stated earlier CZKCIx can start the ISV 11 A microprocessor running a series of diagnostic tests contained in its own ROM As each test is exe cuted its test number is displayed in a set of LEDs mounted on the edge of the M8080 board Refer to Section 3 5 1 to locate and interpret these LEDs The first 9 tests 1 11 octal are regarded as hardcore because they test basic characteristics confined to the ISV11 A An error in any of these 9 tests causes the 8 bit microprocessor to loop within the test thus continuously displaying the number of the first failed test Diagnostics 12 14 octal check softcore characteristics involving the LSI 11 CPU pto cessor and memory Test 13 takes about 11 seconds but 12 and 14 are so fast their numbers may not be noticed in the LEDs Errors in these tests are not allowed to shut down the system However if an error occurs the test number flashes in the LEDs for 10 seconds and the number is upline lo
66. etected and transition delayed These gates are driv en from pins 13 15 and 11 respectively and not 14 of E11 so they gener ate signal trains with on times of two clock periods the latter offset by one period E9 8 which generates the phase locked clock is fed from E11 13 and 11 and thus occupies the second half of the transition de layed on time Binary counters E3 and E1 are configured for a count of 30 17 in E3 plus 13 in E1 Detection of a transition clears E3 and sets an enable disable flip flop E8 5 This allows E3 to count the 2 MHz clock after transition detected goes off but inhibits E1 from doing so When E3 counts to 15 the carry out loads three into E1 and sets the flip flop dis abling E3 and enabling E1 which can then continue the count When E1 reaches 15 total 30 the carry out produces a phase locked clock and clears the flip flop so the next 2 MHz clock clears E3 to restart the count Therefore there is a phase locked clock at each transition and also when there is a count of 30 without a transition E15 is the history shift register Initially the E11 bits are alike so E9 11 is low which causes the 2 MHz clock to shift E11 E9 8 is high so the phase locked clock is low and E9 6 60 SYSTEM LOGIC is also high When the raw data changes the next 2 MHz clock shifts E11 causing pin 15 to be different from the other three outputs In particular pin 15 differs from pin 13 so E9 11 goes high enabling the load
67. feed at the end of a line The entire list is terminated by a carriage return The program then asks Do you wish to save this script A yes causes the question Under what name do you want this script stored The script is stored on the disk under the name given by the operator How ever a default name of ASCRPT is used if the operator responds to the question with a carriage return The monitor then downline loads each diagnostic in the script and exe cutes it As each test is downline loaded its name appears on the oper ator s terminal When the scripted diagnostics have all been run an end message is issued and the operator is prompted to select a new mode 3 4 1 3 Autoscript Mode When this mode is selected the monitor ex ecutes a script of diagnostics previously created in script mode 3 4 2 Local Mode In this mode service personnel can communicate with the host for down line loading and running individual DPM50 diagnostics kept on a disk the host Since they are right there at the remote site they can deal with the equipment on the basis of information provided by the diagnostics Therefore service personnel can alter their troubleshooting strategy dy namically and use the diagnostic in conjunction with other types of test equipment scopes meters After selecting local mode and the controller and terminal dataway port numbers service personnel must go to the remote site and connect if nece
68. for any member of the O subsystem family T 609C To Maximum ambient temperature where a NEMA 12 cabinet is to be installed 9C For the cabinet under consideration 6 feet x 5 feet x 1 foot the surface area is 82 square feet If the cabinet is mounted against a wall or other wise obstructed on one feet x 5 feet side the surface area available for heat dissipation is 52 square feet For any given application the heat produced by the DPM50 sub system is calculated by adding the heat produced by the following things 1 I O modules See detailed module specifications in the O Sub system User Guide and use only the heat dissipation specified as due to field power source 2 The power supply See power supply specifications in O Sub system User Guide 3 The circulating fan 180 Btu hr For some devices the heat specification is only available in watts 1 watt 3 41 Btu hr INSTALLATION 21 10 000 9 000 8 000 Pmax 2x A T T2 Pmax HEAT PRODUCED IN BTU hr 3 000 2 000 1 000 5 10 15 20 25 30 35 40 45 50 55 60 MAXIMUM SITE TEMPERATURE C 6028 Figure 2 2 Cabinet Heat vs Site Temperature Figure 2 2 shows the Pmax 2 X A Ti relationship in graphic form The curves are drawn to show the two most common cabinet instal lations free standing or against a wall When considering a NEMA 12 application for factory floor installation the total he
69. g 9 GND SL1DROPOUTH No signal on dataway TP11 SL1RDATAH Received data to USYNRT TP12 SL1TCLOCKH Transmitter clock from 2 55 556 KHz SL1RCLOCKH Receiver clock to USYNRT gt lt gt lt gt a c xe gp CSCC E cogs wo EA 1E 50000 lt LLJ Ji EpL Ea alo I n E pb 2267 Figure 3 3 M8080 Board 3 5 3 Module Troubleshooting The following procedures are helpful if it becomes necessary to trouble shoot an ISV11 A to one of its two boards Most ISV11 A checks can be performed with the modules installed be cause all test points and LEDs are located at the module edge However when it is necessary to access internal points on the boards use the fol lowing set up procedure MAINTENANCE 43 J1 T1 TRANSMITTER RECEIVER TP13 ay o000000000 NEGATIVE VOLTAGE CONVERTERS c m PROMO PROM1 PROM 2 PROM3 PROM4 SPARE PROM SOCKET Figure 3 4 54 13290 Board 1 Remove the ISV11 A module set 2 Install two double height module extenders or one quad extender 3 Remove the six screws that join the M8080 to the 54 13290 4 Reverse the 54 13290 align its outside edge with the
70. he D C dataway is presented in the DECdataway User s Guide The DPM50 1 0 subsystem is designed to monitor and or control external processes It does this through the use of a variety of digital and analog input output I O modules The LSI 11 directly controls the 1 subsystem and therefore the exter nal process by executing user programs located in its own local memory These programs are initially transferred by the host to the DPM50 as a series of messages over the DECdataway These messages are received by the ISV11 A DECdataway interface and stored in the 51 11 memory This transfer of information from the host to a remote is referred to as downline loading The ISV11 A also can accept data from LSI 11 microcomputer Upon request from the host the ISV11 A formats and transmits this data upline to the host After downline loading a program into a remote DPM50 the host only has to communicate with that task rather than control the external proc ss itself If the DPM50 is gathering data the LSI 11 microcomputer can pre process the raw data before it is upline loaded to the host This division of work among various intelligent components in the system frees the host to communicate with other remotes on the DECdataway Therefore the host maintains fundamental control over the entire system but does so efficiently by delegating most of the work to individual remotes along the DECdataway This arrangement typifies a DIGITAL Dis
71. ided in Table 1 3 INTRODUCTION 15 Table 1 3 ISV11 A Specifications Features Specifications CSR addresses 160140 160142 160144 Interrupts LSI 11 vector locations 300 and 304 Local memory in bytes 5K ROM plus socket and address decoding for another 1K 1K RAM Two consecutive lower wired into connector on DECdataway Port addresses assigned LEDs M8080 four programmable 54 13290 modem dropout Modem dataway interface Operating mode Data format Character size Data rate Transmission technique Transmitter timing Receiver timing Line interface Transmitted signal Receivable signal threshold Error free signal level Common mode isolation Receiver bandpass Half duplex Synchronous serial LSB first 8 bits contains 0 2 stuffing bits 55 556 bits per second Biphase modulation Crystal clock Derived from received signal Transformer coupled 5 V p p into terminated 200 ohm cable 150 mV p p minimum 300 mV p p minimum 350 Vac rms 500 6 KHz to 130 KHz 3 dB points The ISV11 A places one dc and four ac loads on the LSI 11 and has the following maximum current requirements 5 V 3 0 A 12 V 0 37 A 1 6 DOCUMENTATION The following documents are shipped with the DPM50 DPM50 User Guide EK DPM50 UG I O Subsystem User Guide EK OPIOS UG KDF11 AA User s Guide EK KDF11 UG Microcomputer Interfaces Handbook EB 17723 20 Microcomputer Processor Handbook EB 15836 18 LSI 11 23 Program
72. ion 3 7 contains DPM50 troubleshooting flowcharts Service personnel must take a system approach to maintaining a DPM50 with process I O This means distinguishing specific faults in the DPM50 from system wide faults such as problems in the host computer or DEC dataway It also means taking into account the hierarchical nature of the system For example one cannot troubleshoot an LSI 11 bus device from the host if the ISV11 A connecting it to the dataway is not working proper ly On the other hand once system integrity from host to LSI 11 is verified standard LSJ 11 bus diagnostics MAINDECs are run on the LSI 11 for troubleshooting devices and I O modules The host plays no role in such troubleshooting except to download the diagnostics and communicate with the operator Figure 3 1 outlines the hierarchy of software and firmware used for DPMS50 maintenance It shows the functional areas associated with each software firmware routine Figure 3 1 can be used as an index to the par ticular paragraph in this chapter associated with each routine NOTE Discussion of the above mentioned software firmware routines this chapter is brief and of an overview nature In depth procedures for running these routines can be found in the documentation listed in Section 1 6 33 34 MAINTENANCE MASS OTHER MEMORY DEVICES ISB11 A NK DECdataway DZKCH PARAGRAPH 3 2 7 N ISV11 A
73. ird of the 300 mV minimum dataway signal A switch in the 58 SYSTEM LOGIC 36 iii LINE IDLE RAW DATA xr e TRANSITION DETECTED A TRANSITION DLYD N T N PHASE LOCKED CLOCK SSS E a OE R DATA L Figure 4 4 Receiver Timing comparator outputs occurs only when the signal goes above the positive threshold after having been negative or below the negative threshold af ter having been positive Changes in the raw data are synchronized to the clock by a flip flop The logic shown across the lower part of Figure 4 3 contains three main parts a transition detector at the left a phase locked clock generator and a shift register for recording recent transition history in raw data from the receiver circuit This history is necessary for recognizing the start of message and modem dropout It also distinguishes between zeros and ones in the received data it supplies to the USYNRT Figure 4 4 shows the timing of major signals associated with this transition processing log ic A message always starts with several ones followed by at least two zeros for synchronization The timing diagram illustrates signal configuration for a message beginning with 100 followed by several arbitrary bits and then a modem dropout The transition detector generates three signals associ ated with a transition in the raw data Following synchronization of a tran sition
74. is available for the 50 H334 Expander Chassis This chassis is an extender chassis for the D bus and can accommodate up to 10 I O modules A single DPM50 subsystem can accommodate up to seven 7 H334 expan der chassis This gives the DPM50 a total capacity for 77 I O mod ules 10 INTRODUCTION CONNECTOR TO DECdataway OPTIONS 15 INTERFACE LSI 11 BUS KDILH 51 11 ISV11 A CABLE D BUS M7958 151 11 BUS PROCESSOR TEV11 A MSV11 CD MSV11 CD MEMORY MEMORY 151 11 TERMINATOR _ MODULE D BUS EXPANSION __ CONNECTOR 25552 12 n 473 2651 AC ON OFF SLOT 7 NUMBERS 12V ON RuN ENA n H7870 POWER SUPPLY O O ELE FUSE OF HALT Top AC IN CONTROL MASTER CHASSIS A EARLY SHIPMENTS CONNECTOR TO DECdataway DEVICE DEVICE 5 11 CABLE OPTIONS SV11 A INTERFACE INTERFACE D BUS 151 11 BUS KD11 H LSI 11 PROCESSOR MSV11 DD VO TEVILA M MORT MODULES En n 151 11 BUS 77 51 11 TERMINATOR h MODULE i DT D BUS u h EXPANSION E RECEN E 3 2 1 AC ON OFF SLOT oN ON 5 NUMBERS 12V R 58 FUSE OF to POWER CONTROL MASTER CHASSIS NOTE B CURRENT SHIPMENTS A G7272 CONTINUITY MODULE MUST BE INSTALLED IN ANY UNUS
75. k system is not supported 2 4 2 LSI 11 Module Configurations All jumpers and switches on the LSI 11 modules are correctly set at the factory However the configuration should be verified at installation time Location and function of the switches and jumpers on the modules can be found in handbooks supplied with the system The Microcomputer Proces sor Handbook EB 15836 18 supplies this information for the processor and memory modules The Microcomputer Interface Handbook 17723 18 supplies this information for all other LSI 11 bus options 28 INSTALLATION Table 2 1 shows the correct switch and jumper settings for standard mod ules shipped with the DPM50 AA AB CA and CB models Table 2 2 contains the same information for the DPM50 FA FB CA and CB mod els Table 2 1 5 CB LSI 11 Modules Jumper and Switch Settings Module Switches and Jumpers Position W1 W2 W3 W5 W6 W10 8 W11 Out KD11H W4 amp W9 In W7 amp W8 Do not change All Jumpers In MSV11CD 1 SW1 SW2 SW3 SW4 8 SW5 On First 16K SW6 SW7 amp SW8 Off Remaining switches Does not matter W16 Out All other jumpers In MSV11 CD 2 SW1 SW2 SW4 amp SW5 On Second 16K SW3 SW6 SW7 SW8 Off OR MSV11DD W3 amp W2 in Pin W3 Pin 5 7 Pin 10 15 Pin 5 14 SW S5 On Critical factory parameter Switch and jumper settings for additional LSI 11 option modules must be set to integrate the option into the existing sy
76. ke requests on two levels A and B associated respectively with vec tor locations and 304 in the LSI 11 Request inputs to the are held high so making and dropping requests on levels A and B respective ly is under writing control in port 1 bit O and port 2 bit 4 Status of current interrupt requests LSI 11 bus A and B is available to the LSI 11 via CSRO and to the M8080 via ports 1 and 2 SYSTEM LOGIC 63 A request made on either level results in assertion of the BIRQ signal to the LSI 11 Once the LSI 11 responds with DIN and the acknowledgement BIAKI the DCOO3 disables BIRQ and asserts VECTOR This produces a bus reply through the DC004 below and places the vector address on the LSI 11 bus the DCOO5 JAV inputs at the left The signal VEC RQST puts a zero or one on line two depending whether the interrupt is on level A or B 4 4 3 DMA Transfers The upper 32K byte half of the 8080 address space is used for referen cing any 32K byte section of the LSI 11 address space by means of DMA transfers Before initiating any DMA operation with a 28K memory the 8080 must set up AD 15 which is port 2 bit O PCS7 B4 as address bit 15 on the LSI 11 bus This indicates which half of the LSI 11 address space is to be referenced when A15 on the 8080 bus is one Then simply by making a memory reference in the upper half of its own space the 8080 references the selected half of the LSI 11 space using DMA request and control
77. l 77 hex 3F indicates to the 8 bit microprocessor that the ISV11 A is off line disconnected from the DECdataway Although the dataway is half duplex using two addresses allows the ISV11 A to ap pear as a full duplex channel to tasks running on the host and remote pro cessors This is useful because there can be both a read request and a write request outstanding at the same time Which address is used for which transaction is determined by higher level software A technical description of the ISV11 A is presented in Chapter 4 of this user guide 1 3 PHYSICAL DESCRIPTION The principle DPM50 standard components as follows H333 master chassis with H7870 power supply I O control module LSI 11 bus to D bus interface 151 11 KD11 H or LSI 11 23 KDF11 AA processor MOS random access memory minimum 32K word ISV11 A DECdataway Interface 1 3 1 Standard Versions of the DPM50 Currently there are two standard versions of the 50 Each is offered in 115 Vac 230 Vac input power configuration Table 1 1 details the variations Figures 1 4 and 1 5 show the physical arrangement of the components within the H333 master chassis for the two standard versions For more detailed information about the H333 master chassis the I O modules and the IOCM refer to the O Subsystem User Guide 1 3 2 Controls Fuses Indicators The H333 master chassis front panel controls and indicators are on the H78
78. large area along the dataway After the port is selected the monitor starts the ROM resident diagnos tics in the ISV11 A This takes the subsystem off line Failure of the port to come back on line is interpreted by the host as a hardcore error In this case a Field Service Technician must go to the remote site and fix the ISV11 A before that port can be further diagnosed from the host Fot a softcore error the host reports which of the three softcore tests failed In any event if the ISV11 A comes back on line the operator can continue selecting diagnostics to be run In host mode the operator can select operation in single script or au toscript mode 3 4 1 1 Single Diagnostic Mode In single diagnostic mode the oper ator specifies a single diagnostic test to be called in from the disk This test can be executed directly or the operator can elect to patch it If patched the patched version can be saved executed or both 38 MAINTENANCE 3 4 1 2 Script Mode In script mode the operator enters a series of diagnostic file names The task then saves the created script in a special area on the disk as well as executing the complete set When this mode is selected CZKMPx displays the message Enter diagnostics to be scripted The operator responds by listing diagnostic filenames and the number of times each is to be executed consecutively Items in the list filenames and numbers of passes are separated by commas or a line
79. lists the contents of the H7006 A and 7006 B kits Table 2 3 7006 and B Filter Assembly Kits Part No 7423332 00 BC06K 7K H7004 B 7017399 06 H7005 Description Filter mounting panel 40 conductor mirror image cable 40 pin bulkhead filter assembly DLV11 J 20 mA filter cable 8 pin Mate N Lok filter assembly misc mounting hardware Quantity Per Kit H7006 A 7006 1 1 1 0 1 0 0 4 0 4 Only 7423332 00 filter mounting panel can be mounted per H960 cabinet Mount filters from additional kits in the existing mounting panel no more than six if additional filtering is necessary 30 INSTALLATION FILTER H7004 B 40 PIN DLV11 DLV11 F 1 7423332 00 FILTER PANEL Se __ 7006 DLV11 BC06K 7K FILTER DLVII F eres TERMINAL 40 PIN 7423332 00 FILTER PANEL 117006 A q FILTER H7004 B OG MODEM MODEM 40 PIN BC06K 7K ec 4 7423332 00 1 FILTER PANEL J H7006 A 1 NULL BC22A XX TERMINAL CABLE FILTER H700 B 40 PIN TERMINAL TERMINAL M E F TERMINAL BC11U 25 nA 60 RMX IMM pm TOTAL LENGTH BETWEEN MODULE AND TERMINAI OR 15 NOT TO EXCEED 50 FEET NULL MODEM BC22A 10 NULL MODEM 22 10
80. mi croprocessor in the ISV 1 1 A Furthermore since addressing is from differ ent buses and the I O banks occupy different parts of the processors ad dress spaces there are two completely separate address decoders 62 SYSTEM LOGIC The LSI 11 decoder is a standard DC004 PCS4 right that is enabled by matching the ISV11 A CSR jumper address with the address supplied on the B DAL lines Bus control signals to the DC004 come via the trans ceivers on PCS6 as the same signals are also involved in DMA control The sync latches the three least significant address bits which are de coded for selecting the CSRs select signals are backward as high levels are applied to the DAL inputs For output DOUT generates a high or low byte strobe or both depending on DAL O and whether WTBT selects a byte or whole word For input DIN gives an INWD strobe Both the address latch and the data strobe produce a bus reply through the 8641 The LSI 11 supplies the address of the transfer control block TCB via the CSRs on PCS3 The only other data to the ISV11 A is CSRO when a one on DAL O sets the flip flop in the lower right corner on PCS7 to request an 8080 interrupt The gate just above provides a read strobe for CSRO allowing the LSI 11 to read its own interrupt request and other sta tus information via the 74LS367 E7 at the lower left corner on PCS8 For test purposes the ISV11 A can load the CSRs the I O page in LSI 11 address space
81. ming Card EH 17898 20 LSI 11 Programming Card EH 07043 53 MSV11 D E User s Manual EK MSV1D OP ISV11 Field Maintenance Print Set 0609 16 INTRODUCTION MSV11 D Field Maintenance Print Set H333 Field Maintenance Print Set KDF11 A Field Maintenance Print Set KD11 S Field Maintenance Print Set TEV11 Field Maintenance Print Set MP00566 MP00424 MP00734 MP00433 MP00074 The following related documents can be purchased from Digital Equip ment Corporation Information on where to order these documents follows this list DPM50 Diagnostic User Guide DECdataway User s Guide Serial Bus Exerciser Writeup Remote Terminal Tester Writeup Diagnostic Monitor Writeup CVPCADO Process Control Subsystem Writeup DPM DPM PLUS Documentation Set Consists of four manuals DPM DPM PLUS DECdataway Intelligent Subsystem User Guide DPM DPM PLUS Terminal User Guide DPM DPM PLUS System Generation and Management Guide DPM DPM PLUS Release Notes EK DPM00 DM EK ISB11 UG MD 11 CZKCH D MD 11 CZKCI D MD 11 CZKMP D AC A959D MC QJ651 GZ AA J529A TC AA J530A TC AA J531A TC AA J906A TC For additional references refer to Section 1 5 in the O Subsystem User Guide the RSX 11M RSX 11S Documentation Directory AA 2593E TC and the RSX 11M Plus Documentation Directory AA H426A TC These documents can be ordered from the following address Digital Equipment Corporation 444 Whitney Street Northboro Mass 01532 Attn Communic
82. named REX1 Ask the system operator for permission or ask for the tasks to be aborted before closing the channel 4 APPENDICES 75 If a task has been running in the DPM50 LSI 11 microcomputer not only does the connection between the task and the host need to be closed the task within the DPM50 must be terminated It can be ter minated in any of the following ways Cycle the ENABLE HALT switch on the DPM50 H333 master chassis Cycle the ON OFF switch on the DPM50 H333 master chassis Run the CZKCHx serial bus exerciser between th host and the DPM50 in question APPENDIX B SPECIAL CIRCUITS 1 DCOO3 INTERRUPT CONTROL Figures 1 B 2 and B 3 The interrupt control chip is an 18 pin 0 762 cm 0 300 in center DIP device provides circuits to perform an interrupt transaction a com puter system that uses a pass the pulse arbitration scheme The device is used in peripheral interfaces and has two interrupt channels labeled A and B with the A section at a higher priority than the B section Bus sig nals use high impedance input circuits or high drive open collector out puts which allow the device to attach directly to the computer system bus Maximum current required from the Vcc supply is 140 mA 2 DC004 I O ADDRESS DECODER Figures B 4 5 and B 6 The protocol chip is a 20 pin 0 762 cm 0 300 in center DIP device It functions as a register selector providing signals necessary to control da
83. nformation between LSI 11 memory and internal registers in the microprocessor This transfer is under microprocessor control via DMA logic in the interface Therefore data from the host moves over the dataway under micro processor control through the serial line unit internal microprocessor reg isters LSI 11 bus interface and eventually to LSI 11 memory Once data INTRODUCTION 7 DECdataway HOST ISB 11 DPM50 oe ISV11 A SERIAL LINE UNIT 8 DATA LINES 8 BUS 16 ADDR INES ESS LIN PROCESSOR 151 11 BUS LSI 11 BUS INTERFACE USYNRT LSI 11 23 MOS PROCESSOR MEMORY 16 DATA ADDRESS LINES TERMINATOR OPTIONAL OPTIONAL CONTROL INTERFACE INTERFACE MODULE D BUS LSi 11 MA 2263A Figure 1 3 ISV11 A in a DPM50 Subsystem is there the LSI 11 microcomputer can execute the data or operate it Data from the remote makes its way back to the host via the reverse route As stated earlier there are 63 addresses available for ports on the data way address zero is not used Each DPMSO uses a consecutive pair of these addresses The lower address is wired into the dataway port con nector From there it can be read by the ISV11 A microprocessor Since an ISV11 A uses two consecutive addresses the highest address that can be wired into a connector is decimal 62 Reading address 63 in the 8 INTRODUCTION connector octa
84. ninsulated enclosure surface unless special equipment is in stalled to remove excess heat The temperature of air circulating into the 51 11 area must never exceed 60 C Heat produced in a NEMA cabinet can only dissipate through the walls of the enclosure because the cabinets are totally enclosed and lack exter nal ventilation The rate of heat loss through the cabinet walls is a direct function of the temperature difference between inside the cabinet and am bient temperature outside the cabinet Maximum operating temperature 20 INSTALLATION for electronic equipment LSI memory and other modules inside the cabinet is restricted to 609C 1409F Therefore the maximum ambient temperature in which 12 cabinet can be safely operated is also limited by the following considerations 1 Total heat P produced by all electronic equipment inside the cabi net 2 Total cabinet surface area available for heat dissipation Therefore a user considering factory floor installation for the DPM50 in a NEMA 12 cabinet must calculate the temperature limit within which the system can be safely installed For NEMA cabinets DIGITAL has tested the following empirical relation holds true for the DPM50 Pmax 2 X A Ti 2 Where Pmax Heat produced by all the electronics equipment inside the cabinet expressed in Btu hr A Area of cabinet available for heat dissipation T4 Maximum allowable temperature for the electronics
85. number in the LEDs LSB at the top The LEDs also signal failures refer to Section 3 3 During normal operation the 8080 rotates an off light from top to bottom through the LEDs at a rate relative to the frequency at which it returns to its background routines This means that the LEDs cycle slowly when there is a lot of dataway activity to the ISV11 A The cycling speeds up as dataway activity decreases and the LEDs cycle fastest when the system is inactive 3 5 2 Test Points The location and function of the ISV11 A test points are presented in the following discussion This information is useful when troubleshooting the 15 11 Lugs for the test points appear near the LEDs the edge on board view Figure 3 2 On the M8080 the three test points are below the LEDs and are numbered 4 6 from the top down on the 54 13290 they are above the LED and are numbered from the bottom up M8080 Refer to Figure 3 3 Point Signal Meaning TP4 DMR H Internal DMA request TP5 FRPLY H Failed to receive DMA reply TP6 WAIT L Force 8080 wait state 54 13290 Refer to Figure 3 4 Signal including print on which Point it appears Meaning TP 1 PCS2 BUS MEMRL 8080 memory read TP2 SL5 T DATAH USYNRT serial output to modem TP3 12 V through 1K TP4 SL5 USYNRT transmit enable to modem TP5 5 VB through 1K TP6 12 V through 1K TP7 5 TP8 5 VA through 1K 42 MAINTENANCE 54 13290 Cont Point Signal Meanin
86. on 1 4 2 It starts or halts the LSI 11 microcomputer in response to commands from the host 3 It allows bidirectional block transfers of information between the host and 151 11 memory 4 Upon power up or in response to a host command the ISV11 A runs ROM resident diagnostic tests on itself and the LSI 11 CPU proces sor and memory Refer to Chapter 3 Figure 1 3 shows a detailed view of the ISV11 A and its relationship to the host computer and the rest of the DPM50 Through an SB1 1 A controller the host communicates over the dataway with the SV 1 7 A The heart of the ISV 11 A is an eight bit microprocessor This microprocessor executes a microprogram resident in 5K bytes of onboard read only memory ROM It also uses 1K of random access memory RAM for stacks and local storage Figure 1 3 Communication with the host DECdataway is han dled by the microprocessor through a serial line unit based on an LSI syn chronous communications chip It is called a USYNRT Universal Synchro nous Receiver Transmitter The controlling element in the process 1 portion of the equipment is the 51 11 microcomputer Communication between the ISV11 A internal bus and the LSI 11 bus is through an interface in the ISV11 A The micro processor and the LSI 11 can interrupt each other and swap specific in formation through shared 1 registers in the LSI 11 bus interface How ever the principal means of communication is the transfer of i
87. p diagnostics are labeled with test num bers The six flows are in three pairs and all operations shown involve the mi croprocessor The first two drawings illustrate the movement of informa tion in either direction through the serial line unit The next pair shows DMA transfers through the LSI 11 bus interface Figure 4 9 shows the request of an interrupt in the LSI 11 from the ISV11 A and Figure 4 10 illustrates an interrupt request in the opposite direction the only oper ation that employs elements of both interfaces in the ISV11 A There are many other minor operations such as the 8080 reading or writing a port and the LSI 11 making a CSR transfer Components that enter into these simpler operations can easily be identified directly from the circuit sche matics TBMT H INTERRUPT INT 5 H ETC sus INT AcK ETC Bus INT ACK L PRIORITY TEST 6 PCS 2 ENCODER Su 02 0 2 m 3 mm 07 R7 Feo 53 O Q BUS DO 7 H MN BUS O WL PORT SEL L ADDRESS DECODER SEL 8X H BUS A04 5 7 H SL4 A00 03 H SL1 Figure 4 5 Serial Line Out CLOCK COUNTERS x2 9 4 8 MAINT TX ENA DRIVERS sis TRANSMITTER USYNRT CIRCUIT 2 TEST 4 2 SL5 20 DP ENA ADR SEL 0 2 TEST 5 WR TX CLK Si5 TSO T DATA H
88. responding pins for the left and right bytes of its 16 data inputs outputs These connect to the eight data lines of the 8080 bus The 8080 governs the device by supplying control bytes and reading status The USYNRT in turn uses the modem for handling communication over the serial DECdataway Serial data received from the modem at RSI is assem bled into bytes and is available to the processing unit via the eight data lines Transmit bytes supplied over data lines are passed on serially to the modem from TSO The 8080 moves bytes to and from the interface by means of its I O ports Port selection is made by the address decoder at the right on SL4 The number of ports is small and an I O bus control signal is generated either an transfer or memory access in the appropriate address range Therefore decoding a few address bits and signals is suf ficient to select among ports 90 AO BO and the USYNRT registers From port BO the 8080 can learn its own dataway port address wired into the DECdataway connector and available through the gates at the left SEL 8X enables the USYNRT data lines Selection among various registers is made by address bits O 2 applied to the USYNRT address inputs on SL5 Register reading and writing uses separate addresses so is con nected to the USYNRT write input A one enables writing and drives the USYNRT data lines from the 8080 bus through the two 748241s at the lower right When a zero pla
89. s This frees the data lines for transfers during the cycle The status information indicates the kinds of events that occur during the cycle From the latched status bits and 8080 control sig nals WR and DBIN write and data bus 8228 sets up memory coh trol signals and interrupt acknowledgement for the cycle A memory read is for fetching an instruction an operand or an item from the stack writ ing in memory be for an operand or a stack item Bus I O control sig nals in field DI on the print are produced by the 8228 1 outputs How ever they are also asserted by the memory control signals when the address is in the 4000 7FFF range That is in the area of the ISV11 A ad dress space reserved for I O registers The ready input to the 8080 through the 8224 should always be high ex cept when a wait is required for a DMA operation ENA DMA enables the 8093 so that WAIT goes low when the acknowledgement appears READY goes high and the 8080 continues But the DMA signals have no effect when I O WR is true This is done to prevent an unwanted wait from hanging up the 8080 if DMA signals are generated inadvertently because an I O operation looks like a DMA operation to DMA logic When the 8080 does an input or output instruction it puts the one byte address on both the upper and lower half of the address lines Therefore 1 0 port ad dress of 80 or above puts a 1 on line 15 which may generate ENA DMA The 1 WR
90. ssary a portable terminal to the LSI 11 bus At the local terminal service personnel can downline load diagnostics from the host and con trol their execution in the DPM50 using ODT commands 3 4 3 Communications Mode Communications mode is similar to host mode However communication mode provides the operator with more detailed error information at termi nals at the host In host mode the operator receives only pass fail error messages If a diagnostic fails in communication mode any error mes sage normally generated by the diagnostic is upline loaded to the host and displayed on the operator s terminal 3 4 4 161 11 MAINDEC Diagnostics The LSI 11 MAINDEC diagnostics in Table 3 3 are available for use with the CZKMPx diagnostic monitor MAINTENANCE 39 Table 3 3 LSI 11 MAINDEC Diagnostics DPM50 Device Diagnostic Comments KD11 H CVKAACO Basic Instruction test M7246 DVKABAO EIS Instruction test CVKACC1 FIS Instruction test CVKADCO Traps test KDF 11 CJKDACO MEM Management M8 186 CJKDBCO CPU puta 1 location 324 when running host mode KEF11AA CJKDCBO Floating point chip n a CJKDDBO Floating point chip n a MSV 11 CZKMAFO MOS COR 0 124 Exerciser M8044 tests only 28K in host mode DLV11 DVKAEB2 DLV 11 test M7940 DLV 11 J CVDLABO DLV 1 1 J test M8043 DLV 11 F CVDVCBO Off line test M8044 DLV 1 1 E CVDACO Off line test M8017 DZV11 B DVDZAAO Four line ASYNC MUX test part 1 M7957 DVDZBAO Four
91. stem This must be deter mined at the time of installation Directions can be found in the handbooks referenced in the previous paragraph NOTE f a DLV11 J is incorporated into the system its vector address jumpers must be set 340 to avoid conflict with the ISV1 1 A 2 4 3 Serial Line Interface Cable Filter Optional The DPM50 mounted in a properly grounded H960 cabinet is shielded from the EMI RFI radiation commonly found in industrial environments However the EMI RFI radiation may reach the cabinet via the inter connecting cable if the DPM50 LSI 11 microcomputer is interfaced to an external terminal or other serial device Attaching an H7006 filter option where the cable enters the H960 eliminates this INSTALLATION 29 Table 2 2 DPM50 FA LSI 11 Modules Jumper and Switch Module 11 MSV11 DD Settings Switches and Jumpers W1 W2 W3 W4 W5 W6 W8 W15 W16 W18 Pin 1103 Pin 1to 2 Pin 10 to 14 Pin 16 To 15 Critical factory parameter Position in Do not change Out Out In Do not care In In Out In In Out Out In In Two versions of the 7006 filter assembly kit are available to meet the filtering needs of all supported LSI 11 serial line interfaces used in a DPM50 The H7006 A kit is used with the following LSI 11 bus options DLV11 DLV11 E DLV11 F and DZV11 The 7006 is used with the DLV11 J 4 channel asynchronous line interface Table 2 3
92. t disable local memory GR test disable receiver DMA request has been acknowledged by LSI 11 bus 8080 reading LSi 11 address space 8080 writing in LSI 11 address space DMA request generates B DMR for 8080 to access LSI 11 address space Received B DOUT Dataway signal absent Dataway signal dropped out 1 1 2 bit times sans transition or USYNRT receiver status available 8080 addressing LSI 11 space 8X CLK at test socket or can be used for external clock if DIS 8X CLK RAW DATA at test socket or can be used for external data if DIS RAW DATA External test receiver clock for USYNRT External test received data for USYNRT Forced bus reply Generates B HALT Interrupt to 8080 Signal INT QBUS AH INT RQ 4 7 H INWD L I O PAGE L OWL LITE 1 4 L LSI INT REQ H MARGIN 5 V MATCH MEM BUS DO 7 H MEMR H MEMW H MEM SEL L MENB Print PCS4 SL5 PCS4 PCS2 PCS2 PCS2 PCS7 PCS4 PCS4 PCS7 PCS7 SL6 PCS4 SL2 3 PCS5 55 512 PCS4 GLOSSARY 91 Definition LSI 11 bus interrupt control waiting for interrupt on A level or has vector 300 on B DAL lines Interrupt requests to 8080 From B DIN sent by LSI 11 for CSR 8080 addressing 1 register as memory location 8080 IN instruction I O read 8080 OUT instruction I O write Equals I O OR Jumper address inputs to DCOO5s Jumper vector address inpu
93. t the test socket 4 3 1 1 Transmitter Data from the USYNRT enters the transmitter cir cuit at E31 13 C8 ANDed with the T clock The gate keeps the J and K inputs to the E12 5 flip flop high except when the data bit is one and T clock is high Therefore JK is enabled throughout the bit period on a zero and for half the bit period on a one This can be seen in Figure 4 2 which shows the relationship between data flip flop signals and transmitter clocks This means that the flip flop toggles twice during a zero bit but only once during a one The state of the flip flop drives one side or the other of the T1 primary Therefore there are two zero crossings during transmission of a zero on the dataway but only one during a one This is the so called biphase modulation technique of data transmission The circuit D8 senses the 5 V Should the voltage drop slightly 04 conducts and disables T ENA Therefore if the power is failing the trans mitter is disabled even if the USYNRT is sending data which may be in valid SYSTEM LOGIC 57 THRESHOLD COMPARATOR 2 E FILTER V VOLTAGE SYNCHRONIZER REFERENCE RAW DATA H TRANSITION DETECTED LSB IN gt HISTORY Fines IS ger R DATA L REGISTER MA 2287 O R CLOCK L TRANSITION DETECTOR PHASE COUNTER SAMPLE INPUT CLK 2 TTL H Figure 4 3 Receiver Simplified Block Diagram 4 3 1 2 Recei
94. ta flow into and out of up to four word registers eight bytes Bus sig nals can directly attach to the device because receivers and drivers are included on the chip An RC delay circuit is provided to slow the peripher al interface response to data transfer requests The circuit is designed so that if tight tolerance is not required only an external 1K 20 percent re sistor is necessary External RCs can be added to vary the delay Max imum current required from the Vcc supply is 120 mA B 3 0 005 BUS TRANSCEIVER Figures B 7 and B 8 The 4 bit transceiver is a 20 pin 0 762 cm 0 300 in center DIP low pow er Schottky device Its primary use is in peripheral logic In addition to the isolation function the device also provides a comparison circuit for ad dress selection and a constant generator useful for interrupt vector ad dresses The bus 1 0 port has high impedance inputs and high drive 70 mA open collector outputs to allow direct connection to a computer s data bus On the peripheral side a bidirectional port is also provided with standard TTL inputs and 20 mA three state drivers Data on this port is the logical inversion of the data on the bus side Three address jumper inputs are used to compare against three bus in puts and to generate the signal MATCH The MATCH output is open col lector which allows the output of several transceivers to be wired ANDed to form a composite address match signal The address jumpers can
95. ted the USYNRT chip E20 on the 54 13290 or the 8080 pro gram flow is defective MANUAL MODEM TEST This test should be performed if test 6 modem test in the power up diag nostics fails Test 6 is not executed unless the dataway is disconnected Furthermore this manual test should not be performed unless the data way is disconnected to prevent disruption of its ongoing activity The test checks out most of the circuitry interfacing the USYNRT chip to the dataway In particular it verifies the following things 1 The transmitter turns on and off 2 The transmitter transmits ones and zeros 3 The modem analog circuits transmit and receive data 4 The receiver decodes ones and zeros 5 The receiver detects the sync pattern two successive zeros follow ing a one that locks in carrier detected 6 The receiver detects the pattern that drops carrier detected ab sence of any transition for 1 1 1 2 bit times NOTE In either the analog or digital circuitry of the receiver there may be subtle failures which can cause occasional CRC errors or other prob lems However these failures may not be detected by this test or test 6 If such a failure is suspected replace the ISV11 A MAINTENANCE 45 The following tools are required to perform this test Two 6 inch jumpers with alligator clips or miniclips at each end Oscilloscope or logic probe Success or failure is determined by observing the state of the carrier de te
96. terminals because of cabling requirements the DLV11 J can be used only with the DLV 1 1 KA option DZV11 B Asynchronous Multiplexer Interface e RXV21 or RXV11 dual drive floppy disk system requires the REV 1 1 option for local boot capability STATUS INDICATORS 5 v 2v DEV SEL DEVICE SELECT INTER INTERRUPT TIMEOUT Figure 1 7 M7958 O Control Module INTRODUCTION VECTOR SELECT ADDRESS SELECT INITIALIZE SELECT MA 0191 13 The following options are available for the DPM50 Fx and Hx versions Refer to Section 2 4 of this user guide for option selection guidelines DLV11 F or DLV11 J Asynchronous Line Interface and associated terminal s the DLV11 J can be used only with the DLV11 KA op tion DZV11 B Asynchronous Multiplexer Interface RXV21 RXV11 dual drive floppy disk system for local storage only with no local boot capability An additional MSV11 DD 32KW MOS memory module 14 INTRODUCTION 1 4 SOFTWARE The host software is based on the RSX 11M or M Plus real time operating system The LSI 11 microcomputer in each DPM50 subsystem uses the RSX 11S operating system Both have software extensions to allow full use of the Distributed Plant Management system Additional software at the host includes a device driver for the DECdata way and operating software to handle the following functions related to the DPM50 1 Downline System Loa
97. the appropriate DMA memory read or write level and a DMA request that both goes out on the LSI 11 bus and clears flip flop E15 9 at the lower left When the LSI 1 1 sends the DMA grant in E12 5 sets preventing the grant from being passed out to the next device With the grant on negation of both the sync and the reply at the end of the current bus cycle sets E12 9 This generates SACK on the LSI 11 bus to acknowledge that the ISV11 A has become bus master and drops the request following which the LSI 1 1 drops the grant 64 SYSTEM LOGIC The acknowledgement also triggers a timing circuit based on shift register E9 at the upper left on PCS6 SACK sets E19 5 to feed a one into the LSB register and causes the output of the E17 8 AND gate to go low The out put of this gate is fed back to one of its inputs This makes the output oscillate supplying a rising edge clock with a period of 110 ns beginning about half a period after SACK goes true Since the setting of 9 RO clears E19 5 the clock provides timing for the transfer by passing a single one through the shift register This moving one in turn controls the col umn of flip flops shown at the center of the drawing A1 in RO sets T ADDR EN to place the address on the LSI 11 bus and to gate the state of BS7 from port 2 onto the B BS7 line This is to indicate whether the transfer is for memory or the I O bank At the same time a write function turns on T WTBT to specify an output byte Tim
98. ting and controlling a wide range of industrial processes Applications range from simple monitoring functions to controlling complex closed loop sys tems This flexibility is provided by the wide range of digital and analog 1 O modules available 1 modules are available to perform the following functions Input Sensing Outputs Provided DC voltages DC switching AC voltages AC switching Change of state One shot dc switching Contact closure D A conversions A D conversions Pulse trains Event counting Frequency measurement All 1 modules in the DPM50 share a common bus the D bus Figure 1 2 The D bus in the DPM50 master chassis can accommodate up to sev en I O modules It can be extended through the optional H334 expander chassis to add up to 70 I O modules This makes the DPM50 capable of being configured with up to 77 I O modules Connections between I O modules and field wiring of external processes are generally made at screw terminal strips mounted H332 chassis The LSI 11 microcomputer Figure 1 2 provides control over the D bus through the M7958 I O Control Module IOCM This module interfaces the LSI 11 bus to the D bus The accepts command signals from the LSI 11 microcomputer and generates D bus signals for routing data to and from the I O modules Refer to the O Subsystem User Guide for more detailed information about the I O subsystem the IOCM and the I O modules 1 2 2 2 LSI 11 or
99. transmitter clock eight times dataway bit rate Timing signals for DMA High order address bits for DMA Expansion address bits for LSI 11 bus Bank select 7 LSI 11 bus signal to select I O page in LSI 11 address space 87 88 GLOSSARY Signal Print Definition B DAL 0 15 L PCS4 LSI 11 bus data and address lines B DCOK H PCS7 LSI 11 bus dc power okay B DIN L PCS6 LSI 11 bus master requesting input LSI 11 getting vector address in response to interrupt BDMGI L PCS5 LSI 11 bus DMA grant in BDMGO L PCS5 LSI 11 bus DMA grant out BDMRL PCS5 LSI 11 bus DMA request B DOUT L PCS6 LSI 11 bus master has data available for output B HALT L PCS7 LSI 11 bus halt processor BIAKI L PCS4 LSI 11 bus interrupt acknowledge in BIAKO L PCS4 LSI 11 bus interrupt acknowledge out B INIT L PCS4 LSI 11 bus inISV11 A initializes only interrupt control L PCS4 LSI 11 bus interrupt request to LSI 11 BOOT LSI H PCS7 Boots LSI 11 by simulating power up through control of B DCOK BPOK H PCS5 LSI 11 bus ac power okay BRPLY L PCS4 1511 bus reply BS7 H PCS7 Bank select 7 for I O page conditions TBS7 when address placed on LSI 11 bus B SACK L PCS5 LSI 11 bus acknowledges that ISV11 A has been granted master status in DMA operation Signal B SYNC L BUS L BUS A00 15 H BUS D0 7 H BUS D DAL HB L BUS INT ACK L BUS BUS BUS OUT EN L BUS M
100. tributed Plant Man agement system 1 2 2 The DPM50 A detailed functional diagram of the DPM50 is given in Figure 1 2 It shows the functional organization of major components and bus struc tures that make up the DPM50 The DPM50 is divided into the following three main functional areas INTRODUCTION DECdataway ISV11 A DATAWAY TO LSI 11 BUS INTERFACE LSI 11 KD11 H OR 151 11 23 KDF11 AA PROCESSOR lt LSI 11 BUS OPTIONAL INTERFACE IOCM LSI 11 BUS D BUS INTERFACE LSI 11 MEMORY LSI 11 MICROCOMPUTER OPTIONAL INTERFACE TO OPTIONAL EXPANDER CHASIS DBUS _ UP TO 7 I O MODULES SUBSYSTEM FIELD WIRING TO EXTERNAL PROCESS ES MA 5506A Figure 1 2 DPM50 Detailed Functional Diagram The I O Subsystem interfaces directly to an external process through a variety of digital and analog modules The LSI 11 Microcomputer exercises direct local control over the subsystem by executing user programs stored in its memory These programs are initially downline loaded from the host com puter The ISV11 A DECdataway Interface manages DPM50 nication with the host computer over the DECdataway INTRODUCTION 5 The next three sections describe each of the three main functional areas in detail Refer to Figure 1 2 throughout the discussion 1 2 2 1 Subsystem The 1 subsystem is capable of monito
101. ts to 0 0058 Control M8080 LEDs Equals CSR Obit 0 this is LSI 11 request for an 8080 interrupt GR test margin for 5 V for PROMs Address on B DAL equals jumper address DCOO5s LSI 11 addressing ISV 11 A CSRs Data bus for output from local memory Equals BUS MEMR BUS MEMW 8080 accessing local memory Enables match with JA in DCOO5s 9929g GLOSSARY Signal OUT HB H OUT HB L OUT LB H OUT LB L PHASE LOCKED CLK H PORT ADDR 1 6 H R110H RAM SEL L RAW DATAL RBS7L R CLOCK H L RDA H R DATA H L R DCOK L READ 8X L READ CSR L READY H REC H RESET 1H Print PCS3 PCS4 PCS3 PCS4 SL1 SL4 PCS6 SL3 SL1 PCS7 SL1 SL5 SL 1 PCS7 514 PCS7 PCS2 PCS4 PCS2 Definition From OUT HB LSI 11 loading CSR high byte From OUT LB L LSI 11 loading CSR low byte A clock train geared to last signal transition detected on dataway Port address wired into dataway connector Reset time for DMA 8080 accessing the RAM Output of modem receiver circuit Received B BS7 Receiver clock derived from incoming bit stream USYNRT output received data available Modem received data output to USYNRT Received B DCOK 8080 reading 1 register address range 80 87 LSI 11 reading CSR Pulled down by the 8224 ona wait to idle the 8080 15 11 is not now sending information on LSI 11 bus B DAL lines Generated by 822
102. useful What faults or errors have you found in the manual UU U U U U Does this manual satisfy the need you think it was intended to satisfy Does it satisfy your needs Why Please send me the current copy of the Technical Documentation Catalog which contains information on the remainder of DIGITAL s technical documentation Street Company Department WZ Additional copies of this document are available from Digital Equipment Corporation Accessories and Supplies Group Cotton Road Nashua NH 03060 Attention Documentation Products Telephone 1 800 258 1710 Order No EK DPM50 UG 002 SS U U U Do Not Tear Fold and Staple BUSINESS REPLY MAIL FIRST CLASS PERMIT 33 MAYNARD Digital Equipment Corporation Educational Services Development and Publishing 129 Parker Street PK3 1 T12 Maynard MA 01754 No Postage Necessary if Mailed in the United States aps gt Sens ITS 81 bmc DAT Me DNA Y 080 50 gt
103. ver Changes in current flow through the T1 primary are sensed by the receiver circuit shown at top center on SL1 A switch in direction caused either by the serial line secondary or transmitter re verses the state of the raw data outputs shown at the upper right A string of logic components is shown from left to right across the center and in the lower right of the print These logic components process this raw data to detect the start of message derive data bits and a clock to be passed on to the USYNRT and detect a dropout of the received signal The logic is driven by the 2 MHz 92 TTL clock which runs at 36 times the bit rate of the dataway Therefore the clock not only synchronizes the raw data to the ISV 11A but also provides a finer resolution for sampling it Figure 4 3 is a simplified diagram of the receiver with most components in the same relative position as they appear on the print The dual signal generated by the T1 primary from the dataway is applied to a pair of oper ational amplifiers These have gain 1 and high input impedance for iso lation The 56K input resistors prevent a power turn off in the ISV11 A re ceiver from dragging down the dataway The bandpass of the filters at the amplifier outputs eliminates both high and low frequency noise but it atte nuates the signal to about one third For generating raw data the thresh old comparator uses a reference of 50 mV this guarantees the spec of 100 mV one th
104. xtension of the LSI 11 bus The processing unit is comprised of elements of both boards and is shown in the upper left quarter of the figure It includes the 8080 microprocessor its associated clock and gating circuits and local memory Commu nication between microprocessor and local memory is over the 8080 bus This bus runs throughout both boards connecting the processing unit to the other two major parts of the logic The interface between the 8080 bus and the DECdataway is shown in the upper right quarter of the drawing contained entirely on the 54 13290 board This subsystem is based on the USYNRT communications chip and connects to the dataway by a modem The remaining hardware is shown in the lower half of the figure contained on the M8080 board It includes registers decoders and other minor Idgic elements that connect the 8080 bus to LSI 11 bus The LSI 11 bus turn connects to the LSI 11 its memory and peripheral equipment The hardware on each board is shown in a set of circuit schematics code CS Each set has a drawing number in the form X O 1 X is the board des ignation A revised schematic has a revision letter to the right of the drawing number For convenient referencing the individual sheets of each drawing set are labeled For example the labels on the six sheets of 54 13290 0 1 are SL 1 6 and those on the eight sheets of M8080 0 1 Bre PCS1 8 These labels are used as prefixes in signal names to indicate sign
105. ystems Figure 1 1 is a block diagram showing the DPM50 functional organization in a typical DPM system It shows a host computer linked to various re mote subsystems including a DPM50 via a DECdataway Refer to Figure 1 1 throughout the rest of this discussion The DECdataway consists of an ISB11 A interfaced to a PDP 11 and a cable The dataway cable is a twisted shielded pair cable up to 15 000 INTRODUCTION 3 feet 4572 meters long that integrates processes throughout a large in dustrial complex Connectors are placed along the cable creating ports through which messages can pass to or from connected subsystems Communication over the DECdataway is synchronous serial at 55 556 bits per second The host computer maintains control of all communications over the dataway All transactions on the dataway consist of two mes sages first a command from the host to a port and second a response from a port to the host There is one exception the host can broadcast a message to all ports simultaneously with no response allowed from any port Each port connector has address jumpers installed so the host can select which remote to communicate with A port can have more than one address associated with it This is the case with a port connected to a 5 which has two addresses However the number of addresses per DECdataway cannot exceed 63 Therefore one DECdataway can ac commodate 31 DPM50s at most more in depth discussion of t

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