SuperHTM Family E10A-USB Emulator Additional
Contents
1. d Extension setting of the performance result storing counter The 32 bit counter stores the result of performance and two counters can be used as a 64 bit counter To set a 64 bit counter check the Enable check box in the Extend counter group box of the Performance Analysis dialog box for Ch and Ch3 2 Displaying the result of performance The result of performance is displayed in the Performance Analysis window or the PERFORMANCE_ANALYSIS command in hexadecimal 32 bits However when the extension counter is enabled it is displayed in hexadecimal 64 bits Note Ifa performance counter overflows as a result of measurement will be displayed 3 Initializing the measured result To initialize the measured result select Initialize from the popup menu in the Performance Analysis window or specify INIT with the PERFORMANCE_ANALYSIS command 48 RENESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7722 Publication Date Rev 1 00 December 6 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan Renesas Technology Corp Sales Strategic Planning Div Nippon Bldg 2 6 2 Ohte machi Chiyoda ku Tokyo 100 0004 Japan 2CENESAS RE2. 37 RENESAS Note For the command line syntax refer to the online help a Specifying the measurement start end conditions Set the performance measurement conditions in the Action page after conditions have been set in the Event Condition dialog box that is opened by double clicking Ch1 to Ch6 and Ch8 to Ch12 on the Event Condition sheet of the Eventpoint window Notes 1 When no measurement start end conditions are specified measurement is started by executing a program and ended when an event condition is satisfied 2 When only the measurement start or end condition is specified performance cannot be measured Be sure to specify both of the measurement start and end conditions 3 When the measurement start end conditions are specified step operation cannot be performed In addition when execution is restarted from the address where step operation has been stopped by the break conditions of BREAKPOINT or Event Condition step functions are used and operation is disabled Restart execution after the settings of the break conditions of BREAKPOINT or Event Condition have been canceled 4 115 not possible to specify the break conditions and the measurement start end conditions at the same time with one channel If the measurement start end conditions are specified the settings of the break conditions will be disabled 38 RENESAS Table 2 11 Conditions Specified in the Action Page Item PA1 start point Descr
3. RESETA Output 5 32 GND j AJOJN Output 34 GND Input 35 N C ES 36 GND Input to or output from the user system The symbol means that the signal is active low The emulator monitors the GND signal of the user system and detects whether or not the user system is connected When the user system interface cable is connected to this pin and the MPMD pin is set to 0 do not connect to GND but to the MPMD pin directly Connect RESETP and RESETA to the user system if required as shown in figure 1 3 Edge of the board H UDI port connector top view connected to the connector o70 36 00000000 000000000 900000000 3 1 A Pin 1 mark 1 27 M2 6 x 0 45 I4 21 59 37 61 43 51 Pattern inhibited area H UDI port connector top view H UDI port connector front view Figure 1 1 Pin Assignments of the H UDI Port Connector 36 Pins RENESAS Input SH7722 Pin No Signal Output Pin No Note 1 TCK Input 7 2 TRST Input C7 3 TDO Output D8 4 ASEBRK 2 Input D6 TMS Input 09 RESETP Output B9 User reset RESETA Output 5 N C GND E UVCC Output GND 25 GND 3 Output Input to or output from the user system The symbol means that the signal is active low The emulator monitors the GND signal of the u
4. Number of operand cache accesses read number of operand cache accesses write number of operand cache misses read number of operand cache misses write number of operand cache accesses read number of operand cache accesses write System bus occupied rate of request bus The equivalent CPU clock value of the number of requests number of elapsed cycles System bus occupied rate of response bus The equivalent CPU clock value of the number of responses number of elapsed cycles 47 RENESAS Each measurement condition is also counted when conditions in table 2 14 are generated Table 2 14 Performance Measurement Conditions to be Counted Measurement Condition Notes No caching due to the Counted for accessing the cacheable area settings of TLB cacheable bit Cache on counting Accessing the non cacheable area is counted less than the actual number of cycles and counts Accessing the cacheable X Y RAM and U RAM areas is counted more than the actual number of cycles and counts Branch count The counter value is incremented by 2 This means that two cycles are valid for one branch Notes 1 In the non realtime trace mode of the AUD trace and memory output trace normal counting cannot be performed because the generation state of the stall or the execution cycle is changed 2 Since the clock source of the counter is the CPU clock counting also stops when the clock halts in the sleep mode
5. The memory access within the specified range is acquired by a trace The read cycle write cycle or read write cycle can be selected as the bus type ASID value or bus cycle for trace acquisition Setting Method i To open the Event condition 5 or Event condition 6 dialog box double click on the Ch5 OA or Ch6 OA column of the Eventpoint window ii Remove the check mark of the Don t care check box in the Window address page and enter the memory range to be set Event condition 5 Window address ASID Bus State Action Window address Start address H 00000000 End address H 00000000 TET Figure 2 4 Window address Page 26 RENESAS iii Open the ASID page remove the check mark of the Don t care check box and enter the ASID value to be set When the ASID value is not set as a condition do not remove the check mark of the Don t care check box iv Open the Bus state page and specify the bus type and bus cycle that are to be set Event condition 5 Window address ASID Bus State Action Bus state Read Write 6 Read Write Read Write 8 Figure 2 5 Bus State Page v Selecting the Acquire trace check box in the Action page enables acquiring memory access within the range Note To cancel settings select the popup menu that is opened by clicking on the Ch5 OA or Ch6 OA column with the right mous
6. in the Trace type group box of the Trace mode page Set the trace condition to be used Notes 1 Ifan interrupt is generated at the program execution start or end including a step operation the emulator address may be acquired In such a case the following message will be displayed Ignore this address because it is not a user program address EML 2 If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 3 Trace information cannot be acquired for the following branch instructions e The BF and BT instructions whose displacement value is 0 e Branch to H A0000000 by reset 28 RENESAS AUD Trace Function This function is operational when the AUD pin of the device is connected to the emulator It is activated by selecting the AUD trace radio button in the Trace type group box of the Trace mode page Set the trace condition to be used Table 2 9 shows the AUD trace acquisition mode that can be set in each trace function Table 2 9 AUD Trace Acquisition Mode Type Continuous trace occurs Mode Realtime trace Description When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CP
7. Malaysia Tel 603 7955 9390 Fax 603 7955 9510 Colophon 6 0 SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7722 5 Renesas Technology Corp 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan
8. Prefetch address break after executing is satisfied Ch2 Breaks address H 00001058 when the condition Prefetch address break after executing is satisfied Ch4 Breaks address H 0000107a when the condition Prefetch address break after executing is satisfied Ch10 Breaks address H 00001086 when the condition Prefetch address break after executing is satisfied Note Do not set other channels Set the CPU Sequential Extend page as shown in figure 2 1 Then set the program counter and stack pointer PC H 00000800 R15 H 00010000 in the Registers window and click the Go button If this does not execute normally issue a reset and execute the above procedures The program is executed up to the condition of Ch10 and halted Here the condition is satisfied in the order of Ch2 gt 1 gt 4 gt 10 22 RENESAS 1 0 00001058 ali j 0 00001068 p_sam gt sort a 0x00001070 p_sam gt change a 0x00001076 p sam s a 0 0 0000107 _ gt 1 1 1 0 0000107 _ gt 2 2 1 0 00001082 p_sam gt s3 aL3 0 00001086 p 2 lt 4 lt 41 0 0000108 p_sam gt s5 aL5 0 0000108 p_sam gt s6 aL6 1 0 00001092 _ gt 7 7 1 0 00001096 _ gt 8 8 1 0 0000109 p_sam gt s9 aL9 0 0000109 delete sam Figure 2 2 Source Window at Execution Halted Sequential Break 23 RENESAS 2 2 2 Trace Functions The emulator
9. as 1 Waited cycles for WRS The cycles for an issued response response r req that no acceptance signal r gnt is issued to are counted by the System bus clock Even if the waits are issued simultaneously for multiple requests they are counted as 1 46 RENESAS Table 2 13 shows the measurement items and methods that are mainly used Table 2 13 Main Measurement Items Main Measurement Item Elapsed time Measurement Method Number of elapsed cycles x CPU clock cycles Number of execution instructions Number of valid instructions issued number of cases of simultaneous execution of two instructions Number of interrupts accepted Number of exceptions accepted Number of instruction fetches for both cache and non cache Number of memory accesses in an opcode Instruction cache hit ratio Number of instruction cache accesses instruction cache miss counts instruction cache access counts Number of operand accesses for both cache and non cache Number of memory accesses in an operand read number of memory accesses in an operand write Operand cache hit ratio read Number of operand cache accesses read number of operand cache misses read number of operand cache accesses read Operand cache hit ratio write Number of operand cache accesses write number of operand cache misses write number of operand cache accesses write Operand cache hit ratio
10. box 17 RENESAS Table 2 5 Dialog Boxes for Setting Event Conditions cont Function Window Address Data State Address Branch Bus ASID Condition Condition LDTLB Count Condition Dialog Condition Condition Condition Bus Window System Instruction Condition Branch Software Box Address Data ASID Status address Bus Break Count Trace Trace Action Event X X X X X X X X Condition B T 9 dialog and P box Event X X X X X X X Condition B and 10 dialog P box Event X X X X X Condition B and 11 dialog P box Event X X X X X X X X X Condition B T 12 dialog and P box Software X X X X X X X X X trace fixed dialog box Notes 1 Can be set in the dialog box X Cannot be set in the dialog box 2 For the Action item B Setting a break is enabled T Setting a trace is enabled P Setting a performance start or end condition is enabled 18 RENESAS Sequential Setting In the emulator sequential Table 2 6 Sequential Event Conditions Type Event Condition CPU 2 Channel Ch2 gt 1 Sequential Sequential Event Page setting of an Event Condition is enabled Description Halts a program when a condition is satisfied in the order of Event Condition 2 1 An event condition must be set for Ch2 and Ch1 Ch4 gt 3 Halts program when condition is satisfied in the order of Event Condition 4 3 An event condition
11. is enabled a BREAKPOINT is set to a physical address into which address translation is made according to the VP_MAP table However for addresses out of the range of the VP_MAP table the address to which a BREAKPOINT is set depends on the SH7722 MMU status during command input Even when the VP_MAP table is modified after BREAKPOINT setting the address translated when the BREAKPOINT is set valid When the Physical option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address A BREAKPOINT is set after disabling the SH7722 MMU upon program execution After setting the MMU is returned to the original state When a break occurs at the corresponding virtual address the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT When the Virtual option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a virtual address A BREAKPOINT is set after enabling the SH7722 MMU upon program execution After setting the MMU is returned to the original state When an ASID value is specified the BREAKPOINT is set to the virtual address corresponding to the ASID value The emulator sets the BREAKPOINT after rewriting the ASID value to the specified value and returns the ASID value to its original value after setting When no ASID value is specified
12. must be set for Ch4 and Ch3 Ch6 gt 5 Halts a program when a condition is satisfied in the order of Event Condition 6 5 An event condition must be set for Ch6 and Ch5 Ch11 gt 10 Halts a program when a condition is satisfied in the order of Event Condition 11 10 An event condition must be set for Ch11 and Ch10 Many Ch3 gt 2 gt 1 Channel Sequential Halts a program when a condition is satisfied in the order of Event Condition 3 2 1 An event condition must be set for Ch3 Ch2 and gt 3 gt 2 gt 1 Halts program when condition is satisfied in the order of Event Condition 4 3 2 1 An event condition must be set for Ch4 Ch3 Ch2 and Ch1 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 5 4 3 2 1 An event condition must be set for Ch5 Ch4 Ch3 Ch2 and Ch1 Ch6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 6 5 4 3 2 1 An event condition must be set for Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 Ch10 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program when a condition is satisfied in the order of Event Condition 10 6 5 4 3 2 1 An event condition must be set for Ch10 Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 Ch11 gt 10 gt 6 gt 5 gt 4 gt 3 gt 2 gt 1 Halts a program w
13. MFI transfer from the base band side RENESAS 12 Memory Access during Break 13 In the enabled MMU when a memory is accessed and TLB error occurs during break it can be selected whether the TLB exception is controlled or the program jumps to the user exception handler in TLB Mode in the Configuration dialog box When TLB miss exception is enable is selected a Communication Timeout error will occur if the TLB exception handler does not operate correctly When TLB miss exception is disable is selected the program does not jump to the TLB exception handler even if a TLB exception occurs Therefore if the TLB exception handler does not operate correctly a Communication Timeout error will not occur but the memory contents may not be correctly displayed Loading Sessions Information in JTAG clock of the Configuration dialog box cannot be recovered by loading sessions Thus the TCK value will be 1 25 MHz 14 IO Window Display and modification Do not change values of the User Break Controller because it is used by the emulator For each RCLK watchdog timer register there are two registers to be separately used for write and read operations Table 2 3 RCLK Watchdog Timer Register Register Name Usage Register RWTCSR W Write RCLK watchdog timer control status register RWTCNT W Write RCLK watchdog timer counter RWTCSR R Read RCLK watchdog timer control status register RWTCNT R Read RCLK wat
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15. PreHit Channe CPU Match fag CPU Match flag Match flagset gt o PreHit Channel No Select CPU Match flag No Se CH6COA PreHit Channel Select CPU Match flag No Se Ch OCIA PreHit Channel Ch4 1A CPU Match flag Ch110A OA PreHit Channel No Se CPU Match flag 2 Branch PreHit Channel No Se Figure 2 1 CPU Sequential Extend Page a Indicates the channel name for setting conditions b Selects a condition that is satisfied before the channel which sets up conditions When a channel name is selected it is required that the condition of the channel selected here must have already been satisfied When CPU Match flag is selected the CPU match flag must be set When a condition is selected by the channel selected here no break will occur c When a condition is satisfied the CPU match flag is set or cleared When a program breaks the CPU match flag is initialized Set the event condition for each channel in the Event Condition dialog box this also applies to the SystemBus Sequential Extend page 21 RENESAS Usage Example of Sequential Break Extension Setting A tutorial program provided for the product is used as an example For the tutorial program refer to section 6 Tutorial in the SuperH Family EIOA USB Emulator User s Manual The conditions of Event Condition are set as follows 1 5 Chl Breaks address H 00001068 when the condition
16. REJ10J1517 0100 Everywhere you imagine g Nl ESAS SuperH Family E10A USB Emulator Additional Document for User s Manual Supplementary Information on Using the SH7722 Renesas Microcomputer Development Environment System SuperH Family E10A USB for SH7722 HS7722KCUO1HE Rev 1 00 Renesas Technology Revision Date Dec 06 2006 www renesas com Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document 2 Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples 3 You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herei
17. U stops operations until the information is output The user program is not executed in realtime Trace buffer full Trace continue This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed 29 RENESAS To set the AUD trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition mode can be set in the Trace Mode 1 or Trace Mode 2 group box in the Trace Mode page of the Acquisition dialog box Acquisition Trace Mode 2 Internal trace C User Memory trace Trace Mode 1 Realtime trace Non realtime trace Trace Mode 2 Trace continue Trace stop AUD Mode Abit r AUD trace display range Start pointer 0255 End pointer User memory area Trace Extend Mode Trace data with PPC Figure 2 6 Trace Mode Page 30 13 N SAS Notes on AUD Trace 1 When the trace display is performed during user program execution the mnemonics operands or source is not displayed The AUD branch trace function outputs the differences between newly output branch source addresses and previously output branch source addresses The window trace function ou
18. an exception However RTE is counted Exception Number of EA Interrupts are included interruption exceptions accepted Number of interrupts INT NMI is included accepted Number of UBC UBC Performs OR to count the channel hit number of channel hits in the CPU 42 RENESAS Table 2 12 Measurement Items cont Classification Type Measurement Item Option Note CPU Stalled Cycles stalled in full SFM All items are counted performance cycle trace mode with independently cont multi counts Cycles stalled in full SF This item is not counted if the trace mode without stall cycle is generated multi counts simultaneously with a stall cycle that has occurred due to instruction execution TLB TLB Number of UTLB miss UMI The number of TLB miss performance for instruction fetch exceptions generated by an instruction fetch number of EXPEVT sets Number of UTLB miss UMO The number of TLB miss for operand fetch exceptions generated by an operand access number of EXPEVT sets Number of ITLB miss IM The number of ITLB misses for valid accesses does not include UTLB hits or misses Instruction bus Instruction Number of memory MIF The number of memory performance accesses for accesses by an instruction instruction fetch fetch Accesses canceled by an instruction fetch bus are not counted Instruction fetches which have been fetched in anticipation of a branch but not actually executed are counted Accesses
19. are enabled for the RAM area Therefore an operation such as memory write or BREAKPOINT should be set only for the RAM area Cache Operation during User Program Break When cache is enabled the emulator accesses the memory by the following methods e Atmemory write Writes through the cache then issues a single write to outside The LRU is not updated e Atmemory read Reads memory from the cache The LRU is not updated Therefore when memory read or write is performed during user program break the cache state does not change e At breakpoint set Disables the instruction cache Port G The AUD pin is multiplexed as shown in table 2 2 Table 2 2 Multiplexed Functions Port Function 1 Function 2 G PTGA input output port AUDSYNC AUD G PTG3 input output port AUDATAS AUD G PTG2 input output port AUDATA2 AUD G PTG1 input output port AUD G PTGO input output port AUDATAO AUD Note Function 1 can be used when the AUD pins of the device are not connected to the emulator 10 UBC When User is specified in the UBC mode list box in the Configuration dialog box the UBC can be used in the user program Do not use the UBC in the user program as it is used by the emulator when EML is specified in the UBC mode list box in the Configuration dialog box 11 MFI When the MFI boot mode is used be sure to activate the emulator by setting the MFIINT signal as a trigger for the
20. by the PREFI instruction are included Number of instruction The number of accesses for cache access RENESAS an instruction cache during memory access of the opcode 43 Table 2 12 Measurement Items cont Classification Type Measurement Item Option Note Instruction bus Instruction Number of ICM The number of cache misses performance cont instruction cache by an instruction cache cont miss access the number of accesses to the outside of the CPU core due to a cache miss Number of internal XL The number of accesses for RAM access for the XY memory in the instruction fetch XY SH7722 during memory RAM or L memory accesses of the opcode Operand bus Access Number of memory MR The number of memory performance count access for operand accesses by an operand read fetch READ equal to loading on the operand bus Accesses by the PREF instruction or canceled accesses are not included Number of memory MW access for operand fetch WRITE The number of memory accesses by an operand write equal to storing memory on the operand bus Canceled accesses are not included Number of operand CR cache access READ The number of operand cache reads during memory access read of an operand Number of operand CW cache access WRITE The number of operand cache reads during memory access write of an operand The number of accesses to XY memory in the SH7722 Number of inter
21. chdog timer counter The RCLK watchdog timer operates only when the user program is executed Do not change the value of the frequency change register in the 10 window or Memory window The internal I O registers can be accessed from the 10 window However note the following when accessing the SDMR register of the bus state controller Before accessing the SDMR register specify addresses to be accessed in the I O register definition file SH7722 IO and then activate the High performance Embedded Workshop After the I O register definition file is created the MPU s specifications may be changed If each I O register in the I O register definition file differs from addresses described in the hardware manual change the I O register definition file according to the description in the hardware manual The I O register definition file can be customized depending on its format Note that however the EIOA emulator does not support the bit field function RENESAS e Verify In the window the verify function of the input value is disabled 15 Illegal Instructions If illegal instructions are executed by STEP type commands the emulator cannot go to the next program counter 16 Reset CPU and Reset Go in the Debug Menu When Reset Mode of the Configuration dialog box is set as Auto an H UDI reset is issued by executing Reset CPU or Reset Go For the H UDI reset the clock pulse generator and RCLK watchdog timer are not in
22. cts Renesas shall have no liability for damages arising out of such detachment 12 This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas 13 Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries Contents Section 1 Connecting the Emulator with the User 11 Components of the Emulator 1 1 2 Connecting the Emulator with the User 2 1 3 Installing the H UDI Port Connector on the User 3 1 4 Pin Assignments of H UDI Port Connector eese 3 1 5 Recommended Circuit between the H UDI Port Connector and the MPU 6 1 5 1 Recommended Circuit 36 Pin 6 1 5 2 Recommended Circuit 14 Pin 8 Section 2 Software Specifications when Using the SH7722 11 2 1 Differences between SH7722 and the Emulator 11 2 2 Specific Functions for the Emulator when Using the 5 7722 16 2 2 1 Event Condition Functions 16 242 Trace PFulicttonsz eerte de ERI eerte e Rp E ERO e RENE ea E evan 24 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK 34 2 2 4 Notes on Setting Breakpoint Dialog Box se 34 2 2 5 Notes on Setting the Ev
23. e button 27 RENESAS Software Trace Function Note This function can be supported with SHC C compiler manufactured by Renesas Technology Corp including OEM and bundle products V6 0 or later However SHC C compiler including OEM and bundle products V8 0 or later is needed when instructions other than those compatible with SH4 are output When a specific instruction is executed the PC value at execution and the contents of one general register are acquired by trace Describe the Trace x function x is a variable name to be compiled and linked beforehand For details refer to the SuperH gt RISC engine C C Compiler Assembler Optimizing Linkage Editor User s Manual When the load module is downloaded on the emulator and is executed while a software trace function is valid the PC value that has executed the Trace x function the general register value for x and the source lines are displayed To activate the software trace function select the Acquire Software trace radio button in the Software trace dialog box that is opened by double clicking on the software Trace column of the Eventpoint window Note To cancel settings select the Don t care radio button in the Software trace dialog box or select Delete from the popup menu that is opened by clicking on the software Trace column with the right mouse button Internal Trace Function This function is activated by selecting the Internal trace radio button
24. e generated before or after a break For details see table 2 14 c Measurement items Items are measured in the Performance Analysis dialog box for each channel from Chl to Ch4 A maximum of four conditions can be specified at the same time Table 2 12 shows the measurement items Options in table 2 12 are parameters for mode of the PERFORMANCE SET command They are displayed in CONDITION of the Performance Analysis window 41 RENESAS Table 2 12 Measurement Items Classification Type Measurement Item Option Note Disabled None Not measured CPU Cycle Elapsed cycles AC Except for power on period performance counted by the CPU clock Cycles executed in PM The number of privileged privileged mode mode cycles among the number of elapsed cycles Cycles for asserting BL The number of cycles when the SR BL bit the SR BL bit 1 among the number of elapsed cycles Instruction Number of effective The number execution instructions issued instructions number of valid instructions issued number of cases of simultaneous execution of two instructions The number of valid instructions means the number of completed instructions Number of 2 21 The number of times that two instruction executed instructions are executed simultaneously simultaneously among the valid instructions issued Branch Number of BT The number of unconditional unconditional branch branches other than branches occurring after
25. e power supplied to the TRST pin by pulling the pin down by a resistance of 1 kilo ohm and setting PUL15 the PULCR register after a reset The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect the signal lines to other components on the board Since the H UDI and the AUD of the MPU operate with the VccQ supply only the VccQ to the UVCC pin Make the emulator s switch settings so that the user power will be supplied SW2 1 and SW3 1 The resistance values shown in figure 1 3 are for reference For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU For the AUDCK pin guard the pattern between the H UDI port connector and the MPU at GND level RENESAS When the circuit is connected as shown in figure 1 3 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family E10A USB Emulator User s Manual VccQ 3 3 V I O power supply All pulled up at 4 7 kQ or more VccQ VecQ VccQ VccQ H UDI port connector 36 pin type SH7722 x 0 rc e MEC NE AUDSYNC N C N C TCK WE A D D D D D D D D D D 09000292029 TMS GND TRST GND TDI GND TDO ASEBRK GND BRKACK GND UVCC GN RESETP D D D 2 Power on reset signal Reset signal Us
26. e specified number of times Branch trace condition Branch trace Breaks or acquires a trace when a branch occurs with the condition specified by the SH7722 By default trace acquisition is enabled Software trace Selects whether or not the software trace is acquired Action Selects the operation when a condition such as setting a break trace or performance start or end is matched Table 2 5 lists the combinations of conditions that can be set under Ch1 to Ch12 and the software trace 16 RENESAS Table 2 5 Dialog Boxes for Setting Event Conditions Function Bus Window Address Data State Address Branch Bus Bus ASID Condition Condition LDTLB Count Condition Dialog Condition Condition Condition Bus Window System Instruction Condition Branch Software Box Address Data ASID Status address Bus Break Count Trace Trace Action Event X X X X X X X Condition B and 1 dialog P box Event X X X X X Condition B and 2 dialog P box Event X X X X X X X X Condition B and 3 dialog P box Event X X X X X X X X Condition B and 4 dialog P box Event X X X X X X X Condition B T 5 dialog and P box Event X X X X X X X Condition B T 6 dialog and P box Event X X X X X X X X X Break Condition fixed 7 dialog box Event X X X X X X X X Condition B T 8 dialog and P
27. ed herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges 10 Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you 11 In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your produ
28. ent Condition Dialog Box and the BREAKCONDITION SET eene 36 2 2 6 Note on Setting the MODE Command serene 36 2 2 Note on Setting MODE Command eee 36 2 2 8 Performance Measurement Function 37 RENESAS RENESAS Section 1 Connecting the Emulator with the User System 1 1 Components of the Emulator The E10A USB emulator supports the SH7722 Table 1 1 lists the components of the emulator Table 1 1 Components of the Emulator Classi Quan fication Component Appearance tity Remarks Hard Emulator box HS0005KCUO1H ware Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 72 9 g or HS0005KCUO2H Depth 65 0 mm Width 97 0 mm Height 20 0 mm Mass 73 7 g User system interface 1 14 pin type cable Length 20 cm Mass 33 1 g User system interface 1 36 pin type cable gt 4 Length 20 cm Mass 49 2 g only for HS0005KCUO2H USB cable 1 Length 150 cm Mass 50 6 g Soft E10A USB emulator setup 1 HS0005KCUO18SR ware X program lt gt gt SuperH Family E10A HS0005KCUO1HJ USB Emulator User s HS0005KCUO1HE Manual Supplementary HS7722KCUO01HJ Information on Using the HS7722KCU01HE SH7722 and Test program manual for HS0005KCUO1H and HS0005KCUO2H HS0005TMO01HJ and HS0005TMO1HE provided on a CD R Note Additional document for the MPUs supported by the emulator is included Check the tar
29. er system Figure 1 3 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 36 Pin Type Notes 1 Do not use RESETP in the emulator after the user system has been activated When reset signals are used for debugging use RESETA 2 Fix RESETA as high level when it is not used RENESAS 1 5 2 Recommended Circuit 14 Pin Type Figure 1 4 shows a recommended circuit for connection between the H UDI port connector 14 pins and the MPU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used MPMD 0 2 When the emulator is not used MPMD 1 Figure 1 4 shows an example of circuits that allow the MPMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not Reduce the power supplied to the TRST pin by pulling the pin down by a resistance of 1 kilo ohm and setting PUL15 the PULCR register after a reset The pattern between the H UDI port connector and the MPU must be as short as possible Do not connect t
30. et signal is only valid during emulation started with clicking the GO or STEP type button If the reset signal is enabled on the user system in command input wait state it is not sent to the SH7722 Note Do not break the user program when the RESETA signal is being low or the bus release request or wait control signal is being active A TIMEOUT error will occur If the bus release request or wait control signal is fixed to active during break a TIMEOUT error will occur at memory access 5 Direct Memory Access Controller DMAC The DMAC operates even when the emulator is used When a data transfer request is generated the DMAC executes DMA transfer 6 Memory Access during User Program Execution When a memory is accessed from the memory window etc during user program execution the user program is resumed after it has stopped in the emulator to access the memory Therefore realtime emulation cannot be performed The stopping time of the user program is as follows Environment Host computer 800 MHz Pentium JTAG clock 10 MHz TCK clock When a one byte memory is read from the command line window the stopping time will be about 42 ms RENESAS 7 Memory Access during User Program Break The emulator can download the program for the flash memory area for details refer to section 6 22 Download Function to the Flash Memory Area in the SuperH Family E10A USB Emulator User s Manual Other memory write operations
31. get MPU and refer to its additional document RENESAS 1 2 Connecting the Emulator with the User System To connect the 05 emulator hereinafter referred to as the emulator the H UDI port connector must be installed on the user system to connect the user system interface cable When designing the user system refer to the recommended circuit between the H UDI port connector and the MPU In addition read the E1OA USB emulator user s manual and hardware manual for the related device Table 1 2 shows the type number of the emulator the corresponding connector type and the use of AUD function Table 1 2 Type Number AUD Function and Connector Type Type Number Connector AUD Function HS0005KCUO2H 36 pin connector Available HS0005KCUO1H HS0005KCUO2H 14 pin connector Not available The H UDI port connector has the 36 pin and 14 pin types as described below Use them according to the purpose of the usage 1 36 pin type with AUD function The AUD trace function is supported A large amount of trace information can be acquired in realtime The window trace function is also supported for acquiring memory access in the specified range memory access address or memory access data by tracing 2 14 pin type without AUD function The AUD trace function cannot be used because only the H UDI function is supported Since the 14 pin type connector is smaller than the 36 pin type 1 2 5 the area where the connector is installed on t
32. he signal lines to other components on the board Since the H UDI of the MPU operates with the VccQ supply only the VccQ to the UVCC pin Make the emulator s switch settings so that the user power will be supplied SW2 1 and SW3 1 The resistance values shown in figure 1 4 are for reference For the pin processing in cases where the emulator is not used refer to the hardware manual of the related MPU RENESAS When the circuit is connected as shown in figure 1 4 the switches of the emulator are set as SW2 1 and SW3 1 For details refer to section 3 8 Setting the DIP Switches in the SuperH Family E10A USB Emulator User s Manual VccQ 3 3 V I O power supply All pulled up at 4 7 kQ or more VecQ VccQ VccQ H UDI port connector 14 pin type SH7722 RESETP 1 RESETA Power on reset signal Reset signal User system Figure 1 4 Recommended Circuit for Connection between the H UDI Port Connector and MPU when the Emulator is in Use 14 Pin Type Notes 1 Do not use RESETP in the emulator after the user system has been activated When reset signals are used for debugging use RESETA 2 Fix RESETA as high level when it is not used RENESAS RENESAS Section 2 Software Specifications when Using the SH7722 2 1 Differences between the SH7722 and the Emulator 1 When the emulator system is initiated it initializes the general registers and part of the control registers as show
33. he user system can be reduced RENESAS 1 3 Installing the H UDI Port Connector on the User System Table 1 3 shows the recommended H UDI port connectors for the emulator Table 1 3 Recommended H UDI Port Connectors Connector Type Number Manufacturer Specifications 36 pin connector DX10M 36S Hirose Electric Co Ltd Screw type DX10M 36SE Lock pin type DX10G1M 36SE 14 pin connector 2514 6002 Minnesota Mining amp 14 pin straight type Manufacturing Ltd Note When designing the 36 pin connector layout on the user board do not connect any components under the H UDI connector When designing the 14 pin connector layout on the user board do not place any components within 3 mm of the H UDI port connector 1 4 Pin Assignments of the H UDI Port Connector Figures 1 1 and 1 2 show the pin assignments of the 36 pin and 14 pin H UDI port connectors respectively Note Note that the pin number assignments of the H UDI port connector shown on the following pages differ from those of the connector manufacturer RENESAS Input SH7722 Input SH7722 Signal Output No Note Output Pin No Note AUDCK Output A6 19 Input 09 GND 20 AUDATAO Output 21 Input GND 22 AUDATA1 Output 23 Input GND 24 AUDATA2 Output 25 Output GND 26 AUDATA3 Output 27 Input output GND cama 28 GND AUDSYNC 2 Output 29 UVCC Output GND 30 GND N C 31 RESETP 2 Output User reset
34. hed by replacing instructions of the specified address Accordingly it can be set only to the RAM areas in CSO to CS6 and the internal RAM areas A BREAKPOINT cannot be set to the following addresses e ROM areas in CSO to CS6 e Areas other than CSO to CS6 except for the internal RAM slot instruction of a delayed branch instruction An area that can be only read by MMU During step operation BREAKPOINTs are disabled When execution resumes from the address where a BREAKPOINT is specified single step operation is performed at the address before execution resumes Therefore realtime operation cannot be performed When a BREAKPOINT is set to the slot instruction of a delayed branch instruction the PC value becomes an illegal value Accordingly do not seta BREAKPOINT to the slot instruction of a delayed branch instruction Note on DSP repeat loop A BREAKPOINT is equal to a branch instruction In some DSP repeat loops branch instructions cannot be set For these cases do not set BREAKPOINTs Refer to the hardware manual for details When the Normal option is selected in the Memory area group box in the General page of the Configuration dialog box a BREAKPOINT is set to a physical address or a virtual address according to the SH7722 MMU status during command input when the VPMAP_SET RENESAS command setting is disabled The ASID value of the SH7722 PTEH register during command input is used When VPMAP_SET command setting
35. hen a condition is satisfied in the order of Event Condition 11 10 6 5 4 3 2 1 An event condition must be set for Ch11 Ch10 Ch6 Ch5 Ch4 Ch3 Ch2 and Ch1 19 RENESAS Table 2 6 Sequential Event Conditions cont Type Event Condition CPU CPU Extend Description Expands the CPU Sequential Extend page Sequential Event Page cont The sequential setting is enabled with any combination For details refer to section 2 2 1 Sequential Break Extension Setting in this manual SystemBus SystemBus Ch9 gt 8 Sequential Sequential Event Page Event Halts a program when a condition is satisfied for Event Condition 9 8 An event condition must be set for Ch9 and Ch8 Ch8 9 Halts a program when a condition is satisfied for Event Condition 8 9 An event condition must be set for Ch8 and Ch9 SystemBus Extend Expands the SystemBus Sequential Extend page The sequential setting is enabled with any combination For details refer to section 2 2 1 Sequential Break Extension Setting in this manual 20 RENESAS Sequential Break Extension Setting Sequential setting CPU Sequential Event SystemBus Sequential Event CPU Sequential Extend PreHit Channel Ch2 IA OA z CPU Match flag Match flag sett 2 OA DT PreHit Channel No Select v Match flag No Se PreHit Channel No Select X CPU Match flag No Se Chala
36. ion of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above 8 Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology its affiliated companies and their officers directors and employees against any and all damages arising out of such applications 9 You should use the products describ
37. iption Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 1 end point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 1 PA2 pa2 start point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 2 pa2 end point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 2 PAS pa3 start point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 3 pa3 end point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 3 PA4 pa4_start_point Specifies the conditions of Event Condition that has been set as the measurement start condition of performance channel 4 pa4_end_point Specifies the conditions of Event Condition that has been set as the measurement end condition of performance channel 4 RENESAS 39 Event condition 1 Address ASID Bus State Action start point C end point Figure 2 9 Action Page Note or PA2 cannot be set for Ch8 and Ch9 40 13 N SAS b Measurement tolerance e The measured value includes tolerance e Tolerance will b
38. itialized When User is selected and Reset CPU or Reset Go is executed a reset signal input from the user system is waited do not input RESETP RENESAS 2 2 Specific Functions for the Emulator when Using the SH7722 2 2 1 Event Condition Functions The emulator is used to set 12 event conditions Ch1 to Ch12 and the software trace Table 2 4 lists the conditions of Event Condition Table 2 4 Types of Event Conditions Event Condition Type Address bus condition Address Description Breaks when the SH7722 address bus value or the program counter value matches the specified value Data bus condition Data Breaks when the SH7722 data bus value matches the specified value Byte word or longword can be specified as the access data size Bus state condition Bus State There are two bus state condition settings Bus state condition Breaks or acquires a trace when the data bus or the X Bus or Y Bus address bus of the SH7722 is matched Read Write condition Breaks or acquires a trace when the specified read write condition is matched Window address condition Breaks or acquires a trace when the data in the specified memory range is accessed System bus Breaks or acquires a trace when the address or data on the system bus is matched LDTLB instruction event condition Breaks when the SH7722 executes the LDTLB instruction Count Breaks when the conditions set are satisfied th
39. n you should follow the applicable export control laws and regulations and procedures required by such laws and regulations 4 All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com 5 Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document 6 When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products 7 With the except
40. n in table 2 1 The initial values of the actual SH7722 registers are undefined When the emulator is initiated from the workspace a value to be entered is saved in a session Table 2 1 Register Initial Values at Emulator Link Up Register Emulator at Link Up RO to R14 H 00000000 R15 SP H A0000000 RO BANK to R7 BANK H 00000000 PC H A0000000 SR H 700000F0 GBR H 00000000 VBR H 00000000 MACH H 00000000 MACL H 00000000 PR H 00000000 SPC H 00000000 SSR H 000000F0 RS H 00000000 RE H 00000000 MOD H 00000000 H 00000000 AO A1 H 00000000 X1 H 00000000 YO Y1 H 00000000 MO M1 H 00000000 DSR H 00000000 2 The emulator uses the H UDI do not access the H UDI RENESAS 3 Low Power States Sleep Software Standby Module Standby U Standby and R Standby For low power consumption the SH7722 has sleep software standby module standby U standby and R standby states The sleep software standby and module standby states are switched using the SLEEP instruction When the emulator is used the sleep and software standby states can be cleared with either the normal clearing function or with the STOP button and a break will occur The power for some areas is turned off in U standby or R standby state and turned on in using the emulator Note The memory must not be accessed or modified in sleep state 4 Reset Signal The SH7722 res
41. nal XLR RAM access for operand fetch READ XY RAM or L memory RENESAS during memory access read of an operand Accesses via the XY bus and the operand bus are included When MOVX and MOVY are executed simultaneously it increments one count regardless of the read or write Table 2 12 Measurement Items cont Classification Operand bus performance cont Type Access count cont Measurement Option Number of internal XLW RAM access for operand fetch WRITE XY RAM or L memory Note The number of accesses to XY memory in the SH7722 during memory access write of an operand Accesses via the XY bus and the operand bus are included When MOVX and MOVY are executed simultaneously it increments one count regardless of the read or write Number of U RAM UR access READ The number of U memory accesses during memory access read of an operand Accesses via the cache are not included Number of U RAM UW access WRITE The number of U memory accesses during memory access write of an operand Accesses via the cache are not included Access miss count Number of operand CMR cache miss READ The number of cache misses by an operand cache access read number of accesses to the outside of the CPU core due to miss Cache misses are not counted by the PREF instruction Number of operand CMW cache miss WRITE The numbe
42. o button in the Trace type group box of the Trace mode page In this function write the trace data in the specified user memory range Specify the start address to output a trace for the Start edit box in the User memory area group box and the end address for the End Address edit box Set the trace condition to be used Table 2 10 shows the memory output trace acquisition mode that can be set in each trace function Table 2 10 Memory Output Trace Acquisition Mode Type Continuous trace occurs Mode Realtime trace Description When the next branch occurs while the trace information is being output all the information may not be output The user program can be executed in realtime but some trace information will be lost Non realtime trace When the next branch occurs while the trace information is being output the CPU stops operations until the information is output The user program is not executed in realtime Trace buffer full 32 Trace continue This function overwrites the oldest trace information to store the latest trace information Trace stop After the trace buffer becomes full the trace information is no longer acquired The user program is continuously executed RENESAS To set the memory output trace acquisition mode click the Trace window with the right mouse button and select Setting from the pop up menu to display the Acquisition dialog box The AUD trace acquisition m
43. ode can be set in the Trace Mode 1 or Trace Mode 2 group box in the Trace Mode page of the Acquisition dialog box Acquisition Trace Mode Trace type C AUD trace C Internal trace U Mode 1 Realtime trace C Non realtime trace Trace Mode 2 Trace continue Trace stop r AUD Mode Oe r AUD trace display range User memory area Start H 3000 End Address H33 FF Extend Mode Trace data with PPC Figure 2 7 Trace Mode Page 33 RENESAS Notes 1 The memory range for which trace is output is the address on the system bus and not supported for the MMU or cache 2 In the memory range for output do not specify the ranges that the user program has been downloaded or the user program accesses 3 The range for trace output must be 1 MB or less 2 2 3 Notes on Using the JTAG H UDI Clock TCK and AUD Clock AUDCK Set the JTAG clock TCK frequency to lower than the frequency of SH7722 peripheral module clock CKP Set the AUD clock AUDCK frequency to 50 MHz or lower If the frequency is higher than 50 MHz the emulator will not operate normally The set value of the JTAG clock TCK is initialized by executing Reset CPU or Reset Go Thus the TCK value will be 1 25 MHz 2 2 4 Notes on Setting the Breakpoint Dialog Box 1 When an odd address is set the next lowest even address is used 34 A BREAKPOINT is accomplis
44. on instruction 2 2 6 Note on Setting the UBC MODE Command In the Configuration dialog box if User is set while the UBC mode list box has been set Ch10 OA R and Ch11 OA of Event Condition cannot be used 2 2 7 Note on Setting the PPC MODE Command In the Configuration dialog box if User is set while the PPC mode list box has been set 1 and Ch2 of the performance analysis function and options 1 and 2 of the profile function cannot be used 36 RENESAS 2 2 8 Performance Measurement Function The emulator supports the performance measurement function 1 Setting the performance measurement conditions To set the performance measurement conditions use the Performance Analysis dialog box and the PERFORMANCE_SET command When a channel line on the Performance Analysis window is clicked with the right mouse button the popup menu is displayed and the Performance Analysis dialog box is displayed by selecting Setting Performance Analysis Condition Cycle Selection of a count item OPU performance Cycle Count C Instruction Branch C Exception interruption C Stalled Cycle performance C Instruction bus performance Operand bus performance Access count Access miss count Waited cycle System bus performance m Extend counter Enable Figure 2 8 Performance Analysis Dialog
45. r of cache misses by an operand cache access write number of accesses to the outside of the CPU core due to acache miss Write through accesses are not counted Cache misses are not counted by the PREF instruction Number of U RAM read buffer miss UBM RENESAS 45 Table 2 12 Measurement Items cont Classification Type Measurement Item Option Note Operand bus Waited Waited cycles for WOR The number of wait cycles by a performance cycle operand fetch memory access read of an cont READ operand Waited cycles for WOW The number of wait cycles by a operand fetch memory access write of an WRITE operand Waited cycles for WCMR The number of wait cycles by operand cache miss an operand cache miss read READ however the number of wait cycles of cache is included due to contention Waited cycles for WCMW The number of wait cycles by operand cache miss an operand cache miss write WRITE System bus System bus Number of requests RQ The number of valid bus cycles performance cells is counted by the only available system bus clock for Ch3 and Ch4 Number of RS The number of valid bus cycles responses cells is counted by the System bus clock Waited cycles for WRQ The cycles for an issued request request req that no acceptance signal gnt is issued to are counted by the system bus clock Even if the waits are issued simultaneously for multiple requests they are counted
46. ser system and detects whether or not the user system is connected When the user system interface cable is connected to this pin and the MPMD pin is set to 0 do not connect to GND but to the MPMD pin directly Connect RESETP and RESETA to the user system if required as shown in figure 1 4 Pin 1 mark H UDI port connector top view H UDI port connector 23 0 6 x 2 54 15 24 top view Pin 1 mark Unit mm Figure 1 2 Pin Assignments of the H UDI Port Connector 14 Pins RENESAS 1 5 1 5 1 Recommended Circuit between the H UDI Port Connector and the MPU Recommended Circuit 36 Pin Type Figure 1 3 shows a recommended circuit for connection between the H UDI and AUD port connectors 36 pins and the MPU when the emulator is in use Notes 1 Do not connect anything to the N C pins of the H UDI port connector 2 The MPMD pin must be 0 when the emulator is connected and 1 when the emulator is not connected respectively 1 When the emulator is used MPMD 0 2 When the emulator is not used MPMD 1 Figure 1 3 shows an example of circuits that allow the MPMD pin to be GND 0 whenever the emulator is connected by using the user system interface cable When a network resistance is used for pull up it may be affected by a noise Separate TCK from other resistances The TRST pin must be at the low level for a certain period when the power is supplied whether the H UDI is used or not Reduce th
47. supports the trace functions listed in table 2 7 Table 2 7 Trace Functions Memory Output Function Internal Trace AUD Trace Trace Branch trace Supported eight branches Supported Supported Range memory access trace Supported eight events Supported Supported Software trace Supported eight events Supported Supported Table 2 8 shows the type numbers that the AUD function can be used Table 2 8 Type Number and AUD Function Type Number AUD Function HS0005KCUO1H Not supported HS0005KCUO2H Supported 24 RENESAS Branch Trace Functions The branch source and destination addresses their source lines branch types and types of accessed bus masters are displayed Setting Method Select the check box in the Branch group box in the Branch trace page of the Branch trace dialog box that opens by double clicking on the Ch12 Branch column of the Eventpoint window The branch condition to be acquired can be set Branch trace Branch trace Action Branch Dont Acquire subroutine branch instruction trace Acquire exception branch instruction trace Figure 2 3 Branch trace Dialog Box A branch trace can be acquired by selecting the Acquire trace check box of the Action page Note To cancel settings select Delete from the popup menu that is opened by clicking on the Ch12 Branch column with the right mouse button 25 RENESAS Range Memory Access Trace Functions
48. the BREAKPOINT is set to a virtual address corresponding to the ASID value at command input 10 An address physical address to which a BREAKPOINT is set is determined when the 1 BREAKPOINT is set Accordingly even if table is modified after BREAKPOINT setting the BREAKPOINT address remains unchanged When a BREAKPOINT is satisfied with the modified address in the VP_MAP table the cause of termination displayed in the status bar and the Output window is ILLEGAL INSTRUCTION not BREAKPOINT If an address of a BREAKPOINT cannot be correctly set in the ROM or flash memory area mark will be displayed in the BP area of the address on the Source or Disassembly window by refreshing the Memory window etc after Go execution However no break will occur at this address When the program halts with the event condition the mark disappears 35 RENESAS 2 2 5 Notes on Setting the Event Condition Dialog Box and the BREAKCONDITION SET Command 1 When Go to cursor Step In Step Over or Step Out is selected the settings of Event Condition 3 are disabled 2 When an Event Condition is satisfied emulation may stop after two or more instructions have been executed 3 If a PC break address condition is set to the slot instruction after a delayed branch instruction user program execution cannot be terminated before the slot instruction execution execution stops before the branch destinati
49. tputs the differences between newly output addresses and previously output addresses If the previously output address is the same as the upper 16 bits the lower 16 bits are output If it matches the upper 24 bits the lower 8 bits are output If it matches the upper 28 bits the lower 4 bits are output The emulator regenerates the 32 bit address from these differences and displays it in the Trace window If the emulator cannot display the 32 bit address it displays the difference from the previously displayed 32 bit address If the 32 bit address cannot be displayed the source line is not displayed In the emulator when multiple loops are performed to reduce the number of AUD trace displays only the IP counts up In the emulator the maximum number of trace displays is 65534 lines 32767 branches However the maximum number of trace displays differs according to the AUD trace information to be output Therefore the above pointers cannot be always acquired The AUD trace acquisition is not available when User is selected in the UBC mode list box of the Configuration dialog box In this case close the Trace window Do not use the AUD full trace mode for the VIO function If a completion type exception occurs during exception branch acquisition the next address to the address in which an exception occurs is acquired 31 RENESAS Memory Output Trace Function This function is activated by selecting the Use Memory trace radi
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