80c186xl/80c188xl embedded microprocessors specification update
Contents
1. Steppings No Page Status SPECIFICATION CHANGES None for this revision of this specification update Specification Clarifications Steppings No Page Status SPECIFICATION CLARIFICATIONS None for this revision of this specification update Documentation Changes Document No Revision Page Status DOCUMENTATION CHANGES 1 272164 003 18 Doc Changes to PACS Register Definition Figure 2 272164 003 18 Doc State for Interrupt Mask Register Incorrectly Listed 3 272164 003 18 Doc Incorrect Flow Chart Labels 4 272164 003 18 Doc Incorrect AX Register Contents 6 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE IDENTIFICATION INFORMATION Markings 80C186XL and 80C188XL processors may be identified electrically according to device type and stepping Refer to the data sheet for instructions on how to obtain the identifier number A step production devices may be identified as follows The product is marked with a 9 character alphanumeric Intel FPO number underneath the product code number For A step XL devices the ninth character is A For B step XL devices the ninth character is B For C step XL devices the ninth character is C or D Regardless of sample or production status there is a STEPID register which may be examined through software For A step XL devices2. Figure 5 Incorrect INT0 Acknowledge Operation with a Simultaneous INT1 Note This problem occurs only if INT1 is higher priority than INTO If INTO and are configured in cascade mode and the higher priority INT1 occurs between INTO and its expected acknowledge then the acknowledge will appear on INTA1 instead of INTAO Figure 6 INTO INTAO 1 INTI Figure 6 INT0 and INT1 Acknowledge Failure Due to the Higher Priority INT1 Note This problem occurs only if INT1 is higher priority than INTO 272895 002 January 2002 11 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel IMPLICATION If two cascaded interrupt controllers are used the interrupt acknowledge can be sent to the wrong controller This can cause no acknowledge cycle on the INTA1 line after an interrupt on INT1 or on INTAO after an interrupt on INTO In asystem with a single external interrupt controller the errata will cause no acknowledge to be sent on the INTA output Internally the device still functions normally only the state of the output pin is incorrect The Interrupt Request Register and Interrupt Service Register will operate normally The 186 will still run two back to back interrupt acknowledge cycles If the external interrupt controller does not receive the two interrupt acknowledge pulses it will never drive the interrupt type onto the data bus Th
3. the register contains a value of 01H For B step XL devices the register contains a value of 02H For C step XL devices the register contains a value of 03H 272895 002 January 2002 7 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel ERRATA 1 INTx INTAx PROBLEM An internal problem with the Interrupt Control Unit is cascade mode can cause no acknowledge cycle on the INTA1 line after an interrupt on INT1 or on INTA0 after an interrupt on INT0 There are two cases Problem 1 Interrupt 1 is configured in cascaded mode and a higher priority interrupt exists Problem 2 Interrupt 0 is configured in cascaded mode interrupt 1 is higher priority Problem 1 An interrupt acknowledge for INT1 is not generated on INTA1 If two interrupts cascade mode the interrupt acknowledge is generated on INTA0 Condition Another interrupt of higher priority occurs after the decision is made to service Interrupt 1 but before the expected acknowledge cycle on INTA1 Configuration 1 Master Mode 2 INT1 is in Cascade mode and enabled 3 An Interrupt of higher priority than INT1 is enabled DMA Timers INT lines Serial etc Problem 2 An interrupt acknowledge for INTO is not generated on INTAO If two interrupts are in cascade mode the interrupt acknowledge is generated on INTA1 Condition Interrupt 1 configured as higher priority than interrupt 0 occurs after the decision is made
4. to service Interrupt 0 but before the expected acknowledge cycle on INTAO Configuration 1 Master Mode 2 INTO is in Cascade mode and enabled 3 is enabled and higher priority than INTO 8 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE Problem 1 Description Note In the cases below the interrupt controller has already decided to service the INT1 interrupt before the higher priority interrupt occurs Correct operation of the device acknowledges the interrupt on INTA1 after an interrupt on INT1 Normally this occurs even if there is a higher priority interrupt after INT1 but before the acknowledge Figure 1 INTI TMR INT Figure 1 Correct INT1 Acknowledge Sequence with Higher Priority Timer Interrupt Note This interrupt could be any of the following DMA Timers Serial INTO or INT2 The errata occurs when a higher priority interrupt occurs between INT1 and its expected acknowledge The processor completes internal interrupt acknowledge cycles as seen on the status lines but no acknowledge cycle is sent on the INTA1 output Figure 2 INT1 INTA1 INT Figure 2 Incorrect 1 Acknowledge Sequence with Higher Priority Interrupt Note This interrupt could be any of the following DMA Timers Serial INT0 or INT2 272895 002 January 2002 9 041
5. 0L186 EA 80L188 EA 80L186 EB 89L188 EB 272895 002 January 2002 15 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel SPECIFICATION CHANGES None for this revision of this specification update 16 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE SPECIFICATION CLARIFICATIONS None for this revision of this specification update 272895 002 January 2002 170418 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel DOCUMENTATION CHANGES 1 Changes to PACS Register Definition Figure ITEM On page 6 10 of the 80C186XL 80C188XL Microprocessor User s Manual the following corrections should be made to Figure 6 8 PACS Register Definition The register diagram should sequence from U19 through U10 not U19 through U13 In the Bit Mnemonic column U19 13 should be changed to U19 U10 In the Function column U19 13 are compared with A19 13 should be changed to U19 10 are compared with A19 10 Also note that the first active 1k byte boundary of the PCS chip select starts at the first 1k boundary not at OH AFFECTED DOCUMENTS 80C186XL 80C188XL Microprocessor User s Manual order 272164 003 2 Reset State for Interrupt Mask Register Incorrectly Listed ITEM On Page 8 17 of the 80C186XL 80C188XL Microprocessor User s Manual Figure 8 8 titled Interrupt Mask Register incorrectly lists several reset states The reset stat
6. 8 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel If INTO and are configured in cascade mode a higher priority interrupt occurs between INT1 and its expected acknowledge then the acknowledge will appear on INTAO instead Figure 3 INT1 INTA1 INTAO TMR INT 11 Figure 3 INTO And INT1 Acknowledge Failure Due to Higher Priority Timer Interrupt Note This interrupt could be any of the following DMA Timers Serial or INTO Problem 2 Description Note In the cases below the interrupt controller has already decided to service the INTO interrupt before the higher priority INT1 occurs Correct operation acknowledges INTO on INTAO Normally this occurs even if there is a higher priority INT1 after INTO but before the acknowledge Figure 4 INTO INTAO INTI Figure 4 Correct INT0 Acknowledge Operation with a Simultaneous INT1 Note INT1 is the only interrupt that causes the errata to occur 10 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE The errata occurs when INT1 which is higher priority than INT0 occurs between INT0 and its expected acknowledge The processor completes internal interrupt acknowledge cycles as seen on the status lines but no acknowledge cycle is sent on the INTA0 output Figure 5 INTO INTAO INTI
7. INT1 only N A No Yes See Table 1 No N A N A No No N A 272895 002 January 2002 13 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel Hardware Workaround 1 Pull data bus lines 0 to 7 to a known value using pull up resistors to force a defined value on the bus when the errata occurs These resistors will pull the floated bus to 0FFH during the 186 interrupt acknowledge cycle A type 255 interrupt will be read from the bus and executed An interrupt service routine for a type 255 interrupt should be included in the software This solution allows a graceful recovery from the errata condition If the current design uses interrupt type 255 the resistors can be selectively connected to Vcc or Ground to define an unused interrupt type Program cascaded interrupt inputs on the 186 to be level sensitive otherwise the 186 does not recognize that the interrupt is still active Write a simple service routine for the interrupt type defined in step 1 Now that the system has recovered from the errata the original interrupts must be serviced The higher priority interrupt will execute next Finally the interrupt request from the external interrupt controller must be serviced Write a simple service routine for an 8259 interrupt 7 only for cases with two external interrupt controllers In systems with two external interrupt controllers When the errata occurs because of a higher priority internal in
8. dicates the errata specification changes specification clarifications or documentation changes which apply to the 80C186XL 80C188XL product Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted This table uses the following notations Codes Used in Summary Table Stepping x Errata exists in the stepping indicated Specification Change or Clarification that applies to this stepping No mark or Blank box This erratum is fixed in listed stepping or specification change does not apply to listed stepping Page Page Page location of item in this document Status Doc Document change or update will be implemented Fix This erratum is intended to be fixed in a future step of the com ponent Fixed This erratum has been previously fixed NoFix There are no plans to fix this erratum Eval Plans to fix this erratum are under evaluation Row Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document 40418 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE Errata Steppings No Page Status ERRATA A B C D 1 x 8 Fixed INTx INTAx 272895 002 January 2002 5 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel Specification Changes
9. e for INT3 0 should be Fh DMA1 0 should be 3h TMR should be 1h AFFECTED DOCUMENTS 80C186XL 80C188XL Microprocessor User s Manual order 272164 003 3 Incorrect Flow Chart Labels ITEM On page 9 5 of the 80C186XL 80C 188XL Microprocessor User s Manual Figure 9 3 contains incorrect flow chart labels The stem below Conditional statement Counter Compare A should be a YES and the stem to the right should be a NO AFFECTED DOCUMENTS 80C186XL 80C188XL Microprocessor User s Manual order 272164 003 4 Incorrect AX Register Contents ITEM On page 2 16 of the 80C186XL 80C188XL Microprocessor User s Manual the contents of the AX Register in Figure 2 10 Stack Operation should be 12 34 not 10 50 See the top box on the third step of the example top right hand side of figure AFFECTED DOCUMENTS 80C186XL 80C188XL Microprocessor User s Manual order 272164 003 18 of 18 January 2002 272895 002
10. ent It contains all identified errata published prior to this date 07 01 96 001 272895 002 January 2002 1 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel PREFACE As of July 1996 Intel has consolidated available historical device and documentation errata into this new document type called the Specification Update We have endeavored to include all documented errata in the consolidation process however we make no representations or warranties concerning the completeness of the Specification Update This document is an update to the specifications contained in the Affected Documents Related Documents table below This document is a compilation of device and documentation errata specification clarifications and changes It is intended for hardware system manufacturers and software developers of applications operating systems or tools Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents This document may also contain information that was not previously published Affected Documents Related Documents Title Order 80C186XL 80C188XL Microprocessor User s Manual 272164 003 80C186XL 80C188XL 16 Bit High Integration Embedded Processors 272431 003 datasheet Nomenclature Errata are design defects or errors These may cause the published component board system behavior to deviate fr
11. erefore the 186 will read an invalid interrupt type Software Workaround CONDITION WORKAROUND 1 Only INT1 is configured in cascade Use only INTO in cascade mode instead mode and is lower priority than at or make INT1 the highest priority interrupt least one other interrupt or use hardware workaround 2 INT1 and INTO are both in cascade Use only one interrupt in cascade mode mode or use hardware workaround 3 Only INTO is configured in cascade Make INTO higher priority than INT1 or mode and is lower priority than use hardware workaround INT1 12 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE Table 1 Software Workarounds for Problem 1 INT1 Priority Master Cascade INTA1 INTAO Mode Mode 5 Problem Problem Workaround upt Yes INTO and N A Yes Yes Use only one interrupt line in INT1 cascade mode or H W workaround Yes INT1 only Lower Yes No Change to INT0 or make INT1 highest priority Yes INT1 only Higher No No N A Yes INTO only N A No Yes See Table 2 No N A N A No No N A Table 2 Software Workarounds for Problem 2 Master Cascade INTO Priority INTA0 INTA1 Mode Mode vs any INT1 Problem Problem Workaround Yes INTO and N A Yes Yes Use only one interrupt line in INT1 cascade mode or H W workaround Yes INTO only Lower Yes No Make INTO highest priority Yes INTO only Higher No No N A Yes
12. intel 80C186XL 80C188XL EMBEDDED MICROPROCESSORS SPECIFICATION UPDATE Release Date January 2002 Order Number 272895 003 The 80C186XL 80C188XL embedded microprocessors may contain design defects or errors known as errata which may cause the products to deviate from published speci fications Current characterized errata are documented in this specification update Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel retains the right to make changes to specifications and product descriptions at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Third party brands and names are the property of their respective owners Copies of documents which have an ordering number and are referenced in this document o
13. om published specifications Hardware and software designed to be used with any component board and system must consider all errata documented Specification Changes are modifications to the current published specifications These changes will be incorporated in any new release of the specification Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation These clarifications will be incorpo rated in any new release of the specification Documentation Changes include typos errors or omissions from the current published specifications These will be incorporated in any new release of the specification 2 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE NOTE Errata remain in the specification update throughout the product s lifecycle or until a particular stepping is no longer commercially available Under these circumstances errata removed from the specification update are archived and available upon request Specification changes specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation datasheets manuals etc 272895 002 January 2002 3 of 18 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE intel SUMMARY TABLE OF CHANGES The following table in
14. r other Intel literature may be obtained from Intel Corporation P O Box 7641 Mt Prospect IL 60056 7641 or call in North America 1 800 879 4683 Europe 44 0 1793 431 155 France 44 0 1793 421 777 Germany 44 0 1793 421 333 other countries 708 296 9333 Copyright 1997 INTEL CORPORATION ii January 2002 272895 003 intel 80C186XL 80C188XL PROCESSORS SPECIFICATION UPDATE CONTENTS REVISION HISTORY sisticssicasiacccuttonsiransientconoutsanneasuiedusancanvanastadesdancnrannivwante 1 PREFACE sceana onain ananena anana enade iaa maea aada eE nEaN asas 2 SUMMARY TABLE OF CHANGES 4 IDENTIFICATION INFORMATION 7 ERRATA u I AT muu Suma assum 8 SPECIFICATION CHANGES u 16 SPECIFICATION CLARIFICATIONS 17 DOCUMENTATION CHANGES 18 272895 002 January 2002 iii intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE REVISION HISTORY Rev Date Version 01 25 02 003 06 24 97 002 Description Corrected verbiage to clarify there is no D step of the device Changed AX register contents in Stack Operation figure Documentation Change 4 This is the new Specification Update docum
15. terrupt the wrong INTA signal will become active If an 8259 receives an acknowledge and no interrupt is present it assumes a Spurious interrupt occurred and issues an interrupt 7 The service routine for this interrupt must be included in the software Issue non specific End of Interrupt commands in INTO and INT1 service routines only for cases with two external interrupt controllers The situation where the interaction between INTO and INT1 causes the errata is a special case This situation will occur as just described the INTA pulse will be issued to the wrong 8259 In this situation the interrupt input to the wrong 8259 is active when the acknowledge occurs The acknowledged 8259 will drive its interrupt type onto the bus and the CPU will service that interrupt The only difficulty is what happens internally to the 186 The incorrect Interrupt Request and Service Bits have been set To recover from this the interrupt service routine must issue a non specific End of Interrupt command At this point the wrong interrupt has been serviced correctly and because the interrupt inputs are configured to be level sensitive the initial interrupt is now serviced STATUS Fixed on C Stepping Refer to Summary Table of Changes to determine the affected stepping s 14 of 18 January 2002 272895 002 intel 80C186XL AND 80C188XL PROCESSORS SPECIFICATION UPDATE AFFECTED PRODUCTS 80C186 XL 80C188 XL 80C186 EA 80C188 EA 80C186 EB 80C188 EB 8
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