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1. M noels asen We se AUTO TRIG RISING EDGE Fig 4 3 CAENScope oscilloscope tab CAENUpgrader is a software composed of command line tools together with a Java Graphical User Interface for Windows and Linux OS CAENUpgrader allows in few easy steps to upload different firmware versions on CAEN boards to upgrade the NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 37 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 VME digitizers PLL to get board information and to manage the firmware license CAENUpgrader requires the installation of 2 CAEN libraries CAENComm CAENVMELib and Java SE6 or later CAENComm allows CAENUpgrader to access target boards via USB or via CAEN proprietary CONET optical link CAEN Upgrader GUI Upgrade CAEN Front End Hardware CAEN Electronic Instrumentation Bridge Upgrade Available actions Connection Type Config Options o Standard Page Upgrade Firmware USB Backup Page Board Model LINK number J Skip Verify Browse VME Base Address Upgrade Firmware binary file Ready Fig 4 4 CAENUpgrader Graphical User Interface
2. 50 5 44 FLASH ENABLE OXEF2C R W desse tese cese edet sco eL Eee eaaet e Fave nca Yd cueste esee PL 50 5 45 FLASH DATA OXEE30 a ra Qa ER Ee Ee EE SOM 50 5 46 CONFIGURATION RELOAD OXEF34 W 50 6 INSTALLATION c 51 61 POWER ON SEQUENCE uu u Quni QS Qu Abu 51 60 2 POWERON STATUS S uu ua au Sautan nS REA Ee ce ER EE LINER ass 51 0 92 FIRMWARE UPGRADE 5 eve tee Pee UR E E Y n a DEREN 51 6 3 1 VI751 Upgrade files description u n ert tim e er 52 LIST OF FIGURES FIG 1 1 V1751 BLOCK DIAGRAM 9 EG 2 1 MOD V 1 751 FRONT PANEL ier u ee ree repete eoe herede een ie eure epe eue esee bee usos qaa Ds 11 FIG 2 25 MCX CONNECTOR os EET 12 FIG 2 3 AMP DIFFERENTIAL CONNECTOR csscccesscsseeesseecescecsseeceseeesscecsscecsaeeceneesseecsseeceseeesanecsaeesseeseaeeenseeesues 12 FIG 2 4 AMP CLK IN OUT CONNECTOR essere 13 FIG 2 5 PROGRAMMABLE IN OUT CONNECTOR ssceesseeeseeesceessceeeseecececeseecssaeessaeeesaeeesaeeeaeeesaeesa
3. Name Colour Function DTACK green VME read write access to the board CLK_IN green External clock enabled NIM green Standard selection for TRG OUT TRG IN S IN TTL green Standard selection for TRG OUT TRG IN S IN LINK green yellow Network present Data transfer activity LOCK The PLL is locked to the reference clock BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the LOCK LED is turned off RUN green RUN bit set see 6 5 18 TRG green Triggers are accepted DRDY green Event data depending on acquisition mode are present in the Output Buffer BUSY red All the buffers are full OUT LVDS green Signal group OUT direction enabled 2 6 Internal components SW2 4 5 6 Base Addr 31 16 Type 4 rotary switches Function Set the VME base address of the module SW3 CLOCK SOURCE Type Dip Switch Function Select clock source External or Internal SW1 FW Type Dip Switch NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 14 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Function it allows to select whether the Standard STD or the Back up BKP firmware must be loaded at power on default position STD 0000000000000000 0
4. eene enne enne enne nene eenns eines innen 16 TABLE 3 1 BUFFER ORGANIZATION CASE OF 1 835 MSAMPLE CH 21 TABLE 3 2 FRONT PANEL I OS DEFAULT SETTING ccescecesseeeseeceseeceseeeescecesceceseecsaeeceseeceseeceseeceeeseeeseeeeeeeesnes 27 TABLE 5 1 ADDRESS MAP FOR THE MODEL 39 TABLE 5 2 ROM ADDRESS MAP FOR THE MODEL V1751 nennen nennen enne 40 TABLE 5 3 OUTPUT BUFFER MEMORY BLOCK DIVISION CASE OF 1 8MSAMPLES CH MEMORY 43 NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 7 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 1 General description 1 1 Overview The Mod 1751 is a 1 unit wide VME 6U module housing a 8 Channel 10 bit 1 GS s Flash ADC Waveform Digitizer with threshold Auto Trigger capabilities The Mod V1751 can work also as 4 Channel 10 bit 2 GS s Flash ADC Waveform Digitizer Dual Edge Sampling Input dynamics is 1 Vpp single ended or differential The DC offset of the input signal can be adjusted channel per channel by a programmable 16bit DAC on single ended input version The module features a front panel clock reference In Out and a PLL for clock synthesis from internal external references This allows multi board phase synchronizations t
5. 31 29 2 unas 31 39 1 2 0 genes Be pon vs lt b conden Ee E 32 IIL tarde tese te E 32 3 10 DATA TRANSFER CAPABILITIES 7 eritis eed et eo ene na eraot ao cc Rea pe od 33 3 11 EVENTS READOUT 33 S LI A u s u oet be i e eie et e o Sond 33 3 11 1 1 SINGIDED32 u cotta a 33 3 11 1 2 BLOCK TRANSEER D32 D64 2eVME iiie rerit iti P EI TE HERE ERE XE ARE CHE PET 33 3 11 1 3 CHAINED BLOCK TRANSFER 032 064 34 3 11 2 Random readout to be implemented eene enne 34 3 12 d 35 4 SOFTWARE TOOLS nM 36 5 VME INTERFACE Pr 39 Dil REGISTERS ADDRESS etri ciere et pe e E EAE Ee EHE e rea Fe PA RH CEPR FUP ok ape 39 5 2 CONFIGURATION ROM 0 000 0 084 R enne nnne rennen nnne 40
6. A 20 3 2 9 synchronizdtion dne i iter eiie Si QS REI eer 20 33 ACQUISITION MODES 55 a 2500905 eo gat HG DUE FERE TES 20 3 3 1 u u u u S uuu ui uama 20 83 11 Normal mode self calibration ien nri i nce Ee ERE HER ia 20 3 3 1 2 Dual Edge Sampling mode self calibration nete 20 3 3 2 Acquisition ioi e teer eri ctm eres ene i ede da it eb bee ee pans 20 3 3 3 Acquisition Triggering Samples and 0 21 Bedell WERE 22 3 3 4 Eyent iiis i ERIT FERE ERE E ERE ERE 22 NPO Filename Number of pages Page 3 1751 REVI2 DOC 52 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3341 Lu de 23 s MEE uil Pm 24 3 3 4 3 Event format example iecit tester tor EO FE E 24 3 3 5 Temperature monitor and power down eese eee een eene nennen 24 3 35 ADC chips temperature readout u uyu uama Diar rete e Foe eae 24 3 3 5 2 chips over temperature 24 34 TRIGGER MANAGEMENT ieri eee osan n Era Qe de Eine iE e R
7. 5 13 Buffer Organization 0x800C r w Bit Function 8 0 BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the following table NPO 00105 08 V1751x MUTx 12 Filename Number of pages Page 42 V1751_REV12 DOC 52 CAEN Tools for Discovery Document type User s Manual MUT Table 5 3 Output Buffer Memory block division case of 1 8Msamples ch memory Title Revision date Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 CODE Nr of blocks Block size Samples block Block size Samples block 1GS s 1GS s 2GS s 2GS s 0000 1 1 835M 1 835M 3 706M 3 706M 0001 2 0 926M 0 926M 1 835M 1 835M 0010 4 xis T m 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 A write access to this register causes a Software Clear see 8 3 8 This register must not be written while acquisition is running The number of Samples block depends on Custom size register setting see S 5 15 5 14 Buffer Free 0x8010 r w Bit Function 11 0 N Frees the first N Output Buffer Memory Blocks see 5 5 13 5 15 Custom Size 0x8020 r w NPO Bit Function 0 Custom Size disabled 31 0 20 Number of memory locations per event 1 location 7 samples 1GS s 14 samples
8. 1 0000000000000 T i 0 E 5 2 8 sim m oL 1ss3400v3svomm E 5 Exes vL y 278 cir DD Hasa Fig 2 7 Rotary switches location NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 15 CAEN Tools for Discovery Revision date Revision 06 02 2012 12 Document type Title User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 2 7 Technical specifications table Package Analog Input Digital Conversion ADC Sampling Clock generation CLK IN CLK OUT Memory Buffer Trigger Trigger Time Stamp ADC and Memory controller FPGA Optical Link VME interface Upgrade Software Analog Monitor LVDS I O NPO 00105 08 V1751x MUTx 12 Filename 1751 REVI2 DOC 52 16 Table 2 3 Mod V1751 technical specifications 1 unit wide 6U VME64 or 6U VME64X module 8 channels single ended SE or differential 4 channel in DES mode Input range 1Vpp Bandwidth 500MHz Programmable DAC for Offset Adjust x ch SE only Resolution 10 bit Sampling rate 1GS s 2GS s in DUAL EDGE SAMPLING mode simultaneously on each channel multi board synchronization one board can act as clock master External Gate Clock capability NIM TTL for burst or single sampling mode Three operating modes PL
9. eio eae erae AERE Reads 48 5 30 BOARDB INFO OX8140 R I S I yu 48 5 31 MONITOR MODE 0X8 144 R W araa a a RE EE ANEA PE AEE 48 5 32 EVENT SZE 0X8 TAC ER Pe EE Ye ERN AS e EP 48 5 33 VME CONTROL OXEFO00 R W iaia a e tne nennen enne 48 5 34 VMESTATUS OXEF04 49 5 35 BOARD OXEFOS 49 5 36 MCST BASE ADDRESS AND CONTROL OXEFOC 49 5 37 RELOCATION ADDRESS OXEF10 49 5 38 INTERRUPT STATUS ID OXEF14 R W Jise nioan rinasce 49 NPO Filename Number of pages Page 00105 08 1751 12 1751 REVI2 DOC 52 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 5 39 INTERRUPT EVENT NUMBER OXEF18 R W 50 5 40 BLT EVENT NUMBER OXEFIC 1 0 0240 0 50 5 41 SCRATCH OXBE20 R W 50 5 42 SOFTWARE RESET XBE24 W 5 50 5 43 SOFTWARE CLEAR OXEF283 W
10. Tools for Discovery 00105 08 V1751x MUTx 12 Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 TABLE OF CONTENTS T GENERAL DESCRIPTION coal 8 1 1 OVERVIEW erener 8 1 22 BLOCK DIAGRAM unum unanqa 9 2 TECHNICAL SPECIBICA TIONS ssssssscscsscscstcsessssconssstetessdsscssessosvbessivastssoosdstesedsoacensssetecsetsacsessesntesedesedoss 10 2 1 PACKAGING AND COMPLIANCY 10 2 1 1 Supported 10 2 2 POWER REQUIREMENTS riii een ente 10 2 3 REMEMBER 11 2 4 EXTERNAL CONNECTORS cccsssccesssseeeseseecessneeeesssneeecsseeeecssseeeesesseeesseeeesesaeeesssueeesseaeeesseeeeesseseeesenaeees 12 2 4 1 ANALOG INPUT connectors 12 2 4 2 CONTROL connectors a sese ennt 12 2 4 3 ADC REFERENCE CLOCK connectors 13 2 4 4 Digital COnhECtOTS IPTE ERE UE eevee 13 2 4 5 Optical LINK connector eie deett rhe 14 2 5 OTHER FRONT PANEL C
11. DPP Control Software is an application that manages the acquisition in the digitizers which have DPP firmware installed on it The program is made of different parts there is a GUI whose purpose is to set all the parameters for the DPP and for the acquisition the GUI generates a textual configuration file that contains all the parameters This file is read by the Acquisition Engine DPPrunner which is a C console application that programs the digitizer according to the parameters starts the acquisition and manage the data readout The data that can be waveforms time stamps energies or other quantities of interest can be saved to output files or plotted using gnuplot as an external plotting tool exactly like in WaveDump NOTE so far DPP Control Software is developed for Mod x724 and Mod x720 digitizer series DPP PHA Control Software CAEN Electronic Instrumentation M Settings Mode Channel Channel 0 Basic Advanced General Settings Channel Enabled Copy Settings DCOfset 402 ImputDigtaloain Decimation gt IB enuplot graph Energy Histogrem 7000 T T T Pulse Polarity v Trigger and Timing Filter Energy Filter Decay Time Threshold Rise Time Smoothing Factor 4 Flat Top Delay b Holdoff Baseline Mean Trapezoid Gain Peaking Delay RT Discrimination Window Peak Mean B Enabl
12. 1 0 The Output Buffer is not FULL 1 The Output Buffer is FULL 0 0 No Data Ready 1 Event Ready 5 35 Board ID 0xEF08 r w Bit 4 0 VME64X versions this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field see S 3 3 4 Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field see 3 3 4 5 36 MCST Base Address and Control OXEFOC r w Function Bit Function Allows to set up the board for daisy chaining 00 disabled board 9 8 01 last board 10 first board 11 intermediate These bits contain the most significant bits of the MCST CBLT 7 0 address of the module set via VME i e the address used in MCST CBLT operations 5 37 Relocation Address OxEF10 r w Bit Function These bits contains the A31 A16 bits of the address of the module 15 0 it can be set via VME for a relocation of the Base Address of the module 5 38 Interrupt Status ID OxEF14 r w Bit Function 81 0 This register contains the STATUS ID that the module places on the VME data b
13. Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 REGISTER NAME ADDRESS ASIZE DSIZE MODE 5 RES CLR BLT EVENT NUMBER OxEF1C A24 A32 032 X X SCRATCH OxEF20 A24 A32 032 X X SW RESET OxEF24 A24 A32 D32 W SW CLEAR OxEF28 A24 A32 032 FLASH ENABLE OxEF2C A24 A32 D32 FLASH DATA A24 A32 D32 IRW X CONFIGURATION RELOAD OxEF34 A24 A32 D32 W CONFIGURATION ROM 0 000 0 A24 A32 032 R 5 2 Configuration ROM 0xF000 0xF084 r The following registers contain some module s information they are D32 accessible read only manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 5 2 ROM Address Map for the Model V1751 Description Address Content checksum 0 000 4 checksum length2 0 004 0 00 checksum_lengthi 0 008 0 00 checksum lengthO OxFOOC 0x20 constant2 OxF010 0 83 constant1 OxF014 0x84 constant0 OxF018 0x01 c_code OxF01C 0x43 r code OxF020 0 52 OxF024 0x00 oui 0 028 0x40 oui0 OxFO2C OxE6 V1751 VX1751 0x60 V1751B VX1751B 0x61 vers OxF030 17510 VX1751C 0x62 board2 OxF034 V1751 B C 0x00 VX1
14. Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 the waveforms using the external plotting tool gnuplot available on internet for free This program is quite basic and has no graphics but it is an excellent example of C code that demonstrates the use of libraries and methods for an efficient readout and data analysis NOTE WaveDump does not work with digitizers running DPP firmware The users who intend to write the software on their own are suggested to start with this demo and modify it according to their needs For more details please see the WaveDump User Manual and Quick Start Guide Doc nr UM2091 GD2084 Fig 4 2 WaveDump output waveforms CAENScope is a fully graphical program that implements a simple oscilloscope it allows to see the waveforms set the trigger thresholds change the scales of time and amplitude perform simple mathematical operations between the channels save data to file and other operations CAENscope is provided as an executable file the source codes are not distributed NOTE CAENScope does not work with digitizers running DPP firmware and it is not compliant with x742 digitizer family For more details please see the CAENScope Quick Start Guide GD2484 EE RO CAEN Q 5206 Sepe Tools jor Discovery Jens 2 s oe 2 ec o 2
15. 08 1751 12 V1751_REV12 DOC 52 44 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 5 20 Trigger Source Enable Mask 0x810C r w Bit Function 81 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 27 reserved 26 24 Local trigger coincidence level default 0 23 8 reserved 7 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 6 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 4 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 2 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a local trigger as the digitized signal exceeds the Vth threshold see 3 4 3 enables to generate the trigger bit1 enables Ch1 to generate the trigger and so on Bits 26 24 allows to set minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger s
16. 9 2GS s This register must not be written while acquisition is running 5 16 Broadcast ADC Configuration 0x809C w Bit Function 1 Calibration 0 Power Down must always be 0 This register allows to pilot all the relevant ADC signal 5 17 Acquisition Control 0x8100 r w Bit Function 3 0 COUNT ACCEPTED TRIGGERS 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see 3 3 3 2 0 Acquisition STOP 1 Acquisition RUN allows to RUN STOP Acquisition 1 0 00 REGISTER CONTROLLED RUN MODE 01 S IN CONTROLLED RUN MODE 10 reserved 11 MULTI BOARD SYNC MODE Revision Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset see 6 3 8 2 is automatically performed When bit 2 is reset to 0 the stored data are kept available for readout In Stop Mode all triggers are neglected 00105 08 V1751x MUTx 12 Filename 1751 REVI2 DOC Number of pages Page 43 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Bits 1 0 description 00 REGISTER CONTROLLED RUN MODE multiboard synchronization via 5 IN front panel signal RUN control start stop via set clear of bit 2 GATE always active Continuous Gate Mode 01 S IN CONTROLLED RU
17. Bits 1 0 setting see 5 16 Filename Number of pages Page 20 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 CAEN Tools for Discove Document type ry Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 setting the RUN STOP bit bit 2 in the Acquisition Control register bits 1 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE or S IN CONTROLLED RUN MODE driving S IN signal high bits 1 0 of Acquisition Control must be set to 01 Then acquisition is stopped either resetting the RUN STOP bit bit 2 in the Acquisition Control register bits 1 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE or S IN CONTROLLED RUN MODE driving S IN signal low bits 1 0 of Acquisition Control set to 01 3 3 3 Acquisition Triggering Samples and Events When the acquisition is running a trigger signal allows to store the 32 bit counter represents a time reference of the Trigger Time Tag TTT that runs at 1 8 of the sampling clock frequency 1 16 with DES mode actually the capture of the trigger takes place every 2 clock cycles thus the time resolution of the Trigger Time Tag is 2 clock cycles 16 ns This means that the LSB of the TTT is always 0 increment the EVENT COUNTER see 5 27 fil the active buffer with the pre post trigger samples whose number is programmable Acquisition window
18. NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751 REVI2 DOC 52 4 CAEN Tools for Discovery Document type Title Revision date Revision Users Manual MUT V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 5 3 CHANNEL N THRESHOLD 0 1 80 R W 40 5 4 CHANNEL STATUS OX1N88 41 5 5 CHANNEL N AMC FPGA FIRMWARE OXIN8C R a 41 5 6 CHANNEL N BUFFER OCCUPANCY 0 1 94 R a 41 5 1 CHANNEL N DAC 0X1N98 uapa 41 5 8 CHANNEL N ADC CONFIGURATION 9 W 41 5 0 CHANNEL TEMPERATURE MONITOR O0X1NA 42 5 10 CHANNEL CONFIGURATION 0 8000 R W eene enne nennen nennen 42 5 11 CHANNEL CONFIGURATION BIT SET 0 8004 42 5 12 CHANNEL CONFIGURATION BIT CLEAR 0X8008 42 5 13 BUFFER ORGANIZATION OX800C rsen entere nennen 42 5 14 BUFFER FREE 0X98010 teet aside erat AVR E Pa e 43 5 15 CUSTOM SIZE 0X8020 RZW u u u te
19. Output Clock field via CAENupgrader the tool refuses wrong settings for such parameters 3 2 7 Direct Drive programming In Direct Drive BYPASS mode the User can directly set the input frequency Input Clock field real values are allowed Given an input frequency it is possible to set the parameters in order to provide the required signals Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 19 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 2 8 Configuration file Once all parameters are set the tool allows to save the configuration file which includes all the AD9510 device settings see CAENupgrader documentation It is also possible to browse and load into the AD9510 device a pre existing configuration file see CAENupgrader documentation For this purpose it is not necessary the board power cycle 3 2 9 Multiboard synchronization To be implemented 3 3 Acquisition Modes NPO 3 3 1 Channel calibration In order to achieve best performance a self channel calibration procedure should be run after the ADCs have stabilized their operating temperature Whenever the operating temperature changes significantly a new calibration procedure should be performed The calibration is performed through a write access to either Broadcast ADC Configuration or Channel n ADC Configuration reg
20. Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2007 is 0x76120103 5 6 Channel n Buffer Occupancy 0x1n94 r Bit Function 10 0 Occupied buffers 0 1024 5 7 Channel n DAC 0x1n98 r w Bit Function 15 0 DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 0 5V range see also 8 3 1 1 When Channel n Status bit 2 is set to 0 DC offset is updated see 8 5 4 5 8 Channel n ADC Configuration 0x1n9C w Bit Function 1 Calibration Power Down configuration 0 0 Ch Power OK 1 Ch Power Down This register allows to pilot the relevant ADC signal NPO Filename Number of pages Page 00105 08 V 1751x MUTx 12 1751 REVI2 DOC 52 41 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 5 9 Channel n Temperature Monitor 0x1nA8 Revision 12 Bit Function 7 0 Monitored Temperature C These registers allow to monitor the temperature of ADC chips since each ADC houses two channels 0 1 2 3 4 5 6 7 these registers provide identical values in pairs 5 10 Channel Conf
21. all the channels store an event at the same time and in the same way same number of samples and same position with respect to the trigger several trigger sources are available Mother Board Mezzanines Digital Thresholds Local Bus Fig 3 6 Block diagram of Trigger management 3 4 1 External trigger External trigger can be NIM TTL signal on LEMO front panel connector 50 Ohm impedance The external trigger is synchronized with the internal clock see 3 2 if External trigger is not synchronized with the internal clock a one clock period jitter occurs 3 4 2 Software trigger Software trigger are generated via VME bus write access in the relevant register see 5 19 NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 25 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 NPO 3 4 3 Local channel auto trigger Each channel can generate a local trigger as the digitized signal exceeds the Vth threshold ramping up or down depending on Channel Configuration settings see 5 9 The Vth digital threshold the edge type are programmable via VME register accesses see 5 3 N B the local trigger signal does not start directly the event acquisition on the relevant channel such signal is propagated to the central logic which produces the glo
22. channels 0 1 2 3 4 5 6 7 so such registers provide identical temperature values in pairs such values can be readout in the Channel n Temperature Monitor register see 5 5 9 3 3 5 2 ADC chips over temperature protection The V1751 provide an ADC thermal protection feature Each ADC will be automatically powered off whenever the core temperature reaches 90 C The relevant channels will not therefore participate any more to data event and the OverTemp and PowerDown bits of Channel n Status register see 6 5 4 will set to 1 NPO Filename Number of pages Page 00105 08 1751 12 V1751 REVI2 DOC 52 24 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 When the ADC core temperature decreases under 65 the Over temperature flag of Channel n Status register will return to 0 and the relevant channels can be restored to normal operation following these steps Wait until Over temperature flag bit 8 of Channel n Status register returns to 0 Setto 0 Power Down configuration bit 0 of Channel n ADC Configuration see 8 5 8 Power Down flag Bit 7 of Channel n Status register will return to 0 Perform a calibration procedure on the restored channels see 8 3 3 1 Perform a channel synchronization see 8 5 29 3 4 Trigger management All the channels in a board share the same trigger this means that
23. clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel TRG OUT connector NIM or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal 3 5 Front Panel l Os The V1751 is provided with 16 programmable general purpose LVDS I O signals Signals can be programmed via VME see 6 5 23 and 5 24 Default configuration is Table 3 2 Front Panel I Os default setting Nr Direction Description 0 out Ch 0 Trigger Request 1 out Ch 1 Trigger Request 2 out Ch 2 Trigger Request 3 out Ch 3 Trigger Request 4 out Ch 4 Trigger Request 3 out Ch 5 Trigger Request 6 out Ch 6 Trigger Request NPO Filename Number of pages Page 00105 08 V 1751x MUTx 12 1751 REVI2 DOC 52 27 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Nr Direction Description 7 out Ch 7 Trig
24. not possible to readout an event partially see also 3 3 4 3 11 1 1 SINGLE D32 This mode allows to readout a word per time from the header actually 4 words of the first available event followed by all the words until the end of the event then the second event is transferred The exact sequence of the transferred words is shown in 3 3 4 We suggest after the 1 word is transferred to check the Event Size information and then do as many D32 cycles as necessary actually Event Size 1 in order to read completely the event 3 11 1 2 BLOCK TRANSFER D32 D64 2eVME BLT32 allows via a single channel access to read N events in sequence N is set via the BLT Event Number register see 5 40 The event size depends on the Buffer Size Register setting 5 13 namely Event Size 8 Block Size 16 bytes Then it is necessary to perform as many cycles as required in order to readout the programmed number of events We suggest to enable BERR signal during BLT32 cycles in order to end the cycle avoiding filler readout The last BLT32 cycle will not be completed it will be ended by BERR after the N event in memory is transferred see example in the figure below Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 33 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 READOUT BUFFE
25. width 6 5 22 freezing then the buffer for readout purposes while acquisition continues on another buffer Table 3 1 Buffer Organization case of 1 835Msample ch memory REGISTER BUFFER NUMBER SIZE of one BUFFER samples see 5 13 SRAM 1 GS s SRAM 2 GS s 0x00 1 175 3 5M 0x01 2 896k 1 75M 0x02 4 448k 896k 0x03 8 224k 448k 0x04 16 112k 224k 0x05 32 56k 112k 0x06 64 28k 56k 0x07 128 14k 28k 0x08 256 7k 0 09 512 3584 7k Ox0A 1024 1792 3584 NPO An event is therefore composed by the trigger time tag pre and post trigger samples and the event counter Overlap between acquisition windows may occur a new trigger occurs while the board is still storing the samples related to the previous trigger this overlap can be either rejected or accepted programmable via VME If the board is programmed to accept the overlapped triggers as the overlapping trigger arrives the current active buffer is filled up then the samples storage continues on the subsequent one In this case events will not have all the same size see figure below Filename Number of pages Page 21 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 EVENT EVENT n 1 EVENT 2 Reco
26. 000 A24 mode 31 24 23 1615 0 OFFSET 1 i sw4 SWs 3 0 Fig 3 11 A24 addressing 0x00000000 lt gt 0xFFFF0000 A32 mode 31 24 23 1615 0 OFFSET sw2 sw Sws I 53 2 Fig 3 12 A32 addressing The Base Address of the module is selected through four rotary switches see 6 2 6 then it is validated only with either a Power ON cycle or a System Reset see 5 3 8 3 9 1 2 CR CSR address GEO address is picked up from relevant backplane lines and written onto bit 23 19 of CR CSR space indicating the slot number in the crate the recognized Address Modifier for this cycle is 2F This feature is implemented only on versions with 160pin connectors 31 2423 19118 16115 0 GEO OFFSET Fig 3 13 CR CSR addressing 3 9 1 3 Address relocation Relocation Address register see 6 5 37 allows to set via software the board Base Address valid values 0 Such register allows to overwrite the rotary switches settings its setting is enabled via VME Control Register see 5 28 The used addresses are 31 2423 1615 0 OFFSET e A software ADER H ADER L C relocation 31 2423 1615 0 OFFSET lt software ADERL lt relocation Fig 3 14 Software relocation of base address NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52
27. 1 Function Analog input single ended input dynamics 1Vpp 2 500 Mechanical specifications MCX connector CS 85MCX 50 0 16 SUHNER When Dual Edge Sampling mode is used make sure that the EVEN channels are disconnected Absolute max analog input voltage 3Vpp with max 3V or 3V for any DAC offset in single ended configuration CHO GND IN IN Fig 2 3 AMP Differential connector Differential version see options in 1 1 Function Analog input differential input dynamics 1Vpp Zin 100Q Mechanical specifications AMP 3 102203 4 AMP MODUII Absolute max analog input voltage T B D When Dual Edge Sampling mode is used make sure that the EVEN channels are disconnected Absolute max analog input voltage 3Vpp with max 3V or 3V in differential configuration 2 4 2 CONTROL connectors Function TRG OUT Local trigger output NIM TTL on Rt 500 e TRG IN External trigger input NIM TTL Zin 500 e SYNC SAMPLE START Sample front panel input NIM TTL Zin 50Q Filename Number of pages Page 00105 08 1751 12 1751 REVI2 DOC 52 12 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 NPO DAC output 1Vpp on Rt 500 Mechanical specifications 00 type LEMO connectors 2 4 3 ADC REFERENCE CLOCK connectors GND CLK Fig 2 4 A
28. 1 Channel 1 trigger enabled 0 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a TRG_OUT front panel signal as the digitized signal exceeds the Vth threshold see S 3 4 3 enables to generate TRG OUT biti enables Chi to generate the TRG OUT and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the OUT SW TRIGGER ENABLE bit 31 enables the board to generate OUT see 5 19 5 22 Post Trigger Setting 0x8114 r w Bit Function 31 0 Post trigger value The register value sets the number of post trigger samples The number of post trigger samples is Ns NPV NDEL 16 15 This formula becomes 5 2 NDEL 16 15 in DES mode NS number of post trigger samples PostTriggerValue Content of this register NDEL ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA NDEL is 4 with external trigger and 8 with internal trigger 5 23 Front Panel I O Data 0x8118 r w Bit Function 15 0 Front Panel Data Allows to Readout the logic level of LVDS I Os and set the logic level of LVDS Outputs 5 24 Front Panel Control 0x811C r w NPO Bit Function 0 I O Normal operations TRG OUT signals outside trigger presence trigger are generate
29. 10 bit 2 1 GS s Digitizer 06 02 2012 12 2 Technical specifications 2 1 Packaging and Compliancy 2 1 1 Supported VME Crates The module is housed a 6U high 1U wide VME unit The board hosts the VME P1 and P2 connectors and fits into both VME VME64 standard and V430 backplanes VX1751 versions fit VME64X compliant crates 2 2 Power requirements The power requirements of the module are as follows Table 2 1 Model V1751 power requirements 5 V 6 5A 12 V 0 2A 12 V 0 3A NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 10 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 2 3 Front Panel Mod V1751 CLOCK IN INTERNAL CLOCK OUT LOCAL TRIGGER OUT EXTERNAL gt TRIGGER IN SYNC SAMPLE START ANALOG INPUT ANALOG MONITOR OUTPUT DIGITAL I O s 8 CH 10 BIT 1GS s DIGITIZER Fig 2 1 Mod V1751 front panel NPO Filename Number of pages Page 00105 08 1751 12 1751 REVI2 DOC 52 11 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 2 4 External connectors NPO 2 4 1 ANALOG INPUT connectors CHO Fig 2 2 MCX connector Single ended version see options in 8 1
30. 1GHz The required 500 MHz Sampling Clock is obtained by processing CLK INT through Sdiv dividers When an external clock source is used if it has 50MHz frequency then AD9510 programming is not necessary otherwise Ndiv and Rdiv have to be modified in order to achieve PLL lock A REF CLK frequency stability better than 100ppm is mandatory 3 2 3 Trigger Clock TRG CLK signal has a frequency equal to 1 8 of SAMP CLK therefore a 8 samples uncertainty occurs over the acquisition window 16 samples uncertainty with V1751 operated at 2GS s 3 2 4 Output Clock Front panel Clock Output is User programmable Odiv and Odel parameters allows to obtain a signal with the desired frequency and phase shift in order to recover cable line delay and therefore to synchronize daisy chained boards CLK OUT default setting is OFF it is necessary to enable the AD9510 output buffer to enable it 3 2 5 AD9510 programming CAEN has developed a software tool which allows to handle easily the clock parameters the CAENupgrader see www caen it path Products Front End VME Controller VME 3 2 6 PLL programming In PLL mode the User has to enter the divider for input clock frequency input clock PLL mode via CAENupgrader since the VCXO frequency is 1GHz in order to use for example a 50MHz the divider to be entered is 20 Then it is necessary to set the parameters for sampling clock and CLK OUT enable frequency and delay in
31. 32 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 10 Data transfer capabilities The board supports 032 single data readout Block Transfer BLT32 and MBLT64 2eVME and 2eSST cycles Sustained readout rate is up to 60 MB s with MBLT64 up to 100 MB s with 2eVME and up to 160 MB s with 2eSST 3 11 Events readout NPO 3 11 1 Sequential readout The events once written in the SRAMs Memory Event Buffers become available for readout via VME During the memory readout the board can continue to store more events independently from the readout on the free buffers The acquisition process is therefore deadtimeless until the memory becomes full Although the memories are SRAMs VMEBus does not handle directly the addresses but takes them from a FIFO Therefore data are read from the memories sequentially according to the selected Readout Logic from a memory space mapped on 4Kbytes 0x0000 0x0FFC The events are readout sequentially and completely starting from the Header of the first available event followed by the Trigger Time Tag the Event Counter and all the samples of the channels from 0 to 7 Once an event is completed the relevant memory buffer becomes free and ready to be written again old data are lost After the last word in an event the first word Header of the subsequent event is readout It is
32. 751 B C 0x01 board1 OxF038 0 06 boardO OxFO3C OxD7 revis3 OxF040 0x00 revis2 OxF044 0x00 revis1 OxF048 0 00 revisO OxFO4C 0 01 sernum1 OxF080 0 00 sernum0 OxF084 0 16 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration RAM where it is available for readout 5 3 Channel n Threshold 0x1n80 r w Bit Function NPO Filename Number of pages Page 00105 08 1751 12 V1751_REV12 DOC 52 40 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 9 0 Threshold Value for Trigger Generation Each channel can generate a local trigger as the digitized signal exceeds the Vth threshold This register allows to set Vth LSB input range 1 Obit see also 3 4 3 5 4 Channel n Status 0 1 88 Bit Function Over temperature flag 8 0 Ch temperature OK 1 Ch Over temperature Power down flag 7 0 Ch Power OK 1 Ch Power Down Calibrating 6 1 calibration done 0 calibration in progress 5 Buffer free error 1 trying to free a number of buffers too large 3 41 reserved Channel n DAC Channel n DAC ADC bus Busy see 5 5 7 2 1 Busy 0 Ready 1 Memory empty 0 Memory full 5 5 Channel n AMC FPGA Firmware 0x1n8C Bit Function 31 16
33. A is selected via Rotary Switch see 5 2 6 1 RELOC Enabled is selected RELOC register see 5 37 5 0 ALIGN64 Disabled 1 ALIGN64 Enabled see 8 3 11 1 2 0 BERR Not Enabled the module sends a DTACK signal until the CPU inquires the module 4 1 BERR Enabled the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 3 0 Optical Link interrupt disabled 1 Optical Link interrupt enabled 2 0 Interrupt level 0 interrupt disabled Bit 7 this setting is valid only for interrupts broadcasted on VMEbus interrupts broadcasted on optical link feature RORA mode only n RORA mode interrupt request can be removed by accessing VME Control register see S 5 33 and disabling the active interrupt level NPO Filename Number of pages Page 00105 08 V 1751x MUTx 12 1751 REVI2 DOC 52 48 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 n ROAK mode interrupt request is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setting an Interrupt level gt 0 via VME Control register 5 34 VME Status OxEF04 Bit Function 0 BERR FLAG no Bus Error has occurred 2 1 BERR FLAG a Bus Error has occurred this bit is re set after a status register read out
34. L mode internal reference 50 MHz loc oscillator mode external reference IN 100 tolerance PLL Bypass mode Ext 1GHz clock CLK drives directly ADC clocks for 1GS s 2GS s in DUAL EDGE SAMPLING mode AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available using cable adapter DC coupled differential LVDS output clock locked ADC sampling clock Freq 10 500MHz 1 835 and 14 4 MSamples ch sizes available become 3 6 and 28 8 MSamples ch in Dual Edge Sampling mode Multi Event Buffer with independent read and write access Programmable event size and pre post trigger Divisible into 1 1024 buffers Common External TRGIN NIM or TTL and VME Command Individual channel autotrigger time over under threshold TRGOUT NIM or TTL for the trigger propagation to other boards 32bit 4ns 34s range Sync input for Time Stamp alignment One FPGA Altera Cyclone 16 for each ADC 2 channels Data readout and slow control with transfer rate up to 80 MB s to be used instead of VME bus Daisy chainable one A2818 PCI card can control and read eight boards in a chain VME64X compliant D32 BLT32 MBLT64 CBLT32 64 2eVME 2eSST Multi Cast Cycles Transfer rate 60 5 MBLT64 100MB s 2eVME 160MB s 2eSST Sequential and random access to the data of the Multi Event Buffer The Chained readout allows to read one event from all th
35. Levels 1 TRG CLK are TTL I O Levels Bits 5 2 are meaningful for General Purpose I O use only 5 25 Channel Enable Mask 0x8120 r w 1 0 1 0 1 0 Bit Function 7 0 Channel 7 disabled 12 Channel 7 enabled 6 0 Channel 6 disabled 1 Channel 6 enabled 5 0 Channel 5 disabled 12 Channel 5 enabled 0 Channel 4 disabled 1 Channel 4 enabled 3 0 Channel 3 disabled 12 Channel 3 enabled 2 0 Channel 2 disabled 12 Channel 2 enabled 1 0 Channel 1 disabled 1 Channel 1 enabled 0 0 Channel 0 disabled 12 Channel 0 enabled Enabled channels provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running When Dual Edge Sampling mode is used make sure that the EVEN channels are disconnected and disable EVEN channels 0 2 4 6 through this register 5 26 ROC FPGA Firmware Revision 0x8124 r 4 Bit Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 5 27 Event Stored 0 812 r Bit Function 81 0 This register contains the number of events currently stored in the Output Buffer This register value cannot exceed the maximum number of available buffers accord
36. MP CLK IN OUT Connector Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL LVPECL CML Zdiff 1009 Mechanical specifications AMP 3 102203 4 connector Function CLOCK OUT Clock output DC coupled diff LVDS Zdiff 1000 Mechanical specifications AMP 3 102203 4 connector 2 4 4 Digital connectors Fig 2 5 Programmable IN OUT Connector Function N 16 programmable differential LVDS I O signals Zdiff_in 1000 Four Independent signal group 0 3 4 7 8 11 12 15 In Out direction control see also 3 5 Mechanical specifications 3M 7634 5002 34 pin Header Connector Filename Number of pages Page 00105 08 V 175 1x MUTx 12 V1751_REV12 DOC 52 13 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 2 4 5 Optical LINK connector LINK IO TX red wrap RX black wrap Fig 2 6 LC Optical Connector Mechanical specifications Revision 12 LC type connector to be used with Multimode 62 5 125um cable with LC connectors on both sides Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s daisy chainable 2 5 Other front panel components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs
37. N MODE Multiboard synchronization via S IN front panel signal S IN works both as SYNC and START command GATE always active Continuous Gate Mode 11 MULTI CBOARD SYNC MODE A Used only for Multiboard synchronization 5 18 Acquisition Status 0x8104 r Bit Function Board ready for acquisition PLL and ADCs are synchronized correctly 0 not ready 1 read 8 J This bit should be checked after software reset to ensure that the board will enter immediately run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur PLL Status Flag see 2 5 1 0 PLL loss of lock 1 no loss of lock NOTE This bit acts as a flag indicating that a PLL unlock condition has occurred from the last register read This bit is internally restored to 1 after a read access to Status Register see 5 34 PLL Bypass mode see 2 5 1 6 0 No bypass mode 1 Bypass mode Clock source see 2 6 5 0 Internal 7 1 External 4 EVENT FULL itis setto 1 as the maximum nr of events to be read is reached 9 EVENT READY it is set to 1 as at least one event is available to readout 0 RUN off 1 RUNon 1 0 reserved 5 19 Software Trigger 0x8108 w Bit Function 31 0 A write access to this location generates a trigger via software NPO Filename Number of pages Page 00105
38. OMPONENTS 14 2 5 1 ID m EE 14 226 INTERNAT COMPONENTS 25 Tree E DER uo 14 2 7 TECHNICAL SPECIFICATIONS TABLE eeeeeeeeeeene eene enne enne nennen ennt 16 3 FUNCTIONAL DESCRIPTION wicsssisosssssicssessscestesssessncssenccsescisessesseosssncsssscnssscesesossvacsvescasensassonasenss escsssses 17 34 JAXNAEOGINPUT ec eiie lech vete sqa has sade eats slate pene 17 3 1 1 Sirigle ended Ap usa aun uka er aO EUN ERE Fecha Pre Ur M e Ede UE 17 3 1 2 Duterential HR ite deinde dE 17 32 CLOCK DISTRIBUTION Aa TER EE NER Pe REOR sasha 18 3 2 1 Direct Drive _ 18 3 2 2 Mode a uuu usa 19 3 2 3 19 3 2 4 Output CLOCK us 19 3 22 1409310 programming 5e SS SG N atat E la eee cu ope a eti pde cer ipee ooa 19 3 2 6 EM a 19 3 2 7 Direct Drive programming testet ter 19 3 2 8 Configuration
39. REA IRE eS HERE 25 3 4 1 External Tiber MM 25 3 4 2 Software trigger ier iE 25 3 4 3 Loca lchannelauto trigger x seite tte aerei te e Eee REDI aee E icti 26 343 1 Tngs rcomcldernce level eio stint ptor re iege eere ir EE ri ee d eR 26 3 4 4 Trigger distriDullOh izi eie Rr HS ie Qr EE PD IP IEEE QUEE LUE 27 35 FRONTPANELI OS a 27 3 6 ANALOG MONITOR nete eq Roe ERO REPRE GE GE SEDE RET STO SEE E SR EU us SUP RE KE SEE TEES 28 3 6 1 Trigger Majority Mode Monitor Mode 0 0 28 3 6 2 Test Mode Monitor Mode l1 a 29 3 6 3 Buffer Occupancy Mode Monitor Mode 3 nennen eene 29 3 6 4 Voltage Level Mode Monitor Mode 4 a 29 3 7 uu aa tite eater bee bep te erai p Dd Un 29 3 8 RESET CLEAR AND DEFAULT CONFIGURATION 30 3 8 1 Global Reset uc wauu MULIER 30 3 8 2 Memory R set DET 3l 3 8 3 Timet ROSE se 31 En EA is Sau I ec 31 3 91 Addressing Capabilities yo naa beet rei tree
40. RS DATA NPO En m is BERR Block size 1024 bytes BERR enabled BLT size 16384 bytes N 4 Fig 3 15 Example of BLT readout Since some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd it is necessary to add a dummy word which has then to be removed via software in order to avoid data loss This can be achieved by setting the ALIGN64 bit in the VME Control register see S 5 28 MBLT64 cycle is similar to the BLT32 cycle except that the address and data lines are multiplexed to form 64 bit address and data buses The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals DS and DTACK to complete a data cycle 3 11 1 3 CHAINED BLOCK TRANSFER D32 D64 The V1751 allows to readout events from more daisy chained boards Chained Block Transfer mode The technique which handles the CBLT is based on the passing of a token between the boards it is necessary to verify that the used VME crate supports such cycles Several contiguous boards in order to be daisy chained must be configured as first intermediate or last MCST Base Address and Control Register see 5 3600 A common Base Address is then defined via the same register when a BLT cycle is executed at the address CBLT Base 0x0000 OxOFFC the first board starts to transfer its data driv
41. Technical Information Manual Revision n 12 06 February 2012 MOD V1751 4 8 CH 10BIT 2 1 GS s DIGITIZER MANUAL REV 12 NPO 00105 08 V1751x MUTx 12 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards CAEN
42. X CHANNEL CONFIGURATION BIT SET 0x8004 A24 A32 D32 W X X CHANNEL CONFIGURATION BIT CLEAR 0x8008 A24 A32 D32 W X X BUFFER ORGANIZATION 0x800C A24 A32 D32 RW X X BUFFER FREE 0x8010 A24 A32 032 CUSTOM SIZE 0x8020 A24 A32 D32 RW X X BROADCAST ADC CONFIGURATION 0x809C A24 A32 D32 RW X X ACQUISITION CONTROL 0x8100 A24 A32 D32 RW X X ACQUISITION STATUS 0x8104 A24 A32 D32 R SW TRIGGER 0x8108 A24 A32 D32 W TRIGGER SOURCE ENABLE MASK 0x810C A24 A32 D32 RW X X FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 A24 A32 D32 IRW X X POST TRIGGER SETTING 0x8114 A24 A32 D32 RW X X FRONT PANEL I O DATA 0x8118 A24 A32 D32 IRW X X FRONT PANEL I O CONTROL 0x811C A24 A32 D32 IRW X X CHANNEL ENABLE MASK 0x8120 A24 A32 D32 IRW X X ROC FPGA FIRMWARE REVISION 0x8124 A24 A32 032 EVENT STORED 0x812C A24 A32 032 R X X X SET MONITOR DAC 0x8138 A24 A32 D32 IRW X X SW ADC SYNC 0x813C A24 A32 D32 W BOARD INFO 0x8140 A24 A32 032 MONITOR MODE 0x8144 A24 A32 D32 IRW X X EVENT SIZE 0x814C A24 A32 032 X X X VME CONTROL A24 A32 D32 IRW X VME STATUS 4 A24 A32 032 IR BOARD ID OxEF08 A24 A32 D32 RA X X MULTICAST BASE ADDRESS amp CONTROL OxEFOC A24 A32 D32 IRW X RELOCATION ADDRESS OxEF10 A24 A32 D32 RW X INTERRUPT STATUS ID OxEF14 A24 A32 D32 RW X INTERRUPT EVENT NUMBER OxEF18 A24 A32 D32 RW X X NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 39 CAEN Tools for Discovery
43. bal trigger which is distributed to all channels see 3 4 4 THRESHOLD CHO IN N N Local Trigger CH0 Channel Configuration register lt 6 gt 0 Local Trigger CH0 Channel Configuration register lt 6 gt 1 Fig 3 7 Local trigger generation 3 4 3 1 Trigger coincidence level It is possible to set the minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal If for example Trigger Source Enable Mask see 0 bits 7 0 FF all channels enabled and Local trigger coincidence level 1 bits 26 24 whenever an enabled channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 7 0 mask The following figure shows examples with Local trigger coincidence level 1 and 0 Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 26 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 CHO THRESHOLD CHOIN CH THRESHOLD CH1 IN 0j Fig 3 8 Local trigger relationship with Coincidence level 3 4 4 Trigger distribution The OR of all the enabled trigger sources after being synchronized with the internal
44. d Leda nee e Ee ure 43 5 16 BROADCAST ADC CONFIGURATION 0X809C W 1 43 5 17 ACQUISITION CONTROL 0 8100 R W ccccccsssssceccecessesssceeecceecessssseeeeecessesssaseeeceeeeseessseeeceeseesssseeees 43 5 18 ACQUISITION STATUS 0 8104 22020000 00 44 5 19 SOFTWARE TRIGGER 0X8108 4 1 2220 210222 210000 000000000000 44 5 20 TRIGGER SOURCE ENABLE MASK 0X810C 1 4 2 4 1 4 4100000000000000000000000000000000000 0 1 45 5 21 FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 R W 45 5 22 POST TRIGGER SETTING 0X8114 R W 46 5 23 FRONT PANEL I O DATA 0X8118 R W nnne nennen nennen nnne nnne 46 5 24 FRONT PANEL I O CONTROL 0X81 1C R W isses a 46 5 25 CHANNEL ENABLE MASK 0 8120 47 5 26 ROC FPGA FIRMWARE REVISION 0X8124 47 5 27 EVENT STORED 0X8 2C RY si 47 5 28 SET MONITOR DAC 0 8138 1 2 2000000440000010000000000000000000000005050 nnne nennen senes 48 5 29 SW ADC SYNC 0X8 L5C RW de as e as
45. d according to Front Panel Trigger Out Enable Mask 15 setting see 6 5 21 1 I O Test Mode TRG OUT is a logic level set via bit 14 14 12 TRG OUT Test Mode set to 1 0 TRG OUT Test Mode set to 0 13 10 reserved PATTERN LATCH MODE 0 PATTERN field into event headers is the status of 16 LVDS Front Panel Inputs latched with board internal trigger if a post trigger value is set the internal trigger is delayed respect to external one 1 PATTERN field into event headers is the status of 16 LVDS Front Panel Inputs latched with external trigger rising edge 8 reserved 00 General Purpose 01 Programmed 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field see 8 3 3 4 5 0 LVDS I O 15 12 are inputs 9 7 6 Filename Number of pages Page 00105 08 V1751x MUTx 12 1751 REVI2 DOC 52 46 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Bit Function LVDS I O 15 12 are outputs LVDS I O 11 8 are inputs LVDS I O 11 8 are outputs L L 4 3 VDS I O 7 4 are inputs VDS I O 7 4 are outputs 2 LVDS I O 3 0 are inputs 1 LVDS I O 3 0 are outputs 1 0 panel output signals TRG OUT CLKOUT enabled 1 panel output signals TRG OUT CLKOUT enabled in high impedance 0 0 TRG CLK are NIM I O
46. e boards in a VME crate with a BLT access V1751 firmware can be upgraded via VME or Optical Link General purpose C and LabVIEW Libraries Demo and software tools for Windows and Linux 12bit 125 MHz DAC FPGA controlled output four operating modes Test Waveform 1 Vpp test ramp generator Majority MON 2 output signal is proportional to the number of channels enabled under over threshold 1 step 125mV Buffer Occupancy MON output signal is proportional to the Multi Event Buffer Occupancy Voltage level MON output signal is a programmable voltage level 16 general purpose LVDS I O controlled by the FPGA Busy Data Ready Memory full Individual Trig Out and other function can be programmed An Input Pattern from the LVDS can be associated to each trigger as an event marker Number of pages Page CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 Functional description 3 1 Analog Input The module is available either with single ended on MCX connector or on request differential on Tyco MODU II 3 pin connector input channels 3 1 1 Single ended input Input dynamics is 1V Zin 50 Q 16bit DAC allow to add up to 0 5V DC offset to preserve the full dynamic range also with unipolar positive or negative input signals The input bandwidth ranges from DC to 500 MHz Input Dynamic Range 1 Vpp Po
47. e used for this purpose The programming file has the extension CFA CAEN Firmware Archive and is a sort of archive format file aggregating all the standard firmware files compatible with the same family of digitizers CFA and its name follows this general scheme 751 revX Y W Z CFA where e X751 are all the boards the file is compliant to DT5751 6751 V1751 e X Y is major minor revision number of the mainboard FPGA e WZisthe major minor revision number of the channel FPGA WARNING you can restore the previous FW revision in case there is a failure when you run the upgrading program There is a jumper on the mainboard that allows to select the backup copy of the firmware You must upgrade all the FPGAs and keep the revisions aligned it is not guaranteed that the latest revision of one FPGA is compatible with an older revision Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 52
48. ed Width 0252 us Baseline Holdoff Peak Holdoff oo mes 005 4000 ADC channels 8165 49 7022 17 Fig 4 5 DPP Control Software Graphical User Interface and Energy plot NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 38 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 5 VME Interface The following sections will describe in detail the board s VME accessible registers content A N B bit fields that are not described in the register bit map are reserved and must not be over written by the User 5 1 Registers address map Table 5 1 Address Map for the Model V1751 REGISTER NAME ADDRESS ASIZE DSIZE 5 RES CLR EVENT READOUT BUFFER 0x0000 0x0FFC 24 32 64 032 R X X X Channel n THRESHOLD 0 1 80 A24 A32 D32 IRW X X Channel n STATUS 0 1 88 A24 A32 032 R X X Channel n AMC FPGA FIRMWARE REVISION Ox1n8C A24 A32 D32 R Channel n BUFFER OCCUPANCY 0 1 94 A24 A32 032 R X X X Channel n DAC 0 1 98 A24 A32 032 X X Channel n ADC CONFIGURATION Ox1n9C A24 A32 032 R X X Channel n TEMPERATURE MONITOR Ox1nA8 A24 A32 D32 R X X X CHANNEL CONFIGURATION 0x8000 A24 A32 D32 RW X
49. eeseaeeeeaeeesaes 13 FIG 2 6 EC OPTICAL CONNECTOR uw aqna aska Wahana leve ee YE PN sys 14 FIG 2 7 ROTARY AND DIP SWITCHES LOCATION 15 FIG 3 1 SINGLE ENDED INPUT DIAGRAM ssccsssecesseceseeeescecescecesceceseeceseecesceceseeceaeeceseecesceceseeceseeceaeeceaeeseaeeseaeessnes 17 3 2 DIFFERENTIAL INPUT DIAGRAM au L L S e tr a Ere 17 E1G 3 3 CLOCK DISTRIBUTION DIAGRAM 18 FIG 3 4 TRIGGER OVERLAP asuataka oe ee Qo vv qa ede dae 22 FIG 3 5 EVENT ORGANIZATION 24 FIG 3 6 BLOCK DIAGRAM OF TRIGGER 25 3 7 LOCAL TRIGGER GENERATION 26 FIG 3 8 LOCAL TRIGGER RELATIONSHIP WITH COINCIDENCE 4 27 FIG 3 9 MAJORITY LOGIC 2 CHANNELS OVER THRESHOLD BIT 6 OF CH CONFIG REGISTER 0 29 FIG 3 10 BPGA TEST teet riter re REED 30 FIGs A24 ADDRESSING ccie e 32 FIG 3 12 A32 ADDRESS ce 32 NPO Filename Number of pages Page 00105 08 V1751
50. espectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected via the JP2 jumper see 2 6 which can be placed either on the STD position left or in the BKP position right It is possible to upgrade the board firmware via VME by writing the Flash with CAENUpgrader software see 4 available at www caen it website Please refer to CAENUpgrader QuickStart Guide about instructions for use Filename Number of pages Page 51 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 NPO It is strongly suggested to upgrade ONLY one of the stored firmware revisions generally the STD one if both revision are simultaneously updated and a failure occurs it will not be possible to upload the firmware via VME again 6 3 1 V1751 Upgrade files description The board hosts one FPGA on the mainboard and one FPGA for each of the eight channels The channel FPGAs firmware is identical A unique file is provided that will updated all the FPGA at the same time ROC FPGA MAINBOARD FPGA Readout Controller VME interface There is one FPGA Altera Cyclone EP1C20 AMC FPGA CHANNEL FPGA ADC readout Memory Controller There is one FPGA Altera Cyclone EP1C4 All FPGAs can be upgraded via VMEBUS CAENUpgrader utility program must b
51. functions designed specifically for the digitizer family and it supports also the boards running special DPP Digital Pulse Processing firmware The purpose of this library is to allow the user to open the digitizer program it and manage the data acquisition in an easy way with few lines of code the user can make a simple readout program without the necessity to know the details of the registers and the event data format The CAENDigitizer library implements a common interface to the higher software layers masking the details of the physical channel and its protocol thus making the libraries and applications that rely on the CAENDigitizer independent from the physical layer The library is based on the CAENComm library that manages the communication at low level read and write access CAENVMELib and CAENComm libraries must be already installed on the host PC before installing the CAENDigitizer however both CAENVMELib and CAENComm libraries are completely transparent to the user WaveDump is a Console application that allows to program the digitizer according to a text configuration file that contains a list of parameters and instructions to start the acquisition read the data display the readout and trigger rate apply some post processing such as FFT and amplitude histogram save data to a file and also plot Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751 REVI2 DOC 52 36 CAEN Tools for Discovery Document type
52. ger Request 8 out Memory Full 9 out Event Data Ready 10 out Channels Trigger 11 out RUN Status 12 in Trigger Time Tag Reset active low 13 in Memory Clear active low 14 RESERVED 15 RESERVED 3 6 Analog Monitor NPO The board houses a 12bit 125MHz DAC with 0 1 V dynamics on a 50 Ohm load see Fig 1 1 whose input is controlled by the ROC FPGA and the signal output driving 50 Ohm is available on the gt output connector MON output of more boards can be summed by an external Linear Fan In This output is delivered by a 12 bit DAC The DAC control logic implements four operating modes Trigger Majority Mode Monitor Mode 0 Test Mode Monitor Mode 1 Buffer Occupancy Mode Monitor Mode 3 gt Voltage Level Mode Monitor Mode 4 Operating mode is selected via Monitor Mode register see 5 31 Monitor Mode 2 is reserved for future implementation 3 6 1 Trigger Majority Mode Monitor Mode 0 It is possible to generate a Majority signal with the DAC a voltage signal whose amplitude is proportional to the number of channels under over see 6 5 3 threshold 1 step 125mV this allows an external discriminator to produce a global trigger signal as the number of triggering channels has exceeded a particular threshold Filename Number of pages Page 28 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 CAEN Tools for Discovery D
53. h is reset either as acquisition starts or via front panel Reset signal see 3 8 and is incremented at each sampling clock hit It is the trigger time reference NPO Filename Number of pages Page 00105 08 V 1751x MUTx 12 1751 REVI2 DOC 52 23 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 3 4 2 Samples Stored samples data from masked channels are not read When operating V1751 at 2 GS s EVEN channels are automatically disabled Bit 31 30 are useful to acknowledge how many samples are in the last word of an event 1 to 3 example in S 3 3 4 3 shows a case with two samples in the last word 3 3 4 3 Event format example The event format is shown in the following figure case of 8 channels enabled PP PPP EEE PPP PEEP EPP EEEL EECA Eve Sample 0 ch 1 Sample 2 ch 1 Sample 1 ch 1 1 EI Sample 5 ch 1 Sample 4 ch 1 Sample 3 ch 1 o Sai Sampien2 g c 1 Sample 2 ch 7 Sample 1 ch 7 Sample 0 ch 7 1 Sample 5 ch 7 Sample 4 ch 7 Sample 3 ch 7 2587 Fig 3 5 Event Organization 3 3 5 Temperature monitor and power down 3 3 5 1 ADC chips temperature readout The V1751 provide a ADC core temperature monitoring feature useful in order to estimate the steady thermal state and to perform the calibration procedure see 3 3 1 Each ADC houses two
54. her priority anyway it is better to avoid accessing the board via VME and Optical Link simultaneously Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 35 CAEN Tools for Discovery Document type User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Title Revision date Revision 4 Software tools NPO TER TREES omm Library 2 Optical Link Fig 4 1 Block diagram of the software layers CAEN provides drivers for both the physical communication channels the proprietary CONET Optical Link managed by the A2818 PCI card or A3818 PCle cards and the VME bus accessed by the V1718 and V2718 bridges refer to the related User Manuals a set of C and LabView libraries demo applications and utilities Windows and Linux are both supported The available software is the following CAENComm library contains the basic functions for access to hardware the aim of this library is to provide a unique interface to the higher layers regardless the type of physical communication channel Note for VME access CAENcomm is based on CAEN s VME bridges V1718 USB to VME and V2718 PCI PCle to VME In the case of third part bridges or SBCs the user must provide the functions contained the CAENcomm library for the relevant platform The CAENComm requires the CAENVMELib library to be installed even in the cases where the VME is not used CAENDigitizer is a library of
55. ignal for example if bit 7 0 FF all channels enabled and Local trigger coincidence level 1 whenever one channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 7 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see 5 19 5 21 Front Panel Trigger Out Enable Mask 0x8110 r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 8 reserved 0 Channel 7 trigger disabled 7 1 Channel 7 trigger enabled 6 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 4 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 2 _ 0 Channel 2 trigger disabled NPO Filename Number of pages Page 00105 08 V 1751x MUTx 12 1751 REVI2 DOC 52 45 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Bit Function 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled
56. iguration 0x8000 r w Bit Function 12 0 1 GS s rate 1 2 GS s rate Dual Edge Sampling When Dual Edge Sampling mode is used make sure that the EVEN channels are disconnected 11 7 reserved 6 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold allows to generate local trigger either on channel over or under threshold see 5 3 5 reserved 4 0 Memory Random Access 1 Memory Sequential Access 3 0 Test Pattern Generation Disabled 1 Test Pattern Generation Enabled 2 reserved 1 0 Trigger Overlapping Not Enabled 1 Trigger Overlapping Enabled Allows to handle trigger overlap see 3 3 3 0 reserved This register allows to perform settings which apply to all channels It is possible to perform selective set clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0x8008 clear see the following 5 11 and 5 12 Default value is 0x10 5 11 Channel Configuration Bit Set 0x8004 w Bit Function 12 0 Bits set to 1 means that the corresponding bits in the Channel Configuration register are set to 1 5 12 Channel Configuration Bit Clear 0x8008 w Bit Function 12 0 Bits set to 1 means that the corresponding bits in the Channel Configuration register are set to 0
57. ing DTACK properly once the transfer is completed the token is passed to the second board via the IACKIN IACKOUT lines of the crate and so on until the last board which completes the data transfer and asserts BERR which has to be enabled the Master then ends the cycle and the slave boards are rearmed for a new acquisition If the size of the BLT cycle is smaller than the events size the board which has the token waits for another BLT cycle to begin from the point where the previous cycle has ended 3 11 2 Random readout to be implemented Events can be readout partially not necessarily starting from the first available and are not erased from the memories unless a command is performed In order to perform the random readout it is necessary to execute an Event Block Request via VME Indicating the event to be read page number 12 bit datum the offset of the first word to be read inside the event 12 bit datum and the number of words to be read size 10 bit datum At this point the data space can be read starting from the header which Filename Number of pages Page 00105 08 V1751x MUTx 12 1751 REVI2 DOC 52 34 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 12 NPO reports the required size not the actual one of the event the Trigger Time Tag the Event Counter and the part
58. ing to setting of buffer size register NPO Filename Number of pages Page 00105 08 1751 12 V1751_REV12 DOC 52 47 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 5 28 Set Monitor DAC 0x8138 r w Bit Function 11 0 This register allows to set the DAC value 12bit This register allows to set the DAC value in Voltage level mode see 6 2 7 LSB 0 244 mV terminated on 50 Ohm 5 29 SW ADC SYNC 0x813C r w Bit Function 81 0 This register allows to ensure the proper ADC synchronization within the board channels after a calibration procedure 5 30 Board Info 0x8140 r Bit Function 15 8 Memory size code V1751 V1751B 0x02 V1751C 0x10 7 0 Board Type 0x05 5 31 Monitor Mode 0x8144 r w Bit Function This register allows to encode the Analog Monitor see 5 3 6 operation 000 majority 2 0 001 2 waveform generator saw tooth 010 reserved 011 buffer occupancy 100 voltage level 5 32 Event Size 0 814 r Bit Function 31 0 Nr of 32 bit words in the next event 5 33 VME Control r w Bit Function 7 0 Release On Register Access RORA Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode 6 0 RELOC Disabled B
59. ister see 8 5 8 and 5 16 in order to achieve the best performance it is strongly suggested to calibrate the channels through the Broadcast ADC Configuration register 3 3 1 1 Normal mode self calibration Set to 0 the Calibration bit of Broadcast ADC Configuration register Set such bit to 1 The self calibration process will start and the flag Calibrating bit of Channel n Status register see 8 5 4 will be set to 0 Polling on the flag Calibrating bit until it returns to 1 few milliseconds Set again to 0 the Calibration bit of Broadcast ADC Configuration register 3 3 1 2 Dual Edge Sampling mode self calibration Make sure that the EVEN channels are disconnected Disable mask EVEN channels see 6 5 25 Select Dual Edge Sampling mode bit 12 of the channel configuration register see 8 5 9 Setto 0 the Calibration bit of Broadcast ADC Configuration register Set such bit to 1 The self calibration process will start and the flag Calibrating bit of Channel n Status register see 5 4 will be set to 0 Polling on the flag Calibrating bit until it returns to 1 few milliseconds Set again to 0 the Calibration bit of Broadcast ADC Configuration register Whenever switching from one mode Normal or Dual Edge Sampling to another calibration must be repeated 3 3 2 Acquisition run stop The acquisition can be started in two ways according to Acquisition Control register
60. l Form factor Input Memory WV1751XAAAAA V1751 6U VME64 Single ended 1 8 3 6MS ch WV1751BXAAAA V1751B 6U VME64 Differential 1 8 3 6MS ch WV1751CXAAAA V1751C 6U VME64 Single ended 14 4 28 8MS ch WVX1751XAAAA _ VX1751 6U VME64X Single ended 1 8 3 6MS ch WVX1751BXAAA VX1751B 6U VME64X Differential 1 8 3 6MS ch WVX1751CXAAA _ VX1751C 6U VME64X Single ended 14 4 28 8 5 NPO Filename Number of pages Page 00105 08 1751 12 1751 REVI2 DOC 52 8 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 1 2 Block Diagram FRONT PANEL x2 mezzanines Loud AMC FPGA ADC amp MEMORY CONTROLLER lt BUFFERS a gt ao 2 mh 5 eS 5 u uu gt LLI ROC FPGA s Readout control VME interface control L Optical link control M Trigger control External interface control Fig 1 1 Mod V1751 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00105 08 1751 12 1751 REVI2 DOC 52 9 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch
61. mware upgrade tool 5 46 Configuration Reload 0xEF34 w Bit Function 31 0 A write access to this register causes a software reset see 3 8 a reload of Configuration ROM parameters and a PLL reconfiguration NPO Filename Number of pages Page 00105 08 1751 12 V1751_REV12 DOC 52 50 CAEN Tools for Discove ry Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 6 Installation The Mod V1751 fits into GU VME crates The V1751 cannot be operated with CAEN crates VME8001 8002 VX1751 versions require VME64X compliant crates Use only crates with forced cooling air flow Turn the crate OFF before board insertion removal Remove all cables connected to the front panel before board insertion removal CAUTION USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEAT MAY DAMAGE THE MODULE A CAUTION ALL CABLES MUST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE 6 1 Power ON sequence To power ON the board follow this procedure 1 insert the V1751 board into the crate 2 power up the crate 6 2 Power ON status At power ON the module is in the following status e the Output Buffer is cleared e registers are set to their default configuration see 5 6 3 Firmware upgrade NPO The board can store two firmware versions called STD and BKP r
62. o an external clock reference or to a clock Digitizer master board The data stream is continuously written in a circular memory buffer When the trigger occurs the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either via VME or via Optical Link The acquisition can continue without dead time in a new buffer Each channel has a SRAM memory buffer available in the 1 835 and 14 4 MSamples ch sizes which become 3 6 and 28 8 MSamples ch when using Dual Edge Sampling with independent read write access divided in 1 to 1024 buffers of programmable size The trigger signal can be provided via the front panel input as well as via the VMEbus but it can also be generated internally The trigger from one board can be propagated to the other boards through the front panel Trigger Output An Analog Output allows to reproduce the trigger majority a test waveform and the buffer occupancy The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer D32 32 64 bit Block Transfer BLT MBLT 2eVME 2eSST and 32 64 bit Chained Block Transfer CBLT The boards houses a daisy chainable Optical Link able to transfer data at 80 MB s thus it is possible to connect up to eight ADC boards 64 ADC channels to a single Optical Link Controller Mod A2818 Optical Link and VME access are internally arbitrated Table 1 1 Available items Code Mode
63. ocks and NS 2M Nblocks for 1 835 MSamples ch 14 4 MSamples ch version respectively Smaller values can be achieved by writing the number of locations into the Custom Size register see 5 5 15 Nioc 0 means default size events i e the number of memory locations is the maximum allowed Nioc N1means that one event will be made of 7 N1 or 14 N1 DES mode 3 3 4 Event structure An event is structured as follows Header 4 32 bit words Data variable size The event can be readout either via VME or Optical Link data format is 32 bit long word Filename Number of pages Page 22 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 CAEN 2015 for Discovery Len type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 3 4 1 Header It is composed by four words namely Size of the event number of 32 bit long words Board ID GEO Bit24 data format 0 16 bit pattern latched on the LVDS I O as one trigger arrives see 5 24 Channel Mask 21 channels participating to event ex CH5 participating Ch Mask 0xAQ this information must be used by the software to acknowledge which channel the samples are coming from Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see 6 5 15 Trigger Time Tag It is a 32 bit counter 31 bit count 1 overflow bit whic
64. ocument type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 THRESHOLD CHO IN THRESHOLD CH1 IN 250mV 25mV MAJORITY Fig 3 9 Majority logic 2 channels over threshold bit 6 of Ch Config Register 20 In this mode the MON output provides a signal whose amplitude is proportional to the number of channels over the trigger threshold The amplitude step 1 channel over threshold is 125mV 3 6 2 Test Mode Monitor Mode 1 In this mode the MON output provides a sawtooth signal with 1 V amplitude and 30 518 Hz frequency 3 6 3 Buffer Occupancy Mode Monitor Mode 3 In this mode MON out provides a voltage value proportional to the number of buffers filled with events step 1 buffer 2 0 976 mV This mode allows to test the readout efficiency in fact if the average event readout throughput is as fast as trigger rate then MON out value remains constant otherwise if MON out value grows in time this means that readout rate is slower than trigger rate 3 6 4 Voltage Level Mode Monitor Mode 4 In this mode MON out provides a voltage value programmable via the N parameter written the SET MONITOR DAC register with Vmon 1 4096 N 3 7 Test pattern generator NPO The FPGA AMC can emulate the ADC and write into memory a sawtooth signal for test purposes It can be enabled via Channel Configuration register see 8 5 9 The foll
65. of the event required on the channel addressed in the Event Block Request After data readout in order to perform a new random readout it is necessary a new Event Block Request otherwise Bus Error is signaled In order to empty the buffers it is necessary a write access to the Buffer Free register see 5 14 the datum written is the number of buffers in sequence to be emptied BUFFERS SELECT THE BUFFER NUMBER SELECT THE STARTING OFFSET READUT SELECT THE BLOCK LENGHT Fig 3 16 Example of random readout Optical Link The board houses a daisy chainable Optical Link communication path which uses optical fiber cables as physical transmission line able to transfer data at 80 MB s therefore it is possible to connect up to eight V1751 to a single Optical Link Controller for more information see www caen it path Products Front End PCI PCIe Optical Controller The parameters for read write accesses via optical link are the same used by VME cycles Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error VME Control Register bit 3 allows to enable the module to broadcast an interrupt request on the Optical Link the enabled Optical Link Controllers propagate the interrupt on the PCI bus as a request from the Optical Link is sensed VME and Optical Link accesses take place on independent paths and are handled by board internal controller with VME having hig
66. owing figure shows the test ramps for even and odd channels respectively Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 29 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 Even channel test wave 1200 1000 800 600 400 200 0 ps 0 200 400 600 800 H 1000 1200 1400 Even channel down zoom 1023 1000 800 600 400 255 200 63 15 3 0 0 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 Odd channel test wave 1200 1000 800 600 400 200 1200 1400 Odd channel ramp up zoom 1008 100 1023 1000 960 800 768 600 400 200 0 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 Fig 3 10 FPGA test waveform 3 8 Reset Clear and Default Configuration 3 8 1 Global Reset Global Reset is performed Power ON of the module e viaa VME RESET SYSRES Software reset see 5 42 NPO Filename Number of pages Page 00105 08 V 1751x MUTx 12 1751 REVI2 DOC 52 30 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 It allows to clear the data off the Output Buffer the event counter and performs a FPGAs global reset which restores the FPGAs to the default configuration It initializes all counters to their ini
67. rded NPO Not Recorded TRIGGER PRE 4 ACQUISITION WINDOW a 1 Overlapping Triggers Fig 3 4 Trigger Overlap A trigger can be refused for the following causes acquisition is not active memory is FULL and therefore there are no available buffers the required number of samples for building the pre trigger of the event is not reached yet this happens typically as the trigger occurs too early either with respect to the RUN ACQUISITION command see 8 3 3 1 or with respect to a buffer emptying after a MEMORY FULL status the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continues writing on it The Event Counter can be programmed in order to be either incremented or not If this function is enabled the Event Counter value identifies the number of the triggers sent but the event number sequence is lost if the function is not enabled the Event Counter value coincides with the sequence of buffers saved and readout 3 3 3 1 Custom size events It is possible to make events with a number of Memory locations which depends on Buffer Organization register setting see 5 13 smaller than the default value One memory location contains 7 ADC samples and the maximum number of memory locations Ni oc is NS 256K Nbl
68. sitive Unipolar FSR 1 00 0 50 FPGA 0 0 50 1 00 pru Unipolar Bipolar DAC FSR2 Fig 3 1 Single ended input diagram 3 1 2 Differential input Input dynamics is 1Vpp Zdiff 100 0 The input bandwidth ranges from DC to 500 MHz Differential Mode 7 AW AW 9 Zdiff Input MODUII w ui FPGA x DAC Fig 3 2 Differential input diagram NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 17 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 3 2 Clock Distribution NPO MEZZANINES x2 IMS Acquisition amp Memory Control Logic Loca Bus Interface LOCAL BUS OSC CLK Fig 3 3 Clock distribution diagram The module clock distribution takes place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock OSC CLK handles both VME and Local Bus communication between motherboard and mezzanine boards see red traces in the figure above REF CLK handles ADC sampling trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either an external via front panel signal or an in
69. ternal via local oscillator source selection is performed via dip switch SW1 see 6 2 6 in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway REF CLK is processed by AD9510 device which delivers 6 clock out signals 4 signals are sent to ADCs one to the trigger logic and one to drive CLK OUT output refer to AD9510 data sheet for more details http www analog com UploadedFiles Data Sheets AD9510 pdf two operating modes are foreseen Direct Drive Mode and PLL Mode 3 2 1 Direct Drive Mode The aim of this mode is to drive externally the ADCs Sampling Clock generally this is necessary when the required sampling frequency is not a VCXO frequency sub multiple The only requirement over the SAMP CLK is to remain within the ADCs range Filename Number of pages Page 00105 08 V1751x MUTx 12 1751 REVI2 DOC 52 18 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 NPO 3 2 2 PLL Mode The AD9510 features an internal Phase Detector which allows to couple REF CLK with VCXO 1 GHz frequency for this purpose it is necessary that REF CLK is a sub multiple of 1 GHz AD9510 default setting foresees the board internal clock 50MHz as clock source of REF CLK This configuration leads to 100 5 thus obtaining 10MHz at the Phase Detector input and CLK INT
70. tial state and clears all detected error conditions 3 8 2 Memory Reset The Memory Reset clears the data off the Output Buffer The Memory Reset can be forwarded via either a write access to Software Clear Register see S 5 43 or with a pulse sent to the front panel Memory Clear input see 8 3 5 3 8 3 Timer Reset The Timer Reset allows to initialize the timer which allows to tag an event The Timer Reset be forwarded with a pulse sent to Trigger Time Tag Reset input see 3 5 3 9 VMEbus interface NPO The module is provided with a fully compliant VME64 VME64X interface see 6 1 1 whose main features are EUROCARD 9U Format 1 1 and J2 P2 with either 160 pins 5 rows or 96 3 rows connectors A24 A32 and CR CSR address modes 032 BLT MBLT 2eVME 2eSST data modes write capability CBLT data transfers RORA ROAK interrupter Configuration ROM 3 9 1 Addressing capabilities 3 9 1 1 Base address The module works in A24 A32 mode The Base Address of the module can be fixed through four rotary switches see 2 6 and is written into a word of 24 or 32 bit The Base Address can be selected in the range Filename Number of pages Page 1 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 3 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 0x000000 gt OxFF0
71. us during the Interrupt Acknowledge cycle NPO Filename Number of pages Page 00105 08 V1751x MUTx 12 V1751_REV12 DOC 52 49 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 5 39 Interrupt Event Number 0xEF18 r w Bit Function 9 0 INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events INTERRUPT EVENT NUMBER 5 40 BLT Event Number OxEF1C r w Bit Function 7 0 This register contains the number of complete events which has to be transferred via BLT CBLT see 3 11 1 2 5 41 Scratch 0xEF20 r w Bit Function 31 0 Scratch to be used to write read words for VME test purposes 5 42 Software Reset 0xEF24 w Bit Function 31 0 A write access to this location allows to perform a software reset 5 43 Software Clear OXEF28 w Bit Function 31 0 A write access to this location clears all the memories 5 44 Flash Enable OxEF2C r w Bit 0 0 Flash write ENABLED 1 Flash write DISABLED This register is handled by the Firmware upgrade tool 5 45 Flash Data 0xEF30 r w Function Bit Function 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Fir
72. x MUTx 12 V1751_REV12 DOC 52 6 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1751 4 8 Ch 10 bit 2 1 GS s Digitizer 06 02 2012 12 FIG 3 13 CR CSR ADDRESSING uu u Su A 32 FIG 3 14 SOFTWARE RELOCATION OF BASE ADDRESS a s 32 FIG 3 15 EXAMPLE OF RBADOUT reris eee ree repete ore rather perra R 34 FIG 3 16 EXAMPLE OF RANDOM 2 2 2 ea ees eine 35 FIG 4 1 BLOCK DIAGRAM OF THE SOFTWARE LAYERS 36 FIG 4 2 WAVEDUMP OUTPUT WAVEFORMS sss 37 FIG 4 3 CAENSCOPE OSCILLOSCOPE TAB csssccessecesseeeseeeesceceseecesnecescecssneeesaeeeaeeesaecesaeeesaeessceeseaeeeaeeenaeenseeeseas 37 FIG 4 4 CAENUPGRADER GRAPHICAL USER INTERFACE ccescscesseceseeeeseecescecececsseeceseeceaeeceaeeceeeceseeseeeenseeesnes 38 FIG 4 5 DPP CONTROL SOFTWARE GRAPHICAL USER INTERFACE AND ENERGY 38 LIST OF TABLES TABLE AVAILABLE ITEMS e NUES ee ERU ree ERE EUER FERE aae E Vea eae s EYE TRE eX ERA 8 TABLE 2 1 MODEL V1751 POWER 75 1 0000000000000000000000000200 tian na sss s eene t ess 10 TABEE2 2 PRONTPANEELEDS en rr EHE teri pea ro era teur reni 14 TABLE 2 3 MOD V1751 TECHNICAL SPECIFICATIONS

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