F re e s c a le S e m ic o n d u c to r, I n c . ..
Contents
1. 162 MHz 220 MHz Num Characteristic Units Min Max Min Max B1 Valid to CLKIN rising setup 755854 7 5 8 5 FE nS B2 CLKIN rising to invalid hold 1 0 1 0 nS B3 3 Valid to CLKIN rising setup 0 0 nS B4 3 CLKIN rising to invalid hold 0 5 C1 4 1 3 0 5 C1 1 3 nS B5 CLKIN to input high impedance 2 2 Bus clock B6 CLKIN to EDGESEL delay 0 5 0 0 5 0 nS A O N Inputs BG TA A 23 0 PP 15 0 SIZ 1 0 RAV TS EDGESEL D 31 0 and BKPT Inputs IRQ 7 5 3 1 Inputs AS Inputs D 31 0 Table 20 8 lists specifications for timings in Figure 20 6 Figure 20 7 and Figure 20 13 Although output signals that share a specification number have approximately the same timing due to loading differences they do not necessarily change at the same time However they have similar timings that is minimum and maximum times are not mixed Table 20 8 Output AC Timing Specification 162 MHz 220 MHz Num Characteristic Units Min Max Min Max T n 10 54 10 54 ns B10 t23 CLKIN rising to valid E 5 12 5 12 5 ns B11 45 CLKIN rising to invalid 4 0 10 nS hold B12 97 CLKIN to high impedance 10 10 nS three state 58 0 5 C1 10 5 9 0 5 C1 410 5 nS B13 CLKIN rising to valid 10 10 0 5 C1 12 5 0 5 C1 12 5 nS pg14823 CLKIN rising to invalid 0 5 C1 12. ms X E he ipa Scr x d DRAW X SC d 6 24 430 l D 31 0 d p RS X 7 vos aM l cos X Fo ACTV NOP WRITE NOP PALL 1 DACR CASL 2 Figure 20 12 SDRAM Write Cycle with EDGESEL Tied Low Figure 20 13 shows AC timing showing high impedance m A L e OUTPUTS Ak Figure 20 13 AC Output Timing High Impedance 16 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Reset Timing Specifications 20 4 Reset Timing Specifications Table 20 9 lists specifications for the reset timing parameters shown in Figure 20 14 Table 20 9 Reset Timing Specification 162 MHz 220 MHz Num Characteristic Units Min Max Min Max R1 Valid to CLKIN setup 7 5 7 5 m nS R2 CLKIN to invalid hold 1 0 1 0 nS R3 RSTI to invalid hold 1 0 1 0 nS 1 RSTI and D 7 0 are synchronized internally Setup and hold times must be met only if recognition on a particular clock is required Figure 20 14 shows reset timing for the values in Table 20 9 CLKIN RSTI EAT RI j R3 Note Mode selects are registered on the rising CLKIN edge before the cycle in which RSTI is recognized as being negated Figure 20 14 Re
3. PV x Cc cc Figure 20 2 Example Circuit to Control Supply Sequencing 20 2 Clock Timing Specifications Table 20 5 shows the MCF5407 PLL encodings Note that they differ from the MCF5307 DIVIDE 1 0 encodings Table 20 5 Divide Ratio Encodings Input Clock MHz Core Clock MHz PSTCLK MHz D 2 0 DIVIDE 2 0 Multiplier 162 MHz 220 MHz 162 MHz 220 MHz 162 MHz 220 MHz 00x 010 Reserved 011 40 0 54 0 40 0 55 0 3 120 0 162 120 0 165 60 0 81 0 60 0 82 5 100 25 0 40 5 25 0 55 0 4 100 0 162 100 0 220 50 0 81 0 50 0 110 101 25 0 32 4 25 0 44 0 5 125 0 162 125 0 220 67 5 81 0 67 5 110 110 25 0 27 0 25 0 36 6 6 150 0 162 150 0 220 75 0 81 0 75 0 110 111 Reserved Figure 20 3 correlates CLKIN and core clock frequencies for the 3x 6x multipliers 6 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Timing Specifications CLKIN Core Clock l l l l l 40 54 120 162 B 3x gt 40 55 120 165 25 40 5 100 de 4x gt 25 55 100 22 25 32 4 125 162 1 lt 5x I I I I 2
4. 0 0 5 C1 1 0 nS hold B1523 EDGESEL to valid 12 12 nS B1623 EDGESEL to invalid hold 2 2 nS H1 HIZ to high impedance 60 60 nS H2 HIZ to low Impedance 60 60 nS when configured as parallel port outputs Outputs that can change on either CLKIN edge depending only on EDGESEL D 31 0 A 23 0 SCKE SRAS SCAS and DRAMW and on PP 15 8 when individually configured as A 31 24 outputs MOTOROLA For More Information On This Product Go to www freescale com Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 Freescale Semiconductor Inc Input Output AC Timing Specifications 8 9 Outputs that can change on either CLKIN edge depending upon EDGESEL and the interface operating mode DRAM SDRAM RAS 1 0 CAS 3 0 SRAS SCAS DRAMW RAS 1 0 CAS 3 0 D 31 0 A 23 0 TM 2 0 TT 1 0 SIZ 1 0 R W TIP TS BR BD and TA and PP 15 8 when individually configured as A 31 24 outputs High impedance three state D 31 0 Outputs that transition to high impedance due to bus arbitration A 23 0 R W SIZ 1 0 TS AS and TA and PP 15 8 when individually configured as A 31 24 outputs Outputs that change only on falling edge of CLKIN AS CS 7 0 BE 3 0 OE SRAS SCAS DRAMW RAS 1 0 CAS 3 0 AS CS 7 0 BE 3 0 OE 10 D 31 0 A 23 0 TM 2 0 TT 1 0 SIZ 1 0 RAW TIP and TS and on PP 15 8 when individually configured as Note t
5. MHz Num Characteristic Units Min Max Min Max C6 PSTCLK duty cycle at 1 5 V 40 60 40 60 96 G7 BCLKO cycle time 18 5 Note 18 18 Note ns C8 BCLKO duty cycle at 1 5 V 45 55 45 55 C9 CLKIN to BCLKO 1 5 1 5 1 5 1 5 nS The PLL low frequency limit depends on the clock divide ratio chosen See Table 20 5 Figure 20 4 shows timings for the parameters listed in Table 20 6 CLKIN cp i X cs Oe e a ee Note Input and output AC timing specifications are measured to CLKIN with a 50 pF load capacitance not including pin capacitance N Figure 20 4 Clock Timing Figure 20 5 shows PSTCLK timings for parameters listed in Table 20 6 PERCENT Figure 20 5 PSTCLK Timing 20 3 Input Output AC Timing Specifications Table 20 7 lists specifications for parameters shown in Figure 20 6 and Figure 20 7 Note that inputs IRQ 7 5 3 1 BKPT and AS are synchronized internally that is the logic level 8 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output AC Timing Specifications is validated if the value does not change for two consecutive rising CLKIN edges Setup and hold times must be met only if recognition on a particular clock edge is required Table 20 7 Input AC Timing Specification
6. Timing Specifications 20 6 Timer Module AC Timing Specifications Table 20 11 lists specifications for timer module AC timing parameters shown in Figure 20 17 Table 20 11 Timer Module AC Timing Specification 162 MHz 220 MHz Num Characteristic Units Min Max Min Max T1 TIN cycle time 3 3 Bus clocks T2 TIN valid to CLKIN input setup 7 5 PEZ 7 5 nS T3 CLKIN to TIN invalid input hold 1 0 1 0 nS T4 CLKIN to TOUT valid output valid 12 12 nS T5 CLKIN to TOUT invalid output hold 1 0 1 0 nS T6 TIN pulse width 1 1 Bus clocks T7 TOUT pulse width 1 1 Bus clocks Figure 20 17 shows timings for Table 20 11 CLKIN TIN TIN TOUT MOTOROLA Xo o E Hm X 6 X Figure 20 17 Timer Module AC Timing Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to www freescale com 19 Freescale Semiconductor Inc IC Input Output Timing Specifications 20 7 I C Input Output Timing Specifications Table 20 12 lists specifications for the pc input timing parameters shown in Figure 20 18 Table 20 12 C Input Timing Specifications between SCL and SDA 162 MHz 220 MHz Num Characteristic Units Min Max Min Max H Start condition hold time 2 2 E Bus clocks 12 Clo
7. in AC 97 Mode MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parallel Port General Purpose I O Timing Specifications 20 9 Parallel Port General Purpose I O Timing Specifications Table 20 15 lists specifications for general purpose I O timing parameters in Figure 20 22 Table 20 15 General Purpose I O Port AC Timing Specifications 162 MHz 220 MHz Num Characteristic Units Min Max Min Max P1 PP valid to CLKIN input setup 7 5 7 5 nS P2 CLKIN to PP invalid input hold 1 0 mE 1 0 nS P3 CLKIN to PP valid output valid 12 5 12 5 nS P4 CLKIN to PP invalid output hold 1 0 1 0 nS Figure 20 22 shows general purpose O timing CLKIN Jt N as PP OUT X _ gt Figure 20 22 General Purpose I O Timing 24 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DMA Timing Specifications 20 10 DMA Timing Specifications Table 20 15 lists specifications for DMA timing parameters shown in Figure 20 22 Table 20 16 DMA AC Timing Specifications 162 MHz 220 MHz Num Characteristic Units Min Max Min Max M1 DREQ valid to CLKIN input setu
8. which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2003 MCF5407UMAD D For More Information On This Product Go to www freescale com
9. www freescale com 13 Freescale Semiconductor Inc Input Output AC Timing Specifications A 31 0 SRAS SCAS DRAMW D 31 0 RAS CAS ro 395 ee I oes or Bs Se De 11 DN XN NN a X Row X Column ACTV NOP WRITE NOP PALL DACR CASL 2 Figure 20 10 SDRAM Write Cycle with EDGESEL Tied High Figure 20 11 shows an SDRAM read cycle with EDGESEL tied low 14 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Input Output AC Timing Specifications Gl ay eed ae a e see ei see soe 1 ao ot aes tas is um SS SN FNS X Xf 13 A 31 0 X Row X Column X i 4 DRAMW 7 Mo uper dp D 31 0 m c lt r ws Dm EN Br m A E ACTV NOP READ NOP NOP PALL DACR CASL 2 Figure 20 11 SDRAM Read Cycle with EDGESEL Tied Low Figure 20 12 shows an SDRAM write cycle with EDGESEL tied low MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output AC Timing Specifications hot il ees sell o c ses i Bs Bs toe ei 12 oon eg Re Oe A Ae lt A 31 0 X Row X Column X
10. 5 44 125 220 2527 150 162 lt 6x gt 25 86 6 150 220 l l 25 30 35 40 45 50 55 100 110 120 130 140 150 160 170 180 190 200 210 220 CLKIN MHz Core Clock MHz 162 MHz Device 220 MHz Device Figure 20 3 CLKIN to Core Clock Frequency Ranges Table 20 6 lists specifications for the clock timing parameters shown in Figure 20 4 and Figure 20 5 Motorola recommends that CLKIN be used for the system clock BCLKO is provided only for compatibility with slower MCF5307 designs Regardless of the CLKIN frequency driven at power up CLKIN and BCLKO have the same ratio value to the PCLK Although either signal can be used as a clock reference CLKIN leaves more room to meet the bus specifications than BCLKO which is generated as a phase aligned signal to CLKIN Table 20 6 Clock Timing Specification 162 MHz 220 MHz Num Characteristic Units Min Max Min Max C1 CLKIN cycle time 18 5 Note 18 18 Note nS C2 CLKIN rise time 0 5V to 2 4 V 2 2 nS c3 CLKIN fall time 2 4V to 0 5 V 2 2 nS C4 CLKIN duty cycle at 1 5 V 40 60 40 60 96 C5 PSTCLK cycle time 12 3 Note 9 1 Note nS MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output AC Timing Specifications Table 20 6 Clock Timing Specification 162 MHz 220
11. Addendum MCF5407UMAD D Rev 2 2 2003 Freescale Semiconductor Inc ele M ej MOTORHOEA digital dna gence everywhere Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 This errata describes corrections and updates to rev 0 of the MCF5407 ColdFire Integrated Microprocessor User s Manual Motorola document order number MCF5407UM D The General MCF5407 Changes section contains information that needs to be changed throughout the book Please check the world wide web at http www motorola com semiconductors for the latest updates For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 1 General MCF5407 Changes The MCF5407 is offered with the temperature and frequency specifications shown in Table 1 Table 1 MCF5407 Temperature and Frequency Specifications Package Operating Temperature Frequency MIPS Rating 208 plastic QFP 0 to 70 C 54 MHz max CLIN 316 Dhrystone MIPS at 220 MHz max PCLK 220 MHz 208 plastic QFP 40 to 85 C 54 MHz max CLKIN 233 Dhrystone MIPS at 162 MHz max PCLK 162 MHz NOTE These specifications further amend the electrical characteristics described in Section 1 General MCF5407 Changes The following section Chapter 20 Electrical Specifications replaces Chapter 20 of the MCF5407 ColdFire Integrated Microprocessor User s Manual 2 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOR
12. ME PAGE http www motorola com semiconductors DOCUMENT COMMENTS FAX 512 933 2625 Attn TECD Applications Engineering Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in
13. O valid signal from driven or 30 nS three state J10 TCK falling to TDO high impedance 30 nS J11 TCK falling to boundary scan data valid signal from ms 30 nS driven or three state J12 TCK falling to boundary scan data high impedance 30 nS Figure 20 24 shows JTAG timing 26 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to www freescale com MOTOROLA TDI TMS BOUNDARY SCAN DATA INPUT TRST TDO BOUNDARY SCAN DATA OUTPUT MOTOROLA Freescale Semiconductor Inc IEEE 1149 1 JTAG AC Timing Specifications aes SHE COMES lt gt lt q 2 Figure 20 24 IEEE 1149 1 JTAG AC Timing Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HO
14. OLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Parameters Chapter 20 Electrical Specifications This chapter describes the AC and DC electrical specifications and thermal characteristics for the MCF5407 Note that this information was correct at the time this book was published As process technologies improve there is a likelihood that this information may change To confirm that this is the latest information see Motorola s ColdFire webpage http www motorola com coldfire 20 1 General Parameters Table 20 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature Operating outside of these ranges may cause erratic behavior or damage to the processor Table 20 1 Absolute Maximum Ratings Rating Symbol Value Units External I O pads supply voltage 3 3 V power pins EVoc 0 3 to 4 0 V Internal logic supply voltage Wes 0 5 to 2 0 V PLL supply voltage PVoc 0 5 to 2 0 3 V Internal logic supply voltage input voltage level Vin 0 5 to 3 6 4 V Storage temperature range Tstg 55 to 4150 Me IVoc must not exceed EV IV amp c and PV must not differ by more than 0 5 V PV must not exceed EV Vin must not exceed EV A OU N Table 20 2 lists junction and ambient operating temperatures Table 20 2 Operating Temperatures Characteristic Symbol Value Units Max
15. by the prescale and division values programmed in IFDR Because SCL and SDA are open collector type outputs which the processor can only actively drive low the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull up resistor values 3 Specified at a nominal 50 pF load 20 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc UART Module AC Timing Specifications Figure 20 18 shows timing for the values in Table 20 12 and Table 20 13 00 y Js NE KO MEN fy At Xd XI 5 D cT LE DA a a Figure 20 18 I C Input Output Timings 20 8 UART Module AC Timing Specifications Table 20 14 lists specifications for UART module AC timing parameters in Figure 20 19 Table 20 14 UART Module AC Timing Specifications 162 MHz 220 MHz Num Characteristic Units Min Max Min Max U1 RXD valid to CLKIN input setup 7 5 7 5 nS U2 CLKIN to RXD invalid input hold 1 0 1 0 nS U3 CTS valid to CLKIN input setup 7 5 7 5 nS U4 CLKIN to CTS invalid input hold 1 0 1 0 PES ns U5 CLKIN to TXD valid output valid 12 12 nS U6 CLKIN to TXD invalid output hold 1 0 1 0 nS U7 CLKIN to RTS valid output valid 12 12 ns U8 CLKIN to RTS invalid output hold 1 0 1 0 nS U9 CTS high ti
16. c 0 Time Notes 1 Vec PVe rising before EV 2 EV rising much faster than IVcc PVec Figure 20 1 Supply Voltage Sequencing and Separation Cautions IV should not be allowed to rise early 1 This is usually avoided by running the regulator for the IV supply 1 8 V from the voltage generated by the 3 3 V EV supply Figure 20 2 This keeps IV from rising faster than EV IV should not rise so late that a large voltage difference is allowed between the two supplies 2 Typically this situation is avoided by using external discrete diodes in series between supplies as shown in Figure 20 2 The series diodes forward bias when the difference between EV and IV ec reaches approximately 2 1 V causing IV to rise as EV ramps up When the IV regulator begins proper operation the difference between supplies should not exceed 1 5 V and conduction through the diode chain reduces to essentially leakage current During supply sequencing the following general relationship should be adhered to EV S IV EV 2 1 V The PLL Vdd PV supply should comply with these constraints just as IV does In practice PV is typically connected directly to IV with some filtering MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Timing Specifications 3 3 V Supply Regulator EVoc 1 8V Regulator IV
17. ck low period 8 8 Bus clocks I3 SCL SDA rise time Vi 0 5 V to Vi 2 4 V 1 1 mS 14 Data hold time 0 0 nS I5 SCL SDA fall time Vj 2 4 V to Vj 0 5 V 1 1 mS le Clock high time 4 4 EE Bus clocks I7 Data setup time 0 0 nS 18 Start condition setup time for repeated start condition 2 2 Bus clocks only 19 Stop condition setup time 2 2 Bus clocks Table 20 13 lists specifications for the Pc output timing parameters shown in Figure 20 18 Table 20 13 I C Output Timing Specifications between SCL and SDA 162 MHz 220 MHz Num Characteristic Units Min Max Min Max ni Start condition hold time 6 6 Bus clocks 121 Clock low period 10 10 Bus clocks 13 SCL SDA rise time V 0 5 V to Vj 2 4 V Note2 Note2 Note2 Note 2 141 Data hold time 7 7 Bus clocks Ib SCL SDA fall time Vj 2 4 V to Vj 0 5 V 3 3 nS le Clock high time 10 10 Bus clocks 1771 Data setup time 2 2 Bus clocks ig 1 Start condition setup time for repeated start 20 20 Bus clocks condition only ig Stop condition setup time 10 10 Bus clocks 1 Programming IFDR with the maximum frequency IFDR 0x20 results in the minimum output timings listed here The I C interface is designed to scale the data transition time moving it to the middle of the SCL low period The actual position is affected
18. e 1 PVoc 1 65 1 95 V Input high voltage Vin 2 4 3 6 V Input low voltage Vib 0 5 0 5 V Input signal undershoot 0 8 V Input signal overshoot 0 8 V Input leakage current 0 5 2 4 V during normal operation lin 20 pA High impedance three state leakage current 0 5 2 4 V during Its 20 yA normal operation Signal low input current Vi 0 8 V 3 li 0 1 mA Signal high input current Vi 2 0 V 3 li 0 1 mA Output high voltage lop 6 mA 12 mA VoH 2 4 Output low voltage Io 6 mA 12 mA VoL 0 5 Load capacitance all outputs C 50 pF Capacitance 8 V 0 V f 1 MHz CiN TBD pF IVc and PV should be at the same voltage All pins except MTMOD For MTMOD Vj 2 6V Vi 0 4V 3 BKPT TMS DSI TDI DSCLK TRST D 31 0 A 23 0 PP 15 0 TS TA SIZ 1 0 RW BR BD RSTO AS CS 7 0 BE 3 0 OE PSTCLK PSTDDATA 7 0 DSO TOUTT 1 0 SCL SDA RTS 1 0 TXD 1 0 5 BCLKO RAS 1 0 CAS 3 0 DRAMW SCKE SRAS SCAS 6 Capacitance Cy is periodically sampled rather than 100 tested Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Parameters 20 1 1 Supply Voltage Sequencing and Separation Cautions Figure 20 1 shows two situations to avoid in sequencing the IV and EV supplies oO S 9 33V E Voc Q Qa a a a 1 8V4 Moe PVe
19. hat these figures show two representative bus operations and do not attempt to show all cases For explanations of the states SO S5 see Section 18 4 Data Transfer Operation Note that Figure 20 7 does not show all signals that apply to each timing A 31 24 outputs specification See the previous tables for a complete listing Figure 20 6 shows AC timings for normal read and write bus cycles rns Sg d li S SO 1 S2 S3 S4 S5 S0 1 S2 S3 S4 S5 3 a nt et 4 B et gt og CLKIN ES JO Md NW P FT TM 2 0 A TTE X SIZ 1 0 R W Hp X E XT ER 7 ens gt lt l B Figure 20 6 AC Timings Normal Read and Write Bus Cycles Figure 20 7 shows timings for a read cycle with EDGESEL tied to buffered CLKIN 10 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output AC Timing Specifications loli lz2la l4ls5s el 7z 8 o 10 1 eee 14 m n A A 31 0 X Row y Column X EL l SRAS if ERN e lt lt i SCAS ES 816 E DRAMW J l l lt gt D 31 0 l gt tt ms X d E CAS ACTV NOP DACR CASL 2 READ NOP PALL Figure 20 7 SDRAM Read Cycle with EDGESEL Tied to Buffe
20. imum operating junction temperature Tj 95 oc Maximum operating junction temperature Extended Temperature Device Tj 110 oc Maximum operating ambient temperature TAmax 70 oc Maximum operating ambient temperature Extended Temperature Device TAmax 85 oc Minimum operating ambient temperature TAmin 0 oc Minimum operating ambient temperature Extended Temperature Device TAmin 40 oc This published maximum operating ambient temperature should be used only as a system design guideline All device operating parameters are guaranteed only when the junction temperature lies within the specified range MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc General Parameters Table 20 3 lists thermal resistances Table 20 3 Thermal Resistance Characteristic Symbol Value Units Junction to ambient AT 26 1 C W Junction to top reference Vj 1 9 C W Table 20 4 lists DC electrical specifications This table is based on an operating voltage of EVcc 3 3 Vdc 0 3 Vdc and IVcc of 1 8 0 10 Vdc Table 20 4 DC Electrical Specifications Characteristic Symbol Min Max Units External I O pads operation voltage range EVoc 3 0 3 6 Internal logic operation voltage range Voc 1 7 1 9 V PLL operation voltage rang
21. me 38 38 ns U10 CTS low time 38 38 nS U11 CTS rising to TxD valid 20 mE 20 nS U12 RxD setup to CTS falling 10 10 mE nS U13 RxD hold from CTS falling m 5 5 nS U14 TxD to RxD remote loop back 15 15 nS U15 TIN1 setup to CTS falling 10 10 nS U16 TIN1 hold from CTS falling 5 m 5 nS U17 CTS rising to RTS asserted 20 20 ns Figure 20 19 shows UARTO and UARTI timing for the values in Table 20 14 MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Module AC Timing Specifications N CLKIN A N 3 a ra Ca I T Figure 20 19 UARTO and UART1 Module AC Timing UART Mode Figure 20 19 shows timing for UARTI in 8 and 16 bit CODEC mode 22 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc UART Module AC Timing Specifications CTS NS ar EUM Serial bit clock l U11 TxD X 3 8G lt XY TIN1 Frame sync 63 Figure 20 20 UART1 in 8 and 16 bit CODEC Mode Figure 20 21 shows timing for UARTI in AC 97 mode CTS Eis Bit clock l _ _ RTS Frame sync Figure 20 21 UART1
22. p 7 5 7 5 nS M2 CLKIN to DREQ invalid input hold 1 0 1 0 nS M3 CLKIN to DACK valid output valid 10 10 nS M4 CLKIN to DACK invalid output hold 1 0 1 0 nS Figure 20 23 shows DMA AC timing MOTOROLA CLKIN A DREQ X Qe DACK Figure 20 23 DMA Timing Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to www freescale com 25 Table 20 17 IEEE 1149 1 JTAG AC Timing Specifications Freescale Semiconductor Inc IEEE 1149 1 JTAG AC Timing Specifications 20 11 IEEE 1149 1 JTAG AC Timing Specifications Table 20 17 lists specifications for JTAG AC timing parameters shown in Figure 20 24 All Num Characteristic frequencies Units Min Max TCK frequency of operation 0 10 MHz J1 TCK cycle time 100 nS J2a TCK clock pulse high width measured at 1 5 V 40 nS J2b TCK clock pulse low width measured at 1 5 V 40 nS J3a TCK fall time Vi 2 4 V to Vij 0 5V 5 nS J3b TCK rise time Vi 0 5v to Viy 2 4V m 5 nS J4 TDI TMS to TCK rising input setup 10 nS J5 TCK rising to TDI TMS invalid hold 15 nS J6 Boundary scan data valid to TCK setup 10 nS J7 TCK to boundary scan data invalid hold 15 nS J8 TRST pulse width asynchronous to clock edges 15 J9 TCK falling to TD
23. red CLKIN Figure 20 8 shows an SDRAM write cycle with EDGESEL tied to buffered CLKIN MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Input Output AC Timing Specifications lol lilz2 ls3l4ls5 6lz7ls8 9 10 1 12 15 lt A 31 0 X Row X Column X ws X jeg a l D 31 0 c pa RS X T ae l CS A Fo ACTV NOP WRITE NOP PALL 1 DACR CASL 2 Figure 20 8 SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN Figure 20 9 shows an SDRAM read cycle with EDGESEL tied high 12 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com CLKIN Freescale Semiconductor Inc Input Output AC Timing Specifications amp x ill 8 1 ay ier d X f 12 13 OE 14 15 T X Xe A 31 0 Column X SRAS SCAS DRAMW D 31 0 RAS CAS OX i ACTV DACR CASL 2 Figure 20 9 SDRAM Read Cycle with EDGESEL Tied High NOP READ NOP PALL Figure 20 10 shows an SDRAM write cycle with EDGESEL tied high MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 For More Information On This Product Go to
24. set Timing MOTOROLA Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 17 For More Information On This Product Go to www freescale com 20 5 Debug AC Timing Specifications Freescale Semiconductor Inc Debug AC Timing Specifications Table 20 10 lists specifications for the debug AC timing parameters shown in Figure 20 16 Table 20 10 Debug AC Timing Specification 162 MHz 220 MHz Num Characteristic Units Min Max Min Max D1 PSTDDATA to PSTCLK setup 4 5 3 nS D2 PSTCLK to PSTDDATA hold 4 5 3 nS D3 DSI to DSCLK setup 1 1 PSTCLKs D4 DSCLK to DSO hold 4 4 PSTCLKs D5 DSCLK cycle time 5 5 PSTCLKs DSCLK and DSI are synchronized internally D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK Figure 20 15 shows real time trace timing for the values in Table 20 10 PSTCLK NN PSTDDATA 7 0 Figure 20 15 Real Time Trace AC Timing Figure 20 16 shows BDM serial port AC timing for the values in Table 20 10 OMEN NEN NN ae DSCLK F 03 re gt DSI Current Next s DSO x Past X Current Figure 20 16 BDM Serial Port AC Timing 18 Errata to MCF5407 Integrated Microprocessor User s Manual rev 0 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timer Module AC
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