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1. Qeder Restoration war 23 18352217 Qu 07910214 ty ot speed vt engueue Enqueve opergiion was not rejected Buffer Pood ID gt 0x20 frame StamusCommand Ou Frame f 00 short panye butter 5 1 E umgle Frame olfwt O8 1280 tame lenge u 1 58 Frame Partion ID Addoem gt 0609107240 by Verbose mode Debug Tag L lt Olic Chamet lt OCT Software Dequeve nace event Oros fietoanos not toeohea at are mtag Operation wat not reacted Butter Pool K Q0 Frame StanayComenand 000 Frame Korzset i short tingle buffer empie Frame offset 328 gih lt Cede 118 Partiban ID lt 0 29102140 7140522798 EMI FM1 Engine BML Restoraion Regueed fase Port ID lt 1075 5 Debug flow ABC sate ILL 1 fD 2 Que 20000026061 000800009400000000 tmestamp 11408477 ees w e s 1 155 cs 2 MM Prepare Ox b65a 00 2140083151 30 ace in a Action x to enqueue tame Orden Rettorapon equam fane Port D id SEC S nx cate 1 1 1 ib lt Dwe 2000002 nthe L000800009400000000 FPM tenestanp 7140682251 w bug Tag L POND 0601 Chemet lt O90 connect portal OO FMI
2. conet portal VMI Command Dxpatztwd trace eveni Geder Restotation wm not toeo hed at been wat Got ejected Buller Pood ID OOD Frame Status C Orear Os Parme Formar sort angie butter nimple frame offwt Odi 1780 fame 0994 1149 Frame Partibon ID lt Adaren 020414280 mode Debug Tag L FOR Otit Charme lt 021 Software O1 Dequeoe trace event win 901 podhod enqueur operaton was not reecied Bufter K OQO Frame Statu Command AO Frame format 2 hort pagi waffe Frame offset gt aB 128 Ware length 0x94 143 Frase Pareoon ID lt Ove Address 070818180 Sul FMI Eng BML Action Ordering Restorseon Required fase Port ID Qar 20000029102 1 400800008a0000000 2139614572 _ ooc nne rent sorce 4 I9 185520047989 Qu Ox2b813180 30 1155224852 21 18552227222 029202149 12 FMI Action 1 aqme ame Ordering 22222 ARO ROO Smegtamo AMMA mode Debug Tag L POND lt dile Charest a Gat Oreg cone Oe MI Lagqueue Comman Deapatrhed trace 2 22 1652237222 FMI 02010210
3. Piy mw uso we baron kutun Wa IOAN 4 wa Te Sect erat CXII Sac Fre Generated files CW uboot ddrinit c DDR SDRAM CFG mem OxFF702110 CSO BNDS mem OxFF702000 CSO CONFIG mem OxFF702080 CSO CONFIG 2 mem OxFF7020CO TIMING CFG 3 mem OxFF702100 TIMING CFG 0 mem OxFF702104 TIMING CFG 1 mem OxFF702108 TIMING CFG 2 mem O xFF70210C DDR SDRAM CFG 2 mem OxFF702114 DDR SDRAM MODE OxFF702115 mem DDR Controller i Registers 47000008 0 80014202 0 00030000 0 00330104 Ox6E6BBB46 OxOFASDOCC 0 24401050 0 00061421 Rdefrine define deLrine Rdefine define define define define define DDR Controller configured registers values Rdefine define define define define define DDR 1 INIT FXT ADDR ADDR 70214 DDR 1 SDRAM RCW 1 ADDR DDR 1 SDRAM RCW 2 ADDR DDR 1 DATA INIT ADDR DDR 1 SDRAM MD CNTL ADDR DDR 1 DDRCDR 1 ADDR DDR 1 DDRCDR 2 ADDR SDRAM CFG MEM EN MASK SDRAM CFG2 D INIT MASK DDR 1 50 BNDS VAL DDR 1 CS1 BNDS VAL DDR 1 CS2 BNDS VAL DDR 1 CS3 BNDS VAL DDR 1 CS0 CONFIG VAL DDR 1 CS1 CONFIG VAL OxFF702180 xFF702184 xFFT702128 OxFF702120 2 28 2 2 0 80000000 0 00000010 x3F 0 00 0 00
4. kuqa Arey C h Cote TEX Capre Cee ira Coh ros Carn P Dont Sok wa 3o Sete POD Pewee Caper Orar Rusa and Vora an were ct Preece Zerecondure mc Re US Tx OF e TM 85 Artar Bett enact Coste Yawa Mage VC Pistons m 0 Fw M Dore Qervergs OOO Enga Pwy mew uto nt and wa adero Wo ord 0 wa Te Yus MPEG Amat X111 Sorter ere 4 24080 ds ode PBL1 pb Edt Search Run Profle Processor Expert Window Help x4 Qr MP LIE LI odeWarthor Dey 05 paiid 0 v Documentation o Generated Code Sources S ia Vw Corfigustions v2 Operating System soc P00 v2 0 5 Embedaed Components DOR 1 PEL 1 PEL S wbisiipont Manager apconhig Changed values are highlighted after import freescale 9 a 71 comen Inspector 21 elopment Studio no NF IU DUU IN DDR Reference Clock Memory Controller Comghes MEM Ri CFG 8 9 cba Frequency reference dock Lore Clusters PLL Care Complenues PLL SEL 96 99 obo000 CCt PU fl Cl FU El 100 108 ObOO00 OCI Pu C2 PU SEL 104 107 Qt0000 ft C3 SEL 108 111 0600
5. erat X111 Predefined configurations Scenario Name Description DPAA All DPAA All Enable FM Timestamps DPAA 1 DPAA FM DPAA QM Decode Only 4 2 freescale Measures an overview of all of the DPAA activity Measures an overview of all of the DPAA Activity Overview of FM1 activity FM1 marks the frames for debug and generates trace Overview of FM2 activity FM2marks the frames for debug and generates trace FM1 and FM2 mark the frames for debug but don t generate trace Only QM generates Trace Decodes and existing DPAA Binary Trace File freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc You should now Be familiar with the QorlQ Configuration Suite basics V1 supports PBL amp DDR configuration available since June 2011 V2 adds Device Tree DPAA Graphing tools available since
6. w 4 irt Ege Py SMAI MS mw molo yi and we deron La mcondkusta Wa IOAN OF eoe neni Te X111 P PE ES QE Saw te EN 2 a D plor SANE am Properties Mame Memory Controller Complex MEM 8 9 MEM PLL RAT 10 14 DDR PLL Output Clock Core Clusters PLL CC1 PLL CFG 64 65 RAT 66 70 Core Cluster 1 PLL Clock ZFS 72 73 PLL 74 78 Core Cluster 2 PLL Clock CC3 PLL 80 81 PLL 82 86 Core Cluster 3 PLL Clock CC4 PLL CFG 88 89 CC4 RAT 90 94 Core Complexes PLL CD PLL SEL 96 99 Core PLL Clock C1 PLL SEL 100 103 Core 1 PLL Clock C2 PLL SEL 104 107 Core 2 PLL Clock SEL 108 111 Core 3 PLL Clock SEL 112 115 C5 PLL SEL 116 119 C6 SEL 120 123 C PLL SEL 124 127 2 freescale Value Ob01 Higher Frequency reference cl 0601100 12 1 async mode only 600 000 MHz Ob00 Core cluster PLL 1 autpu 0601111 15 1 Async 1 500 GHz Ob00 Core cluster PLL 2 autput freq 0601111 15 1 Async 1 500 Hz Core cluster PLL 3 output Ob01001 9 1 Async 900 000 MHz Ob00 Core cluster PLL 4 output freq 0601111 15 1 Async ObOOOO C
7. Migr a Facius Qon hoewerge OCC Erpa Pwy mw ad wu yayuna Wa of 4 O Te Py W Tus ete watak X111 moro Va Generated files CW uboot ddrinit c DDR SDRAM CFG mem OxFF702110 CSO BNDS mem OxFF702000 CSO CONFIG mem OxFF702080 CSO CONFIG 2 mem OxFF7020CO TIMING CFG 3 mem OxFF702100 TIMING CFG 0 mem OxFF702104 TIMING CFG 1 mem OxFF702108 TIMING CFG 2 mem O xFF70210C DDR SDRAM CFG 2 mem OxFF702114 DDR SDRAM MODE OxFF702115 mem DDR Controller i Registers 47000008 0 80014202 0 00030000 0 00330104 Ox6E6BBB46 OxOFASDOCC 0 24401050 0 00061421 Rdefrine define deLrine Rdefine define define define define define DDR Controller configured registers values Rdefine define define define define define DDR 1 INIT FXT ADDR ADDR 70214 DDR 1 SDRAM RCW 1 ADDR DDR 1 SDRAM RCW 2 ADDR DDR 1 DATA INIT ADDR DDR 1 SDRAM MD CNTL ADDR DDR 1 DDRCDR 1 ADDR DDR 1 DDRCDR 2 ADDR SDRAM CFG MEM EN MASK SDRAM CFG2 D INIT MASK DDR 1 50 BNDS VAL DDR 1 CS1 BNDS VAL DDR 1 CS2 BNDS VAL DDR 1 CS3 BNDS VAL DDR 1 CS0 CONFIG VAL DDR 1 CS1 CONFIG VAL OxFF702180 xFF702184 xFFT702128 OxFF702120 2 28 2 2 0 80000000 0 00000010 x3F 0
8. 20 fod maste portals gm portal id 0 kq false Godn 1 lt a portal id 3 q false liodn 1 lt portals gt Total gids 150000 lt totalfgidts gt fodenemornypartition e MEM 157 DDR NON CACHEABLE c ftadmemorypartition lt piarmemerypanitions e MEM IST DOR NON CACHEABLE lt of d reoeenorvpartition tases Aeg 1 T Base lt rthramesdegth gt 30000 rf ea mes pl rteeshold ox pfartreshold gt st ntreshold O sfdrmeshold gt trepart name tmOportOl IG number 1 engine neon import name fm OportO3 type 1G number 3 engine hmo ai n me tmOpont sm 1 erfald QCS DPAA Component Features 1 e Default values capability Instant display of relevant description for each configuration parameter e Easy access to configuration settings for each DPAA element S5 Component Inspector 22 Basic Advanced Expert I 7 10x 1 1 1 1 110 Queue base Queue count This attribute is only relevant when used in a queue elements inside of the distribution element It defines the number of permitted sequential values Valid values for count are powers of 2 When Mame Total number of Fqids 1500000 Fad memory partition Primary DDR non cacheable Pfdr memory partit
9. Files of type smi 4 2 freescale E Processor Expert Eclipse Platform Fle fat Search Protect Run Processo Dpat Widow 0 a e eio vy f t f 3 apot test FIO Document auiem gt Gere ted Code Sources ProcessorE pert pe Configurations paced v2 0 OF l5 Operating 5 s DQ BS Cancel EZ Pu mp y tage COUPE Coffee Cora Uo res Cn elo yy for Sobre 8 evt a m 41 Caper Coruna Ts Satanas Bere Vora adiens ct mc Rey US Tx 7 O8 Atar festo Creve Magee VOC Parton w 4 DC Dongs Q OC Py molo ma te lt beers Lacoste Wa ote OF Cu wa wa Te tery Sete erat CXII ax wa Import XMLs Feature Demo Importing files previously generated by the tool won t produce the same output objects coordinates are not saved the xmls and are calculated using a placement algorithm at the import time Processor Papert Eclipse Platform I I m mi xl Import demo Fille Edit Navigate Search Project Run Processor Expert Window Help LS mi EN d 05 4 r x z T y Pro
10. cpu PowerPC 408060 amp Property cpuD PowerPC 4080480 4 V L2 0 I2 cache device type device type cpu TTT 8 cpul PowerPC 408061 Value reg lt 0 0 gt 2 Console Progess 0 Sext 1 cpu2 PowerPC 4080 2 B Property next level cache amp L2 0 Qus 12 matches N worsspace E cpu3 PowerPC 40803 Names red iu m alan memory Value lt 0x0 gt L2 0 2 12 9 QR Generated Code i bman portalseff 4000000 Property next level cache lt amp gt 0905204 qman portals Ff4200000 Name next level cache y soc 00000 value z amp L2 0 y 7 O rooted rapidioO rapidio ffetcoo00 G localbus ffe124000 cpui PowerPC 408001 0 pcie ffe200000 Pa pci pcie Ffe201000 pci2 pcie ffe202000 B Fsl dpaa cpu2 PowerPC 408082 129 HE 130 131 cpu3 PowerPC 408083 411 139 nE 140 141 if 107 w lt lt gt o 2 Fm P aj mn Lon res Bee Er yy for 8 evt tmi 1 cocoa Caper Corona betel Gotta money and Yorn av Sere ot Preece mc Heg US Tx OS e 9 143 rtu 57 em Magevy VOC Parton w 4 Sort ead Py ent TM var 4 YY 4
11. a qud 06 ONG men a Lat An Vit et e ieee ugue w arm oe De wr qoos bean oor Tome ede hep o has t 4 Hom nnt 2 w roger time e P WT comm mama omo domm j per yros DR rend C ue Ono v OU The ater FOYT Mut Te a s den in Sh L gt ce p 25005009158 M 14 w 7 mrt mto oe s amm P 1 gt on Pod i ced E ne sa 4 es L gt freesid eger mi Freeh 1 1 tuso am FOOT JI Ce me reee me oor wp NOT ev Sm www a ardeo be ee w woa paynu aae 1 omm Md paip tes t Loved cede m wwe ort dodo s oon oF et ooo heat kw ood x wx STONE but p ADIN a dabo 4 du enm mom be is tanso ep muitaj otes 4 be tet das 4 om wass to se m Decem rer a 1 ev 1 rtt others L e Gras C Co 2 freescale U etd eed misteret I l hrt O afri eec fw v p kun Aw OE Code TET 24 wd fr tar Trocesmr Caper ta
12. kutim dO 4 heb wa Te Sect CXII Deter ere Fre BOOTROM Step 4 Prepare configuration data file for SD MMC using L2 cache Component Inspector i3 Properties Name Value Device BOOTROM Reset Configuration PLL Configuration Device Status SerDes Configuration Boot Configuration High Speed I O Configuratio General Purpose POR Confit Engineering Use POR Config Pin Multiplexing Configurati Miscellaneous Configuration Boot ROM Data Configuratio Offset ji Output Configuration SD MMC Control Words User s Code Length 00080000 2 Source Address 00001000 H Target Address F8F80000 H Execution Start Addres F FFF000 H Configuration Words Data Structure 104 2 freescale Adding configuration pairs address data to be included into configuration data file V 4 2 freescale Data Structure Data Structure Delay 256 of CCB clocks 4 Configuration Words dig structure definition Version specific item Sett 3 105 SDAC configuration parameters fi 2zed0c DHA transaction 40000001 00000100 Delay command Basic Advanced Expert int 2 Address tr 10000001 Pata 0x L2 SRAH configuration parameters tr 720100 8 B8 D D base address ff F20ed4 ECC errors disabled
13. Run time Measurement OMS 040 Li Cemcmmples Catat DOR combo emn 4 I CPU QMan combo FU loging wih pachet ra A 14 paded DPAA Qam Onqueue Courts a UU PAte ea mom i M g zz Progress agar tn daptar Chee tine E gt x reca kuqa AAwa C5 Cod o TEX Con mos Wapa Pe Egy Dont Sra X net MEG ar OLEE 57 Exper Qel Coruna Eobhan Ta Satanas Spree acordi ane ct Faca Zarecondute mc US Tx OF Artur 7 Corse uem ny waww Mages VOC Priorem 4 Pap Gort Enga Py SMAPS mw umol na yi and wu Ka mcondusa Wa ord OF bivio Qw wa Te Ny CXII Serer ores be How counters work A particular happening in the System on Chip is called an event In this case we are counting Hammer hits 52 2 freescale Counter 2 Event Processing Unit ter Value These counters could be counting Cache Misses DDR Access Or MORE Ctr 1 Ctr 2 o Co Fw bre E 89 wm 05 6 x Con ms 0 pa Pe Don Sukta go Sete MEO Pewee 59 Caper Coruna Eobhan Ta Gotten Sy vore and Vora av were ot Preece
14. ive festo Gee Stect Cow Vw Mage Parton a wet lt oy Degree Mwy SMa VY a 4 2 a ss v irine 4 Tx rots eov ar 4 s amp ii hem xor 4 2 freescale DPAA Hands on Generated Code Usage HW configuration P4080 v2 0 Loopback on FM ports used SW configuration CodeWarrior PA 10 1 2 NetCommSw v4 5 Usecase running Import DpaaQcsUseCases NetCommSw and UserEnv for P4080 Replace generated code files luser envibare UseCases common controller DPAA QCS fmc config c doc_struct h Clean amp build project Run on target Receive output 2 freescale CodeWarrior Projects 3 File Name E 325 DpaaQcsUseCases QCS Dbg 2 Binaries Includes El Gp NetcCommSw Eg gccport Icf zr libs El p user El amp env El l p bare l p inc El l p UseCases El 7p common controller El gp DPAA l p common inc El gp 0 5 L dpc config c dpc config h dpc_defaults c defaults h dpc_struct h 8 fmc config c fmc config h fmc exec c fmc h l init qcs c L main c l p integrations OCS Dbg E QCS Dbg launch gt Referenced Projects SaAnalysispointsManager apconfig wem Pu mp y ge Ay gt delt Nar Pre Lov owe 163 gt
15. and Yorn av adea Freeecate Zenecoadctaer mc Atar festo gt Pen Peete karwa kzim Wo amp rofw pots neler nt Lon vos Cn Ww Er yy for amp Mage Petters 4 Pe Gert Dongs Py owe w wa cw UL Fs Ui Reg US Tux amp 7 CO Of eive wa Te pect CXII ax Wa Explorer Tree View Operations on nodes back forward gt Device Tree Properties Interrupts Device Tree Nodes DTI soc i2 device tree Expand collapse 4 aliases i 4 cpus General information Documentation AS cen d In g d esce 4 dcsr dcsr f00000000 This section describes general information about the selected node This node is used ta repres bman portals fF4000000 present if the processor is nd SO rt gx Mame soc socBffe000000 Press F1 for more details gman portals ff4200000 Parent device tree dh Insert node F3 rt n ode A imn Delete node Delete Lines 13 1420 Rename node F2 Delete node cane ddr2 m 015 Search _ R e n am e n O d e 1 Refresh FS This section describes information about the selected node s properties 8 4 iommu amp A Expand P X E e Other operations mpic Pid Colapse Name val
16. DataPath Trace Visibility into FM and QM activities via Nexus Trace Trace data Can be collected from a running system Without interrupting it and Without affecting its performance Can be collected to on board trace buffer Is timestamped so it can be used to precisely measure the timings FM trace Optionally output by each FM engine BMI KeyGen Parser etc Timestamped internally by the FM clock The trace data contains FD FM port number NIA etc QM trace Optionally output by each QM enqueue and dequeue point trace data contains FQID channel frame address frame length enqueue dequeue flag portal type and number etc Traced frames Only the tagged frames are traced Tagged FD DD bits set Rxflow the frames tagged by the FM as configured by the Packet Analysis Tool Other flows the frames tagged by the instrumented software running on the cores Se z freescale s Configuring the Packet Tools Run Measure Help 5 9 Q7 B Cong Con g2 22 Q Configuration Select the Connection and Scenariothat will be used to collect the trace data for analysis 2 00 Target connection x TAP configuration and system type e g P5020 Processor P4080 7 Status 9 unknown try scanning probe 2 Name Description Configuration Script DPAA All Dverview of the activity FM1 and FM2 mark a
17. Gort Erpa mw umo nt ma haero OOO Y AZ Gw POLS Of ove Ce a y fus eraut X111 weh Ya 4 DDR Step 2 Import DDR1 and DDR2 Registers Dump Under QCS Processor Expert p4080 core0 Source main c CodeWarrior Development Studio File Edit Source Refactor Navigate Search Project Run Profiler Processor Expert Window Help 3 7 Ee u iig QqQ mv y Project Panel 22 H T 1 Component Inspector x ET Basic Advanced Expert I p s M E z z rdb core Import i e pd sn gt Documentation Memory Dump File Generated Code Input File DADebianshare GorIQsDK 03 O08 DDR hweonfig noneyddr1 _OxFFeOO8000_O FreOoerfF bin d File Format Raw Binary v gt Configurations Access Size JA 2 0 gt Operating System Addressable Size 5 Endian made 8 9 0 080 v2 n B E Embedded Components Address Information P Dl PBL1 PBL Beginning memory address 005000 DDR_mc1 DDR 1 DDR mcz bDR SaAnalysispaints anager apcanfig EE p4080 coreo gt CFG DDR Controller memory address Use default H Debug Settings 12 Hardware Debug core E LEF L DL a Ev Components Library x h 0 Categories Alphabetical Assistant CPUs
18. Coh mes Carn P 100 Processor Caper Coruna Ta Satanas and ane ot Preece mc Hep US Tx OV Atar festo w 4 Paipa Gort Py mw rol oe yi Fesoni Wa of CAA Te W wert CXII wee aswa re 2 freescale Properties e h a n g n g toO b010 6 1 cfg sys pll 0 2 Pins LA 29 31 Device desired 400 Mhz gt 600 Mhz 6 1 M cfg core pll 0 2 06011 3 2 1 5 1 cfg corel pll 0 2 06011 3 2 1 5 1 1600 Mhz 2 900 Mhz Pins LBCTL LALE LGPL2 LOE 4 CCB Clock SYSCLK Ratio Pins B UART SOUTI READ cfg sys pll 0 2 DDR Complex DDRCLK R ddr pll 0 2 4 e500 Core CCB Clock Ratio Cored 4 1 Corel 4 Core clocking cfg_core0_pll 0 2 06000 4 1 sm cf corel 0 2 0b000 4 1 I O Port Selection s to 3 2 cfg io ports 0 3 MI eTSEC3 x1 gt SerDes lane 3 ins TSEC1_TXD 3 1 TSEC2 TX ER 4 SerDes Configuration Y 4 SerDes Reference Clock cfg srds refclk 4 SerDes PLL Time out SerDes reference cla C h ang I ng cfq srds pll toe Disable I pit Port Selection cfg_io_ports 0 3 051111 PCIe to hav
19. Zarecomdure mc He US Tx OF Atar festo my www Mage Parton 4 Gort Ege Py SMAI MS mw molo yi Cree wa adero Ra coadura Al oc eoe nee Te Py erat X111 Sor er Step 3 Observe Power on reset overview details MERI NBN lia 2 Boon Puente Resort Q fepotfW Fi Report for P2020 Q Reporter Pino 83 Power On Reset Target Configuration Overview for P2020 fiber Usar 23137 Freencete QCS_TESTELALD 120522 1 ndiae werkapece PMD Raport hire Power On Reset Target Configuration Overview for P2020 3 Copyright 1 1997 2012 Preescale Semiconductor Ino All Rights Reserved 2 http wwu freescale com zail suppert iceescale coe Power On Reset Configuration settings PLL Configuration settings CCB Clock PLL Ratio settings for information only Cock SYSCLK Rano 61 500 O00 MHz ctg sys pl 0 2 POR Signa sys pil G 290 29 sys pi 1 ot LAM sys pit 2 JT Ur DOR Complex DORCLK Ratio Copyright 1997 2012 Freescale Semiconductor Inc All Rights Reserved 2 http 2 www freescale com cfg_sys_pll
20. Zoom 100 Selection 323 gn QCS DPAA Component Features 4 Immediate code generation at user request in any stage of TS Project Panel MM s om Inspect El FTF_demo_usecase Generating code Joj x Generate x Expert Project Documentation a gt Generated Code Sources B ProcessorExperF pe E E Configurations P4080_v2_0_ChF 1 5 Operating System E Cpus F socC iPanan v2 0 za Embedded Components 3108 DPAA1 DPAA QorIQ _ 20 1 Generating cade dema usecaselProcessoarExpert pe Always run in background Run in Background Cancel Details gt gt B ES E Sage Immediate notification for all errors occurring during the code generation process Problems 53 El Console 1 error warnings others Description RC errors 1 item ERROR Incorrect size For queue distribution id 2 2 freescale di import XMLs Feature based files DPAA objects Connections between them DPAA objects configuration Automatic update of the objects and links after import is done hand DPC Configuration this is the file that has to be imported le xml wersion 1 0 encoding 2 utr 8a amp 2 lt dpe xmlns xi 2 http J immr w3 org 2001 XInclude zxi include href config guest M xml gt zxi include href pod guest O nmL gt cbran name pman ma
21. mc Rg US Tx 47 y m Of TM Artar Corse Vasa 1 meae Mage Pistons w Factus Dor Qonyarpa Enga Mey 2UAMNTMOS mew tole ed s Ferca karwaccnykutu Wa ord o eve nene Te ery Mapa watak CXII Sorter ore Ya 1 Event A Counter 1 Event H Event Z Counter n Scenario A scenario is a CONTAINER of GOOD scenario would count and combine using metrics all of the information required to e required counters measure something useful such as cache key events for a measurement misses or buffer overflows counter lt gt event connections metrics metric is a math equation of captured event counts o lt etter vee O Mapa Pre egy Eon rot POS Powel e 60 mec Orel Gowen Sahara Pur and cae mc Re O freescale TM Artar Sechs vn3tuct faen morum Magn VIC tT Puy SUAM VOS Sewer uto ni Vyara terana of karwa IOS OF a AA was vd eet Here Scenarios Tool measures cache accesses Expected Results Selected scenario bw fet ls Pe removes cnn X A captures overall amp sili Evert Rate Summary per second sil Evam Rate Summary per second traffic a
22. files used in the creation of a bootstrap typically to either Linux or another OS Installs as an Eclipse update package under 20 eupports configuration complexity without altering OS Application software Extensible with on chip validation tools freescale Installing Processor Expert for QoriQ You need either CodeWarrior for PA 10 1 or later OR you download an Eclipse version for free OR you use an existing Eclipse workbench you have installed Wind River QNX GNU etc Processor Expert for QorlQ Configuration Suite installs using the Eclipse updater s Add new software capability The Configuration Suite is 100 pure Java so it should run on any Eclipse 3 6 1 or later host environment Windows Linux Solaris Mac OS 32 bit 64 bit 4 freescale 10 ERE freescale amupa the Se C 5 Cons TEST Coder Comma CWs the Durg ob adea apa Kota maa 1 Peer Frenos 000 Nos Wa Saloon Serrated ation ow Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Pech Can iG Dorana FICC Creer q SEARTANOS Tree Turiel Y tuni anti be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed wapar iwa 331 1 Sere sedertrc inc
23. Cow GLAS y Va Pws a wt iv vys Wf tre un dt All kawi we Aloe 1 wa T eov v ae 4 freescale DPAA Configuration Lab 6 Using Data Patt rap Poneto thw oun Cong TES T Coder Cotten the freerge w W wa t od aan api wiki POS Perr LOC Anr Far oa Cowen Sale oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc DPAA Hands on Problem Statement Receive 1GE traffic on first FMAN Split incoming traffic in IP frames and others Frames with specified IP source are directed in specified FQIDs and then in SW Portal 0 rames IP src 32 xx xx 32 EN FQID 0x2B IP src 48 48 48 48 mE FQID 0x2C FQID 0x2D 0x2D IP src 16 16 16 16 Other IPs FQID 0x2E 0x2E FQID 0x2F 2 FQID 0x20 MAC dst 0 7 76 MAC dst 55 55 55 xx xx xx rames 4 freescale 147 DPAA Hands on QCS Solution Build PCD configuration according to hands on requirements Additional 1 FQ ranges and 1 FMa
24. Zoom 100 Selection 644 547 o Te reca wo DE Code TET Cera Con mms Carn Pe Energy Dont Soka 3o eet e 1 50 cece Caper Qel Guna Gales Ta Sarge Rywremy ai a cadens z Preece baraconckumtar mc Rep US Tx OF O freescale TM Deets wasta Cost Magn Prior 4 Por aqa Ocnverge Erpa Mey 2UAIT VOS eww tob nt Ver sS Na mcoadura Wo Al of OF erat X111 The Graphing Palette e Policy establishes the order of distribution e Distribution sorts incoming frames Classification defines the classification and software portal Policer allows enforcement Frame Queue s Software Portals amp Channels e Link between objects y di plow 1 151 orl G e l k t rw we ne A y wa Py 1 wwe Wt eat Bal 1 2 4 2 freescale Add a Set of Frame Queues 1 QMan configuration 1 Adda FQIDs range FQR1 for enqueued frames and configure FQld 1 and count 200 2 Switch to QMan tab and make the following settings Total FQIDs 150000 Fqd Pfdr mem partitionzPrimary DDR non cacheable B Crea pape 13
25. 76 Caper Coruna Ts Gotten Sy vore and av ades ot Preece Zereconmdurm mc Beg US Pe OF Pon tct en Mae wa wet T Jar 9 Pepe Mwy MAX Uu Lot Vy ma tt lt teers Heec Y te POLS wa Te W Tet ap i Con 2 freescale Missio Jn I E 17 GT i An I LAT AION HEATET TELE SP UT ye sty Dy Gregory s Freescale i Login Annotate this Page s Browse matory tty Recommendations Freescaw gt Processor Esperi ana EmbesS ed Comgonents Ara atie Eemedden Components QORX SUITE Processor Expert for QoriQ Configuration Suite Documentation Te 2042 Configuration Suite is designed to simplify the cnnfigura amp on of our most Compile and powerful devices Tha configuration suite a eet of tools for comfiguring the Oona to s known working state trom silicon reset to avoid the typical hoard bring up issues hal exist i mast complex aoppiicstons wm custom hardware designs This sufe of 0015 implemented as a set of components sach of which mows he of the silicon control registers configuration speciics muang rules and Me necessary value ranges for all the confiyuraton properties Leveraging Processor Expert technology a framework for these embedded componen
26. Protocol header fields O Non header field Available protocol fields mt E vlan amp lic_snap E mpls E 4 E ipv Go tcp E udp qu Fw mp tage 111 Pre Lov tele t 35 Se rew 158 roce Orel Corona Sa Ts Aaa Sus mu r A 11 a fe r k e TM Sett Push Cow wn Mae w a rwn gu 2 i denmvwys UW Epa Hi w 4r Hee Y ote ots 2 Te tw Establish 3 Classification Paths 1 Link ipv4 src classification to ethernet dst classification 2 Draw 3 links from ipv4 src classification to FQIDs1 1 i 30 30 Za 1 1 ethernet ds N 2 T 4 2 freescale Configure ipv4 src Classification Entries 1 Select the ipv4 src classification 2 Qo to the Entries tab in Property Panel 3 Set ethernet dst Classification2 on miss entry Properties Classification Classification Entries IP Fragmentation Entries Destination Condition Action IP Fragmentation FQR 1 on hit Enqueue Mane OManiFOR 1 on hit Enqueue None OManiFOR 1 on hit Enqueue None Classification Classification on miss Goto Classification Man an miss Add drop entry 4 To FQIDs1 1 Data Ox20EEEE20 Mask FFOOOOFF Queue base 0000002B 2 Dataz0x30303030 Mask FFFFFFFF Queue basez00000
27. Workflow Generate Code Create Project Configure Component tree Cond pem aee or del mlt tomen mi imper piScd 42 Pf Devicn Tree Tree ioe 1 ds Cer whe aa pa rrt CIF caa SATE Oe OF 1 gt ete fom espa eee amp cul Po IX Dele node Renere nodi pun ss Cu 3 eo aves qui Fo Refresh wu ane mt c deb bree fhe Mr Hm t E ous Fp 2 po FE Celadt domm tren om YS n a 41 2 7 1 j OP DON 200 E LUCI tnu Pu 1 Colspse del 5 Teef bmnsreportaismittacono00 wre lt gna portaegra2ono00 reg 000000 it 1 we ba aa k shil aat W ren j wee 77 Select v Validate C C ile DTS UIT n bash P CET dtc f b 0 p R 8 I dts o dtb i cts YU nun gt wm Wawa The seton ete geve 4 r me em t Denm to cpi Gana n t mc Cate w II DIT puni Feweifi attciwes Temm Tree nhe Peper ted T bpmencctated On ono mu 4d he X t annor eo 4 42 s Urs O
28. ope eon win Buffer Poot K C20 Frame Status Command OO Frame Formar c La tingle offer empir Frame ofhet gt Oxi 2 2 SITA 129 fame DOA 148 Frame Partition ID Owe Address On268cabco 1 UTTITITYTTTY TT an atr b mn NH a ierit te Pee I a for iM TSECS Ro wate n 1 in 4 je b e e gt gt EI gt Trace Polte Decoded Trace Configuration Notes The data is automatically displayed after collection To see previously collected data double click on the project you want fre ge Wi OE Code TEXT Cnet ire Coro pa P Pont Soka 35 Sete POL 70 Caper Gowen Sete and Vora armada ot Preece Derecomdote mc Hep US Tx 47 OF ole Artar Cors Yawa 1 Mage Gort Cheever mew uto nt ad aw yayuna Wa ote rod 4 suyus Py W Tues Sete wak X111 moira Va Data Flows From Trace Data Frame Processing Stages e Paket Anayss aw 8 L gt Me Meswre Restore Down 2 a Performa onfig T mestamp Decode Only Asin Processing Path Angiysi
29. Ne Extensible suite of tools with a common user interface Consolidate into a common tools framework Processor Expert Provide new device support aligned with silicon roadmap Add more configuration tools over time customers to add their own configuration tools to extend what we offer freescale QoriQ Configuration Suite Now Available QorlQ Configuration Suite v2 3 x is NOW AVAILABLE Supports all QorlQ and Qorivva devices Works with Eclipse 3 6 Eclipse 3 7 development tools Pure Java solution for maximum choice of host system support Add in to CodeWarrior Development Studio for PA v10 1 or later Available from www freescale com QCS FREE DOWNLOAD Includes the following configuration tools all designed to collaborate on consistent configuration PBL tool to define the Reset Control Word bit values and PBI data for the pre boot BOOTROM generator for those QorlQ without RCW functionality DDR configuration supports setting the controller to a working state for any DDR Data path graphical view helps to define data path configuration for the DPAA Hardware Device Tree editor supports references synchronous GUI and XML editing node validation based on specification bindings Packaged as a separate product with installer and wizard functionality Must be a QorlQ customer or under QorlQ NDA for download permission Actual URL is http www freescale com webapp sps sit
30. Pudor erc OCC Mey mw amont tmm ma we aro DeC Y At ore DOORS 4 owe eb Te E Tw X111 wee ere Vua BOOTROM Configuration tool Power on Reset POR configuration signal value binary value obo represents a signal pulled down to GND and a value 0b1 represents a signal pulled up to Vdd regardless of the sense of the functional signal name on the signal Configur ation flle data structure including control and configuration words two parts that needs to be put together with user s code typically u boot image to create booting image for a device Address Reserved BOOT signature Control Words structure 0x44 0x47 Reserved m Ox4C Ox4F Reserved 0x50 0x53 Source Address Config Address 1 Config Data 1 Contig Address 2 omi Data 2 0x54 0x57 Reserved MOSQ Target Address E Contig Dela N 0x60 0x63 Execution Starting Address Configuration Words structure Reserved Config Existing U Boot image 0x68 0x6B Number of Address Data pairs Reserved ey 4 2 freescale a pc Pq USS 4 Cheever Ege Pwy mw uolo tmd BOOTROM Hands on e Step 1 Create configuration project for the P2020 device e Step 2 Use BOOTROM tool to review amp change settings Details Change CCB and core clocking 600 900 MHz e I O port config
31. freescale Tool Introduction AM 11020 W August 2013 Procl Stee C 5 Cons TEST Coder Cotten Comma the Perg aod dean POS Foetus aper hos Saee Wa Serrated ation ow of mede Im Beg uS fur amp To Oft futur Maqay vir uter ina Poche Qui Dorana OUICC Crgine Pay uq ALLENS Tree Turiel Y tuni anii Sree dera of Serer padder Cae bin Hoe ed wapartwa warwa 20 Peace Sem sedertre Inc Promise Before you leave today you will Understand why configuration tools will help you Understand some other tools for optimizing QorlQ devices Configuration Tools specifically Have undergone a basic walkthrough of the tools Used actual configurations and modified them based on requests to configure RCW pre boot loader settings ri BOOTROM P1 P2 devices without RCW use this tool DDR memory controller settings Device Trees Linuxe hardware device tree settings Data Path graphs configuring the DPAA Know where to get more information e 4 em mp tmn Cues lb R Coro Cpa P E yy Tor 5 eet e r Pv CL 2 Caper Qe Cor
32. Configuration 2 Project Importer Device Tree Eat Tutorials EE Go Select the tool data imature and power on reset configuration of PLPG devw fw yaaa kuqa C 8 Cedo TET Ceti ira Co mms Pe Don okra go est POD Peewee Corona Ta Gotten uae Sy mprem and were ot F wawcate mc Re US Tx Ere OF 2 TM 99 Atar festo 4 Gort Py SMAPS mw molo yi 4 wa adero Wo Al OF eu a nee Te erat X111 Sor er r A we Lev vg AU d w w ud Made wr w9 ef 4 Pv www 1 ver v 4 a uw Component Inspector Ye gt ote wr ove ttt yee t 40 42244254 44 00000000 4 00080000 40 900000000 50100001000 54100000000 58 11200000 90000060 00 1107f000 mat Io o T usa as ua Gesa 64 00000000 pill 1222 68 00000010 LII Ciock FLL settings fcr 11 Clock SYSCLE Batic ofg sys pii cfg sys pli 2 tt 11 0 702110 4 43000000 85 fTfT702000 2 2 7020
33. fin densa Preece mc US Tx 67 OF 142 Caper Gowen Sy vore and V 7 Pon tct Mage Pater w 4 Pep Seri Py molo y SEL we taro Doan A o GA 4 Q wa Te NOV Sete eret X111 Daraa Fr Device Tree Step 4 P4040 Device Tree 13 Goto Search menu select Device Tree Search tab gt enter cous text gt press Search 14 n Search view select the found matches associated with the generated file device tree has 4 cores and looks as follows p eerch CiC Search 7 Tree Search uva Search 7 Search Conkwring bet cud w Case sendive ay string any characte escape for 7 9 Regue expression Fis name patterns Patterns ore pared by 0 comme any string 7 w eris yw SS Component Inspector 23 Basic Advanced Expert lg C P4080 v2 0 5 x ELI on HWDeviceTree Properties 96 gt Workspace Selected resources eg vals gc cpus 1 set 5 device tree address cells lt 0 1 gt a Mame 0 PowerPC 40606 size cells 0x0 aliases Parent cpus i cpus Properties 3 TER 9
34. mc Rep US Tx CO festo Cose m www Magee Petters w 4 Fut Toad Py SMAI MOS umo na yi w4 we be errs kain Wa Gw ORS eoe ge Te ON TV Tus Sete X111 aec ucu Va Device Tree Step 1 Create New Project cont 1 Steps File gt New gt QorlQ Configuration Project enter Project name Next select SoC p4080 v2 0 Next select Device Trees component gt Next browse to an existing p4080ds dts file gt Finish 2 Wait while the device tree component is updating with the imported data 3 Expand ProcessorExpert pe gt Embedded Components gt click on DT1 HWDevice I ree component 4 The imported dts file is added under mported Files folder 5 Open generated device tree file Generated_Code P4080_v2_0 dts At this moment the imported dts and the generated one are identical 4 Device Tree Step 2 Remove Unnecessary Nodes 6 Search for CPU nodes the tree view you should see 8 cores with properties each 7 Delete cpu4 cpu you have two options Using graphical editor OR Using text editor Component Inspector ETT HwDeviceTree 5 device tree aliases cpus EH cpu0 PowerPC 4080 0 E cpul PowerPC 4080 1 E cpu2 PowerPC 4080 2 E cpu3 PowerPC 408063 a mem Se Insert node E cpu7 Delete node
35. root P1020RDB cd boot formal root P1020RDB boot format Is I rwxr xr x 1 root root 10400 Apr 7 2010 boot format J Peon FOOL 220 7 2040 Contig Sramsdat The utility shows how to use it when typing boot format Usage boot format config file image sd dev o out config spi spiimage config file includes boot signature and config words 1mage the U Boot image for booting from eSDHC eSPI dev SDCard s device node e g dev sdb dev mmcb1k0 Spiimage boot image for SPI mode out config modified config file for SD mode BOOTROM tool generated config file can be used together with U Boot image and put on an SD MMC card using command line e g for dev mmcbIkO boot format BOOTROMI Boot Contig dat u boot brin dev mmcblLlkO f pote ten Ar j wheter L U Bee IP Er yy for S k t 1v med MIC 1 106 Caper Gowen Etin ta Sy vore and av ot Preece Deccan mc Reg x Magn vec y amp Gert em m Q CC Ev Mwy SMa ioe Yy tt lt 2 ha tL Y AZ On POLS lt wh Te W Tw wa ive r 4 gt d freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LO
36. Component Component Configuration Tools DDR Peripheral Ini db PBL Peripheral Ini wm y AA h Pp Coe res Cpa P Er yy Or Sobre t eet m medir Powe ice 122 Caper Corona Ta Satanas Sy orem and Vora av cadens ot Preece Zerecondurm mc Beg US Tx amp 7 C TM Det Coste e Mage 4 DC Pwy molo ym 4 4r lt teers Veo VW QU of we ORS OF e Te Seapets erat CXII G 5 4 DDR Step 3 Review Decoded Configurations Advanced Expert lp Component Inspector x Properties Import Export Name Value Details hr Device DDR Controller 1 DDR Controller 1 Memory type DDR DDR Bus Clock 667 MHz DDR Data Rate 1334 MT s Type of DIMM Unbuffered DIMMs Bus mode 64 bit bus SDRAM Control Configuration Control Configuration 1 SDRAM self refresh during Enabled E ECC Error Checking and Enabled 000 Dynamic power manager Disabled Beat burst mode 8 beat burst Timing mode 1T Timing Concurent auto precharg Enabled Control Configuration 2 DLL Reset no 005 Configuration Use differential DOS signals ODT Configuration Assert ODT to internal 105 only dur Number of posted refresh 1 refresh is issued at a ti
37. Esqueue Command Depatched trece event RestOcat on wet ngaue operaponm wat fot Buffer Pool 1D 020 Frame StatuCommatd gt Fearne Format Ox bert tingle butler 080 128 tame tengo 0994 140 Frame part on ID Addens gt 5 bus Tag 1 Chani lt O21 Softwiee Qvi Dequeve trace event Order not espe wa ot fected Bufier Pool 0 Cad Sieus Ow Frame Format lt Ou hort single buffer smple Frame offset gt Ou BO 27 18533519108 1855519195 s Sa Port 8 1241 length sma pa EOD PAI BM masa ERE PN Prepare e 1 te 2000000 t s 222809004065 tame gt 4 Verbos mode Debug Tag gt OxLic Channel Duct conet portal Qvo FM Exqueue COMMAS hace event Ceder Retrato wat 185551780290 5 not spected at Enqueve operation was not rejected Suffer Pool ID gt 0420 frame StatuComemaed Ou rame Format gt 0 butter wrote fame GIA OHO 126 lt 004 146 Frame ID gt Our OOo J z Verc mode Det Tag 1 AJID lt Channel 2921 Software portal 0 9 Dequewe trace event Cider Restoration mas not at enqueue 32 18553780132
38. Se C 5 Cons TEST Coder Comma CWs the Durg ob adea apa Kota maa 1 Peer Frenos 000 Nos Wa Saloon Serrated ation ow Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Pech Can iG Dorana FICC Creer q SEARTANOS Tree Turiel Y tuni anti be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed wapar iwa 331 1 Sere sedertrc inc QoriQ Optimization Suite Processor Expert QoriQ Optimization Suite Scenarios Tool DDRv Tool E ue Lio D 4 P 4 Pw Fee He Aw Cra Cp IP Eon t evt PO Pes AEC 44 Caper Corona Te Satanas Symone and are were ot Preece mc Rep US Tx OF TM Atar Vasa Mage v Piga Gort Piy mw umo tm w rod 4 awa ery Tus ete eret X111 Saeco moro What is the PEx Optimization Suite new generation of products aimed at allowing customers to solve systems
39. fsleUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 O00B images boot p4080ds R PPSXN 0 10 s g Ow cenet Ae ar Pise ut ra re 3 X v Sq 91 lt a gt Xu G 2 uw us JA wea A o pe I e TM rta tet e tw ne am va Pater 4 wet eri Donwys E en wy TVA y baron of d kawa wo aros OR 4 eive wt 1 51 Pre boot L SGMII oader Step 8 Change Serdes for 2 x 4 e Starting from previous Ox10 5g rev2 high bin txt config let s adapt Serdes protocol configuration to allow 2x4 SGMII S Component Inspector x Basic Advanced Expert hh m Properties Import Mame Description RCW Source PLL Configuration E SerBbes PLL and Protocol Configuration SerDes Reference Clocks SRDS_EN 178 SRDS PRTCL 128 133 5805 RATIO Bl 136 138 SerDes PLL 1 Clock SRDS DIV B1 139 143 SRDS DIV B1 Lanes A B 139 SRDS DIV B1 LanesC D 140 SRDS DIV Bi LanesE F 141 SRDS DIV Bl Lanes GIH 142 SRDS DIV Bl Lanes 1 1 143 SRDS RATIO B 144 146 SerDes PLL 2 Clock SRDS DIv B2 147 SRDS RATIO B3 148 150 SerDes PLL 3 Clock SRDS DIV B3 151 SRDS LPD 152 161 SRDS LPD Bi Lane A 152 SRDS LPD Bi LaneB 153 si 2 freescale 5805 PRTCL 128 133 SRDS PRTCL Bank3 le
40. memory Rename node bman porta qman porta eo Refresh soc soc Ff 0 Expand localbus fF Collapse 0 pcie r 1 pcie ffe201000 pci2 pcie ffe202000 Fsl dpaa LLL Select all 4 nodes and press delete To reflect the modifications in the graphical editor too save the file Ctrl S Delete one node at a time After each deletion dts file is automatically generated Pw Aw Cra Conv Cn IP Tory Sete Powe AIL Caper Coruna ta Satanas Sy orem and Yorn av were ot F wawcate Zerecosdurm mc Beg US Tx amp 7 OF Ly TM 141 Artar fest Cose f n uwa Migr Paiga Goeverge Erpa Tan Py 4 beers Wa Kt p Oz 4 eov wa Te Oy W Tus Aart CXII Amira Yu Device Tree Step 3 Solve Validation Errors 8 Look in the Properties view There are 8 errors 9 Click on each error and go to the corresponding line in the device tree file 48 P4080 v2 O dts 32 185 bman portal8iO0O000 i i 186 cell index 0x4 10 There are undefined references In 197 compatible fsi p4060 bman portali fsi bman portal Some nodes pointing to the removed 188 reg lt 0 10000 0 4000 0 104000 0 1000 gt 6 159 cpu handle lt e
41. portal device node that has children in the device tree hierarchy and describes how child device nodes should be addressed It defines the number of v lt u32 gt cells used to encode the size field in a child w node s reg property If missing a client program sa gt should assume a default value of 1 Mesi Ge Rot quon ipi Roten aa ag UA ON 27 Artar Corer Vasa Lyran Migr 0 hort arp Py mw yore Device trees inclusion The Include tree allows easy navigation among device tree fragments dts dtsi Hovering support for properties and nodes a tool tip appears displaying their initial locations Hyperlink detection for include declarations and device tree references Ctrl left click Cormponerr Faeto wDewoeT des EGON des zt 5 502155 dies 2 11 bmen portmi81 000 b SCC pre dei s node is defined im 550 power is dea QSD dtu a 55 pS0209 post 4541 20 aris bon hu bre 74 anno man portas aw le sonda di ine 57 Gore gran i portats ams Gone rege Lass DTIHW Derice Tree des puedas wr ku des compatible f21 taan portel garni 0 82 reg 12000 UK OL Ix 10 3 qon esdee 0
42. 80010 6 1 cfg_sys_pll cfg_sys_pll cfg sys 11 DOR Complex Clock PLL Ratio settings for informstion only et DOR Complex O0RCLK Ratio et es 2 freescale 4 1 ddr pil 0 2 400 000 06001 41 WP i 1k ddr 0 2 00001 4 1 POR Signa Valve Pin location a cfg ddr 211 6 2 ddr pil O obo TSEC 1588 OUT ee 0001 4 1 dar pu 1 050 TSEC 1588 PULSE QUT T VOTE fg ddr pil 6 oe X Tc 138 TES cfg ddr p v ddr 2 TSEC 1588 PULSE dd cfg ddr pll 1 00 TSEC 1588 PULSE OUTI cfg dd 11 2 dbi TSEC 1588 PuLSf OUT 500 Core Clock PLL Ratio settings for information only UN 770 e500 Core CCB Clock Ratio Cored 32 Core 32 Core 900 000 MHz Core1 900 000 er rr e500 Core Clock PLL Ratio settings for information only e560 Core CCB Clock Ratio a Cored 5 2 Corel 5 2 a Coret 999 000 Mtz Corel 900 000 nz AN wo C 5 Cedo TEX Coro pa P Port net POD Peewee 1 03 Scene Caper Coruna Te Satanas and ot Preece Zenecondotae mc Rep US Tx OF festo Vas my www Magee w 4 Facts Der Py molo yi we
43. 96 99 Core PLL Clock C1 PLL SEL 100 103 Core 1 PLL Clock C2 PLL SEL 104 107 Core 2 PLL Clock C3 SEL 108 111 Core 3 PLL Clock PLL SEL 112 115 Core 4 PLL Clock C5 PLL 5EL 116 119 Core 5 PLL Clock SEL 120 123 Core 6 PLL Clock C PLL SEL 124 127 Core 7 PLL Clock Clock FMz Clack 2 freescale Value 100 000 MHz obO1000 8 1 100 000 MHz Ob01 Higher Frequency reference clock 0601100 12 1 async mode only 80 6 MHz cutoff 600 000 MHz ObO000 CC1 PLL 1 1 200 GHz ObOOOO Cc1 PLL 1 1 200 GHz ObOO00 Cei PLL 71 1 200 GHz oboo CC1 PLL f1 1 200 GHz 061100 CC4 PLL 1 1 200 GHz 061100 CC4 PLL 1 1 200 GHz 061100 CC4 PLL 11 1 200 GHz 061100 CC4 PLL 1 1 200 GHz 450 000 MHz 450 000 MHz Platform Fregfsystem PLL targeting 667 MHz and above operation 87 Basic Advanced Expert I 7 hanging the ratio to 8 1 makes platform clock 800 MHz 600 Mhz 2 800 Mhz Details i emor Controller Complex PLL settings And also changes the LBC and PME clocks fw yakuq kuqa Aw C 5 Cedo TET Oant Cee ire Comes Caa Pe Energy 3o net vata t POD Peewee Caper Gerona Ta Getter ai av cadena ot Preece Zarecondute mc Rep US Tx 7 OF Atar festo
44. Defeat tec eeoback a AG rait an et Dent Merwe Foou Pool urbe of buffer BE Pigs 2 03 11i Buffe mafa sum Buffer Cure ke sigriet 47 2 AN wo C 5 Cedo TET Cra Con mmo Stee P Port Peewee Qe Corona ta Aaa Sy vorem and Vora av adea ot Preece mc Heg US Tx OF Atar festo Vas Um www Magee Prior w 4 Pa Der EOC Py molo Vz we rod nene wa Te ery W Tus Sete watak X111 Va Properties Panel 3 gt Graphing Palette zy io 4c Basic Advanced Expert I moe FMan Port BMan QOmu Frame Manager Port nf FLD Rx Port Port name Error FQ Id Frame Man ager MaCaddess is 8 B en Ra P O rt S HODNOfSet at Speed m N Loopback 17x Port C use IRO EmoFOld Frame Buffer Pools Selecting an item on the graphing panel and double click gets you the ZZ Force Buffer Pool Id properties for that object feral f Buffer context mode Buffer size Resizable 8 C rO a e e V e W Add Cache line alignment I
45. From memory data DDR Configuration Configured device P2020 sheet congue Maximum speed rating Auto configuration Import from memory file Capacity Discrete DRAM 2 DRAM Module Configuration mode DDR Controller DRAM Settings Type Data Rate Ranks Data Bus width 5 Latency 6 clocks tRP tRCD 135ns v ECC Enabled Select 1st DDR Controller 17 Caper ta Satanas Sy vore and Vora Freeecate Zenecomdctaen mc US te 87 Pon Agi v V tuqu Dore EOC Enga Py umo Yorn ec TM Iu och Custer Hewes Mgr yt i wy x Thea f gt 4 4r lt teers Veo VW A4 Ow DOLES wa Te Ty W Tw Rev vetat XIII ees QCS project explorer Component x Properties E zm m l p2020rdb pcal Mame Value Details t gt Documentation Device DDR Controller 1 DDR Controller 1 t la Generated Cade Memory type DDR DDR Bus Clock 400 MHz DDR Data Rate 800 MT s Ry ProcessorExpert pe MA E Type of DIMM Unbuffered DIMMs Configurations Bus mode 64 brt bus P2020 Cnf Operating System a Processors gt SoC P2020 SDRAM Control Configuration 5 Control Configuration 1 gt Control Configuration 2 t SDRAM T
46. Sy vorenm and av cadena ot Preece Deaconan mc Beg US Tx OF Atar festo Vas my www Magee Prior w 4 Der EOC Py 4 wa be ewes Wa KU OF ww wa Te M Ty Aart X111 x H Properties Import MEM PLL CF 8 9 MEM PLL RAT 10 14 DDR PLL Output Clock E Core Clusters PLL PLL CFG 64 65 CCL PLL RAT 66 70 Core Cluster 1 PLL Clock Cc CFG 72 73 CC PLL RAT 74 78 Core Cluster 2 PLL Clock PLL CFG 80 81 82 86 CC4 PLL CFG 88 89 RAT 90 94 Core Cluster 4 PLL Clock Core Complexes PLL E Other PLL LBC Clock PME Clock SerDes PLL SerDes PLL and Protocol Config 3j Misc PLL Related Configuratior DDR SYNC 184 Boot Configuration Clocking Configuration PME CLK SEL 224 CLK SEL 225 2 SEL 226 DRAM LAT 230 231 DDR RATE 232 ac noa o Memory Controller Complex 4 Value Details ObO1 Higher Frequency reference cl S et DbO1101 13 1 async mode only 650 000 MHz CC3 PLL RAT monn dela e to 12 1 to set 1 500 Hz Db c luster PLL 2 output Freq Frame Manager 1 500 GHz Core
47. Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc DPAA Overview DPAA Data Path Acceleration Architecture provides the infrastructure to pass packets to from cores Network hardware accelerators and network interfaces Interfaces The architecture contains several hardware components Frame Manager FM Buffer Manager BM Queue Manager gm Hal 8006 ratore security SEC Pattern Matching Engine Policing Each hardware component is performing specific operations on the incoming outgoing frames BM Manages data storage buffer pools Is a shared resource among cores network interfaces and HW accelerators FM supports in line off line packet parsing and initial classification It enables policing and flow and QoS based packet distribution to the cores QM Manages the queuing of data between cores network interfaces and HW accelerators SEC provides cryptographic acceleration PME high performance hardware pattern matching functionality 4 Cw CS Cod lb LAF re Cpa P Er ny tort evt m r Pex P Am T Caper Cowen Lamia Byron and Vora av adden cot Preece DZerecondctm mc Reg US Tx 67 OF TM or eon V D
48. fEF20000 80010000 enable S12 Ebyte of SRAM Soped by CPU data cache Sample L2 SRAM us supported only for Boot ROM Data Configura CO ratio n parameters fw kuqa Aw C 8 sit C vei ire Oo rv twee P ery Dont eet AOD ww ANC I Exper Coe Corona Ta Getter Sy mprenm and av arada ot F wawcate mc Re US Tx amp OF Atar festo my www Mage Prior Gort Ege Py molo yi and wa adero La mcoadura Al OF eoe nae Te q Tw erat X111 Serer ore BOOTROM Step 5 Usage of configuration data file with external booting utility application B Bo x W gt 48 42144154 Control Words b 64 00000000 66 86600006 86 TT720100 54 f8f 8o0000 88 T1720e44 9p f720008 94 80010000 Tf72e48c ac 86804 49000001 a4 86008160 ac 2 e 4 2 freescale Use a booting utility boot format from a BSP package for P2020RDB P102RDB Once you have installed BSP and let configured Itib to build root file system rootfs tar gz uboot for Linux boot Boot the board using this root file system and boot format utility can be located under
49. wa adero Al OF ove Te erat X111 Properties Name Device 4 Power On Reset Configuration 4 PLL Configuration 4 CCB Clock SYSCLK Ratio cfg sys pll 0 2 4 DDR Complex DDRCLK Ratio cfg ddr pill 0 2 a e500 Core CCB Clock Ratio cfg core pll 0 2 cfg corel pll 0 2 5 Device Status 4 SerDes Configuration 4 SerDes Reference Clock cfg srds refclk 4 SerDes PLL Time out cfg srds pll toe a VO Port Selection cfg io ports 0 3 4 Boot Configuration 4 Boot ROM Location cfg rom loc 0 3 4 Boot Sequencer Configuration cfg boot seq 0 1 4 CPU Boot Configuration cfg boot cfg cpul boot gt High Speed VO Configuri gt General Purpose POR gt Engineering Use POR 4 Pin Multiplexing Configuration 4 eTSECI Configuration cfg tsec reduce tsecl prtcl 0 1 eTSEC2 Configuration cfg sgmii2 eTSEC3 Configuration cfg sgmii3 gt Miscellaneous Configuration 4 Boot ROM Data Confiquration 2 freescale Value BOOTROM 6 1 Details BOOTROM 0b010 6 Changing 01070 41 0001 location start Corel booting from SD 0 011 3 ard 060 SerDes reference clock 125 M Pins TSEC 1588 ALARM Obl Disable PLL lock time out co Pins TRIG OUT Ob1101 PCIe 1 x1 gt SerDes lan 061111 Local b C
50. wt 4 wt eX iem DLC prn Mwy 2 NM wr 4 aderat La mcondkta Wa 4 eov wa Te Tus Aart CXII Amira re QCS DPAA Component Overview Flowchart representation of DPAA component is a software solution intended to ease creation of complex 5 DPAA configurations t TS Have an intuitive graphical representation gt Easy to understand the overall dud architecture as well as individual DPAA components QCS integrated component designed to iz puel ease DPAA configuration for QorlQ iru devices Interactive and user friendly interface in i order to provide the best user experience Allows customers to easily translate i their own data flow into a valid driver GE configuration Designed to deal with complex DPAA user scenarios 4 2 freescale a cemil versions LO encodings utf 2 mins aia htp www w3 0ng 2001 XIndude cfadata canfur pine nares hen gt port 1G nmumbere 0 policy L2TPv3 port IG numbers 3 policy 0 lt engina gt engine names Ten 1 jconf gt cfgdata lt bean name brnan maste portale lt binportal id lt 0 irg false tenportal id 3 vg Talse
51. 00 0 00 0x30014202 define PEX CONFIG DDR1 INIT EXT ADDR define PEX CONFIG DDR1 TIMING 4 define FEX CONFIG DDR1 TIMING 5 define PEX CONFIG DDR1 ZQ define PEX CONFIG DDR1 WRLVL CNIL define PEX CONFIG DDR1 RCW 1 DDR Controller 1 configuration global structures define PEX CONFIG DDR1 RCW 2 ddr cig regs t ddr regs i1 ca 0 bnds cs 1 bnds c8 2 bnds cs 3 bnds 0 config 1 config CS 2 config PEX CONFIG DDR1 CSO BNDS PEX CONFIG DDR1 CS1 BNDS PEX CONFIG DDR1 CS2 BNDS PEX CONFIG DDR1 CS3 BNDS Ox00000000 0200220001 0202401400 0x89080600 x8655F614 0 00000000 ox00000000 PEX CONFIG DDR1 50 CONFIG PEX CONFIG DDR1 CS1 CONFIG PEX CONFIG DDR1 C52 CONFIG 4 2 freescale freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Hardware Device
52. 0x30014202 define PEX CONFIG DDR1 INIT EXT ADDR define PEX CONFIG DDR1 TIMING 4 define FEX CONFIG DDR1 TIMING 5 define PEX CONFIG DDR1 ZQ define PEX CONFIG DDR1 WRLVL CNIL define PEX CONFIG DDR1 RCW 1 DDR Controller 1 configuration global structures define PEX CONFIG DDR1 RCW 2 ddr cig regs t ddr regs i1 ca 0 bnds cs 1 bnds c8 2 bnds cs 3 bnds 0 config 1 config CS 2 config PEX CONFIG DDR1 CSO BNDS PEX CONFIG DDR1 CS1 BNDS PEX CONFIG DDR1 CS2 BNDS PEX CONFIG DDR1 CS3 BNDS Ox00000000 0200220001 0202401400 0x89080600 x8655F614 0 00000000 ox00000000 PEX CONFIG DDR1 50 CONFIG PEX CONFIG DDR1 CS1 CONFIG PEX CONFIG DDR1 C52 CONFIG 4 2 freescale Steps to adapt DDR configuration file in CodeWarrior Open the CW config file you want to adapt D Program Files Freescale CW PA v10 1 PA PA_Support Initialization_Files QorlQ_ P4080DS_init_core0 cfg Replace DDH1 config section with the one from D Profiles o08844 workspace p4080 Generated_Code ddrCtrl 1 cfg Use this new config file with your stationary project 4 freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette o
53. CL 13 DDR3 1866 107 Fixed burst length BL of 8 and burst chop BC of 4 125ns 6 CL 11 CDDR3 1600 125 vin the moue register set IMRS L5ns6 CL 9 DDR3 1333 15E Sutoctabie BUA or BLA Gn the Ry OTF 1 9705 CL 7 DDR3 1066 1871 Self refresh mode Operating temperature Fook OC 095 Commercial 0 C Tc 95 C None 541115 8192 cycle refresh at 0 C to 85 C Industrial 40 C lt Te lt 498 C 8192 cycle refresh at 45 to 95 e Revision I Self refresh temperature SRT e Write leveling Multipurpose register Note 1 Not all options listed can be combined to Output driver calibration define an offered product Use the part catalog search on http www micron com for available offerings Pu tm ote lE Y Cy Coh ros Can P Por Sok net m medi 24 Powe ict Caper Corwen betes ta Gotten logo Sy vore and av were ot Preece mc Rep US Tx amp 7 OF e TM 1 6 Artar Corse Pun yeme Mag v Facius Gort Ege Py SMAPS mw Sol na yd w4 Peete Wa ord 4 eu wa wa Te Thes Sect swak X111 DDR Wizard simplifies configuration 3 New Configuration Project qe 7
54. Communications Processors win Data Path See an EN Featured Documentabon QORIGCSFROCENXUG Processor Exped Users Guide QORIOCSGETSTARTEDUG Configuration Suite Users Guide OORIOCSNSTALLUG installalian Users Current Updates and Releases Gor QCeonfigSunue 3 x Galileo Configuration Sute installer for 25 GonQCconhg3ute 3 6 y Hallos Configuration Siste Installer tor Eciose 3 6 x Hesos mu QM Die 275 Ete Eclipse Compamttiility Ectpse Gaileo 35 0 gt Ecose ieiws 2 63x Development Studis Processor Expert Onermtatan Freescale Technology Forum b Software Meets Silicon Blog by Freescale s sofware experts e tE D Preven fre yatai kuqa Waw OE Cedo TE C apana afra Co roo Wapa 902 Pow 77 Caper Gowen Ta Aarau logs and Voris z Ferca mc Rep US Tx 06 Beets Corse Ln mew Mage VOC 4 Gort OCC Enga Py Aola mmi amd Truc Kamcondusa We dU of oc Aa MPEG what X111 Frenette aqa awa Ya Supporting the Most Sophisticated Customers FUIURE ELECTRONICS CO LTD ADVA OPTICAL NETWORK AEONIUM SERVICES LTD ALCATEL LUCENT ALCATEL LUCENT AG ALVARION ARROW ELECTRONICS
55. Gur Pe 07 kur wu eter mech Custer fwe neum Mae w 4 wet 2 i ma tt NA i NO WOM Y AZ ww gt os aT al EJ eR 22 File Name size Type 8KB CodeWarrior Lin 46 KB C Source File C Header File 6KB C Source File 3KB C Header File SKB C Header File 6KB C Source File 1KB C Header File 26 KB C Source File 7KB CHeader File 11KB C Source File 2KB C Source File 51 1KB w SS amp amp amp DPAA Hands on Usecase Output Report Use a serial terminal to receive usecase output Input frames Frames transmitted by usecase on FMAN port2 5 frames on FMO Port 4 IPV4 UDP VLAN ARP IPVA TCP Output report Frames received are enqueued according to PCD FMO Port1 FQID 45 0x2D FQID 46 0x2E FQID 32 0x20 FQID 32 0x20 FQID 46 0x2E 2 freescale HHHH HetComm Device Drivers THEE AT Version 4 5 HHHH built on Hay 28 2812 Usage gt lt command options argi argH Type For help HCS W gt gt Executing Test DPAA Basic 1 QCS use case gt INFO FH CPUBB E Freescale NetComm Software 4 5 58 5 HetCommSu zPeripheral Code FHan Controller code uer 186 2 2 loaded to IRAN Sending 5 frames on Port 16 Ffml_p2tx from FQR Frame received on Q x2d From FOR FQR1 Frame received on Q x2e from F R FQR1
56. as interrupts 133 gonq uc des 1 qorepoc 1 deu qonaeduest 0 deo bwmen portml1829000 duet 1 9 cell index regen des t ma ila f bmmn portal Qorerusba notro dea reg Dx4O 00 Dy Loar 1060 qoreruibz d 0d interrupts 1 qr tal desi a taqam 4 2 0 bemnsporta1Bl4000D prome G des celi index lt 0 9 gt nclude fsl p50202z1 pre dts1 gore mano k5 compacinije sl DMN portal ta 1600 qor beran dcs in compatible property is defined in qrq man Q des E dts ine 94 mron O La 0 An i model fs1 F5020DB8 compatible 251 PS5020D3 faddress cells kaa zu buffer ceocl90 include 1 Device tree Include tree 12 11 772747 s declaration interrupt parent mpic node ecbernet3 pantti reference ethernet4 w sener4 ethernetsS w saners phy ramii O ibhv romii 2 wv lt 4 28 Exper Gowen Eth Sy vore and Yor ane akawa TM Arter Cursor V neam Mag 4 Pere qu Devt OCC Epa Toad Pwy mw mob om ys 4 rt aro See kawan kutun Y At ore BOBS owe eb Te Ty X111 wea ere Vua Interrupts tree The Interrupts t
57. clo F H Trj B C D des 2 152 568 v 1 10 MALI 105 53 NN cs SRDS PRTCL FM2 dTSEC 3 4 15 5j2 5G 10GEC n ay ae 2 0x10 to 0x16 4 x SGMII Debug at Reserved 1 2 dTSEC 1 4 1 5 2 5 GEC 3 4 SGMII Debug gt 11512 55 2 dTSEC 1 4 1 sRIO 2 sRIO 1 Debug 2 55 2 56 5 2 5 PM 10GEC sRIO 2 sRIO 1 Debug 4 x SGMII 3 125 3 125 1512 55 dTSEC 1 4 sRIO 2 sRIQ 1 Debug 4 x SGMII 3 1254 o 126 o Se dTSEC 1 4 Lad Reserved 1 SerDes Protocol Select Bits 128 133 For additional information see description of the SROS PRTCL Field in device documentation This item modifies SROS_PRTCLS 5RO5_PRTCLO bits in the RCWSRS register Fay raba fee _ Rook 1 Pu 125 79 F3 425 78 TT ta 17E Banke TIII Table 5 SerDes Lane Multiplexing Configuration P4080DS slots as per user manual Pre boot Loader Step 9 Adapt Serdes Clocks S ComponentInspector 22 2 Properties Import Value Detail Description SERDES 8 please refer to the P4080 RCW Source LBC FCM NAND Flash S R O req uires PLL Configuration E Serbes PLL and Protocol Con
58. esn AIr 1 Ormar EA Te Sman Pucca Serre and Yor ane were Fa Decon itr e 9 fr I TM 124 beta abit Cowher fees Mag e 4 wet qu Gor OCC Ev heady Mey ms rere Dd MAK tarea ote IOLA Te 9 serat DDR Step 5 Adapt CW Config File Open the CW config file you want to adapt D Program Files Freescale CW PA v10 1 PA PA_Support Initialization_Files QorlQ P4080DS init core0 tcl Replace DDH1 config section with the one from DAProfilesib08844 Workspace p4080 Generated Code ddrCtrl 1 tcl Use the new config file with your stationary project 4 freescale the Ad C5 Cong TEST Cotton Comma Cu the Durg LW wat ob aan apa Kota makes POS Press Expert eed Cha ux Saee Wa etia of mede ttc onte y _ Rew us fat amp Tn eter Deeta Teu Lyco Vegev Tbe ina Pecha Quel Dorana FICC Crewe Phy Mine S4ARTANOS Turtur Y wni ant Orroit be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed wapar iwa 331 1 Sere sedertri inc 2 This tool is 995 and requires a TAP to be purchased s
59. fot lage Seach Project Run PracemerEmet moos 3 q iz o wm y AA 4 5 Lon Cn Ww Er yy tert Sk pone 1 evt m mmi i 2 4 152 Troc r bap x uma 5 i axur kus mu and Vord a av F1 ECCO mc usa L tar festo Cow Pen ny www Magee VOC Parton w 4 Gort Donya Enga Mwy SMOG mw mole ym ma tt teers HMM Y DOORS 4 owe eb Te eer E Tw Sete X111 wee ere Vua 4 e 1 Add SW PortalO channel 2 Link FQIDs1 to WQO of SW PortalO L pie zio e Fie Edt Newgate Pract u Proceso Expert Window Hao 5 5 orn 2 Dogoem OS oe z w ME T Cs Jy GJ e freescale 153 kuqa Aw Cedo TET Cogeltumor Coh mes Carn P Energy Dont okra 3o tst POD Pewee Exper Coruna Ta Satanas Symone and ane ct Preece Zarecondote mc US Tx OF Artur Ven Um www Mage VEU 4 Paiga Dori Py mw role yi and wu s Fueeca Ka mcondusa Wa ote OF nene wa Te y Mapa CXII
60. gn AN wo C 5 Cedo TET Cra Con Stee P Port go net POL Peewee Caper Corona Eobhan Te Satanas Symone and ane ot Preece mc US Tx OF Atar festo 4 Gort Py SMAPS mw molo yi and beers Wa M Te NP Sete serat CXII Sorter eres Ya Optimal DDR configuration Read ODT Optimal DDR configuration Basic Advanced Expe 3 Component Inspector gt Properties Import Export Validation Choose DDR tests to be executed 3 Test Validation stages Stagel Centering the clock Read ODT and driver Write ODT and driver f Basic Testing DDR Test Test results Controller DRAM 43 ohm 50 ohm 55 ohm 60 ohm 75 ohm 120 ohm 150 ohm controller ODT Tests to be executed can be changed between executions Pattern Write Read Write Compare Walking Ones Walking Zeros P Proceed to next validation step f gn CE Cedo TET Cra Con rms Stee P Port net 970 Peewee Caper Coruna Gotten and av were z Ferca Zanecomdote mc Rep U
61. n Import frome an PEL fhe Use ACW Mard coded configuration Projects A Tutorials type ffer teat DR Vou PPSSN 0510 13g bqht Object Dump Only select the PBL tool for now Select Me to te for importing an existing POL configuration and choose the appropriate fie Format P d fw Aw C ana Comm Cp P Creepy Torn gt 35 Powe 84 Carma kamkuna Satanas logs Syvoraem and Vora ct Percale mc Reg US Tx ETa Ot Atar Coste unm Mage Parton w 4 Py SMO mw molo TM E ad mak Wa oft produc CAA Ma Te V Thes MPEG Anat X111 aqa aswa ine 4 Ss Component Inspector 53 Properties Import Decode Input File Input File D hocs FTFip4 80dslR PPSXM Oxi lrcw 0x10 5g rev2 low bin txt Input Format XXD Object Dump Input data aa55 aa55 010e 0100 4c58 0000 0000 0000 ULU Aus oan 1818 5218 0000 cccc 4046 4000 3c3c 2000 R GF lt lt 80 0000 5100 0000 0000 0000 0000 0000 a 0000 0000 0000 0000 0813 8040 7555 7878 a Guz The content of the file to be imported is displayed x
62. need QCS 2 2 1 or later installed Get it from WWW freescale com qcs Use Eclipse Add new software Eclipse updater capability to install DDRV on top of QCS Use as an update link http freescale com lgfiles updates Eclipse Helios36 DDH Validation for installation over QCS installed over Eclipse 3 6 or CW PA 10 http treescale com lgfiles updates Eclipse Indigo3 DDHR Validation for installation over QCS installed over Eclipse 3 7 DDRV is a licensed product 4 wem whom tan UAY paf am sn Fra Conv 15 w gt j 54 taper G Ts ssa us ut E fre v h ha r M TM rt a 2 Costo ws we relents i woe 12 1 anf Ya 7 dt we bero of karwa we alo 1 wa ae 4 freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Optimization Suite Scenarios Tool
63. type Main Entries Classifcation1 Policyl No Ee Extract I Au Protocol header fields 2 Non header field A Available protocol fields Fass foffset nextp hchecksum ipv6 eI tcp El udp gre J pppoe Extracted protocol fields 4 wem tae fhe ii pal erst Pra T i j 156 5 Ts us tne h be 4 r TM esf Path wn new A y Py Vu taqa Qe ings int MAX M pgs steers im y 4 ave 1 7 4 lt 4 s Link IPv4 Distribution to ipv4 src Classification Mai n S Entries Name Classification 1 Extract Protocol head Non header fie Available protocol fields age mt E ipv teo E udp gre Gh pppoe Extracted protocol fields Ova Src 4 wem Cw y tage 4 6 dett neler w Pre Ue re p ow 157 Caper Gowen ta Aarau B rin TM Cnr wn Mage VOC 4 1 B 251 C haero Feo W ate 1 w s vi Te aio Add a Classification and Extract ethernet dst and remove ethernet type Main Entries Mame Classification2 Policy1 ipv4 ipv4 sr Extract ka assasi
64. wea Serer ores be Define the Parse Classify Distribute Configuration 1 Add a Policy1 to split IP frames traffic and then a link from port FM1 P2 to receive incoming frames 2 Add distribution for IP frames and extract IPv4 protocol then configure QBase 39 Basic IX Distribution x Available protocols Distribution name Distribution 1 ethernet vlan snap gt minencap sctp dccp jpsec ah ipsec esp ES m Bt ME 5 Queue base Queue count P d wem wu Cw tum U he 4 tet re Loe ppi 4 amp 3o Som ree EC 1 154 lt lt Corl Ge dehin Ts Xam Vor A 21 te itr e TM 7 Pouch Cow wn Magy Parton 0 Sort Enga Py molo yes 4 7 haero kutim Wo Al pz OC wa Te ret 13 eae Link the Distributions to the Policy 1 Add a Pass through distribution for other non IP frames and configure QBase 32 2 Link Policy1 to IPv4 distribution and then to Pass through in this order 4 freescale 5 Add a Classification Add a classification for IP source and extract ipv4 src and remove ethernet
65. 0 0000 Component Inspector view 0xC 6000 0000 OxC SFFF FFFF qman portals fF4200000 desr desr Fooo00000 pci3 pcie fFe203000 pci2 pcie FFe202000 OxC 4000 0000 3FFF FFFF pcil pcie tre201000 OxC 2000 0000 1FFF FFFF 0 pcie FFeZ200000 4 freescale SSS iii E P O Device tree views synchronization Device tree views e GUI lt gt text editor symmetry Memory map view gt GUI editor symmetry Modifications are reflected in all editors SS Component Inspector 25 pw 6 o E 8 Device Tree Properties Interrupts Device Tree Nodes DTI Ibe e i2c 118000 j2c 119000 J 4 12 119100 General information 4 serial serial 11c500 4 NU Mun Properties serial2 serial 11d500 4 serial3 serial 11d600 This section describes information about the selected node s gpio 1350000 gt crypto crypto 300000 4 sec mon sec_mon 314000 Name Value 4 pme 316000 reg fel24000 0 4 gman qmani 318000 ranges 0 0 es00000 bman bman 31a000 compatible fsl p4080 elb t a rio rapidio ffFe0cO000 interrupts 25200 a Ibe localbus ffei24000 address cells 2 4 0 pcie Ffe200000 size cells 1 4 pcil pcie ffe201000 a pci2 pcie ffe202000 4 fsl dpaa 3 v Device tree Include tree lt 3 DTIHWDeviceTree dts 23 1812 lbc localbus8Bffei24000 reg lt Ox
66. 0 1 a Independent Interface eT SEC in standard width mode Pins EC MDC _ Serial Gigabit MI SGMIT 01 or RMI mode Pins TSEC1_TXDO TSEC1_TXD7 eTSEC2 Configuration eTSEC2 Configuration Serial Gigabit MI SGMIT cfg sgmii2 Serial Gigabit MII SGMIT 511 i Il i cfg tsec reduce T MDC s l A m o mode Reduced Gigabit RGMI asia Wa Configuration Serial Gigabit MII 5 gt fg tsec2_prtcl 02 Ip duced er Bit Interface RTBI _TXDO TSEC2_ cfg sgmiis eTSEC in ETSEC3 i i cfg sgmii3 Media Interface MI C 1588 ALARM OUT2 gt Miscellaneous Configuration Boot ROM Data Confiqurati g cfg tsec reduce Gigabi Media Independent Interface GMI MDC U 7 UU 7 U gt CO uration for cfg_tsec3_prtcl 0 1 Interface TBI RT_RTSO_B UART_RTS1_B eISEC 2 amp 3 Serial Gigabit 22 2 freescale fw yatay gn C 8 Ceti ire Co mms Carn P Erangy Dn Setters S POD 1 01 Corona kamkuna Ta Getter Sy prenm and av adea ot Perce Decorina mc Re US Tx Bre OF Atar festo Ion tech my www Magev Gort Ege Py mw molo yi
67. 00 187 x 1066 Features Von 3 Vppo SV 4 071 1 5 center terminated push pull 1 0 Differential bidirectional data strobe n bit prefetch architecture Differential clock inputs CK CK 8 internal banks Nominal and dynamic on die termination ODT for data strobe and mask signals Programmable CAS READ latency CL Posted CAS additive latency AL Programmable CAS WRITE lateney CWL bared q K Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set IMRSII Selectable or BLS on the fly OTF Sell refresh mode Te of OC to 95 C 541115 8192 cycle refresh ai 0 C to B5 rms 8192 cycle refresh at 85 10 95 Self refresh temperature SRT Write leveling Multipurpose register Output driver calibration 2 2 freescale Options Marking Configuration 512 Megx4 312M4 256 Meg x 256M8 128 Mee x 16 LBM IG FBGA package Pb free x4 71 ball mm x 10 5mm Rev DA 78 ball 9mm x 11 Rev D HX e FBGA package Pb free x16 96 ball mm x 1mm Rev D HA ball 8mm x 14mm Rev K n e Timing cycle time 938p amp CI 14 DDRA 2133 093 L Inse CL 13 I DDRO 1866 107 1 25159 CT 11 cDDR3 1600 125 L5ns e CIL 9 IDDR3 13331 15I I H7ns CL 7 DDR 1066 1871 Operating temperature Commercial OC Te 5 95 C None industrial 40 C 5 Te 495 C I Revision M Note 1 Not all options l
68. 00 CCI PU f SEL 112 115 Obll1O0 CC4 Pii Fu 91 116 119 Ob1100 CC4 Pu 1 C PLL SEL 120 123 061100 CC4 Ph fl C PLL SEL 124 127 0b1100 CC4 PU fl Other PLL PBLI pbi 2 00000000 AASS AASS 1 0100 4 56 0000 0000 0000 00000010 00000020 00000030 00000040 1818 Fis cece 4046 4000 FESO 0000 6100 0000 0000 0000 0000 OCSE 6000 0000 0000 0000 0000 0000 0613 8040 em Fw Eme hm Arte 86 3C3C 2000 0000 020 0000 0000 758B 7 7 E Coto TES Cera Con mms O pa Pe Oey Done Sukta 3o Sete med Caper Coruna Ta Getter axi av cadena ot Preece Zarecondote mc Re US Tx 7 OF Atar Coste Vu Um www Mage Parton w 4 Facts Qinti euin Py SMAPS umo na POS Preece Ra mcoadura mof rode ove nae Te erat X111 Sor er 2 A E paren AUT p RE Properties Marne Import System Clack System PLL 5 Memory Controller Complex 5 5 CFG 0 1 SYS PLL_RAT 2 6 DDR Reference Clock PLL 8 9 MEM PLL RAT 10 14 DDR PLL Output Clock Core Clusters PLL Core Complexes PLL 4 T Other PLL CO PLL SEL
69. 000 crypto crypto 300000 4 sec mon sec_mon 314000 pme pme 316000 gman gman 316000 E k g k I I k I Device tree Include tree T 2 freescale 9 amp 4 A Contents DI Search Related Topics E Bookmarks D 49 Help 23 al is Index s General information Documentation Properties This section describes general information about the selected node Direct Memory Access c Press F1 for more detai dual 100300 address cells Parent soc soc iffe000000 I Lines 1547 1582 Requir ed yes 1 Value type CELLLIST Constraints not defined v Properties Description This property may be used This section describes information about the selected node s properties device node that has children the device tree Xx hierarchy and describes how child device nodes M should be addressed It defines the number of Name value lt u32 gt cells used to encode the address field in Hein puas aS 4 child node s reg property If missing a client program should assume a default value of 2 compatible fsl eloplus dma req 100300 4 Hsize cells ranges 100100 200 cel Property cell index Required yes Type U32 Value type CELLLIST Constraints not defined Description SOC n The cel index property is the hardware index of the Descrip tion This prope be used
70. 000 00000000 00000000 ffe02b20 07777 77000000 00000000 00000000 xm e 9 2 freescale 1 8 dock delay CLK 2 WRIV ode 16 1 4 Seok 1 2 5 8 Mok Made 1 0 clock 51 18 dokdeay 01 M 0 LU dokdelay 01 01 38 dockdelay 01 M 21 l2dodkdeday Wil 21 5 8 91 21 3 docdea 21 05 N8dokdea 1 01 Jes 01 01 01 iSi amp dodelay 01 071 071 3 2 dock delay values wu tm d Cote didnt Cw res CM ery 53 Caper cel Gowen Ertha Ta Gotta Doren and Vora wv De Cu uA P Migr 4 Pei 27 4 tt lt tara Hee Y A w OLET 4 wh Te ole DDR Controderi v Reg mame Int value 0081 SDRAM CFG U DOSI SDRAM CG 2 DOSI SDRAM MODE 0081 SDRAM MODE 2 0081 SDRAM MD CNIL DOSI SDRAM INTERVAL 30030 0 0051 DATA INIT X 0051 SDRAM GK CNIL 0081 DOS3 INIT EXT ADORESS 0051 TIMING CFG 4 DDS1 TMNG CFG 5 14 0081 ZQ CNIL 330606 0061 0061 SR NTR DOSI RCW 1 DORI SDRAM ROW 2 0061 CNTL 2 0051 CNTL 3 DOSI SDRAM MODE 3 0081 SDRAM MODE 4 DOSI SDRAM MODE 5 DOSI SDRAM MODE 6 DOS1 MODE 7 DORI SDRAM MODE 8 DOS3 DDRDSR 1 DOSI DDRDSR 2 DDR Validation Tool Availability You
71. 00000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00110105 00000000 00000000 03000000 00000000 P P UP UPS UP C 5 Coop TED Cn d 1 1 5 Caper ta Satanas ad Vond2a av cadena ct Finca Derecomdctm mc US Tx amp 7 OF festo Vas Um www Magev Prior w 4 Der Py 4 s Fuascata Lamconduta Wa of ord OF yee Te Thus MPEG wera X111 Sorter eres AP oes Upa P Er yy Uw 1 evt PO Pee UICE Generate DDR configuration u rr Project Panel I y Component Inspector 2 2 lt alf Properties Import Export V E p2020rdb pcal Documentation Generate Processor Expert Code Device Generated Code haesmnnr hne 125 p2020rdb pcal b Documentation gt Generated Code LI ddriCtrl 1 tcl Le InitDdrRegisters 1 c 6 p2020ds ddr c fw Fee kun C5 Cedo TET Cm ure Cipa E t go Tia rote gt PSZ 1 1 6 Sre Eazec O0 Orar s as rer and Vc fis Larec US te im O fr le Arteri Bess C arwi Pun Lyanga Mages MIC Plor Facius Gort
72. 0000000 00000000 expo rt nctio n SERDES Reference Clocks Bank1 125MHz Bank2 125MHz Bank3 125MHz 2 ready DRAM Initializing using SPD Detected UDIMM s Detected UDIMM s 2 GiB left unmapped DDR 4 GiB DDR3 64 bit CL 9 ECC on Testing 0x00000000 Ox7fffffff Testing 0x80000000 Oxffffffff Remap DDR 2 GiB left unmapped Hit any key to stop autoboot 0 2 freescale gt md Oxfe008000 AEN Create Lab4 project File New QorlQ Configuration Project QodQ Configuration Project DDR Contigurabon Select P4080 rev 2 Configured device P4080 v2 0 Configure 1st DDR Controller Configuration mede Auto comigurabon Inport from memory file Select only DDR tool Type DORs DRAM Configuration 1Gh 12834b x Rate 1333MT s gt Speed Rating 1333MT s Ranks i Registered DIMM Dota Bus width 4 bits gt Mirrored DIMM Take the default configuration RP APCD 13 5 m ECC Enabled Presets Save Open Presets Folder Load Ppida DORI PCI0600 2GB 9 7 7 20 Select Ist DDR Controller 7 lt Beck Prsh Cancel o ove hen Fra Co oes Sec n ro wy twm mr 4 Powe it 121 gt Ces Cowes Lawhusw Ts AUN lord aw ade sx c wau Le ECORI heg te ite Beets Couture fee Mage
73. 02C 3 Dataz0x10101010 Mask FFFFFFFF Queue basez0000002D Se 2 freescale M Pu b m y Arv elt ya in t re D eat k e Configure the ethernet dst Entries 1 Link Pass through distribution to FQIDs1 2 Draw 2 links from ethernet dst classification to FQIDs1 3 Configure ethernet dst classification Entries to FQIDs1 1 Data 0 7 76000000 Mask FFFFFF000000 Queue base 0000002bE 2 Data 555555000000 Mask FFFFFF000000 Queue base 0000002F Channel 0x5 03 5W Portal 5 0 M Pu b m y Arv elt rts Pon v re D i e 2 freescale Configure the FMan Port 6 FMan 1 Port 1 configuration 1 Port name fmOport01 MAC address 00 04 9f 00 02 66 Interface RGMII Speed 1 Gbps 2 Enable Loopback and Reset on Init 3 Enable Rx port Error FQld 20 Default FQld 20 4 Enable Tx port Error FQla 40 Default FQId 0 5 Add and use BufferPool0 Number of buffers 100 Buffer pool Id 0 Buffer Size 51200 7 FMan 1 Tx configuration 1 Channel for FM1 Port 1 1 Adda FQIDs range FQR2 used to transmit frames on FM1 and configure FQld 201 and count 1 2 Add FM port1 channel 3 Link FQIDs2 to FM1 port1 channel WQO wem Cm v p y tage d eit lar Pret s Levy amp 3o Se roe 162 4 Ces Go he t sx UA l i eee ue O w
74. 080 and P4040 are same SOC otherwise Walk through the next slides using QCS Hardware Device Tree editor to solve this scenario rw t r pi gt PAoa sh epy fwe ne 4 4 2 freescale Device Tree Step 1 Create New Project Creete a f et on Peer t tow Gori Configuration Propect E vas ram the Sec pou modd Mike to Soe to be used type fitter best gt k s 3 vL 0 Oper Chi VPN ve v Hr w Phe 5 awe New QorlQ Configuration Project wives Lev Deters Te Crit Device Tree Hardware Device Tree nd LU Wort 1 Mew UO FI Lomiburation Project eun Toolset sedesc tion 1 5 ene OR Choose what do you want to configure Properties den Input File Files b05648 Desktop PEx Device Tree dts p4080ds dts Components to be selected k y cumple tas Select the device tree file to be imported O C 9 Device Trees irm Project im cale conductor Goto Wo Co Z freescale veneer Pw kun AA C5 Coop TEST C DAF vm Ca Miey Torn evt 1 39 Exper ta Gotten ai av cadens ot Preece
75. 4 5 82 162 165 SRDS LPO 83 170 173 CC 00 Core cluster PLL 2 nu 0 LCS PLL RAT 1000 8 1 Async Core Complexes PLL CO PLL SEL O00 CE1 PLL L1 FLL SEL O00 ECT PLL 71 Ce PLL SEL UO LE PLL L3 PLL SEL 000 CCT PLL EJ SERDES PLL and Protoco n cm L c io OV tora egie 0 Per ger al Sr ha rato DOR 2 50 50000 KASI AARSE OIGE 0200 GAS 0 90120010 2219 0000 009909 0900 09040 2409 9000 2600 20200020 0000 0900 0000 0000 0000 0000 0000 0000 20200030 5005 006 0000 0020 0000 0000 0000 0000 001290040 09000 0009 0000 0000 0812 8090 2 4 SSSA 6650 2000 4 3 f gn CE Cedo TET Cra Con rms Stee P Port net 970 Peewee 1 2 Caper Corona Te Satanas Symone and are were ot Preece mc Rep US Tx OF Atar festo Gort Py SMAPS mw molo yi ad wx karwacnkutu Wa rod 4 O nee ay W Yus ete watak X111 mora Va Pre boot Loader standard component interface Seas Chip version and errata information p zm SET E Chip version PAM E Erratum information 1 sess
76. 500mc 1499 985000MHz 2 0 pyr 8023 0020 99 99 52 e500mc 1489 385000MHz 2 0 pyr 8023 0020 99 99 x e500mc 1439 385000MHz 2 0 pyr 8023 0020 99 99 total bogomips 399 99 timebase platform model Memory 49999500 P4080 DS fsl P4038005 4086 MB On a Linux amp machine create the device tree binaries before and after changes Boot the Linux kernel on p4080DS board Check the number of CPUS that Linux kernel sees before and after changes use proc cpuinfo command You should obtain the results from left side only 4 cores are in use with the new device tree 4 2 freescale Conclusions sequence of steps for modifying hardware device trees has been presented benefits of using Hardware Device Tree tool are First device tree editor including two modes for editing GUI and text Easy to understand device trees structure due to the visual representation eupports device tree bindings and validation Allows users to add their own device trees Provides features for all the main aspects of hardware device trees lt is an editor and a validation tool for creating valid and well formed device trees Works on Linux and Windows hosts 4 4 wem Pu tae ett plow nt Fra Co 17 w gt j 145 lt 4 k S hs amane us E T k ha a TM key a
77. 80 90 80014202 94 6 702100 98 90030900 c ff702104 80 55770802 a417 702108 aB 5f599543 9 9999 999999 999999999999999999999992995 ac iff 0210c cfg mir pli 5 2 bo 9fa0 4di fttttttititttttttttttitttitttttitittttttttttttttittttiitttttttttttttittttitttttt efe ate pii 2 e 58124401200 6 Power On Reset Target Configuration Overview for P2020 t cfg pii 31 bc f702118 ear e0 00049852 Gar pii Obi c4 702124 8 0 220100 cciff702130 a6 03000000 d4 40000001 d8 950002100 dc 70212 eDidesadrpeef 64166702110 lt 3020000 ec ff700C08 f 0 90000000 LIED f8B BOF0001D fciefefeter DOA Compiles Clock FLL Fatio setting LE DOR Compiex JOACE fetio BOOTROM Device DDR Device Ce HADevice Device Cow Fiker on for P200 project pete FD OER Descnpten n nes CoUsSemb231A Freescale 29 22 1 6 w space 92029 Documentos BOCTROMI PowerDoReset Report htm gt i VECES CCB Clock PLL Ratio settings for information only OCS Clack SYSCLK 61 600 000 MHz 744 2 b cw 2 sys pil 0 2 le 2 a m a a ata a a n a a ata a ua a a n afa ad sys 1 cfg sys pil 2 400 000 MHz 41 fw yatay kuqa Aw C 8 Code TET Cogeftumor
78. ASB AVNET ELECTRONICS BARCO N V CANOGA PERKINS CEAC INT L CES CREATIVE ELECTRONIC CHANGWON UNIV CISCO CISCO SYSTEMS CONTINOUS COMPUTING CRYPTO AG CYAN INC DIALOGIC INC DSPACE GMBH EDIXIA EMBEDDED SOLUTIONS EMCOSYS FUTURE ELECT INC GAMMA SP Z O O GE INTELLEGENT PLATFORMS LTD GIGAMON SYSTEMS GUODIAN NANJING AUTOMATION HEIDENHAIN GMBH IEP GMBH INTERFACE CONCEPT IPWIRELESS ISKRATEL ELECTRONICS ITEC CONSULTING AS JUNIPER NETWORKS JUNIPER NETWORKS INDIA KDS Ron Configuration COMPUTER SYSTEMS MIRANDA TECHNOLOGIES MOTOROLA MOBILITY INC MYSTICAL ROSE TECHNOLOGIES NARI NETWORKS NKB VS PURESILICON INC REDCOM LABORATORIES INC ROHDE amp SCHWARZ ROHDESCHWARZ GMBHCO KG ROSS VIDEO SASET CHENGDU SERVERGY SERVERGY INC SIMENA SOUTHERN FEDERAL UNIVERSITY SUSQUEHANNA INTERNATIONAL GROUP LLP TECHNOLOGY OF INFINITY THERMO FISHER SCIENTIFIC WB S A WINDRIVER WT MICROELECTRONICS CO ZODIAC o 2 freescale i 4 Pricing amp Availability Part numbers CWA QIQ OPTP FL floating license amp CWA QIQ OPTP NL node locked Price 999 Annual Subscription License Duration 1 year Support amp Maintenance Included e Availability Scenarios Tool Now DDRv Now 4 2 freescale freescale QorIQ 1 thw Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Far oa Cowen Sa
79. C Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc New QorlQ Configuration Project ile Edit Source Refactor Navigate Search Run Project Processor Expert Window Help Create a GorlQ Configuration Project New Alt Shift N gt QorlQ Configuration Project Open File Choose the location for the new project p gt Makefile Project with Existing Code Close Ctrl W C Project Close All Ctrl Shift W C Project Project name P2020 DDRv lt Save Ctri S L3 Project Use default location Save As Convert to a C C Project Locationi C Workspace DDRv eclipse workspace P2020_DDR Browse Save All Ctrl Shift S Source Folder Revert C3 Folder Source File F2 ibi Header File 2 7 E Refresh FS File from Template Convert Line Delimiters To E Class CT Task Print Ctrl P F Other Switch Workspace Restart a Import Export Einish Properties Alt Enter Exit ee Sajan ys fe koa Aw OE Cote TEX 0 ape Cors
80. CPU Core Related Scenarios m Utilizatian Customer Benefit Cache MMU System Optimization Cores and Core Compia Load Store Unit SoC DDR DDR Related Scenarios DDR Traffic Measures whole system C O D ex ty Abst racti n a d 5 Of DDR Traffic by Whole System a DDR Traffic Scenarios that measure whole system or individual CoreNet CoreNet Coherency Fabric Scenarios u S e CoreNet Traffic All CoreMet Traffic AID CoreMet Traffic PCIe CoreMet Traffic PCIe St re a n ed IO SO lve S eve ral CoreNet Traffic BMan Portal CoreNet Traffic BMan Portal s CoreNet Traffic QMan Portal CoreMet Traffic Portal D e rfo rm a S S U e S CoreNet Traffic CCSR CoreMet Traffic CCSR a CoreMet Traffic DMA CoreNet Traffic DMA D el Ive r F S L expe rti S e tO u S rs DPAA QMan Data Path Scenarios for the Queue Manager Dequeue Counts Measures dequeue counts on SW portal and HW DC por Probe less field based usage DPAA SEC QA ib 8 Corfu Ta rg et a reas I Security Engl DMA Select QorlQ devices P3 T4 B4 and future Layerscape devices Linux Systems focus but also supports bare metal uie k G G 0 02 G 02 G 1 1 at EI ront 4 i 13 m Performance Analysis including visualization 2 2 freescale 56 Optimized workflow for efficiently narrowing down
81. DRAM 00000000 DDRi SDRAM MODE 4 00000000 DDR1 SDRAM MODE 5 00000000 DDRi SDRAM MODE 6 00000000 DDR1 SDRAM MODE 7 00000000 DDRi SDRAM MODE 8 00000000 Wa DDR1_DDRDSR_1 00000000 DDRi DDRDSR 2 00000000 C 5 Code TE T Conf vos CM Ww Er yy evt m 4C 1 e 9 52 Trocessor Caper Gowen Seles ta Satanas and ane akwa Preece Zanccomdetar mc ds US Ty itr fr I TM festo Cose em Umi www Magee Petters w 4 Fut Goewerge Toad Py SMAI MS mw umo na yi 54 TPS we hedera karwacyykztiu Wa RO ww FORA wa Te VT pects sura CXII P2020RDB PCA Compare optimal DDR configuration with uboot chosen values Read DDR configuration from uboot md ffe02000 ffe02000 0000003f 00000000 00000000 00000000 ffe02080 80014202 00000000 00000000 00000000 02100 90030000 D01 10104 61608846 Ofa8c8cc 02110 7000008 24401040 00441421 00000000 D 02120 00000000 0c300100 deadbeef 00000000 02130 03000000 00000000 00000000 00000000 ffe02160 00220001 02401400 00000000 00000000 ffe02170 89080600 00000000 gt 02000 02000 00000000 00000000 00000000 00000000 02010 00000000 00000
82. Descipian 2 SERDES amp plaermt Workaround Mewerkenund PLL Configuration ees Sees PLL and Protocol Configuratie Fl Misc PLL Related Configuration 2 C 0 Settings of RCW fields E Boot Configuration I Fl Clocking Configuration 0 Memory and High Speed 1 0 Config 00000 General Purpose Information 2 r L Pin Multiplexing Configuration C C 0 E Group A Pin Configuration BH Group Pin Configuration 0 PE PBL Data 245p o PBlDaa mets O O Possibility to add PBI data 22 dnpuDaa mes Possibility to import RCW settings Z freescale 1S tram pn Mer uir Page bre BOE freescale DDR Configuratio DR Configu AA thw oun Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Far oa Cowen Sale oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Get DRAM informat
83. Frame received on 0 826 From F R FQR1 Frame received on 0 8228 From F R FQR1 Frame received on Q Hx2e from F R FQR1 A II gt Test DPAA Basic Passed lt lt lt 11 tests passed successfully fF gt gt gt System is terminating Farewell secuta Cw Feenteti Wu aT Wes Sere Conf ve ste Nh 9 i 164 orcas G Te Farle ad Vora ane a nuu ZI T heu ot artar teva Poaztech ws M v Facts Donc Cheewerge Eo oh Mwy Duy w am 22 4 e y 82 4 icc 4 eon Teo anid 9 sco DPAA Hands on Output Analysis Output analysis FManO Frame1 IPV4 Frame IP src 16 16 16 16 IP frame gt IP miss gt MAC match gt Enqueued FQID 45 0x2D Frame2 IPVA UDP Frame MAC dst 0a 7a 76 5b 67 e9 IP frame gt IP miss gt MAC match gt Enqueued FQID 46 0x2E Frames VLAN non IPV4 Frame non IP frame gt Enqueued FQID 32 0x20 Frame4 ARP non IPV4 Frame non IP frame gt Enqueued FQID 32 0x20 Frame2 IPVA TCP Frame MAC dst 0a 7a 76 5b 67 e9 IP frame gt miss gt MAC match gt Enqueued FQID 46 0x2E 4 wem wu Pu ga elt Ref ums IE v2 Pt eyy 7 et 5 165 lt 4 Ge iw aidara ue f UA T i h h TM leta eis Ces t Meow V 4 Vr tag oy a
84. MS 42 brc ua mmy ve Vers 4 ti SFO ONRIIE W CU w BOBS 4 Gu wd To alo fus seras Centering of the clock after ODT optimization Results gt Choose tests Centering of CLK ADJ clock scenario E cock NE saat 12 clock delay paps mam after finding pa h s the right ODT 3 8 clock delay E 0 3 values 1 2 clock delay 0 2 0 3 3 0 3 5 8 clock delay 0 3 3 4 clock delay 7 8 clock 0 3 RN 0 3 0 3 0 3 0 3 0 3 0 3 0 3 17 8 clock 5 0 3 9 4 clock delay 0 3 19 8 clock delay 0 3 0 3 0 3 5 2 clock delay 0 3 0 3 La eis E 5 WRLVL 4 2 freescale 194 222225 Generate optimized DDR configuration p2020rdb pcal L Documentation Component D etails Generated Code Device DDR Controller 1 DDR Controller 1 Sources DDR 3 DDR Bus Clock 400 MHz DDR Data Rate 800 MT s 4 Ry ProcessorExpert pe n Type of DIMM Unbuffered DIMMs Configurations 5 f P2020 Fuss an nus Operating System E a a Processors E peran S 95 SoC P2020 gt r F gt SDRAM Timing Configurations il DDR mci cli chip select addressin yes 4 Chip Select 0 Enabled 4 Memory Bounds Start Address 0 H Size 1 GB 4 Configuration Auto Precharge Always no I
85. Nov 201 1 V2 2 adds Bootrom tool amp all QorlQ NPI available since May 2012 Be familiar with the QorlQ Optimization Suite basics DDRv for on chip validation of DDR controller configuration Scenarios tool for capturing running system results for various characteristics Packet tool for visualizing the flow of packets within a QorlQ device Solution Strategy Extensible suite of tools to solve these problems Consolidate into a common tools framework Processor Expert Provide new device support aligned with silicon roadmap Add more configuration tools over time Allow customers to add their own configuration tools to extend what we offer Se 2 freescale gt gt Processor Expert for QorlQ For More Info Freescale s Processor Expert landing page http www freescale com webapp sps site prod summary sp code PROCESSOR EXPEHT amp tidZPEH http AWwww processorexpert com QorlQ Configuration Suite http www freescale com webapp sps site prod summary jsp code PE QORIQ SUITE amp tid PEH QorlQ Optimization Suite htto Awww freescale com webapp sps site orod summary iso code PE QORIQ OPTI SUITE amp tid PEH Freescale Component Store purchasing embedded software http www freescale com webapp sps site homepaae jsp code BEAN STORE MAIN amp tidZSWnT Co wm fu Haie ga Cote lt 1 C jan U DOA Ca felony fon Sk t 1 et medi su
86. OSB 6000 ODDO oooo ODDO PBL1 F Move QOOOO0D040 OOOO OOOO OOOO OOOO 813 5040 Pees Bese SaAnalysispoir Rename FZ Import Export Refresh Generating the PBL provides the same Show in Remate Systems view Clean Selected File s RCW as the high speed RCW seen In the Build Selected File s 4 Generate Processor Expert Code S D fsl Ubuntu 32bit mnt hgfs DebianShare QorlQSDK_02_ 03 _00B images boot p4080ds R_PPSXN_Ox10 File Edit View Terminal Help fsleUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 O00B images boot p4080ds R PPSXN 0 10 ls hv lp lnx dtb 0x10 130 rev2 low bin 0x18 13g sbenl rev2 low bin txt hv 2p lnx lwe dtb 0x10 13g rev2 low bin txt 0x10 5g rev2 high bin hv 4p lnx lnx lwe lwe dtb 0x10 13g sbenO rev2 low bin 0x18 5g rev2 high bin txt 0x18 13g rev2 high bin 0x10 13g rev2 low bin txt rcw 0x18 5g rev2 low bin rcw 0x10 13g rev2 high bin txt rcw 0x10 13g sbenl rev2 low bin rcw 0x10 rev2 low bin txt fsl Ubuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 PPSXN _0x10 xxd rcw 0x10 5g rev2 high bin 0000000 aa55 aa55 010 0100 105a 0000 0000 0000 0000010 lele 181e 0000 cccc 4046 4000 3c3c 2000 0000020 0 0000 6100 0000 0000 0000 0000 0000 0000030 0000 0000 008b 6000 0000 0000 0000 0000 0000040 0000 0000 0000 0000 0813 8040 223 b25c
87. Pre boot Loader RCW Configuration t Ja T Z2 7 Bun Project ProceseorExpert ert c kerar 7017 5 w Wrote 2000 775 Sx Properties Method vent gt Documentaton 05 Code Name Val Details gt eg Component name FBL1 PLL Configuration 00000000000 EE Y and Prutocol Confuyurwtinn Y 5805 178 1 Ser SADS pRTCL 123 133 0 22 Berk L A mp6 RATID 81 130 130 System PLL bits 0 1 00 Platform freg system RATIO B2 1941957 Sick Ten 5 PLL RAT bits 2 6 00101 5 1 prbesdes Components BS 349 190 99 9 Memory Controller Comp C 83 151 0 12 6 c Y sapa ipo 152 101 MEM PLL bits 8 2 00 Lower frequency refe T mre pinea PLL RAT bits 10 00001 1 1 syne made T SRDS LUPO B1 laneE 0 aa rot paeem 220 pO 8 154 0 rat sene Core Clusters PLL 5 Ph eo RA CC1_PLL_CFG 00 Core cluster PLL 1 ou Y Sams 170 S1 isre powered PLL 1000 8 1 Async T SOS J20 Bi lanet 1158 0 Y o8 120 Bl Lene 190 0 SROS B1 Lane l 163 0 Lane rot power SOS 120 81 laned PAg 0 5
88. RAT 90 94 Core Cluster 4 PLL Clock Core Complexes PLL CU PLL SEL 96 99 Core O PLL Clock C1 PLL SEL 100 105 Core 1 PLL Clock C2 PLL SEL 104 107 Core 2 PLL Clock C3 SEL 108 111 Core 3 PLL Clock C4 PLL SEL 112 115 Core 4 PLL Clack C5 PLL SEL 116 119 Core 5 PLL Clock C6 PLL SEL 120 123 Core 6 PLL Clock C SEL 124 127 Core 7 PLL Clock 4 2 freescale Memory Controller Complex Value 1 Higher Frequency reference cl 0601101 13 1 async mode anl Ob00 Core cluster PLL 1 output freg 01111 15 1 Asvnc 1 500 GHz Core cluster PLL 2 output Freq 0601111 15 1 Async 1 500 GHz 0601 Core cluster PLL 3 output Freq ObO1001 9 1 Async 900 000 MHz Core cluster PLL 4 output Freq 0601111 15 1 Async 1 500 GHz ObOO00 PLL 71 1 500 Hz ObO000 CC1 PLL 11 1 500 GHz ObO000 j1 1 500 GHz ObOO00 CC1 PLL 11 1 500 GHz 061100 PLL 1 1 500 GHz 061100 CC4 PLL 1 1 500 Hz 061100 CC4 PLL 1 1 500 GHz 061100 CC4 PLL 11 1 500 GHz Basic Advanced Expert Ig 7 E Details 650 MHz gt 1 3GHz 89 Set MEM PLL RAT to 13 1 fre r p tmn Cr he k One ra Co res pa P Don Sok wa Sete vaat POD Peewee Qe kamkuna ta Getter
89. S Tx ETa OF 51 TM Atar festo w 4 irt Ege Py SMAI MS mw molo yi 4 la mconkta Wa ofi ord OF un ww Ma W C1 Frese Race a 4 P2020RDB PCA DDRV optimized test results Reg name Init value Test results SDRAM 7000008 DDR1 SDRAM CFG 2 24401050 i DDRi SDRAM MODE 00061421 CLK ADJ X 0 1 8 cycles 1 4 cycles 3 8 cycles 1 2 cycles 5 8 cycles 3 4 cycles 7 8 cycles 1 DORI SDRAM MODE 2 00000000 i 0 clock delay 0 1 0 1 0 1 0 1 0 1 DDR1 SDRAM MD CNTL 00000000 1 8 clock delay 0 1 0 1 0 1 0 1 SDRAM INTERVAL 0C30030C 1 4 clock delay 0 1 0 0 1 0 1 DDR DATA INIT 00000000 3 8 clock delay 0 1 JA dM 1 0 1 DDR1_SDRAM_CLK_CNTL 02000000 10 clock 0 1 DDR1_INIT_ADDR 00000000 0 1 DDRI INIT EXT ADDRESS 00000000 3 4 clock delay 0 1 DDR1_TIMING_CFG_4 00220001 7 8 clock delay 0 1 DDRI TIMIMG CFG 5 02401400 i 1 clock delay 0 1 DORI ZQ CNTL 29080600 I 9 8 clock delay 0 1 n DDR1_WRLVL_CNTL 8655F605 WRLVL START 5 4 clock delay 0 1 DDR1 SR 00000000 i 11 8 clock delay 0 1 SDRAM RCW 1 00000000 DDRi SDRAM RCW 2 00000000 3 2 clock delay w 13 8 lock delay O ptim al DDR1_WRLVL_CNTL 2 00000000 WRLVL CNTL 3 00000000 settings DDRI S
90. Te ty wawita wert X111 Amico be Observe DDR validation test results 3 Component Inspector Properties Import Export Validation Choose DDR tests to be executed Test Result Validation stages Stagel amp Centering the clock amp Read ODT and driver Write ODT and driver Smoke Tests Select Test Options Test Run times Pattern Write Read Write Compare E Walking Ones E Walking Zeros Connection settings Test results WRLVL START Remote system IP 127 0 0 1 Disconnect Available connections System P5020 ETAP 1d 10 82 138 191 7 ADJ amp WRLV 0 clock delay 1 8 clock delay 1 4 clock delay 3 8 clock delay 1 2 clock delay 5 8 clock delay 3 4 clock delay 7 8 clock delay 1 clock delay 9 8 clock delay 5 4 clock delay 11 8 clock delay 3 2 clock delay 13 8 clock delay 7 4 clock delay 15 8 clock delay 2 clock delay 17 8 clock delay 9 4 clock delay 19 8 clock delay 5 2 clock delay 0 cycles 1 8 cycles 1 4 cycles 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 CLK ADJ 3 8 cycles 1 2 cycles 5 8 cycles 3 4 cycles 7 8 cycles 1 cycles 0 3 0 3 0 3 0 3 0 3 wass lr mee 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 Test results per DDR configuration 2 freescale 50 Pw
91. Un P egy Er wi m r vorat 1 08 eve Ont LET re Pet 9 EET oe freescale ccena qr arare Select device and DDR component New QorlQ Configuration Project Devices Select the SoC you would like to use Soc to be used type filter text Silicon Revision Choose silican revision Creates project for P2020 derivative 2 freescale New QorlQ Configuration Project Toolset selection Choose what do you want to configure Components to be selected type filter text 4 Components BOOTROM Configuration DDR Memory Controller Configuration Device Tree Editor The DDR Memory Controller configuration tool supports the specific settings for a custom DDR based on the manufacturers data sheet and includes optional clock bus and DMA settings wm y AA ode lk eC wheter oe ra Lon res U Bee IP Er yy for S k t 1v med rocesmr Coe Corona Ts Sywram and av were ot Preece mc Heg US Pe OF Pon tct en Mae e 4 wet gu 9 OC opm Pwy VAS molo yt 4 tt lt te eros eeu kaw kin Y QU of POLS OF nee Te ery pete eraut CXII wea ere DDR Ne
92. and application performance problems in the QorlQ and Layerscape Family of devices Users can analyze their applications unencumbered by the complexity of the debug IP Provides a simple clear and concise way of configuring the QorlQ debug IP to solve performance problems Continues the usage of the proven Scenarios Concept providing customers with recipes to analyze common and complex performance problems Transfer Freescale s knowledge to customers Scenarios Supports bare metal and Linux applications Special focus on Linux User space applications e freescale g 3 freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge Ld W wa t od aan api wiki POS Perr LOC Far oa Cowen Sale oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc DDR Validation is a licensed product leveraging QCS EL Component Inspector Zi Properties Import Expo Vali lame Device DDR Controller 1 Memory type DDR 3 DDR Bus Clock 400 Type of DIMM Unbuffered DIMMs Bus
93. aner Gore uL Ts Pucca Serene and Vora festo Patch n ww Mage Parier ma te lt Feed V Rote POLS 14 CO AA p Mya Hele twr obe QS Dovey UU wa ie rot we Sere cU aca Lenccoo amp A IER A owe AIr 1 Rey US zz C amo ot V a DC Ege Mwy SMAI chia Component Inspector 22 Basic JAdvanced Expert h 7 P n W Properties import Export Validation c Results Choosetests 2 Validation stage E Centering the clock E Read ODT and driver Write ODT and driver E Operational DDR tests Choose validation mode Summary Logs Scripts Updated configuration registers Error cap Name Value Name Ww Start Validation Test results fe yataq kuqa Aw C 8 Cod o TET Cedar ce Cra Con mmo Carn P Pont Sra S eet MEO Pewee 1 28 Processor Caper Coruna Ta Gotten and armada ot Perce Zerecondore mc Hep US Tx OV Artur festo nva Mage VOC w 4 Gort EOC Enga Py mw rool oe yi and wu Ka mcondusa Wa ord bive nene wa Te
94. apar iwa ownwen 331 Sere sedrtrc inc Pre boot Loader Hands on Step 1 Import and decode low speed config 0x10 5g rev2 low bin txt Platform clock 600MHz Core clock 1 2GHz FMAN1 2 clock 450 MHz DDR clock 600MHz 1 2GHz Step 2 Use PBL tool to increase clock speed up to Platform clock 800MHz Core clock 1 5GHz FMAN1 2 clock 600 MHz DDR clock 650MHz clock 1 3GHz Step 3 Use PBL tool to generate new RCW and compare outcomes With rcw 0x10 5g rev2 high bin txt Step 4 Change Serdes Config to support 8 Gbe compare result With rcw 0x16 all rev2 high bin o 2 freescale Pre Boot Loader Step 1 Create a New Project Now Oorl I Proci ar Devices the Sec you mould Mike to Creete a Can Configure st n Propet tere an fw he rm ram Soc to be used type Faites best 2 gt TOT we IL Hon Same a Magus T Praet Parir Prone Ey d J Powe zrtee tre Propart Wendie Oper Crit Oper Fi Cade 3 ounce Phir Potter Sour s Pie tres wives Lee Deters Te Til i Hew riU LO raf pot gb Oper 1 Wizard What s New Choose whet do you mant to Properties a tes Cortar si
95. ase of use Enables key use cases Packet Oriented System Level Performance Analysis SoC Data Plane Configuration Debug Packet Processing Latency Analysis Packet Processing Critical 19 lt Resource Monitoring CORE EEUU Du Select a Oath unde 0 16 Decode Only Processing Path Analysis View By Frames Processed Processing Path Details Processed 13 Processing Path _ Target areas SoC debug analysis feature enablement Source Linux Systems 1000 x Analysis data interpretation and Path 1 Latency Platform Clock Cycles visualization Users External Customers Freescale internal developers 2 freescale Main Use Cases Packet Tracing Lost Packet Analysis Latency Analysis Packet Sequence Analysis QM Performance Analysis 4 2 freescale ohows which parts of the system process the frames For example use this to verify that the frame flow is what you expect Understand why the frames become lost in the system For example use this to check how the FM PCD changes affect where frames are sent Precisely measure the time spent processing frames at various points in the system oee how an entire sequence of frames was processed For example use this to measure the performance of the SEC Use QM profile data to measure the performance of the system at data flow level 64
96. ce T We type pedal Working set define working set fw yaaa kuqa C 8 Cedo TET Ceti ira Co mms Pe Don okra go est POD Peewee e 26 Caper Te Satanas Sumu Dynion and adea ot Zarecomdura mc Re US Tx OF O freescale TM Artur Boss Car NN Lyanga Magn Prior Paipa Corsi overga QUOC Mendy Mey SUEVOS mw uso ni Vyara 4 aed adero Ra mcoakurmr Wa OF OF suwa eb wa Sete erat X111 ax Device Tree Bindings e Each node has a binding representing its schema It describes what properties are optional or required and what each means gu 5 e 527 c3 amp Device Tree Properties Interrupts Device Tree Nodes DIL 4 corenet cf 18000 jormmu 20000 rmu rmu d3000 mpic pic 40000 timer 41100 msiD msi 4 1600 msil 115141800 msi2 msi 41a00 timer 42100 4 guts global utilities e0000 pins global utilities e0e00 clockgen global utilities e1000 rcpm global utilities e2000 sfp sfp es000 serdes serdes ea000 dmal dma 100300 dmal dma 101300 sdhc sdhc 1 14000 i2c 118000 i2c 119000 i2c 119100 serial serial 11c500 seriall serial 11c600 serial2 serial 11d500 serial3 serial 11d600 gpioD gpio 130
97. cessor Ex Using the xmls i My Compoentispeto aie Advanced Expert i i i i H i i i l 0 i i i i i i i i 150 i i i leo i i i 29 E m generated by the hands on scenario presented in the Device E Flowchi Policy Engine Forts p EN a lE Le E 34 33 TE 9 1 9660 upper slides d deem Ban CN FF Buffer F p Mu F Policer E Distrib a Classifi Prokoce c FH gran E F RS SEC T P i Policy rm DO 11 t L Channel 0941 lies FMA port 22 2 a x gt T rd IE Sja H Foom 100 Selection 823 wem Pu P ai tmn d 4 dett Pre CAF tpi oe rrey re 35 Tpu n 42 gt Cowes Pe datetaciut oJ kur ax lord a ane ae Ux c7 Freercate Lacco 111 t heg te ite h on bury V Paip Gert MOC Py mw rool na ys W Tues epee erat X111 Ya z freescale is Beh Dude 4 freescale amupa the
98. ci PLL F1 1 500 GHz ObOOO0 CC1 PLL F1 1 500 GHz ObOOO00 PLL f1 1 500 GHz OboO00 Ci 1 500 GHz 061100 CC4 PLL f1 061100 CC4 PLL f1 061100 CC4 PLL f1 061100 CC4 PLL 1 Changing the CC1 CC4 PLL RAT for cores to 15 1 sets core clocks to 1 5 Ghz 1 2 Ghz gt 1 5 Ghz CC1 clocks core 0 3 CC4 clocks core 4 7 Note Please change CC2 also even if unused to reach exact high rcw E Cote TET Co pa P Dor 3o S eet POD Pewee Fw tpm Aw Caper Gowen Ta Getter axi av were z Preece Zarecomdute mc Rep US Tx 7 OF Atar festo 4 Dri Ege Py SMAI MOS mw molo yi and we yayawa s Fee Wa IOAN OF eoe neni Te a Toy suras X111 Serer 88 Pre boot Loader Increase DDR Output Clock ComponentInspector 22 Properties Import Mame MEM PLL CFG 8 9 10 14 Core Clusters PLL PLL 64 65 CC1 PLL RAT 66 70 Core Cluster 1 PLL Clock 2 PLL 72 73 CCe PLL 74 78 Core Cluster 2 PLL Clock PLL 80 81 PLL RAT 82 86 Core Cluster 3 PLL Clock CC4 PLL CFG 88 89 CC4 PLL
99. cluster PLL 3 output Freq C O C lt 0601100 12 1 Async ObO0 Core cluster PLL 4 output 0601111 15 1 Async 1 500 GHz 30 000 MHz 400 000 MHz Both DDR in asynchronous mode Platform Clock jz Ob1 Core Cluster PLL 2 Ob1 Core Cluster PLL 3 2 450 MH gt 600 MH ObO1 8 8 8 9 9 9 10 10 10 11 11 Z Z Refer to hardware specification obs om oo fe yaaa kuqa C 8 Cedo TET Ceti ira Co mms Stee Pe Don okra go est POD 90 Caper Coruna Sele Ta Satanas Spree and were ot F wawcate Zarecomdure mc He US Tx OF Atar festo 4 Gort Py SMAPS mw molo yi f TM reescale amd wa aderat s karwccnykztiu Wo OC eu us wa Te A fy MPEG CXII Sorter ore be Pre boot Loader Step 7 Generate Upgraded RCW TS Project Panel 22 E amp E 126 lL Documentation 1 15 Generated Cade Sources Sz T El Configurat Mew k PBL1 pbl cod _ DOD00O0O0O0O0OOC 55 AASS Dl E 0100 1054 OOOO OOOO OOOO 00000010 1 1 1 0000 4046 4000 2000 mdi soc ids 00000020 FESO 0000 6100 0000 oooo oooo D000 D000 B Embedded pon 3 Delete Keri 00000030 ODOD ODDO D
100. cpu4 gt Cpus 190 interrupts lt 0 71 0 2 0 0 0 0 gt 19 Es bman portal 10000 193 bman portald 14000 bman portal 14000 194 cell index 0x5 195 compatible fsl p4080 bman portal fsl bman portal bman portal 18000 196 reg lt 0x14000 Ox4000 0 105000 0 1000 gt 6 127 cpu handle c amp cpu5 4410 owed vaa Mae ID Mae Mise Marin bman portal 1c000 qportal4 Console SG Progress 8 errors 0 warnings 0 others qportal5 Description Resource Path Locat 5 Errors 8 items qportal6 P4080 v2 prijaenerated line 189 Device Tree Undefined reference cpu handle P4080 v2 j pri Generated_ line 197 Device Tree qportal7 9 Undefined reference cpu handle P4080 v2 jprjlGenerated line 205 Device Tree Undefined reference cpu handle P4080 v2 j pri Generated_ line 213 Device Tree 8 Im th 8 od es n a S m ar Undefined reference cpu handle P4080 v2 JjprjjGenerated line 288 Device Tree 3 Undefined reference cpu handle P4080 v2 JjprjjGenerated line 298 Device Tree Im an 8 er 3 Undefined reference cpu handle P4080 v2 pri Generated_ line 308 Device Tree Undefined reference cpu handle P4080 v2 prj Generated_ line 318 Device Tree o Co wem qu Pu tga 7 291 Cy ra OAF rp Owe tte ben 7 wy mci 4 Powe 1
101. dbeef 00000000 0 ffe02130 03000000 00000000 00000000 00000000 02160 00220001 02401400 00000000 00000000 ffe02170 89080600 86751608 00000000 00000000 Address Information e gt md ffe02b00 Beginning memory address read from memory dump file ffe02b00 00000000 00000000 00000000 00000000 DDR Controller memory address 702000 Use default ffe02b10 00000000 00000000 00000000 00000000 ffe02b20 5dc07777 77000000 00000000 00000000 J www Save content to a file gt e 9 freescale Device Tree Edito Lab 5 Changing the thw oun Cong TES T Coder Cotten Comma C Waw the freerge w W wa t od aan api wiki POS Perr LOC Anr Far oa Cowen Sale oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Device Hands on What we will do e Define hardware device tree for P4040 starting from P4080 device tree Import the P4080 which has 8 cores Configure to P4040 which has 4 cores Note P4
102. dn vary 20 s ONRIIE W ats wa T AL a DPAA Hands on Conclusions e Outcome generated code for DPAA Hands on In order to accomplish DPAA hands on requirements the following initialization code must be written 220 lines of XML code 750 lines of C code Benefits of using QCS DPAA By using QCS DPAA tool the same result can be accomplished as follows Requested configuration accomplished in approximately ten minutes Configuration done by using a few mouse clicks and visual parameters settings Provides an easy to understand overview of the entire DPAA hands on architecture DPAA tool helps accomplish your desired configuration by highlighting valid choices and prevent you making invalid selections by performing automatic constraints checking by providing instant access to configuration settings by displaying relevant summary of current configuration by immediate code generation at request in any stage of your work 4 freescale 16 freescale
103. e PCle ER 4 Boot Configuration 4 Boot ROM Location SHIO and amd 94771 ad oe etu ev cfg rom lac 0 3 061111 Local bus 8 T S E C 1 TX ER 0 LS I BAAS Gee SOME aTSEC2 1 25 Giga 71 SOME eTSECI 4 Boot Sequencer Configuration e 22 0a 25 5800 5 Gipi SOME TSEC2 p 0 25 71 SGMEeTSECI cfg boot seq 0 1 0611 Boot sequencer disabled GPL3 LFWP_B LGPL5 SMOLOXQSG SGMBSTSECI pt 1 25 1 SOME aT SECI 104 Gaga PG Enpresa 2 di 25 Gg 3 SGME 2 xd 125 Gen 71 SSME eTSECI C 4 CPU Boot Configuration AEs Os Cap CY eTSECI cpu boot Obl CPU allowed to boot default Pins LA27 1 Port chg smi ruit alio be jog e xd Stn for eTSECZ te SOME mode cfg cpul boot 061 CPU allowed to boot default Pins LA16 2 Port mant be logic additam tor aT 4E C te eperme m SOME mode t High Speed I O Configuration 4 Lama f gt General Purpose POR Configuratior Series UDO Selection power on reset comiguistion fg ports n3 Engineering Use POR Configur Sees une E SOME T SECI bl gt Sees ue 3 OD gt Sees ime 0 S 1 iu one 1 SOME 4 Pin Multiplexing Configuration 100 gt lana 2 SOME sTSEC3 21 gt Sarwa lana eTSEC1 Configuration cfg tsec reduce tsecl prtcl
104. e prod summary jsp code PE QOHIQ SUITE amp tid PEH ee e Z freescale ue arme Me We Fehr oret vee D og Mah a File Edit Navigate Search Project Run Processor Expert Window Help F3 H Q iB m e S ES S Processor Ex i r ac e ERES EZ testi oe Documentation Propertes Import e e Generated Code Name A SRDS_PRTCL 128 133 2 SerDes PLL and Protocol Configuration EG Bak3 ddrCtri 2 cfg SerDes Reference Clocks ale lco E e T H li a lc lola elelo SD REF CLK1 MHz Debug b 0x02 8 anaes Le SD REF CLK2 MHz 5 2 5 PEE bw 22 Guo nM Lb 2 i Debug pom ES pn gt Sources TIO R3 Pow 2 Gus modsi CO se 5 2 56 B ProcessorExpert pe SerDes PLL 1 Clock EM2 4 1 Configurations SRDS DIV Bi 139 143 GMI Debug fb PaoS0 v2 0 SRDS DIV Bi Lanes 139 E E Operating System SRDS Bi LanesC D 140 b es _ AxSGMI Processors SRDS DIV Bi LanesE F 141 ees Cu GB 4080 v2 0 SRDS DIV B1 LanesG H 142 1 drin en Embedded Components ee Anas RO sHOi Debug lf PBL1 PBL SRDS RATIO B2 144 146 z DDR mci DDR SerDes PLL 2 Clock SerDes Protocol Select NM Bo SRDS DIV B2 147 Bits 128 133 HT DDR mcz DDR Se E EN mE E E SRDS RATIO 148 150 For additio
105. ee Editing DPAA Configuration v Provide Optimization Tools to support runtime visibility into these complex parts to help calibrate and debug your systems DDR validation tool to ensure DDR functionally configured for custom board Scenarios tool for collecting and visualizing runtime trace data Packet tool for understanding the flow of packets within a QorlQ device Se 2 freescale freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Why QoriQ Configuration Suite Configuration of QorlQ processors is increasing in complexity Even more complexity is around the corner We support many many configuration settings Reference manuals are huge and intimidating to new customers Configuration problems during board bring up are HARD and COSILY Learning command line tools requires more training etc Solution Strategy to solve these problems o 2
106. eparately Current version is v1 3 and is available from the Freescale website use Buy Direct to purchase online l DDR Validation Tool Activate Component Inspector x Bv Properties gt Import Export Validation 125 p2020rdb pcal e D Mame Value Details gt ocumentation m Device DDR Controller 1 DDR Controller 1 gt gt Generated Code M emory type Sources S eS DDR Bus Clock 400 MHz DDR Data Rate 800 MT s Type of DIMM Unbuffered DIMMs Configurations P2020 Cnf Operating System a Processors a SDRAM Control Configuration gt Control Configuration 1 gt Control Configuration 2 gt SDRAM Timing Configurations 4 Auto adjust chip select addressin yes Chip Select Enabled 4 Memory Bounds Start Address 0 Size 1 GB 4 Configuration Auto Precharge Always no Internal Banks Number Number of row bits Number of column bits amp internal banks 14 row bits 10 column bits ODT for writes confiqurati Assert ODT only during writes to C ODT for reads configuratic Never assert ODT for reads Partial array self refresh t Chip Select 1 t Chip Select 2 p Chip Select 3 License file lt QCS Install directory gt eclipse Optimization license dat oe 2 freescale Full Array Disabled Disabled Disabled fw v p v Ar Caint CoA ww 1 27 C
107. ernal Banks Number 8 internal banks Number of row bits 14 row bits Number of column bits 10 column bits ODT for writes configurati Assert ODT only during writes to C ODT for reads configuratic Never assert ODT for reads Partial array self refresh Full Array t Chip 1 Disabled p Chip 2 Disabled p Chip Select 3 Disabled e 22 Pw Fee tun Aw OE Coop TEST C Lge res Swe P Sete rode POD Pes DUCIT 1 13 Caper Corwen Eth Te Aaa Sy vore and av Pec baracoacdkatnr mc US te i tre OT oe Artar 7 Pouch fee Mew VET Q OC Pegs Pwy molo Vi a ma te lt be ews Feu kawan kzim Wo 208 25 eo wa Te W Tus ete eret X111 Hewes Serer ore Review DDR registers values n5 Project Panel 125 p2020rdb pcal gt la Documentation gt Generated Code gt Sources 5 ProcessorExpert pe 4 Configurations P2020 Cnf Operating System Processors gt SoC P2020 4 Embedded Components DDR madra Inspector Properties x Component Inspector s Import Export Validatic Name Device Memory type DDR Bus Clock Type of DIMM Bus mode SDRAM Control Configuration Control Configuration 1 Control Confi
108. figuration 3 1 25 G h Z 8 n k 1 lan e SerDes Reference Clocks SROS EM 178 Ubi SerDes enabled E F G H Set to Divide by 1 SRDS PRTCL 128 133 xf amp Bank f AG ae F E 5805 RATIO Bi 136 138 DbD10 25 1 SerDes PLL 1 Clock 3 125 GHz 5805 DIV B1 139 143 SRDS DIV B1 Lanes AJB 139 ObO Divide by 1 off of Bank 1 PLL SRDS DIV Bi Lanes CIO 140 Divide by 1 off of Bank 1 PLL SRDS DIV B1 LanesE F 141 Divide by 1 off of Bank 1 PLL SRDS DIV Bi Lanes G H 142 b Divide by 1 off of Bank 1 PLL SRDS DIV Lanes 11 143 Divide by 1 off of Bank 1 PLL SRDS RATIO B2 144 146 ObOOO 10 1 SerDes PLL z Clock 1 250 GHz 5805 DIY B2 147 obo Divide 1 aff of Ban SRDS RATIO BS 148 150 DbODD 10 1 SerDes PLL 3 Clock 1 250 GHz 5805 DIV BS 151 b Divide by 1 off OR Bank 3 PLL E SRDS LPD 152 161 Set SRDS LPD B1 Lane 152 Lane not powered do SRDS LPO B1 LaneB 153 Lane nat powered down S RDS RATIO B2 to 10 1 PBLi pbl 2 A455 A55 0100 1054 0000 00000010 iEIE 181E 0000 cCCCC 58430 OOOO 000 00000020 FESO 0000 6100 0000 0000 0000 oooo 0000 SGMII requires 1 250 GHz OOOOOOSO OOOO OOOO D SE B000 OOOO 00000040 0000 D000 D000 oooo 0813 8040 B153 SSE2 on Bank2 and Bank3 2 freescale w
109. ft xfeiz4000 0 1000 gt ranges 0 0 Oxf Oxes000000 0x8000000 0 Oxf OxffdfOOO0 0x8000 compatible fsl p4080 elbc fsl elbc simple bus interrupts 25 2 0 D gt address cells lt 2 gt NS lt gt gt 31 2 freescale dw SS Memory Map 23 OxF FFDF 0000 FFDE FFFF FFOO 0000 FEFF FFFF FEOO 0000 OxF FDFF FFFF OxF F803 0000 OxF F802 0000 OxF F801 0000 OxF F800 0000 F7FF FFFF OxF F440 0000 OxF F420 0000 OxF F400 0000 OxF F3FF FFFF OxF F000 0000 EFFF FFFF OxF E800 0000 OxF FFFF OxF 1972000 ser 0100 OxF 0000 0000 FFFF FFFF DxC 6000 0000 OxC 5FFF FFFF 0xC 4000 0000 OxC FFFF DxC 2000 0000 OxC 1FFF FFFF OxC 0000 0000 a a 38 ENTIRE ADDRESS SPACE Ibe localbus ffe124000 pcil 201000 pci pcie FFe200000 Ibe localbus ffe124000 pci0 pcie ffe200000 freescale LS Data Path i g To O e A 0 thw oun Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge w W wa t od aan api wiki POS Perr LOC Anr Far oa Cowen Sale oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS
110. guration 2 SDRAM Timing Configurations Auto adjust chip select addressin Inspector Pinned Component Enabled Remove Component from Project Help on Component Save Component Settings As Template Configuration Ka Cc Ts x 2 freescale Partial array self refresh wii LE Nw C5 CodsTE Y C x Cn 1 14 kuer Gowen Dn ta Satanas Sew T v Lo mt gt w Qe wies Head Pwy mw umo yi atc E Atar fast Cowie Tm 4 w t iios am lb Review DDR registers values contd DDRI C52 BNDS DDRI C53 BMDS DDRI C50 CONFIG DDRI 51 CONFIG DDRI C52 CONFIG DDRI C53 CONFIG DDRI CS0 CONFIG 2 DDRI CONFIG 2 DDRI C52 CONFIG 2 DDRI C53 CONFIG 2 DDRI THMING CFG 3 DDRI THMING CFG 0 DDRI TIMING CFG 1 DDRI THMING CFG 2 DDRI SDRAM CFG DDRI SDRAM CFG 2 DDRI SDRAM MODE rr bt PR P Init value 00000000 00000000 80014202 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00050000 00330104 6E6B8846 DFAS DOLL 47000008 24401050 dh anm anm onm orn te Ta After reset gt C30 BMDS 00000003F 00000000 p DDRI BMDS 00000000 00000000 00000000 00000000 000
111. hanging boot configuration to allow booting Media Independent Interface MIT 061 eTSEC in standard width mode Pins EC MDC ObO1 eTSEC in MI or mode Serial Gigabit MI SGMIT eTSEC in SGMII mode Serial Gigabit MII SGMIT eTSEC in SGMII made Pins TSECI TXDO TSECI TXD7 Pins LGPL1 Pins 1588 ALARM OUT2 102 001111 gt 000111 4 Boot Configuration 4 Boot ROM Location cfg rom loc 0 3 4 Boot Sequencer Configuration Pins TSEC3 0b1111 Loca bus GPCM 16 bit cfg boot seq 0 1 0611 Boot sequencer disabled Pins LGPLS LFWI 4 CPU Boot Configuration cpu boot Obl CPU allowed to boot default Pins LAZ cfg cpul boot CPU boot holdoff Pins LA16 Pins 1 5 TXD 3 1 TSEC2 TX ObO Ob1 4 Boot Configuration 4 Boot ROM Location cfg rom loc 0 3 a Boot Sequencer Configuratig cfg boot seq 0 1 4 CPU Boot Configuration 061111 Local bus GPCM 16 bit Pins TSECS TXD 0611 Boot sequencer disabled Pins LGPL3 LFWI cfg cpu boot Obl CPU allowed to boot default Pins LAAT cfg cpul boot UDU LFU boot holdoff Pins LA16 ge Aw C 5 Cedo TEXT C yanuta hpa Corm pa P Pont Suk kwa go eet POL Peewee Caper Gerona Te Satanas and an adea ot
112. iming Configurations E DDR_mc1 DDR Auto adjust chip select addressin yes Chip Select 0 Enabled 4 Memory Bounds Start Address 0 H Size 1 GB 4 Configuration Auto Precharge Always Internal Banks Number 8 internal banks Number of row bits 14 row bits Number of column bits 10 column bits ODT for writes configurati Assert ODT only during writes to C ODT for reads configuratic Never assert ODT for reads Partial array self refresh Full Array t Chip 1 Disabled p Chip 2 Disabled p Chip Select 3 Disabled Pw E koga 2 Code TERT Cogelfumes C Oo vos pa Pro Energy Pont ukiwa 35 POG e 18 Caper Coruna Ts Satanas Sy vore and Vora ane Preece Zenecomdtar mc US te ite Of festo Cote fee Migr VOC Parton 4 Pep Sori h Pwy moles yi ma te lt we iwa kawan Akzuim Wo t O Gw 20 275 4 eo eub wa Te W Tus waw q uru Va Review DDR registers values n5 Project Panel 125 p2020rdb pcal gt la Documentation gt Generated Code gt Sources 5 ProcessorExpert pe 4 Configurations P2020 Cnf Operating System Processors gt SoC P2020 4 Embedded Components DDR madra Inspector P
113. ion P2020RDB PCA From P2020RDB PCA rooz t mi Dam ele L 33 gt Micron DDR3 SDRAM From MT41J512M4 64 Meg x 4 x 8 Banks E MT41J256MS8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks o 2 freescale How about rest of the timing parameters Table 1 Key Timing Parameters Data Rate MTis Target RCD RP Tool automatically 9931234 M BO B um computes tRCD 6 13 13 13 1391 1391 1391 and CL qu o 11 11 11 BJ 1375 User can change s s J o s these values if I 171 B Bl B required Features Options Marking Configuration n Von Vppo 3 SV HOSS S 2 Meg x 4 12M4 e 1 5V center terminated push pull 1 0 256 Meg x 8 ISAMA Dillerential bidirectional data strobe 128 Meg x 16 AMIR Hn bit prefetch architecture FBGA package Pb free x4 e Differential clock inputs CK CRY Tit ball 8mm x 10 5mm Rev 1 DA B internal banks TB ball 8mm x 11 5mm Rev D HX e Nominal and dynamic on dic termination ODT e FBGA package Pb free x16 for data strobe and mask signals 96 hall Omm x 14mm Rev D HA l rogrammable CAS READ latency 96 ball Smm x 14mm Rev r1 Posted CAS additive latency AL e Timing cycle time e Programmable CAS WRITE latency CWL based 938ps amp CL 14 DDICI 2133 093 CK L inse
114. ion Primary DDR non cacheable Exceptions Callback NULL Automatic input validation configuration Use error IRQ constraints checking and instant display Partition number of Faids 0 of relevant conflict messages Runtime Frames depth 30000 Pfdr threshold o FMan Pork SFdr reservation threshold M E H Frame Manager Port non PCD Port Id Port name MAC address InterFace Rami Speed 1 Gbps M 4 oon g Pw homie dr w Era 9 79 w 36 lt a gt Xu G Tue fe us OA A We 13 NUMAE TM rta o w we ne Ah wa Pater 4 wi bert 42 an i QCS DPAA Component Features 2 S Companent Inspector 52 e On the fly wu NEC ONCE 2 s configuratio T n validation 44 45 highlighting correct choices and graying out the invalid ones il E e gt F r FOIDs 1 j 1 200 2d Zoom 100 Basic link 546 248 QCS DPAA Component Features 3 5 Companent Inspector e 1 ipv4 1 Distribution FMan service Instant display of Hz relevant configuration p summary for each DPAA element Fa rm r range 39 39 Extracted protocols Extracted Fields Mane J Combined Fields None FOIDs 1 j 1 200
115. isted can be combined to IT 14 14 14 13 13 13 11 11 11 13 09 13 91 13 75 x 1309 13 91 13 75 111 13 1 13 1 define an offered product Use the part catalog search on http www micron com for available offerings Tool automatically computes tRCD and CL User can change these values If required 13 09 13 91 13 75 13 1 Pu i alus tga fhe Cadel C jan COF Ca or r Ta eb iwaw mn Perce mc Beg US Tx 7 OT Liem veys 727 g 71 a amo ot V a Mwy QCS project explorer Component x Properties E zm m l p2020rdb pcal Mame Value Details t gt Documentation Device DDR Controller 1 DDR Controller 1 t la Generated Cade Memory type DDR DDR Bus Clock 400 MHz DDR Data Rate 800 MT s Ry ProcessorExpert pe MA E Type of DIMM Unbuffered DIMMs Configurations Bus mode 64 brt bus P2020 Cnf Operating System a Processors gt SoC P2020 SDRAM Control Configuration 5 Control Configuration 1 gt Control Configuration 2 t SDRAM Timing Configurations E DDR_mc1 DDR Auto adjust chip select addressin yes Chip Select 0 Enabled 4 Memory Bounds Start Address 0 H Size 1 GB 4 Configuration Auto Precharge Always Int
116. l Confiquratic fe Sources Control Configuration 1 ProcessorE SDRAM self refresh durir Enabled E E Confit New ECC Error Checking anc Disabled P Open Dynamic power manager Disabled gt Oper Open With Beat burst made 8 beat burst Warning DDR must use 4 beat burs E E Cpus Timing mode 1T Timing E D 5i Copy Ctrl C I O Driver Impedance Full Strength Bd Embe E Concurent auto prechar Enabled Pl Delete Delete 2 D Mave InitbdrRegiskters 1 6 main c 49 D Rename F2 ua Import HERHEHSEHEHESHEEHSHHESHSEHEHHEHEEREIHHEHREHS Ss Components Libra zorExpert DDR Tool memory initialization EUER ategories Alpha P 2 Refresh F5 oller 1 Registers ILS ips Shaw in Remake Systems view zi E Configuratio Clean Selected File s 1 CFG 8 DDR Build Selected File s 110 0 47040000 PBL z Generate Processor Expert Cade Run As PULS 1 OxFEOQOSOO0 Dx3F ebug 45 i k Profile 4s ENDS Team em l xFEODSO008 Ox0040007F Compare With k Replace with k CONFIG Properties Alt Enter em 1l OxFEOQOSOSO Ox60044202 CONF IG isassemt em l OxFEQOSO84 xS g g4z 0z Make Targets k CONFIG 2 Show In Windows Explorer em 1 DxDD 4 2 Fw mpm ote nd 7 r 3o wi m rode
117. le connections setu reca wo DE Coto TET Cera Con mms Carn Pe Energy Caper Corona awka Ta Aaa and av adea ot F wawcate mc Re US Tx 87 C a TM 48 Atar festo w 4 Gort Py SMAI MOS mw molo Yoo 4 and s Ferca Wa ord o wa Te ery erat CXII Ya Properties Import Export Checl the Choose DDR tests to be executed scenarios to be tested Test TBD s Validation stages Stagel 2 Centering the clock Read ODT and driver Write ODT and driver Basic Testing Double click DDR Test on test to see its content Select Test Options Run times i EJ nd Choose which test to be executed and how many times Start Validation e reca fre kuqa AAwa OE Cedo TET OAF ire Coh mes pa Egy Dont Soka ao Sete FEO e 9 49 Exper Coruna Ta Satanas Spree and Vora ane cadena ct Preece Zarecondote mc US Tx OF 4 fr I TM Artur w 0 Facius Dort Mey mw iol eth td and we s Fusco Wa 4 bive nene Aa
118. le oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Installing QCS should be done already DAPEx Sessions AMF ENT T1020 QCS QCS233 zip Skip if you already have QCS v2 2 installed Setup for labs Create a directory where you have read write permissions Eg C QCS221 from now we ll call this directory lt qcs gt If you already have QCS installed use that directory as lt acs gt Follow the instructions in lt qcs gt labs QORIQCSINS TALLUG pdf 4 2 freescale freescale Pre boot Loader Lab 2 Custom Hardwa thw kam Se C 5 Cong TES T O Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Far oa Cowen Sale oae Wa bantuo Sir ren Symptom ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher w
119. ll the fra DpaaAll py All Enable FM Timestar Dverview of the DPAA activity FM1 and FM2 mark all the fra DpaaAllEnableFMTstamps py DPAA FMI Dverview of the FM1 activity FM1 marks all the frames ford DpaaFMI py Dverview of the FM2 activity FM2 marks all the frames for d DpaaFM2 py 1 and FM2 mark all the frames for debug but do not gene DpaaQM py Decode Only Decode an existing DPAA binary trace file The target connec DecodeTraceFile py 4 n LA mtm aai a OT gun th ha va lb MS LL g Scenarios e Python scripts containing predefined trace setting configurations e he scripts use the tool s API for configuring the DPAA trace settings he tool ships with scenarios for tracing all frames in FM1 FM2 and QM for tracing frames only in QM only in FM1 etc Also available a scenario for analyzing trace from a file The users can define their own scenarios 2 freescale 0 Configuring the Packet Tools Trace buffer DP AA All Enable FM Timestar Overveew of the DP NPC Nexus Port Controller 16kB buffer for non intrusive trace collection Oude el e DDR trace buffer located to the system s external memory large capacity Buffer Trace 4 NPC H 4 DDR Intrusiveness depends on the Notes x j sys
120. me Use quad ranked DIMM no Address Parity Disabled Register Control Word Disabled Corrupted data feature Enabled SDRAM Timing Configurations Chip Select Enabled Memory Bounds Start Address 0 H p endis lt Coal res C ben x iere ug e 9 123 Unete UK Pul Uit Ginna GGe Bipe hah Maf SILO a freescale Ut of 4 ove geb wa Te TV Sete erat ax wa 4 bru Fees muon V DDR Step 4 Generate DDR Config File Processor Expert p4080 Generated_Code ddrCtrl_1 cfg CodeWarrior Development Studio File Edit Navigate Search Project Run Profiler Processor Expert Window Help 1 d 4 E37 lal amp mi iF o uz Project Panel amp T amp Component Inspector 22 w z i 2020rdb cored Properties TT p4080 Documentation neme Value Details Generated Code Component name DDR mcl 2 1 cfg 2 Device DDR Controller 1 DDR Controller 1 E z cfg Memory DDR 3 Warning DDR3 must use 4 beat burs c InitbdrRegisters 1 c DDR Data Rate 1333 MHz DDR Bus Clock 667 MHz InitbdrRegisters 2 c of DIMM Unbuffered DIMMs Bus mode 64 bit bus Warning DDR3 must use 4 beat burs Le p4080_v2 005 ddr c PBLI pbl m SDRAM Contro
121. mode 64 bit bus Pricing 995 License file lt QCS Install directory eclipse Optimization license dat Se 2 freescale 47 X1 omponent Inspector Basic Advanced Expert 7 E Properties Import Export Vali datior Choose DDR tests to be executed Test results Test Validation stages f Stage 2 Centering the clock Read ODT and driver Write ODT and driver Dcycles 1 8 cycles 1 4 cycles 3 8 cycles 1 2 cycles 5 8 cycles 3 4 cycles 7 8 cycles 1 cycles 0 clock delay l 8clockdelay 11 4 clock delay 3 8 clock delay 11 2 clock delay 5 8 clock delay 3 4 clock delay 17 8 clock delay 11 clock delay 9 8 clock delay 5 4 clock delay Test stages scenarios WRLVL START Select Test Options 11 8 clock delay 3 2 clock delay 13 8 clock delay 17 4 clock delay 115 8 clock delay 2 clock delay 17 8 clock delay 9 4 clock delay 19 8 clock delay 5 2 clock delay Test Run times Pattern Write 0 Read Write Compare Walking Ones Walking Zeros 0 0 0 Tests to be executed per each scenario start Validation Connection settings Remote system IP 121001 Co nn ect on Availab
122. n Test Result Validation stage EJ Centering the clock 4 100 E Read ODT and driver LE Write ODT and driver Ed Operational DDR tests Click cell to choose optimized ODT value e 9 wem Pu 711 Alar re Cor rrey 3o Sow ro 132 gt Cowes Vor A aw C Fasc LN COCOS ITI t heg te ite Beets wn Mage v 4 Pea Ege Py TEL be ewes faici Damon Wo OC Te fus ee Aan X111 wee Daraa Ya DDR write ODT and drive strength test results Sy Component Inspector 5i Properties Import Export Validation Test Result Results Choose tests amp Validation stage Ej Centering the clock 100 EN E Read ODT and driver E9 Write ODT and driver Ed Operational DDR tests Full Strength E ca k 2 Bl Click cell to choose optimized ODT value A lt lt e 9 wem wu Fw L ymi W tae a Fra OU res Sec 133 roce Ces Co L Laune vf ad Vora ade sux Feeecate Lanecom tz heu Tx itr TM rta Sects C t Mow
123. n Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc BOOTROM Configuration tool Lorrgonem inspecto Adyanced Exper ie ant D BOOTROM BOOTROM twice Powe On Reset Confugut ation s FLUC s COB Check i SOK Helps in Power on Reset POR OO a E tnt Cin Ker the valor OWO 41 0000 44 device configuration by definition of 5 values for POR configuration signals 2 and generates overview report LL including POR value required for LN each POR configuration pin device specific ne P ttn e Helps in building a configuration w to be used in a boot image creation process boot format for various memory interfaces a V fe mp tmn 4 6 h ote eo U rp Louvre 9n Levy tit ry ww nct 2 MIC 1 096 Caper Orar Ta Getter and Vora cadens lt lt Preece mc Re US Tx amp 7 O08 e TM Beets Isatis Vasa 1
124. n port channel to be used for transmission FMan1 PCD flow Traffic received by FM1 porti is 2 split in IP frames and other m lt m frames by Policy1 ipv4 i w NG Channel w0 distribution Ponal 0 1 TRU IP frames classified in of the n 3 defined ranges of IP source are directed into FQIDs 43 45 21 201 All other IP frames are classified by MAC destination and are directed into FQIDs 46 amp 47 All other non IP frames are directed FQID 32 4 2 freescale bi Lab 4 DPAA Hands on 1 Create a new QCS project called Lab4 1 Choose P4080 2 0 2 Choose a DPAA component and select empty component 2 Maximize the DPAA Component Inspector arm Fakir E CUERS ES ITSS Fe Edi Nyipati Seach Wn Process Expert Widow Heb r ug We t T Pace e ub gt p Leere Cost ie Sources ie S 99 2 0 OF 5 i gt Cos T uon 20 K gt Erbedaec Corponents d cea E Poders e Co e 9 2 freescale See 1 BO B th IU F gt wam pt o ERR 4 5 4 dmm 222 149 11 4 vacas Er tage Sour h ie ES 0 mant eraga Port rz fC Oo tarot Port are
125. nal information see description of the SRDS PRTCL field in device documentation This item modifies SRDS PRTCL5 SRDS bits in the RCWSR5 register Seres PI 3 Clock fru Aha como 1 A Me DD Ta d FEF EE 1 Robes FE Ee Bord 0000000 0000 00000010 C 11 0000 00000020 0000 00000030 gi T i 0000 00000040 0000 0000050 0 0000 00000060 C 0000 E Problems Console Writable Insert 2 2 freescale reca fw yaaa kuqa Wao DE Coto TET Cera Con mms Wapa Pe Energy Dont Setters go est POD Exper Corona Eobhan Sy mprem and av adea ot F wawcate mc Re US Tx amp 7 OF Atar festo w 4 Gort Py SMAI MOS mew molo ym and oc nene wa Te wayaw twa erat CXII ucu ore Ya What s Different About QoriQ Processor Expert MCUs use Processor Expert to generate source code that is code size optimized and only includes the minimal functions and operations to support initialization and peripheral drivers Previously Processor Expert was included CodeWarrior only Now Processor Expert plug ins can be installed into any Eclipse Processors uses Processor Expert to generate configuration 4
126. net4 w geneti FowerPC eSa Linssi 23 101 ethernet5 enet5 H cpu PowerPC 5004 M ethernet 4enet PowerPC e500mcog5 23 ethernet amp e het7 5 Properties 14 ethernet amp ienecb cpu PowerPC c800mct7 This secbon describes information about the selected node s properties m ethernet dest deseipho0000000 36 serialo Pariato bman portaisgp f4000000 gt x 37 seriall lt seriai qman portals ff4200000 Name Value 5 serial sot cesr w serials di t apickogrfeocoono dest AR 3 24000 mis 5 m poedbife 200000 etherneti gt pc lt pell poepifa201 000 x uabO tubo paedpffezccpon 2 enet2 ethernet ethernec4 _ ethernecs ethernet text Device tree lt lf Problems Console 1 _ Text to be searched based on some sen 20 matches n working set 5 dea m 1 dts 271 matches Case serative M whale word 17 serial gt sensi e Regdar expression To wea Select zero one or more options 35 geri serapticsoo 5 gt 5 type serial us 2 gt WW D11 600 1 Worepa
127. nmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc 6 DDR Configuration Lab 4b Changing the Configuration Startinc DDR Step 1 Dump u boot DDR Registers U Boot 2010 12 00001 0612800 Jan 28 2011 22 20 46 Deploy S DK2 Ou boot CPUO 4080 Version 2 0 0x82080020 Core E500MC Version 2 0 0x80230020 Clock Configuration CPUO0 1499 985 MHz CPU1 1499 985 MHz CPU2 1499 985 MHz CPU3 1499 985 MHz CPU4 1499 985 MHz CPU5 1499 985 MHz CPU6 1499 985 MHz e No interleaving CPU7 1499 985 MHz T 799 992 MHz fs dd r cti ntlv null DDR 649 994 MHz 1299 987 MT s data rate Asynchronous LBC 99 999 MHz FMAN1 599 994 MHz FMAN2 599 994 MHz PME 399 996 MHz Use CW to con nect L1 D cache 32 kB enabled 32 kB enabled Board P4080DS Sys ID 0x17 Sys Ver 0x01 FPGA Ver OxOc vBank 4 and d u m D D H 1 36 bit Addressing Reset Configuration Word RCW DDR2 registers 00000000 105a0000 00000000 1 1 181 0000cccc 00000010 40464000 3c3c2000 fe800000 61000000 Memo V browser 00000020 00000000 00000000 00000000 008b6000 00000030 00000000 00000000 0
128. nternal Banks Number Number of row bits Number of column bits internal banks 14 row bits 10 column bits ODT for writes confiqurati Assert ODT only during writes to C ODT for reads configuratic Never assert ODT for reads Partial array self refresh Full Array gt Chip Select 1 Disabled p Chip Select 2 Disabled gt Chip Select 3 Disabled Pricing 995 License file QCS Install directory eclipse Optimization license dat fe mp tae h C b jamu Co res 0 Bee IP E yy bw Shore eet m mei i A 1 135 2 Gowen Ta Byron and were ot Preece Zerecondura mc He US Tx OV e TM ert Pesto Coste em nmm Mage VOC Parton v 4 DC Dongs Enga Pwy umo na ym 4 AZ Ow Te 4 V waw ivl 13 eee be P2020RDB PCA Import DDR configuration from existing system running uboot At uboot prompt gt md ffe02000 ffe02000 0000003f 00000000 00000000 00000000 x Basic Advanced bpet h B ffe02080 80014202 00000000 00000000 00000000 ffe02100 00030000 00110104 61608846 Ofa8c8cc seh OKT E emory Dump File ffe02110 c7000008 24401040 00441421 00000000 CA Users 00086 Desktop p2020ddrv_ubootdump te ffe02120 00000000 0c300100 dea
129. ow cvs Disabled v pcie Oxffe202000 Low kc HOF pcie 0xfF8000000 AS E pcie OxfF8010000 Active High pcie OxFF8020000 High to Low lt o T wem Fw mp lite i dett re Loe ppi Levy it et os 4 re gt 8 20 Ces Cowes AUN lords ane Sere c7 Freeecate Lancome cts us s P t t Ces yer w 1 rt U 0 rpm Mwy MAJ w Lot V e trma we xeroka ot Kawucnhaty Wu Sofas RET 24 ove wa Te A y id ete X11 Ya Memory Map view Sy Memory Map 23 ENTIRE ADDRESS SPACE localbus ffe 124000 Any hw device tree can be seen FFD 0000 OxF FFDE FFFF P AH ed localbus ffe124000 Local Access Windows LAW E FEOF EFF Each LAW maps to a specified target interface such as DDR DoF FOE PPT OxF F304 0000 Controller Localbus Ex D re S S y etc es pcil n xF F800 0000 pcie FFe200000 Each device tree node having reg see and ranges properties defines a 2 memory range inside outside 2 Configuration Control and Status Qus OxF F000 0000 R e Q ste C C S H S D ace re a localbus ffe124000 The Memory Map view pops up J automatically when a device tree B component 15 selected inside OxC 600
130. performance issues anywhere the system a a e 2 1 E Parts Peal te nou i y wa ghee 6 Fart To TA UCU b v i e e y M z What is Visually identify the system level problem areas in seconds T 2 freescale Tool fle Hep 0 LCJ Protect Eom U mano i l perf arca h 2 nn 01 08 1 15 29 07 Raw Event Counts per sami M 201109 11 16 21657 A re DOR SIMPLE 0 READ CYCLES 2 i nn 200 08 11 19 282821 CPU Core Complevtrafh Cache ope snd csd 8 ee Bh W D CPU Branch Mes baba a DORT SMPLE WRITE CYCLES 3 b Sonst T HU Meses and dota TUB revo 1 DOR 2 FORCED PAGE CLOGINGS NOA at CPU gt MMU avi patan ere DOR SINPLE 3 FORCED PAGE CLOSINGE 0 P 5 Eben tcd 25 DOR BIMPLE 4 FORCED CLOSINGE FROM Chu Intemugts a D CPU CPU usage m Superior and User prse i CPU CPU utfigalion and IPC 41 COU Coche operations DOR CCA fk 5 veda M WI DOR COR psge mires and a 0 7 gt Offline Configeation binave it Sted Run troe Messurement ag gt apd Auria Core w Run time Measurement SEC L Aurime PM i
131. ree represents the hierarchy and routing of interrupts in the platform hardware The left side displays the actual representation of the Interrupt tree starting from the root interrupt controller The right side displays the interrupts sources for the selected device tree node Device Tree Properties Interrupts Interrupt tree lt Propert wes gnarcportalipof 4 204000 interructs qmarrpottakpO fF 1208000 Interrupt number wvelfcense c quoq UN 233 Low to High qmanrportalipofr42 10000 234 Lew bo High 4214000 235 Low bo Hugh ganarcoortalposff42 12000 236 Low bo High gnac portalpos f 42 1c000 23 Properties qmareportalposff4220000 ow Interrupts pos 4224000 ongast e000000 d Interrupt number Interrupt level sense s v jy to Low eror y Controllardp0 ffa00600C 16 Active High memor y contr oen posfte 0wCfc 5 cache comtrober 0 7 Het 000 pore 6015000 0 f hele Oo 600 041800 Domain map eo4 t messager td edd 090 Dev 2 139 o eer l Parent interupts lt Child interrupts Int 1 Int 2 Int 3 Int 40 rapidio 0xffe0cO000 INTA Disabled Disabled v Disabled localbus 0xffe124000 INTB v Disabled x Disabled v Disabled pcie Oxffe200000 INTC Disabled BUSINESS v Disabled Disabled pcie OxFfe201000 INTD Disabled Ni Disabled Actwel
132. roperties x Component Inspector s Import Export Validatic Name Device Memory type DDR Bus Clock Type of DIMM Bus mode SDRAM Control Configuration Control Configuration 1 Control Configuration 2 SDRAM Timing Configurations Auto adjust chip select addressin Inspector Pinned Component Enabled Remove Component from Project Help on Component Save Component Settings As Template Configuration Ka Cc Ts x 2 freescale Partial array self refresh e gt Cadelt ats 1 9 Caper eu Te Gotten P Qe wies Head Pwy mw umo yi atc E Review DDR registers values contd DDRI C52 BNDS DDRI C53 BMDS DDRI C50 CONFIG DDRI 51 CONFIG DDRI C52 CONFIG DDRI C53 CONFIG DDRI CS0 CONFIG 2 DDRI CONFIG 2 DDRI C52 CONFIG 2 DDRI C53 CONFIG 2 DDRI THMING CFG 3 DDRI THMING CFG 0 DDRI TIMING CFG 1 DDRI THMING CFG 2 DDRI SDRAM CFG DDRI SDRAM CFG 2 DDRI SDRAM MODE rr bt PR P Init value 00000000 00000000 80014202 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00050000 00330104 6E6B8846 DFAS DOLL 47000008 24401050 dh anm anm onm orn te Ta After re
133. s View By Frames Processed Processing Path Details Part Processing Path 2 2D L j 0 Frames Processed DPAA Engine Analysis OAT Da uror TOC rr P Source Path 1 Latency Platform Clock Cycles Sort By Latency Value 1 a Alys Lieta tate 5009 enhigurati on Note 4 x e 9 freescale Al Frame Details an string any character Path Frame Event 4 Path 2 4 Frame 0 1 Enqueue by SwPortal Dequeue py SEC Enqueue by SEC Dequeue by Sw ortal frame 2 frame 3 Frame 4 frame 5 Frame 6 frame 7 One 030600 9818866 9818922 9825284 9825332 Latency Details Sequence 1 SwPartal gt 2 QM QM gt SEC 4 SEC 5 SEC gt QM 6 7 QM gt SwPortal FQID 9003 CID 0 FQID 9003 CID 2112 FQID 9002 CID 0 FQID 9002 CID 0 e freescale Pw gn AN wo C 5 Cedo TET Cra Con rms Stee P Port go net POL Peewee 72 Caper Ta Satanas Sumu and adea ot F wawcate Zarecondura mc Re US Tx OF Atar festo my www Magev VOC Gort Ege Py molo yi wa adero sS Al ord oc ove nee Te
134. s well as 4 HER mms individual subsystem J traffic including Ue poris traffic from cores ma Fman Qman Accesses LM Ted HT Total traffic E 27 to CPC1 M im m and CPC2 T cas ARS Unbalance a c between platform caches EA o n Fman B b Access e imbalance be seen by analyzing these subsystems Majority of CPC1 accesses are made by the CPU top right Majority of CPC2 access are from Fman and Qman Remainder of the traffic is due to PCI LACK OF BALANCED ACCESSES suggests DDR interleaving is not configured properly e Fixing the configuration provides a performance boost freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir ren Serato ed ow time meris of eee Sette onmtucmr Ir Row uS fur amp Tnt Deeta uapa Seu dyes Vegqev MO urbe ina Qui Dorana QUICC ua SAEARTANCS Tower Tun tard Y tuni ani be derat c of Freee wawa AU thee Of un wit Cane bin Hae awpa ed iher wapar iwa ownwen 331 Sere sedrtrc inc Packet Analysis Tool Customer Benefits Complexity abstraction and e
135. set gt C30 BMDS 00000003F 00000000 p DDRI BMDS 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00110105 00000000 00000000 03000000 00000000 P P UP UPS UP Pw Aw C 5 Cedo TET Cn d 20 Gowen Ta and Yorn av cadens lt lt Preece mc Re US Tx amp 7 C Arteri Facius Corti hoeverge Enpa Piy uola 4 s Fuascata La mconkta Wa of ord eye Te Yus MPEG wera CXII Sorter eres AP oes Upa P Er yy Uw 1 evt PO Pee UICE Generate DDR configuration u rr Project Panel I y Component Inspector 2 2 lt alf Properties Import Export V E p2020rdb pcal Documentation Generate Processor Expert Code Device Generated Code haesmnnr hne 125 p2020rdb pcal b Documentation gt Generated Code LI ddriCtrl 1 tcl Le InitDdrRegisters 1 c 6 p2020ds ddr c ya ua kuqa Aw CE Code TET ra Coro E t Sh tero Sete oe 21 Gowen Byron andi PETTY zn US Tx i Of reescale Artar Beets Corwin
136. ster gt lt portals gt lt bmportal id mn lt portals gt lt liodn gt 2 0 lt liodn gt lt irng gt Ealse lt irqg gt lt bmen gt lt hutferpool name bpool 1 gt zxhuffers 1 huffers xsize 512 00c size z hufferpool O 2 freescale false gt Imports DPAA configuration from Freescale extensions to NetPDL xml The xml files can be generated using the QCS solution or can be created by PCD Configuration z xml version 1 u znetpncrd 40 lt distrihbution name bDistributionl lt queue count 1 lIase xl lt action type classification name Clazssificationl lt protoacols gt lt protocolret name vlan lt protacols gt z distribution lt distrihbution name Distribution gt lt Queue count 2 hase On2 gt zfieldref name ethernet sro gt lt fi ldaret 11 type gt lt key gt lt protacols gt lt protocolret name lan lt protocols gt z distribution import XMLs Feature can be imported at project creation time or later after the project is created New QorIQ Configuration Project DPAA Configuration File or Folder nat specified Input File elect the DPAA dpc xml File to be imported 3 hy A ceni Documents lt Back D kto B 1 Documents e My Computer T Network File name
137. sts Read Write Compare Walking Ones Walking Zeros Choose validation mode Start Validation Connection settings System P2020 USBTAP id Hardware configurations Sd fw ge AAwa CE Cedo TET re Coh rms Stee Eeg Pont net POL Par AAEE ec 1 30 Caper cel Guna Ss Aarau Dutos ad Preece Zarecomdtm mc Rep US Tx Of reescale Artur Beets Coste Vasa 1 Mage VC w 4 erpa Erpa Py mw Sirol na ym ad we baro J Faini Damnoni IOAN 4 wa Te Sects eret CXII wee Serer ere Fre Centering of the clock results 8 Component Inspector 21 Properties Import Export Validation Test Result Results gt Choose tests z Validation stage ELK Centering the clock 40 39 e RN Saw e pa os Fade aps ps LL D T T T T mere T acces T TT T T Click cell to choose Write level start and CLK ADJ values e 22 freescale 131 DDR read ODT and driver strength test results 5 Component Inspector 2 h Properties Import Export Validatio
138. t mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R RRRSS 0 16 15 hv 1lp lnx agent dtb hv 1p lnx host dtb rcw all rev2 high bin 0x16 all rev2 low bin hv lp lnx dtb hv 4p lnx lnx lwe lwe dtb 0x16 all rev2 high bin txt 0x16 all rev2 low bin txt fsleUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R RRRSS 0x16 xxd rcw 0x16 all rev2 high bin 0000000 55 55 010e 0100 105a 0000 0000 0000 U U Eust 0000010 lele 181 0000 cccc 5840 0000 3c3c 2000 lt lt 0000020 80 0000 6100 0000 0000 0000 0000 0000 0000030 0000 0000 008b 6000 0000 0000 0000 0000 ore 0000040 0000 0000 0000 0000 0813 8040 b163 99e2 If sLeUbuntu 32b 32bit mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R RRRSS 0 16 2 wem Cw bmp d 2 Pret pt gt 2 4 94 04 4 Lau us vf a aw NOD TM rta aft Cw ne m Meco vo hor port envy MAL vy oh Mwy TVA ur eat a e OR 4 87 4 wa Te Kw ive oral i freescale Poneto thw kam Se C 5 Cong TES T Coder Cotten Comma C Waw the freerge W wa t od aan api wiki POS Perr LOC Expert eed Cowen Sale oae Wa bantuo Sir re
139. tem s load and on the amount of ki ME trace data o Use Uboot to reserve memory for it see the user manual e o o 2 freescale ud Data Collection After defining the configuration select Measure Launch p starting The results will appear in the Results folder of the project folder Results are collected as part of the project and will appear if the tool layout uses the default view on the left side of the tool 2 freescale Data Display Analysis Frame Details Decoded Trace Table Profile Decoded Trace Configuration Notes Seven tabs are available at the bottom of the table view Analysis system level analysis data based on the QM trace Frame Details details for each traced frame Decoded Trace Table a table view showing the trace data the key attributes of the trace data such as frame address timestamp etc are displayed using separate columns Profile a text view showing a trace based QM profile Decoded Trace a text view showing the decoded trace data Configuration a read only display of the data that was used to collect the trace data Notes displays and also allows entering new annotations for the analysis data V 2 2 freescale 69 Evert Oenciipton oo hh a
140. ts mates to align tools with new silicon products and support upgraded models Processor Expert technology and therefore Configuration Suite designad as set of plog ms that functon within a standard Eclipse enmdronment such 38 Codev arice Development Shido Users will create a 0000 Configuration Project mat defines 211 imported and generated conhigurabon fies andor source Code ihal a version control system can be used A sample wizard is esed 10 select basic configuration values and to define defaut settings The Componeri inspector window Is used lo modify each property Eam property automatically evaluated to ensure that Me values are Correct anc consesterd with each cler Each tool has a set of at ls applied 10 ensure the configuration set is property defined induding checks with other tools for consistunt configurason of fe entire Gon silicon product Each component generates nutput in ha form necessary tor configuration PEL data hex formal DDR configuration source code for u boot fmc smi data Device Tree source filas for dts and forth Every toot and property thas tool fip styla Gocurnentshan aligned with me product manuals 2 freescale mars Supported Devices P2040 P2040 P 2941 Low End Quad Core Communications Processors with Data Pam P3041 Qono P3941 Quad Core Communications Processors Data Path F4040 05102 P4040 Quad Core
141. tt lt Veo VW QU of we ORS OF e Te Seapets erat CXII G 5 Device Tree Step 5 Apply and Test Changes processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips 0 e500mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 4 500 1488 385000MHz 2 0 pvr 8023 0020 99 99 52 e500mc 1489 385000MHz 2 0 pvr 8023 0020 99 99 r3 e500mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 4 50 1489 985000MHz 2 0 pvr 8023 0020 99 99 55 e500mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 B e500mc 1489 385000MHz 2 0 pvr 8023 0020 99 99 2 e500rme 1489 3985000MHz 2 0 pvr 8023 0020 99 99 total bogomips 299 99 timebase platform model Memory 49999500 P4080 DS fs P4080085 4095 MB processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips 10 500 1439 385000MHz 2 0 pyr 8023 0020 99 99 1 e
142. u Pu mp y tage C b jamu U Co res 0 Bee Ww E yy fr eet m mei Pe Caper Corona betes ta Satanas Sy orem and Yorn av ot Pec mc Rep US Tx amp 7 C 4 Artar festo Coste Magee VOC Parton w 4 Dongs Q OC Py molo ma te lt Hee Y t of OF un wa nee wa Te Ty W ete eraut X111 aec een PBL Step 9 Generate Pre boot Loader and Compare with the RCW Provided in the SDK TS Project Panel Z3 0 F lt amp E tb p4080ds_0 lL Documentation 1 15 Generated Cade i S m PBLI pbl 22 Em Configuray Ne 00000000 AASS 55 010 0100 1054 0000 0000 0000 pO Open 00000010 1E1E 181E 0000 ccec 5840 0000 3cC3C 2000 Operating Open With k Secs Ey 00000020 FESO 0000 6100 0000 0000 oooo 0000 ooon 3 r soci nonnonso noon 0000 onsB 6000 0000 bedded P on E Bets Dein 00000040 0000 0000 0000 0000 0813 8040 Bi63 SOE2 dd PBLLR Move SaAnalysispoir Rename FZ I mem Import io Eo esee ee gy Export t Refresh F5 PU med etd Generating the PBL now provides us the Ban eiecre TELS same RCW than the RCW seen in the Generate Processor Expert Code I oDK2 3 4 fsl Ubuntu 32bi
143. ue msi ms address cells 1 _ Import device 4 mms Device tree settings Sai actelis 1 msi2 msi MITT device type tre e 4 quts global utilities e0000 x E nine ranges 0 f 000000 1000000 J Include device 4 rcpm global utilities e2000 Eee EMERGE tree 4 sfp es000 4 serdes serdes ea000 I I t a dmal dma 100300 Validate device Brie doa blac 3 tree ta Device tree Include tree lt gt j Search in device tree gt e 9 wem wu Fm r p U he 4 4 re Ue ppi wt as 21 3o Sow r ow w 1 25 aon TF Orar by Las cre and Vora an Z wau wc Oa Ita i try s te 08 TM rta ast vw e uar ier e ge lt U 0 pm Mwy ATS reb V 4 we of Pecos La mcowkzta Wo cod OF wa Te OM fus CXII renee Ya lf prMWOewoTee dis 7 OTIHWDevkeTreedts 12 i interrupr parenr aimpic ases aliases en 24 ccsr 25 dcsr amp dcsr General information Di 26 ethernetO 4epeto This section describes general information about the selected node ws qu EH PowerPC 500 t 20 ethernet2 enesti 4 121 2 lt Name aliases 2 29 ethernet3 m que Power PC 25000 2 Parent device tree iD ether
144. uration required interfaces PCle SRIO and eTSEC boot location set to boot from SD MMC card Step 3 Observe Power on Reset overview details Generated overview report txt HTML Step 4 Use BOOTROM tool to prepare configuration data file for boot Image processing Generated configuration file dat support of booting from on chip ROM e g eSDHC or eSPl base data file for boot image processing using external booting utility application Step 5 Usage of configuration data file with external booting utility appl ication using boot_format this application is a part of BSP release 4 2 freescale is at et Open Path origina Qon Open Fie Fem QC D WA 1 Mekefile Proiect with Cose low Proet ET ne AR Soc to he wed 4 4 Source Fokter iter fet 1 22 Seve 211 Stems Weeder lie a Pl bat He tom Temple Waive Cusr f r Che Cii n 3 pa Comvert Line Dekemreten To Puri P Creates propect P dewetive Santech Worngacs Aarten 4 J T What s New Product Relec Import ut gs Web Resources Service Pd eee win de you mpat 0 configure Servic Properties Ate mtm to be sefectert fepe Her tet Corrpenests y BOOTEOM Corfiguratian DDS Lerner
145. w Project Wizard New QorlQ Configuration Project DDR Configuration Configured device P2020 Change to 2Gb 128Mb x 16 Configure 1st DDR Controller Configuration mode Auto configuratic 2 Import from A file Discrete DRAM DDR Controller Fro m Imemory data Setting i sheet Data Rate 800 MT s gt DRAM Speed Rating 1333 M s v Ranks 1 gt Maximum speed Data Bus width 64bis gt ratin g CAS Latency 6 clocks i tRP ARCD Capacity ECC Enabled 1 DRAM Module Select 1st DDR Controller 4 wem Pu mp tmn U he 4 0t Pre lr ele tr 35 Se rew gt lt Gowen buf Ts Smara Screw ad Vora an Fim T 1 TM Cast Cervo wn Mae w a rwn gu Jer WUC opm H wy Ad we haero Zee kaw helo Wo A Ow Of wa Te r Get DRAM information P2020RDB PCA From P2020RDB PCA rooz t mi Dam ele L 33 gt Micron DDR3 SDRAM From MT41J512M4 64 Meg x 4 x 8 Banks E MT41J256MS8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks o 2 freescale x e px s 11 How about rest of the timing parameters Table 1 Key Timing Parameters p 211 45 x 1866 16
146. wen ta Satira and Vora av ades ot Preece baracoacoatar mc Beg US zz O8 Artar festo Meee VOC Parton w Dongs Q OC Pwy molo Z 4 karwacnykzutu Wa mof p Oz OF wa Te W Yus swak X111 awa Agenda Explore Configuration Tools available Explore Optimization Tools available Describe how people get the tools What is using QCS Review each tool Pre boot loader RCW configuration DDR configuration Device Tree Editor Data Path graphs and configuring the DPAA Summary Where to get more information Walkthrough Labs backup slides Lab 1 Installing QCS Lab 2 Pre boot loader RCW Configuration Lab 3 Bootrom generator Lab 4 DDR configuration Lab 5 Device Tree Editor Lab 6 Data Path graphs and configuring the DPAA e 2 o 2 freescale QoriQ Software Enablement Strategy v Provide Development Systems Complete boards for evaluation of QorlQ devices Y Provide Runtime software for QorlQ products MKV Hypervisor Linux BSPs Reference Designs Y Provide Bring up tools and development systems GNU tools CodeWarrior debuggers probes boards Y Provide Configuration Tools to support your application of QorlQ on your custom board ROW BootROM Pin Mux DDR Configuration Device Tr
147. y ogee CXII Sorter ores be DDRv Basic Connection Test S Component Inspector x W Basic Advanced Expert h 1 Hun basic test to 4 E gt Validation stage confirm targ et Ed Centering the clock ti Read and driver BIST Write Read Compare MEE CO n n ec 1 Write ODT and driver Compare WakngOns Choose validation mode Summary gt Logs Scripts Indepth Updated configuration registers Error cap Name A Run Result Connection settings System P2020 USBTAP id Hardware configurations Aw C 5 Code TET Cra Comm pa P Creepy Don wapo t eet Poww ICL woe e 1 29 Exper Corwen ta Satanas and Yorn ane z Preece Danecomduta mc et US te 4 reescale TM festo Coste on www Mage euin Py mw mobs yi md be terres kutim Wo A O Gw 4 ng Ww Te TOV bey eret X111 aec ucu ere Configure DDR scenarios and tests zu l mmmnmmemnr InmnsmerTmrm Basic Advanced Expert Properties Import Export Validation Test E V Valida Choose tests s S ES Ae Read ODT and driver Ed Write ODT and driver S Operational DDR te

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