NUC740 EVB user manual
Contents
1. m Cem EE RXCERR pe 1 E ip H d iu 8 ens W DW ERR rad iu ccc aq 5 Ea e ewe M n erR B d 57 TAW ERE ENT oR NO ON amp T Ern RENE 8 mn mcos E n le EE 3 2 3 2 Y 3 d 3 m 5 vob Long 1 g faze mu EP EE EP Eo P 95 5 8 j EAS S m ES EE 5488848 d m x END 5 En 288888 Tib s Bn PESE BE ugarow Tan 10K E E 5 m x ia 1 Exp2. broad schematic 10 100 Mbps Fast Ethernet PHY ine 1 86 5236 sw 1 5 46 RX DV 1 8x 2 RESETE 2 89 10 NO ON ERR 2 4 7 ERR Rw2 mmm dex 3 Sole x 4 5 Transformer 508 1 HEADER 3 a gt RWI A ASK o wan DIP aW uwt cwi ses eed ele miel me cw2 PY IE SNS e 77 7 1 0 1uF 10UF 16V wEOrszos5 HEO TX CLK COL 1 16 RB RWA 10P NOON CRS 2 15 CRSO amp 6 3 A 529022222232 cca RX CLK 3 134 er er 508 1 3r2 8 RDO 4 5000 8 ps 6 gt RXD1 5 12 RXDD1 5 1 6 2 4 ird RXD2 6 11 RXDD2 NC 1 RP 65 9900 RXD3 7 10 RXD3 5 88 MDIO 8 9 MDIOO ReH FOGD 0 3 m 9 wH Sp mH Wanao RX g SW 18 o VOD 39
3. 5 4 2 FLASH AND SDRAM 6 4 3 PCMCIA CONNECTOR 6 4 4 PHY WAN PORT AND LAN 6 LL MEI CR 6 4 6 UART 2 USB AND LED 6 4 7 6 4 8 POWER ON SETTING naa SE RRRRARRRRRRRAAARRRRRERRAXARXRARARRRRRSRRXASRRNRSSRARXARXRARRRSEASARSEKRRRSEAR R 6 4 9 RESET 7 4 10 POWER bist US INNAM MIO GORDON CENE ERR ERRARE 7 5 CIRCUIT BLOCK DESCRIPTION AND JUMPER 7 5 1
4. 8 5 2 POWER 11 5 3 MEMORY 12 5 4 PCMCIA FUNCTION BLOCK 13 5 5 LAN amp WAN FUNCTION BLOCKS 14 5 6 USB AND nanna 19 6 20 7 SCHEMATIC 24 Publication Release Date Apr 2009 2 Revision B NUC740 nuvoTon User Manual 1 Revision history version date May 13 2003 Initial Issued Sep 3 2008 Update Apr 6 2009 Change part number to NUC740 Publication Release Date Apr 2009 3 Revision B NUC740 Bm
5. RW35 JP47 RW16 CBLLNK PWRDWN Publication Release Date Apr 2009 16 Revision B NUC740 User Manual VDD WAN VDD O JP38 Operating Mode Select RW13 COLLED OPO PHY Address RXDO PHYADO Pulled low normally PHY Address RXD1 PHYAD1 Pulled low normally Operating Mode Select RW15 SPDLED 1 10K PHY Address RXD2 PHYAD2 Pulled low normally Operating Mode Select RW19 ACTLED 2 10K Disables Scrambing Enables Scrambing RW24 RX_CLK SCRAMBLE Pulled low normally PHY Address RXD3 PHYAD3 Pulled low normally Node Mode Repeater Mode ERR RPTR Pulled low normally PHY Address CRS 4 Pulled low normally 10K WAN VDD WAN VDD 0 Normal Operation 0 MII 1 Enables Test Mode RW32 1 RMII RX DV TESTMODE COL RMII Pulled low normally Pulled low normally 10K Publication Release Date Apr 2009 17 Revision B NUC740 User Manual 3V3 PHY Address RXDO PHYADO Pulled low normally Operating Mode Select RL13 COLLED PHY Address RXD1 PHYAD1 Pulled low normally Operating Mode Select RL15 SPDLED 1 10K PHY Address RXD2 PHYAD2 Pulled low normally Operating Mode Select RL18 ACTLED OP2 0 Disables Scrambing 1 Enables Scrambing RL23 RX_CLK
6. 0 012 YEN BS 2018 XEM Bs ar 0920 HIE pu S E E E VPP 5 sem 38 MEM 013 82 0014 MEM 027 0 0028 sero Wee iru eed 35 MEM 03 ction 33 MEM 012 0013 MEM 025 48 0027 NOTE 292 017 MEM D11 79 0012 eus 5 MEM 025 47 0026 aub 00 XXE Wow nu no Hi E 7 3 At 31 MEM D1 44009 GND rA MEM D22 40 0923 39 47 30 RFB 07 13 008 GND MEM 021 39 0022 5 20 45 07 10 Full chip unlock On OR MEM 05 211 MEM 37 0021 MEA A 03 remos bos up a poa 15883 ES 2 23 vss 26 FLASH n vep 7 004 GND 72 pir 35 CEs 25 MEM AD MEM 02 21093 MEM D16 31 0017 E a E Hum E ELE Bossa no on ieor 29 He Pana MEM 2013 RM TUS AGE MEM 06 Um Ra IEEE oos Hewes oR MEM rue par aneno on Ore wee a E Sta v Bosse 478 NO ON cor cos cos eos cor coe cow con co Leow Leou
7. USB gt 604 5 IRQI VP nRTS USB POWER RCV nRi USB_DN VO nCD FSEO nDTR umane nTOE nDSR USB1_ON OFF TD VMInCTS amp POWER ETHERENT USB PCMCIA WAN USB1 Direct i BANK 3 i Boot ROM 64kX16 BTSC amp i NUC740 Supply i ONE PORT i connect from i BANK 3 2MX16 CS3 i i i 1 8V 3 3V i LAN CPU H B Probe Header i and 5V Power ONE POET i i i H i i USB2 UART or 1 0 i SDRAM 2MX32 two pieces Expansion Switching i Select i i two banks i i i Function unstien i i i cente 4 Connector CTS RNC RO Title NUC740 EVB Bize Document Number Rev NUC740 EVB A Date Monday April 06 2009 Bheet 1 of 8 FIGURE 2 Circuit Function Block 51 MCU The MCU Block consists of 8 16 32 bits RISC controller NUC740 clock generator reset circuit display LED boot up setting and muti ice connector 8 16 32 bits CPU NUC740 is our production We have connector that is the same pin with NUC740 for easy debugging The I5MBZ crystal is must mount on the board CC2 20P FIGURE 3 Clock Generator Publication Release Date Apr 2009 8 Revision B NUC740 nuvoTon User Manual e We used the reset IC that make sure re
8. RESELLANIWAN ol EE WAN RESET LAN WAN IBI RESET_LAN WAN wet EN WP EN ERR TX0 ERR nWBEO SDQNO 9 DWBETSDOMTE nWBEO SDOQMO Ve SPED ty LAN Jp nNVBE2 SDaN RESET LAN WAN I cou nWBE3 SDQM3 Sh Ras WBES SDOMG cou crs lt sp SD Reni sp ci CASH wol a Wet some Pp SOW TA CLK 30 0 TXI EN Bo socso socss Dip SD cst 80 _ 51 RX1D O 3 RXID O 3 Rx CLK _ 35 8 5 RAI GLK Rxr ERR XT 8 ERR TX1 ERR TX ERR CSO CSH LAN vwncrse PC RST RST USB1 ON OFF USB SPEEDI RcvinRIE Ca VP nRTS USB DP Es USB MODE RXD IRQ 58 USB SUSPND ooa CPU al Exo zs s 2 95 9155 9 gt USB 3 USB SUSPND USB MODE RXD IRQ VP nRTS USB POWER RCV nRIi USB DN VO nCDit FSEO nDTR spe nTOE nDSR USB1 ON OFF TD POWER ETHERENT USB PCMCIA Memory WAN i USB1
9. GREEN E1 2 i 7 d a E P ENS 8398993 LES LAU 52 ELM bn 8 10K vet rei 0039477 Eo SSSSDNLSINSUIZDEI x FOOTE 2 EE SSPTSBBSA EDIITER 3358088155829 av ZENER x Bp x m oN 552428222522 2 Es Tux 23 TRE 1 5525846 8 H 14 GREEN 88 8 gg TOOK E 5 pe MR oe rm conza EE E VUE Ee TOOK Y on HA isi uS ON Lene e TALEN usevas E Eod oat Er ES TEM E pod os a tees Sods none EAS woes HAB 1 Lin m BRE id a SR m i Bas Pj i BH e aoe Sse wanted BR i h BE IHE 10 E PEIE USR BENA TER Ei M Orato go 401 pn BANN vob d 1 3 2 Usa SPEED A a Ha ti m 2008 09 m 9 i 3 oa H4 i 2 24 EE SoS vods He Pd Ls Wow 14 8 RPK x 25 ETE EE o
10. zizj J2l2 zigala ak 3 HEADER 3 a VD WAN_VDD 5239 2240 Address Operating Moda RW15 RXDi 1 1 SPDLED amp 1 CW21 Pulled normally 1 z 22pF WAN_VDD 10K 10K Yw RH20 RH25 RN30 REMOTE 5 READER 3 HEADER 3 25 MHz Rie CBLLNK 0 RW17 Dwi VDD 42 CW22 COLLED EN 9 WAN3 PHY Address Rw18 Operating Mode Z2pF 10K HEADER 3 RXD2 2 1 ACTLED OP2 44 300R RED 8 Pulled Tow normall 2 1 sv B 2 Nar 10K 10K xn HEADER 3 HEADER 3 Yw2 8 WAN_VDD 1 RW21 Rw22 DW2 WAN_VDD WAN_VDD o P 37246 8 1 SPDLED Y JPAT MER OUT 2 Address i ambing RW24 d ND 5 RXD3 CLK SCRAMBLE 33 300R YELLOW Pulled low normally Pulled low normally 2 25 50 MHz HEADER 3 Lw2 10K HEADER 3 HEADER 3 REF CLK xm E HEADER 3 OK NOON GREEN FB 2250 JP51 WAN_VDD JP48 CW23 10P NO ON RW27 9 o 23249 RW26 ACTLED 4 Address RW28 1 eater Mode RW28 2 2 2 CRS PHYADA 1 RXERR RPTR dis OR DWa HEADER2 57 HEADER 2 Pulled low normally 2 lled norma 2 An 300R 10K 3 10K 93 HEADER 3 HEADER 3 Dwa WAN_VDD WAN_VDD CBLLNK 0 Normal Operation JPs2 ps3 1 Enables Test Mode RW32 d 300R
11. D won L2 32 eis Rws RESET 40 DYDD F21 S WAN 41 20 6 did ry PETI 50R 1 Xm 22 19 po MDC 1 16 MDCO Xn 43 l1 1x02 TX 15 IX ITT cewa DGND 44 PROP 17 DO TX EN 3 14 EN Rw9 PEGBSISL 45 DI 46 TX ERR DDO 4 13 DODO DODO AGND 46 NC TER DOS i5 TxD1 5 121x001 1001 TSR 1 Rw10 BGRESG 4 14 CBLLNK TXD2 6 11 TX EN TER 1 O tuF2KV 1496 48 13 TXD3 T 10_ 14003 RXOD0 2 cws 508 1 RW BGRES LINAC T LED HOPS TX ERR 8 9 DO ERR RXOD1 6 8K 5 H RX DV CRS DV Rw7 _ zv FB 9 SW RX ERR TSR 1 758 1 placed close to as MDCO 47 amp 48 as MDIOG Chasis Ground much as REF GLK possible 280 SV3LAN ao oo 004 224 555006 42256 Settings Latched Inpui AVDD 1 VDD WAN AVDD y T 7 PHY Address RW12 Operating Mode 4 cwi cwi4 FB cwis cwie RXDO PHYADO 1 COLLED 21 28 Pulled normal 2 S 3844 CWi8 cw19 0 010 0 1 10UF 16V 10UF 16V 0 01 o tuF
12. om iios Towe owr Touf ev aru ev sent bloc vraa Yr e le cra eo Len lee Towe miv Tanev E ves cow com cow coi eom eom ern eom coz Leoz coz see ET K 9 ast RF15 1 1 2 K ora E Sn s gt Es uz Hmm Ex Publication Release Date Apr 2009 26 Revision NUC740 User Manual 10 100 Mbps Fast Ethernet PHY the Gr voo broad schematic 2916 CLK ie RESET LAN WAN ERU 9
13. VWnCTS 5 12 VM 5 D RUAA D2 i 6 11 SUSPEND 6 o SPEED SUSPND 7 10 77 SUSPND SPEED lt SPEED n Nc 2 DIRE 8 m RUI2 PDIUSBPTIA Sw 08 Publication Release Date Apr 2009 30 User Manual MODE RXD 1 16 9 RXD MMInCTSE 2 15 RIOUY RUM TR CTS 3 14 R2CUT RAIN 27 DSR 4 13 221 DCD RCV nRI 5 12 jg RA MUN RI TXD 6 11 REGUT PINT DOR VPInRTSE 7 10 RIS FSEO nD TRE 8 9 20 1 DTR BIN TOUT 4g ECT 1UF 18Vey TAOUT 24 RU2 gaw Y 42 SHUTDOWN 45 cus 7 10UF 16V 44 16 Y 3 13 Gh 2 EIL 10UF 16V teus 16 zn MN cus MAX241 SO RUF REV CONNECTOR DB9 Female 5 4 0 115 CH 29 1 Female NUCT40 EVB Bie Document Number lev B NUC740 EVB 04 ate Monday April 06 2009 Ehe 7 of Revision B NUC740 pLLIu User Manual Switching the external or on
14. User Manual 2 General Description The evaluation board is a test platform that is suitable for the sample of NUC740 The board include the powerful 16 32 bit ARM based RISC micro controller NUC740 USB function memory PCMCIA function power control system LAN and WAN Ethernet port This allows us to test and debug all NUC740CD function This document shows the system based hardware design We would describe the jumper function selectable function and how to connect with the NUC740 in detail 3 Features e NUC740 16 32 bit ARM7TDMI RISC micro controller Boot ROM and AP flash 2M 16 bits for expansion SDRAM One 512 4 banks 32 M bits SDRAM External I O PCMCIA application Wireless LAN General I O control signal UART or 2 USB show status LEDs USB USB function LAN and WAN 10 100M Ethernet interface Embedded ICE Interface Expansion Function one port WAN and 4 ports LAN Publication Release Date Apr 2009 4 Revision B NUC740 User Manual 4 The Function Blocks PCMCIA Wireless LAN USB signal USB Device Console or Loop Power Device EVB Board Fig 1 The Function Block of Evaluation Board 41 CPU NUC740 NUC740 is our protagonist That is for her what we do every thing The NUC740 is using ARM7TDMI core inside It is a low power general purpose integrated circuits The NUC740 offers 8K byte I cache SRAM a 2K byte D cache SRAM and two MACs of E
15. 69 1 UCS5 74HC04 70 1 UC6 TOP SWITCH 71 2 UD2 UDI 512X4X32 64M 72 1 UFI W39L010 73 1 UF2 W28J160B T 2MX16 74 2 UI1 UF4 7404 75 1 UD 74F244 76 1 013 PCMCIA SOCKET 77 2 UL1 UW1 PE 68515L 78 2 UL2 UW2 DM9161 79 1 Power CON Publication Release Date Apr 2009 22 Revision B NUC740 Inm User Manual 80 2 UP2 UP4 MIC29152 81 1 UP3 MSOP 8 MIC3975 82 1 UU2 MAX241 SO 83 1 006 2 2 84 1 UU7 CONNECTOR DB9 Female 85 1 UU8 PDIUSBP11A 86 8 01 02 04 05 06 07 08 09 Nuvoton Logo 87 1 15MHz 88 2 YLLYWI 25 MHz 89 2 YL2 YW2 25 50 MHz Publication Release Date Apr 2009 23 Revision B NUC740 pLLIu User Manual 7 Schematic PCMCIA EE TROZE CS2R Pc nWBE1 SDOMt MEM_OE WAN CPU 0 241 MEM 00 31 COLO ERSO coo 5 WAITER s 8 oy 0100 Ib unco MEMORY 8 0 24 MEM 24 DOE _ Q NEERI oo CLR 3 caw 538 DV Roe XV BS eee ERR ERR CEXIDILGL MEM BP
16. d Is Is Es E aeu H b ucs 2 ds n s 1 4 USBPOW A23 224 5 NES pr er H in 1 mcos mcer 8 A E ics 1 1 40 A E E E cei Ey Ys E A E 166 AV5518 Tels D11 JVSS33 2 AME HEADER HEADER ge 2 Ron rm 7 4 ES A att Tos AE IP wa ava VSSTE m woos 5 mcus T om TS 1 Rom A A Zz E E Bl 2 umi vem ois 1 A E EH i 2 A 2 59 ERE M HERDER I E E E FEE 22 5 8 HEADER HEADER 5 A 19 57 0033 HEADER 30 mca m x Cr m Root MEE ucs Les 4 10K ye 1 TAEK 1 54 010 DOME e owe aaa 888 2888 innt SEE HERDER Zo m ala En 434 xen con 8859 spes U 3 cae a 554 aag a sie ahe 9 we PS WIDTH 3252 3 sa xp ud 4 1 a AIK aL ESET Lawan ad tem m ARA is RENDE
17. 6 44 X INPACK 4 4 12_ vov E 74 244 E o GND Attribute R W 75 47u 16V 0 1UF Gun 16V 5264 vst 3 HEADER 3 READER 3 NUC740 EVB Document Number Rev NUC740EVB Date Monday April 06 2009 Bhe 5 o 8 Publication Release Date Apr 2009 28 Revision B NUC740 User Manual 1v8 18V 9 GREEN Lp2 47 JP55 T t T gt 1 2 FB HEADER 2 CP5 CP6 CP7 5v e CP8 0 1UF 9 470 16 0 1UF 16V GREEN E 1K RP9 in o n POWER SW FB DC10 4 4 2 2 2 cpa e 0 1UF 400UF 16 O 1UF tooUF 16V Tee bras x 4 aan ava FB uw 9 GREEN m LP4 560 RP10 d CES 4 4 EN OUT 1 IN ADJ 8 14 TX CP13 215 0 10 9 MIC29152 47U 16V 470 16V 10UF 16V RP2 RP3 1 2K 10K 1 8 3V3LAN EN GND 9 2 E d ADJ GND 126 5608 A ARPA 4
18. 0 n DQMI3 0 1 01 SDRAM 0 740 64Mb 512Kx4x32 FIGURE 8 SDRAM Interface 5 4 PCMCIA Function Block The PCMCIA function is using one bank of the external memory that is the bank 2 We select 1 and attribute memory Read Write by address A23 When A23 is High state that memory is access I O memory If A23 is Low state that memory is access attribute memory The PCMCIA function block is used the external bank 2 The 52 signal must connect with PCMCIA connector The REG signal control by GPIO20 IRQ3 The PCMCIA power depends LI1 112 LI3 and 114 If thePCBA are mounted the and 112 The power is 5V Otherwise the PCBA are mounted and 114 that the power is 3 3V GP20 IRQ3 amp gt 2 4 4 33 nECS2 S UI2B MEM A23 RIG 33R nWBE1 MEM 23 5VD _ 23 MEM A23 MEM A23 1 0 R W MEM A23 0 Attribute R W Publication Release Date Apr 2009 13 Revision B NUC740 Bm User Manual FIGURE 9 PCMCIA bank selector The PCMCIA signals VS1 VS2 can select HI or LOW by the JP64 and JP65 VDD_3 3V Figure 10 VS1 and VS2 jump selector 5 5 LAN amp WAN Function Blocks In LAN and WAN block that we used 10 100 physical layer IC DM9161 of the DAVICOM It can support MII and RMII mode We let reset signal come from t
19. 5 OUTPUT GND E 1 RES L o 18V MSOP 8 MIC3975 1 ovr 1 2K 1 2 5 IN ADJ 2k z 75 7 5 CP22 cp23 CP24 29152 0 1UF 16V 10UF 16V 1 2K Title NUC740 EVB Bize Document Number NUC740 EVB 0 1 Monday April 06 2009 Bheet 6 of 6 Publication Release Date Apr 2009 29 Revision B nuvoTon pLLIu O NUC740 USB DP pe USB USB HOST cut Rut 33uF 16V 10K LU rB1206 USB1_ON OFF ON OFE H 8 t ec 1 ELM be OR cur Sor 33uF 16V 0 0tuF 4 212 RUS ha 1206 103 1K NA 18K 15K LU2 FBi208 NEN 1 veus D 2 cut2 CU10 02 x 3 33uF 16V O 01uF Al FB1206 104 15 15K uus ava MODE RXD i calis wo 1 14 ava USB_MODEIRXD nTOE nOSRE 2 15 OE 2 MODE nTOE nDSR OE amp RCVInRI amp RCV VPO VP nRTS 4 13 VP 4 11 RUT D2
20. RL20 RUM DL2 HERDER 2 0 Disables Scrambing 9 JP28 VES 1 SPOLED Address 1 Enables Scrambing RL23 BUT 2 RXD3_ PHY AD3 SCRAMBLE i pas 33 300R YELLOW Pulled low normally Pulled low normally 2950 HEADER 3 10K 10K RL36 oj JP29 R3 HEADER 3 rd FB NU S BEWRDWN 1 VDD JP30 VDD 10P NO ON RL26 013 2 0 Node Mode 31 RL25 ACTLED 3 PHY Address RL27 1 Repeater Mode 828 3 9 HEADER 3 CRS 4 RXERR RPTR Pulled low normally 2 Pulled low normally 2 57 300R GREEN 10K 3 10K HEADER 3 HEADER 3 DL4 VDD CBLLNK gt 0 Normal Operation 2232 0 a 5233 1 bles Test 1 RL32 300R RL33 RX 1 COL 1 NUC740 EVB Pulled low normally 2 Pulled normally 2 10K 10K 2 10K Size Document Number Rev HEADER 3 HEADER 3 B NUC740 EVB A Date Monday April 06 2009 Bheet 4 of 8 Publication Release Date Apr 2009 27 Revision NUC740 User Manual A 0 24 MEM A24 15 20 30 MEM DO RESET 4
21. SCRAMBLE Pulled low normally PHY Address PHYAD3 Pulled low normally 0 Node Mode 1 Repeater Mod RL28 RX ERR RPTR Pulled low normally PHY Address CRS PHYADA Pulled low normally HEADER 3 3V3 VDD 3V3 VDD 0 Normal Operation C 0 MII 1 Enables Test Mode 31 1 RMII RX DV TESTMODE COL RMII Pulled low normally Pulled low normally 10K HEADER 3 HEADER 3 FIGURE 14 Ethernet Power on Setting Publication Release Date Apr 2009 18 Revision B NUC740 5 6 USB and UART Functions USB is a main function and difference with other broadband router We have an independent USB port that connect to NUC740 USB function and a second USB port that is connect to GPIO However the second USB function is optional with UART function Our USB is host controller that must supply the current to other device Therefore we have a power switch UU8 to control the current The 2 USB is the same UU6 In order to let 2 USB and UART function cannot conflict that we used switch to separate the control signal That is UU1 and 1705 FIGURE 15 UUI is turn off the UART function UUS is turn off the 2 USB function You must turn off the switch 1 of the UU5 when use the console and UART function of the NUC740 UU1 The 2 USB must have a transceiver to improve the function The control signal is next 005 SW 1X8 FIGURE 15 Switch devices for 2
22. TXD3 TXOD3 8i n 2 MDIOO TX ERR TX0 ERR SW 1X8 SW 1X8 FIGURE 13 LAN and WAN MII Switch In LAN and WAN blocks that have some power on set functions must setting They show on the next table and FIGURE 14 Publication Release Date Apr 2009 15 Revision B NUC740 User Manual Setting Hi Lo Note Phy address bit 0 1 0 RX DO Phy address bit 1 1 0 RX DI Phy address bit 2 1 0 RX D2 Phy address bit 3 1 0 RX D3 Phy address bit 3 1 0 CRS Testmode Normal Option Test Mode Rx DV RMII RMII MII COL RPTR Repeater mode Node mode default RX ERR Scramble Enable Disable RX CLK Cable Link Link Without Link CBLLNK Power down mode Power Down mode Normal mode PWRDWN Notel 1 is LAN function block 0 WAN Function Block OP2 OPI OPO Function Note 0 0 0 Dual speed 100 10 HDX COLLED 0 0 1 Reserved SPDLED 0 1 0 Reversved OP2 ACTLED 0 1 1 Manual select 10 HDX 1 0 0 Manual select 10 FDX 1 0 1 Manual select 100 HDX 1 1 0 Manual select 100TX FDX 1 1 1 Auto negotiation enable with all capabilities The LAN setting headers are JP17 JP18 JP19 JP20 JP22 JP23 JP27 JP28 JP30 JP31 JP32 JP33 JP21 and JP29 The WAN setting headers are JP37 JP38 JP39 JP40 1 42 JP43 JP45 JP46 JP48 JP49 52 JP53 JP41 and JP47 3V3_VDD Q VDD Q RL35 PWRDWN
23. USB and UART MODE RXD VM nCTS nTOE nDSR RCV nRI VP nRTS FSEO nDTR User Manual 16 15 13 11 SW 1X8 GPIO USB UART Note GP4 RCV nRI GP5 VP nRTS GP6 VM nCTS GP7 VO nCD GP8 FSEO nTDR GP9 NTOE nDSR GP10 TXD USB Mode RXD Suspend In order to control the USB power switch That must select over current protect by GP18 NIRQI and control USB function on off by GP12 Publication Release Date Apr 2009 19 Revision B NUC740 BAGG User Manual 6 BOM NUC740 EVB Broad of NUC740 Bill Of Materials April 11 2003 15 07 17 Item Quantity Reference Part Pagel 1 2 2 20 2 78 CP1 CI1 CF1 CD1 CW2 CL2 CF2 CD2 CW3 CL3 CI3 CD3 CC3 CW4 CP4 CL4 CD4 CC4 CW5 CL5 CF5 CD5 CC5 CU6 CP6 CF6 CD6 CC6 CF7 CD7 CC7 CW8 CP8 CL8 CD8 CC8 CW9 CL9 CD9 CC9 CW 10 CL10 CD10 CC10 CU11 CD11 CC11 CD12 CC12 CW13 CL13 CC13 CP14 CC14 CD15 CC15 CD16 CW17 CP17 CL17 CD17 CW 18 18 18 18 19 CL19 CD19 CP20 CD20 CD21 CD22 CP23 CD23 CP24 CD24 CD25 CD26 3 20 CD CIA CP5 CP7 CF8 CF10 CP13 CD13 CD14 CP15 CC16 CC17 CC18 CP19 CC19 CC20 CP21 CC21 CD27 CD28 4 10 CC22 CW23 CL23 CC24 CC25 CC26 CC28 CC29 CC37 CC38 CC23 10 6 7 CU8 CU10 CF11 CW12 CL12 CW16 CL16 7 12 CW1 CL1 CU3 CU4 CUS CU9 CW 14 CL14 CW15 CL15 CP 16 CP22 Nn ja CW21 CL21 CW22 CL22 22pF CONU1 CONU2
24. 857 pame 3 oor vaes spamas 5 bri MEM MEM Dane 71 MEM Ad A9 AT 26 42 SDOMOF do ud A 5940 ae 5 Y iR dcs ER utin uve MU BOOTER LzL MEM AI 24 MEMO non NEMAS 2 85 5828388 iEn TE aa Sue E 0029 MEM 64 Bas CASE e nase ws9Lo10 RFIG MEM 027 50 0028 Gas pur SD Wer sees E a a IL EX MEM A15 1 p 48 16 b D25 47 0928 MEM A4 61 5 so ane eu cee Hate IS RM HIS inr EE eh AG sas Bs BOOTER MEM 023 42 0024 2 Done 71 127 VSS 45 015 2 022 40 0023 AT 28 2 de ei i Boke S Bar 95 Bact A cue Drum 29 8155 EE Bons MEN EA Firme ST mra m E 2149 015 MEM D18 34 0019 24 4148 0013 Fag 05 017 33 008 MEM D31 56 A11 A20 30 9 2295 MEM 1 0017 MEM M Ne
25. B NUC740 nuvoTon User Manual RC80 RC87 10K MEM D14 MEM 011 RC91 10K MEM 013 MEM D10 4 7K JP8 LO external clock from EXTAL pin is served as internal system clock JP8 HI PLL output clock is used as internal system clock JP7 HI the external memory format is Little Endian mode JP7 LO the external memory format is Big Endian mode JP6 JP5 BUS WIDTH JP2 1 LO LO 8 BITS 0 0 RESERVED LO HI 16 BITS LO HI 128 PINS HI LO 32 BITS HI LO 160 PINS HI HI RESERVED HI HI 176 PINS FIGURE 6 Power on setting interface We put two kinds JT AG connector for ICE In which one has 20 pins and the other has 14 pins JP61 decide the JATG power is 3 3V or 5V 3V3 HEADER 3 Publication Release Date Apr 2009 10 Revision B NUC740 nuvoTon User Manual POWER RC35 SHORT nTRST D 5VD O 46 SHORT 5VD RC67 5VD nSRST RC82 TDI RC83 10K TMS RC84 10K nSRST TCK OR NO ON T Figure 8 JTAG Connector 5 2 Power We used 5V adapter for the evaluation board We planned use 2 pieces of 1A current regulator change voltage from 5V to 3 3V One supports the peripheral power that are PHY and memory The other one only support to NUC740 The CPU core power is come from 1 8V regulator We used the inductor to separ
26. C41 RC42 RC43 RC45 RC47 RC48 RC49 52 53 54 55 58 RC59 RC60 RC61 RC62 RC63 RC64 RC65 RC66 RC69 RC70 RC71 RC72 RC73 RC78 RC79 RU3 RF8 RF10 RU12 RC20 RC21 RL25 RW26 RC31 RC32 RC38 RC39 RC44 RC50 RCS1 RC68 RC22 1M RC56 RC57 NO ON RU1 RI1 RU2 RP3 RI7 RI8 RI9 RI10 RI11 RW12 RL12 HEADER 22X2 HEADER 2 FB 33PR 47 OR 10K Publication Release Date Apr 2009 User Manual Revision B NUC740 Inm User Manual RI12 RW13 RL13 RI13 RW14 RL14 RI14 RW15 RL15 RW16 RL17 RW18 RL18 RW19 RL22 RW23 RL23 RW24 RL27 RW28 RL28 RW29 RL31 RW32 RL32 RW33 RL33 RW34 RL34 RW35 RL35 RC67 RC80 RC81 RC82 RC83 RC84 RC85 RC86 RC87 RC88 RC90 43 3 RW1 RL2 RC74 100K 44 4 RF15 RC75 RC89 RC91 4 7K 45 10 RU5 RP9 RF13 RC100 RC101 RC103 RC104 RC105 RC106 RC107 46 1 RC102 10 47 5 RW36 RL36 RC108 RC109 NO ON RC110 48 4 RF6 RF7 RF9 RF11 4 7K NO ON 49 2 RF12 RF14 47K 50 2 RL1 RW3 1 5K 51 8 RW2 RL3 RWA RLA RWS RL5 SOR 1 RW10 RL10 52 8 RW6 RL6 RW7 RL7 RW8 RL8 75R 1 RW9 RL9 53 2 RL11 RW11 6 8K 54 8 RL16 RW17 RL21 RW22 RL26 300R RW27 RL30 RW31 55 2 RL20 RW21 33 56 2 RP6 RPI 2K 57 3 RP2 RP5 RP7 12K 58 1 RP4 560R 59 1 RP10 560 60 1 RU4 100 61 4 RU6 RU7 RU8 RU9 15K 62 2 RUIO RUI1 27 63 1 SPI POWER SW 64 2 SWI SWA DIP 4W 65 6 UU1 SW2 SW3 UUS SW5 SW6 SW 1X8 66 1 UCI NUC740 67 1 UC3 MIC8II 68 1 UC4 7408
27. Direct i Flash Boot ROM 64kX16 BTSC amp i NUC740 H Supply ONE PORT connect from NEUEN BANK 3 2MX16 i 1 1 8V 3 3 i CPU attributs Probe Header and Power ONE POET i i i i USB2 UART or I O i SDRAM 2MX32 two pieces i i Expansion switching Select i two banks DEAE M H function i d Connector i NM i E Tie NUC740 EVB Document Number Nuc740 EVB Date Monday Apri 06 2009 heet 1 o Publication Release Date Apr 2009 24 Revision B NUC740 User Manual
28. MEM_D 0 31 0010 E RX GLK Reck 4 E DOCE Rony BTCSHB ERR JE ROER MEM MEM RXDD 0 3 Rn RESET LANWAN Be 0 3 WAN RESET LAN WAN lir RESET LAN WAN BM WPit EN TO ERR DO ERR nwaEorsp avos b WE nWBEO SDOMO nwaBE2iSDQM R Me LAN WE SDONOME HWBENSUGMSE JR NWBEZ SDCAD RESET LANIWAN cou nWBES SDQMSSBI sp nWBE3 SDOM3 a case Boni SD_CAS SO Cast _ sb wee M nic Sooke Mer n ck SD so csos 50 DU EN Bp EN C50 so css TxiD o 3 r3 1010 3 SD CS1 SD CSts RIDE 8 o cuc CLR Xt Dv FLASH amp SDRAM BL TX ERR ERR CS1 LAN vMincTs PC_RST f nTOE nDSR USB1_ON OFF FSEO nDTR USB SPEEDI f voinco RCV nRI vP nRTS USB_DP xl USB MODE RXD IGE hS USB SUSPND Se sea ese CPU a EE 99 xz uz 5 85 ald BASSE GS 9 BERE USE
29. NUC740 Inm User Manual NUC740 Evaluation Board User Manual The information described in this document is the exclusive intellectual property of Nuvoton Electronics Corporation and shall not be reproduced without permission from Nuvoton Nuvoton is providing this document only for reference purposes of NUC740 based system design Nuvoton assumes no responsibility for errors or omissions All data and specifications are subject to change without notice For additional information or questions please contact Nuvoton Electronics Corp Publication Release Date Apr 2009 l Revision B NUC740 BGG User Manual 1 REVISION 5 3 2 GENERAL DESCRIPTION 4 4 4 THE FUNCTION 5 5 4 1 NUC74O
30. ORG RX DV TESTMODE COL 2 Pulled low normally Pulled normally 10K 10K 10K HEADER 3 HEADER 3 Document Number ev B NUC740 EVB 1 jate Monday Apri 0 2009 Ense 8 of Publication Release Date Apr 2009 31 Revision NUC740 Bm User Manual Important Notice Nuvoton products are not designed intended authorized or warranted for use as components in systems or equipment intended for surgical implantation atomic energy control instruments airplane or spaceship instruments transportation instruments traffic signal instruments combustion control instruments or for other applications intended to support or sustain life Further more Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury death or severe property or environmental damage could occur Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales Please note that all data and specifications are subject to change without notice All the trademarks of products and companies mentioned in this datasheet belong to their respective owners Publication Release Date Apr 2009 32 Revision B
31. R S 2 Y cca coe ccs eer cca eco cow eos cow cow OVE Av owr owr 16V tev cow ecw cen amp aro ev Taru i66 Taru ev tus v vasis vasis mr T Deere 5 RETE Iu Publication Release Date Apr 2009 25 Revision B NUC740 User Manual ey um EVE nWEESDOMDH op T vraa B VES ee me ups ier e A p A9 l 8 FB 58 Bas Tie Cast Rast a E 2 wer 52 MEM A5 62 AS SD CsoW x 2229889 AS CS 59 spans csor ejar 6337
32. RESET MEM 16 39 A18 MEM D1 MEM 17 26116 De L2 MEM D2 MEM A21 7404 MEM 4r 03 MEM A20 MEM 19 48 18 p ks MEM D4 MEM A19 MEM 00 31 MEM A20 49 19 MEM DS MEM A18 010 MEM A21 50 251 8 MEM D amp 3 3V MEM 17 22 53 ps fs MEM D7 R0 40K 24 65 23 ua MEM AQ MEM A14 9 MEM A25 56 os eg 28 MEM A1 pad MEM A2 RH gt ES 2 ix mem STSCHG AS MEM A23 s 4 pe MEM A23 MEM Ds 65 pa nWAIT ware 7404 MEM D11 37 010 nRESET MEM D12 38 011 RST 013 38 012 nWBEt SDQMts MEM 40 013 MEM Dis 41 074 61 Reg 33R CER az 7 GND nOE RIS AA aa IS lt lt nECS2 CER ggg CD 82 Ris AAT GND 8 Wee 15 OE CO er 82 JORDE WEP MEM A23 19 EN IQWRE 45 War L8 nWAIT IREQ ngog REQ POM ie INPACK 1 REO PCM 16 REQ vep HE 2 oo P x iX x 101516 E 3 1 VDD 3 3V 17 3 7 wee s8 Reser Sf GND vec 74 244 1 GND RINS RIZ ND 33R 40K 40K PCMCIA SOCKET 3 3V 0 nWBE1 a L2 Bi 4 4 MEM A23 tolEN 3 3V 3 3 NOUSE NO USE 2 18 9 2 i 36 x 10K
33. RESETE aa 10P NO ON RX DV 1 8 DV MII 2 RX ERR 2 7 RXICERR des seges 29 3 100K HEADER 3 966 82 CLK ents gt 5OR 1 10P NO ON DIP AW 4 put 8858 SIS SIRIRIRIS IR 233 ais TT RASS sw E 2 5 2 1 16 pum 100 16 28u2EUOSSSOS CRS 2 15 ORS 258565055585 m eri 555526855552 RX CLK 3 44 8 7 cial 1 ore Fete RXDO 4 13 8 NC 0 1uF RDI 5 12 5 1 6 2 RX RXD2 6 11 RXIDZ hs 4 1 RX RD gt 2290 RXD3 7 10 103 s Re E E 5555 NDIO 9 8 Mone te RX 3r RXDVITESTMODE 9 23 Sw 1x8 RXID O 3 9 EDD 38 DVDD zc o 12 14 RLS 40 DVDD 8 PELIGRA EN 1 RESET DEN sw3 DVDD TXD 0 15 3V3 AVDDS SOR 1 Xm 42 49 1 16 De T Xn 43 X12 TO 18 Txp2 TX CLK 2 18 IX ca DGND 44 Xl DO 47 Do3 TX EN 3 44 EN RL9 PE 68515L o 1uF 45 DGND 3 46 TX ERR DDO 4 13 TXIDO 46 Nn DER IH 15 DOI 5 12 TXID1 DADI RMIT TER 1 BGRESG 47 44 CBLLNK 11 EN 758 1 4 4 BORESG GABLESTSILINMSTS L43 AGTEDE 7 10 TXID3 RXIDO aw cue A TX ERR 8
34. TX ERR RXID1 6 8K i RXi DV CRS DV 758 1 7SR 1 2 FB 1 9 VDD ERR placed close to 89 9 Swine pins 47 amp 48 as MDIOT Chasis Ground much as REF possible 2986 3V3LAN 22 Power on Reset Settings Latched Inputs iii inui AVDD 048161 FB 2 FB VDD 3V3_AVDD A I JP17 4 JP18 9 PHY Address Operating t RL13 cuis RXDO PHYADO COLLED 1 esa Pulled low normally 2 214 4844 CL19 O 01UF 10UF 16 10UF 16V 0 010 0 tuF 10K 10K 3 HEADER 3 HEADER 3 See lt VDD 2219 q JP20 xn Address RL14 Operating Mode t RL15 RXD1 _PHYAD1 SPDLED 1 i 21 Pulled ix 2 2 10K 10K RLI9 RL24 RL29 REMOTE HEADER 3 HEADER 3 25 wer xm VDD 3vg_AVDD 2 22 9 2 23 22 COLLED E 10K HEADER 3 Address Operating t RL18 22pF 2 PHYAD2 1 ACTLED OP2 2 300R RED 7 Pulled low normally 2 2 P24 10K 3 3 HEADER 3 HEADER 3 1 viz JP26 2 VDD VDD 4
35. USB CON CP3 CP2 100UF 16V CU1 CU7 CU12 33uF 16V CU2 1UF 16V DW1 DL1 DC1 RED DC2 DW3 DL3 DC3 DC4 DC5 DC7 DC8 DC9 DC10 DC11 F2 gt 16 1 DC6 3 0V ZENER 17 2 DL2 DW2 YELLOW 18 2 DL4 DW4 ORG 19 1 20 1 2 20 0 1uF 47U 16V 10P NO ON 0 01UF 10UF 16V CW6 CL6 CW7 CL7 0 luF 2KV GREEN Publication Release Date Apr 2009 20 Revision NUC740 E 21 22 23 24 25 27 28 29 31 32 34 35 36 38 39 40 41 42 N 16 JC3 JC4 CON1 JL1 JW1 CON26A JL2 JW2 RJ 45L JP1 JP2 JP5 JP6 JP7 JP8 HEADER 3 JP16 JP17 JP18 JP19 JP20 JP21 JP22 JP23 JP26 JP27 JP28 JP29 JP30 JP3 1 JP32 JP33 JP36 JP37 JP38 JP39 JP40 JP41 JP42 JP43 JP44 JP45 JP46 JP47 JP48 JP49 JP52 JP53 JP61 JP63 JP64 JP65 JP14 JP12 JP13 HEADER 16X2 15 HEADER 5X2 JP24 JP50 JP51 JP55 JP62 145 HEADER 30 77 16 HEADER 30X2 LP1 LF1 LD1 LC1 LW2 LP2 LL2 LF2 LC2 LL3 L13 LF3 LWA LPA LLA LIA LCA LWS LP5 LL5 LC5 LW6 LP6 LC6 LC7 LC8 LC9 LILLI2 NO USE LU1 LU2 LU3 LU4 FB1206 PR1 PR2 PR3 PR4 PR5 PR6 PR7 PR8 PR9 PR10 PR11 PR12 PR13 PR14 PR15 PR16 17 18 QF1 QF2 BC558 NO ON QF3 BC548B RC1 RI4 R16 33R RI2 RC2 RI3 RC3 RC4 RI5 RCS5 RC6 RC7 RP8 RC8 RC9 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC18 RC19 RC23 RC24 RC25 RC26 RC27 RC28 RC29 RC30 RC33 RC34 RC36 RC37 RC40 R
36. ard to extension 4 ports switch output 4 5 JTAG We used it to connect to CPU with ICE It s debug tool 4 6 UART 2 USB and LED Those functions are creating by the programmable I O ports of CPU The UART and 274 USB are optional functions We used switch to select it The UART can do console connection or RS232 full function connector The 2 USB needs a transceiver or external USB transceiver connects to USB device The LED function is showing the power on or power off mode 47 USB We have one USB host controller It is USB 1 1 compliant specification On the evaluation board that we would have one power switch IC This IC can output current typically limited to 0 85A below the 5A safety requirement 4 8 Power on setting After power on reset there are four Power On setting pins to configure NUC740 system configuration We must set the next function Di5pin Internal System Clock Select D14 pin Big Little Endian Mode Select D 13 12 Boot ROM FLASH Data Bus Width D 11 10 Test Chip Configuration D 9 8 Package Type Select Publication Release Date Apr 2009 6 Revision B NUC740 Inm User Manual We would have eight groups jumper setting to do it On section 5 1 have more improve description 4 9 Reset schematic We put one schematic on the board It use reset IC schematic that make sure reset timer is fine The other things that on board device reset fun
37. ator the analog and digital power We put the fuse on the voltage input side for measure the current of NUC740 We had put a switch on the power input line that can let the power shut down and did not DC 5V on the PCBA If LAN port needs supply four ports The 2 5V power would come from the other 2 5V regulator The Power flow chart was show in FIGURE 8 Publication Release Date Apr 2009 11 Revision B NUC740 nuvoTon E User Manual 1 Power supply flow chart m FIGURE 8 Power flow chart 5 3 Memory Block The memory block includes three parts 128k 8 boot ROM 2 16 bits for application program and 512 4 32 M bits SDRAM The UF1 is 128k 8 boot ROM The JP62 must short pin and pin 2 The JP63 must short pin and pin2 for UF2 that saved the application program When the user uses the UF2 flash memory connects to boot rom bank that JP62 must open and JP63 must short pin 2 3 When you do this change that you must take care the boot room type PVF RF16 10K BOOTER HEADER 3 SDRAM size is 512 4 Banks 32 bits We use the Nuvoton solution W986432DH We connect with SDRAM follow rule of the FIGURE 8 Publication Release Date Apr 2009 12 Revision B NUC740 nuvoTon Dmm User Manual A 10 0 A 24 0 1 A 10 0 A13 BSO A14 BS1 D 31 0 DRI 31 0 MCLK CLK MCKE CKE nSCS 1 0 nscso ncs nSRAS nRAS nSCAS nCAS nSWE nWE nSDQM 3
38. ction would have two choices to do reset function One is that device has reset schematic on itself side The other one is which be control by the GPIO of the CPU We use a keypad for system reset The push bottom must functional when system is shutdown 4 10 Power 5V 3 3V and 1 8V are we needed power We used external DC 5V adapter supply the board power and used linear regulator change from 5V voltage to the 3 3V voltage and change from 3 3V voltage to 1 8V voltage We put the 5 linear regulators support CPU power VDD18 VDD33 USBVDD DVDD18 AVDDIS that destination is measure the CPU current S Circuit Block Description and Jumper Setting The circuit block has 7 parts 1 MCU 2 Power Block 3 Memory Block 4 PCMCIA Function Block 5 LAN Block 6 WAN Block 7 USB Function Block The Circuit blocks are shown in FIGURE 2 Publication Release Date Apr 2009 7 Revision NUC740 nuvoTon E User Manual PCMCIA Opao Roat _ TROD M waT C528 Aad Pc oe nWBE1 SDOM1 _OE WAN CPU M MEM 0 24 MEM D 0 31 OL0 WAIT i goa 3 goun E bs 8 MEM AQ 24 cui a cu 2 1 8 20 OE D 0 31
39. n x zs 18 88 7 E m ves mio on zx 80 Poen acis ee e HERE E 22 Hi ipm E io GES ps Feo BRE FEE 1 18 H eek 015 Fos Dia 3 M Ze 4 C REA GE 2 EZ 4054 pose i HEADER 220 2 Hg FAS T E EIN 5 4 5 ip p 28 E 2 BENN ann eios i uir Be mrs n 1m 47 aca DS 3 E USB INST s s 1 Mm x RES EE i m Enable ONT mon 03 1 TDOT RENN at bow at Um Ter 2c 13 DERE D 5 i i Em E i s Nucz4o 49458285 I ESCI ESC2 com ie E xen pnr ERE a d E 1 1 TACK E ERR i i 1 st Ties 1 ER i 1 fa 8 B CARA 43 com RR gt SD WER 47 RASS 9 6 HEADER 3 A CASE H 6 Sut SP RNa I rf m Exod BORA AL EAS Es
40. set time more than 240ms The function of the device is to assert a reset if either the power supply drops below a designated reset threshold level or is forced low This function take more ensure for system The other thing is that have a buffer to make sure reset signal fan out is enough We used a gate to association reset signal come from and MIC811 Reset IC 5VD RESET MIC811 TOP SWITCH FIGURE 4 Reset schematic We have expansion function is show the status by 7 LEDs that control by GPIO of the NUC740CD They GPIOO GPIO2 GPIO3 GPIO15 and GPIO16 Function EBI Test GDMA Test Cache On Off APB module amp NAT USB test GPIO GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 15 GPIO 16 Signal Name LMDO LMDI LMD2 LMD3 EO RC101 1 2 gt LED GREEN 1 RC1 3Y 1K Q DC3 7 LED GREEN EO RC1 4Y 1K DC4p gt LED GREEN LMD3 RCTO5 1K DC5p 44 LED GREEN LMD2 RC1 6 1K gt LED GREEN LMD1 RC1 7Y 1K gt LED GREEN LMDO FIGURE 5 Status LED The power on setting that we follow next table Power On Setting Internal System Clock Select Little Big Endian Mode Select Boot ROM FLASH Data Bus Width 015 JP8 014 JP7 D 13 12 JP6 JP5 D 11 10 Fixed D 9 8 JP2 JP1 Test Chip ConFiguration Package Type Select Publication Release Date Apr 2009 9 Revision
41. thernet controller that reduces total system cost An NAT Accelerator is support to reduce the software loading for network address translation processing We support 15MHZ frequency for CPU In the PCBA that would have test point for every one pin The Publication Release Date Apr 2009 5 Revision NUC740 User Manual others that we do use power regulator support the power of the NUC740 4 2 Flash and SDRAM We put boot room flash and SDRAM on the evaluation board The boot room sizes 1 piece 256K 8 bits PLCC package They are using the ROM bank We would put the other flash for application program The sizes could be 2M 16 or 1M 16 bytes or 0 5M 16 bytes TSOP package which used the external I O bank The SDRAM has one piece and sizes are 2M 32 bytes 43 PCMCIA connector We support one PCMCIA 16 bits PC Card socket The main goal destination is which can connects with wireless LAN card It is using the external memory interface of CPU We would use bank two and high address A23 to control I O or attribute access 4 4 PHY WAN port and LAN port This is main function that do broadband gateway We choose one port PHY IC of DM9161 of DAVICOM It supports MII mode and RMII mode We made connect WAN port and LAN port on board or it can connect with an external wire The function block would show some connect status LED We have an extension function one MII socket That is for used the daughter bo
42. wo schematic One connects to reset system The other is local RC reset schematic Which one used depends by system design They JP16 JP36 show on the FIGURE 11 RL2 100K 10uF FIGURE 11 Reset Schematic The LAN clock is come from two kind parts too They are crystal and OSC The FIGURE 12 is their schematic HEADER 3 Publication Release Date Apr 2009 14 Revision B NUC740 NUVOTON User Manual XT1 XT1 121 25 50 MHz HEADER 3 22pF REF CLK ug E 25 MHz XT2 CL22 22pF FIGURE 12 LAN Clock generator In order to make sure that expand function work well We control on off signal with the switch SW1 SW2 SW3 LAN SW4 SW5 SW6 WAN We must turn off them when we test Ethernet expansion function That can make sure signals no influence with others They show on FIGURE 13 sw2 SW3 COL 1 16 COL1 MDC MDC1 R 2 15 RS1 TX CLK TX1 CLK RX CLK 3 14 RX1 CLK TX EN TX1 EN RXDO ay RXTDO TXDO TX1DO RXD1 5 1 1 12 RXTD TXD1 TX1D1 RXD2 6 9 11 RXTD TXD2 TX1D2 RXD3 7 10 E TXD3 TX1D3 MDIO 8 9 TX ERR TX1 ERR SW 1X8 SW1 RX DV RX0 DV RX DV RX1 DV RX ERR RX0 ERR RX ERR RX1 ERR DIP AW SW5 COL COLO MDC MDCO R 2J m 115 CRSO TX TXO CLK RX_CLK 3 14 CLK TX EN EN RXDO 4 rum RXODO TXDO TXODO RXD 51 12 RXOD TXD1 TX0D1 RXD2 6 11 RX0D2 TXD2 TXOD2 E Sy XD 7 10 OD
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