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1. Acroma g THE LEADER IN INDUSTRIAL 1 0 VPX VLX85 VPX VLX110 VPX VLX155 VPX VLX85CC VPX VLX110CC VPX VLX155CC USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 920 A11F000 VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Table of Contents 1 0 GENERAL INFORMATION uc ccccccccsccsccescesccsccsscnscesccsccnsenscnscnsenscnsensecnsensensenssensensensennsenss 5 Ordering NO HIV ACI ONIN isis napa rd detiene 5 a AP e E nn o EE E ATT 6 PCle Interface Features cccssccscccsccccccccscccscccscccccsccscccsccccccccssccsscosccccssccsscossccsccsesscesscosccceess 7 SON iii 7 ENGINEERING DESIGN KIT cccccccccccccccsccccccceceececcccececcccccececcececececeeeeceeeeesececeeceeeececeseseceeeeseecececececceceeececeecens 7 BOARD DLL CONTROL SOFTWARE cccccccccccccccccececceccecccccececececeeeeceeeecececeeeecseceecececeeeeeeeececeeseeeeeseceeceeeeeceecens 8 BOARD VxWORKS SOFTWARE ccccccccccecececeecceccccceceeccececeeceececececeeceeeececeeeeeeceecececeesesecececeesesececeecececceececccecens 8 BOARD QNX SOFTWARE isso Error Bookmark not defined BOARD Linux SOFTWARE cccccccccccceccccccccccccececceececcececeeeceseececececeeceeeececeeeeseceeeeceeeeeecececececeeeceeeeececeeccececececens 8 OT ON INC CS
2. A Flash Erase Chip command is executed by writing logic 1 to bit 0 of this register at base address plus 24H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 of the Flash Status 2 register as logic 0 The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic O when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase chip operation will be ignored Note that a hardware reset during the chip erase operation will immediately terminate the operation Flash Data Register Read Write BAR2 28H This read write register holds the data byte which is sent to the flash chip upon issuing of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 7 gt 0 Read Write BAR2 2CH This read write register holds the least significant byte of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 15 gt 8 Read Write BAR2
3. 30H This read write register sets bits 15 to 8 of the address to which the flash chip is written upon issue of a Flash Start Write command Although only the least significant 8 bits of this register are used reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Flash Address 23 gt 16 Read Write BAR2 34H This read write register sets bits 23 to 16 of the address to which the flash chip is written upon issue of a Flash Start Write command The upper 7 bits of this register are used to select Flash sectors for erasure Reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfer Acromag Inc Tel 248 295 0310 40 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Flash Configuration The VPX VLX board uses a flash configuration device to store programming information for the Xilinx FPGA The flash configuration device and FPGA are hardwired together so that during power up the contents of the configuration device are downloaded to the FPGA The flash configuration data can be reprogrammed using the PCle bus interface The following is the general procedure for reprogramming the flash memory and reconfiguration of the Xilinx FPGA 1 Acromag Inc Tel 248 295 0310 Disable auto configuration by setting bit O Stop Configuration of the Configuration Control register to logic high Clear the Xilinx FPGA of its previous configuration by
4. 8048H 804CH Note An SRAM DMA Request will occur only after a data write cycle to the address defined by the DMA Threshold Registers Table 3 18 Dual Port DMA Threshold Registers Reset Values Acromag Inc Tel 248 295 0310 The FPGA Port SRAM DMA Channel 0 1 Threshold Registers are used to initiate an automatic DMA transfer When the internal address counter is equal to the value in the DMA Channel 0 Threshold Register a Channel O DMA request will be initiated Similarly when the internal address counter is equal the value in the DMA Channel 1 Threshold Register and there is valid data at that address a Channel 1 DMA request will be initiated This feature must be enabled via bits 1 and 2 for Channels O 1 respectively of the FPGA SRAM Control Register Note that DMA settings must be configured prior to the initiated transfer on both the BARO and BAR2 registers ADMA transfer in progress is indicated via bits O and 1 for DMA Channels O and 1 respectively in the DMA Control Register See the DMA Registers section of this manual for further details Reading of the Threshold register will return the corresponding DMA Threshold Writing the Threshold registers will set the corresponding DMA Threshold to the provided value Bits O to 19 of this registers are used in the VPX VLX Reading or writing to this register is possible via 32 bit data transfers only FPGA Port SRAM DMA Channel 0 1 Threshold Registers Reset Values
5. DMA Command Registers Read Write BARO 10CH and 12CH occcccccnnccnnnnnnnnnnnnancncncnananananonononononano 33 DMA VPX Board Starting Address Registers Read Write BARO 110H and 130H eee 34 Start DMA Transfer Write Only BARO 114H and 134H oocccccnnnncnnnncnnnccnnnnnonoccnnnnonacnnnnnonaronnnonanonoss 34 BARZ MEMORY DAPR eet eu sceuathews 35 Flash A E A 41 Direct PCle DUS TO XIN COMIEUra Ol yoana a E a 42 Configuration Status Register Read Only BAR2 OOOOH oooccccccnnnccncncnnnccnnnnnnnccnnncnnnccnnncnnanonononaninonos 37 Configuration Control Read Write BAR2 04H ooooononnnnnncccnnnnnnnnnnonononononanancccnnnncnnnnnnnnononononananacncnnnns 37 Configuration Data Write Only BAR2 O8H ccccccsccsssecccecessecccseesecesseesesesseensecesseeeeecesseenessesss 37 Flash Status 1 Read Only BAR2 FOCH eremie ia 38 Flash Status 2 Read Only ABAR TO a A T E E TT RE 38 Flash Read Read Only BAR 2 42 14 Fl octal 38 Flash Reset Write Only BAR2 18H ooocccncccnncccnncnnncccnnnonanoconononaronononanonnnnnnnnononnnnnnornnnnnnaronnncnnanonanonos 39 Flash Start Write Write Only BAR2 1CH iii ct 39 Flash Erase Sector Write Only BAR2 20H sssesssseessssresssreresesseressserenssrsresssssressseeeessrsreesseeresssereessss 39 Flash Erase Chip Write Only BAR t 24H a a 40 Flash Data Register Read Write BAR2 28H oooocc
6. This VLX module uses the 150 pin Samtec connector part number QSS 075 01 L D A which mates with the mezzanine module connector part number QTS 075 02 L D A K Write Disable Jumper Write Disable Jumper Removal of surface mount resistor R172 disables write to the to the Xilinx FPGA configuration flash device The location of R172 is shown in resistor location drawing If write disable to the configuration flash is required it is recommended that the board be returned to Acromag for removal of R172 The board can be easily damaged without the use of special SMT tools Board Crystal Oscillator 125MHz Frequency Stability 0 0020 or 20ppm Double Data Rate 2 SDRAM 32M x 32 bit Density e Micron MT47H32M16CC SDRAM Crystal Oscillator 200MHz e Frequency Stability 0 01 or 100ppm DDR SDRAM Clock 125MHz Data Transfer Rate 250M longwords 32 bits s Acromag Inc Tel 248 295 0310 69 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Dual Port SRAM VPX VLX 1Meg x 64 bit Integrated Devices Technology IDT70T3509MS133BP 133 Megahertz Speed Flash Memory 16M x 8 bit 128 addressable sectors of which 41 are used for FPGA Configuration PCIe Bus Interface PCI Express 1 1 PCI Express electrical and protocol standards Performs 2 5 Gbps data rate per lane and per direction ANSI VITA 42 0 Complies with XMC module mechanicals and connectors ANSI VITA 42 3 XMC module with PCI Express Interface 4K Memory S
7. U7 Acromag Inc Tel 248 295 0310 60 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DDR2 SDRAM supports continuous writes or single cycle reads The SRAM port connected to the PCle bus through U5 supports reading and writing using a burst double word 4 byte or DMA transfers For double word 4byte accesses address and control signals are applied to the SRAM during one clock cycle and either a write will occur on the next cycle or a read in two clock cycles DMA accesses operate using the continuous burst method for maximum data throughput The control signal starting address and data if writing are applied to the SRAM during one clock cycle Then during a write DMA transfer new data is applied to the bus every subsequent clock cycle until the transfer is complete During DMA transfers the address is incremented internally in the Dual Port SRAM Please refer to the IDT70T3509SM Data Sheet See Related Publications for more detailed information The board contains two 32M x 16 bit DDR2 SDRAM devices The DDR2 SDRAM uses double data rate architecture to achieve high speed operation The double data rate architecture has an interface designed to transfer two data words per clock cycle DDR2 Data strobe signal DQS is edge aligned with data for reading data and center aligned with data for writing data The DDR2 SDRAM provides for programmable read or write burst lengths of four locations The example
8. VPRW is 5V for the XMC On Board 1 0V Power to Current Rating Virtex 5 FPGA Maximum available for the user programmable FPGA les Operating Temperature Airflow Requirements Model Op Temp Airflow Requirements VPX VLX 0 C to 70 C 100 LFM ENVIRONMENTAL VPX VLX CC 40 C to 85 C 200 CFM if not installed in a conduction cooled chassis Relative Humidity 5 95 Non Condensing Storage Temperature 55 C to 100 C Non Isolated PCle bus and field commons have a direct electrical Acromag Inc Tel 248 295 0310 66 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL connection Conduction Cooled XMC mezzanine card VPX VLX CC models comply with ANSI VITA 20 2001 R2005 Designed to meet the following environmental standards per ANSI VITA47 2005 R2007 Model VPX VLX Environmental Class EAC4 Operating Temperature AC1 0 to 70 C Non Operating Class C3 Vibration Class V2 Shock 20g Model VPX VLX CC Environmental Class ECC3 Operating Temperature CC4 40 to 85 C Non Operating Class C3 Vibration Class V3 Shock 40g Designed to comply with EMC Directive 2004 108 EC Class B Radiated Field Immunity RFI Complies with IEC 61000 4 3 with no register upsets Conducted R F Immunity CRFI Complies with IEC 61000 4 6 with no register upsets Surge Immunity Not required for signal I O per IEC 61000 4 5 Electric Fast Transient EFT Immunity Complies with IEC 610
9. 5 Global Interrupt as FUNCTION Enable Bit Not Used bits are read as logic O 0 Board Interrupts Disabled Han Interrupts Enabled VPX Board Interrupt Enable This bit must be set to enable the PCle bus interrupt signal to be driven active Acromag Inc Tel 248 295 0310 31 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DMA System Starting Address LSB Registers Read Write BARO 100H and 120H This register contains the least significant 32 address bits of the DMA System Starting Address The DMA System Starting Address register meaning depends on the selected DMA mode see bit 3 of DMA command register For Direct DMA Mode this address register specifies the physical address of a contiguous memory buffer where data will be read written For scatter gather DMA mode this address register points to the first element of the chained listed of page descriptors The DMA System Starting Address Register at BARO base address plus 100H 120H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit transfers DMA System Starting Address MSB Registers Read Write BARO 104H and 124H This register contains the most significant 32 address bits of the DMA System Starting Address The DMA System Starting Address register meaning depends on the selected DMA mode see bit 3 of DMA command register For Direct DMA Mode this address regis
10. AE on etouatatee E 70 PEEB 0K Ataca dai 70 Certificate of Volatility cicera nE E ou cenaoacanemees sunemavecemsnceeenoeneees 71 VPX VLX BlOCk DIA AM AAA 72 All trademarks are the property of their respective owners IMPORTANT SAFETY CONSIDERATIONS You must consider the possible negative effects of power wiring component sensor or software failure in the design of any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility The information of this manual may change without notice Acromag makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc RELATED PUBLICATIONS The following manuals and part specifications provide the necessary information for in depth understanding of the AX board Virtex 5 Data Book http www xilinx com IDT70T3519S Spec http www idt com IDT70T3509MS Spec http www idt com Acromag Inc Tel 248 295 0310 4 w
11. D19 DO Register D30 D20 DMA Channel 0 Threshold Reg DMA Channel 1 Threshold Reg Not Used Read as logic 0 7FFFFH Not Used Read as logic 0 FFFFFH 50 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL FPGA Port SRAM Address Reset Registers 0 1 Read Write BAR2 8050H 8054H WARNING The DMA Ch 0 Threshold Register must not equal the Address Reset Register 0 and the DMA Ch 1 Threshold Register must not equal the Address Reset Register 1 If these registers are equal and the address reset is enabled via the FPGA Port SRAM Control Register an infinite loop will be created within the internal logic of the FPGA The FPGA Port SRAM Address Reset Registers are used to reset the internal address counter to a user defined value immediately upon reaching the DMA Threshold value For example after an SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 0 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 0 Similarly after a SRAM write cycle where the internal address counter is equal to the value defined in the DMA Channel 1 Threshold Register the internal address counter will then be loaded with the value defined in the Address Reset Register 1 This allows for the internal address counter to be changed without any interruption in the tr
12. SRAM read write interface logic PCle Bus A four lane PCI Express 1 1 bus operating at a speed of 2 5 Gbps per lane per direction is provided This gives up to 2GBytes sec data rate on the bus PCle Bus Master The PCle interface logic becomes the bus master to perform DMA transfers DMA Operation The PCle bus interface supports two independent DMA channels capable of transferring data to and from the on board SRAM The example design implements DMA block and demand modes of operation 64 32 16 8 bit I O Register Read Write is performed through data transfer cycles in the PCle memory space All registers can be accessed via 32 16 or 8 bit data transfers Access to Dual Port Memory can be accessed via 64 or 32 bit transfers Compatibility Complies with PCle Base Specification Revision 1 1 Provides one multifunction interrupt The VPX VLX is compatible with XMC VITA 42 3 specification for P15 All VPX VLX products will require support drivers specific to your operating system Acromag provides an engineering design kit for the VLX boards sold separately a must buy for first time VLX module purchasers The design kit model XMC VLX EDK provides the user with the basic information required to develop a custom FPGA program for download to the Xilinx user programmable FPGA The design kit includes a CD containing schematics parts list part location drawing example VHDL source and other utility files T
13. connector is a 64 pin female receptacle header AMP 120527 1 or equivalent which mates to the male connector on the VPX PMC XMC module carrier board AMP 120521 1 or equivalent N R e 0 OY U1 Un Un On Un P Es W 0 IWIWIWINININININ jejejejeje N U9 WW W O V UT IN e N W W 10 J UT IN FR 100 IN JB JW 1O WO DM ON e ch o Em 2 Em a E 6 zZ 8 cm ECA ES EN Non Isolation Considerations The board is non isolated since there is electrical continuity between the VPX backplane and VPX VLX board grounds As such the field I O connections are not isolated from the system Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections Acromag Inc Tel 248 295 0310 11 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL The model VPX VLX field I O connections are made through the rear via J4 for a single PMC XMC mezzanine I O module card Flash Write Disable Resistor By default the flash memory U6 is read write enabled Removal of resistor R172 disables writing the flash configuration device Refer to the Resistor Location Drawing at the end of this manual to identify the board location of R172 Jumper Settings for the VPX VLX PCIe Lane Selection Ground Selection The VPX VLX has two jumpers for selecting the number of PCle lanes used from the backplane and another to control how the chassis
14. design provided by Acromag is designed for a fixed burst length of four A burst length of 8 is also available but not supported by the Acromag example design The DDR2 SDRAM operates from a differential clock DDR2_CK and DDR2_CK_n the crossing of DDR2_CK going HIGH and DDR2_CK_n going LOW will be referred to as the positive edge of DDR2_CK Commands address and control signals are registered at every positive edge of DDR2_CK Input data is registered on both edges of DQS and output data is referenced to both edges of DQS as well as to both edges of DDR2_ CK Acromag Inc Tel 248 295 0310 61 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Local Bus Signals The local bus interface between the PCle bus interface chip U5 and the user programmable FPGA U7 consists of the following signals The Local Address bus LA bits 21 to 2 are used to decode the 4M byte address space allocated by the PCle bus to BAR2 Also LA 26 bit 26 of the local address bus is logic high when the PCle bus is performing an access to BAR2 address space LBEO_n LBE1_n LBE2_n and LBE3_n are the local bus byte enables LBEO_n when logic low indicates that the least significant byte on data lines D7 to DO is selected for the read or write transfer Likewise LBE3_n when logic low indicates that the most significant byte on data lines D31 to D24 is selected for the read or write transfer The Local Data LD bus bits 31 to O are bi d
15. ground is connected Note that the jumpers are in the same location on each model regardless of the presence of the conduction cooling metalwork This jumper sets the VPX VLX to use the first 4 lanes fat pipe or the first 8 lanes double fat pipe from the backplane Users should take care that these lanes are routed directory to the host card and are not shared by another module The default selection is 4 lanes Refer to diagram below for jumper position This jumper allows the user to attach the board metalwork chassis ground to either the DC ground or let it remain isolated The default selection is to attach it to ground Refer to diagram below for jumper position Acromag Inc Tel 248 295 0310 12 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL ee TS Pins 1 2 CHS G attached to bo D GND Defa 2 E e ETS Pins 2 3 CHS C Eat Bree EN enn floating IHES NE Pt Re la ult AA E h Rear Connector Pinout The following tables list all the board connections to the PMC J4 Rear I O connector Rear Site Connector J4Mapping to VPX Backplane P2 Connector Table 2 2 PMC Rear I O This connector contains the PMC XMC Rear J4 I O Signals These signals Signals are routed to the VPX backplane P2 connector a Rearing a p2 er 2 Rearin4 2 P2B1 3 Rearinw3 p2D1 4 Rearin4 4 P2 A1 5 Rearing5 P2F2 6 Rearjn4 6 p2c2 7 Rearin47 P2 2 8 amp 8 Rearin4 8 P282 9 Rearin4 9
16. iaa a dao 8 2 0 PREPARATION FOR USE avsscscccscccccssccnscesccsccsccnscnscnsccnsenscnsecsecnsensensecnsensensensensensensessenses 8 Unpacking and Inspecting suis aaa 8 Card Cage Considerations susissnassicaaor scsi 9 BARDIA eaa EE A A 9 Default Hardware Configuration for the VPX VLX cccccccsssseccecceeseccccseesecceseaeseceeseaueeceesseeneceessuaeeeeesseees 10 Front Panel Field I O CoNNector o occccnoccccononccnonencnononccnononcanonarenonoarononarcnonnarenononrcnonarcnonnarenonanccnanarenononoss 10 Rear P4 Field I O Connector ccccccsescccccscccccsseccccuseccccnececcsescncececsesececcececcseneseasesesescucesenneseaceceseneneeees 10 Non Isolation Considerations ccccccscccccccccccccccccccccscccsccccccccccccscccsccccccccsccesscecsccsscccsscescces 11 Flash Write Disable Resistor ici 12 Jumper Settings for the VPX VLX ccscsccccscscscsccscscsccccccsceccscecscecescccscececcecscnceseececsceseecess 12 e aa Be ahem E a a A E rene EA 12 ELTA S Ee SC CIO EEEE EEA EEE EAEE ENE A 12 Rear Connector PNO tas date 13 Rear ote Connector A EE EE Ea 13 XMC Connector PINO inicias cds 14 XMC Connector P5 ssssesssssssessseeeressereresseerereserereressorreseseoreresseereseeoerresesrereeeesoereseeserrreeseereeseseoreeeeeeoresesoeeeees 14 VPX Backplane Connector PiNoutS sessesessesessssecssoecescesesoecesoecessecescecesosceseececeeoeseecessesese 16 VPX PO Connector Power and System COntrols cccccsssccccssscccce
17. logic 0 There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via bits 23 17 of the Flash Address 23 16 register at base address plus 34H Issuing a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified A flash bit cannot be programmed from logic O to logic 1 Only an erase chip operation can convert logic O back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip or Flash Erase Sector command must be performed The system can determine the status of the erase operation by reading the Flash Ready Busy status Bit 7 of the Flash Status 2 register at base address plus 10H will read as logic O when chip erase is completed Any other flash commands written to the flash chip during execution of the flash erase sector operation are ignored Note that a hardware reset during Acromag Inc Tel 248 295 0310 39 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL the erase sector operation will immediately terminate the operation Flash Erase Chip Write Only BAR2 24H This write only register is used to erase the entire contents of the flash chip A flash bit cannot be programmed from logic O to logic 1 Only an erase chip operation can convert logic O back to logic 1 Prior to reprogramming of the flash chip a Flash Erase Chip command must be performed
18. or DREQ1 active The SRAM control register method allows a DMA transfer to be initiated when an FPGA generated address counter is equal to the DMA Channel Threshold Register That is when the predetermined amount of data is available in the SRAM the hardware will automatically start a DMA transfer Interrupt Control Status Register Read Write BARO 00H This Interrupt Control Status register at BARO base address offset OOH is used to monitor and clear pending board interrupts An interrupt can originate from the two DMA channels or U7 the user programmable FPGA All board interrupts are enabled or disabled via bit 31 of the Global Interrupt Enable register at BARO O8H Table 3 3 Interrupt Control Status Register Bit s FUNCTION When designing software This bit when set indicates a pending board interrupt It ape reflects a pending interrupt from DMA channel 0 or DMA drivers it is best to treat this channel 1 or the U7 FPGA It will reflect this status even if the register as two 16 bit registers Board Interrupt enable bit 31 is disabled The upper 16 bits are Interrupt TO No Interrupt Pending Control bits and the lower 16 interrupt Pending bits are Interrupt Status al DMA Channel 0 Interrupt Pending Status Bit 16 must be set to logic high for this bit to go active Write logic high to clear bit 0 No Interrupt Pending Interrupt Pending DMA Channel 1 Interrupt Pending Status Bit 17 must be set to logic h
19. setting the Configuration Control register bit 2 to logic high Software must also keep bit 0 set to a logic high Read INIT as logic high Bit 1 of Configuration Status register before programming is initiated Verify that the Flash Chip is not busy by reading bit 7 of the Flash Status 2 register at base address plus 10H as logic O before starting a new Flash operation Erase the current flash contents by using the Flash Erase Sector method Flash erase sectors are implemented by setting bit 0 of the Flash Erase Sector register to logic high There are 128 flash sectors which are addressed via the most significant seven flash address lines The most significant seven flash address lines are set via the Flash Address 23 16 register at base address plus 34H Issuing a Flash Erase Sector command will erase the contents of the flash chip only in the sector specified Verify that the Flash Chip is not busy by reading bit 7 of the Flash Status 2 register at base address plus 10H as logic O before going to the next step Download the Configuration file to the flash configuration chip via the PCle bus i Write the byte to be sent to the Flash Data register at base address plus 28H ii Write the address of the Flash Chip to receive the new data byte to the Flash Address registers at base address plus 2CH 30H and 34H Issuing a Flash Start Write will automatically increment this address after the prior Flash Write has been completed T
20. that the flash be overwritten until you have tested your code The reconfigure direct method will allow programming of the FPGA directly from the PCle bus If for some reason the VPX VLX does not perform as expected you can power the VPX VLX down Upon power up the example design provided by Acromag will again be loaded into the FPGA The Using the XMC SLX Engineering Design Kit document provided in the engineering design kit will guide you through the steps required to modify the example design for your custom application See the Direct PCle bus to Xilinx Configuration section for a description of the steps required to perform reconfiguration directly from the PCle bus The registers provided in the FPGA Programming Memory Map are used to implement a direct reconfiguration After you have thoroughly tested your customized FPGA design you can erase the flash and write your application code to flash Once the flash 24 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL is erased you will not be able to go back to the example design by simply powering down and restarting the board See the Flash Configuration section for a description of the steps required to write new data or to reprogram the example design code to the flash device The registers provided in the FPGA Programming Memory Map are used to implement a flash erase and reprogram operations PCle CONFIGURATION ADDRESS SPACE This boar
21. 00 4 4 Level 2 0 5KV at field I O terminals Electrostatic Discharge ESD Immunity Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge Level 2 4KV enclosure port contact discharge Radiated Emissions Meets or exceeds European Norm 61000 6 3 2007 for class B equipment Shielded cable with I O connections in shielded enclosure is required to meet compliance Acromag Inc Tel 248 295 0310 67 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL VPX Specification Compliant with VITA 46 Base VPX Standard VITA 46 4 complaint backplane signals 4x fat pipe PCle jumper selected Rear I O routed per VITA 46 9 P2w1 P64s Front I O is only available on the VPX VLX air cooled model if optional AXM modules are installed Backplane Compatible with the following VITA 65 Profiles Module Profile Slot Profile MOD3 PER 2F 16 3 1 3 SLT3 PER 2F 14 3 1 MOD3 PER 1F 16 3 2 2 SLT3 PER 1F 14 3 2 MOD3 PAY 2F 16 2 7 1 SLT3 PAY 2F 14 2 7 MOD3 PAY 1D 16 2 6 1 SLT3 PAY 1D 14 2 6 1 Board is compatible with payload profiles but has no hosting capabilities This list is not all inclusive Other profiles may be compatible Contact the factory with any questions User Programmable U7 FPGA VPX VLX85 Xilinx XCSVLX85T 1FF1136 e 51 840 CLB Flip Flops e 840 000 Distributed RAM Bits e 216 18Kbit Block RAMs e 48 DSP Slices 6 Clock Management Tiles User Programmable U7 FPGA VPX VLX110 Xil
22. 10 VPX VLX155 USER S MANUAL VPX VLX CC Conduction Cooled Step 1 Take your XMC module and verify that the front panel has been removed Verify the jumper settings now Step 2 Loosen the two screws on the standoff of the XMC module by about 1 turn This will allow you to easily move the position of the hex standoffs Step 3 Install the XMC module onto the VPX CC carrier by carefully angling the board so that the board to board connectors align and then pressing downward If the hex standoffs prevent the insertion of the board rotate them slightly until the module will fit Angle Board to align XMC mating connectors Loosen standoff screws Press downward turning standoffs 2x if needed Acromag Inc Tel 248 295 0310 21 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Step 4 Install the 16x M2 x 6 screws on this side of the board and tighten the 2 standoff screws ad hn aaaa gaaa gana C 4 94V 8 E189010 Acromag Inc Tel 248 295 0310 22 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 Acromag Inc Tel 248 295 0310 USER S MANUAL Step 5 Flip the VPX VLX CC over and install 2x M2 5 x 5 screws for the standoffs into the locations noted in the picture below Optionally users can install another 10x M2 x 6 screws into the bottom to further secure the VPX VLX to the metalwork Install 2x M2 5 x 5 screws Optional 10x M2 x 6 screws Note that only f
23. 5 can be monitored via the Flash Status 1 register at base address plus OCH Flash Reset Write Only BAR2 18H This write only register is used to initiate a reset of the flash chip A Flash Reset command is executed by writing logic 1 to bit 0 of this register at base address plus 18H Writing the flash reset command resets the chip to reading data mode Flash reset can be useful when busy is held active Flash Start Write Write Only BAR2 1CH This write only register is used to initiate the write of a byte to the flash chip A Flash Start Write command is executed by writing logic 1 to bit 0 of this register at base address plus 1CH Prior to issuing a Flash Start Write the Flash Data and Address registers must be set with the desired data and address to be written See the Flash Data and Address registers at base address plus 28H 2CH 30H and 34H Issuing a Flash Start Write will automatically increment this address after the previously issued Flash Write has completed Thus the address will not need to be set prior to issuing the next Flash Start Write if consecutive addresses are to be written Flash Erase Sector Write Only BAR2 20H A Flash Erase Sector command is executed by writing logic 1 to bit 0 of this register at base address plus 20H Verify that the Flash Chip is not busy from a previous operation before beginning a new operation This is accomplished by reading bit 7 of the Flash Status 2 register as
24. 805CH to logic high Acromag Inc Tel 248 295 0310 55 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DDR SDRAM Mask Register Read Write BAR2 8084H The DDR SDRAM mask register holds the write mask data bits that accompany the write data as it is written to the DDR SDRAM If a given data mask DM bit is set low the corresponding data will be written to memory If the DM bit is set high the corresponding data will be ignored and a write will not be executed to that byte location The DDR SDRAM is set for a burst of four for the purposes of this design example Table 3 23 DDR SDRAM Mask DDR SDRAM Mask Register Register Bit Write Register Byte Masked Byte O DO to D7 Byte 1 D8 to D15 Byte 2 D16 to D23 Byte 3 D24 to D31 Byte O DO to D7 Byte 1 D8 to D15 Byte 2 D16 to D23 Byte 3 D24 to D31 ae 1 All bits labeled Not Used will return logic O when read Byte 1 D8 to D15 Byte 2 D16 to D23 Byte 3 D24 to D31 Byte 0 DO to D7 Byte 1 D8 to D15 Byte 2 D16 to D23 B as 7 3 D24 to D31 T gt Not Po NotUsed Read or writing this register is possible via 32 16 or 8 bit transfers Acromag Inc Tel 248 295 0310 56 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL System Monitor Status Control Register Read Write BAR2 8088H This read write register will access the system monitor register at the address set in the System Monito
25. D GND GND GND GND GND GND GND GND GND Note BOLD ITALIC signals are NOT USED by this carrier board Acromag Inc Tel 248 295 0310 18 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Rear I O pin mapping diagram as defined in VITA 46 9 This product is complaint to rear I O routing P2w1 P64s DE r4 Ki 4 EJ O y ALO EJ 10 kki Cpa ae LAN 2 jo A AA AAA AE a PRISA Cue A A 7 Set STP aAA FS Installing and Removing XMC Module The procedure for installing the XMC module onto the VPX card varies depending on the model VPX VLX Air Cooled Step 1 Take the XMC module and verify that it has a front panel attached and properly screwed into the XMC module 2X M2 5 x Step 2 Install the XMC module onto the VPX carrier by carefully angling the board so that the front panel slips though the gap in the metalwork Once set align the connectors and gently push down until the connectors are fully seated Acromag Inc Tel 248 295 0310 19 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL ath at w gt ig t ATT ded TE A 4 A i Step 3 Flip the VPX VLX over and install 4x M2 5 x 5 screws into the locations noted in the picture below These correspond to the standoffs and the front XMC panel on the attached module Acromag Inc Tel 248 295 0310 20 www acromag com VPX VLX85 VPX VLX1
26. PRW is 5V on the VPX VLX CoN JU Le CS A O 1 oe poem ow perm pom r GND GND TCK GND GND MI GND GND TMS GND GND a CI GND GND TDI GND GND RFU RFU RFU RFU RFU GND GND TDO GND GND GAO GND GND GA1 GND GND Acromag Inc Tel 248 295 0310 14 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL GND GND GA2 GND GND MSDA PCleR4p PCleR4n RFU PCleR5p PCleR5n GND GND MVMRO GND GND MSCL PCleR6p PCleR6n RFU PCleR7p PCleR7n RFU GND GND RFU GND GND RFU Acromag Inc Tel 248 295 0310 15 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL VPX Backplane Connector Pinouts VPX PO Connector Power and System Controls Table 2 4 VPX PO Connector Table 2 4 indicates the pin assignments for the VPX 3U assignments at the PO connector The connector consists of 8 wafers with up to 7 signals on each The system management bus signals SMO SM1 SM2 and SM3 use I C to implement the Intelligent Platform Management Bus IPMB per VITA 46 11 CAUTION The VPX VLX CAN NOT BE PLUGGED INTO A 6U VPX SYSTEM DUE TO POWER INCOMPATIBILITIES BETWTEEN THE 3U AND 6U FORM FACTORS PLUGGING THE VPX VLX INTO A 6U SYSTEM WILL DAMAGE THE BOARD Refer to the VPX specifications for additional information on these signals Water rowe Row rowe RowD Rowe Rows Rowa Coa f ax aa ow ea as es gt eave vv SM2 SM3 GND 12V_AUX GND SYSRST NVMRO GAP GA4 GND 3 3V_AUX GND SMO SM1 GA3 GA2 GND 12
27. Reg D31 D24 D23 D16 D15 D8 D7 DO Registers Num Device ID Vendor ID 0x5801 VPX VLX85 0x5802 VPX VLX110 16D5 0x5804 VPX VLX155 ap Status Command 2 ClassCode 118000 ReviD 00 3 ist Header Latency Cache 64 bit Memory Base Address for Memory Accesses to PCle interrupt and DMA Registers 4K Soace BARO 64 bit Memory Base Address 32 bit Data to Virtex 5 Na User Registers 4M Space BAR2 64 bit Memory Base Address 64 bit Data NA to Dual Port Memory 8M Space BAR4 to Notusd y O Subsystem ID Subsystem Vendor ID 0x5801 VPX VLX85 0x5802 VPX VLX110 16D5 0x5804 VPX VLX155 1 5 1 10 1 1 13 14 Acromag Inc Tel 248 295 0310 26 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL This board is allocated memory space address BARO to access the PCle interrupt and DMA registers The PCle bus decodes 4K bytes for these memory space registers This board is allocated a 4M byte block of memory BAR2 that is addressable in the PCle bus memory space BAR2 space is used to access the board s flash configuration functions and the reprogrammable Virtex 5 FPGA registers In addition this board is allocated BAR4 memory of 8M bytes The BAR4 memory is addressable in the PCle bus memory space to access the board s Dual Port Memory transfers Note that the base model VPX VLX does not utilize the entire block of memory Acromag Inc Tel 248 295 0310 2 www acromag
28. SV 14 S XALUYIA 919801 ld ha ir JINON WXY sng 3NINVZZIN TANVWd 1NOYW 91901 TOYLNOO SOVAYALN WVYS z Yad 3dO9SdIHO DVWLP VOds4 S XALUIA 91 X INGE NV4ds 91 X INGE NVy4as c ALVY VLiVd 319no0 c ALVY ViVvd 31a4n00 WWW acromag com Ta Acromag Inc Tel 248 295 0310 VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL R172 Resistor Location Board Bottom View ee ones aL E 1 Fre Em foe dr a E y Y 34 k BATEE CS TT E PE RE i hi b ie Tea gi il a 2 ALSe B LOL WSN WOXIM DVINOYIW weet yobs iat ae ae A a E ah n an F a aia aly o aye aperea A EL ens Acromag Inc Tel 248 295 0310 73 www acromag com
29. UUUUUUU la 21 downto A O O OSOS SSO ld 00003030 ads_n A CST a a readyn OO hr on TR lbe0_n lbei_n lbe2_n lbe3_n la 26 Local Bus Read Cycle Diagram ck LIU UUU UU UU UU UU UU UU UU UU UU UU la 21 downto 2 001 Jozoso A o ld 00000005 00000000 ads_n A rdyack_n a O lt I of har on Ibe0_n lbei_n Ibe2_n Ibe3_n la 26 Local Bus Write and Read Cycle Diagram d LU U U UU UU UU UU UU UU UU UU UU uuu la 21 downto 2 0200E 02011 ld 0000A0A0 00003030 un ps 8 ryan LS readyn hw_r_n a Ibe0_n lbei_n Ibe _n lbe3_n la 26 Acromag Inc Tel 248 295 0310 64 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL 5 0 SERVICE AND REPAIR Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board Whena board is first produced and when any repair is made it is tested before shipment Service and Repair Assistance Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair Preliminary Service Procedure CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Where to Get Help Before beginning repair be sure th
30. V_AU GND GA1 GAO TCK GND TDO TDI GND TMS TRST GND REF_CLK REF_CLK GND RES RES GND Note BOLD ITALIC signals are NOT USED by the VPX VLX board Acromag Inc Tel 248 295 0310 16 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL VPX P1 Connector PCle Table 2 5 VPX P1 Connector The VPX 3U P1 connector contains the high speed PCle signals The VPX VLX is compliant to VITA 46 4 The board is jumper selectable to select the bottom 4 lanes LO L3 The upper four are fully discounted from the backplane via a switch so they will not interfere with any other cards using those signals on the backplane water rowe Row Rowe RowD Rowe rows rowa Note BOLD ITALIC signals are NOT USED by this carrier board Acromag Inc Tel 248 295 0310 17 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL VPX Backplane P2 Connector Mapping to Rear Site I O Connector J4 Table 2 6 VPX P2 Connector The VPX P2 connector contains all of the Rear I O routing from the PMC J4 connector This connector consists of 16 differential wafers with 7 signals each This pin out is compliant with VITA 46 9 P2w1 P64s Note that the backplane connected to the VPX VLX should be VITA 46 9 P2w1 P64s compliant to avoid any possible signal contentions Wafer RowG RowF Rowe RowD Rowc RowB Rowa GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GN
31. XM A30 high speed analog input mezzanine module is present Bits 27 and 28 are DMA acknowledgement bits and will read a logic high while the corresponding DMA channel transfer is active Bit 31 of this register when set to a logic 1 will issue a reset signal to the FPGA hardware Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 44 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Table 3 14 Software Reset and FUNCTION Status Register Mezzanine interrupt status is identified via data bits O 1 All bits labeled Not Used to 7 Read of a 1 indicates that an interrupt is 7 logic 0 wh pending for the corresponding data bit A pending will return logic O when interrupt will remain active until disabled via the read mezzanine interrupt control registers Logic 0 Logic 1 USERO Control Logie 0 Board clock PUC Default Logic 1 Not Use Mezzanine A anar e aaee Code 15 13 001 for all Acromag digital I O mezzanine boards 010 for the AXM A30 mezzanine board DACKO Status Logic high is a valid acknowledgement for DMA channel O DACK1 Status Logic high is a valid acknowledgement for DMA channel 1 The most significant bit of this register when set to a logic 1 will issue a software reset Logic 0 No Operation Logic 1 Software reset issued to Xilin
32. an be stored in this location This device also will report board temperature from a temperature sensor on the board Acromag Inc Tel 248 295 0310 59 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL LED s The VPX VLX uses three LEDs to indicate the status of PCle link training The VPXLNK VPX back plane to the system processor XMCLNK XMC link train to the XMC site will be green during active data cycles Note that each LED is labeled on the board PCIe INTERFACE LOGIC The PCle bus interface logic on this board provides a 2 5Gbps interface to the carrier CPU board per PCI Express Specification 1 1 The interface to the carrier CPU board allows complete control of all board functions PCle bus endpoint interface logic is contained within a user interface FPGA This logic includes support for PCle commands including configuration read write and memory read write In addition the PCle interface requester and or completion accesses Payload of up to 256 bytes is supported The PCle interface supports sending interrupt requests as either legacy interrupts or Message Signaled Interrupts MSI The mode is programmed using the MSI Enable bit in the Message Control Register of the MSI Capability Structure For more information on the MSI capability structure see section 6 8 of the PCI Local Base Specification v3 0 If the MSI Enable bit is set to a 1 then the core will generate MSI request If the MSI Enable bi
33. ansfer of data to FPGA port of the DP SRAM This feature must be enabled via bits 3 and 4 for Channel O 1 thresholds respectively of the FPGA Port SRAM Control Register Note that the DMA transfers do not have to be enabled for this feature to function Reading of either register will return the corresponding internal address reset value Writing this register will set the corresponding internal address reset register to the provided value Bits O to 19 of these registers are used in the VPX VLX The most significant bits are not used and will return logic O when read A system reset will cause these registers to reset to OOOOOH VPX Board Identification Code Register Read Only BAR2 8058H Acromag Inc Tel 248 295 0310 The VPX Board Identification Code register at BAR2 plus 8058H stores an ID code that can used to uniquely identify the VPX Virtex 5 card This register will read A3 hex as provided by the Acromag example design The user can change the hardware setting of this register in the programmable FPGA code This ID code can be used to properly assign software drivers to multiple VPX boards that may have the same device and vender ID in a given system Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers 51 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DDR SDRAM Control Register Read Write BAR2 805CH This read write register is used to control
34. at all of the procedures in the Preparation for Use section have been followed Also refer to the documentation of your board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Acromag s application engineers can also be contacted directly for technical assistance via email telephone or FAX through the contact information listed at the bottom of this page When needed complete repair services are also available Acromag Inc Tel 248 295 0310 65 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL 6 0 SPECIFICATIONS PHYSICAL Physical Configuration 3U VPX Board Height 3 937 inches 100 0 mm Depth 6 299 inches 160 0 mm Board Thickness 0 063 inches 1 60 mm Pitch Thickness includes all metalwork VPX VLX 0 80 inches 20 32 mm VPX VLX CC 0 85 inches 21 59 mm Unit Weight Model VPX VLX 9 22802 0 2616 Kg Model VPX VLX CC 11 69 0z 0 3316 Kg POWER REQUIREMENTS Power will vary dependent on 3 3 VDC 5 Typical 1600 mA Max 3900 mA the application 5 0 VDC 5 Typical 2800 mA Max 5200 mA 5V Maximum rise time of 100m 12 VDC 45 Up to 1A for XMC module seconds 12 VDC 5 Up to 1A for XMC module
35. burst read or write to DDR SDRAM The DDR SDRAM is set for a burst length of four and will require the DDR SDRAM Write register be preloaded with four 32 bit data values prior to issuing the write operation The DDR SDRAM Read register will contain four 32 bit data values following the issue of a read operation For either a read or write the DDR SDRAM Address register must be written with the desired command and address location for the access FUNCTION Start DDR SDRAM write operation The DDR SDRAM Write and Mask registers must first be written with the desired data that are to be burst out to the DDR SDRAM In addition the DDR SDRAM Address register must be written with the write address and command prior to setting this bit Logic o No operation performed Write Transfer Performed Start DDR SDRAM read operation The Address Register must be written with the start address location and the read command prior to setting this bit The DDR SDRAM Read registers are filled with 222 WIDE Ale FO DOR Wie data FFO aos a Table 3 19 DDR SDRAM Control Register 1 All bits labeled Not Used will return logic O when read four data words that are read in a burst from the DDR SDRAM Logic 0 No operation performed Logic 1 Logic 1 Read Transfer Performed Not Not Used ee WDF_Almost_Full DDR Write data FIFO is almost full when this bit is Logic 1 Software can monitor to avoid over filli
36. bus FPGA 003B System Monitor Status Control Register 0038 PCle bus FPGA System Monitor Address Register 003C Not Used Not Used 0040 7FFF Not Used 7FFC Acromag Inc Tel 248 295 0310 35 WWW acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Table 3 8 Example Design BAR2 D31 D16 D15 DOO BAR2 BAR2 Memory Map Addr Addr 1 The board will return O for 8003 Software Reset and Status Register 8000 all addresses that are Not 8007 Mezzanine Module 8004 Used y Memory Space 18 802B 8028 802F Rear I O Connector Read Register 802C 8033 Rear I O Connector Write Register 8030 8037 DMA Control Register 8034 803B FPGA Port SRAM Register 8038 entrain FPGA Port SRAM Register 803C ee IE ameero 8053 Address Reset Register 0 DP SRAM 8050 805B XMC Board Identification Code Dll A3 for Acromag Example Design aost DDR SDRAM Control Register 805c DDR SDRAM Read Registers DO D1 D2 D3 DDR SDRAM Write Registers DO D1 D2 D3 DDR SDRAM Mask Register 808B Reprogrammable FPGA 8088 AAA s 808F Reprogrammable FPGA 808C BN smsem manor nares resser 8093 Additional Mezzanine Module Space 8100 gt 8137 8090 y y 3FFFFF Otherwise Not Used 3FFFFC Acromag Inc Tel 248 295 0310 36 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL This memory map reflects byte accesses using the Little Endian byte ordering format Little Endian u
37. byte addresses to store the low order byte Little Endian means that the least significant byte is stored at the lowest memory address and the most significant byte is stored at the highest memory address The Intel x86 family of microprocessors uses Little Endian byte ordering Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Big endian means that the most significant Acromag Inc Tel 248 295 0310 25 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL byte is stored at the lowest memory address and the least significant byte is stored at the highest memory address Layout of a 64 bit long int High address CONFIGURATION REGISTERS The PCle specification requires software driven initialization and configuration via the Configuration Address space This board provides 512 bytes of configuration registers for this purpose It contains the configuration registers shown in Table 3 1 to facilitate Plug and Play compatibility The Configuration Registers are accessed via the Configuration Address and Data Ports The most important Configuration Registers are the Base Address Registers and the Interrupt Line Register which must be read to determine the base address assigned to the board and the interrupt request line that goes active on a board interrupt request Table 3 1 Configuration
38. cccccccccncnnnnnnnnnncccccnncnanonononononnnnnanananonononnnnnnnnnnononnnnn 40 Flash Address 7 gt 0 Read Write BAR2 2CH ooccccnncccccnnnnnnnnonanancncnonococononnnnnnononanananoconononnnnnnnnnnnononanos 40 Flash Address 15 gt 8 Read Write BAR2 30H occcccccccncnnncnnnnnnnncncnononoconononononononananccononocnnnnononnnnnnnnnnns 40 Flash Address 23 gt 16 Read Write BAR2 34 H ooocccccncnnnnnnnnnnnncncncnnncnnnnnonononononananarononocononononononnnnnans 40 SYSTEM MONITOR REGISTERS U5 PCle DUusS scscccsvsvscscscscccccccccccecsscscscscececccccccccscsesececs 41 System Monitor Status Control Register Read Write BAR2 38H ccccccccccsssssseeeeseeeeeseeeeeeeeeeeess 43 Acromag Inc Tel 248 295 0310 2 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL System Monitor Address Register Write Only BAR2 3CH ccccccccsecccceeeseeceeeeeecceseeeeeecesseeeeeeeees 43 BARZ U7 FPGA REGISTER Saa iia 44 Software Reset and Status Register Read Write BAR2 8000H ccccccccccccssseeeeeeseeeeeeseeeeeeeeeeess 44 Rear I O Connector Read Register Read Only BAR2 802CH oocccccnccccncnnnnnnnononanancnccnnccnnananonononononono 45 Rear I O Connector Write Register Read Write BAR2 8030H uu eeeceeeeeeeeeeeeeeeeeeeeeeeeeeees 46 DMA Control Register Read Write BAR2 8034H cccesssesceccccccccseseeseeeeeeeeseceeeeeeessseseeesuu
39. com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL BARO MEMORY MAP Note that any registers bits not CET Interrupt Control Status mentioned will remain at the default value logic low CONE DMA Status Abort Register CONE Global Interrupt Enable Bit 31 100H DMA Channel O System Address LSB 104H DMA Channel O System Address MSB 108H DMA Channel O Transfer Size in bytes 10CH DMA Channel 0 Command 110H DMA Channel 0 XMC Board Starting a aH 0 DMA DMA Channel 0 Start DMA Transfer Bit DMA Channel 0 Start DMA Transfer Bit Start DMA Transfer Bit Fa fem ooo C 134H DMA Channel 1 Start DMA Transfer Bit The BARO registers are implemented in the PCle bus interface chip rather than the user programmable FPGA As such the user cannot change the logic functions implemented in BARO These are read write registers that are software controlled and provide interrupt control status and DMA control status The Interrupt Control Status is at BARO base address plus OOH offset The DMA registers are at BARO base address plus offset 100H to 134H These registers control the transfer direction size system address and XMC addresses for DMA channel 0 and channel 1 Acromag Inc Tel 248 295 0310 28 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL The Dual Port SRAM control registers at BAR2 must also be used to set up a DMA Demand Mode transfer The Demand mode transfer is initiated by driving signals DREQO
40. d is a PCI Express Base Specification Revision 1 1 compliant PCle bus board The PCle bus is defined to address three distinct address spaces I O memory and configuration space This board can be accessed via the PCle bus memory and configuration spaces The card s configuration registers are initialized by system software at power up to configure the card The board is a Plug and Play PCle card As a Plug and Play card the board s base addresses are not selected via jumpers but are assigned by system software upon power up via the configuration registers A PCle bus configuration access is used to read write the PCle card s configuration registers When the computer is first powered up the computer s system configuration software scans the PCle bus to determine what PCle devices are present The software also determines the configuration requirements of the PCle card The system software accesses the configuration registers to determine how many blocks of memory space the module requires It then programs the board s configuration registers with the unique memory base address Since this board is relocatable and not fixed in address space its device driver must use the mapping information stored in the board s Configuration Space registers to determine where the board is mapped in memory space The memory maps in this chapter reflect byte accesses using the Little Endian byte ordering format Little Endian uses even
41. d to identify the exact source of the Programmable Virtex 5 FPGA interrupt Bits 16 to 18 of this register are used to enable or disable interrupts from specific functions This Interrupt register must have bits 16 and 17 set to logic high in order for DMA interrupts to occur on DMA channels O and 1 respectively Bit 18 must be set to logic high to enable interrupts from U7 the programmable FPGA The mezzanine board interrupt enable bits must also be set if interrupts are to originate from the mezzanine board which are passed through the programmable FPGA to this register s pending status bits DMA Status Abort Register Read Write BARO 04H This DMA Status register at BARO base address plus O4H is used to identify a DMA transfer complete status and to issue a DMA channel abort The DMA complete status bit 0 or 1 will remain logic high until cleared by writing logic high back to the same bit The start of anew DMA transfer hardware initiated will also clear a set Transfer Complete bit The DMA abort bits 8 and 9 corresponding to channels O and 1 respectively when set to logic high will abort the current DMA transfer If asserted and the channel still has outstanding requests all requests are handled before the transfer is aborted otherwise the transfer is immediately aborted If asserted and the current transfer is a Completion than a Completion with Completion Abort status is sent and the DMA transfer is stopped This regis
42. d to re enable the device for reading array data if DQ5 goes high DQ5 will go high during a Flash Start Flash Status 2 Read Only BAR2 10H This read only register is used to read the ready or busy status of the flash chip The Flash Status 2 register is at base address plus 10H The system must first verify that that Flash Chip is not busy before executing a new Flash command The Flash Chip is busy if bit 7 of this register is set to logic 1 The Flash will always be busy while bit O of the Configuration Control register is set to logic 0 Table 3 12 Flash Status 2 __Bit s __ FUNCTION Not Used bits are read as logic 0 Busy Ready Set bit 0 of the Configuration Control Register 7 register to logic 1 before monitoring this busy bit O Flash Chip is Ready Flash Chip is Busy Flash Read Read Only BAR2 14H A Flash Read command is executed by reading this register at base address plus 14H Prior to issue of a Flash Read the Flash Address registers must be set with the desired address to be read See the Flash Address registers at Acromag Inc Tel 248 295 0310 38 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL base address plus 2CH 30H and 34H The system must issue the Flash Reset command to re enable the device for reading array data if DQ5 goes high DQ5 can go high during a Flash Start Write Flash Erase Chip or Flash Erase Sector operation DQ
43. ed in 32 bit address space then bits 63 32 must be set to 0 descriptor is stored in DMA able system memory These are not BARO registers Page Address If a page is located in 64 bit address space 63 32 then the full 64 bit address must be initialized Page Size The size of the memory page in units of 31 0 bytes and a multiple of 8 bytes Next Descriptor The address of the next page descriptor which must be aligned on a 4 byte aia of boundary bits 1 0 must be 00 Setting bit O to logic 1 indicates that the Next Descriptor current descriptor is the last descriptor in 10H 63 32 l the chain DMA VPX Board Starting Address Registers Read Write BARO 110H and 130H The DMA VPX Board Starting Address register specifies the physical address of the board s Dual Port SRAM memory where data will be read written Data bits from 22 to 2 of this register are used to address the SRAM Data bit 2 selects the low 32 bit SRAM U4 when logic low and selects the upper 32 bit SRAM U19 when logic high Data bits from 22 to 3 correspond to SRAM address lines from 19 to O The DMA VPX Board Starting Address register at BARO base address plus 110H 130H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit data transfers Start DMA Transfer Write Only BARO 114H and 134H The Start DMA Transfer register is used to software start a DMA transfer Setting b
44. eeeensssns 47 FPGA SRAM Data Register Read Write BAR2 8038H and 803CH ccccccccnnnnnnnnccccccnccnnnnnnnnnnonononnnos 47 FPGA Port SRAM Control Register Read Write BAR2 8040H cccccccccccccccnnnnnnnncncccnncncnananonononononanos 47 FPGA Port SRAM Internal Address Register Read Write BAR2 8044H ooooonnnnnccccncccnnnnnnnnnnnnnnonans 49 FPGA Port SRAM DMA Channel 0 1 Threshold Registers Read Write BAR2 8048H 804CH 50 FPGA Port SRAM Address Reset Registers 0 1 Read Write BAR2 8050H 8054H eens 51 VPX Board Identification Code Register Read Only BAR2 8058H ccccccssssseeceeeeeseecesseeeeeeeseeees 51 DDR SDRAM Control Register Read Write BAR2 805CH ooonnnnnncccncccncnnnonnnonnnnnananaconoconanannnononononanos 52 DDR SDRAM Address Register Read Write BAR2 8060H oooonccccccncccccnnncnnnnnnonananacccnncnnnnnnnnnnonononanos 53 DDR SDRAM Read Registers Read Only BAR2 8064H to 8070H ooccccccnnnnccnncnnnaccnnnnnnnaconnnonaronononos 54 DDR SDRAM Write Registers Read Write BAR2 8074H to 8080H cccccccccncnnnnnncncccccncccnananonanonononanos 55 DDR SDRAM Mask Register Read Write BAR2 8084H ccccccccccccccsseeeesseeeeeeeeeeeceesssseeeeeseeeeeeensess 56 System Monitor Status Control Register Read Write BAR2 8088H ooocccccccccccnnnnnnnnnnnnananananccnnnns 57 System Monitor Status Control Regist
45. er Read Write BAR2 8088H Error Bookmark not defined System Monitor Address Register Write Only BAR2 808CH oocccccccnccccnccnnnccnnnnnnaconcnononoconnnonanonoss 57 DUAL FORT MEMO Mirta 58 BARG MEMORY MAP Scsi aaa 58 Static RAM Memory Read Write BAR4 000000H to 7FFFFFH ccccccccccccccsssseeseseeeeeseeeeeeeeeeeeess 58 4 0 THEORY OF OPERATION costniasi ico Operation ofthe VP XViD aa 59 2C BUS anad Temperature SENSOR sscesssves cee ven a 59 CR a A N ass eactia AE naw asusianoe dana E A aly AE r 60 PCIe INTER FACE LOGIC atada 60 SYNCHRONOUS DualsPOrE SRA Micra nai 60 DORZ SDRAM a 61 Local BUS MS tada 62 Local Bus CLOCK CONTROL aa 63 D0 SER VICE ANDREPATR oo ic OO Service and Repair Assistance ainia 65 Preliminary Service Procedure sesessesessesessscecescecosoeceesecssoecesoecescecesoecesoecessscecesoesssoesesseoe 65 Where to Get He lD iniciada ai 65 Acromag Inc Tel 248 295 0310 3 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL 6 0 Se ECIEIC AMON Sinai niaio 66 A A e e 66 POWER REQUIREMENTS aia 66 ENVIRONMENTAL e e o o ue atuaa saat 66 MP SPCC Col MN a a aa ics aasedieeucnea E ees 68 EPGAUV PXAV LXG5 sois 68 FPGA IN PHAN LX TIO a tato E 68 FPGA VPX VEX IS Satan 68 READ GE eas 69 PRONTI 2 epee a 69 WET DIS AL UII CF aren o o 69 Double Data Rate 2 SDRAM naaa 69 Dual Port SRAM id 70 A sates Gach tesa ie tan caren nate ta cquee tales AE E E E A
46. er These signals are not accessible via a register but can be used in custom firmware The DMA Status Abort register at BARO plus 04H register bits O and 1 can be used to identify DMA transfer complete status FPGA SRAM Data Register Read Write BAR2 8038H and 803CH The FPGA SRAM Data Read Register is provided to access the SRAM port that links directly to the user programmable Virtex 5 FPGA Reading or writing BAR2 8038H accesses the SRAM least significant data lines 31 to O Reading or writing BAR2 803CH accesses the most significant SRAM data lines 63 to 32 Reading or writing these registers is only possible using 32 bit transfers The address for the SRAM read or write is initialized by the Dual Port SRAM Internal Address register at BAR2 8044H With each additional read or write to BAR2 803CH the address is automatically incremented Writing the SRAM would proceed by first setting the Address register at BAR2 8044H Next the least significant 32 bit data word is written to BAR2 8038H Finally after the most significant 32 bit data word is written at BAR2 803CH the address is automatically incremented FPGA Port SRAM Control Register Read Write BAR2 8040H This read write register is used to control the Dual Port SRAM including enabling write automatic DMA transfer and automatic address reset on DMA thresholds The default power up state of this register is logic low A reset will set all bits in this regis
47. f Linux libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O cards and CompactPCI I O cards The software supports X86 CPUs only and is implemented as library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards The following two whitepapers related to VPX are available for download on Acromag s website or by contacting your sales representative e Introduction to VPX VITA 46 48 and 65 e Will Acromag s VPX4810 work in my system 2 0 PREPARATION FOR USE Unpacking and Inspecting Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened Ifthe carrier s agent is absent when the carton is opened and the Acromag Inc Tel 248 295 0310 8 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG WARN ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS I N G This board utilizes static sensitive components and should only be handled at a static safe workstation Card Cage Considerations Backplane contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to
48. he VLX modules are intended for users fluent in the use of Xilinx FPGA design tools 7 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL BOARD DLL CONTROL SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 2000 XP Vista 7 applications accessing Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCI I O Cards This software Model PCISW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLs that are compatible with a number of programming environments including Visual C Visual Basic NET and others The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers BOARD VxWORKS SOFTWARE BOARD Linux SOFTWARE References Acromag provides a software product sold separately consisting of board VxWorks software This software Model PMCSW API VXW is composed of VxWorks real time operating system libraries for all Acromag PMC XMC and VPX I O board products PCI and PCle I O Cards and CompactPCI I O Cards The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI and PCle boards Acromag provides a software product consisting of board Linux software This software Model PMCSW API LNX is composed o
49. hus the address will not need to be set prior to issuing the next Flash Start Write The first byte of the configuration file should be written to address O of the Flash Chip The Flash Start Write operation will take 9u seconds to complete iii Issue a Flash Start Write command to the Flash Chip by writing 41 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL logic 1 to bit O of base address plus 1CH iv Verify that the Flash Chip is not busy by reading bit 7 as logic O of the Flash Status 2 register at base address plus 10H before going back to step i to write the next byte 8 Enable auto configuration by setting bit O Stop Configuration of the Configuration Control register to logic low 9 Verify that the configuration is complete by reading DONE bit 0 of Configuration Status Register as logic high 10 Thereafter at power up the configuration file will automatically be loaded into the FPGA Direct PCIe bus to Xilinx Configuration Configuration of the Xilinx FPGA can be implemented directly from the PCle bus The following is the general procedure for re configuration of the Xilinx FPGA via the PCle bus 1 Disable auto configuration by setting bit O Stop Configuration of the Configuration Control register to logic high 2 Clear the Xilinx FPGA of its previous configuration by setting the Configuration Control register bit 2 to logic high 3 Read INIT as logic high Bit 1 of Configuration Stat
50. igh for this bit to go active Write logic high to clear bit eee renege No Interrupt Pending sss Interrupt Pending aa Interrupt Pending Interrupt Pending Not ee bits are read as logic O U7 FGPA Interrupt Pending Status Bit 18 must be set to logic high for this bit to go active DMA Channel 0 Interrupt Enable QO DMA Channel 0 Interrupt Disabled DMA Channel 0 Interrupt Enabled 17 DMA Channel 1 Interrupt Enable 0 DMAChannel 1 Interrupt Disabled DMA Channel 1 Interrupt Enabled 18 U7 Programmable FPGA Interrupt Enable 0 Interrupt Disabled Interrupt Enabled 19 31 Not Used bits are read as logic O Acromag Inc Tel 248 295 0310 29 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL A board pending interrupt is identified via bit O of this register Logic high on bit 0 indicates a board pending interrupt Bit 0 indicates a pending interrupt as long as DMA Channel 0 DMA Channel 1 or U7 Programmable FPGA interrupt pending status bits 1 2 or 3 respectively remain active A DMA channel 0 pending status can be cleared released by writing logic high to bit 1 the interrupt pending status bit Likewise writing logic high to bit 2 of this register clears DMA channel 1 pending status The U7 Programmable FPGA interrupt Pending status will pass the interrupt status of U7 only when bit 18 is set to logic high The Software Reset and Status Register at BAR2 8000H can be rea
51. inating from the front AXM mezzanine module if present USERo CLOCK CONTROL Bit 8 of this register controls the USERo signal The USERo control signal is used to select between the 125MHz clock and the user defined clock PLL_CLK The user defined clock is defined in the example code of the Note USERo selects the Local FPGA and output on signal PLL_CLK The Digital Clock Manager of the FPGA bus clock offers a wide range of clock management features including clock multiplication and division for generation of a user defined clock PLL_CLK A 125MHz crystal generated clock signal FPGA_CLK_PLL is input to the FPGA for use in generation of the user defined clock signal PLL_CLK The PLL_CLK can be a minimum of 62 5MHz and a maximum of 125MHz Since the PLL_CLK signal is generated and driven by the FPGA it will only be available after the FPGA is configured See the example VHDL file included in the engineering design kit and the Xilinx documentation on the Digital Clock Manager for more information The USERO signal is controlled via a bit 8 of the Software Reset and Status Register at BAR2 plus 8000H The USERO control bit 8 is by default set to a logic low to select the PLL_CLK clock as the board clock frequency Bit 8 set to logic high will select the 125MHz clock as the board clock frequency Bits 15 to 13 of this register will read 001 for all Acromag digital I O AXM DOx mezzanine modules These bits will read 010 when the A
52. inx XCSVLX110T 1FF1136 e 69 120 CLB Flip Flops e 1 120 000 Distributed RAM Bits e 296 18Kbit Block RAMs e 64 DSP Slices 6 Clock Management Tiles User Programmable U7 FPGA VPX VLX155 Xilinx XCSVLX155T 1FF1136 e 97 280 CLB Flip Flops e 1 640 000 Distributed RAM Bits e 424 18Kbit Block RAMs e 128 DSP Slices 6 Clock Management Tiles Acromag Inc Tel 248 295 0310 68 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL REAR I O The rear I O P4 PMC connector connects directly to banks 1 4 and 21 of the FPGA The bank 1 4 and 21 Vcco pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards Table 6 39 of the Virtex 5 User Guide available from Xilinx lists all the supported lOStandards available The example design defines the rear I O with 2 5 volt LVDS e Maximum Recommended Clock Rate 150MHz 6 7ns clock period e Veco Supply Voltage ooeec y VOIt e VOH Output High Voltage o 1 602 volt e VOL Output Low Voltage eee eens 0 898 volt e VODIFF Differential Output Voltage 350m volt typical e VOCM Output Common Mode Voltage 1 25 volt typical e VIDIFF Differential Input Voltage 100m volt minimum e VICM Input Common Mode Voltage 0 3 volt min 1 2 volt typical 2 2 volt max FRONT I O If optional AXM mezzanine modules are used air cooled VPX VLX models only refer to the AXM user s manual for front I O specifications
53. irectional signals used for both read and write data transfers ADS_n the address data strobe signal will pulse low for one local bus clock cycle at the start of a new read or write access The ADS_n signal is driven by the PCle bus interface chip U5 Readyn must be driven low on read or write cycle by the programmable FPGA U7 and held low until Rdyack_n is driven low by the PCle bus interface chip U5 This is shown on the read and write diagrams that follow Rdyack_n is driven low by the PCle bus FPGA U5 to signify the end of the read or write cycle The LW_R_n signal when logic high indicates a write transfer in which data is moving from the PCle bus to the reprogrammable FPGA U7 This signal when logic low indicates a read transfer in which data is moving from the reprogrammable FPGA U7 to the PCle bus For a read cycle the LD data signals should be driven active prior to driving Readyn active LD and Readyn should be held active until Rdyack_n is detected active The LA LBEO_n LBE1_n LBE2_n LBE3_n LD LW_R_n signals are guaranteed to setup at least 2 LCLK FPGA_CLK clock cycles before signal ADS_n goes active These signals are also guaranteed to be held active a minimum of 2 clock cycles after Readyn goes active Also Rdyack_n will not pulse active sooner than 2 LCLK FPGA_CLK clock cycles after Readyn goes active Both LCLK and FPGA_CLK are driven by the same zero delay Cypress clock driver Signal ADS_n
54. is driven by an OLogic register using the LCK at the bus interface FPGA ADS_nis received at the programmable FPGA using FPGA_CLK at an lLogic register This interface is considered synchronous to the LCLK FPGA_CLK by Acromag Acromag Inc Tel 248 295 0310 62 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Local Bus CLOCK CONTROL Clk the local bus clock as seen in the following timing diagrams can be one of two sources By default clk is a Digital Clock Manager DCM generated clock frequency Clk can also be selected directly from the board 125MHz frequency The Local bus clk signal is controlled by USERo The board clock is routed to the Dual Port SRAM and user programmable FPGA U7 using a low skew clock driver Cypress CY23EP05 The on board 125MHz crystal oscillator is input to the user programmable FPGA via signal FPGA_CLK_PLL After the user programmable FPGA U7 is configured an FPGA DCM generated clock signal PLL_CLK is selected as the board clock the default condition By setting bit 8 of the Software Reset and Status register at BAR2 plus 8000H to a logic high the 125MHz clock may be selected as the board clock By setting bit 8 to a logic low the PLL_CLK becomes the board clock frequency The default state of bit 8 is logic low Acromag Inc Tel 248 295 0310 63 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Local Bus Write Cycle Diagram ck LIL UUUUUUUUUUUUUUUUU
55. it 0 to logic 1 will start the corresponding channel s DMA transfer The Start DMA Transfer register at BARO base address plus 114H 134H is used to start the DMA channel 0 1 transfer Writing to these registers is possible via 32 bit data transfers Acromag Inc Tel 248 295 0310 34 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 BAR2 MEMORY MAP USER S MANUAL The memory space address map used to program the FPGA and flash device is shown in Table 3 8 Note that the base address for the board BAR2 in memory space must be added to the addresses shown to properly access these registers Register accesses as 32 16 and 8 bit transfers in memory space are permitted All addresses in BAR2 from O to 7FFF hex are fixed and cannot be changed by the user via the programmable Virtex 5 FPGA Table 3 8 BARZ D31 DOS DO7 Doo RARZ BAR2 Memory Map z Not Used Configuration Status Register 0000 1 The board will return O for md Configuration Control all addresses that are Not 0007 Register 0004 Used 000B 0017 001B 001F Not Used Not Used Not Used Not Used Not Used Not Used Configuration Data Py Flash Status 1 Register 1 i 0013 Flash Status 2 Register 0010 Flash Read Flash Reset Flash Start Write 0008 000C 0014 0018 001C Flash Erase Sector 1 002B Not Used Not Used Flash Data Register 0028 Flash Address 7 gt 0 002C 1 PCle
56. iting this register is possible via 32 bit data transfers The 10 bits digitized and output from the ADC can be converted to temperature by using the following equation Temperatui PC td 273 15 1024 The 10 bits digitized and output from the ADC can be converted to voltage by using the following equation DCcode A A SupplyVolagevolts 3V pplyVolageavolts TT System Monitor Address Register Write Only BAR2 3CH This write only register is used to set the system monitor address register with a valid address for the System Monitor internal status or control registers Valid addresses are given in the following table Additional addresses can be found in the Xilinx System Monitor document UG192 available from Xilinx Writing this register is possible via 32 bit data transfers The address value written to this register can be read on bits 22 to 16 of the System Monitor Status Control register at BAR2 plus 38H IS Eon Register Map Minimum Temperature Acromag Inc Tel 248 295 0310 43 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL BAR2 U7 FPGA REGISTERS Software Reset and Status Register Read Write BAR2 8000H This read write register is used to Software reset the board monitor the Status of board interrupts and select the on board active clock as shown in Table 3 14 Bits O to 7 of this register are used to monitor the interrupt pending status of interrupts orig
57. ive are shown 23 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL 3 0 PROGRAMMING INFORMATION This section provides the specific information necessary to program and operate the board GETTING STARTED Acromag Inc Tel 248 295 0310 The VPX VLX board is shipped with the user programmable Xilinx FPGA code stored in flash memory Upon power up the VPX VLX will automatically configure the FPGA with the example design code stored in flash As a first step become familiar with the VPX VLX with the example code supplied by Acromag The board will perform all the functions of the example design as described in this manual The Example Design Memory Map section gives a description of the I O operations performed by the example design It will allow testing of digital I O interrupts read write of dual port SRAM and testing of both DMA channels It is strongly recommended that you become familiar with the board features by using the example design as provided by Acromag CAUTION Do not attempt to reconfigure the flash memory until after you have tested and become familiar with the VPX VLX as provided in the example design After you are familiar with the VPX VLX and have tested it using the example design you can move on to step 2 Here you will modify the example design VHDL code slightly It is recommended that you test this modified example design using the reconfiguration direct method It is not recommended
58. lects the bank address BA1 and BAO while the value on A9 to AO selects the starting column location Invalid combinations Functionality of the controller is unpredictable for these commands Acromag Inc Tel 248 295 0310 53 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DDR SDRAM Read Registers Read Only BAR2 8064H to 8070H Table 3 21 DDR SDRAM Read Registers The four DDR SDRAM Read registers are read only and hold the last four data values read from the DDR SDRAM The DDR SDRAM is set for a burst of four for the purposes of this design example A DDR SDRAM read is implemented by executing the following steps a Set the DDR SDRAM Address register with the starting address location and read command Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A25 A24 A23 A22 A10 A9 AO b Set the start read bit of the DDR SDRAM Control register at base address 805C Set bit 1 of the SDRAM Control Register at 805CH to logic high The data is read from the SDRAM and moved to the SDRAM Read Registers at 8064H to 8070H Read of these registers directly after write of logic 1 to the SDRAM Control Register at 805CH can result in a read error To ensure the SDRAM data has been written into and is available in the Read register a 500ns delay after issue of the start read via the DDR SDRAM Control register may be necessary Reading these registers is possible via 32 16 or 8 bit t
59. mmand Register DMA transfers must start aligned to Double Lword boundary when performing DMA transfers The DMA Command register is used to set the priority Scatter Gather enable and to indicate the command to be used for the DMA transfer The Memory Read Burst command is used to program a read transfer The data is moved from system memory to the boards SRAM memory The Memory Write Burst command is used to program a write transfer The data moves from the board s SRAM to system memory Writing to these registers is possible via 32 bit data transfers Bitls FUNCTION 0 Not Used bit is read as logic 0 1 Not Used bit is read as logic 0 Not Used bit is read as logic 0 o Direct DMA Mode Enable Scatter Gather Mode 7to4 DMA Command Memory Read Burst Memory Write Burst Acromag Inc Tel 248 295 0310 33 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL In Scatter Gather DMA transfer mode the DMA start address is a pointer to a chained list of page descriptors Each descriptor contains the address and size of a data block page as well as the next descriptor block The following table describes the 20 byte block Scatter Gather descriptor Table 3 7 Scatter Gather ore Fed Beton Descriptor Block This block The Start address of memory page that Page Address must be aligned on an 8 byte boundary 31 3 bits2 0 must be 000 If a page is locat
60. ng the write data FIFO AF_Almost_Full DDR Address FIFO is almost full when this bit is Logic 1 Software can monitor to avoid over filling the DDR Address FIFO Acromag Inc Tel 248 295 0310 52 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DDR SDRAM Address Register Read Write BAR2 8060H This read write register is used to set the DDR SDRAM column address row address bank chip select and command This register must be written prior to initiating a DDR SDRAM read or write burst transfer via bits O or 1 of the DDR SDRAM Control register ES DDR SDRAM Column address is written to these bits A A9 AO Table 3 20 DDR SDRAM Address Command Register 1 All bits labeled Not Used column address is required when a read or write command will return logic 0 when is present on bits 29 to 31 There are 1024 unique columns read The DDR SDRAM Row address is written to these bits There A22 A10 are 8192 unique rows ADA A93 The DDR SDRAM Bank address BA1 BAO is written to these f bits The DDR SDRAM has four unique banks DDR SDRAM Command Write The write burst access is initiated to the row Logic given on bits A10 to A22 The value on A24 and 000 A23 selects the bank address BA1 and BAO while the value on A9 to AO selects the starting column location Read A31 A29 The read burst access is initiated to the row given on bits A10 to A22 The value on A24 and A23 se
61. odel adequate air circulation of at least 100 LFM must be provided to prevent a temperature rise above the maximum operating temperature IMPORTANT If a VPX VLX CC model is not installed in a conduction cooled chassis air circulation of at least 200 LFM must be provided to prevent a temperature rise above the maximum operating temperature This board is designed to work with a Backplane profile of BKP3 DISO6 15 2 7 n Failure to use a compatible backplane could result in damage to Acromag Inc Tel 248 295 0310 9 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL this product or others in the chassis For more information on backplane compatibility please refer to the Acromag VPX4810 Compatibility Whitepaper WARNING THE VPX VLX CAN ONLY BE USED ON A 3U BACKPLANE PLUGGING THIS MODULE INTO A 6U BACKPLANE WILL RESULT IN DAMAGE TO THIS BOARD DUE INCOMPATIBLE POWER SUPPLY CONNECTIONS Default Hardware Configuration for the VPX VLX The board may be configured differently depending on the application When the board is shipped from the factory it is configured as follows e The onboard flash memory device is read write enabled e The default configuration of the programmable software control register bits at power up are described in section 3 The control registers must be programmed to the desired configuration before starting data input or output operation Front Panel Field I O Connector The front panel c
62. omatic reset is enabled an infinite loop will be created within the internal logic of the FPGA Logic 1 Enable Auto DMA Request Channel 0 Logic 1 Enable Auto DMA Request Channel 1 If enabled via this bit the Internal Address Counter will be loaded with the value in Address Reset Register O when the counter is equal to the DMA Channel 0 Threshold Register See the Address Reset Register description for further details DMA does not have to be enabled to use this feature Logic O Disable Add Reset on DMA Ch 0 Threshold Logic 1 Enable Add Reset on DMA Ch O Threshold If enabled via this bit the Internal Address Counter will be loaded with the value in Address Reset Register 1 when the counter is equal to the DMA Channel 1 Threshold Register See the Address Reset Register description for further details DMA does not have to be enabled to use this feature Logic 0 Disable Add Reset on DMA Ch 1 Threshold Logic 1 Enable Add Reset on DMA Ch 1 Threshold If enabled via this bit a DMA Channel 1 request will be issued when the internal address counter is equal to the DMA Channel 1 Threshold Register This will have the same effect as writing a 1 to bit 1 of the DMA Control Register at BAR2 2 plus 8034H Logic O Disable Auto DMA Request Channel 1 Acromag Inc Tel 248 295 0310 48 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL FPGA Port SRAM Internal Addre
63. onnector provides the field I O interface connections via optional AXM mezzanine I O modules purchased separately Rear P4 Field I O Connector The PMC XMC rear I O P4 connector connects directly to the user programmable FPGA The VCCO pins are powered by 2 5 volts and thus will support the 2 5 volt lOStandards The IOSTANDARD attribute can be set in the user constraints file UCF For example rear I O can be defined for LVCMOS25 low voltage CMOS The example design defines the rear I O to LVDS_25 Low Voltage Differential Signaling in the user constraints file The 2 5 volt lOStandards available are listed in table 6 39 of the Virtex 5 User Guide available from Xilinx The example design defines the rear I O connector with 32 LVDS I O pairs The LVDS pairs are arranged in the same row in Table 2 1 For example RIOO_P and RIOO_N form a signal pair The P identifies the Positive input while the N identifies the Negative input Acromag Inc Tel 248 295 0310 10 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Table 2 1 Board Rear Field I O Pin Connections Ch Pin Pin The example design implements ROOP L A ROON _ _________ 2 5volt LVDS I O to the rear 1 connector Signal pairs are 2 routed to pins 1 3 2 4 etc 3 RO3 P 6 RIB NCS RO4P lt S SRI N Y o UI RO6 P 13 RO6N_ _ _ _ ROSP 18 ROON 0 1 RIO23 P 46 RIOZ N RIO24 P 49 RIO4N_ S 31 This
64. p2 e3 10 Rearin4 10 P2 83 ll da Rearin419 p2D5 20 Rearin4 20 P2 A5 za Rearin4 21 P2 F6 22 Rearin4 22 P2 C6 za Rearjn4 23 P2 E6 24 Rearin4 24 P2 86 ll as Rearjn4 25 P2 E7 26 Rearin4 26 P2 87 27 Rearina 27 P207 28 Rearin4 28 P2 A7 za Rearima 29 P2F8 30 Rearin4 30 P2 C8 ll 31 Rearjn4 31 P2 E8 32 Rearin4 32 P2 88 la Rear ind 33 p2 e9 34 Rearins 34 P289 Acromag Inc Tel 248 295 0310 13 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL as Rearjn4 35 P2 D9 36 Rearin4 36 P2 A9 laz Rearina 37 P2 F10 38 Rearin4 38 P2 C10 ll 39 RearJn4 39 p2 e10 40 Rear Jn4 40 P2 B10 a Rearjn4 41 P2 E11 42 Rearinq 42 P2 B11 43 Rearsnd a3 p2 p11_ 44 Rearin4 44 P2 A11 ll 45 Rearjn4 45 P2 F12 46 Rearinq 46 P2 C12 laz Rearina a7 P2 12 48 Rearinq 48 P2 B12 49 Rearjn4 49 P2 E13 50 Rearinq 50 P2 B13 51 Rearjn4 51 P2 D13 52 Rearin4 52 P2 A13 53 RearJn4 53 P2 F14 54 Rear Jn4 54 P2 C14 ll ss Rearjn4 55 P2 E14 56 Rear Jn4 56 P2 B14 ll sz RearJn4 57 P2 E15 58 Rear Jn4 58 P2 B15 59 Rear Jn4 59 P2 D15 60 Rearin4 S0 P2 A15 61 Rearjn4 61 P2 F16 62 RearJn4 62 P2 C16 63 Rear Jn4 63 P2 E16 64 Rearjn4 64 P2 B16 XMC Connector Pinout XMC Connector P5 Table 2 3 XMC Connector P5 This connector contains eight PCle lanes as well as all XMC power and control signals Note that V
65. pace Required BARO 64 bit Base Address Register O for access to configuration registers 4M Memory Space Required BAR2 64 bit Base Address Register 2 for access to the user programmable FPGA U7 8M Memory Space Required BAR4 64 bit Base Address Register 1 for access to Dual Port SRAM Interrupts Source of interrupt can be from the U7 programmable FPGA or DMA Channels Supports sending interrupt requests as either legacy interrupts or Message Signaled Interrupts MSI MSI capability is supported as an extended capability in the Type O PCI configuration space Acromag Inc Tel 248 295 0310 70 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Certificate of Volatility Certificate of Volatility Acromag Model Manufacturer VPX VLX85 E Acromag Inc VPX VLX110 E 30765 Wixom Rd VPX VLX155 E Wixom MI 48393 Volatile Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed m Yes o No Type SRAM SDRAM etc Size User Modifiable Function Process to Sanitize SRAM 1Meg x 72 m Yes Data storage for Power Down o No FPGA Type SRAM SDRAM etc Size User Modifiable Function Process to Sanitize FPGA based RAM Variable up m Yes Data storage for Power Down to 1 28Mbyte o No FPGA Type SRAM SDRAM etc Size User Modifiable Function Process to Sanitize SDRAM 32M x 32 m Yes Data storage for Power Down o No FPGA Non Vola
66. r Address Register at BAR2 plus 808CH For example the address of the System Monitor Status register that is to be accessed is first set via the System Monitor Address register at BAR2 plus 808CH Next this register at BAR2 plus 8088H is read Bits 22 to 16 of this register hold the address of the system monitor register that is accessed Data bits 15 to 6 of this register hold the ADC code temperature Vccint or Vccaux value Data bits 5 to O are not used Valid addresses are given in column one of Table 3 24 Reading or writing this register is possible via 32 bit data transfers The 10 bits digitized and output from the ADC can be converted to temperature by using the following equation Temperatui PC POP AA 273 15 1024 The 10 bits digitized and output from the ADC can be converted to voltage by using the following equation ADCcode 3y SupplvVolazgevolts pplyVolage amp volts ia System Monitor Address Register Write Only BAR2 808CH This write only register is used to set the system monitor address register with a valid address for the System Monitor internal status or control registers Valid addresses are given in the following table Additional addresses can be found in the Xilinx System Monitor document UG192 available from Xilinx Reading or writing this register is possible via 32 bit data transfers The address value written to this register can be read on bits 22 to 16 of the System Monito
67. r Status Control register at BAR2 plus 8088hex Table 3 24 System Monitor Register Map 00h aximum Temperature M Maximum Vccint Maximum Vccaux inimum Temperature Minimum Vccaux Acromag Inc Tel 248 295 0310 57 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DUAL PORT MEMORY A 1Meg x 64 bit Dual Port synchronous SRAM DP SRAM is provided on the VLX board One port of the SRAM connects directly to the local bus to allow for PCle access The remaining port connects directly with the user programmable FPGA This design allows for the user to maximize data throughput between the Field O s and the controlling processor There are two automatic DMA initiators available that will trigger upon a user set threshold Furthermore upon a DMA transfer the internal counter can be reset to a user specified value See DMA Registers for more information on these operations These features can be individually controlled through the SRAM Control Registers BAR4 MEMORY MAP Static RAM Memory Read Write BAR4 000000H to 7FFFFFH The Static RAM memory space is used to provide read or write access to on board SRAM memory This memory space allows access to the SRAM from the port on the PCle bus side of the SRAM The Static RAM device has a 1Meg x 64 bit capacity on the VPX VLX Reading or writing to this memory space using DMA access is also only possible via 64 bit transfers The FPGA Port SRAM Registe
68. r at BAR2 8038H and 803CH are provided for testing the SRAM port that links directly to the user programmable Virtex 5 FPGA Acromag Inc Tel 248 295 0310 58 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL 4 0 THEORY OF OPERATION This section contains information regarding the design of the board A description of the basic functionality of the circuitry used on the board is also provided Refer to the VPX VLX Block Diagram shown at the end of this manual and the block diagram just beyond the next paragraph as you review this material Operation of the VPX VLX The VPX VLX can connect to the VPX bus as a Fat Pipe PCle x4 device This is controlled by physical jumper Refer to the jumper settings section for further information The PCle bus is then routed to a switch that automatically connects via 4 lanes to the XMC module The VPX VLX rear I O is routed from the J4 connector to the VPX P2 connector PMC I O XMC f PCI X PCle to PCI X XMC Expansion Bridge Site PCle x8 XMC VPX Configuration Backplane Jumper Connector st co x x lt 2 g O O A PClex4 Low Latency E PCle Mux PCle x4 PCle Switch PCle x4 PClex4 Low Latency PCle Mux 12C Bus and Temperature sensor There is one I2C bus to access the FRU Field Replaceable Unit Information such as board module number part number and revision level c
69. ransfers DDR SDRAM Read Registers Base Addr D31 DO Base Addr 8067 DDR SDRAM Read Register DO 8064 806B DDR SDRAM Read Register D1 8068 806F DDR SDRAM Read Register D2 806C 8073 DDR SDRAM Read Register D3 8070 Acromag Inc Tel 248 295 0310 54 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DDR SDRAM Write Registers Read Write BAR2 8074H to 8080H The four DDR SDRAM Write registers hold four data values that are to be written to the DDR SDRAM The DDR SDRAM is set for a burst of four for the purposes of this design example A DDR SDRAM write is implemented by executing the following steps 1 Write the four 32 bit data values that are to be written to the DDR SDRAM to the registers at base address 8074H to 8080H DDR SDRAM Write Registers Table 3 22 DDR SDRAM Write Registers 8077 DDR SDRAM Write Register DO 807B DDR SDRAM Write Register D1 078 807F DDR SDRAM Write Register D2 807C 8083 DDR SDRAM Write Register D3 0 2 Set the DDR SDRAM Mask bits as desired at base address 8084H A value of OH would enable all bytes to be written 3 Issue the Write Command a Set the DDR SDRAM Address register with the starting address location and write command Write the following value to the SDRAM Address Register at 8060H A31 A29 A28 A25 A24 A23 A22 A10 A9 AO Set the start write bit of the DDR SDRAM Control register at base address 805C Set bit O of the SDRAM Control Register at
70. s which only support rear I O OPERATING MODEL TEMPERATURE RANGE VPX VLX85 XCSVLX85T 0 C to 70 C VPX VLX85CC XCSVLX85T 40 C to 85 C Acromag Inc Tel 248 295 0310 5 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Key Features Acromag Inc Tel 248 295 0310 PCle x4 lane VITA 46 4 Backplane Compliance The VPX VLX supports a 4 lane PCle connection to the backplane VPX VLX is compatible with Open VPX VITA 65 0 ESD Strip The VPX VLX board has been designed to provide electrostatic discharge ESD capability by using an ESD strip on the board Injector Ejector Handle The VPX VLX uses a modern injector ejector handle which pushes the board into the rack during installation and has a positive self locking mechanism so it cannot be unlocked accidentally This handle is fully IEEE 1101 10 compliant and is needed to give leverage to install and remove the board EMC Front Panel The VPX VLX uses the preferred EMC front panel per IEEE 1101 10 specification Conduction Cooled Frame The VPX VLX CC models have a custom conduction cooled assembly consisting of a conduction cooled frame thermo bars ejector injectors and wedge locks designed to thermally conduct heat away from the Conduction Cooled XMC module Reconfigurable Xilinx FPGA In system configuration of the FPGA is performed through a flash configuration device or via the PCle bus This provides a means for creating cus
71. s written to set the LVDS output channels and can also be read to verify the output channel settings Reading or writing this register is possible via 32 bit 16 bit or 8 bit data transfers Write Read Data Rear Connector Write Rear Connector Read Register Bit Output Channels Input Channels A DO Acromag Inc Tel 248 295 0310 46 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DMA Control Register Read Write BAR2 8034H The DMA Control Register is used to request a DMA Demand mode transfer The hardware signals DREQO and DREQ1 are driven active by software setting bits O or 1 of this register to request the DMA transfer The transfer must include the Static RAM Memory as either the source or the destination For software triggered DMA bit 0 is used to request a DMA channel O transfer while bit 1 is used to request a channel 1 transfer The bit must be set to logic high to request a transfer Once set the bit will remain asserted until the DMA transfer has started If both bits are set simultaneously the channel 0 DMA transfer will be implemented first followed by channel 1 In a user application a data ready condition such as a memory buffer full condition can be physically tied via logic in the FPGA to the DREQO or DREQ1 FPGA signals to cause the DMA transfer to start Signals DACKO_n and DACK1_n input to the programmable FPGA from the bus interface FPGA UD are held active during a DMA transf
72. seccseecccsescccseueeeseuecesseuseesseesesseaesessaases 16 Acromag Inc Tel 248 295 0310 1 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL VPA P COMME GLOR PE it A AAA AA EA 17 VPA PZ CONNECT O do 18 Installing and REMOVING XMC MoOMdulle ccsceccecscsccccccscsccccccscnceccccecnceccccecscececcecscesescess 19 O emer sea act me o A oT A ee ee ee eR 19 VPXVLX CC CONGUETION Cooled scien iis sere a ori 21 3 0 PROGRAMMING INFORMATION ssssssssssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 24 GETTING STARTED nia a E EES 24 PCle CONFIGURATION ADDRESS SPACE cescssccscesccccescecccccccccccccsccccescescescecccccccscsscsccs 25 CONFIGURATION REGISTERS airesin erns aa e a e 26 BARO MEMORY IMA Poca rada 28 Interrupt Control Status Register Read Write BARO OOH cccccccccccceceeeeeseeseeeeeeseeseseseeeeeeeeeeeeees 29 DMA Status Abort Register Read Write BARO O4H ccccccccccccecccsseeeeeeseeeeeeeeeeeeeeseseeseeeeeueeeeeesses 30 Global Interrupt Enable Bit 31 Read Write BARO O8H ooccccccccccnnnccnnnnnnnnanccccnnncnnnnnnnnnononononananacanonos 31 DMA System Starting Address LSB Registers Read Write BARO 100H and 120H eccess 32 DMA System Starting Address MSB Registers Read Write BARO 104H and 124H 0 eee 32 DMA Transfer Size Registers Read Write BARO 108H and 128H oooocccccncnnnnnnnnncccccncncnonanonanonononanos 33
73. ses even byte addresses to store the low order byte The Intel x86 family of microprocessors uses Little Endian byte ordering In Big Endian the lower order byte is stored at odd byte addresses Configuration Status Register Read Only BAR2 0000H This read only register reflects the status of configuration complete and Xilinx configuration clear bits This Configuration Status register is read at base address plus OH Table 3 9 Configuration Status Bit s E DONE O Xilinx FPGA is not configured 1 Xilinx FPGA configuration is complete INIT Register INIT is held low until the Xilinx is clear of its current configuration INIT transitions high when the clearing of the current Xilinx configuration is complete 2to7 Not Used bits are read as logic 0 Configuration Control Read Write BAR2 04H This read write register is used to stop Xilinx configuration and clear Xilinx configuration memory This Configuration Control register is accessed at base address plus O4H FUNCTION Stop Xilinx Configuration Enable Xilinx FPGA configuration Stop Xilinx FPGA configuration This bit should be set to logic high until after the Flash device is written with valid program data Table 3 10 Configuration Control Register Not Used bit is read as logic 0 Clear Current Xilinx Configuration Logic low has no effect Logic high resets the Xilinx configuration logic Re configura
74. ss Register Read Write BAR2 8044H The FPGA Port SRAM Internal Address Register is used to view and set the Warning To guarantee internal SRAM address The FPGA will only write using 64 bit data transfers functionality disable DP SRAM allowing for FFFFF hex unique memory accesses Reading this register will write cycles via bit 0 of the return the internal SRAM address Due to delays during data processing and DP SRAM Control Registers the PCle transfer the actual internal address may be slightly greater than the before writing to the DP SRAM address read Writing to this register will set the Internal SRAM Address to Internal Address Register the provided value Bits O to 19 of this register are used Writing logic 1 to bit 31 of this register or a system reset will cause the Internal SRAM Address to reset to 00000H the start of the SRAM memory Reading or writing to this register is possible via 32 bit data transfers only The SRAM Internal Address will automatically be incremented upon a write or read of the most significant SRAM Data Port at BAR2 803CH Table 3 17 FPGA Port SRAM FPGA Port SRAM Internal Address Register Internal Address Register D30 D20 D19 DO SRAM Internal Not oe Read as ler dire Address Reset logic 0 Acromag Inc Tel 248 295 0310 49 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL FPGA Port SRAM DMA Channel 0 1 Threshold Registers Read Write BAR2
75. t is set to 0 the core generates legacy interrupt messages The board performs DMA transfers on channels O and 1 The DMA transfers can be started via software or hardware Hardware signal DREQO driven active by the programmable FPGA will start a DMA channel 0 transfer Hardware signal DREQ1 driven active will start a DMA channel 1 transfer To identify the pins corresponding to these signals see the user constraints UCF file provided in the engineering design kit The DACKO and DACK1 signals will go active upon the start of a DMA transfer and remain active until its completion The example device driver software purchased separately can be used to exercise DMA block software and demand hardware modes of operation SYNCHRONOUS Dual Port SRAM The VPX VLX model DPSRAM size is 1M x 64 bit One port of the SRAM interfaces to the PCle bus interface chip the Xilinx Virtex 5 LX30T device U5 The other port connects directly to the programmable FPGA U7 This configuration allows for a continuous data flow from the field inputs through the FPGA to the SRAM and then to the PCle bus Both ports of the SRAM operate in Pipeline mode This allows for faster operational speed but does cause a one cycle delay during read operations The pins corresponding to the control signals address and data buses are in the user constraint UCF file provided in the engineering design kit The SRAM port connected directly to the user programmable FPGA
76. ter can be read or written via 32 bit transfers Acromag Inc Tel 248 295 0310 30 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Table 3 4 DMA Status Register Bit s FUNCTION DMA Channel 0 Transfer Complete This bit is cleared by write of logic high to this bit or start of anew DMA transfer DMA BARO REGISTERS HE AN Transfer not Complete DMA transfers must start 1 Transfer Completed aligned to Double Lword DMA Loi 1 Transfer Complete This bit is cleared by bit DMA transfers 0 Transfer not Complete Na Completed r iat Used bits are read as logic 0 DMA Channel 0 Abort on write of logic high to this bit 0 No Action Abort Channel 0 DMA transfer DMA Channel 1 Abort on write of logic high to this bit 0 No Action Abort Channel 1 DMA transfer Not Used bits are read as logic 0 16 19 DMA Channel 1 State Encoding 20 23 npe see bit descriptions given for Channels O on bits 16 19 24 31 Not Used bits are read as logic 0 Global Interrupt Enable Bit 31 Read Write BARO 08H This Global Interrupt Enable bit at BARO base address offset 08H is used to enable all board interrupts An interrupt can originate from the two DMA channels or U7 the programmable FPGA All board interrupts are enabled when bit 31 is set to logic high Likewise board interrupts are disabled with bit 31 set to logic low Bit 31 of this register can be read or written Table 3
77. ter specifies the physical address of a contiguous memory buffer where data will be read written For scatter gather DMA mode this address register points to the first element of the chained listed of page descriptors The DMA System Starting Address Register at BARO base address plus 104H 124H is used to set the DMA channel 0 1 data starting address Writing to these registers is possible via 32 bit transfers Acromag Inc Tel 248 295 0310 32 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL DMA Transfer Size Registers Read Write BARO 108H and 128H The DMA Transfer Size Register is used to set the size of the DMA transfer that moves data between system memory and the board s Dual Port SRAM The transfer size indicates the total amount of data to transfer in units of bytes The onboard static RAM for the VPX VLX has 8 Megabyte maximum Capacity As such the maximum value that should be written to this register is 8000000 hex WARNING The VPX VLX will allow for a larger value to be written than available SRAM size which will cause undesirable operations This address must be set to a DWORD boundary multiple of 4 for proper operation The DMA Transfer Size Register at BARO base address 108H 128H is used to set the DMA channel 0 1 data transfer size Writing to these registers is possible via 32 bit data transfers DMA Command Registers Read Write BARO 10CH and 12CH Table 3 6 DMA Co
78. ter to O Reading or writing to this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 47 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Table 3 16 FPGA Port SRAM Control Register This bit controls the VHDL signal SRAM_ENABLE This signal must be set to logic high to enable writes to SRAM from the FPGA The SRAM Internal Address register must also be set 1 Bits are not used and will with the start address at which the data begins filling the return logic O when read SRAM 2 All DMA transfer settings in Logic O Disable Write and Enable Read the DMA Registers at BARO Enable Write and Disable Read houl i eae r as eee ont 9 If enabled via this bit a DMA channel 0 request will be issued enabling automatic DMA l eee ae when the internal address counter is equal to the DMA Channel O Threshold Register This will have the same effect as writing a 1 to bit O of the DMA Control Register at BAR2 plus 8034H See Synchronous DP SRAM in Section 4 0 for 3 WARNING Before enabling Address Reset on DMA Thresholds bits 3 amp further details on using this feature 4 verify that the DMA Logic 0 Disable Auto DMA Request Channel 0 Ch O Threshold Register is not equal to the Address Reset Register 0 and the DMA Ch 1 Threshold Register is not equal to the Address Reset Register 1 If these registers are equal and aut
79. the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power Refer to the specifications section for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the system boards plus the installed Acromag board within the voltage tolerances specified Acromag s VPX VLX models are sold in different pitches as determined by the cooling technique The VPX VLX models are 0 8 pitch boards and the VPX VLX CC models are 0 85 pitch Verify your chassis compliance to accommodate the various board pitches In an air cooled assembly adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering In a conduction cooled assembly adequate thermal conduction must be provided to prevent a temperature rise above the maximum operating temperature IMPORTANT For a VPX VLX m
80. tile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed m Yes o No Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 16Mbyte m Yes Storage of Code for Clear Flash memory by writing o No FPGA a logic 1 to bit 0 of the Flash Erase Chip Register at BAR2 24H Type EEPROM Flash etc Size User Modifiable Function Process to Sanitize Flash 32Mbit o Yes Storage of Code for Not Applicable m No PCle bus Interface Device Type EEPROM Flash etc User Modifiable Function Process to Sanitize EEPROM o Yes IMPI FRU Not Applicable m No information Acromag Representative Name Title Email Office Phone Office Fax Joseph Primeau Dir of Sales jprimeauWacromag com 248 295 0823 248 624 9234 and Marketing Acromag Inc Tel 248 295 0310 1 www acromag com USER S MANUAL VPX VLX85 VPX VLX110 VPX VLX155 VPX VLX Block Diagram 919071 LdNYHYALNI L ANY 0 HO YNG S4JAIYd X20719 91907 TOHLNOD MIJS MOT HAXATdILINW 91907 TOHLNOO aa 49079 NOLLVENDIANOO 3OVI831NI L18 v9 z Y d4 NOHH sng 319d 30VIY3LNI 810d L0 X7 S X3LEIA pian 49010 Z VES ao e por 49079 WHS lt LOCAL BUS 49019 VOdW AG et 291907 SOV4AYALNI Bias sng 1v901 HW SZL 0y43SN 91901 8 TOYLNO9 14N9493L1NI 39V3431NI O I WVYS LYOd 1VNG dvd 119 8 X W9 L YJ 9YNYN AYOWAW NOILVYNSISANOO M9019 IWLISIG H
81. tion can begin after INIT transitions high 2 Not Used bits are read as logic O Configuration Data Write Only BAR2 08H This write only register is used to write Xilinx configuration data directly to the Xilinx FPGA from the PCle bus The Configuration Data register is accessed at base address plus 08H The entire configuration file must be Acromag Inc Tel 248 295 0310 3 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL written to the Xilinx FPGA one byte at a time Configuration complete is verified by reading DONE bit 0 of the Configuration Status Register as logic high A write to the Configuration Data register while auto configuration from Flash is active will cause the Xilinx configuration to fail Auto configuration is stopped by writing logic 1 to bit O of the Configuration Control register at base address plus O4H The Xilinx FPGA should also be cleared of its current configuration prior to loading of a new configuration file The FPGA is cleared of its current configuration by writing logic 1 to bit 2 at address plus O4H Flash Status 1 Read Only BAR2 OCH This read only register is used to read the DQ5 status of the flash chip The Flash Status 1 register is at base address plus OCH Table 3 11 Flash Status 1 FUNCTION Register Not Used bits are read as logic 1 or 0 DQS o Chip enabled for reading array data The system must issue the Flash Reset comman
82. tom user defined designs 32M x 32 DDR SDRAM A 32M x 32 bit double data rate DDR2 dynamic random access memory DRAM is directly accessed through the Xilinx user programmable FPGA Read and write accesses to the DDR2 SDRAM are burst oriented 1Meg x 64 Dual Port SRAM A 1Meg x 64 bit dual port static random access memory SRAM is included One port of the SRAM provides a direct link from the PCle bus to the SRAM memory The second port of the SRAM provides a direct link to the Xilinx user programmable FPGA Interface to Front Multifunction Modules Various mezzanine modules AXM model prefix ordered separately allow the user to select the Front I O required for their application Interface to Rear P4 Connector The Virtex 5 FPGA is directly connected to 64 pins of the rear P4 connector All 2 5volt IO standards supported by the Virtex 5 device are available The example design provides low voltage differential signaling as 32 LVDS input output signals Write Disable Jumper User configurable flash memory can be hardware write disabled by removal of an on board zero ohm surface 6 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL PCle Interface Features Software ENGINEERING DESIGN KIT Acromag Inc Tel 248 295 0310 mount resistor Example Design Provided The example VHDL design includes implementation of the Local bus interface control of digital front and rear I O and
83. us register before programming is initiated 4 Download the Configuration file directly to the Xilinx FPGA by writing to the Configuration Data register The entire configuration file must be written to the Xilinx FPGA one byte at a time to the Configuration Data register at base address plus O8H 5 Verify that the configuration is complete by reading DONE bit 0 of Configuration Status Register as logic high DONE is expected to be logic high immediately after the last byte of the configuration file is written to the Xilinx FPGA 6 At each power up the configuration file will need to be reloaded into the FPGA Acromag Inc Tel 248 295 0310 42 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL SYSTEM MONITOR REGISTERS U5 PCle bus System Monitor Status Control Register Read Write BAR2 38H This read write register will access the system monitor register at the address set in the System Monitor Address Register For example the address of the System Monitor Status register that is to be accessed is first set via the System Monitor Address register at BAR2 plus 3CH Next this register at BAR2 plus 38H is read Bits 22 to 16 of this register hold the address of the system monitor register that is accessed Data bits 15 to 6 of this register hold the ADC code temperature Vccint or Vccaux value Data bits 5 to O are not used Valid addresses are given in column one of Table 3 13 Reading or wr
84. ww acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL MT47H32M16CC Spec CY23EP05 Specification http www micron com http www cypress com 1 0 GENERAL INFORMATION Ordering Information Table 1 1 The VPX VLX boards are available in both standard and extended temperature ranges The VPX VLX series is a 3U VPX Non Intelligent product design using a 4x PCle bus connection The VPX VLX uses a PLX Technology PCle Switch Chip PEX 8624 and PLX Technology PCle to PCI Bridge Chip PEX 8114 to interface between the VPX bus and the XMC mezzanine I O module card The re configurable XMC modules use the Xilinx Virtex 5 LX FPGA Re configuration of the FPGA is possible via a direct download into the Xilinx FPGA over the PCle bus In addition on board flash memory can be loaded with FPGA configuration data for automatic Xilinx configuration on power up Flash programming is also implemented over the PCle bus Acromag provides an example design that includes an interface to the user rear I O and front I O connectors and an example memory interface controller to the 32M x 32 bit DDR SDRAM The example design also includes an interface to the SRAM with DMA hardware support The following table list the orderable models and their corresponding operating temperature range Models VPX VLX85 110 155 are air cooled front and rear I O products Models VPX VLX85 110 155CC are extended temperature conduction cooled product
85. x user 8 programmable FPGA Rear I O Connector Read Register Read Only BAR2 802CH The Rear I O Connector Read Register is used to read the LVDS input status of 16 channels This example design has 16 channels identified in Table 3 15 programmed as LVDS input only channels Table 2 1 shows each channel and its corresponding P4 connector pin assignment This Rear I O Connector Read register is a read only register and writing to this register has no effect on the LVDS input channels Reading from this register is possible via 32 bit 16 bit or 8 bit data transfers Acromag Inc Tel 248 295 0310 45 www acromag com VPX VLX85 VPX VLX110 VPX VLX155 USER S MANUAL Rear I O Connector Write Register Read Write BAR2 8030H Table 3 15 Rear I O Registers Column 1 identifies the write data bit that drives the output channel listed in column 2 Column 1 also identifies the read data bit that returns the input channel listed in column 3 For example data bit O drives output channel 1 when written and returns channel O register setting when read All bits labeled Not Used will return logic O when read The Rear I O Connector Write Register is used to set 16 LVDS output channels This example design has 16 channels identified in Table 3 15 fixed as LVDS output only channels Table 2 1 shows the P4 connector pins and their corresponding channel identifiers This Rear I O Connector Write register i

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