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RM0016 - STMicroelectronics

1. 2_ Transmit Shift Register Receive Shift Register UART2 RX gai UART2 CK UART2 CK CONTROL UART2 GTR GUARD TIME REGISTER UART2 CR5 UART2 v v SCEN IRLP IREN LINEN STOP BITS CPOL CPHA LBCL IrDA SIR BLOCK 4 UART2 CR4 UART2_CR1 T T T LBDIEN LBDL LBDF ADD Lp R8 8 UARTD WAKE PCEN PS PIEN 7 v v v TRANSMIT WAKE UP t RECEIVER lt CONTROL UNIT CONTROL UART2 CR2 Y y 1 4 ILIEN TEN REN RWU SBK RXNE IDLE OR NF FE PE UART2_SR 445 INTERRUPT CONTROL TRANSMITTER RATE CONTROL UART2 BRRi UARTDIV UARTDIV 1 1 4 fMASTER UART2_BRR2 AUTOMATIC RESYNCHRONIZATION UNIT UARTDIV 15 12 UARTDIV S3 0 7 43 0 UART2 CR6 Y RECEIVER RATE LDUM L
2. MCU bus Write Read 2 4 1 DR DATA REGISTER Transmit Data Register TDR Receive Data Register RDR 84 14 b 4 P Transmit Shift Register Receive Shift Register UART1_RX amp rs UART1 CK UART CK CONTROL UART1 GTR H gt GUARD TIME REGISTER 1 CR5 UART1_CR3 vi v scen HDSEL RLP IREN orken Lect IrDA SIR ENDEC BLOCK UART1_CR4 UART1_CR1 LBDIEN LBDL LBDF ADD Ly T8 UARTD M WAKEPCEN PS PIEN UART1_BRR 4 i MASTER BAUD RATE TRANSMIT WAKE_UP gt RECEIVER GENERATOR CONTROL UNIT gt CONTROL 4 UART1_CR2 Y vv v Y T TIEN TCIENRIEN TEN REN RWU SBK TC RXNE IDLE OR NF FE PE UART1_SR y yv INTERRUPT CONTROL 4 318 462 DoclD14587 Rev 12 ky RM0016 Universal asynchronous receiver transmitter UART Figure 111 UART2 block diagram MCU bus Write Read b 4 UART2 DR DATA REGISTER Transmit Data Register TDR Receive Data Register RDR
3. 9 bit Word length M bit is set 1 stop bit Possible Next Data Frame Data Frame Bit Next Start J i 7 7 Sto Start Bit 0 1 2 Bit4 Bits Bit6 Bit7 Bits B Bit CLOCK AE Start Idle Frame Bit Break Frame Extra Start 4 Bit LBCL bit controls last data clock pulse 8 bit Word length M bit is reset 1 stop bit Possible Next Data Frame Data Frame Parity Start Bit ext Bit Bito Bi Bits Bita Bis Bite Biz 50 CLOCK re Start Idle Frame Bit Break Frame Extra Sun ZU it LBCL bit controls last data clock pulse 3 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART 22 3 2 Note Note d 1 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status When the M bit is set word length is 9 bits and the 9th bit the MSB has to be stored in the T8 bit in the UART CR1 register When the transmit enable bit TEN is set the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the UART CK pin Character transmission During an UART transmission data shifts out least significant bit first on the UART TX pin In thi
4. MASTER SLAVE MSBit 4 LSBit MSBit LSBit 8 BIT SHIFT REGISTER 4 MiSo MiSo 8 BIT SHIFT REGISTER A MOSI MOSI SPI CLOCK cK SCK GENERATOR 55 Vpp NSS Not used if NSS is managed a by software The MOSI pins are connected together and the MISO pins are connected together In this way data is transferred serially between master and slave most significant bit first The communication is always initiated by the master When the master device transmits data to a slave device via MOSI pin the slave device responds the MISO pin This implies full duplex communication with both data out and data in synchronized with the same clock signal which is provided by the master device via the SCK pin Slave select NSS pin management A hardware or software slave select management configuration can be set using the Software slave select management SSM bit from the SPI_CR2 register e Software NSS management SSM 1 with this configuration slave select information is driven internally by the Internal slave select SSI bit value in the SPI_CR2 register The external NSS pin remains free for other application uses e Hardware NSS management SSM 0 For devices set as master this configuration allows multimaster capability For devices set as slave the NSS pin works as a cl
5. aor LL ES MN 9 e Inter Frame Space Inter Frame Space Remote Frame Extended identifier or Overload Frame 4 64 4 Std Arbitr Field Ext Arbitr Field Ctrl Field CRC Field Ack Field lt 12 lt 20 gt 6 a 16 7 EXID 28 18 EXID 17 0 DLC CRC EOF 5 5 9 tc lt Data Frame or Inter Frame Space Remote Frame Error Frame or Overload Frame 4 Error Flag Echo Error Delimiter a T R lt 8 Data Frame or Any Frame 4 Inter Frame Space Remote Frame cel Suspend Transmission Bus gt 8 End Of Frame o Error Delimiter AA Inter Frame Space Overload Delimiter Overload Frame or Error Frame 4 Overload Flag Overload Flag Echo Delimiter 6 R lt gt ja 8 Legend 0 lt lt 8 DoclD14587 Rev 12 393 462 Controller area network beCAN 0016 23 7 394 462 SOF Start Of Frame ID Identifier RTR Remote Transmission Request IDE Identifier Extension rO r1 Reserved bits DLC Data Length Code CRC Cyclic Redundancy Code Error flag 6 dominant bits if node is error active else 6 recessive bits Suspend transmission applies to error passive nodes only EOF End of Frame ACK Acknowledge bit send as recessive Ctrl Control Interrupts Two interrupt vectors are dedicated to beCAN Each interrupt source can be independently enabled or disable
6. 5 Header Address 5 EV9 EV6 S Header A Datat A Data2 A DataN 2 A DataN 1 A DataN NA P EV5 EV6 EV7 EV7 EV7 2 EV7 1 Legend S Start S Repeated Start P Stop A Acknowledge Non acknowledge EVx Event with interrupt if ITEVTEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing the DR register EV6 ADDR1 cleared by reading SR1 register followed by reading SR3 In 10 bit master receiver mode this sequence should be followed by writing CR2 with START 1 EV7 RxNE 1 cleared by reading DR register EV7 2 BTF 1 DataN 2 in DR and DataN 1 in shift register program ACK 0 Read DataN 2 in DR Program STOP 1 read DataN 1 EV9 ADD10 1 cleared by reading SR1 register followed by writing DR register EV5 EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence EV7 software sequence must be completed before the end of the current byte transfer In case EV7 software sequence can not be managed before the current byte end of transfer it is recommended to use BTF instead of RXNE with the drawback of slowing the communication DoclD14587 Rev 12 293 595 Inter integrated circuit 2 interface 0016 294 595 When 3 bytes remain to be read RxNE 1 gt Nothing DataN 2 not read DataN 1 received BTF 1 because both shift and data registers are full DataN 2 i
7. 133 Timer feature 1 134 Glossary of internal timer 135 Explanation of indices n and X 136 Counting direction versus encoder 183 Output control for complementary OCi and channels with break Om 205 register map uus eee eu tele Oe he e Mcd oe Rr ee Rein 217 TIM2 register map m oem pepe oe ae wp e E puede E 244 TIMS register map ues Ex esce RE e Rete ee denso nee Ox PER x X ee 246 TIMS register map uium lm eec m em E ue Rr Een 246 TIM4 register 1 255 TIMO register map sullo mme Rem res ed Se ea 256 SPI behavior in low power modes 275 SPI interrupt 41 275 SPI register map and reset values 282 DoclD14587 Rev 12 17 462 List of tables 0016 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61
8. Address offset Register name 7 6 5 4 3 2 1 0 0x00 TIM1 CR1 ARPE CMS1 CMSO DIR OPM URS UDIS CEN 2 Reset value 0 0 0 0 0 0 0 0 0x01 TIM1 CR2 MMS2 MMS1 50 COMS CCPC x Reset value 0 0 0 0 0 0 0 0 0x02 TIM1 SMCR MSM TS2 TS1 TSO SMS2 SMS1 SMSO x Reset value 0 0 0 0 0 0 0 0 0x03 TIM1 ETR ETP ECE ETPS1 ETPSO EFT3 EFT2 EFT1 EFTO Reset value 0 0 0 0 0 0 0 0 0 04 TIM1 IER BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE Reset value 0 0 0 0 0 0 0 0 0x05 TIM1 SR1 BIF TIF COMIF CC4IF CCSIF CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0x06 TIM1 SR2 CC40F CC30F CC20F CC1OF Reset value 0 0 0 0 0 0 0 0 0x07 EGR BG TG COMG CC4G CC3G CC2G CC1G UG x Reset value 0 0 0 0 0 0 0 0 TIM1 CCMR1 OC1CE OC1M2 OC1M1 OC1MO OC1PE OC1FE 151 CC1S0 output mode Reset value 0 0 0 0 0 0 0 0 0x08 TIM1 CCMR1 IC1F3 IC1F2 IC1F1 IC1PSC1 IC1PSCO 151 CC1S0 input mode Reset value 0 0 0 0 0 0 0 0 TIM1 CCMR2 OC2CE OC2M2 OC2M1 OC2MO OC2PE OC2FE 251 250 output mode Reset value 0 0 0 0 0 0 0 0 0x09 TIM1 CCMR2 IC2F3 IC2F2 IC2F1 IC2F0 IC2PSC1 IC2PSCO 251 CC2S0 input mode Reset value 0 0 0 0 0 0 0 0 CCMR3 OC3CE OC3M2 OC3M1 OC3MO OC3FE CC381 50 output mode Reset value 0 0 0 0 0 0 0 0 0x0A CCMR3 IC3F3 IC3F2 IC3F1 IC3PSC1 IC3PSCO CC38S1 50 input mode Reset value 0 0 0 0 0 0 0 0 TIM1 CCMR4 OC4M2 OCAM1 OC4M0 OC4PE OC4FE CC
9. Inter integrated circuit 2 interface 0016 21 7 14 register map and reset values Table 51 12 register map Address Register 9 7 6 5 4 3 2 1 0 offset name 0 12 _ 1 NO STRETCH 2 Reset value 0 0 0 0 0 0 0 0 Oxo 2 CR2 SWRST 5 POS ACK STOP START Reset value 0 0 0 0 0 0 0 0 ame 12C_FREQR 2 FREQ 5 0 Reset value 0 0 000000 dus 2 OARL ADDJ7 1 ADDO Reset value 0000000 0 2 OARH ADDMODE ADDCONF E ADD 9 8 Reset value 0 0 0 0 0 00 0 0x05 Reserved I2C DR DR 7 0 Reset value 0 2 SR1 RXNE STOPF ADD10 BTF ADDR SB Reset value 0 0 0 0 0 0 0 0 didi 2 SR2 WUFH OVR AF ARLO BERR Reset value 0 0 0 0 0 0 0 0 12C_SR3 z GENCALL TRA BUSY MSL Reset value 0 0 0 0 0 0 0 0 I2C ITR ITBUFEN ITEVTEN ITERREN Reset value 0 0 0 0 0 0 0 0 2 CCRL CCR 7 0 0x0B Reset value 00000000 A 2 CCRH FS DUTY CCR 11 8 Reset value 0 0 0 0 0000 aan I2C TRISER E z TRISE 5 0 Reset value 0 0 000010 314 595 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART 22 Universal asynchronous receiver transmitter UART 22 1 Introduction The UARTS in the STM8S and STM8AF microcontroller families UART1 UART2 UART3 or UARTA offer a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynchronous ser
10. 130 TIM1 general block diagram 139 Time Daso uhlt eder eg Ce Re oe sup s wee dead A 140 16 bit read sequence for the counter CNTR 141 Counter in up counting 1 142 Counter update when ARPE 0 ARR not preloaded with prescaler 2 143 Counter update event when ARPE 1 TIM1 ARR 143 Counter in down counting 144 Counter update when ARPE 0 ARR not preloaded with prescaler 2 145 Counter update when ARPE 1 ARR preloaded with prescaler 1 145 Counter in center aligned 146 Counter timing diagram fox fck ARR 06h ARPE 1 147 Update rate examples depending on mode and TIM1 register settings 149 Clock trigger controller block diagram 150 Control circuit in normal mode fox psc fMASTER 151 TI2 external clock connection example 151 Control circuit in external clock mode 1 152 DoclD14587 Rev 12 19 462 List of figures 0016 Figure 47 Figure 48 Figure 49 Figure
11. 1 1 1 T 1 1 1 1 1 1 1 1 IO XX DX S Stat LSB MSB Stop LBCL bit controls last data clock pulse Figure 124 UART data clock timing diagram Mz1 Idle or preceding transmission Start M 1 9 data bits Stop Idle or next transmission gt z gt gt Clock CPOL 0 C J a Clock CPOL 0 CPHA 1 Clock CPOL 1 CPHA 0 H epe pers unn PUL rui epe Clock CPOL 1 CPHA 1 mE i Data E ZX 2 4 5 6 7 8 i Start LSB MSB Stop LBCL bit controls last data clock pulse DoclD14587 Rev 12 337 462 Universal asynchronous receiver transmitter UART 0016 Note 22 3 10 Note 22 3 11 Note 338 462 Figure 125 RX data setup hold time SCLK capture strobe on SCLK rising edge this example pa ns valid DATA bit 15 tHoLD tserup thorn 1 16 bit time 1 16 The function of UART CK is different in Smartcard mode Refer to Section 22 3 11 Smartcard for more details Single wire half duplex communication The UART can be configured to follow a single wire half duplex protocol Single wire half duplex mode is selected by setting the HDSEL bit in the UART_CR8 register In this mode the foll
12. 349 LIN synch field 351 UARTDIV read write operations when 0 351 UARTDIV read write operations when 1 352 Bit sampling in reception 355 UART interrupt mapping diagram 357 CAN network topology 374 beCAN block 375 beCAN operating modes 376 beCAN in silent 41 378 beCAN in loop back mode 378 DoclD14587 Rev 12 21 462 List of figures 0016 Figure 145 Figure 146 Figure 147 Figure 148 Figure 149 Figure 150 Figure 151 Figure 152 Figure 153 Figure 154 Figure 155 Figure 156 Figure 157 Figure 158 Figure 159 Figure 160 Figure 161 Figure 162 Figure 163 Figure 164 Figure 165 22 462 beCAN in combined mode 379 Transmit mailbox states 381 Receive FIFO 382 32 bit filter bank configuration FSC
13. The FMHx and FMLx bits are located in the CAN FMR1 and CAN FMR2 registers Filter registers Filter mode STID 10 3 P UD w EXID FMHx 0 FMHx 0 1 1 pping EXID 28 21 2018 A 17 15 0 FMLx 1 FMLx 0 FMLx 1 Identifier CAN FxR1 CAN FxR2 ID ID n ID n n n Identifier Mask CAN FxR3 FxR4 M ID net M ID n Identifier CAN FxR5 FxR6 ID ID ID nef ID n2 n1 2 Identifier Mask CAN_FxR7 CAN_FxR8 M M ID n amp 2 10 n3 ID Identifier n Filter number M Mask x Filter bank number d DoclD14587 Rev 12 385 462 Controller area network beCAN 0016 Figure 150 16 8 bit filter bank configuration FSCx bits 0601 CAN FCRx register Filter registers Filter mode NEA STID 10 3 END EXID FMHx 0 FMHx 0 1 FMHx 1 pping EXID 28 21 20 18 amp A 17 15 FMLx 0 FMLx 1 FMLx 0 FMLx 1 Identifier FxR1 CAN FxR2 ID ID n ID n n n Identifier Mask CAN FxR3 4 ID nd ID nd Identifier FxR5 ID ID ID nd ID n 2 n1 2 Identifier Mask FxR6 M M ID n2 ID n 3 Identifier FxR7 ID ID ID m3 n 4 2 n 3 Identifier Mask CAN_FxR8 M M ID m4 10 n 5 ID Identifier n Filter number M Mask x Filter bank number
14. 1 81 Devices with trimming 81 CLK interrupt requests 88 Peripheral clock gating bits 2 anaa 94 Peripheral clock gating bits 6 eee 95 CLK register map and reset values 99 Low power mode management 101 I O port configuration summary 1 106 Effect of low power modes on 107 Recommended and non recommended configurations for analog input 108 GPIO register 2 112 Time base calculation table 115 AWU register map RE EORR eR Pepe cn 119 Beeper register 122 Watchdog timeout period LSI clock frequency 128 2 124 IWDG register 126 Window watchdog timing 130 Effect of low power modes 130 WWDOG register map and reset 132 Timer
15. forward jitter backward jitter forward TH TI2 down up down Im DoclD14587 Rev 12 2 RM0016 16 bit advanced control timer TIM1 17 6 2 When the timer is configured in encoder interface mode it provides information on the current position of the sensors Dynamic information such as speed acceleration and slowdown can be obtained by measuring the period between two encoder events using a second timer configured in capture mode The output of the encoder which indicates the mechanical zero can be used for this purpose Depending on the time between two events the counter can also be read at regular intervals This can be done by latching the counter value into a third input capture register if one is available In this case the capture signal must be periodic and can be generated by another timer TIM1 interrupts TIM1 has eight interrupt request sources mapped on 2 interrupt vectors e Break interrupt e Trigger interrupt e Commutation interrupt e Capture compare 4 interrupt e Capture compare interrupt e Capture compare 2 interrupt e Capture compare 1 interrupt e Update interrupt example overflow underflow and counter initialization To use the interrupt features for each interrupt channel used set the desired interrupt enable bits BIE TIE COMIE and UIE in the TIM1 IER register to enable interrupt requests The differen
16. 1 325 Start bit detection une ee 327 Data sampling for noise detection 329 How to code UART DIV in the BRR registers 331 Mute mode using idle line 334 Mute mode using Address mark detection 335 UART example of synchronous 337 UART data clock timing diagram 0 337 UART data clock timing diagram 1 337 RX data setup hold 2 338 ISO 7816 3 asynchronous 339 Parity error detection using 1 5 stop bits 340 IrDA SIR ENDEC block 342 IrDA data modulation 3 16 normal 342 Break detection in LIN mode 11 bit break length LBDL bit is 345 Break detection in LIN mode vs framing error detection 346 LIN identifier field parity 348 LIN identifier field parity 348 LIN header reception
17. 404 _ 1 415 l Ra PCRS E Ho NE o1 0 cr 311 CAN 417 310 UII DM CERE 418 12 1 200 1 43 2 301 FMR2 44 304 CAMDEN SOD 302 396 JeG 309 CAN MEOR egesta seh av tia bd estilos Se xs MEDIUM NIS 303 CAN MDAR 412 RR rins 303 CAN 41 SRY 305 CAN MFMIR 409 2 307 CAN MIDRT 410 5 3 308 GAN emit WORT RICE FOR 313 _ 414 8 68 Ly DoclD14587 Rev 12 459 462 RM0016 125 1 192 IWDG PR 125 TIMI 216 IWDG RLR 126 PSCRH 207 TIMI PSCRL
18. COUNTER REGISTER 31 32 33 34 35 36 0 01 02 03 0405 06 07 COUNTER OVERFLOW UPDATE EVENT UEV UPDATE INTERRUPT FLAG UIF AUTO RELOAD PRELOAD REGISTER FF 36 AUTO RELOAD SHADOW REGISTER FF 36 Write new value ARR New value transferred immediately in shadow register In Figure 36 the prescaler divider is set to 1 so CK CNT has the same frequency as PSC The auto reload preload is enabled ARPE 1 so the next counter overflow occurs at OxFF The new auto reload value register value of 36h is taken into account after the overflow which generates a UEV Figure 36 Counter update event when ARPE z 1 TIM1 ARR preloaded CK PSC CNT EN TIMER CLOCK CK ONT COUNTER REGISTER _ FB FC FO FE FF 00 01 02 03 o4 COUNTER OVERFLOW UPDATE EVENT UEV UPDATE INTERRUPT FLAG UIF AUTO RELOAD PRELOAD REGISTER FF 36 AUTO RELOAD SHADOW REGISTER FF 36 Write a new value in TIMx ARR New value transferred in shadow register on counter overflow d DoclD14587 Rev 12 143 595 16 bit advanced control timer TIM1 0016 17 3 5 144 595 Down counting mod
19. Legends SB Start Bit STB Stop Bit PB Parity Bit In case of wakeup by an address mark the MSB bit of the data is taken into account and not the parity bit Even parity the parity bit is calculated to obtain an even number of 1s inside the frame made of the 7 or 8 LSB bits depending on whether M is equal to 0 or 1 and the parity bit Ex data 00110101 4 bits set gt parity bit will be 0 if even parity is selected PS bit in UART CR 1 0 Odd parity the parity bit is calculated to obtain an odd number of 15 inside the frame made of the 7 or 8 LSB bits depending on whether M is equal to 0 or 1 and the parity bit Example data 00110101 4 bits set gt parity bit will be 1 if odd parity is selected PS bit in UART CRI 1 Transmission If the PCEN bit is set in UART CR1 then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit to give an even number of 1 s if even parity is selected PS 0 or an odd number of 1 s if odd parity is selected 5 1 Reception If the parity check fails the PE flag is set the SR register an interrupt is generated if the PIEN bit is set in the UART CHR1 register DoclD14587 Rev 12 333 462 Universal asynchronous receiver transmitter UART 0016 22 3 7 334 462 Multi processor communication It is possible to perform multi processor communication with the UART se
20. 0016 General purpose ports GPIO Figure 24 GPIO block diagram P BUFFER ALTERNATE 4 OUTPUT PAD 0 ALTERNATE ENABLE E gt PULL UP OUTPUT gt REGISTER gt gt d Von REGISTER EG VAN PIN CR1 REGISTER T gt SLOPE m PROTECTION SK CR2 REGISTER 1 N BUFFER DIODES Analog input On Off INPUT trigger IDR REGISTER KA Read only ALTERNATE FUNCTION INPUT TO ON CHIP PERIPHERAL EXTERNAL enon INTERRUPT OTHER TO INTERRUPT BITS CONTROLLER 17840 Note The output stage is disabled when the analog input is selected 11 3 Port configuration and usage 2 An output data register input register IDR data direction register DDR always associated with each port The control register 1 CR1 and control register 2 CR2 allow input output options An I O pin is programmed using the corresponding bits in the DDR ODR CR1 and CR2 registers Bit n in the registers corresponds to pin n of the Port The various configurations are summarized in Table 21 DoclD14587 Rev 12 105 595 General purpose ports GPIO 0016 11 3 1 106 595 Table 21 I O port configuration summary Diodes Mode E T pus Function Pull up P buffer to Vpp to Vss 0 0 0 Floating without Off interrupt Pull up without Input 0 i interrupt on Off 0 0
21. mode register 3 TIM1 CCMR3 Address offset Ox0A Reset value 0x00 Refer to the CCMR1 register description above Channel configured in output 7 6 5 4 3 2 1 0 OC3CE OC3M 2 0 OC3PE OC3FE CC3S 1 0 rw rw rw rw rw rw rw rw Bit 7 Output compare 3 clear enable Bits 6 4 OC3M 2 0 Output compare 3 mode Bit 3 Output compare 3 preload enable Bit 2 Output compare 3 fast enable Bits 1 0 CC3S 1 0 Capture compare 3 selection This bitfield defines the direction of the channel input output and the used input 00 CC3 channel is configured as output 01 channel is configured as input IC3 is mapped on 10 CC3 channel is configured as input IC3 is mapped on TI4FP3 11 Reserved Note 5 bits writable only when the channel is off and 0 and updated in TIM1 CCER2 Channel configured in input IC3F 3 0 IC3PSC 1 0 CC3S 1 0 Bits 7 4 Input capture 3 filter Bits 3 2 IC3PSC 1 0 Input capture 3 prescaler Bits 1 0 CC3S 1 0 Capture compare 3 selection This bitfield defines the direction of the channel input output and the used input 00 CC3 channel is configured as output 01 channel is configured as input IC3 is mapped on 10 CC3 channel is configured as input IC3 is mapped on TI4FP3 11 Reserved CC3S bits are writable only when the channel i
22. e 0 e fisi e MASTER e with current prescaling selection 50 duty cycle is not guaranteed on all possible prescaled values The selection is controlled by the CCOSEL 3 0 bits in the Configurable clock output register CLK_CCOR The user has to select first the desired clock for the dedicated I O pin see Pin Description chapter This I O must be set at 1 in the corresponding Px 1 register to be set as input with pull up or push pull output The sequence to really output the chosen clock starts with CCOEN 1 in Configurable clock output register CLK CCOR The CCOBSY is set to indicate that the configurable clock output system is operating As long as the CCOBSY bit is set the CCOSEL bits are write protected The CCO automatically activates the target oscillator if needed The CCORDY bit is set when the chosen clock is ready To disable the clock output the user has to clear the CCOEN bit Both CCOBSY and CCORDY remain at 1 till the shut down is completed The time between the clear of CCOEN and the reset of the two flags can be relatively long for instance in case the selected clock output is very slow compared to fcopy CLK interrupts The following interrupts can be generated by the clock controller e Master clock source switch event e Clock Security System event Both interrupts are individually maskable Table 16 CLK interrupt requests Enable Exit Exit Event Inter
23. 107 11 7 Input mode details 108 11 7 1 Alternate function input 108 11 7 2 Interrupt capability 108 11 73 Analog channels 1 108 11 7 4 Schmitt trigger ave i keei3 e yx erase 109 11 75 Analog ss coe Rs rs RR Pa Ren ad 109 11 8 Output mode details 109 11 8 1 Alternate function output 109 11 8 2 Slope control 222 5554 aaa As 109 59 GPIO registers KEE ia 110 11 9 1 Port x output data register PX_ODR 110 11 9 2 Port x pin input register Px_IDR 110 11 9 3 Port x data direction register PX DDR 111 11 9 4 Port x control register 1 1 111 11 9 5 x control register 2 2 112 11 9 6 register map and reset values 112 12 Auto wakeup AWU 113 12 1 Introduction 113 12 2 LSI clock measurement 113 123 AWU functional description 114 12 3 1 AWU op
24. 377 23 4 4 Time triggered communication 377 Ky DoclD14587 Rev 12 13 462 Contents RM0016 235 TestMOdesS Lui to eiae goto p a clos A aa eee 378 23 5 1 Silent mode ire ed paaa badges UE erre px n 378 23 5 2 Loopback mode 378 23 5 8 Loop back combined with silent mode 379 23 6 Functional description 379 23 6 1 Transmission 0 1 379 23 6 2 Reception handling 382 23 6 3 Identifier filtering 1 383 23 6 4 Message storage 389 23 6 5 Error 391 29 6 6 2 25 TREES 392 237 nested 2260558 Des sod 394 23 8 Register access protection 395 209 Glock 35523255220 RR ced DE Cedere gr Rad RE 395 23 10 beCAN low power 395 23 11 beCAN registers iol tat ERI OPES REIP CEFR eee eae tees 396 23 11 1 CAN master control register CAN 396 23 11 2 CAN master status register CAN 397 23 11 3 CAN transmit status register
25. 361 22 7 6 Control register 2 UART 2 362 22 7 7 Control register UART 364 22 7 8 Control register 4 UART 4 365 22 7 9 Control register 5 UART 5 366 22 7 10 Control register 6 UART 6 367 22 7 11 Guard time register UART 368 22 7 12 Prescaler register UART_PSCR 369 22 7 13 UART register map and reset 370 23 Controller area network 373 23 1 IntroducliOli es 373 23 2 beCAN 373 23 3 beCAN general description 374 23 3 1 CAN 2 0B active core 374 23 32 Control status and configuration registers 374 29 3 83 TxmallbOX6esS R EH eee 375 23 3 4 Acceptance filters 375 23 4 Operating modes 376 23 4 1 Initialization mode 376 23 4 2 Normal mode 1 377 23 4 8 Sleep mode low power
26. 195 17 7 9 Capture compare mode register 1 TIM1_CCMR1 196 17 7 10 Capture compare mode register 2 2 200 8 462 DoclD14587 Rev 12 Ly RM0016 Contents 17 7 11 Capture compare mode register 1_ 201 17 7 12 Capture compare mode register 4 4 202 17 7 13 Capture compare enable register 1 CCER1 203 17 7 14 Capture compare enable register 2 CCER2 206 17 7 15 Counter high CNTRH 206 17 7 16 Counter low CNTRL 207 17 7 17 Prescaler high PSCRH 207 17 7 18 Prescaler low PSCRL 207 17 7 19 Auto reload register high ARRH 208 17 7 20 Auto reload register low ARRL 208 17 7 21 Repetition counter register 208 17 7 22 Capture compare register 1 high TIM1_CCR1H 209 17 7 23 Capture compare register 1 low TIM1_CCRIL 209 17 7 24 Capture compare register 2 high TIM1_CCR2H 210 17 7 25 Capture compare register 2 low TIM1_CCR2L 210 17 7 26 Capture compare register 3 high TIM1_CCR3H 211 17 7 27 Capture comp
27. gt TRGO from 6 TRO 14 TRGO from 11 CH c TH gt Trigger TRO TIM1 CH2 po T2 Controller 6 TIM5_CH1 gt gt TIM5_CH2 ppr 12 gt Trigger TRGO TRGO from 5 ITR2 Controller TRGO from TIM1 ITR3 y v 2 158 595 DoclD14587 Rev 12 RM0016 16 bit advanced control timer 1 Figure 54 presents an overview of the trigger selection and the master mode selection blocks Figure 54 Trigger master mode selection blocks TRIGGER SELECTION BLOCK TIMx SMCR TS 2 0 MASTER MODE SELECTION BLOCK UG TRGO from 6 pP ONTEN ITR UEV s MATCHI TRGO TRGO from TIM5 TRON OCIREF gt OCSREF THF ED OC3REF OCAREF From the Capture THFP1 x ee Compare block lt TI2FP2 MMSI 2 0 ETRF CR2 Note Using one timer as prescaler for another timer Refer to Figure 55 to see how timer A can be configured to act as a prescaler for timer B 1 4 Configure timer A in master mode so that it outputs a periodic trigger signal on each UEV To configure that a rising edge is output on TRGO1 each time an update event is generated write MMS 010 in the TIMx CR2 register Connect the TRGO1 output of timer A to timer B timer B must be configured in slave mode using ITR
28. y L PUER La Capture Compare 4 Register gt TIM1_CH4 HERE Legend Preload registers transferred to shadow registers on update event UEV according to control bit event nem d DoclD14587 Rev 12 139 595 16 bit advanced control timer TIM1 0016 17 3 Note 140 595 TIM1 time base unit The timer has a time base unit that includes e 16 bit up down counter e 16 bit auto reload register e Repetition counter e Prescaler Figure 32 Time base unit TIM1 ARRH ARRL TIM1 RCR UEV gt Auto reload register Repetition counter register UIF CK PSC K CNT EV cko 16 bit Counter Repetition Counter TIM1 PSCRH PSCRL TIM1 CNTRH CNTRL Legend Reo Preload registers transferred 1o shadow registers on update event UEV according to control bit le 16 bit counter the prescaler the auto reload register and the repetition counter register can be written or read by software The auto reload register is composed of a preload register plus a shadow register Writing to the auto reload register can be done in two modes e Auto reload preload enabled ARPE bit set in the TIM1 CR1 register In this mode when data is written to the auto reload register it is kept in the preload register and transferred into the shadow register at the next update event
29. NOMINAL BIT TIME min 5 x tg SYNC SEG BIT SEGMENT 1 BS1 BIT SEGMENT 2 BS2 1 gt lt 1851 tBs2 e 1 16 x ty 1 8X ty SAMPLE POINT TRANSMIT POINT 1 BaudRate NominalBitTime NominalBitTime ty tgs tggo with BS1 3 0 1 xt BS2 2 0 1 xt ty BRP 5 0 1 x t sys where t refers to the time quantum is the system clock period faster 5 0 BS1 3 0 and BS2 2 0 are defined in the CAN_BTR1 and CAN BTR2 registers 392 462 DoclD14587 Rev 12 Ly RM0016 Controller area network beCAN d Figure 155 CAN frames Inter Frame Space Inter Frame Space Data Frame Standard identifier or Overload Frame a 44 8 N 4 Arbitration Field Ctrl Field Data Field CRC Field Ack Filg 12 4 6 8 N gt a 16 gt 7 STID 10 0 DLC CRC EOF LL x ES 2 i E Inter Frame Space Inter Frame Space Data Frame Extended identifier or Overload Frame de 64 8 Std Arbitr Field Ext Arbitr Field Ctrl Field Data Field CRC Field Aok Field 12 6 ies Nw 16 7 EXID 28 18 EXID 17 0 DLC CRC EOF ow 5 9 oc lt Inter Frame Space Inter Frame Space Remote Frame Standard identifier or Overload Frame 44 Arbitration Field Ctrl Field CRC Field Ack Field 12 6 16 5 7 STID 10 0 DLC CRC EOF
30. 0016 Interrupt controller Table 8 Software priority levels Software priority Level 1 10 Level 0 main 1 0 Low Level 1 0 1 Level 2 0 0 High Level 3 2 software priority disabled 1 1 Figure 13 Interrupt processing flowchart PENDING Y Y N Interrupt has the same or a N lower software priority than current one 1 0 Y FETCH NEXT THE INTERRUPT 5 INSTRUCTION STAYS PENDING oe Gor Y RET age 26s N Qos Y Y RESTORE PC X Y CCR EXECUTE Y FROM STACK INSTRUCTION STACK PC X Y A CCR LOAD 11 0 FROM INTERRUPT SW REG LOAD PC FROM INTERRUPT VECTOR Caution If the interrupt mask bits 10 and 11 are set within an interrupt service routine ISR with the instruction SIM removal of the interrupt mask with RIM causes the software priority to be set to level 0 To restore the correct priority when disabling and enabling interrupts inside an ISR follow the procedures presented in Table 8 for disabling and enabling the interrupts Table 9 Interrupt enabling disabling inside an ISR Disabling the interrupts Enabling the interrupts asm 2 54 PUSH ISR_CC POP ISR CC POP CC SIM endasm endasm 1 ISR CC is a variable which stores the current value of the CC register 6 2 1 Servicing pending interrupts 3 Several interrupts be pending at the same time The interrupt to be taken into account is determined by the following two step process DoclD14587 Rev 12 59 595 Interrup
31. set by hw cleared by sw set by hw DATA 2 OxF2 roofer Tee ss es eee set by hw cleared by sw Lowe X i DATA 3 OxF3 pa fos Jos 57 set by hw software rites OxF1 in SPI DR Software waits until 1 and writes OxF2 in SPI DR Software waits unti 1 and writes OxF3 in SPI DR Software waits until T software waits until BSY 0 reset by hw Note 268 595 Bidirectional transmit procedure BDM 1 and BDOE 1 In this mode the procedure is similar to the Transmit only procedure except that the BDM and BDOE bits must both be set in the SPI CR2 register before enabling the SPI Unidirectional receive only procedure BDM 0 RXONLY 1 In this mode the procedure can be reduced as described below see Figure 98 1 Setthe RXONLY bit in the SPI CR2 register 2 Enable the SPI by setting bit SPE to 1 a master mode this immediately activates the generation of the SCK clock and data is received serially until the SPI is disabled SPE 0 b In slave mode data are received when the SPI master device drives NSS low and generates the SCK clock 3 Wait until RXNE 1 and read the SPI DR register to get the received data this clears the RXNE bit Repeat this operation for each data to be received This procedure can be also implemented using dedicate
32. bits in the corresponding TIM1_CCER registers This means bypassing the deadtime generator which allows a specific waveform such as PWM or static active level to be sent on one output while the complementary output remains at its inactive level Alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with deadtime When only is enabled CCiE 0 CCiNE 1 itis not complemented and becomes active as soon as is high For example if CCiNP 0 then On the other hand when both OCi and are enabled CCiE 1 OCi becomes active when OCiREF is high whereas OCiN is complemented and becomes active when is low Six step PWM generation for motor control When complementary outputs are implemented on a channel preload bits are available on the OCi M CCi E and CCi NE bits The preload bits are transferred to the active bits at the commutation event COM This allows the configuration for the next step to be programmed in advance and for configuration of all the channels to be changed at the same time The COM event can be generated by software by setting the COMG bit in the TIM1 EGR register or by hardware trigger on the rising edge of TRGI A flag is set when the COM event occurs COMIF bit in the TIM1 SR register which can generate an interrupt if the COMIE bit is set in the TIM1 IER register Figu
33. 10 Reserved 11 Reserved Note 5 bits are writable only when the channel is off CC3E 0 in CCER2 18 6 11 Capture compare enable register 1 TIMx 1 Address offset 0x08 or TIM2 0x07 TIM3 0x0A TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 Reserved CC2P CC2E Reserved CCIE r rw rw r rw rw Bits 6 7 Reserved Bit 5 CC2P Capture compare 2 output polarity Refer to CC1P description Bit 4 CC2E Capture compare 2 output enable Refer to CC1E description 2 238 595 DoclD14587 Rev 12 RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 Bits 2 3 Bit 1 Bit 0 Reserved Capture compare 1 output polarity CC1 channel configured as output 0 OC1 active high 1 OC1 active low CC1 channel configured as input for capture function see Figure 64 0 Capture is done on a rising edge of TI1F or TI2F 1 Capture is done on a falling edge of TI1F or TI2F CC1E Capture Compare 1 output Enable CC1 channel configured as output 0 Off OC1 is not active 1 On OC1 signal is output on the corresponding output pin CC1 channel configured as input In this case this bit determines if a capture of the counter value can be made in the input capture compare register 1 TIMx CCR1 or not 0 Capture disabled 1 Capture enabled 18 6 12 Capture compare en
34. rw Bit 7 Bits 6 5 Bit 4 Bit 3 Bits 2 1 Bit 0 416 462 Reserved FSC3 1 0 Filter scale configuration These bits define the scale configuration of Filter 3 FACT3 Filter active The software sets this bit to activate Filter 3 To modify the Filter 3 registers CAN F3Rx the FACT3 bit must be cleared 0 Filter 3 is not active 1 Filter 3 is active Reserved FSC2 1 0 Filter scale configuration These bits define the scale configuration of Filter 2 2 Filter active The software sets this bit to activate Filter 2 To modify the Filter 2 registers CAN F2Rx the FACT bit must be cleared 0 Filter 2 is not active 1 Filter 2 is active DoclD14587 Rev 12 2 0016 Controller area network beCAN CAN filter configuration register 3 CAN FCR3 Address offset See Table 71 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved FSC51 FSC50 5 Reserved FSC41 FSC40 FACT4 r rw rw rw r rw rw rw Bit7 Reserved Bits 6 5 FSC5 1 0 Filter scale configuration These bits define the scale configuration of Filter 5 Bit 4 FACTS Filter active The software sets this bit to activate Filter 5 To modify the Filter 5 registers CAN_F5Rx the FACT5 bit must be cleared 0 Filter 5 is not active 1 Filter 5 is active Bit3 Reserved Bits 2 1 FSC4 1 0 Filter scale configuration These bits define the scale configuration of Filter 4 Bit FACTA Filter active 2 T
35. 439 24 11 5 ADC configuration register 2 2 440 24 11 6 ADC configuration register 441 24 11 7 ADC data register high DRH 442 24 11 8 ADC data register low DRL 442 24 11 9 ADC Schmitt trigger disable register high ADC_TDRH 443 24 11 10 ADC Schmitt trigger disable register low ADC_TDRL 443 24 11 11 ADC high threshold register high ADC_HTRH 444 24 11 12 ADC high threshold register low ADC_HTRL 444 24 11 13 ADC low threshold register high 445 24 11 14 ADC low threshold register low ADC_LTRL 445 24 11 15 ADC watchdog status register high ADC_AWSRH 446 24 11 16 ADC watchdog status register low ADC_AWSRL 446 DoclD14587 Rev 12 15 462 Contents 0016 24 11 17 ADC watchdog control register high ADC_AWCRH 447 24 11 18 ADC watchdog control register low ADC_AWCRL 447 24 12 ADC register map and reset values 448 25 Revision history 450 16 462 DoclD14587 Rev 12 Ly RM0016 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12
36. 5j 5 oftware resets EOC bit DoclD14587 Rev 12 431 462 Analog digital converter ADC RM0016 24 6 ADC low power modes Table 73 Low power modes Mode Description Wait No effect on ADC In devices with extended features the ADC is automatically switched off Halt before entering Halt Active halt mode After waking up from Active halt the Active halt ADON bit must be set by software to power on the ADC and a delay of 7 us is needed before starting a new conversion The ADC does not have the capability to wake the device from Active halt or Halt mode 24 7 ADC interrupts The ADC interrupt control bits are summarized in Table 74 Table 75 and Table 76 Table 74 ADC Interrupts in single and non buffered continuous mode ADC1 and ADC2 Enable bits gt 2 0 0 0 1 Don t 1 0 1 1 AWSx Don t care Status flags Exit Exit from from AWDG EOC Wait Halt Flag is set if the channel Flag is set at the end of crosses the each conversion programmedthresholds Flag is set if the channel Flag is set at the end of crosses the each conversion andan Yes No programmedthresholds interrupt is generated Flag is set if the channel crosses the programmed Flag is set at the end of An interrupt is Yes No each conversion generated but continuous conversion is not stopped
37. CCR1 for example when input rises 1 Select the active input For example to link the TIM1 register to the TI1 input write the CC1S bits to 01 in the TIM1 CCMR1 register This configures the channel in input mode and the TIM1 CCR 1 register becomes read only 2 Program the required input filter duration for the signal to be connected to the timer This is done for each Tli input using the bits in the TIM1 CCMRi registers For example if the input signal is unstable for up to five tmaster cycles when it toggles the filter duration must be performed for longer than five clock cycles The filter bits allow a duration of eight cycles to be selected by writing them to 0011 in the TIMx CCMR 1 register With this filter setting a transition on 1 is valid only when eight consecutive samples with the new level have been detected sampled at faster frequency 3 Select the edge of the active transition on the channel by writing the CC1P bit to 0 in the TIM1 CCER 1 register rising edge in this case 4 Program the input prescaler In this example the capture needs to be performed at each valid transition so the prescaler is disabled write the IC1PS bits to 00 in the TIM1 CCMHR register 5 Enable capture from the counter into the capture register by setting the CC1E bit in the TIM1 CCER register 6 If needed enable the related interrupt request by setting the CC1IE bit in the TIM1 IER register Wh
38. Mailbox 1 Mailbox 0 Receive FIFO 2 Mailbox 0 7 Acceptance Filters 3 Transmission Scheduler Filter bank 0 CAN 2 0B Active Core DoclD14587 Rev 12 375 462 Controller area network beCAN 0016 23 4 Note 23 4 1 376 462 Figure 142 beCAN operating modes Reset Normal INRQ ACK Initialization SLAK 0 SLAK 0 INAK 0 INAK 1 INRQ SYNC SLEEP Operating modes beCAN has three main operating modes Initialization Normal and Sleep After a hardware reset beCAN is in sleep mode to reduce power consumption The software requests beCAN to enter Initialization or Sleep mode by setting the INRQ or SLEEP bits in the CAN MCR register Once the mode has been entered beCAN confirms it by setting the INAK or SLAK bits in the CAN register When neither INAK nor SLAK are set beCAN is in Normal mode Before entering Normal mode beCAN always has to synchronize on the CAN bus To synchronize waits until the CAN bus is idle this means 11 consecutive recessive bits have been monitored on CANRX The beCAN controls the PGO port CAN TX pin when the beCAN is in Normal mode whereas the PGO port is controlled by the PG and PG DDH GPIO registers while the beCAN is in Initialization mode or
39. Bit9 Bitto wait delimiter delimiter Read Samples 0 0 0 0 0 0 0 0 0 0 0 LBDF 3 DoclD14587 Rev 12 345 462 Universal asynchronous receiver transmitter UART 0016 Note 346 462 Figure 131 Break detection in LIN mode vs framing error detection In these examples we suppose that LBDL 1 11 bit break length 0 8 bit data Case 1 break occurring after an Idle RX line data 1 IDLE BREAK data2 0x55 data 3 header 1 data time 1 data time RXNE FE LBDF Case 2 break occurring while a data is being received RX line data 1 data 2 BREAK data2 0x55 data 3 header 1 data time 1 data time RXNE FE LBDF Response transmission master is the publisher of the response The response is composed of bytes with a standard UART format 8 bit data 1 stop bit no parity In order to send n data bytes the application must repeat the following sequence n times 1 Write data in UART DR register 2 Wait for RXNE flag in UART_SR register 3 Check for readback value by reading the UART_DR register Response reception master is the subscriber of the response In order to receive n data bytes the application must repeat following sequence n times 1 Wait for the RXNE flag in the UART_SR register 2 Read the UART_DR register Discard response slave to slav
40. COUNTER lt gt lt gt t tpULSE Example This example shows how to generate a positive pulse on with a length of tpy_se and after a delay of Ay as soon as a positive edge is detected on the TI2 input Follow the procedure below to use IC2 as trigger 1 e Map IC2 TI2 by writing CC2S 01 in the TIM1 CCMR2 register C2must detect a rising edge so write CC2P 0 in the TIM1 CCER 1 register e Configure IC2 as trigger for the clock trigger controller TRGI by writing TS 110 in the TIM1 SMCR register e 1 2 is used to start the counter by writing SMS to 110 in the 1 register trigger mode DoclD14587 Rev 12 175 595 16 bit advanced control timer TIM1 0016 176 595 The waveform is defined by writing the compare registers taking into account the clock frequency and the counter prescaler as follows e is defined by the value written in the TIM1 CCR 1 register e is defined by the difference between the auto reload value and the compare value TIM1 ARR TIM1_CCR1 e To build a waveform with a transition from 0 to 1 when a compare match occurs and a transition from 1 to 0 when the counter reaches the auto reload value enable PWM mode 2 by writing 111 in the TIM1 CCMHR register Alternatively enable the preload registers by writing OC1PE 1 in the CCMR 1 regist
41. EXID 7 0 Bits 7 0 EXID 7 0 Extended identifier 8 least significant bits of the Extended part of the extended identifier CAN mailbox data length control register CAN MDLCR Address offset See Table 66 and Table 67 Reset value 0 7 6 5 4 3 2 1 0 TGT Reserved DLC 3 0 rw r rw rw rw rw Bit 7 TGT Transmit global time This bit should be used only when the hardware is in the Time Trigger Communication mode TTCM bit in the CAN_MCR register is set It must be cleared by user in Normal mode to transfer last two data bytes correctly 0 CAN_MTSRH and CAN_MTSRL registers are not sent 1 CAN_MTSRH and CAN_MTSRL registers are sent in the last two data bytes of the message Bits 6 4 Reserved Bits 3 0 DLC 3 0 Data length code This field defines the number of data bytes in a data frame or a remote frame request d DoclD14587 Rev 12 411 462 Controller area network beCAN 0016 CAN mailbox data register CAN MDAR x 1 8 Address offset See Table 66 and Table 67 Reset value OxXX 7 6 5 4 3 2 1 0 DATA 7 0 rw rw rw rw rw rw rw rw Bits 7 0 DATA 7 0 Data A data byte of the message A message can contain from 0 to 8 data bytes Note These bits are write protected when the mailbox is not in empty state CAN mailbox time stamp register low CAN_MTSRL Address offset See Table 66 and
42. Reset value 0 0 0 0 0 0 0 0 SR1 CC2IF CCI1IF UIF Reset value 0 0 0 0 0 0 0 0 08 TIM3 SR2 CC2OF 1 Reset value 0 0 0 0 0 0 0 0 deed TIM3_EGR CC2G UG x Reset value 0 0 0 0 0 0 0 0 CCMR1 ocim2 1 1 OC1MO CC1S1 CC1S0 output mode Reset value 0 0 0 0 0 0 0 0 0x05 CCMR1 IC1F3 IC1F2 IC1F1 1 0 5 ICIPSCO CC1S1 CC1S0 input mode Reset value 0 0 0 0 0 0 0 0 TIM3_ CCMR2 4 OC2M2 OC2MI OC2MO OC2PE 251 280 output mode Reset value 0 0 0 0 0 0 0 0 0x06 CCMR2 IC2F3 IC2F2 IC2F1 IC2FO0 IC2PSC1 IC2PSCO 251 CC2S0 input mode Reset value 0 0 0 0 0 0 0 0 ius TIM3 CCER1 g CC2P CC2E 1 Reset value 0 0 0 0 0 0 0 0 TIM3 CNTRH CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 Reset value 0 0 0 0 0 0 0 0 did CNTRL CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO x Reset value 0 0 0 0 0 0 0 0 ik PSCR gt PSC3 PSC2 PSC1 PSCO A Reset value 0 0 0 0 0 0 0 0 ARRH ARR15 ARR14 ARR13 ARR12 ARR11 ARR10 ARR9 ARR8 0x0B Reset value 1 1 1 1 1 1 1 1 dad ARRL ARR6 ARR5 ARR4 ARR2 ARR1 ARRO Reset value 1 1 1 1 1 1 1 1 dum TIM3 CCR1H 115 CCR114 CCR113 CCR112 CCRI11 CCRI10 CCR19 CCR18 n Reset value 0 0 0 0 0 0 0 0 CCR1L 17 CCR16 CCR15 14 CCR13 CCR12 CCR11 CCR10 Reset value 0 0 0 0 0 0 0 0
43. 0 clear ADDR by reading SR1 register followed by reading SR3 register program STOP 1 just after ADDR is cleared EV7 RxNE 1 cleared by reading DR register 2 DoclD14587 Rev 12 295 595 Inter integrated circuit 2 interface 0016 21 4 3 296 595 EV9 ADD10 1 cleared by reading SR1 register followed by writing DR register 2 EV5 EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence 3 EV6 software sequence must be completed before the ACK pulse of the current byte transfer Error conditions The following are the error conditions which may cause communication to fail Bus error BERR This error occurs when the 2 interface detects an external stop or a start condition during an address or data transfer In this case e BERR bit is set and an interrupt is generated if the ITERREN bit is set e Inthe case of the slave data are discarded and the lines are released by hardware Inthe case of a misplaced start the slave considers it is a restart and waits for an address or a stop condition Inthe case of a misplaced stop the slave reacts in the same way as for a stop condition and the lines are released by hardware In the case of the master the lines are not released and there is no effect in the state of the current transmission software can decide if it wants to abort the current transmission or not Acknowledge failure AF This er
44. TH CNT EN counter cLock ck cnt ck Psc ULL COUNTER REGISTER 30 31 32 33 34 a5 36 37 38 mo L Write TIF 0 poe 3 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 d Combining trigger modes with external clock mode 2 External clock mode 2 can be used with another trigger mode For example the ETR can be used as the external clock input and a different input can be selected as trigger input in trigger standard mode trigger reset mode or trigger gated mode Care must be taken not to select ETR as TRGI through the TS bits in the TIM1 SMCR register Example Use the following procedure to enable the up counter at each rising edge on the ETR as soon as a rising edge occurs on TI1 standard trigger mode with external ETR clock 1 Configure the external trigger input circuit by writing to the TIM1 ETR register Write ETF 0000 no filter needed in this example Write ETPS 00 to disable the prescaler write ETP 0 to detect rising edges on the ETR and write ECE 1 to enable external clock mode 2 2 Configure channel 1 to detect rising edges 1 Configure the input filter duration IC1F 0000 The capture prescaler is not used for triggering and does not need to be configured The 15 bits select the input capture source and do not need to be configured either Write CC1P 0 in the TIM1 CCER 1 register to select rising edge polarity
45. a SOFTWARE i IRR A PRIORITY 0 LEVEL gt ES ate LE TRAP eee oer seer rea 11 d 4 3 11 cm 3 1 1 2 ru 3 1109 3 3 11 5 tc RIM MB MILII H4 3 11 z de edu MAN 3 0 11 10 10 DoclD14587 Rev 12 63 595 Interrupt controller ITC 0016 6 5 2 Caution 64 595 Nested interrupt management mode In this mode interrupts are allowed during interrupt routines This mode is activated as soon as an interrupt priority level lower than level 3 is set The hardware priority is given in the following order from the lowest to the highest priority that is MAIN IT4 IT3 IT2 IT1 ITO and TRAP The software priority is configured for each interrupt vector by setting the corresponding I1 xand IO x bits of the ITC SPRx register 1 x and IO x bits have the same meaning as 11 and 10 bits of the CCR register see Table 10 Level 0 can not be programmed I1 x21 10 x0 In this case the previously stored value is kept For example if previous value is OXCF and programmed value equals 64h the result is 44h The RESET and TRAP vectors have no software priorities When one is serviced bits 11 and 10 of the register are both set If bits 11 x and IO x are modified while t
46. bits 1 On OC1 signal is output on the corresponding output pin depending on the MOE OSSI OSSR OIS1 OIS1N and bits CC1 channel is configured as input This bit determines if a capture of the counter value can be made in the input capture compare register 1 1 or not 0 Capture disabled 1 Capture enabled Note On channels that have a complementary output this bit is preloaded If the CCPC bit is set in the TIM1 2 register the active bit takes the new value from the preload bit only when a COM is generated 3 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 Table 38 Output control for complementary and channels with break feature Conirol bits Output states MOE OSSI OSSR CCiE CCiNE OCi OCiN 0 0 0 Output disabled Output disabled not driven by the timer not driven by the timer 0 0 1 Output disabled polarity OCN not driven by the timer OCiREF xor CCNP 0 1 0 polarity OC Output disabled OCIREF xor not driven by the timer Complementary to OC REF 0 1 1 OCIREF polarity deadtime not OC REF polarity deadtime 1 x3 1 0 0 Output disabled Output disabled not driven by the timer not driven by the timer Off state 1 0 1 output enabled with inactive 2 2 on state OC Off state 1 1 0 pon
47. 135 17 16 bit advanced control timer TIM1 137 17 1 Introduction 137 17 2 main features 138 17 3 TIM1 time base unit 140 Ly DoclD14587 Rev 12 7 462 Contents RM0016 17 31 Reading and writing to the 16 bit counter 141 17 8 2 Write sequence for 16 bit TIM1 ARR register 141 17 3 3 Prescaler dix re Gua e pod len Re BORA 141 17 34 Up counting mode 142 17 3 5 Down counting 144 17 3 6 Center aligned mode up down counting 146 17 8 7 Repetition down counter 148 17 4 clock trigger 150 17 4 1 Prescaler clock CK 5 150 17 4 2 Internal clock source MASTER 151 17 4 8 External clock source mode 1 151 17 4 4 External clock source 2 153 17 4 5 Trigger synchronization 154 17 4 6 Synchronization between TIM1 TIM5 TIM6 timers 158 17 5 capture compare channels 164 17 5 4 Write sequence fo
48. 288 TIN pog key tenia eee 210 AMT eoe serai un aan TIM1 CCMR1 MUNERE 196 TIMx CR2 TED 227 TIM1 CCMR2 200 EGR tance 232 1_ 201 TIMx IER ND tak QR aa ie Ec A A 229 Uu Ecc MEUM 200 niin 21 TIME 009 TIMX SME 228 TIN OIE cog TIMXCSRT d uon pio TME RE eo CCR2L 210 211 U TIMI CCR3L 211 TIM1_CCR4H 212 2 ER CORAL ae ecd Ha CNTRH pen 1_ 207 21 E TIMI CRI 22 857 TIMI CR2 ias SART 365 DTR 869 TIMI EGR COME uS P 867 TIMI a 309 460 462 DoclD14587 Rev 12 Index RM0016 UART GTR 368
49. COUNTER REGISTER 0 1 2 33 34 35 36 00 01 02 yo 02 3 TIF DoclD14587 Rev 12 155 595 16 bit advanced control timer 0016 156 595 Trigger gated mode The counter can be enabled depending on the level of a selected input Example Use the following procedure to enable the up counter when TI1 input is low 1 Configure channel 1 to detect low levels on Configure the input filter duration IC1F 0000 The capture prescaler is not used for triggering and does not need to be configured The 15 bits select the input capture source and do not need to be configured either Write CC1P 1 in the CCER 1 register to validate the polarity and detect low level 2 Configure the timer in trigger gated mode by writing SMS 101 in the SMCR register Select 1 as the input source by writing TS 101 in the TIM1 SMCR register 3 Enable the counter by writing CEN 1 in the TIM1 CR 1 register in trigger gated mode the counter does not start if CEN 0 irrespective of the trigger input level The counter starts counting on the internal clock as long as TI1 is low It stops as soon as TI1 becomes high The TIF flag is set when the counter starts or stops The delay between the rising edge on and the actual reset of the counter is due to the resynchronization circuit on 1 input Figure 51 Control circuit in trigger gated mode
50. TPR 399 ADC CSR 438 CAN TSR 398 436 _ 28 _ 437 CLK 97 DRH 442 CLK CKDIVR 93 ADC DRL 442 CLK CMSR 91 ADC 444 CLK CSSR 96 ADC HTRL 444 CLK ECKR 90 445 CLK HSITRIMR 98 ADC 1 445 UE ICKL MEME COEM RENE 89 ADC 443 CLK 1 94 ADC TDRL 443 CLK PCKENRO 95 AWU APR 118 CLK SWCR 92 AWU CSRI UR 2 AWU TBR 118 e ioe EE E AEE B E 1 69 121 EXTL CB2 70 F _ 1_ 406 FLASH CRY osse Seas CAN 2 407 E DGR 403 RN ESR
51. 7 6 5 4 3 2 1 0 Reserved SWIMCLK r rw Bits 7 1 Reserved 0 SWIMCLK SWIM clock divider 98 462 This bit is set and cleared by software 0 SWIM clock divided by 2 1 SWIM clock not divided by 2 d DoclD14587 Rev 12 RM0016 Clock control CLK 9 10 CLK register map and reset values Table 19 CLK register map and reset values Address Register name 7 6 5 4 3 2 1 0 offset 0x00 CLK ICKR REGAH LSIRDY LSIEN FHWU HSIRDY HSIEN Reset value 0 0 0 0 0 0 0 1 0 01 ECKR HSERDY HSEEN a Reset value 0 0 0 0 0 0 0 0 0x02 Reserved area 1 byte 0x03 CLK CMSR CKM7 CKM6 CKM5 CKM4 CKM3 CKM2 CKM1 CKMO Reset value 1 1 1 0 0 0 0 1 0x04 CLK_SWR SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 511 SWIO Reset value 1 1 1 0 0 0 0 1 0x05 CLK SWCR SWIF SWIEN SWEN SWBSY Reset value x x x x x x 0x06 CLK CKDIVR 5 HSIDIV1 HSIDIVO CPUDIV2 CPUDIV12 CPUDIVO Reset value 0 0 0 1 1 0 0 0 0x07 CLK PCKENR1 PCKEN17 PCKEN16 PCKEN15 PCKEN14 PCKEN13 PCKEN12 PCKEN11 PCKEN10 Reset value 1 1 1 1 1 1 1 1 0x08 CLK CSSR CSSD CSSDIE AUX CSSEN Reset value 0 0 0 0 0 0 0 0 CLK CCOR CCOBSY CCORDY CCOSEL3 CCOSEL2 CCOSEL1 CCOSELO CCOEN 0x09 Reset value 0 0 0 0 0 0 0 0 Ox0A CLK PCKENR2 PCKEN27 PCKEN26 PCKEN25 PCKEN24 PCKEN23 PCKEN22 PCKEN21 20 Reset value 1 1 1 1 1 1 1 1 0x0B Reserved area 1 byte 0x0C CLK HSITRIMR HSITRIM2 HSITRIM
52. Analog digital converter ADC 0016 Note Caution 24 5 5 Note 428 462 When using scan mode it is not possible to use channels AINO to AINn in output mode because the output stage of each channel is disabled when it is selected by the ADC multiplexer A single conversion is performed for each channel starting with AINO and the data is stored in the data buffer registers ADC_DBxR When the last channel channel n has been converted the EOC End of Conversion flag is set and an interrupt is generated if the EOCIE bit is set The converted values for each channel can be read from the data buffer registers The OVR flag is set if one of the data buffer registers is overwritten before it has been read see Section 24 5 5 Do not clear the SCAN bit while the conversion sequence is in progress Single scan mode can be stopped immediately by clearing the ADON bit To start a new SCAN conversion clear the EOC bit and set the ADON bit in the 1 register Continuous scan mode This mode is like single scan mode except that each time the last channel has been converted a new scan conversion from channel 0 to channel n starts automatically The OVR flag is set if one of the data buffer registers is overwritten before it has been read see Section 24 5 5 Continuous scan mode is started by setting the ADON bit while the SCAN and CONT bits are set Do not clear the SCAN bit while scan conversion is in
53. CC3IE CC2IE CC1IE UIE axo 0x03 Reset value 0 0 0 0 0 0 0 0 244 595 DoclD14587 Rev 12 ky 0016 16 bit general purpose timers 2 TIM3 TIM5 Table 40 TIM2 register map continued Address offset product Register name 7 6 5 4 3 2 1 0 dependent TIM2 SR1 CC3IF CC2IF CC1IF UIF 0 02 0x04 Reset value 0 0 0 0 0 0 0 0 2 SR2 CC3OF CC20F CC1OF 0x03 0x03 Reset value 0 0 0 0 0 0 0 0 TIM2 EGR CC3G CC2G CC1G UG 0x04 0x06 Reset value 0 0 0 0 0 0 0 0 TIM2 CCMR1 OC1M2 OC1M1 OC1MO CC1S1 CC1S0 output mode Reset value 0 0 0 0 0 0 0 0 0x05 0x07 TIM2 CCMR1 IC1F3 IC1F2 IC1F1 IC1FO IC1PSC1 IC1PSCO CC1S1 CC1S0 input mode Reset value 0 0 0 0 0 0 0 0 2 CCMR2 OC2M2 OC2M1 2 0 OC2PE 251 250 output mode Reset value 0 0 0 0 0 0 0 0 0x06 0x08 TIM2 CCMR2 IC2F3 IC2F2 IC2F1 IC2F0 IC2PSC1 IC2PSCO 251 CC2S0 input mode Reset value 0 0 0 0 0 0 0 0 2 CCMR3 OC3M2 OC3M1 OC3MO CC3S1 50 output mode Reset value 0 0 0 0 0 0 0 0 0x07 0x09 2 CCMR3 IC3F3 IC3F2 IC3F1 IC3FO IC3PSC1 IC3PSCO CC3S1 CC3S0 input mode Reset value 0 0 0 0 0 0 0 0 TIM2 CCER1 2 2 1 1 0x08 20 Reset value 0 0 0 0 0 0 0 0 TIM2 CCER2 0x03 Reset value 0 0 0 0 0 0 0 0 Ox0A 0x0C TIM2 CNTRH CNT15
54. TIM3 CCR2H CCR215 CCR214 CCR213 CCR212 CCR211 CCR210 CCR29 CCR28 Reset value 0 0 0 0 0 0 0 0 Jh TIM3_CCR2L CCR27 CCR26 CCR25 CCR24 CCR23 CCR22 CCR21 CCR20 i Reset value 0 0 0 0 0 0 0 0 Table 42 TIM5 register map Address Register name 7 6 5 4 3 2 1 0 00 5 CR1 ARPE B OPM URS UDIS CEN Reset value 0 0 0 0 0 0 0 0 m TIM5 CR2 MMS2 MMS1 MMSO COMS CCPC Reset value 0 0 0 0 0 0 0 5 SMCR MSM TS2 TS1 TSO SMS2 SMS1 SMSO Reset value 0 0 0 0 0 0 0 246 595 DoclD14587 Rev 12 q 0016 16 bit general purpose timers 2 TIM3 TIM5 Table 42 TIM5 register map continued Address Register name 7 6 5 4 3 2 1 0 0x03 5 IER TIE CC3IE CC2IE 1 Reset value 0 0 0 0 0 0 0 0 0x64 5 SR1 TIF CC2IF CCHIF UIF Reset value 0 0 0 0 0 0 0 0 0x05 TIM5 SR2 z CC3OF CC20F 1 Reset value 0 0 0 0 0 0 0 0 0x06 TIM5 EGR TG CC3G CC2G CC1G UG Reset value 0 0 0 0 0 0 0 0 TIM5 CCMR1 OC1M2 OC1M1 OC1MO CC1S1 CC1S0 output mode Reset value 0 0 0 0 0 0 0 0 0x07 TIM5_CCMR1 IC1F3 IC1F2 IC1F1 IC1FO IC1PSC1 5 CC1S1 150 input mode Reset value 0 0 0 0 0 0 0 0 5 CCMR2 OC2M2 OC2M1 OC2MO OC2PE 251 250 output mode Reset value 0 0 0 0 0 0 0 0 0x08 TIM5 CCMR2 IC2F3 IC2F2 IC2F1 2 0 IC2P
55. e master mode the communication starts immediately and stops when the SPE bit is reset and the current reception stops There is no need to read the BSY flag in this mode It is always set when an SPI communication is ongoing e n slave mode the SPI continues to receive as long as the NSS is pulled down or the SSI bit is reset in NSS software mode and the SCK is running Data transmission and reception procedures Rx and Tx buffer In reception data are received and then stored into an internal Rx buffer while In transmission data are first stored into an internal Tx buffer before being transmitted A read access of the SPI DR register returns the Rx buffered value whereas a write access of the SPI DR stores the written data into the Tx buffer Start sequence in master mode e Infull duplex 0 and RXONLY 0 The sequence begins when data is written into the SPI DR register Tx buffer The data is then parallel loaded from the Tx buffer into the 8 bit shift register during the first bit transmission and then shifted out serially to the MOSI pin Atthe same time the received data on MISO pin is shifted in serially to the 8 bit shift register and then parallel loaded into the DR register Rx Buffer DoclD14587 Rev 12 263 595 Serial peripheral interface SPI 0016 In unidirectional receive only mode BDM 0 RXONLY 1 The sequence begins as soon as the bit SPE 1
56. 001 Enable the counter enable signal is used as a trigger output TRGO It is used to start several timers at the same time or to control a window in which a slave timer is enabled The counter enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in gated mode When the counter enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode is selected see the MSM bit description in 5 SMCR register 010 Update The update event is selected as a trigger output TRGO 011 Reserved 100 Reserved 101 Reserved 111 Reserved Bits 3 0 Reserved must be kept cleared 3 DoclD14587 Rev 12 227 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 6 3 Slave mode control register 5 SMCR Address offset 0x02 Reset value 0x00 7 6 5 4 3 2 1 0 MSM TS 2 0 Reserved SMS 2 0 rw rw rw rw r rw rw rw Note This register is only available in TIM5 see Table 42 on page 246 Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between timers through TRGO Bits 6 4 TS 2 0 Trigger selection This bit field selects the trigger input to be used to synchronize the counter 000 Internal trigger ITRO connected to TIM6 TRGO 001 Internal trigger ITR1 connected to TIM6 TRGO 010 Res
57. 0016 Discard response Software can set the RWU bit immediately LIN Slave parity In LIN Slave mode LINEN and LSLV bits are set LIN parity checking can be enabled by setting the PCEN bit An interrupt is generated if an ID parity error occurs PE bit rises and the PIEN bit is set In this case the parity bits of the LIN Identifier Field are checked The identifier character is recognized as the third received character after a break character included Figure 132 LIN identifier field parity bits parity bits lt gt lt gt lt LIN Break LIN Synch Identifier Field Field gt The bits involved are the two MSB positions 7th and 8th bits of the identifier character The check is performed as specified by the LIN specification Figure 133 LIN identifier field parity check start bit parity bits stop bit identifier bits x IDO ID1 102 1103 ID4 ID5 PO P1 gt Identifier Field IDOGID1 2 4 1 ID16ID36ID4GID5 LIN header error detection The LIN Header Error Flag indicates that an invalid LIN Header has been detected When a LIN Header Error occurs e The LHE flag is set e An interrupt is generated if the RIEN bit the UART_CR2 register is set The LHE bit is reset by an access to the UART_SR register
58. 161 Triggering timer B with the UEV of timer A 162 Triggering timer B with counter enable CNT EN of timer A 163 Triggering Timer and B with Timer A 1 164 Capture compare channel 1 main circuit 164 16 bit read sequence for the TIM1 CCRi register in capture mode 165 Channel input stage block diagram 166 Input stage of TIM 1 channel 1 1 166 PWM input signal 168 PWM input signal measurement example 169 Channel output stage block diagram 169 Detailed output stage of channel with complementary output channel 1 170 Output compare mode toggle on 1 171 Edge aligned counting mode PWM mode 1 waveforms ARR 8 173 Center aligned PWM waveforms ARR 8 174 Example of one pulse 1 175 Complementary output with deadtime insertion 177 Deadtime waveforms with a delay greater than the negative pulse 177 Deadtime waveforms with a delay greater than the p
59. 280 20 45 SPI data register SPI DR 281 20 4 6 CRC polynomial register SPI 281 20 47 Rx CRC register SPI 281 20 4 8 SPI Tx register SPI TXCRCR 282 20 5 SPI register and reset values 282 21 Inter integrated circuit 2 interface 283 21 1 IntroducliOl TEIL den Rad 265 283 212 283 21 3 general 284 214 functional description 286 AF UNE C slave mode NERONE ET 286 Ky DoclD14587 Rev 12 11 462 Contents RM0016 PIAS 288 21 4 8 Error conditions 22252 55 eee eae 296 21 4 48 SDA SCL line 297 21 5 1 low power modes 298 21 6 I C interrupts 22252 cbexa tw oed na cw ad Da dra enu es 298 21 7 300 21 7 1 Control register 1 2 1 300 21 7 2 Control register 2 2 2 301 21 7 3 Fre
60. Bits 7 6 Reserved Bits 5 0 FREQ 5 0 Peripheral clock frequency 1 The FREQ field is used by the peripheral to generate data setup and hold times compliant with the 2 specifications The FREQ bits must be programmed with the peripheral input clock frequency value The allowed range is between 1 MHz and 24 MHz 000000 not allowed 000001 1 MHz 000010 2 MHz 011000 24 MHz Higher values not allowed 1 minimum peripheral clock frequencies for respecting the 1 C bus timings 1 MHz for standard mode and 4 MHz for fast mode 302 595 d DoclD14587 Rev 12 0016 Inter integrated circuit PC interface 21 7 4 Own address register LSB 2 OARL Address offset 0x03 Reset value 0x00 7 6 5 4 3 2 0 ADD 7 1 ADDO rw rw Bits 7 1 ADD 7 1 Interface address bits 7 1 of address Bit ADD 0 Interface address 7 bit addressing mode don t care 10 bit addressing mode bit 0 of address 21 7 5 Own address register MSB 2 OARH Address offset 0x04 Reset value 0x00 7 6 5 4 3 2 0 ADDMODE ADDCONF Reserved ADD 9 8 Reserved rw rw r rw r Bit 7 ADDMODE Addressing mode Slave mode 0 7 bit slave address 10 bit address not acknowledged 1 10 bit slave address 7 bit address not acknowledged Bit6 ADDCONF Address mode configuration This bit must set by software must always be written as 1 Bits 5 3 Reserved Bits 2 1 ADD 9 8 Interface address 10 bit add
61. DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 Channel configured in output 7 6 5 OC1CE OC1M 2 0 OC1PE CC1S 1 0 rw rw rw Bit 7 OC1CE Output compare 1 clear enable This bit is used to enable the clearing of the channel 1 output compare signal OC1 REF by an external event on the TIM1 ETR pin see Section 17 5 9 on page 182 0 OC1REF is not affected by the ETRF input signal derived from the TIM1 ETR pin 1 OC1REF is cleared as soon as a high level is detected ETRF input signal derived from the TIM1 ETR pin Bits 6 4 OC1M Output compare 1 mode 3 These bits define the behavior of the output reference signal OC1REF from which OC1 is derived OC1REF is active high whereas OC1 active level depends on the CC1P bit 000 Frozen The comparison between the output compare register TIM1 CCR1 and the counter register TIM1 CNT has no effect on the outputs 001 Set channel 1 to active level on match OC1REF signal is forced high when the counter register TIM1 CNT matches the capture compare register 1 TIM1 CCR1 010 Set channel 1 to inactive level on match OC1REF signal is forced low when the counter register TIM1 CNT matches the capture compare register 1 TIM1 CCR1 011 Toggle OC1REF toggles when TIM1 CNT TIM1 CCR1 100 Force inactive level OC1REF is forced low 101 Force active level OC1REF is forced hig
62. Figure 80 gives an example of counter operation showing count signal generation and direction control It also shows how input jitter is compensated where both edges are selected This might occur if the sensor is positioned near one of the switching points In the example below configuration is as follows CC1S 01 TIM1_CCMR1 register mapped on 1 25 01 TIM1 CCMR2 register IC2 mapped on 2 CC1P 0 TIM1 CCER 1 register non inverted 1 CC2P 0 TIM1_CCER2 register IC2 non inverted IC2 TI2 SMS 011 TIM1 SMCR register both inputs are active on both rising and falling edges CEN 1 TIM1 CR1 register counter is enabled Figure 80 Example of counter operation in encoder interface mode forward jitter backward jitter forward 2 H up down H Figure 81 gives an example of counter behavior when polarity is inverted same configuration as Figure 80 except that CC1P 1 Figure 81 Example of encoder interface mode with IC1 polarity inverted
63. Output stage Refer to Section 17 5 4 Output stage on page 169 Section 17 5 5 Forced output mode on page 170 Section 17 5 7 PWM mode on page 172 Note As the clock trigger controller and the associated TIMx 2 and TIMx_SMCR registers are not implemented TIM2 TIM3 the one pulse mode described in Section 17 5 7 PWM mode is not available TIM2 TIM3 As shown in Figure 87 TIMx outputs have no deadtime or complementary outputs Figure 87 Output stage channels from capture compare OC1REF output 54 TIMx_CH1 control OC2REF EP output P TIMx CH2 control OC2 OC3REF output PM TIMx CH3 control The output stage generates an intermediate waveform which is then used for reference OCxREF active high Polarity acts at the end of the chain see Figure 86 Figure 88 Output stage of channel 1 Counter CCR1 Counter CCR1 0 Output OC1 Output Mode _OCTREF 1 Circuit Controller CCER1 OC1M 2 0 med CC1E TIMx CCER1 224 595 DoclD14587 Rev 12 d RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 5 d TIM2 TIM3 TIM5 interrupts The timers have 4 interrupt request sources Capture compare 3 interrupt Capture compare 2 interrupt Captur
64. The option bytes are used to configure device hardware features and memory protection They are located in a dedicated memory array of one block The option bytes can be modified both in ICP SWIM and in IAP mode with OPT bit of the FLASH CRe2 register set to 1 and the bit of the FLASH NCR2 register set to 0 see Section 4 8 2 Flash control register 2 FLASH 2 and Section 4 8 3 Flash complementary control register 2 FLASH 2 2 DoclD14587 Rev 12 43 595 Flash program memory and data EEPROM 0016 4 5 4 5 1 4 5 2 44 595 Refer to the option byte section in the datasheet for more information on option bytes and to the STM8 SWIM protocol and debug module user manual UM0470 for details how to program them Memory protection Readout protection Readout protection is selected by programming the ROP option byte to OXAA When readout protection is enabled reading or modifying the Flash program memory and DATA area in ICP mode using the SWIM interface is forbidden whatever the write protection settings Furthermore on medium and high density STM8S and STMB8AF the debug module DM cannot start code execution by the CPU when the readout protection is active and the CPU is stalled Even if no protection can be considered as totally unbreakable the readout feature provides a very high level of protection for a general purpose microcontroller Removing the readout protection The read
65. 0 No action 1 A capture compare event is generated on channel 1 If the CC1 channel is configured in output mode The CC1IF flag is set and the corresponding interrupt request is sent if enabled If the CC1 channel is configured in input mode The current value of the counter is captured the TIM1 CCR 1 register The CC1IF flag is set and the corresponding interrupt request is sent if enabled The CC1OF flag is set if the CC1IF flag is already high Bit 0 UG Update generation This bit can be set by software and is automatically cleared by hardware 0 No action 1 Re initializes the counter and generates an update of the registers Note that the prescaler counter is also cleared The counter is cleared if center aligned mode is selected or if DIR 0 up counting Otherwise it takes the auto reload value TIM1 ARR if DIR 1 down counting Capture compare mode register 1 TIM1 1 Address offset 0x08 Reset value 0x00 This channel can be used in input capture mode or in output compare mode The direction of the channel is defined by configuring the CC1S bits All the other bits of this register have a different function in input and output mode For a given bit describes its function when the channel is configured in output describes its function when the channel is configured in input Therefore be aware that the same bit can have a different meaning for the input and output stage d
66. 12 596 on the whole temperature range To obtain a precise AWU time interval or beeper output the exact LSI frequency has to be measured Use the following procedure 1 Setthe MSR bit in the Control status register AWU_CSR to connect the LSI clock internally to a timer input capture 2 Measure the frequency of the LSI clock using the Timer input capture interrupt 3 Write the appropriate value in the APR 5 0 bits in the Asynchronous prescaler register AWU to adjust the AWU time interval to the desired length The AWUTB 3 0 bits can be modified to select different time intervals LSI clock frequency measurement can also be used to calibrate the beeper frequency see Section 13 2 2 DoclD14587 Rev 12 3 RM0016 Auto wakeup AWU 12 4 AWU registers 12 4 1 Control status register AWU_CSR Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved AWUF AWUEN Reserved MSR r rw r rw Bits 7 6 Reserved Bit 5 AWUF Auto wakeup flag This bit is set by hardware when the AWU module generates an interrupt and cleared by reading the AWU register Writing to this bit does not change its value 0 No AWU interrupt occurred 1 AWU interrupt occurred Bit 4 AWUEN Auto wakeup enable This bit is set and cleared by software It enables the auto wakeup feature If the microcontroller enters Active halt or Wait mode the AWU feature wakes up the microcontrolle
67. 207 P TIMI RCR 208 TIMI SMCR 189 PK SGA 111 1_5 1 193 2 oc ce ee cada RR cR ERR 112 SR2 ccc cc essen 194 PADDR Cc 111 4_ 255 De V 110 TIM4_CNTR 254 PX ODR ae 110 4_ 1 250 4_ 2 251 R TIM4 EGR 254 TIM4 253 RST_SR 76 4 PSCR 254 TIM4 SMCR 251 S 4_5 1 253 TIMx_ARRH 241 uror CMM TIMx ARRL 242 SPI T ME Sc E LE eno a TNE CERE PRETI 239 MN 233 EU CX CHER vues poppe CR X 236 Eur E INCOME MC fe ey 237 reece iur PE S 242 EAMUS _ 1 243 TIMx CCR2H 243 T TIME DGROL iR udrtine Rs 243 T TERIS 208 TMOA T ee UE o pog TIME SCHOL Levi d aded Finge coit d a a MIT 218
68. 332 22 3 6 Parity control gece eed Dia eda Edw da 333 22 3 7 Multi processor communication 334 22 3 8 local interconnection network mode 335 22 3 9 UART synchronous communication 336 22 8 10 Single wire half duplex communication 338 22 3 11 Smartcard RERO RUE en 338 12 462 DoclD14587 Rev 12 Ky RM0016 Contents 22 3 12 IrDA SIR ENDEC block 340 22 4 LIN mode functional description 343 22 4 44 Master mode 343 22 4 Slave mode with automatic resynchronization disabled 347 22 4 3 Slave mode with automatic resynchronization enabled 350 22 4 4 LIN mode selection 355 225 UART low power 356 22 6 UART interrupts sess per rh ch 356 22 7 JLARMTIfTOgISIBIS woven kie EXER ee EREESEREREPREXGA ee ees 358 22 7 1 Status register UART SR 358 22 7 2 Data register DR 360 22 7 3 Baud rate register 1 1 360 22 7 4 Baud rate register 2 2 361 22 7 5 Control register 1 UART 1
69. Bits 4 0 Reserved IDE Extended identifier This bit defines the identifier type of message in the mailbox 0 Standard identifier 1 Extended identifier RTR Remote transmission request 0 Data frame 1 Remote frame STID 10 6 Standard identifier 5 most significant bits of the standard part of the identifier or EXID 28 24 Extended identifier 5 most significant bits of the Base part of extended identifier CAN mailbox identifier register 2 CAN_MIDR2 Address offset See Table 66 and Table 67 Reset value 0 6 5 4 3 2 1 0 STID 5 0 EXID 23 18 EXID 17 16 rw rw rw Bits 7 2 Bits 1 0 410 462 STID 5 0 Standard Identifier 6 least significant bits of the standard part of the identifier or EXID 23 18 Extended Identifier 6 least significant bits of the Base part of extended identifier EXID 17 16 Extended Identifier 2 most significant bits of the Extended part of the extended identifier 2 DoclD14587 Rev 12 0016 Controller area network beCAN CAN mailbox identifier register 3 CAN MIDR3 Address offset See Table 66 and Table 67 Reset value 0 EXID 15 8 Bits 7 0 EXID 15 8 Extended identifier Bit 15 to 8 of the Extended part of the extended identifier CAN mailbox identifier register 4 CAN MIDR4 Address offset See Table 66 and Table 67 Reset value 0
70. DoclD14587 Rev 12 135 595 Timer overview RM0016 136 595 Table 35 Glossary of internal timer signals continued Internal signal name UEV Description Update event UIF Update interrupt Related figures Figure 35 Counter update when ARPE 0 ARR not preloaded with prescaler 2 on page 143 Table 36 Explanation of indices 7 n and 1 Signal number May be 1 2 3 4 depending on the device Bit number May be 1 2 3 4 depending on the device Register number May be 1 2 3 4 depending on the device n Signal number when already used May be 1 2 3 4 depending on the device Timer number May be 1 2 3 4 5 6 depending on the device Don t care for bits 1 These indices are used in Section 17 Section 18 and Section 19 DoclD14587 Rev 12 d 0016 16 bit advanced control timer TIM1 17 16 bit advanced control timer TIM1 This section gives a description of the full set of timer features 17 1 Introduction 3 TIM1 consists of a 16 bit up down auto reload counter driven by a programmable prescaler The timer may be used for a variety of purposes including Time base generation Measuring the pulse lengths of input signals input capture Generating output waveforms output compare PWM and one pulse mode Interrupt capability on various events capture compare overflow break trig
71. Immediately after the TXRQ bit has been set the mailbox enters pending state and waits to become the highest priority mailbox see Transmit Priority As soon as the mailbox has the highest priority it will be scheduled for transmission The transmission of the message of the scheduled mailbox will start enter transmit state when the CAN bus becomes idle Once the mailbox has been successfully transmitted it will become empty again The hardware indicates a successful transmission by setting the RQCP and TXOK bits in the CAN MCSR and CAN TSR registers If the transmission fails the cause is indicated by the ALST bit in the CAN MCSR register in case of an Arbitration Lost and or the TERR bit in case of transmission error detection Transmit priority By identifier When more than one transmit mailbox is pending the transmission order is given by the identifier of the message stored in the mailbox The message with the lowest identifier value has the highest priority according to the arbitration of the CAN protocol If the identifier values are equal the lower mailbox number will be scheduled first DoclD14587 Rev 12 379 462 Controller area network beCAN 0016 380 462 By transmit request order The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN MCR register In this mode the priority order is given by the transmit request order This mode is very useful for segmented transmissi
72. In synchronous mode the following bits must be kept cleared e LINEN bit in the UART register e SCEN HDSEL and IREN bits in the UART CR5 register This feature is only available in UART1 UART2 and UAHTA The UART CK pin is the output of the UART transmitter clock No clock pulses are sent to the UART CK pin during start bit and stop bit Depending on the state of the bit in the UART register clock pulses will or will not be generated during the last valid data bit address mark The CPOL bit in the UART CR3 register allows the user to select the clock polarity and the bit in the UART_CR3 register allows the user to select the phase of the external clock see Figure 122 Figure 123 amp Figure 124 During idle and break frames the external CK clock is not activated In synchronous mode the UART receiver works differently compared to asynchronous mode If RE 1 the data is sampled on SCLK rising or falling edge depending on CPOL and without any oversampling A setup and a hold time even if the hold time is not relevant due to the SPI protocol must be respected which depends on the baud rate 1 16 bit time for an integer baud rate The UART CK pin works in conjunction with the TX pin When the UART transmitter is disabled TEN and REN 0 UART CK and UART_TX pins go into high impedance state The LBCL CPOL and bits in UART_CR3 have to be selected when both the transmitter
73. Introduction In circuit debugging mode or in circuit programming mode are managed through a single wire hardware interface featuring ultrafast memory programming Coupled with an in circuit debugging module it also offers a non intrusive emulation mode making the in circuit debugger extremely powerful close in performance to a full featured emulator Main features e Based on an asynchronous high sink 8 mA open drain bidirectional communication e Allows reading or writing any part of memory space e Access to CPU registers A X Y CC SP They are memory mapped for read or write access e intrusive read write on the fly to the RAM and peripheral registers e Device reset capability with status flag in the Reset status register RST SH e Clock speed selectable in the SWIM clock control register SWIMCCR SWIM pin can be used as a standard with some restrictions if you also want to use it for debug The most secure way is to provide on the PCB a strap option Figure 12 SWIM pin connection for application q4 341 e MCU SWIM PAO SWIM interface for tools 4 41 e Jumper selection for debug purposes SWIM modes After a power on reset the SWIM is reset and enters OFF mode 1 OFF Default state after power on reset The SWIM pin cannot be used by the application as an 2 WO This state is entered by sof
74. MTSRH tt Configuration Diagnostic Receive FIFO in DGR register 420 462 DoclD14587 Rev 12 Ly 0016 Controller area network beCAN Table 69 beCAN control and status page register map and reset values Address Register name 7 6 5 4 3 2 1 0 Offset dm TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ Reset Value 0 0 0 0 0 0 1 0 RX TX WKUI ERRI SLAK INAK Reset Value 0 0 0 0 0 0 1 0 TSR TXOK2 TXOK1 TXOKO RQCP2 RQCP1 RQCPO Reset Value 0 0 0 0 0 0 0 0 de CAN_TPR LOw2 LOW1 LOWO TME2 TME1 TMEO CODE1 CODEO Reset Value 0 0 0 0 1 1 0 0 mdi CAN RFR RFOM FOVR FULL FMP1 FMPO Reset Value 0 0 0 0 0 0 0 0 CAN IER WKUIE FOVIE FFIE FMPIE TMEIE 0x05 Reset Value 0 a 0 0 0 0 0 0 dus 2 RX SAMP SILM LBKM Reset Value 0 0 0 0 1 1 0 0 CAN PSR PS2 PS1 PSO Reset Value 0 0 0 0 0 0 0 0 Table 70 mailbox pages register map and reset values Address Register name 7 6 5 4 3 2 1 0 Offset 0x00 MFMIR FMI7 FMI6 5 FMI4 FMI3 FMI2 FMIO Receive Reset Value x x x x x x x x 0x00 CAN_MCSR TERR ALST TXOK RQCP ABRQ TXRQ Transmit Reset Value 0 0 0 0 0 0 0 0 MDLCR TGT DLC3 DLC2 DLC1 DLCO 0x01 Reset Value x x x x x x x x CAN MIDR1 IDE RTR STID10 STID9 STID8 STID7 STID6 0x02 EXID28 EXID27 EXID26 EXID25 EXID24 R
75. life augmented Reference man ual y 5 85 series and STMB8AF series 8 bit microcontrollers Introduction This reference manual provides complete information for application developers on how to use STM8S and STMB8AF series microcontroller memory and peripherals The STMB8AF series of microcontrollers is designed for automotive applications with different memory densities packages and peripherals The low density STM8AF devices are the STM8AF6223 26 with 8 Kbytes of Flash memory The medium density STM8AF devices are the STM8AF624x and STM8AF6266 68 microcontrollers with 16 to 32 Kbytes of Flash memory The high density STM8AF devices are the STM8AF52xx and STM8AF6269 8x Ax microcontrollers with 32 to 128 Kbytes of Flash memory The STMBS series of microcontrollers is designed for general purpose applications with different memory densities packages and peripherals The value line low density STM8S devices are the STM8S003xx microcontrollers with 8 Kbytes of Flash memory The value line medium density STM8S devices are the STM8S005xx microcontrollers with 32 Kbytes of Flash memory The value line high density STM8S devices are the STM8S007xx microcontrollers with 64 Kbytes of Flash memory The access line low density STM8S devices are the STM8S103xx and STM8S903xx microcontrollers with 8 Kbytes of Flash memory The access line medium density STM8S devices are the STM8S105xx microcontrollers with 16 to 32 Kbytes o
76. AUTO RELOAD PRELOAD REGISTER AUTO RELOAD SHADOW REGISTER ET EB osyo4JosJozyorjooyFF FBF Fo FB oojaejss s4 06 Cleared by software FF 36 FF 36 Write a new value TIMx ARR New value transferred in shadow register on counter underflow DoclD14587 Rev 12 145 595 16 bit advanced control timer TIM1 0016 17 3 6 146 595 Center aligned mode up down counting In center aligned mode the counter counts from 0 to the auto reload value of 1 content of the TIM1 ARR register This generates a counter overflow event The counter then counts down to 0 and generates a counter underflow event After this the counter restarts counting from 0 In this mode the direction bit DIR in the TIM1_CR1 register cannot be written It is updated by hardware and gives the current direction of the counter The Figure 40 shows an example of this counting mode Figure 40 Counter in center aligned mode Counter gt Overflow Underflow Overflow Underflow Time If the timer has a repetition counter as in TIM1 the UEV is generated after up and down counting and repeated for the number of times programmed in the repetition counter register TIM1_RCR Otherwise the UEV is generated at each counter overflow and at each counter underflow S
77. BDM 0 and RXLONY 0 Case of discontinuous 270 2C bus protocol MONET TO TEE TR ET ETT ES 284 diagram oos Em 285 Transfer sequence diagram for slave 287 Transfer sequence diagram for slave 288 Transfer sequence diagram for master 291 Method 1 transfer sequence diagram for master 292 Method 2 transfer sequence diagram for master receiver when N gt 2 293 Method 2 transfer sequence diagram for master receiver when 2 295 Method 2 transfer sequence diagram for master receiver when 1 295 12 interrupt mapping 299 UART1 block 22 2 318 UART2 block diagram 2222 2 22 emm mem emm rg m deeds 319 UART block 2 320 UARTA block 2 22 2 321 Word length programming 0 4 322 Configurable stop 324 TC TXE behavior when 0
78. BRP 1 fmaster 2 406 462 DoclD14587 Rev 12 RM0016 Controller area network beCAN 23 11 14 CAN bit timing register 2 CAN_BTR2 Address offset See Table 71 Reset value 0x23 7 6 5 4 3 2 1 0 Reserved BS2 2 0 BS1 3 0 r rw rw rw rw rw rw nw This register can only be accessed by the software when the CAN hardware is in initialization mode Bit 7 Reserved must be kept cleared Bits 6 4 BS2 2 0 Bit Segment 2 These bits define the number of time quanta in Bit Segment 2 Bit Segment 2 BS2 1 Bits 3 0 BS1 3 0 Bit Segment 1 3 These bits define the number of time quanta in Bit Segment 1 Bit Segment 1 BS1 1 For more information on bit timing please refer to Section 23 6 6 Bit timing DoclD14587 Rev 12 407 462 Controller area network beCAN RM0016 23 11 15 Mailbox registers This chapter describes the registers of the transmit and receive mailboxes Refer to Section 23 6 4 Message storage for detailed register mapping Transmit and receive mailboxes have the same registers except CAN_MCSR register in a transmit mailbox is replaced by CAN_MFMIR register in a receive mailbox A receive mailbox is always write protected A transmit mailbox is write enabled only while empty the corresponding TME bit in the CAN_TPR register is set Caution As the mailbox registers usually have no defined reset value the user should not r
79. Bit 6 OVR Overrun flag This bit is set by hardware and cleared by software 0 No overrun 1 An overrun was detected in the data buffer registers Refer to Section 24 5 5 on page 428 for more details Bits 5 0 Reserved must be kept cleared 3 DoclD14587 Rev 12 441 462 Analog digital converter ADC RM0016 24 11 7 ADC data register high ADC_DRH Address offset 0x24 Reset value 0 DH 7 0 Bits 7 0 24 11 8 DH 7 0 Data bits high These bits are set reset by hardware and are read only When the ADC is in single or non buffered continuous mode they contain the high part of the converted data in right aligned or left aligned format depending on the ALIGN bit Left Data Alignment These bits contain the 8 MSB bits of the converted data The MSB must be read first before reading the LSB see Section 24 9 Reading the conversion result and Figure 165 Right Data Alignment These bits contain the ADC data width 8 MSB bits of the converted data Remaining bits are tied to zero See Figure 164 ADC data register low DRL Address offset 0x25 Reset value 0 DL 7 0 Bits 7 0 442 462 DL 7 0 Data bits low These bits are set reset by hardware and are read only When the ADC is in single or non buffered continuous mode they contain the low part of the A D conversion result in right aligned or left alig
80. CAN 398 23 11 4 CAN transmit priority register CAN TPR 399 23 11 5 CAN receive FIFO register CAN 401 23 11 6 CAN interrupt enable register 402 23 11 7 diagnostic register CAN DGR 403 23 11 8 CAN page select register CAN PSR 403 23 11 9 CAN error status register CAN 404 23 11 10 CAN error interrupt enable register CAN EIER 405 23 11 11 CAN transmit error counter register TECR 405 23 11 12 CAN receive error counter register CAN 406 23 11 13 CAN bit timing register 1 CAN BTR1 406 23 11 14 CAN bit timing register 2 CAN BTR2 407 23 11 15 Mailbox registers 408 23 11 16 CAN filter registers 413 23 12 CAN register 419 23 12 1 Page mapping for CAN 420 24 Analog digital converter ADC 423 14 462 DoclD14587 Rev 12 Ky RM0016 Contents d 24 1 24 2 24 3 24 4 24 5 24 6 24 7 24 8 24 9 24 10 24 11 rr 423 ADC main features 423 ADC extended featu
81. Each be individually programmed as a digital input or digital output In addition some ports may have alternate functions like analog inputs external interrupts input output for on chip peripherals Only one alternate function can be mapped to a pin at a time the alternate function mapping is controlled by option byte Refer to the datasheet for a description of the option bytes An output data register input data register data direction register and two configuration registers are associated with each port A particular port will behave as an input or output depending on the status of the data direction register of the port GPIO main features e Port bits can be configured individually e Selectable input modes floating input or input with pull up e Selectable output modes push pull output or pseudo open drain e Separate registers for data input and output e External interrupts can be enabled and disabled individually e Output slope control for reduced EMC noise e Alternate function I Os for on chip peripherals e Input Schmitt trigger be disabled on analog inputs for reduced power consumption e Read modify write possible on data output latch e 5 V tolerant inputs e O state guaranteed in voltage range 1 6 V to Vppiomax 2 DoclD14587 Rev 12
82. In interrupt is and an interrupt is generated and scan generated conversion is stopped 434 462 DoclD14587 Rev 12 Ly RM0016 Analog digital converter ADC 24 8 24 9 d Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion Data can be aligned in the following ways Right Alignment 8 Least Significant bits are written in the ADC_DL register then the remaining Most Significant bits are written in the ADC_DH register The Least Significant Byte must be read first followed by the Most Significant Byte In this case the LDW instruction can be used as it has the same reading order Figure 164 Right alignment of data D9 D8 ADC DRH D7 D6 D5 D4 D3 D2 D1 DO ADC_DRL Left Alignment 8 Most Significant bits are written in the ADC_DH register then the remaining Least Significant bits are written in the ADC_DL register The Most Significant Byte must be read first followed by the Least Significant Byte Figure 165 Left alignment of data D9 D8 D7 D6 D5 D4 D3 D2 ADC_DRH D1 DO ADC_DRL Reading the conversion result The conversion results from ADC_DRH and ADC_DRL data registers must be read in a specific order to guarantee data coherency This order depends on the data alignment refer to Section 24 8 Data alignment When the ADC
83. LBDIEN D LHDF LHDIEN 2 DoclD14587 Rev 12 357 462 Universal asynchronous receiver transmitter UART 0016 22 7 UART registers 22 7 1 Status register UART SR Address offset 0x00 Reset value 0 0 7 6 5 4 3 2 1 0 TC RXNE IDLE OR LHE NF FE PE r rc 0 rc 0 r r r r r Bit7 TXE Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register An interrupt is generated if the TIEN bit 21 the UART_CR2 register It is cleared by a write to the UART DR register 0 Data is not transferred to the shift register 1 Data is transferred to the shift register Bit 6 TC Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and TXE bit is set An interrupt is generated if TCIEN 1 in the CR2 register The TC bit is cleared either by a software sequence a read to the UART_SR register followed by a write to the UART DR register or by programming the bit to 0 This clear sequence is recommended only for multibuffer communications 0 Transmission is not complete 1 Transmission is complete Bit 5 RXNE Read data register not empty This bit is set by hardware when the content of the RDR shift register has been transferred to the UART DR register An interrupt is generated if RIEN 1 in the UART CR2 register It is cleared by a
84. MODE OE EN ONLY SSM SSI Y v Y NSS The SPI is connected to external devices through four pins e MISO Master In Slave Out data port C7 This pin can be used to transmit data in slave mode and receive data in master mode e MOSI Master Out Slave In data port C6 This pin can be used to transmit data in master mode and receive data in slave mode SCK Serial Clock output port C5 for SPI masters and Serial Clock input for SPI slaves e NSS Slave select port E5 This is a optional pin to select a slave device This pin acts as a chip select to let the SPI master communicate with slaves individually and to avoid contention on the data lines Slave NSS inputs can be driven by standard ports on the master device When configured in master mode MSTR bit 21 and if NSS is pulled low the SPI enters master mode fault state the MSTR bit is automatically reset and the device is configured in slave mode refer to Section 20 3 9 Error flags on page 274 A basic example of interconnections between a single master and a single slave is illustrated in Figure 92 258 595 DoclD14587 Rev 12 Ly 0016 Serial peripheral interface SPI Note When using the SPI in High speed mode the I Os where SPI outputs are connected should be programmed as fast slope outputs in order to be able to reach the expected bus speed Figure 92 Single master single slave application
85. Output compare 2 mode Bit OC2PE Output compare 2 preload enable Bit 2 Reserved Bits 1 0 CC2S 1 0 Capture compare 2 selection This bitfield defines the direction of the channel input output as well as the used input 00 CC2 channel is configured as output 01 CC2 channel is configured as input 2 is mapped 2 2 10 CC2 channel is configured as input IC2 is mapped TH FP2 11 CC2 channel is configured as input IC2 is mapped on TRC This mode works only if an internal trigger input is selected through the TS bit 5 SMCR register Note 25 bits writable only when the channel is off CC2E 0 in TIMx 1 236 595 DoclD14587 Rev 12 Ly RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 Channel configured in input IC2F 3 0 IC2PSC 1 0 CC2S 1 0 Bits 7 4 IC2F 3 0 Input capture 2 filter Bits 3 2 IC2PCS 1 0 Input capture 2 prescaler Bits 1 0 CC2S 1 0 Capture compare 2 selection 18 6 10 This bitfield defines the direction of the channel input output as well as the used input 00 CC2 channel is configured as output 01 CC2 channel is configured as input IC2 is mapped on TI2FP2 10 CC2 channel is configured as input IC2 is mapped on TI1FP2 11 Reserved Note 25 bits are writable only when the channel is off CC2E 0 in 1 Capture compare mode register 3 TIMx CCMR3 Refer to Capture compare mode register
86. Read CCR1H Read CCR1L C 1 C1S 1 OO mode CC1S 0 capture CC1E CC1G TIM1 capture compare channels The timer I O pins TIM1 can be configured either for input capture or output compare functions The choice is made by configuring the CCiS channel selection bits in the capture compare channel mode registers TIM1 CCMRij where iis the channel number Each Capture Compare channel is built around a capture compare register including a shadow register an input stage for capture with digital filter multiplexing and prescaler and an output stage with comparator and output control Figure 61 Capture compare channel 1 main circuit input read in progress write in progress Capture Compare Preload Register capture transfer output compare transfer f P fione Capture Compare shadow Register TIMx EGR Counter write CCR1H write CCR1L CC1S 1 CC1S 0 EY CCMR1 Comparator rom time base unit 164 595 DoclD14587 Rev 12 3 16 bit advanced control timer TIM1 0016 capture compare block is made of one preload register and one shadow register Write and read always access the preload register In capture mode captures are made in the shadow register
87. Reserved 11 Reserved ALIGN Data alignment This bit is set and cleared by software 0 Left alignment the eight MSB bits are written in the DRH register then the remaining LSB bits are written in the DRL register The reading order should be MSB first and then LSB 1 Right alignment eight LSB bits are written in the ADC_DRL register then the remaining MSB bits are written in the register The reading order should be LSB first and then MSB Note The ALIGN bit influences the DRH ADC DRL register reading order and not the reading order of the buffer registers Reserved must be kept cleared SCAN Scan mode enable This bit is set and cleared by software 0 Scan mode disabled 1 Scan mode enabled Note This bit is not available for ADC2 Reserved must be kept cleared d DoclD14587 Rev 12 RM0016 Analog digital converter ADC 24 11 6 ADC configuration register 3 ADC_CR3 Address offset 0x23 Reset value 0x00 6 5 4 3 2 1 0 DBUF OVR Reserved rc 0 r Note This register is not available for ADC2 Bit 7 DBUF Data buffer enable This bit is set and cleared by software It is used together with the CONT bit enable buffered continuous mode DBUF 1 CONT 1 When DBUF is set converted values are stored in the ADC_DBxRH and DBxRL registers instead of the DRH and ADC_DRL registers 0 Data buffer disabled 1 Data buffer enabled
88. Reset Value 0 0 0 0 0 0 0 0 m UART4_PSCR PSC7 PSC6 5 5 5 4 5 5 2 PSC1 PSCO Reset Value 0 0 0 0 0 0 0 0 372 462 DoclD14587 Rev 12 Ky RM0016 Controller area network beCAN 23 23 1 23 2 2 Controller area network Introduction The Basic Enhanced CAN peripheral named beCAN interfaces the CAN network It supports the CAN protocol version 2 0A and B It has been designed to manage high number of incoming messages efficiently with a minimum CPU load It also meets the priority requirements for transmit messages For safety critical applications the CAN controller provides all hardware functions for supporting the CAN Time triggered Communication option beCAN main features e Supports CAN protocol version 2 0 A B Active e Bitrates up to 1 Mbit s e Supports the Time Triggered Communication option Transmission e Three transmit mailboxes e Configurable transmit priority e Time Stamp on SOF transmission Reception e One receive FIFO with three stages e Six scalable filter banks e Identifier list feature e Configurable FIFO overrun e Time Stamp on SOF reception Time triggered communication option Disable automatic retransmission mode e 16 bit free running timer e Configurable timer resolution e Time Stamp sent in last two data bytes Management e Maskable interrupts e Software efficient mailbox mapping at a unique address space DoclD14587 Rev 12 373 462 Cont
89. SWIM pin connection 57 Interrupt processing flowchart 2 2 2 59 Priority decision process 2 60 Concurrent interrupt 63 Nested interrupt management 65 Power supply 72 Resebclrcull Sa Gk Puig Radon eee Gee de 73 VDD VDDIO voltage detection POR BOR 74 ehe qii RC 78 HSE clock SOUICOS ou Ue dee perde d t ERE Ced rate a Eds a 79 Clock switching flowchart automatic mode example 84 Clock switching flowchart manual mode example 85 GPIO block 105 AWU block diagram 113 Beep block diagram 120 Independent watchdog IWDG block diagram 123 Watchdog block diagram 2 2 128 Approximate timeout 1 129 Window watchdog timing
90. TIM1 TRIG renamed TIM1 ETR Section 20 Serial peripheral interface SPI Added note related to parallel multislave structures in Section 20 3 2 Configuring the SPI in slave mode Section 21 Inter integrated circuit I2C interface Modified Figure 101 I2C block diagram on page 285 Figure 102 Transfer sequence diagram for slave transmitter and Figure 103 Transfer sequence diagram for slave receiver Modified Section 21 4 2 I2C master mode Modified PO bit description changed in Section 21 7 2 Control register 2 I2C 2 Modified note 8 in Section 21 7 7 Status register 1 I2C 5 1 Section 21 7 11 Clock control register low I2C_CCRL and Section 21 7 12 Clock control register high 2 Added Table 50 2 values for SCL frequency table MASTER 10 MHz or 16 MHz Section 22 Universal asynchronous receiver transmitter UART Updated L N break and delimiter detection Updated Table 54 Baud rate programming and error calculation Updated interrupt source flags and slave mode features updated in Section 22 2 2 DoclD14587 Rev 12 455 462 Revision history RM0016 456 462 Table 79 Document revision history continued Date 31 Jan 2011 Revision 7 continued Changes Section 23 Controller area network Modified upper limit in Section 23 9 Clock system SLEEP and AWUM bit description
91. TIMx ARRH ARRL UEV A Auto Reload Register UIF CK PSC K CNT Prescaler CK 16 bit Counter UEV Legend Preload registers transferred PSCR CNTRH CNTRL event UEV according o Vj interrupt Ly DoclD14587 Rev 12 221 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 4 2 222 595 For more details refer to Section 17 3 TIM1 time base unit page 140 Prescaler The prescaler implementation is as follows e prescaler is based on a 16 bit counter controlled through a 4 bit register in the TIMx register It can be changed on the fly as this control register is buffered It can divide the counter clock frequency by any power of 2 from 1 to 32768 The counter clock frequency is calculated as follows fck psc 2 96 RI 0 The prescaler value is loaded through a preload register The shadow register which contains the current value to be used is loaded as soon as the LS Byte has been written The new prescaler value is taken into account in the following period after the next counter update event Read operations to the TIMx PSCR registers access the preload registers so no special care needs to be taken to read them Counter operation Refer to Section 17 3 4 Up counting mode on page 142 Clock trigger controller A clock trigger controller and the associated TIMx CR2 and TIMx S
92. Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Ly Interr pt levels dhe noeh e be CR n ede be 26 GPU register map retreat race e eR ae Re nca 27 CFG GCR register 28 List of abbreviations 1 33 Block SIZ8 uec Rare tech qd pieds UU gun dx e ede od 49 Memory access versus programming method 50 Flash register and reset 56 Software priority levels 59 Interrupt enabling disabling inside an ISR 59 Vector address map versus software priority 64 Dedicated interrupt instruction set 65 Interrupt register 1 71 HST register map usu se ese te He dba RE rds 76 Devices with 4 trimming
93. The break character is sent without taking into account the number of stop bits If the UART is programmed with 2 stop bits the TX line is pulled low until the end of the first stop bit only Then 2 logic 1 bits are inserted before the next character If the software resets the SBK bit before the start of break transmission the break character is not transmitted For two consecutive breaks the SBK bit should be set after the stop bit of the previous break Idle character Setting the TEN bit drives the UART to send an idle frame before the first data frame Receiver The UART can receive data words of either 8 or 9 bits When the M bit is set word length is 9 bits and the MSB is stored in the R8 bit in the UART CR1 register Start bit detection In the UART the start bit is detected when a specific sequence of samples is recognized This sequence is 1 1 10 XO X OX OX 0 X OX 0 The start bit detection sequence shown in Figure 117 2 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Figure 117 Start bit detection RX line 4 Ideal 1 1 1 1 1 1 1 1 1 1 1 1 t te ts ts te tr fe values h amp tx tx tx tx tx tx hots fo hsh 6 16 E oOo e 7 6 _ gt 4 7 6 gt E One bit time M Conditions i
94. This bit determines the word length It is set or cleared by software 0 1 Start bit 8 Data bits n Stop bit n depending on STOP 1 0 bits in the register 1 1 Start bit 9 Data bits 1 Stop bit Note The M bit must not be modified during a data transfer both transmission and reception In LIN slave mode the M bit and the STOPT 1 0 bits in the UART register should be kept at 0 Bit 3 WAKE Wakeup method d This bit determines the UART wakeup method it is set or cleared by software 0 Idle Line 1 Address Mark DoclD14587 Rev 12 361 462 Universal asynchronous receiver transmitter UART 0016 Bit 2 PCEN Parity control enable Bit 1 Bit 0 22 7 6 UART Mode This bit selects the hardware parity control generation and detection When the parity control is enabled the computed parity is inserted at the MSB position 9th bit if M 1 8th bit if M 0 and parity is checked on the received data This bit is set and cleared by software Once it is set PCEN is active after the current byte in reception and in transmission 0 Parity control disabled 1 Parity control enabled LIN slave mode This bit enables the LIN identifier parity check while the UART is in LIN slave mode 0 Identifier parity check disabled 1 Identifier parity check enabled PS Parity selection This bit selects the odd or even parity when the parity generation detection is enabled PCEN bit set in UART mode It i
95. Timer B UG Timer B write CNT Timer B TIF Write 0 DoclD14587 Rev 12 161 595 16 bit advanced control timer 0016 162 595 Using one timer to start another timer Example 1 The enable of timer B is set with the UEV of timer A refer to Figure 55 for connections Timer B starts counting from its current value which can be non zero on the divided internal clock as soon as the UEV is generated by timer A When timer B receives the trigger signal its CEN bit is automatically set and the counter counts until O is written to the CEN bit in the TIM1 CR1 register Both counter clock frequencies are divided by four by the prescaler compared to fyaster fck 2 1 Configure timer A master mode to send its UEV as trigger output MMS 010 in the TIM1 CR register 2 Configure the timer A period TIM1 ARR registers 3 Configure timer B to get the input trigger from timer A see TS 2 0 bit definitions in TIM1 SMCR register 4 Configure timer B in trigger mode SMS 110 in TIM1 SMCR register 5 Start timer A by writing 1 in the CEN bit TIM1 CR register Figure 58 Triggering timer B with the UEV of timer A TIMERA UEV taster Timer A UEV TimerA CNT X rb Xr Xr Loa Xo X Timer B CNT 46 47 48 Timer B CEN CNT Timer B
96. UEV e Auto reload preload disabled ARPE bit cleared the TIM1 CR1 register In this mode when data is written to the auto reload register it is transferred into the shadow register immediately An update event is generated e On a counter overflow or underflow e software setting the UG bit in the TIM1_EGR register e Byatrigger event from the clock trigger controller With preload enabled ARPE 1 when an update event occurs The auto reload shadow register is updated with the preload value TIM1 ARR and the buffer of the prescaler is reloaded with the preload value content of the TIM1 PSCR register The UEV can be disabled by setting the UDIS bit in the TIM1 1 The counter is clocked by the prescaler output CK which is enabled only when the counter enable bit CEN in TIM1 CHR1 register is set The actual counter enable signal CNT EN is set 1 clock cycle after CEN 2 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 3 1 Note 17 3 2 17 3 3 2 Reading and writing to the 16 bit counter There is no buffering when writing to the counter Both TIM1 CNTRH and TIM1 CNTRL can be written at any time so it is suggested not to write a new value into the counter while itis running to avoid loading an incorrect intermediate content An 8 bit buffer is implemented for the read Software must read the MS byte first after which the LS byte value is buffered automat
97. d The following steps are required to disable write protection of the main program area 1 Write a first 8 bit key into the FLASH PUKR register When this register is written for the first time after a reset the data bus content is not latched into the register but compared to the first hardware key value 0x56 2 Ifthe key available on the data bus is incorrect the FLASH register remains locked until the next reset Any new write commands sent to this address are discarded 3 If the first hardware key is correct when the FLASH PUKR register is written for the second time the data bus content is still not latched into the register but compared to the second hardware key value OxAE 4 Ifthe key available on the data bus is incorrect the write protection on program memory remains locked until the next reset Any new write commands sent to this address is discarded 5 If the second hardware key is correct the main program memory is write unprotected and the PUL bit of the FLASH IAPSR is set see Section 4 8 8 Flash status register FLASH 5 register Before starting programming the application must verify that PUL bit is effectively set The application can choose at any time to disable again write access to the Flash program memory by clearing the PUL bit Enabling write access to the DATA area After a device reset it is possible to disable the DATA area write protection by writing consecutively two
98. each rising edge of RXNE or TXE flags DoclD14587 Rev 12 265 595 Serial peripheral interface SPI 0016 Figure 94 TXE RXNE BSY behavior in full duplex mode RXONLY 0 Case of continuous transfers Example in Master Mode with CPOL 1 CPHA 1 DATA1 OxF1 DATA2 OxF2 OxF3 MISOMOSI out oofer Joe os ous e Te oe os or oo oa Tee o 57 set by hw set by hw TXE flag cleared by sw cleared by sw set by hw a BSY flag by hw reset by hw DATA1 1 DATA 2 0xA2 DATA 3 7 spe fee os es s eor oo Tee es osos ooo op Tee eps e RXNE flag li po Rx Buffer E T read SPI DR ur J E software software waits oftware waits Software waits until software waits until software waits until rites OxF1 until 1 and until RXNE 1 1 and writes RXNE 1 and reads OxA2 RXNE 1 and reads in SPI DR writes OxF2 in nd reads OxA1 OxF3 in SPI DR from SPI DR OxA3 from SPI DR SPI DR rom SPI DR Figure 95 TXE RXNE BSY behavior in slave full duplex mode BDM 0 RXONLY 0 Case of continuous transfers Example in Slave Mode with CPOL 1 CPHA 1 SCK DATA 1 OxF1 DATA 2 OxF2 DATA 3 OxF3 visomos out oof Joe ee Te os Joo oe Te eo s s oT Tees res oo set by hw set by hw TXE flag cleared sw cleared by sw set by hw or
99. see Table 17 0 faster to peripheral disabled 1 faster to peripheral enabled Table 17 Peripheral clock gating bits Control bit Peripheral PCKEN17 16 15 TIM2 TIM5 product dependent PCKEN14 TIM4 TIM6 product dependent PCKEN13 UART 1 2 3 4 product dependent see datasheet PCKEN12 for bit assignment table PCKEN11 SPI PCKEN10 2 2 94 462 DoclD14587 Rev 12 0016 Clock control CLK 9 9 8 Peripheral clock gating register 2 PCKENR2 Address offset OxOA Reset value OxFF PCKEN2 7 0 Bits 7 0 PCKEN2 7 0 Peripheral clock enable These bits are written by software to enable or disable the fmaster clock to the corresponding peripheral See Table 17 0 faster to peripheral disabled 1 faster to peripheral enabled Table 18 Peripheral clock gating bits Control bit Peripheral PCKEN27 CAN product dependent see datasheet PCKEN26 Reserved PCKEN25 Reserved PCKEN24 Reserved PCKEN23 ADC PCKEN22 AWU PCKEN 1 Reserved 20 Reserved Ky DoclD14587 Rev 12 95 462 Clock control CLK RM0016 9 9 9 Clock security system register CLK_CSSR Address offset 0x08 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved CSSD CSSDIE AUX CSSEN r rc wO rw r rwo Bits 7 4 Reserved must be kept cleared Bit 3 CSSD Clock security sys
100. with see TS 2 0 bit definitions in TIMx SMCR register Section 23 4 Operating modes added a note about port the Disclaimer 2 DoclD14587 Rev 12 457 462 Revision history RM0016 458 462 Table 79 Document revision history continued Date 23 Sep 2015 Revision 12 Changes Window watchdog WWDG Corrected the downcounter bit number in Figure 28 Watchdog block diagram Inter integrated circuit 12C interface Removed PEC calculation and PEC register boxes in Figure 101 2 block diagram Universal asynchronous receiver transmitter UART Updated the LIN version in Section 22 1 Introduction Controller area network beCAN Improved the readability of Figure 148 to Figure 151 2 DoclD14587 Rev 12 RM0016 Index Index A CAN MIDR4 411 ADC AWCRH scere UU NEUE EE RED 397 CAN MTSRH 412 _ 447 8 412 ADC AWSRH 446 CAN PSR 403 AWSRL 446 406 _ 1 439 RFR 401 _ 2 440 TEGR 405 441
101. 0 PE Peripheral enable 0 Peripheral disable 1 Peripheral enable the corresponding I Os are selected as alternate functions Note If this bit is reset while a communication is on going the peripheral is disabled at the end of the current communication when back to IDLE state All bit resets due to 0 occur at the end of the communication 300 595 DoclD14587 Rev 12 Ly 0016 Inter integrated circuit 2 interface 21 7 2 Control register 2 2 CR2 Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 SWRST Reserved POS ACK STOP START rw r rw rw rw rw Bit 7 SWRST Software reset When set the 2 is at reset state Before resetting this bit make sure the 2 lines are released and the bus is free 0 2 Peripheral not at reset state 1 I2C Peripheral at reset state Note This bit be used in case the BUSY bit is set to 1 when no stop condition has been detected on the bus Bits 6 4 Reserved Bit 3 POS Acknowledge position for data reception This bit is set and cleared by software and cleared by hardware when 0 0 ACK bit controls the N ACK of the current byte being received in the shift register 1 ACK bit controls the N ACK of the next byte which will be received in the shift register Note The POS bit is used when the procedure for reception of 2 bytes see Method 2 transfer sequence diagram for master receiver when N 2 is followed It must be configured
102. 0016 Figure 115 Configurable stop bits 8 bit Word length M bit is reset Possible Next Data Frame Data Frame Parity Start S Bit Bito Bitt Bite Bits Bite Bi LE CLOCK Lee d LBCL bit controls last data clock pulse a 1 Stop Bit iod Next Data Frame Data Frame Bi y it Next Start z Start Bit Bito Bit Bit2 Bits Bite Bit7 Bit b 1 1 2 stop Bits Possible Next Data Frame Parity Data Frame Bit Next Start _ 2Stop Start Bit Bit Biti Bit Bits Bit5 Bit7 Bits Bit 2 Stop Bits Procedure 1 Program the M bit in CH1 to define the word length 2 Program the number of stop bits in UART 3 Select the desired baud rate by programming the baud rate registers in the following order a UART BRR2 b UART_BRR1 4 Setthe TEN bit in UART_CR2 to enable transmitter mode 5 Write the data to send in the UART_DR register this clears the bit Repeat this for each data to be transmitted in case of single buffer 6 the last data is written to the DR register wait until TC is set to 1 which indicates that the last data transmission is complete This last step is required for instance to avoid last data t
103. 0x03 Reset value 0x02 6 4 2 BSY OVR MODF CRCERR WKUP Reserved TXE RXNE rc_w0 rc_w0 rc_w0 rc_w0 r 280 595 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSY Busy flag 0 SPI not busy 1 SPI is busy in communication This flag is set and reset by hardware Note BSY flag must be used with cautious refer to Section 20 3 7 Status flags on page 272 and Section 20 3 8 Disabling the SPI on page 272 OVR Overrun flag 0 No Overrun occurred 1 Overrun occurred This flag is set by hardware and reset by a software sequence MODF Mode fault 0 No Mode fault occurred 1 Mode fault occurred This flag is set by hardware and reset by a software sequence CRCERR error flag 0 CRC value received matches the SPI RXCRCR value 1 CRC value received does not match the SPI RXCRCR value This flag is set by hardware and cleared by software writing O WKUP Wakeup flag 0 No wakeup event occurred 1 Wakeup event occurred This flag is set on the first sampling edge on SCK when the 5 8 is in Halt mode and the SPI is configured as slave This flag is reset by software writing O Reserved TXE Transmit buffer empty 0 Tx buffer not empty 1 Tx buffer empty RXNE Receive buffer not empty 0 Rx buffer empty 1 Rx buffer not empty d DoclD14587 Rev 12 RM0016 Serial peripheral interface SPI 20 4 5 SPI data regi
104. 1 TIM1 1 on page 196 for details on using these bits Address offset 0x07 or 0x09 TIM2 0x09 5 for TIM2 address see Section Reset value 0x00 Channel configured in output 7 6 5 4 3 2 0 Reserved OC3M 2 0 OC3PE Reserved CC3S 1 0 r rw rw rw rw r rw Note This register is not available in TIM3 Bit 7 Reserved Bits 6 4 OC3M 2 0 Output compare mode Bit OC3PE Output compare preload enable Bit 2 Reserved Bits 1 0 CC3S 1 0 Capture compare 3 selection This bitfield defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 channel is configured as input IC3 is mapped on 10 Reserved 11 Reserved Note 5 bits are writable only when the channel is off CC3E 0 in CCER2 Ly DoclD14587 Rev 12 237 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 Channel configured in input 7 6 5 4 2 1 0 IC3F 3 0 IC3PSC 1 0 CC3S 1 0 rw rw rw rw rw rw rw Note This register is not available in TIM3 Bits 7 4 IC3F 3 0 Input capture 3 filter Bits 3 2 IC3PSC 1 0 Input capture 3 prescaler Bits 1 0 CC3S 1 0 Capture compare 3 selection This bitfield defines the direction of the channel input output as well as the used input 00 channel is configured as output 01 channel is configured as input IC3 is mapped on
105. 1 Floating with interrupt Off 0 1 1 Pull up with interrupt On On 1 0 0 Open drain output Off On 1 1 0 Push pull output Off On 1 0 1 drain output fast Oft Output 1 1 1 Push pull fast mode Off On True open drain on POR E 1 X X d Not implemented plemented specific pins 1 1 The diode connected to Vpp is not implemented in true open drain pads A local protection between the pad and Vo is implemented to protect the device against positive stress Input modes Clearing the DDRx bit selects input mode In this mode reading a IDR bit returns the digital value of the corresponding pin Refer to Section 11 7 Input mode details on page 108 for information on analog input external interrupts and Schmitt trigger enable disable As shown in Table 21 four different input modes can be theoretically be configured by software floating without interrupt floating with interrupt pull up without interrupt or pull up with interrupt However in practice not all ports have external interrupt capability or pull ups You should refer to the datasheet pin out description for details on the actual hardware capability of each port 2 DoclD14587 Rev 12 RM0016 General purpose ports GPIO 11 3 2 11 4 11 5 11 6 Note 2 Output modes Setting the DDRx bit selects output mode In this mode writing to the ODR bits applies a digital value to the I O through the latch Rea
106. 1 a 2 00 pe als apace aire eme cue T esed 1 0 1 5 IR tee 3 1 3 11 9 Q RIM oc ae m C 4 AEETI 3 11 35 1 9 SRAEUMIN a a a Cmn 3 0 11 10 10 6 6 External interrupts Five interrupt vectors are dedicated to external Interrupt events e 5 lines on Port A PA 6 2 e 8lines on Port B PB 7 0 e 8lines on Port C PC 7 0 e on Port D PD 6 0 e 8lines on Port E PE 7 0 PD7 is the Top Level Interrupt source TLI except for 20 pin packages on which the Top Level Interrupt source TLI can be available on the PC3 pin using an alternate function remapping option bit Refer to option bytes section in the product datasheet for more details To generate an interrupt the corresponding GPIO port must be configured in input mode with interrupts enabled Refer to the register description in the GPIO chapter for details The interrupt sensitivity must be configured in the external interrupt control register 1 EXTI_CR1 and external interrupt control register 2 CR2 see Section 6 9 3 and Section 6 9 4 6 7 Interrupt instructions Table 11 shows the interrupt instructions Table 11 Dedicated interrupt instruction set Instruction New description Function example n 10 N 2 HALT Entering Halt mode 1 0 IRET Interrupt routine return Pop CCR A X Y PC 11 H 0 N Z C JRM Jump if 11 0 11 level
107. 2 CPU register map pees Register name 7 6 5 4 3 2 1 0 offset 0x00 A MSB LSB 0x01 PCE MSB i LSB 0x02 PCH MSB LSB 0x03 PCL MSB LSB 0x04 XH MSB x E LSB 0x05 XL MSB LSB 0x06 YH MSB 5 LSB 0x07 YL MSB E LSB 0x08 SPH MSB LSB 0x09 SPL MSB LSB 0x0A V 0 11 H 10 2 C 1 3 Global configuration register CFG 1 3 1 Activation level The MCU activation level is configured by programming the AL bit in the CFG_GCR register For information on the use of this bit refer to Section 6 4 Activation level low power mode control on page 62 1 3 2 SWIM disable By default after an MCU reset the SWIM pin is configured to allow communication with an external tool for debugging or Flash EEPROM programming This pin can be configured by the application for use as a general purpose I O This is done by setting the SWD bit in the register Ly DoclD14587 Rev 12 27 595 Central processing unit CPU 0016 1 3 3 Description of global configuration register CFG Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved AL SWD rw rw Bits 7 2 Reserved Bit 1 AL Activation level This bit is set and cleared by software It configures main or interrupt only activation 0 Main activation level An IRET instruction causes the context to be retrieved from the stack and the main pro
108. 24 11 14 ADC low threshold register low ADC_LTRL Address offset 0x2B Reset value 0x00 7 6 5 4 3 2 1 0 Reserved LT 1 0 r rw rw Note This register is not available for ADC2 Bits 7 2 Reserved must be kept cleared Bits 1 0 LT 1 0 Analog watchdog low voltage threshold LSB d These bits are set and cleared by software They define the LSB of the low threshold Vggr for the Analog Watchdog DoclD14587 Rev 12 445 462 Analog digital converter ADC 0016 24 11 15 ADC watchdog status register high AWSRH Address offset 2 Reset value 0x00 7 6 5 4 3 2 Reserved AWS 9 8 rc wO rc wO r Note This register is not available for ADC2 Bits 7 2 Reserved must be kept cleared Bits 1 0 AWS 9 8 Analog watchdog status flags 9 8 These bits are set by hardware and cleared by software In buffered continuous mode DBUF 1 1 AWS flags behave as described in Table 75 scan mode 5 1 AWS flags behave as described in Table 76 0 No analog watchdog event in data buffer register x 1 Analog watchdog event occurred in data buffer register x 24 11 16 ADC watchdog status register low ADC_AWSRL Address offset 0x2D Reset value 0x00 AWS 7 0 rc_w0 rc wO rc wO rc 0 rc wO rc 0 rc 0 rc wO Note This register is not available for ADC2 Bits 7 0 AWS 7 0 Analog watchdog status flags 7 0 T
109. 3 Configure the timer in trigger mode by writing SMS 110 in the TIM1 SMCR register Select 1 as the input source by writing TS 101 in the TIM1SMCR register A rising edge on TI1 enables the counter and sets the TIF flag Consequently the counter counts on the ETR rising edges The delay between the rising edge on and the actual reset of the counter is due to the resynchronization circuit on input The delay between the rising edge on the ETR and the actual reset of the counter is due to the resynchronization circuit on the ETRP signal Figure 52 Control circuit in external clock mode 2 trigger mode TH CEN ETR COUNTER CLOCK CK ONT CK PSC COUNTER REGISTER 34 35 36 TIF DoclD14587 Rev 12 157 595 16 bit advanced control timer TIM1 0016 17 4 6 Synchronization between TIM1 TIM5 TIM6 timers STM8AF and 5 85 low density devices the timers are linked together internally for timer synchronization or chaining When one timer is configured in master mode it can output a trigger TRGO to reset start stop or clock the counter of any other timer configured in slave mode Figure 53 Timer chaining system implementation example TIM 1 TRGO from TIM6 ITRO TRGO from 5 ITR2 Trigger TRGO TIM5 H Controller p
110. 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 20 462 External trigger input block diagram 1 153 Control circuit in external clock 2 153 Control circuit in trigger 154 Control circuit in trigger reset mode 155 Control circuit in trigger gated 156 Control circuit in external clock mode 2 trigger mode 157 Timer chaining system implementation example 158 Trigger master mode selection blocks 159 Master slave timer example 159 Gating timer B with OC1REF of timer 160 Gating timer B with the counter enable signal of timer CONT
111. 9 1 CPU condition code register interrupt bits CCR for the values to be programmed for each priority SPR1 bits 1 0 are forced to 1 by hardware TLI SPR8 bits 7 4 are forced to 1 by hardware Note lt is forbidden to write 10 priority level 0 If 10 is written the previous value is kept and the interrupt priority remains unchanged 2 68 595 DoclD14587 Rev 12 RM0016 Interrupt controller ITC 6 9 3 External interrupt control register 1 EXTI_CR1 Address offset 0x00 Reset value 0x00 PDIS 1 0 15 1 0 PBIS 1 0 PAIS 1 0 rw rw rw rw Bits 7 6 PDIS 1 0 Port D external interrupt sensitivity bits These bits can only be written when 11 10 in the CCR register are both set to 1 level They define the sensitivity of Port D external interrupts 00 Falling edge and low level 01 Rising edge only 10 Falling edge only 11 Rising and falling edge Bits 5 4 PCIS 1 0 Port C external interrupt sensitivity bits These bits can only be written when 11 and 10 in the CCR register are both set to 1 level They define the sensitivity of Port C external interrupts 00 Falling edge and low level 01 Rising edge only 10 Falling edge only 11 Rising and falling edge Bits 3 2 PBIS 1 0 Port B external interrupt sensitivity bits These bits can only be written when 11 and 10 in the CCR register are both set to 1 level They define the sensitivity of Port B external interr
112. 9 596 0 032 0x0412 0x41 0 02 9 598 0 020 0x0693 Ox68h 0x03 19 2 19 193 0 032 0x0209 0x20 0x09 19 208 0 040 0x0341 0x34 0x01 57 6 57 471 0 224 0 00 OxOE 57 554 0 080 0 0116 0x11 0x06 115 2 114 942 0 224 0x0057 0x05 0x07 115 108 0 080 0x008B 0x08 OxOB 230 4 232 558 0 937 0x002B 0x02 OxOB 231 884 0 644 0x0045 0x04 0x05 460 8 454 545 1 358 0x0016 0x01 0x06 457 143 0 794 0x0023 0x02 0x03 921 6 NA NA NA NA 941 176 2 124 0 11 0x01 0x01 1 Error Calculated Desired Baud Rate Desired Baud Rate Note 22 3 5 332 462 The lower the faster frequency the lower will be the accuracy for a particular baud rate The upper limit of the achievable baud rate can be fixed with this data Clock deviation tolerance of the UART receiver The USART s asynchronous receiver works correctly only if the total clock system deviation is less than the USART receiver s tolerance The causes which contribute to the total deviation are DTRA Deviation due to the transmitter error which also includes the deviation of the transmitter s local oscillator DQUANT Error due to the baud rate quantization of the receiver DREC Deviation of the receiver s local oscillator DTCL Deviation due to the transmission line generally due to the transceivers which can introduce an asymmetry between the low to high transition timing an
113. Bit 7 Reserved Bit 6 4 LEC 2 0 Last error code Bit 3 This field holds a code which indicates the type of the last error detected on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared to 0 The code 7 is unused and be written by the CPU to check for update 000 No Error 001 Stuff Error 010 Form Error 011 Acknowledgment Error 100 Bit recessive Error 101 Bit dominant Error 110 CRC Error 111 Set by software Reserved Bit 2 BOFF Bus off flag This bit is set by hardware when it enters the bus off state The bus off state is entered on CAN TECR overrun TEC greater than 255 refer to Section 23 6 5 on page 391 Bit 1 EPVF Error passive flag This bit is set by hardware when the Error Passive limit has been reached Receive Error Counter or Transmit Error Counter greater than 127 Bit EWGF Error warning flag 404 462 This bit is set by hardware when the warning limit has been reached Receive Error Counter or Transmit Error Counter greater than 96 d DoclD14587 Rev 12 RM0016 Controller area network beCAN 23 11 10 CAN error interrupt enable register CAN_EIER Address offset See Table 71 Reset value 0000 0000 00h 6 5 3 ERRIE Reserved LECIE Reserved BOFIE EPVIE EWGIE r rw r Bit 7 Bit 6 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
114. CLK HSITRIMR 98 9 9 12 SWIM clock control register CLK 98 9 10 CLK register and reset values 99 10 Power management 100 10 1 General considerations 100 10 1 1 Clock management for low consumption 101 10 2 Low power modes 101 10 2 1 Waitmode 102 10 22 Haltmode 102 10 2 3 Active halt modes 102 10 3 Additional analog power controls 103 10 3 1 Fast Flash wakeup from Halt mode 103 10 3 2 Very low Flash consumption in Active halt mode 103 11 General purpose I O ports GPIO 104 DENEN 104 112 GPIO main features 104 11 8 Port configuration and usage 105 11 3 1 input modes s nue re RR E Rx t ht Ren DR e ete 106 11 3 2 Output modes 107 11 4 Reset configuration 107 11 5 Unused WO pinS 532552545 RR E RR 107 Ky DoclD14587 Rev 12 5 462 Contents RM0016 11 8 Low power modes
115. CLK register description for more details DoclD14587 Rev 12 77 462 Clock control CLK 0016 Figure 20 Clock tree CKM 7 0 HSE Ext CPUDIV 2 0 fuse OSCIN HSE OSC 1 24MHz OSCOUT EXTCLK OPT BIT 4 f 8 fcp Master MASTER CPU Clock n6 1 CSS HSIDIV 1 0 Switch 132 64 8 128 HSI RC p 4 fusipiv 16 ja To CPU and window watchdog LSI EN OPT 5 LSI RC fst 128 kHz to Timers 12C To independent watchdog SPI Peripheral clock MU enable 8 bits PRSC 1 0 BITS UART k it AW 128 kHz auto wakeup unit AWU CKAWUSEL OPT BIT CCOSEL 3 0 fusi fuisipiv fuse Configurable clock output MASTER fopu 2 fcpu 4 fcpu 8 fepu 1 6 fopy 32 fopy 64 1 Legend HSE High speed external clock signal HSI High speed internal clock signal LSI Low Speed internal clock signal 2 78 462 DoclD14587 Rev 12 RM0016 Clock control CLK 9 1 d Master clock sources 4 different clock sources can be used to drive the master clock 1 24 MHz high speed external crystal oscillator HSE Up to 24 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC
116. DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Impact of clock deviation on maximum baud rate The choice of the nominal baud rate UARTDIVNOM will influence both the quantization error DQUANT and the measurement error DMEAS The worst case occurs for UARTDIVMIN Consequently at a given CPU frequency the maximum possible nominal baud rate LPRMIN should be chosen with respect to the maximum tolerated deviation given by the equation DTRA 1 2 UARTDIVMIN DTCL lt 3 75 Example A nominal baud rate of 20 Kbits s at TCPU 125 ns 8 MHz leads to UARTDIVNOM 25d UARTDIVMIN 25 0 15 25 21 25 DQUANT 1 2 UARTDIVMIN 0 001596 Figure 138 Bit sampling in reception mode RDI LINE sampled values Boe dod ws do XR WE EE dt bh I 6 16 gt 4 7 16 gt 4 7 16 gt One bit time 4 22 4 4 LIN mode selection Table 58 LIN mode selection LINE LSLV LASE Meaning 0 LIN mode disabled LIN Master Mode 0 LIN Slave Mode 1 with Automatic resynchronization disabled 1 LIN Slave Mode with Automatic resynchronization enabled Ly DoclD14587 Rev 12 355 462 Universal asynchronous receiver transmitter UART 0016 22 5 UART low power modes Table 59 UART interface behavior in low power modes Mode Description No effect on UART Wait UART interrupts cause t
117. Event interrupt enable 0 Event interrupt disabled 1 Event interrupt enabled This interrupt is generated when SB 1 Master ADDR 1 Master Slave ADD10 1 Master STOPF 1 Slave 1 with no or RXNE event TXE event to 1 if ITBUFEN 1 RXNE event to 1if ITBUFEN 1 WUFH 1 asynchronous interrupt to wakeup from Halt ITERREN Error interrupt enable 0 Error interrupt disabled 1 Error interrupt enabled This interrupt is generated when BERR 1 ARLO 1 AF 1 OVR 1 DoclD14587 Rev 12 309 595 Inter integrated circuit PC interface RM0016 21 7 11 Clock control register low 2 CCRL Address offset 0x02 Reset value 0 0 7 6 5 4 3 0 CCR 7 0 rw Bits 7 0 CCR 7 0 Clock control register Master mode 310 595 Controls the SCLH clock in Master mode Standard mode Period I2C 2 CCR tMASTER thigh CCR tuaster tlow CCR tyAsTER Fast mode If DUTY 0 Period I2C 3 CCR tMASTER thigh CCR tmaster tow 2 CCR tuaster If DUTY 1 to reach 400 kHz Period I2C 225 CCR tMASTER thigh 9 CCR taster liy 16 CCR MASTER Note 1 faster MAsTER IS the input clock to the peripheral configured using clock control register The minimum allowed value is 04h except in FAST DUTY mode where the minimum allowed value is 0x01 thigh l scL lwiscLH See de
118. Flag is set if the channel crosses the programmed thresholds Flag is set at the end of An interrupt is each conversion and an Yes no generated but continuous conversion is not stopped interrupt is generated 1 BSIZE Data buffer size 8 or 10 depending on the product 432 462 DoclD14587 Rev 12 d RM0016 Analog digital converter ADC Table 75 ADC interrupts in buffered continuous mode ADC1 Enable bits Status flags Exit Exit from from 8 AWSx AWD EOC Wait Halt ul Don t The flag is set at the end 0 of BSIZE conversions No is 0 The flag is set at the end 0 Don t 1 0 of BSIZE conversions Yes No care and an interrupt is generated The flag is set at the end 1 0 0 of BSIZE conversions if No No at least one of the AWSXx bits is set The flag is set and The flag is set at the end the end of BSIZE Data Buffer Full 1 1 0 conversions if at least Yes No one of the AWSx bits is Flag is set if conversion set Continuous on buffer x crosses the conversion is not thresholds programmed stopped in the ADC_HTR and The flag is set at the end The flag is set at the end ADC_LTR registers of BSIZE conversions if of BSIZE conversions 1 0 1 Yes No at least one of the and an interrupt is AWSx bits is set generated The flag is set immediately as soon as one of the AWSx bits is The flag is setat the en
119. Flash program memory and data EEPROM Figure 11 UBC area size definition on high density STM8S and STM8AF with up to 128 Kbytes of Flash program memory 0x00 8000 Interrupt vector table 1 0x00 807F Page 0 1 0 00 8200 512 bytes Page 1 ot 0x00 8400 a 512 bytes Page 2 E 0x00 8600 Q 512 bytes Page 3 T 0 00 8800 aos he Qa 2 Uo 1K to 128 Kbytes User boot code area No og 2 0x02 7800 512 bytes Page 252 0x02 7A00 512 bytes Page 253 0x02 7C00 512 bytes Page 254 0x02 7 00 12 Page 255 0x02 7FFF oie bytes mem 1 UBC 7 0 0x00 means no user boot code area is defined Refer to the datasheets for the description of the UBC option byte 2 The first 2 pages 1 Kbytes contain the interrupt vectors of which only 128 bytes 32 IT vectors are used 4 4 4 Data EEPROM DATA The data EEPROM area can be used to store application data By default the DATA area is write protected to prevent unintentional modification when the main program is updated in IAP mode The write protection can be unlocked only by using a specific MASS key sequence refer to Enabling write access to the DATA area Refer to Section 4 4 Memory organization for the size of the DATA area 4 4 5 Main program area The main program is the part of the Flash program memory which is used to store the application code see Figure 6 Figure 7 and Figure 8 4 4 6 Option bytes
120. Master ADD10 ITEV TEN Stop received Slave STOPF Data byte transfer finished BTF Wakeup from Halt WUFH ITEVTEN Yes Yes Receive buffer not empty RXNE ITEVTEN and Transmit buffer empty TXE ITBUFEN Bus error BERR No Arbitration loss Master ARLO ITERREN Acknowledge failure AF Overrun underrun OVR DoclD14587 Rev 12 d RM0016 Inter integrated circuit PC interface 3 Figure 109 2 interrupt mapping diagram SB ITEVTEN ADDR ADD10 STOPF WUFH BTF it event ITBUFEN e9 RXNE ITERREN BERR ARLO it error AF OVR 12C global interrupt DoclD14587 Rev 12 299 595 Inter integrated circuit 2 interface 0016 217 I C registers 21 7 1 Control register 1 2 CR1 Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 NOSTRETCH ENGC Reserved PE rw rw r rw Bit 7 NOSTRETCH Clock stretching disable Slave mode This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set until it is reset by software 0 Clock stretching enabled 1 Clock stretching disabled Bit6 ENGC General call enable 0 General call disabled Address 0x00 is NACKed 1 General call enabled Address 0x00 is ACKed Bits 5 1 Reserved Bit
121. Note This bit has no effect on true open arain ports refer to pin marked T in datasheet pin description table DoclD14587 Rev 12 111 595 General purpose ports GPIO 0016 11 9 5 Port x control register 2 Px CR2 Address offset 0x04 Reset value 0x00 7 6 5 4 3 2 1 0 C27 C26 C25 C24 C22 C21 C20 rw rw rw rw rw rw rw rw Bits 7 0 C2 7 0 Control bits These bits are set and cleared by software They select different functions in input mode and output mode In input mode the CR2 bit enables the interrupt capability if available If the does not have interrupt capability setting the CR2 bit has no effect In output mode setting the bit increases the speed of the This applies to ports with and O4 output types see pin description table In input mode DDR 0 0 External interrupt disabled 1 External interrupt enabled n output mode DDR 1 0 Output speed up to 2 MHz 1 Output speed up to 10 MHz 11 9 6 GPIO register map and reset values Each GPIO port has five registers mapped as shown in Table 24 Refer to the register map in the corresponding datasheet for the base address for each port Note At reset state all ports are input floating Exceptions are indicated in the pin description table of the corresponding datasheet Table 24 GPIO register map Address Register 7 6 5 4 3 2 1 0 offset name Px ODR ODR7 ODR6 ODRS5 OD
122. Refer to the option byte description in the datasheet DoclD14587 Rev 12 123 595 Independent watchdog IWDG 0016 124 595 Timeout period The timeout period be configured through the IWDG IWDG registers It is determined by the following equation T22xTjg xPxR where T Timeout period Tisi 1 figi _ 2 2 0 2 R RLR 7 0 1 The IWDG counter must be refreshed by software before this timeout period expires Otherwise an IWDG reset will be generated after the following delay has elapsed since the last refresh operation D T 6xTig where D delay between the last refresh operation and the IWDG reset Table 28 Watchdog timeout period LSI clock frequency 128 kHz Timeout Prescaler divider PR 2 0 bits RL 7 0 0x00 RL 7 0 OxFF 4 0 62 5 us 15 90 ms 8 1 125 us 31 90 ms A6 2 250 us 63 70 ms 32 3 500 us 127 ms 64 4 1 00 ms 255 ms 128 5 2 00 ms 510 ms 256 6 4 00 ms 1 025 d DoclD14587 Rev 12 RM0016 Independent watchdog IWDG 14 3 14 3 1 IWDG registers Key register IWDG_KR Address offset 0x00 Reset value 0 7 0 w Bits 7 0 14 3 2 KEY 7 0 Key value The KEY_REFRESH value must be written by software at regular intervals otherwise the watchdog generates an MCU reset when the counter reaches 0 If the IWDG is not enabled by option byte see datasheet for
123. SPI speed 10 MHz NSS management by hardware or software for both master and slave Programmable clock polarity and phase Programmable data order with MSB first or LSB first shifting Dedicated transmission and reception flags with interrupt capability SPI bus busy status flag Master mode fault and overrun flags with interrupt capability Hardware CRC feature for reliable communication CRC value can be transmitted as last byte in Tx mode CRC error checking for last received byte Wakeup capability The MCU wakes up from Low power mode in full or half duplex transmit only modes DoclD14587 Rev 12 257 595 Serial peripheral interface SPI 0016 20 3 SPI functional description 20 3 1 General description The block diagram of the SPI is shown in Figure 91 Figure 91 SPI block diagram ADDRESS AND DATA BUS ZN READ RX BUFFER MOSI A ERR SHIFT REGISTER THE RXIE E WKE o jojo o 47 SBFirst T MOD wk VR TX BUFFER Bev Ove ERR Up WRITE COMMUNICATION f CONTROL MASTER BAUD RATE GENERATOR BR 2 0 i LSB pinsy SPE BR2 BR1 BRO MSTRICPOLICPHA Y L MASTER CONTROL LOGIC BIDI Bipi RC CRC 9 Rx
124. Section 22 on page 315 Updated CAN filter and external clock description in Section 23 on page 373 Renamed ADC to ADC1 and ADC2 in Section 24 on page 423 Updated Continuous scan mode on page 428 Updated Conversion on external trigger on page 430 Updated Section 4 Flash program memory and data EEPROM Changed name of SWUAH bit to REGAH in Section 9 9 1 Internal clock register CLK_ICKR on page 89 Modified LSI frequency measurement in Section 11 1 on page 104 Modified Peripheral clock gating register 1 1 on 22 Sep 2008 3 page 94 Modified Section 11 8 2 Slope control on page 109 Added description of TIM5 TIM6 in Section 16 Timer overview Section 18 16 bit general purpose timers TIM2 TIM3 TIM5 and Section 19 8 bit basic timer TIM4 TIM6 Updated Section 24 5 6 Analog watchdog 2 450 462 DoclD14587 Rev 12 0016 Revision history Table 79 Document revision history continued Date Revision Changes Removed memory and register map information transferred to datasheets Register absolute addresses replaced by offsets refer now to register map in datasheet for the base addresses Added Note related to TLI interrupt in Section 6 2 1 on page 59 Added TLI in Section 6 5 Concurrent and nested interrupt management Updated Flash program density to 32 128 Kbytes for high density STM8S devices in Section 4 Flash program memory and data EEPROM Updated size
125. Separate CRC calculators are implemented for transmitted data and received data The CRC is calculated using a programmable polynomial serially on each bit The CRC is calculated on the sampling clock edge defined by the and CPOL bits in the SPI CR1 register CRC calculation is enabled by setting the CRCEN bit in the SPI CR1 register This action resets the CRC registers SPI RXCRCR and SPI TXCRCR When the CRCNEXT bit in SPI CR2 is set the SPI TXCRCR value is transmitted at the end of the current byte transmission If a byte is present in the Tx buffer the CRC value is transmitted only after the transmission of this byte During the transmission of CRC the CRC calculator is switched off and the register value remains unchanged The CRCERR flag in the SPI SR register is set if the value received in the shift register during the SPI TXCRCR value transmission does not match the SPI RXCRCR value 3 DoclD14587 Rev 12 0016 Serial peripheral interface SPI SPI communication using CRC is possible through the following procedure e Program the CPOL CPHA LSBfirst BR SSM SSI and MSTR values e Program the polynomial in the SPI CRCPR register e Enable the CRC calculation by setting the CRCEN bit in the CR1 register This also clears the SPI RXCRCR and SPI TXCRCR registers e Enable the SPI by setting the SPE bit in SPI 1 e Start the communication and sustain the communication until all but one byte has been tran
126. TIF Write 0 d DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 Note d Example 2 As in the previous example both counters can be initialized before starting to count Figure 59 shows the behavior with the same configuration as in Figure 57 but in trigger standard mode instead of trigger gated mode SMS 110 in the TIM1 SMCR register Figure 59 Triggering timer B with counter enable CNT EN of timer A was UU UU UU UU UU UU UU UU UU Timer A CEN CNT_EN Timer A UG TimerA CNT 78 Y 00 Y o y 02 Timer B CNT CD E7 X es X E9 EA Timer B UG Timer B write CNT Timer B TIF Write TIF 0 Starting 2 timers synchronously in response to an external trigger Example The enable of timer A is set when its TI1 input rises and the enable of timer B is set with the enable of timer A refer to Figure 55 for connections To ensure the counters alignment timer A must be configured in master slave mode slave with respect to Tl1 master with respect to timer B 1 Configure timer A master mode to send its enable as trigger output MMS 001 in the CR2 register 2 Configure timer A slave mode to get the input trigger from TI1 TS 100 in the TIMx SMCR register 3 Configure timer A in trigger mode SMS 110 in the TIMx SMCR register 4 Configure timer A in m
127. Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 18 462 2 interface behavior in low power modes 298 2 Interrupt 298 2 CCR values for SCL frequency table MASTER 10 MHz or 16 2 312 IC register Map ERIT TE TR TTE EET TR 314 UART configurations lt eesse res I 3 315 Noise detection from sampled data 330 Baud rate programming and error calculation 332 UART receiver tolerance when DIV 3 0 is 2 332 UART receiver s tolerance when UART_DIV 3 0 is different from zero 333 Frame Tormmal iuc cedere Ur Marea P deg E RR pa PE Mee uuu 333 LIN mode 1 355 UART interface behavior in low power 356 UART interrupt 356 UART1 register 370 UART2 register 370 UARTS register 371 UART
128. Table 67 Reset value OxXX 7 6 5 4 3 2 1 0 TIME 7 0 r r r r r r r r Bits 7 0 TIME 7 0 Message time stamp low This field contains the low byte of the 16 bit timer value captured at the SOF detection CAN mailbox time stamp register high CAN MTSRH Address offset See Table 66 and Table 67 Reset value OxXX 7 6 5 4 3 2 1 0 TIME 15 8 Bits 7 0 412 462 TIME 15 8 Message time stamp high This field contains the high byte of the 16 bit timer value captured at the SOF detection 2 DoclD14587 Rev 12 RM0016 Controller area network beCAN 23 11 16 CAN filter registers filter mode register 1 CAN_FMR1 Address offset See Table 71 Reset value 0x00 FML3 FMH2 FML2 FMH1 FML1 FMHO FMLO rw rw rw rw rw rw rw Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2 Bit 1 Bit 0 d FMH3 Filter 3 mode high Mode of the high identifier mask registers of Filter 3 0 High registers are in mask mode 1 High registers are in identifier list mode FML3 Filter 3 mode low Mode of the low identifier mask registers of Filter 3 0 Low registers are in mask mode 1 Low registers are in identifier list mode FMH2 Filter 2 mode high Mode of the high identifier mask registers of Filter 2 0 High registers are in mask mode 1 High registers are in identifier list mode FML2 Filter 2 mode low Mode of the low identifier mask registers of Filter 2 0 Low
129. UART SR sintiera nehi esaa m sse Ri 358 WWDG 131 WWDG 132 d DoclD14587 Rev 12 461 462 RM0016 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 462 462 DoclD14587 Rev 12 2
130. and the receiver are disabled TEN REN 0 to ensure that the clock pulses function correctly These bits should not be changed while the transmitter or the receiver is enabled It is recommended to set TE and RE are set in the same instruction in order to minimize the setup and the hold time of the receiver The UART supports master mode only it cannot receive or send data related to an input clock SCLK is always an output The data given in this section apply only when the UART DIV 3 0 bits in the UART BRR2 register are kept at 0 Else the setup and hold times are not 1 16 of a bit time but 4 16 of a bit time This option allows to serially control peripherals which consist of shift registers without losing any functions of the asynchronous communication which can still talk to other asynchronous transmitters and receivers 3 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART d Figure 122 UART example of synchronous transmission RX j Data out TX 9 Data in UART Synchronous device for example slave SPI SCLK M Clock Figure 123 UART data clock timing diagram 0 Clock CPOL 0 CPHA QP Clock CPOL 0 CPHA 1 Clock CPOL 1 0 Clock CPOL 1 CPHA 1 Idle or precedin Idle or next transmission 9 Start M 0 8 data bits Stop transmission gi
131. at startup with the content of the UBC option byte Refer to the datasheets for the protected pages according to the bit values 4 8 5 Flash protection register FLASH_NFPR Address offset 0x04 Reset value OxFF 7 6 5 4 3 2 1 0 NWPB5 NWPB4 NWPB3 NWPB2 NWPB1 NWPBO Reserved ro ro ro ro ro ro Bits 7 6 Reserved Bits 5 0 WPB 5 0 User boot code area protection bits These bits show the size of the boot code area They reflect the content of the NUBC option byte Refer o the datasheet for the protected pages according to the bit values 4 8 6 Flash program memory unprotecting key register FLASH PUKR Address offset 0x08 Reset value 0x00 6 5 4 3 2 1 0 MASS PRG KEYS rw Bits 7 0 PUK 7 0 Main program memory unlock keys This byte is written by software all modes It returns 0 00 when read Refer to Enabling write access to the main program memory on page 44 for the description of main program area write unprotection mechanism d 54 595 DoclD14587 Rev 12 0016 Flash program memory and data EEPROM 4 8 7 Data EEPROM unprotection key register FLASH DUKR Address offset 0x0A Reset value 0x00 7 6 5 4 3 2 1 0 MASS_DATA KEYS rw Bits 7 0 DUK 7 0 Data EEPROM write unlock keys This byte is written by software all modes It returns 0x00 when read Refer to Enabling write access to the DATA area on page 45 for the description of main p
132. automatically into the recessive state when a main clock failure occurs so that the CAN network does not get stuck by the device However to ensure this the PGO I O pin must be configured in pull up mode prior to using the beCAN In this way when a failure occurs and the alternate function is disabled the line is pulled up instead of floating beCAN low power modes Table 68 beCAN behavior in low power modes Mode Description No effect beCAN except that accesses to Tx Rx mailboxes and filter values are not Wait possible CPU clock is stopped beCAN interrupts cause the device to exit from WAIT mode Slow No effect on beCAN BeCAN is halted If the beCAN has been successfully put in Sleep mode refer to Halt Active Section 23 4 3 before executing the halt instruction any falling edge detected on halt CAN RX pin will trigger a Rx interrupt and wake up the device from Halt Active halt mode If a CAN frame is received in Wait Halt or Active halt modes the microcontroller will be woken up but the CAN frame will be lost DoclD14587 Rev 12 395 462 Controller area network beCAN 0016 23 11 beCAN registers 23 11 1 CAN master control register CAN Address offset 0 00 Reset value 0x02 FA 6 5 4 3 2 1 0 AWUM NART RFLM TXFP SLEEP INRQ rw rw rw rw rw rw rw rw Bit 7 TTCM Time Triggered Communication Mode 0 Time Trigg
133. before data reception starts In this case to NACK the 2nd byte the ACK bit must be cleared just after ADDR is cleared Note Bit 2 ACK Acknowledge enable This bit is set and cleared by software and cleared by hardware when 0 0 No acknowledge returned 1 Acknowledge returned after a byte is received matched address or data Bit 1 STOP Stop generation The bit is set and cleared by software cleared by hardware when a Stop condition is detected set by hardware when a timeout error is detected n Master mode 0 No Stop generation 1 Stop generation after the current byte transfer or after the current Start condition is sent n Slave mode 0 No Stop generation 1 Release the SCL and SDA lines after the current byte transfer Bit START Start generation d This bit is set and cleared by software and cleared by hardware when start is sent or 0 n Master mode 0 No Start generation 1 Repeated start generation n Slave mode 0 No Start generation 1 Start generation when the bus is free DoclD14587 Rev 12 301 595 Inter integrated circuit 2 interface 0016 Note 21 7 3 When STOP or START is set the user must not perform any write access to 2 2 before the control bit is cleared by hardware Otherwise a second STOP or START request may occur Frequency register I2C FREQR Address offset 0x02 Reset value 0x00 Reserved FREQ 5 0 r rw
134. better to use TXE and RXNE flags instead Disabling the SPI When a transfer is terminated the application can stop the communication by disabling the SPI peripheral This is done by resetting the SPE bit For some configurations disabling the SPI and entering Halt mode while a transfer is on going can cause the current transfer to be corrupted and or it can happen that the BSY flag becomes unreliable DoclD14587 Rev 12 Ly RM0016 Serial peripheral interface SPI Note 2 To avoid any of these effects it is recommended to respect the following procedure when disabling the SPI In master or slave full duplex mode BDM 0 RXONLY 0 Wait until RXNE 1 to receive the last data Wait until 1 Then wait until BSY 0 Disable the SPI SPE 0 and eventually enter Halt mode or disable the peripheral clock In master or slave unidirectional transmit only mode BDM 0 RXONLY 0 or bidirectional transmit mode BDM 1 1 After the last data is written in the SPI DR register 1 Wait until 1 2 Then wait until BSY 0 3 Disable the SPI SPE 0 and if desired enter Halt mode or disable the peripheral clock In master unidirectional receive only mode MSTR 1 BDM 0 RXONLY 1 or bidirectional receive mode MSTR 1 BDM 1 BDOE 0 This case must be managed in a particular way to ensure that the SPI does not initiate a new transfer 1 Wait for
135. boot code area ro E N hy Q 2 0x00 9F00 3 64 bytes Page 124 0x00 9F40 64 bytes Page 125 0x00 9F80 64 bytes Page 126 0X00 SEON 64 bytes Page 127 0x00 9FFF N number of protected pages UBC 7 0 2 UBC 7 0 0x00 means no user boot code area is defined Refer to the datasheets for the description of the UBC option byte 3 The first 2 pages 128 bytes contain the interrupt vectors DoclD14587 Rev 12 41 595 d Flash program memory and data EEPROM RM0016 42 595 Figure 10 UBC area size definition on medium density STM8S and STM8AF with up to 32 Kbytes of Flash program memory 0x00 8000 0x00 807F 0x00 8200 0x00 8400 0x00 8600 0x00 8800 0x00 F800 0x00 FA00 0x00 FC00 0x00 00 0x00 FFFF Interrupt vector table 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes Page 0 Page 1 Page 2 Page 3 Page 60 Page 61 Page 62 Page 63 UBC 7 0 0x01 1 Kbytes 0x02 2 Kbytes UBC 7 0 Ox3E 32 Kbytes UBC 7 0 1K to 32 Kbytes User boot code area N number of protected pages UBC 7 0 2 for UBC 7 0 gt 1 UBC 7 0 0 00 means no user boot code area is defined Refer to the datasheets for the description of the UBC option byte The first 2 pages 1 Kbytes contain the 128 bytes of interrupt vectors 32 IT vectors DoclD14587 Rev 12 d 0016
136. by hardware It indicates that the CCO clock is being output 0 CCO clock not available 1 CCO clock available Bits 4 1 CCOSEL 3 0 Configurable clock output selection These bits are written by software to select the source of the output clock available on the CLK_CCO pin They are write protected when CCOBSY is set 0000 fusipiv 0001 0010 fuse 0011 Reserved 0100 0101 fopy 2 0110 fopu 4 0111 fopy 8 1000 16 1001 fopy 32 1010 fopy 64 1011 fusi 1100 fuAsTER 1101 fopu 1110 fopu 1111 Bit CCOEN Configurable clock output enable d This bit is set and cleared by software 0 CCO clock output disabled 1 CCO clock output enabled DoclD14587 Rev 12 97 462 Clock control CLK 0016 9 9 11 HSI clock calibration trimming register CLK HSITRIMR Address offset 0 0 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved HSITRIM 3 0 r rw rw rw rw Bits 7 4 Reserved must be kept cleared Bits 3 0 HSITRIM 3 0 HSI trimming value These bits are written by software to fine tune the HSI calibration Note In high density STM8S and 5 devices only bits 2 0 are available In other devices bits 3 0 are available to achieve a better HSI resolution Compatibility with bits 2 0 can be selected through options bytes refer to datasheet 9 9 12 SWIM clock control register SWIMCCR Address offset 0 00 Reset value ODXXXX
137. by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bits 6 0 T 6 0 7 bit counter MSB to LSB These bits contain the value of the watchdog counter It is decremented every 12288 fcpy cycles approximately A reset is produced when it rolls over from 0x40 to Ox3F T6 becomes cleared 1 This bit is not used if the hardware watchdog option is enabled by option byte d DoclD14587 Rev 12 131 595 Window watchdog WWDG RM0016 15 9 2 Window register WWDG_WR Address offset 0x01 Reset value Ox7F 7 6 5 4 3 2 1 0 w6 w5 w4 w3 w2 w1 WO Reserved rw rw rw rw rw rw rw Bit 7 Reserved Bits 6 0 W 6 0 7 bit window value These bits contain the window value to be compared to the downcounter 15 10 Window watchdog register map and reset values Table 32 WWDG register map and reset values Address Register 7 6 5 4 3 2 1 0 offset name 0x00 WWDG_CR WDGA T6 T5 T4 T3 T2 Ti TO Reset value 0 1 1 1 1 1 1 1 oxi WWDG WR w6 w5 WA W3 w2 w1 WO Reset value 0 1 1 1 1 1 1 1 132 595 DoclD14587 Rev 12 d RM0016 Timer overview 16 Timer overview The devices in the STM8S and STM8AF family may be equipped with up to three different timer types Advanced control TIM1 general purpose 2 5 and basic timers TIM4 TIM6 The timers share the same architecture but
138. by reading SR1 register followed by reading SR3 EV2 RXNE 1 cleared by reading DR register EV4 STOPF 1 cleared by reading SR1 register followed by writing CR2 register EV1 event stretches SCL low until the end of the corresponding software sequence EV2 software sequence must be performed before the end of the current byte transfer After checking the SR1 register content the user should perform the complete clearing sequence for each flag found set Thus for the ADDR and STOPF flags the following sequence is recommended inside the I2C interrupt routine READ SR1 if ADDR 1 READ SR1 READ SR3 if STOPF 1 READ SR1 WRITE CR2 The purpose is to make sure that both ADDR and STOPF flags are cleared if both are found set 5 See also Note 8 on page 306 Closing slave communication After the last data byte is transferred a Stop condition is generated by the master The interface detects this condition and sets the STOPF bit and generates an interrupt if the ITEVTEN bit is set STOPF is cleared by a read of the SR1 register followed by a write to the CR2 register see Figure 104 I C master mode In Master mode the 2 interface initiates a data transfer and generates the clock signal A serial data transfer always begins with a Start condition and ends with a Stop condition Master mode is selected as soon as the Start condition is generated on the bus with a START bit The following is the required sequence i
139. by software to control the output waveform provided that the preload registers are not enabled 0 Otherwise the TIMx CCRi shadow registers are updated only at the next UEV see example in Figure 69 Figure 69 Output compare mode toggle on OC1 Write B201h in the CC1R register CNT 0039 003A X 0038 B200 X 2 1 Y TIMx CCR1 003A B201 OC1REF OC1 ict nm dd Match detected on OCR1 Interrupt generated if enabled DoclD14587 Rev 12 171 595 16 bit advanced control timer TIM1 0016 17 5 7 172 595 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIM1 ARR register and a duty cycle determined by the value of the TIM1 CCRi registers The PWM mode can be selected independently on each channel one PWM per OC output by writing 110 PWM mode 1 or 111 PWM mode 2 in the OCM bits in the CCMRi registers The corresponding preload register must be enabled by setting the OC PE bits in the TIM1_CCMRi registers The auto reload preload register in up counting or center aligned modes may be optionally enabled by setting the ARPE bit in the TIM1_CR1 register As the preload registers are transferred to the shadow registers only when an UEV occurs all registers have to be initialized by setting the UG bit in the TIM1_EGR register before starting the counter OCi polarity is software programmable u
140. clearing the INRQ bit in the CAN MCR register Afterwards the beCAN is synchronized with the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits Bus Idle state before finishing the switch to Normal mode and being ready to take part in bus activities The switch completion is confirmed by hardware by clearing the INAK bit in the CAN MSR register The initialization of the filter values is independent from Initialization mode but must be done while the filter bank is not active corresponding FACTx bit cleared The filter bank scale and mode configuration must be configured in initialization mode Sleep mode low power To reduce power consumption has a low power mode called Sleep mode This mode is entered on software request by setting the SLEEP bit in the CAN MCR register In this mode the beCAN clock is stopped however software can still access the beCAN mailboxes If software requests entry to initialization mode by setting the bit while beCAN is in sleep mode it must also clear the SLEEP bit beCAN can be woken up exit Sleep mode either by software clearing the SLEEP bit or on detection of CAN bus activity On CAN bus activity detection hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN MCR register is set If the AWUM bit is cleared software has to clear the SLEEP bit when a wakeup interrupt occurs
141. clock stretching is disabled and the 2 interface is transmitting data The interface has not updated the DR with the next byte TXE 1 before the clock comes for the next byte In this case e The same byte in the DR register will be sent again e user should make sure that data received on the receiver side during an underrun error is discarded and that the next bytes are written within the clock low time specified in the I C bus standard e For the first byte to be transmitted the DR must be written after ADDR is cleared and before the first SCL rising edge If it is not possible the receiver must discard the first data SDA SCL line control e clock stretching is enabled Transmitter mode If 1 and 1 the interface holds the clock line low before transmission to wait for the microcontroller to read SR1 and then write the byte in the Data register both buffer and shift register are empty Receiver mode If RXNE 1 and 1 the interface holds the clock line low after reception to wait for the microcontroller to read SR1 and then read the byte in the Data Register or write to CR2 both buffer and shift register are full e f clock stretching is disabled in Slave mode Overrun error in case of RXNE 1 and no read of DR has been done before the next byte is received The last received byte is lost Underrun error in case 1 and no write into DR has been done before
142. e The buffer of the prescaler is reloaded with the preload value content of the TIM1 PSCR register e auto reload shadow register is updated with the preload value content of the TIM1 ARR register Note that the auto reload is updated before the counter is reloaded so that the next period is the expected one Figure 38 and Figure 39 show some examples of the counter behavior for different clock frequencies when TIM1 ARR 0x36 In downcounting mode preload is not normally used Consequently the new value is taken into account in the next period see Figure 36 3 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 2 Figure 38 Counter update when ARPE 0 ARR not preloaded with prescaler 2 CK PSC CNT EN TIMER CLOCK CK CONT COUNTER REGISTER COUNTER UNDERFLOW UPDATE EVENT UEV UPDATE INTERRUPT FLAG UIF AUTO RELOAD PRELOAD REGISTER AUTO RELOAD SHADOW REGISTER iugum 06 Josjo4Jos o2 o oofa6 35 s4 33 Ja2 Ja1 JaoJ2F FF 36 Write a new value in TIMx ARR Figure 39 Counter update when ARPE 1 ARR preloaded with prescaler 1 New value transferred immediately in shadow register CK PSC _ TIMER CLOCK ONT COUNTER REGISTER COUNTER UNDERFLOW UPDATE EVENT UEV UPDATE INTERRUPT FLAG UIF
143. event It is cleared by software 0 No update has occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow or underflow if UDIS 0 in the TIM1 CR1 register When CNT is re initialized by software using the UG bit in TIM1 register if URS 0 and UDIS 0 in the TIM1 CR1 register When CNT is re initialized by a trigger event refer to the TIM1 register description if URS 0 and UDIS 0 in the TIM1 CR 1 register 17 7 7 Status register 2 TIM1 SR2 Address offset 0x06 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved CC30F 2 CC1OF Reserved r rc wO rc wO rc wO rc wO r Bits 7 5 Reserved must be kept cleared Bit 4 CCAOF Capture compare 4 overcapture flag Refer to CC1OF description Bit 3 CC3OF Capture compare 3 overcapture flag Refer to description 3 194 595 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 Bit 2 Bit 1 Bit 0 17 7 8 CC20F Capture compare 2 overcapture flag Refer to CC1OF description CC10F Capture compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode It is cleared by software by writing it to O 0 No overcapture has been detected 1 The counter value has been captured in TIM1 CCR 1 register while CC1IF flag was already set Reserved must be kept cleared Event ge
144. following figure Figure 100 2 bus protocol ACK 8 9 START STOP CONDITION CONDITION Acknowledge may be enabled or disabled by software The I C interface addresses 7 10 bit and or general call address can be selected by software 2 DoclD14587 Rev 12 d RM0016 Inter integrated circuit PC interface The block diagram of the I C interface is shown in the following figure Figure 101 I C block diagram DATA REGISTER DATA SDA 4 CONTROL DATA SHIFT REGISTER COMPARATOR OWN ADDRESS REGISTERS CLOCK SCL 4 0 CONTROL CLOCK CONTROL REGISTER CCR CONTROL REGISTERS CR1 amp CR2 STATUS REGISTERS OG LOGIC SR1 SR2 amp SR3 4 1 INTERRUPTS DoclD14587 Rev 12 285 595 Inter integrated circuit 2 interface 0016 21 4 21 4 1 Note 286 595 functional description By default the 2 interface operates in Slave mode To switch from default Slave mode to Master mode a Start condition generation is needed slave mode The peripheral input clock must be programmed in the 2 FREQR register in order to generate correct timings The peripheral input clock frequency must be at least e 1MHzin Standard mode 4MHzin Fast mode As soon as a start condition is detected the addre
145. for selected between normal and Low power IrDA mode 0 Normal mode 1 Low power mode Note This bit is not available for UARTS IREN IrDA mode Enable This bit is set and cleared by software 0 IrDA disabled 1 IrDA enabled Note This bit is not available for UARTS Reserved must be kept cleared DoclD14587 Rev 12 d RM0016 Universal asynchronous receiver transmitter UART 22 7 10 Control register 6 UART_CR6 Address offset 0x09 Reset value 0x00 6 3 2 LDUM Reserved LSLV LASE Reserved LHDIEN LHDF LSF r rw rw r rw rc_w0 rc wO Note Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bits 0 d This register is not available for UARTI1 LDUM LIN Divider Update Method 0 LDIV is updated as soon as BRR1 is written if no automatic resynchronization update occurs at the same time 1 LDIV is updated at the next received character when RXNE 1 after a write to the BRR1 register LDIV is coded using the two register BRR1 and BRR2 This bit is reset by hardware once LDIV is updated with the measured baud rate at the end of the synch field Reserved LSLV LIN Slave Enable 0 LIN Master Mode 1 LIN Slave Mode LASE LIN automatic resynchronisation enable 0 LIN automatic resynchronization disabled 1 LIN automatic resynchronization enabled Reserved LHDIEN LIN Header Detection Interrupt Enable Header
146. from the clock trigger mode controller Bit 0 CEN Counter enable 0 Counter disabled 1 Counter enabled Note External clock trigger gated mode and encoder mode can work only if the CEN bit has been previously set by software However trigger mode can set the CEN bit automatically by hardware 3 DoclD14587 Rev 12 187 595 16 bit advanced control timer TIM1 0016 17 7 2 Control register 2 TIM1 CR2 Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved MMS 2 0 COMS CCPC Reserved Reserved r rw rw rw rw rw Bit7 Reserved Bits 6 4 MMS 2 0 Master mode selection Bit3 Bit 2 Bit 1 Bit 0 188 595 These bits select the information to be sent in master mode to the ADC or to the other timers for synchronization TRGO The combination is as follows 000 Reset The UG bit from the TIM1_EGR register is used as trigger output TRGO If the reset is generated by the trigger input clock trigger mode controller configured in reset mode the signal on TRGO is delayed compared to the actual reset 001 Enable The counter enable signal is used as trigger output TRGO It is used to start several timers or the ADC to control a window in which a slave timer or the ADC is enabled The counter enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in trigger gated mode When the counter enable signal is controlled by the
147. gt 8 CCiF OCiREF 0 0 Down counting configuration Down counting is active when the DIR bit in the TIM1 CR1 register is high Refer to Down counting mode on page 144 In PWM mode 1 the reference signal OC REF is low as long as TIM1 gt TIM1_CCRi Otherwise it becomes high If the compare value in the TIM1 CCRiregisters is greater than the auto reload value in the TIM1 ARR register OCiREF is held at 1 Zero percent PWM is not possible in this mode PWM center aligned mode Center aligned mode is active when the CMS bits in the TIM1 CR1 register are different from 00 all the remaining configurations have the same effect on the OC REF OCi signals The compare flag is set when the counter counts up down or up and down depending on the CMS bits configuration The direction bit DIR in the TIM1_CR1 register is updated by hardware and is read only in this mode refer to Center aligned mode up down counting on page 146 Figure 71 shows some center aligned PWM waveforms in an example where e 1 ARR 8 e PWM mode is PWM mode 1 e The flag is set arrow symbol in Figure 71 in three different cases When the counter counts down CMS 01 When the counter counts up CMS 10 When the counter counts up and down CMS 11 DoclD14587 Rev 12 173 595 16 bit advanced control timer TIM1 RM0016 174 595 Figure 71 Center aligned PWM waveforms ARR
148. has TXOK 0 highest priority ABRO 1 TME 0 Mailbox does not have highest priority CAN Bus IDLE Transmit failed NART 1 TRANSMIT RQCP 0 Transmit failed NART 0 Transmit succeeded DoclD14587 Rev 12 381 462 Controller area network beCAN 0016 23 6 2 382 462 Reception handling For the reception of CAN messages three mailboxes organized as a FIFO are provided In order to save CPU load simplify the software and guarantee data consistency the FIFO is managed completely by hardware The application accesses the messages stored in the FIFO through the FIFO output mailbox Valid message A received message is considered as valid when it has been received correctly according to the CAN protocol no error until the last but one bit of the EOF field and It passed through the identifier filtering successfully see Section 23 6 3 Identifier filtering Figure 147 Receive FIFO states Valid Message p PENDING 1 Release FMP 01b Mailbox FOVR 0 Release Valid Message Mailbox Received RFOM 1 PENDING 2 FMP 10b FOVR 0 Release Valid Message Mailbox Received RFOM 1 PENDING 3 FMP 11b Valid Message FOVR 0 OVERRUN Release FMP 11b Mailbox FOVR 1 RFOM 1 Valid Message Received FIFO management Starting from the empty state the first valid message received is stored in the FIFO which
149. high These bits are set reset by hardware and are read only When the ADC is in buffered continuous or scan mode they contain the high part of the converted data The data is in right aligned or left aligned format depending on the ALIGN bit Left Data Alignment These bits contain the eight MSB bits of the converted data Right Data Alignment These bits contain the eight ADC data width MSB bits of the converted data Remaining bits are tied to zero See Figure 164 d DoclD14587 Rev 12 RM0016 Analog digital converter ADC 24 11 2 ADC data buffer register x low ADC_DBxRL x or O 7 or 0 9 Address offset 0x01 2 channel number Reset value 0x00 7 6 5 4 3 2 1 0 DBL 7 0 r r r r r r r r Note Data buffer registers are not available for ADC2 The data buffer size and base address 3 device dependent are specified in the corresponding datasheet Note that the data buffer registers and the other ADC registers have different base addresses Bits 7 0 DBL 7 0 Data bits low These bits are set reset by hardware and are read only When the ADC is in buffered continuous or scan mode they contain the low part of the A D conversion result in right aligned or left aligned format depending on the ALIGN bit Left Data Alignment These bits contain the eight ADC data width LSB bits of the converted data Remaining bits of the register are tied to zero See Figure 165 Right D
150. i tovaidate 1 0 X 0 X 0 X 0 00 0 X X X X X X the start bit oN Falling edge At least 2 bits At least 2 bits detection out of 3 at 0 out of 3 at 0 ai15471b Note If the sequence is not complete the start bit detection aborts and the receiver returns to the 2 idle state no flag is set where it waits for a falling edge If only 2 out of the 3 bits are at 0 sampling on the 372 5 7 pits or sampling on the 8 9th and 10 bits the start bit is validated but the NF noise flag bit is set The start bit is confirmed if the last 3 samples are at 0 sampling on the 87 9 ang 1017 bits Character reception During an UART reception data shifts in least significant bit first through the pin In this mode the UART DR register consists of a buffer RDR between the internal bus and the received shift register see Figure 2 Procedure 1 Program the M bit in UART_CR1 to define the word length 2 Program the number of stop bits in UART CR3 3 Select the desired baud rate by programming the baud rate registers in the following order a UART BRR2 b UART 1 4 Setthe REN bit UART CR2 This enables the receiver which begins searching for a start bit DoclD14587 Rev 12 327 462 Universal asynchronous receiver transmitter UART 0016 Note 328 462 When a character is received e The RXNE bit is set It indicates that the content of the shift register is transferred
151. in order to exit from sleep mode If the wakeup interrupt is enabled WKUIE bit set in CAN IER register a wakeup interrupt will be generated on detection of CAN bus activity even if the automatically performs the wakeup sequence After the SLEEP bit has been cleared Sleep mode is exited once beCAN has synchronized with the CAN bus refer to Figure 142 beCAN operating modes However the Rx line has to be in recessive state to leave this mode Sleep mode is exited once the SLAK bit has been cleared by hardware Time triggered communication mode The Time Triggered Communication Mode in CAN bit has to be set to enable the Time Triggered Communication mechanism In this mode the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN MTSRH and CAN MTSRL registers for Rx and Tx mailboxes The internal counter is captured on the sample point of the Start Of Frame bit in both reception and transmission The TGT bit Transmit Global Time in CAN MDLCR enables automatic transmission of the contents of both CAN MTSRH and CAN MTSRL in the two last data bytes of the message refer to the TTCAN specification ISO 11898 4 DoclD14587 Rev 12 377 462 Controller area network beCAN 0016 23 5 23 5 1 23 5 2 378 462 Test modes Test modes be selected by the SILM and LBKM bits in the CAN register These bits must be configured wh
152. in this mode Encoder mode and external clock mode 2 are not compatible and must not be selected together In encoder interface mode the counter is modified automatically depending on the speed and the direction of the incremental encoder The content of the counter therefore always represents the encoder s position The count direction corresponds to the rotation direction of the connected sensor Table 37 summarizes the possible combinations of counting directions and encoder signals assuming that 1 and TI2 do not switch at the same time Table 37 Counting direction versus encoder signals Level on opposite THFP1 signal TI2FP2 signal signal nene Rising Falling Rising Falling Counting on High Down Up No count No count TH only Low Up Down No count No count Counting on High No count No count Up Down TI2 only Low No count No count Down Up Counting on High Down Up Up Down both TI1 and Low Up Down Down Up An external incremental encoder can be connected directly to the MCU without external interface logic However comparators are normally used to convert the encoder s differential outputs to digital signals This greatly increases noise immunity The third encoder output which indicates the mechanical zero position may be connected to an external interrupt input and trigger a counter reset DoclD14587 Rev 12 183 595 16 bit advanced control timer TIM1 0016 184 595
153. integrated circuit PC interface 21 7 8 Status register 2 2 SR2 Address offset 0x08 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved WUFH Reserved OVR AF ARLO BERR r rc wO r rc wO rc wO rc 0 rc wO Bits 7 6 Reserved 5 WUFH Wakeup from Halt 0 no wakeup from Halt mode 1 7 bit address or header match in Halt mode slave mode or Halt entered when in master mode Note This bit is set asynchronously in slave mode during HALT mode It is set only if ITEVTEN 1 cleared by software writing 0 or by hardware when 0 Bit 4 Reserved Bit 3 OVR Overrun underrun 0 No overrun underrun 1 Overrun or underrun Set by hardware in slave mode when NOSTRETCH 1 and In reception when a new byte is received including ACK pulse and the DR register has not been read yet New received byte is lost In transmission when a new byte should be sent and the DR register has not been written yet The same byte is sent twice Cleared by software writing 0 or by hardware when 0 Note ifthe DR write occurs very close to the SCL rising edge the sent data is unspecified and a hold timing error occurs Bit 2 AF Acknowledge failure 0 No acknowledge failure 1 Acknowledge failure Set by hardware when no acknowledge is returned Cleared by software writing 0 or by hardware when PE 0 Bit 1 ARLO Arbitration lost master mode 0 No Arbitration lost detected 1 Arbitration lost detect
154. longer corresponds to the same captured value as the LS byte 17 5 1 Write sequence for 16 bit TIM1 CCRi registers 2 16 bit values are loaded in the TIM1 CCRi registers through preload registers This must be performed by two write instructions one for each byte The MS byte must be written first The shadow register update is blocked as soon as the MS byte has been written and stays blocked until the LS byte is written Do not use the LDW instruction as this writes the LS byte first and produces incorrect results in this case DoclD14587 Rev 12 165 595 16 bit advanced control timer TIM1 RM0016 17 5 2 166 595 Input stage Figure 63 Channel input stage block diagram TH THFP1 2 gt TRC TI2FP1 DP IC2 T2 Input Filter amp CH2 3 M TI2FP2 TRC Lp IC3 TIM1_cHg I 18 p EdgeDetector 4 p 4 Input Filter amp TIAFP3 HPN C4 EdgeDetecor TMFP4 a gt THF ED TRC to clock trigger controller to capture compare channels Figure 64 shows how the input stage samples the corresponding Tl input to generate filtered signal TI F Then an edge detector with polarity selection generates a signal which can be used as trigger input by t
155. message available The filter match index is stored in the CAN_MFMIR register The 16 bit time stamp value is stored in the CAN_MTSRH and CAN_MTSRL registers Table 67 Receive mailbox mapping Offset to Receive Mailbox base Register name address bytes 0 1 MDLCR 2 CAN MIDR1 3 CAN MIDR2 4 CAN MIDR3 5 MIDR4 6 CAN MDAR1 7 CAN MDAR2 8 CAN MDAR3 9 CAN MDAR4 10 CAN MDAR5 11 CAN MDARG6 12 CAN MDAR7 13 CAN MDAR8 14 CAN MTSRL 15 CAN MTSRH DoclD14587 Rev 12 2 RM0016 Controller area network beCAN 23 6 5 Note 2 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter TECR register and a Receive Error Counter CAN register which get incremented or decremented according to the error condition For detailed information about TEC and REC management please refer to the CAN standard Both of them may be read by software to determine the stability of the network Furthermore the CAN hardware provides detailed information on the current error status in CAN ESR register By means of CAN EIER register and ERRIE bit in CAN IER register the software can configure the interrupt generation on error detection in a very flexible way Bus Off recovery The Bus Off state is reached when TEC is greater then 255 this state is indicated by
156. must be cleared 2 418 462 DoclD14587 Rev 12 RM0016 Controller area network beCAN 23 12 2 CAN register Figure 157 CAN register mapping 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 CAN MASTER CONTROL REGISTER CAN_MCR CAN MASTER STATUS REGISTER CAN_MSR CAN TRANSMIT STATUS REGISTER CAN_TSR CAN TRANSMIT PRIORITY REGISTER CAN_TPR CAN RECEIVE FIFO REGISTER CAN INTERRUPT ENABLE REGISTER CAN_RFR CAN_IER CAN DIAGNOSTIC REGISTER CAN_DGR CAN PAGE SELECTION REGISTER CAN_PSR D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST D REGIST DoclD14587 Rev 12 419 462 Controller area network beCAN 0016 23 12 1 Page mapping for CAN Figure 158 CAN page mapping PAGE 0 PAGE 1 PAGE 2 PAGE 3 PAGE 4 0x00 CAN MCSR CAN MCSR CAN FOR1 CAN F2R1 CAN F4R1 0x01 CAN MDLCR CAN MDLCR CAN FOR2 CAN F2R2 CAN F4R2 0x02 CAN_MIDR1 CAN_MIDR1 CAN FOR3 CAN F2R3 CAN F4R3 0x03 CAN MIDR2 CAN MIDR2 FOR4 CAN_F2R4 CAN_F4R4 0x04 MIDR3 M
157. needed to restore the system clock the SPI slave sends or receives a few data before being able to communicate correctly It is then mandatory to use the following protocol A specific value is written into the SPI DR before entering Halt mode This value indicates to the external master that the SPI is in Halt mode The external master sends the same byte continuously until it receives from the SPI slave device a new value other than the unique value indicating the SPI is in Halt mode This new value indicates the SPI slave has woken up and can correctly communicate Restrictions in receive only modes The wakeup functionality is not guaranteed in receive only modes BDM 0 and RXONLY 1 or BDM 1 and BDOE 0 since the time needed to restore the system clock can be greater than the data reception time A loss of data in reception would then be induced and the slave device can not indicate to the master which data has been properly received SPI interrupts Table 46 SPI interrupt requests Enable Exit Exit Event Interrupt event tla control from from 9 bit Wait Halt Transmit buffer empty flag TXE TXIE Yes No Receive buffer not empty flag RXNE RXIE Yes No DoclD14587 Rev 12 275 595 Serial peripheral interface SPI 0016 Table 46 SPI interrupt requests Enable Exit Exit Event Interrupt event tla control from from 9 bit Wait Halt Wakeup event flag WKUP WKIE Yes Yes Master mo
158. operation To use the beep function perform the following steps in order 1 Calibrate the LS clock frequency as described in Section 13 2 2 Beeper calibration to define BEEPDIV 4 0 value 2 Select 1 kHz 2 kHz or 4 kHz output frequency by writing to the BEEPSEL 1 0 bits in the Beeper control status register CSR 3 Setthe BEEPEN bit in the Beeper control status register to enable the LS clock source The prescaler counter starts to count only if BEEPDIV 4 0 value is different from its reset value Ox1F 2 DoclD14587 Rev 12 0016 Beeper 13 2 2 Beeper calibration This procedure can be used to calibrate the LS 128 kHz clock in order to reach the standard frequency output 1 kHz 2 kHz or 4 kHz Use the following procedure 1 Measure the LSI clock frequency refer to Section 12 3 3 LSI clock frequency measurement above 2 Calculate the BEEPpyy value as follows where A and x are the integer and fractional part of f lt 8 in KHz A 2 when x is less than or equal to A 1 2 A else BEEPpyy 1 3 Write the resulting value the BEEPDIV 4 0 bits in the Beeper control status register CSR 13 3 Beeper registers 13 3 1 Beeper control status register BEEP CSR Address offset 0x00 Reset value Ox1F 7 6 5 4 3 2 1 0 BEEPSEL 1 0 BEEPEN BEEPDIV 4 0 rw rw w Bits 7 6 BEEPSEL 1 0 Beep se
159. oscillator HSI 128 kHz low speed internal RC LSI Each clock source can be switched on or off independently when it is not used to optimize power consumption HSE The high speed external clock signal HSE can be generated from two possible clock sources HSE external crystal ceramic resonator HSE user external clock Figure 21 HSE clock sources Hardware configuration 5 9 OSCOUT T E t I O available EXTERNAL SOURCE OSCIN OSCOUT a 7 Crystal ceramic resonators LOAD CAPACITORS The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time The loading capacitance values must be adjusted according to the selected oscillator DoclD14587 Rev 12 79 462 Clock control CLK 0016 Note 9 1 2 Note 80 462 External crystal ceramic resonator HSE crystal The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on the main clock with 50 duty cycle The associated hardware configuration is shown in Figure 21 Refer to the electrical characteristics section for more details At start up the clock signal produced by the oscillator is not stable and by default a delay of 2048 osc cycles is inserted before the clock signal is released You can program a shorter s
160. pointer The user must take care to initialize this pointer Correct loading of this pointer is usually performed by the initialization code generated by the development tools linker file In the default stack model this pointer is initialized to the RAM end address Stack roll over limit In some devices a stack roll over limit is implemented at a fixed address If the stack pointer is decreased below the stack roll over limit using a push operation or during context saving for subroutines or interrupt routines it is reset to the RAM end address The stack pointer does not roll over if stack pointer arithmetic is used Such behavior of the stack pointer is of particular importance when developing software on a device with a different memory configuration than the target device DoclD14587 Rev 12 31 595 Memory and register map 0016 32 595 Customized stack model STM8S and STMBAF stack pointer handling allows a customized stack model to be implemented This permits a flexible stack size without restrictions due to the stack roll over limit Implementing the customized stack also benefits portability of the software on products with different memory configurations Figure 5 shows the customized stack model Figure 5 Customized stack model RAM Start address Optional guard cells 2 Flexible stack size Stack pointer initialization value Stack roll over limit 3 End address Customized stack mode
161. progress Continuous scan mode can be stopped immediately by clearing the ADON bit Alternatively if the CONT bit is cleared while conversion is ongoing conversion stops the next time the last channel has been converted In scan mode do not use a bit manipulation instruction BRES to clear the EOC flag This is because this performs a read modify write on the whole ADC_CSR register reading the current channel number from the CH 3 0 register and writing it back which changes the last channel number for the scan sequence The correct way to clear the EOC flag in continuous scan mode is to load a byte in the ADC_CSR register from a RAM variable clearing the EOC flag and reloading the last channel number for the scan sequence Overrun flag The OVR error flag is set by hardware in buffered continuous mode single scan or continuous scan modes It indicates that one of the ten data buffer registers was overwritten by a new converted value before the previous value was read In this case it is recommended to start a new conversion Setting the ADON bit automatically clears the OVR flag 2 DoclD14587 Rev 12 RM0016 Analog digital converter ADC 24 5 6 Note d Analog watchdog The analog watchdog is enabled by default for single conversion and non buffered continuous conversion modes The AWD analog watchdog flag is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold
162. read Busy flag BSY This BSY flag is set and reset by hardware writing to this flag has no effect The BSY flag indicates the state of the communication layer of the SPI When BSY is set it indicates that the SPI is busy communicating There is one exception in master mode bidirectional receive mode MSTR 1 and BDM 1 and BDOE 0 where the BSY flag is kept low during the reception The BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI and enters Halt mode or disable the peripheral clock This will avoid corrupting the last transfer For this the procedure described below must be strictly respected The BSY flag is also useful to avoid write collisions in a multimaster system The BSY flag is set when a transfer starts with the exception of master mode bidirectional receive mode MSTR 1 and BDM 1 and BDOE 0 It is reset e whena transfer is finished except in master mode if the communication is continuous e when the SPI is disabled e when a master mode fault occurs 1 When communication is not continuous the BSY flag is low between each communication When communication is continuous in master mode the BSY flag is kept high during the whole transfers When communication is continuous in slave mode the BSY flag goes back to low state for one SPI clock cycle between each transfer Do not use the BSY flag to handle each data transmission or reception It is
163. read to the DR register In UART2 and it can also be cleared by writing 0 0 Data is not received 1 Received data is ready to be read Bit4 IDLE IDLE line detected 358 462 This bit is set by hardware when an Idle Line is detected An interrupt is generated if the ILIEN 1 in the UART CR register It is cleared by a software sequence a read to the SR register followed by a read to the UART DR register 0 No Idle Line is detected 1 Idle Line is detected 3 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART 2 Bit 3 Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE 1 An interrupt is generated if RIEN 1 in the UART CRe register It is cleared by a software sequence a read to the register followed by a read to the UART register 0 No Overrun error 1 Overrun error is detected LHE LIN Header Error LIN slave mode During LIN Header reception this bit signals three error types Break delimiter too short Synch Field error Deviation error if LASE 1 m Identifier framing error 0 No LIN Header error 1 LIN Header error detected Bit 2 NF Noise flag 9 This bit is set by hardware when noise is detected on a received frame It is cleared by a software sequence a read to the UART_SR register followed by
164. register TIM1 CCR 1 preload value is loaded in the shadow register at each UEV Note These bits can no longer be modified while LOCK level 3 has been programmed LOCK bits in TIM1 BKR register and CC1S 00 the channel is configured in output For correct operation preload registers must be enabled when the timer is in PWM mode This is not mandatory in one pulse mode OPM bit set in TIM1 CH register Bit 2 OC1FE Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output 0 CC1 behaves normally depending on the counter and CCR1 values even when the trigger is on The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles 1 An active edge on the trigger input acts like a compare match on the CC1 output If this happens OC is set to the compare level irrespective of the result of the comparison The delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles OCFE acts only if the channel is configured in PWM1 or PWM2 mode Bits 1 0 CC1S 1 0 Capture compare 1 selection 198 595 This bitfield defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is configured as input IC1 is mapped 10 CC1 channel is configured as input is mapped on 2 1 11 CC1 channel is configured as input IC1
165. register Px CR2 At reset state the interrupts are disabled If a pin alternate function is TLI use the Px CR2 bit to enable disable the interrupt The TLI interrupt is associated to a dedicated interrupt vector Analog channels Analog channels can be selected by the ADC peripheral The corresponding input and output stages are then automatically disabled As mentioned in the next section the input Schmitt trigger should be disabled in the ADC_TDR register when using the analog channels Table 23 Recommended and non recommended configurations for analog input DDR CR1 0 CR2 ADC TDR Configuration Comments Floating Input without interrupt Recommended analog input 0 Schmitt trigger disabled configuration X X Input with pull up enabled Not recommended for analog input when analog voltage is present since these Output configurations cause excess current flow on the input pin X Output Both input and output stages are disabled on ADC selected channel 108 595 d DoclD14587 Rev 12 0016 General purpose ports GPIO 11 7 4 Schmitt trigger On all I Os with an analog input it is possible to disable the Schmitt trigger even if the corresponding ADC channel is not enabled two registers and ADC_TDRL allow to disable the Schmitt trigger Setting one bit in these registers leads to disabling the corresponding Schmitt
166. register is set HSI on e HSEEN bit in the External clock register CLK ECKR is cleared HSE off e The AUX bit is set to indicate that the HSI 8 auxiliary clock source is forced You can clear the CSSD bit by software but the AUX bit is cleared only by reset To select a faster clock speed you can modify the HSIDIV 1 0 bits in the CLK CKDIVR register after the CSSD bit in the CLK CSSR register is cleared If HSE is not the current clock master when a failure is detected the master clock is not Switched to the auxiliary clock and none of the above actions are performed except e HSEEN bit is cleared in the CLK ECKR register HSE is then switched OFF e The CSSD bit is set in the CLK CSSR register and interrupt is generated if CSSDIE is also set it can be cleared by software If HSE is not the current clock master and the master clock switch to HSE is ongoing the SWBSY bit in the CLK SWCR register must be cleared by software before clearing the CSSD bit If HSE is selected by CCOSEL to be in output mode see Clock out capability CCO when a failure is detected the selection is automatically changed to force HSI HSIDIV instead of HSE DoclD14587 Rev 12 87 462 Clock control CLK 0016 9 7 Note 9 8 88 462 Clock out capability CCO The configurable Clock Output CCO capability allows you to output a clock on the external CCO pin You can select one of 6 clock signals as CCO clock e
167. resolution in a reduced voltage range Refer to the datasheet for details on the allowed reference voltage range Timing diagram As shown in Figure 162 after ADC power on the ADC needs a stabilization time equivalent to one conversion time before it starts converting accurately For subsequent conversions there is no stabilization delay and ADON needs to be set only once The ADC conversion time takes 14 clock cycles After conversion the EOC flag is set and the 10 bit ADC Data register contains the result of the conversion 3 DoclD14587 Rev 12 RM0016 Analog digital converter ADC 2 Figure 162 Timing diagram in single mode CONT 0 1 l 5 Software sets ADON bit 1st time oftware sets ADON bit 2nd time ADC ADC Conversion tSTAB Conversion Time tCONV ADON E l 1 gt 5 1 Software resets EOC bit Figure 163 Timing diagram in continuous mode CONT 1 lt A L ls lg Software sets ADON bit 1st time sets ADON bit 2nd time Software resets ADON or ONT bit ADON 4 1st Conversion 2nd Conversion nth ADC Conversion ADC f tSTAB tCONV tCONV lt gt 4
168. see Section 19 6 10 Reset value OxFF 7 6 5 4 3 2 1 0 ARR 7 0 rw rw rw rw rw rw rw rw Bits 7 0 ARR 7 0 Auto reload value 19 6 10 TIM4 TIM6 register map and reset values In some STM8S and 5 devices TIM4 register locations at offset 0x01 and 0x02 are reserved In this case the TIM4_IER and subsequent registers in the TIM4 block are offset by 2 more bytes Refer to the datasheet for the product specific register map Table 43 TIM4 register map Address offset Register 7 6 5 4 3 2 1 0 product name dependent TIM4 CR1 ARPE OPM URS UDIS CEN Reset value 0 0 0 0 0 0 0 0 0x01 Reserved 0x02 Reserved TIM4 IER Reset value 0 0 0 0 0 0 0 0 TIM4 SR 0x02 0x04 Reset value 0 0 0 0 0 0 0 0 TIM4 EGR UG 0x03 0x05 Reset value 0 0 0 0 0 0 0 0 4 CNTR CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO 0x04 0x06 Reset value 0 0 0 0 0 0 0 0 TIM4_PSCR 2 j PSC2 PSC1 PSCO 0x07 Reset value 0 0 0 0 0 0 0 0 06 M4 ARR ARR ARR6 ARRS ARRA ARR3 ARR2 ARRI ARRO Reset value 1 1 1 1 1 1 1 1 Ly DoclD14587 Rev 12 255 595 8 bit basic timer TIM4 TIM6 0016 Table 44 TIM6 register map po Register name 7 6 5 4 3 2 1 0 0 00 TIM6 CR1 ARPE OPM URS UDIS CEN Reset value 0 0 0 0 0 0 0 0 0x01 6 CR2 MMS2 MMS1 MMSO Reset value 0 0 0 0 0 0 0 0 0x02
169. some have additional unique features The common timer architecture which includes identical register mapping and common basic features simplifies their use and makes it easier to design applications Table 33 shows the main timer characteristics In STM8S and STMB8AF devices with TIM1 TIM5 and TIMG the timers do not share resources but they can be linked together and synchronized as described in Synchronization between TIM1 TIM5 and 6 timers on page 158 In STM8S and STMB8AF devices with TIM1 TIM2 and TIM4 the timers are not linked together This section gives a comparison of the different timer features Table 34 a glossary of internal timer signal names Table 35 Section 17 16 bit advanced control timer TIM1 contains a full description of all the various timer modes The other timer sections Section 18 and Section 19 are more brief and give only specific details on each timer its block diagram and register description Table 33 Timer characteristics Symbol Parameter Min Typ Max Unit tw ICAP in Input capture pulse time 2 tres TIM Timer resolution time 1 Timer resolution with 16 bit counter 16 bit Restim Timer resolution with 8 bit counter bit Counter clock period when internal clock is tCOUNTER selected 1 tMASTER Maximum possible count with 16 bit counter 65 536 COUNT z Maximum possible count with 8 bit count
170. the CAN standard 1 A message will be transmitted only once independently of the transmission result successful error or arbitration lost Bit 3 RFLM Receive FIFO Locked Mode 396 462 0 Receive FIFO not locked on overrun Once a receive FIFO is full the next incoming message will overwrite the previous one 1 Receive FIFO locked against overrun Once a receive FIFO is full the next incoming message will be discarded d DoclD14587 Rev 12 Controller area network beCAN Bit 2 TXFP Transmit FIFO Priority This bit controls the transmission order when several mailboxes are pending at the same time 0 Priority driven by the identifier of the message 1 Priority driven by the request order chronologically Bit 1 SLEEP Sleep Mode Request This bit must be set by software to request the CAN hardware to enter Sleep mode If the AWUM bit is not set the Sleep mode is entered as soon as the current CAN activity CAN frame transmission or reception has completed If the AWUM bit is set and the CAN bus is active the CAN does not enter Sleep mode the SLEEP bit is not set and the WKUI bit of the CAN MSR register is set This bit must be cleared by software to exit Sleep mode It can be cleared by hardware when the AWUM bit is set and a SOF bit is detected on the CAN Rx signal After a reset the CAN is in Sleep mode and the SLEEP bit is set Bit 0 INRQ Initialization Request The software clears this bit to switch the har
171. the LSF bit is set If LHE bit is set due to this error during Fields other than LIN Synch Field or if LASE bit is reset then the current received Header is discarded and the UART searches for a new Break Field Note on LIN Header time out limit According to the LIN specification the maximum length of a LIN Header which does not cause a time out is equal to 1 4 34 1 2 49 TBIT MASTER TBIT MASTER refers to the master baud rate DoclD14587 Rev 12 349 462 Universal asynchronous receiver transmitter UART 0016 When checking this time out the slave node is desynchronized for the reception of the LIN Break and Synch fields Consequently a margin must be allowed taking into account the worst case This occurs when the LIN identifier lasts exactly 10 TBIT MASTER periods In this case the LIN Break and Synch fields last 49 10 39 TBIT MASTER periods Assuming the slave measures these first 39 bits with a desynchronized clock of 15 596 This leads to a maximum allowed Header Length of 39 x 1 0 845 TBIT MASTER 10 TBIT MASTER 56 15 TBIT SLAVE A margin is provided so that the time out occurs when the header length is greater than 57 SLAVE periods If it is less than or equal to 57 periods then no time out occurs Mute mode and errors In mute mode if an LHE error occurs during the analysis of the LIN Synch Field or if a LIN Header Time out occurs then the LHE bit is set but it d
172. the second to last occurrence of RXNE 1 n 1 2 Then wait for one SPI clock cycle using a software loop before disabling the SPI SPE 0 3 Then wait for the last RXNE 1 before entering Halt mode or disabling the peripheral clock In master bidirectional receive mode MSTR 1 and BDM 1 and BDOE 0 the BSY flag is kept low during a transfer In slave receive only mode MSTR 0 BDM z 0 RXONLY 1 or bidirectional receive mode MSTR 0 BDM 1 BDOE 0 1 You disable the SPI write SPE 1 whenever you want the current transfer will complete before being effectively disabled 2 Then if you want to enter Halt mode you must first wait until BSY 0 before entering Halt mode or disabling the peripheral clock DoclD14587 Rev 12 273 595 Serial peripheral interface SPI 0016 20 3 9 274 595 Error flags Master mode fault MODF Master mode fault occurs when the master device has its NSS pin pulled low in 55 hardware mode or SSI bit low in NSS software mode this automatically sets the MODF bit Master mode fault affects the SPI peripheral in the following ways e bit is set and SPI interrupt is generated if the ERRIE bit is set e SPE bit is reset This blocks all output from the device and disables the SPI interface e MSTR bit is reset thus forcing the device into slave mode Use the following software sequence to clear the MODF bit 1 Mak
173. time to disable again write access to the DATA area by clearing the DUL bit DoclD14587 Rev 12 45 595 Flash program memory and data EEPROM 0016 4 5 3 4 6 4 6 1 Note 4 6 2 46 595 Enabling write access to option bytes The procedure for enabling write access to the option byte area is the same as the one used for data EEPROM However the OPT bit in the Flash control register 2 FLASH 2 must be set and the corresponding bit in the Flash complementary control register 2 FLASH 2 must be cleared to enable write access to the option bytes Memory programming The main program memory and the DATA area must be unlocked before attempting to perform any program operation The unlock mechanism depends on the memory area to be programmed as described in Section 4 5 2 Memory access security system MASS Read while write RWW The RWW feature allows write operations to be performed on data EEPROM while reading and executing the program memory Execution time is therefore optimized The opposite operation is not allowed Data memory cannot be read while writing to the program memory This RWW feature is always enabled and can be used at any time Any access to Flash control registers FLASH CR1 and FLASH CR2 while writing to the memory stalls the CPU making RWW unavailable RWW feature is not available on all devices Refer to the datasheets for addition information Byte programming T
174. to Table 28 14 3 4 IWDG register map and reset values Table 29 IWDG register map Address Register 7 6 5 4 3 2 1 0 offset name IWDG KR KEY 7 0 0x09 Reset value XXXXXXXX IWDG_PR PR2 2 0 0x01 Reset value 0 0 0 0 0 000 IWDG_RLR RL7 7 0 0x02 Reset value 11111111 126 595 2 DoclD14587 Rev 12 RM0016 Window watchdog WWDG 15 15 1 15 2 15 3 d Window watchdog WWDG Introduction The window watchdog is used to detect the occurrence of a software fault usually generated by external interference or by unforeseen logical conditions which causes the application program to abandon its normal sequence The watchdog circuit generates an MCU reset on expiry of a programmed time period unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared An MCU reset is also generated if the 7 bit downcounter value in the control register is refreshed before the downcounter has reached the window register value This implies that the counter must be refreshed in a limited window WWDG main features e Programmable free running downcounter e Conditional reset Reset if watchdog activated when the downcounter value becomes less than 0x40 Reset if watchdog activated if the downcounter is reloaded outside the window see Figure 30 Hardware software watchdog activation selectable by option byte e Optional reset on HALT instruction configura
175. to signal that the last request for mailbox 0 has been completed The request could be a transmit or an abort request This bit is cleared by software writing 1 23 11 4 transmit priority register CAN Address offset 0x03 Reset value 0 0 7 6 5 4 3 2 1 0 LOW 2 LOW1 LOWO TME2 TME1 TMEO CODE1 CODEO r r r r r r r r Bit 7 LOW2 Lowest Priority Flag for Mailbox 2 This bit is set by hardware when more than one mailbox is pending for transmission and mailbox 2 has the lowest priority Note ltis set to zero when only one mailbox is pending Bit 6 LOW1 Lowest Priority Flag for Mailbox 1 This bit is set by hardware when more than one mailbox is pending for transmission and mailbox 1 has the lowest priority Note ltis set to zero when only one mailbox is pending Bit 5 LOWO Lowest Priority Flag for Mailbox 0 This bit is set by hardware when more than one mailbox is pending for transmission and mailbox 0 has the lowest priority Note ltis set to zero when only one mailbox is pending Bit 4 TME2 Transmit Mailbox 2 Empty d This bit is set by hardware when no transmit request is pending for mailbox 2 Note This bit is reserved forced to 0 by hardware ST7 beCAN compatibility mode 2 bit 0 in CAN DGR register DoclD14587 Rev 12 399 462 Controller area network beCAN 0016 Bit 3 TME1 Transmit Mailbox 1 Empty This bit is set by hardware when no transmit request is pending for mailbox 1 Bit2 TMEO Trans
176. to the auto reload value 2 DoclD14587 Rev 12 149 595 16 bit advanced control timer TIM1 RM0016 17 4 17 4 1 150 595 clock trigger controller The clock trigger controller allows the timer clock sources input triggers and output triggers to be configured The block diagram is shown in Figure 43 Figure 43 Clock trigger controller block diagram TIM1_ETR TRGO from 6 ITRO TRGO from TIM5 ITR2 From input stage MASTER EN Trigger ETR PIRE Controller Polarity Selection amp Edge gt Detector amp Prescaler 5 Put filter TGI m Clock Trigger TRC TRG Mode Controller THF ED Lr gt i P Encoder From input stage MTM marea LR merce Prescaler clock PSC The time base unit prescaler clock CK PSC can be provided by the following clock Sources e Internal clock e External clock mode 1 External timer input TIx e External clock mode 2 External trigger input ETR e Internal trigger inputs ITR using one timer as prescaler for another timer Refer to Using one timer as prescaler for another timer on page 159 for more details DoclD14587 Rev 12 To other CK PSC w TRGO timers Reset Enable Up Down Count To Time Base Unit d RM0016 16 bit advanced control time
177. trigger input there is a delay on TRGO except if the master slave mode is selected see the MSM bit description in TIM1_SMCR register 010 Update The update event is selected as trigger output TRGO 011 Compare pulse MATCH1 The trigger output sends a positive pulse when the CC1IF flag is to be set even if it was already high as soon as a capture or a compare match occurs TRGO 100 Compare OC1REF signal is used as trigger output TRGO 101 Compare OC2REF signal is used as trigger output TRGO 110 Compare OC3REF signal is used as trigger output TRGO 111 Compare OC4REF signal is used as trigger output TRGO Reserved must be kept cleared COMS Capture compare control update selection 0 When capture compare control bits are preloaded CCPC 1 they are updated by setting the COMG bit 1 When capture compare control bits are preloaded CCPC 1 they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note This bit acts only on channels with complementary outputs Reserved forced by hardware to 0 CCPC Capture compare preloaded control 0 The CCE and CCNP bits in the TIM1 CCERi registers and the bit in the TIM1_CCMRi registers are not preloaded 1 CCIE CCINE and OCM bits are preloaded after having been written they are updated only when COMG bit is set in the TIM1_EGR register Note This bit acts only on channels with comp
178. trigger input buffer In case an is used as analog input and the corresponding ADC channel is enabled CH 3 0 bits in register the Schmitt trigger is disabled whatever the status of the corresponding bit in ADC_TDRH or ADC_TDRL registers 11 7 5 Analog function Selected can be used to deliver analog signal to ADC Comparators or DAC periphery The GPIO pin have to be configured in the input floating configuration without interrupt default state to use it for analog function The current consumption of the IO with enabled analog function can be reduced by disabling unused Schmitt trigger in IO input section either by TRIGRx register in ADC interface see Section 14 3 15 Schmitt trigger disabling or by switching on a corresponding analog switch in RI by setting corresponding bit in RI IOSRx see Section 11 2 2 I O groups See the product datasheet for pins with analog functions 11 8 Output mode details 11 8 1 Alternate function output Alternate function outputs provide a direct path from a peripheral to an output or to an I O pad taking precedence over the port bit in the data output latch register ODR and forcing the Px DDR corresponding bit to 1 An alternate function output can be push pull or pseudo open drain depending on the peripheral and Control register 1 Px CR1 and slope can be controlled depending on the Control register 2 Px CR2 values Examples SPI output pins must be se
179. updated in Section 23 11 1 CAN master control register CAN External beCAN clock source removed together with bit CLKS of CAN BTR2 register Removed CAN register CLK CANCCR Section 24 Analog digital converter ADC Updated address offset for ADC _CSR to ADC_AWCRL Added AIN12 and Note 1 in Figure 159 ADC1 block diagram and note related to AIN12 in Section 24 5 4 Conversion modes 15 Dec 2011 Added value line STM8S devices on page 1 Modified Section 4 4 1 STM8S and STM8AF memory organization on page 36 Modified Section 6 6 External interrupts on page 65 Modified TLIS bit description in Section 6 9 4 External interrupt control register 1 EXTI CR2 on page 70 Modified Figure 20 Clock tree on page 78 Modiifed HSE oscillator in quartz crystal configuration in Section 9 6 Clock security system CSS on page 87 Removed one sentence in Section 11 8 1 Alternate function output on page 109 Modified Timeout period on page 124 Modified Figure 101 I2C block diagram on page 285 SMBA pin removed Replaced SYSCLK with fcpy in Section 15 Window watchdog WWDG on page 127 Modified Section 15 7 Using Halt mode with the WWDG WWDGHALT option on page 131 Removed note 1 below Figure 101 I2C block diagram on page 285 Added one note in Section Output stage Added one note to OPM bit description in Section 18 6 1 Control register 1 TIMx CH1 Note added below Se
180. value LSB 2 prescaler value divides the PSC clock frequency The counter clock frequency is equal to fek psc PSCR 15 0 1 contains the value which is loaded in the active prescaler register at each UEV including when the counter is cleared through the UG bit of the TIM1 EGR register or through the trigger controller when configured in trigger reset mode A UEV must be generated so that a new prescaler value can be taken into account DoclD14587 Rev 12 207 595 16 bit advanced control timer TIM1 0016 17 7 19 Auto reload register high TIM1 ARRH Address offset 0x12 Reset value OxFF ARR 15 8 Bits 7 0 ARR 15 8 Auto reload value MSB ARR is the value to be loaded in the actual auto reload register Refer to the Section 17 3 TIM1 time base unit on page 140 for more details about ARR update and behavior The counter is blocked while the auto reload value is null 17 7 20 Auto reload register low ARRL Address offset 0x13 Reset value OxFF ARR 7 0 Bits 7 0 ARR 7 0 Auto reload value LSB 17 7 24 Repetition counter register TIM1 Address offset 0x14 Reset value 0x00 REP 7 0 Bits 7 0 REP 7 0 Repetition counter value When the preload registers are enabled these bits allow the user to set up the update rate of the compare registers periodic transfer
181. values called MASS keys to the FLASH DUKR register see Section 4 8 9 Flash register map and reset values These programmed keys are then compared to two hardware key values e First hardware key 001010 1110 OxAE Second hardware key 000101 0110 0x56 The following steps are required to disable write protection of the DATA area 1 Write a first 8 bit key into the FLASH DUKR register When this register is written for the first time after a reset the data bus content is not latched into the register but compared to the first hardware key value OxAE 2 Ifthe key available on the data bus is incorrect the application can re enter two MASS keys to try unprotecting the DATA area 3 If the first hardware key is correct the FLASH DUKR register is programmed with the second key The data bus content is still not latched into the register but compared to the second hardware key value 0x56 4 Ifthe key available on the data bus is incorrect the data EEPROM area remains write protected until the next reset Any new write command sent to this address is ignored 5 Ifthe second hardware key is correct the DATA area is write unprotected and the DUL bit of the FLASH IAPSR register is set see Section 4 8 8 Flash status register FLASH 5 Before starting programming the application must verify that the DATA area is not write protected by checking that the DUL bit is effectively set The application can choose at any
182. when capture compare control bits CC E OCM have been updated It is cleared by software 0 No COM has occurred 1 COM interrupt pending CC4IF Capture compare 4 interrupt flag Refer to CC1IF description CC3IF Capture compare 3 interrupt flag Refer to CC1IF description DoclD14587 Rev 12 193 595 16 bit advanced control timer TIM1 0016 Bit 2 CC2IF Capture compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF Capture compare 1 interrupt flag If channel CC1 is configured as output This flag is set by hardware when the counter matches the compare value with some exception in center aligned mode refer to the CMS bits from TIM1_CR1 register description It is cleared by software 0 No match 1 The content of the counter register TIM1 CNT matches the content of the TIM1 CCR 1 register Note When the contents of TIMx CCRi are greater than the contents of TIMx ARR the CCilF bit goes high on the counter overflow in up counting and up down counting modes or underflow in down counting mode If channel CC1 is configured as input This bit is set by hardware on a capture It is cleared by software or by reading the TIM1 CCR1L register 0 No input capture has occurred 1 The counter value has been captured in the TIM1 CCR1 register an edge has been detected on IC1 which matches the selected polarity Bit UIF Update interrupt flag This bit is set by hardware on an update
183. which is copied into the preload register In compare mode the content of the preload register is copied into the shadow register which is compared to the counter When the channel is configured in output mode 5 00 in the TIM1 CCMRi registers the TIM1 CCRiregisters be accessed without any restriction When the channel is configured in input mode the sequence for reading the TIM1 CCRi registers is the same as for the counter see Figure 62 When a capture occurs the content of the counter is captured into the TIM1 CCRi shadow registers Then this value is loaded into the preload register except during a read sequence when the preload register is frozen Figure 62 16 bit read sequence for the TIM1 CCRi register in capture mode shadow register Other is buffered into the preload register Beginning of the sequence Read Preload register Att0 MS Byte is frozen Y _ Other instructions Read Preload register At t0 01 S Byte lis no longer frozen Sequence completed r d pM ERES register is buffered into Linstructions the preload register Figure 62 shows the sequence for reading the CCRi registers the 16 bit timers This buffered value remains unchanged until the 16 bit read sequence is completed After a complete read sequence if only the TIM1_CCRIL registers are read they return the LS byte of the count value at the time of the read If the MS byte is read after the LS byte it no
184. 0 7 6 5 4 3 2 1 0 CCR1 15 8 rw rw rw rw rw rw rw rw Bits 7 0 CCR1 15 8 Capture compare 1 value MSB If the CC1 channel is configured as output CC1S bits 1 register The value of CCR1 is loaded permanently into the actual capture compare 1 register if the preload feature is not enabled OC1PE bit in TIMx CCMR1 Otherwise the preload value is copied in the active capture compare 1 register when a UEV occurs The active capture compare register contains the value which is compared to the counter register TIMx CNT and signalled on the OC1 output If the CC1 channel is configured as input CC1S bits in TIMx_CCMR1 register The value of CCR1 is the counter value transferred by the last input capture 1 event IC1 In this case these bits are read only 242 595 DoclD14587 Rev 12 Ly RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 6 19 register 1 low TIMx CCR1L Address offset 00x10 or 0x12 2 OxOE TIM3 0x12 TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 CCR1 7 0 rw rw rw rw rw rw rw rw Bits 7 0 CCR1 7 0 Capture compare 1 value LSB 18 6 20 Capture compare register 2 high TIMx CCR2H Address offset 00x11 or 0x13 TIM2 OxOF TIM3 0x13 TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 CCR2 15 8 rw rw rw rw rw rw rw rw Bits
185. 00 s set active 001 sset inactive 010 Toggles 011 e is set in the interrupt status register bits in the TIM1 SR1 register e An interrupt is generated if the corresponding interrupt mask is set bits in the TIM1 IER register DoclD14587 Rev 12 Ly RM0016 16 bit advanced control timer TIM1 d The output compare mode is defined by the OCM bits in the TIM1 CCMRi registers The active or inactive level polarity is defined by the CC P bits in the TIM1 CCERiregisters The TIM1 CCRiregisters can be programmed with or without preload registers using the bits the TIM1 CCMRi registers In output compare mode the UEV has no effect on the OCiREF and OC output The timing resolution is one count of the counter Output compare mode can also be used to output a single pulse Procedure 1 Select the counter clock internal external or prescaler 2 Write the desired data in the TIM1 ARR and TIM1 CCRi registers 3 Setthe CCIIE bits if an interrupt request is to be generated 4 Select the output mode as follows Write OCM 011 to toggle the OC output pin when CNT matches Write OC PE 0 to disable the preload register Write 0 to select active high polarity Write 1 to enable the output 5 Enable the counter by setting the CEN bit in the TIMx_CR1 register The TIM1 CCRiregisters can be updated at any time
186. 0100 22APRpi fi s 0101 2 APRpiv f s 0110 2 s 0111 26APRpiv fLs 1000 2 APRpiy fi s 1001 28APRpiv fLs 1010 22 1 1011 2 APRES f s 1100 2 s 1101 21 APRpiv fLs 1110 5x2 APRp fi s 1111 30x2 APRpy fi 6 118 462 DoclD14587 Rev 12 Ly RM0016 Auto wakeup AWU 12 4 4 AWU register map and reset values Table 26 AWU register map Address Register 7 6 5 4 3 2 1 0 offset name AWU_CSR AWUF AWUEN 5 MSR Reset value 0 0 0 0 0 0 0 0 AWU APR z APR5 APR4 APR3 APR2 APR1 APRO Reset value 0 0 1 1 1 1 1 1 oxa AWU_TBR 2 AWUTB3 AWUTB2 AWUTB1 AWUTBO Reset value 0 0 0 0 0 0 0 0 2 DoclD14587 Rev 12 119 462 Beeper BEEP RM0016 13 13 1 13 2 13 2 1 Note 120 462 Beeper BEEP Introduction This function generates a beep signal in the range of 1 2 or 4 kHz when the LS clock is operating at a frequency of 128 kHz Figure 26 Beep block diagram HSE clock 4 24 MHz CKAWUSEL PRSC 1 0 OPTION bits OPTION bit Prescaler MSR 128 kHz LS clock To timer input capture LSI RC for measurement 128kHz BEEPDIV 4 0 bits BEEPSEL 1 0 bits 8 kHz 3 BIT COUNTER 2 2 2 4 2 5 BIT BEEPER PROG COUNTER Beeper functional description Beeper
187. 1 HSITRIMO Reset value 0 0 0 0 0 0 0 0 CLK SWIMCCR SWIMCLK 0x0D Reset value x X x 0 d DoclD14587 Rev 12 99 462 Power management 0016 10 10 1 100 462 Power management By default after a system or power reset the microcontroller is in Run mode In this mode the CPU is clocked by fcpy and executes the program code the system clocks are distributed to the active peripherals and the microcontroller is drawing full power While in Run mode still keeping the CPU running and executing code the application has several ways to reduce power consumption such as e Slowing down the system clocks e Gating the clocks to individual peripherals when they are unused e Switching off any unused analog functions However when the CPU does not need to be kept running three dedicated low power modes can be used Wait e Active halt configurable for slow or fast wakeup e configurable for slow or fast wakeup You can select one of these three modes and configure them to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources General considerations Low power consumption features are generally very important for all types of application for energy saving Ultra low power features are especially important for mobile applications to ensure long battery lifetimes This is also crucial for en
188. 1 CH1N 9 oOx Enable Circuit CC1NE CC1E 1 CCER1 OC1M 2 0 DTG 7 0 MOE OSSIJOSSR CCMR1 TIM1 DTR TIM1 CCER1 CCER1 loisin ost OISR Forced output mode In output mode bits 00 in the TIM1 CCMRi registers each output compare signal can be forced to high or low level directly by software independently of any comparison between the output compare register and the counter To force an output compare signal to its active level write 101 in the bits in the corresponding TIM1 CCMRi registers OCiREF is forced high OC REF is always active high and the OC output is forced high or low depending on the CCP polarity bits For example if CC P 0 active high gt OCi is forced high The OCiREF signal be forced low by writing the OCM bits to 100 in the TIMx CCMRx registers Nevertheless the comparison between the TIM1 CCRi shadow registers and the counter is still performed and allows the flag to be set Interrupt requests can be sent accordingly This is described in the output compare mode section below Output compare mode This function is used to control an output waveform or indicate when a period of time has elapsed When a match is found between the capture compare register and the counter e Depending on the output compare mode the corresponding OC output pin A Keeps its level OCM 0
189. 1 as the internal trigger Select this through the TS bits in the TIMx_SMCR register see TS 2 0 bit definitions in TIMx SMCR register Put the clock trigger controller in external clock mode 1 by writing SMS 111 in the TIMx SMCR register This causes timer B to be clocked by the rising edge of the periodic timer A trigger signal which corresponds to the timer A counter overflow Enable both timers by setting their respective CEN bits TIMx CR1 register If OCi is selected on timer A as trigger output MMS 1 its rising edge is used to clock the counter of timer B Figure 55 Master slave timer example TIMER A TIMER B Clock MMS TS UEV ps MASTER TRGO ITR1 SLAVE 5 MODE MODE PRESCALER COUNTER CONTROL CONTROL PRESCALER COUNTER INPUT TRIGGER SELECTION Ly DoclD14587 Rev 12 159 595 16 bit advanced control timer TIM1 0016 Note 160 595 Using one timer to enable another timer Example 1 The enable of timer B is controlled with the output compare 1 of timer A refer to Figure 56 for connections Timer B counts on the divided internal clock only when OC1REF of timer A is high Both counter clock frequencies are divided by four by the prescaler compared to uasTER faster 4 1 Configure timer A master mode to send its output compare 1 reference OC1REF signal as
190. 14587 Rev 12 339 462 Universal asynchronous receiver transmitter UART 0016 Note 22 3 12 Note 340 462 1 e The output enable signal for the Smartcard I O enables driving into a bidirectional line which is also driven by the Smartcard This signal is active while transmitting the start and data bits and transmitting NACK While transmitting the stop bits this signal is disabled so that the UART weakly drives a 1 on the bidirectional line A break character is not significant in Smartcard mode A 00h data with a framing error will be treated as data and not as a break No IDLE frame is transmitted when toggling the TEN bit The IDLE frame as defined for the other configurations is not defined by the ISO protocol Figure 127 details how the NACK signal is sampled by the UART In this example the UART is transmitting a data and is configured with 1 5 stop bits The receiver part of the UART is enabled in order to check the integrity of the data and the NACK signal Figure 127 Parity error detection using 1 5 stop bits Bit 7 Parity Bit 1 5 Stop Bit 1 bit time 1 5 bit time 6 p sampling at sampling at 8th 9th 10th 16th 17th 18th 0 5 bit time 1 bit time Jigen sampling at sampling at 8th 9th 10th 8th 9th 10th The UART can provide a clock to the smartcard through the UART CK output In smartcard mode UART CK is not a
191. 16 18 6 3 Slave mode control register 5 228 18 6 4 Interrupt enable register TIMx IER 229 18 6 5 Status register 1 TIMx SR1 230 18 6 6 Status register 2 TIMx SR2 231 18 6 7 Event generation register EGR 232 18 6 8 Capture compare mode register 1 TIMx 1 233 18 6 9 Capture compare mode register 2 TIMx_CCMR2 236 18 6 10 Capture compare mode register TIMx 237 18 6 11 enable register 1 TIMx CCER1 238 18 6 12 Capture compare enable register 2 TIMx CCER2 239 18 6 13 Counter high TIMx CNTRH 239 18 6 14 Counter low TIMx CNTRL 240 18 6 15 Prescaler register TIMx 241 18 6 16 Auto reload register high TIMx ARRH 241 18 6 17 Auto reload register low TIMx ARRL 242 18 6 18 Capture compare register 1 high TIMx CCR1H 242 18 6 19 Capture compare register 1 low TIMx CCR1L 243 18 6 20 Capture compare register 2 high TIMx CCR2H 243 18 6 21 register 2 low CCR2L 243 18 6 22 Capture com
192. 1DBxRH and ADC1DBxRL data buffer registers are read ADC1 only there is no internal locking mechanism Therefore the user must check the OVR flag in the ADC CRS register after having read the ADC1DBxRH and AD1CDBXRL registers If the OVR flag is cleared this ensures that the values just read from the ADC1DBxRH and AD1CDBxRL registers are consistent Another way to ensure data consistency with right alignment of data is to read ADC1DBxRH and ADC1DBxRL with the following sequence which must not be interrupted ADC READ LDW X ADC_DBORH CPW X ADC_DBORH JREQ ADC_END LDW X ADC_DBORH ADC_END DoclD14587 Rev 12 435 462 Analog digital converter ADC 0016 24 10 24 11 24 11 1 Schmitt trigger disable registers The ADC and ADC registers are used to disable the Schmitt triggers available in the AIN analog input pins Disabling the Schmitt trigger lowers the power consumption in the ADC registers ADC data buffer register x high DBxRH 0 7 or 0 9 Address offset 0x00 2 channel number Reset value 0x00 DBH 7 0 r r r r r r r Note 436 462 Data buffer registers are not available for ADC2 The data buffer size and base address are device dependent and are specified in the corresponding datasheet Note that the data buffer registers and the other ADC registers have different base addresses Bits 7 0 DBH 7 0 Data bits
193. 2 Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 OPT WPRG ERASE FPRG Reserved PRG rw rw rw rw r rw Bit 7 OPT Write option bytes This bit is set and cleared by software 0 Write access to option bytes disabled 1 Write access to option bytes enabled Bit 6 WPRG Word programming This bit is set by software and cleared by hardware when the operation is completed 0 Word program operation disabled 1 Word program operation enabled Bit5 ERASE Block erasing This bit is set by software and cleared by hardware when the operation is completed 0 Block erase operation disabled 1 Block erase operation enabled Bit 4 FPRG Fast block programming This bit is set by software and cleared by hardware when the operation is completed 0 Fast block program operation disabled 1 Fast block program operation enabled Bits 3 1 Reserved Bit 0 PRG Standard block programming This bit is set by software and cleared by hardware when the operation is completed 0 Standard block programming operation disabled 1 Standard block programming operation enabled automatically first erasing 1 The ERASE and FPRG bits are locked when the memory is busy d 52 595 DoclD14587 Rev 12 RM0016 Flash program memory and data EEPROM 4 8 3 Flash complementary control register 2 FLASH_NCR2 Address offset 0x02 Reset value 7 6 5 4 3 2 1 0 NOPT NWPRG NERASE NFPRG Reserved NPRG rw rw rw r
194. 2 0x01 TIM3 0x03 TIM5 for TIM2 address see Section Reset value 0x00 6 5 4 Reserved TIE Reserved CC2IE CC1IE UIE r rw r Bits 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 3 Reserved TIE Trigger interrupt enable 0 Trigger interrupt disabled 1 Trigger interrupt enabled Note In TIMZ TIMS this bit is reserved Reserved must be kept cleared Capture compare 3 interrupt enable 0 CC3 interrupt disabled 1 CC3 interrupt enabled CC2IE Capture compare 2 interrupt enable 0 CC2 interrupt disabled 1 CC2 interrupt enabled CC1IE Capture compare 1 interrupt enable 0 CC1 interrupt disabled 1 CC1 interrupt enabled UIE Update interrupt enable 0 Update interrupt disabled 1 Update interrupt enabled DoclD14587 Rev 12 229 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 6 5 7 Status register 1 TIMx_SR1 Address offset 0x02 or 0x04 TIM2 0x02 TIM3 0x04 TIM5 for TIM2 address see Section Reset value 0x00 6 5 4 3 2 1 0 Reserved TIF Reserved CC3IF CC2IF CC1IF UIF r wO r wO rc 0 rc wO rc wO Bit 7 Bit 6 Bits 5 4 BIt 3 Bit 2 Bit 1 Bit 0 230 595 Reserved TIF Trigger interrupt flag This flag is set by hardware on a trigger event active edge is detected on TRGI signal and both edges are detected when gated mode i
195. 23 11 11 ERRIE Error interrupt enable 0 No interrupt is generated when an error condition is pending in the CAN_ESR ERRI bit in CAN_MSR is set 1 An interrupt is generated when an error condition is pending in the CAN_ESR ERRI bit in CAN_MSR is set Refer to Figure 156 for more details Reserved LECIE Last error code interrupt enable 0 ERRI bit is not set when the error code in LEC 2 0 is set by hardware on error detection 1 ERRI bit is set when the error code in LEC 2 0 is set by hardware on error detection Reserved BOFIE Bus Off interrupt enable 0 ERRI bit is not set when BOFF is set 1 ERRI bit is set when BOFF is set EPVIE Error passive interrupt enable 0 ERRI bit is not set when EPVF is set 1 ERRI bit is set when EPVF is set EWGIE Error warning interrupt enable 0 ERRI bit is not set when EWGF is set 1 ERRI bit is set when EWGF is set CAN transmit error counter register CAN TECR Address offset See Table 71 Reset value 0000 0000 00h 6 5 4 3 2 1 0 TEC 7 0 Bits 7 0 2 TEC 7 0 Transmit error counter In case of an error during transmission this counter is incremented by 8 depending on the error condition as defined by the CAN standard After every successful transmission the counter is decremented by 1 or reset to 0 if the CAN controller exited from bus off to error active state When the counter value exceeds 127 the CAN controller enters th
196. 3 11 0 11 Ly DoclD14587 Rev 12 65 595 Interrupt controller ITC 0016 Table 11 Dedicated interrupt instruction set continued Instruction New description Function example n 10 N Z C JRNM Jump if 11 0 lt gt 11 11 0 lt gt 11 Pop CCR from the stack Memory gt CCR 11 H lO N Z C PUSH CC Push CC on the stack CC gt Memory RIM Enable interrupt level 0 set Load 10 in 11 0 of CCR 1 0 SIM Disable interrupt level 3 set Load 11 in 11 0 of CCR 1 1 TRAP Software trap Software NMI 1 1 WFI Wait for interrupt 1 0 6 8 Interrupt mapping Refer to the corresponding device datasheet for the table of interrupt vector addresses 2 66 595 DoclD14587 Rev 12 RM0016 Interrupt controller ITC 6 9 ITC and EXTI registers 6 9 1 CPU condition code register interrupt bits CCR Address refer to the general hardware register map table in the datasheet Reset value 0x28 7 6 5 4 3 2 1 V 11 H 10 2 r r rw r rw r r r Bits 5 3 1 1 1 0 Software interrupt priority bits These two bits indicate the software priority of the current interrupt request When an interrupt request occurs the software priority of the corresponding vector is loaded automatically from the software priority registers ITC_SPRx The I 1 0 bits can be also set cleared by software using the RIM SIM HA
197. 30000 30120 48 0 40 A6 30075 19 0 25 10A 20000 20000 0 FA 20000 0 190 1 The following table gives the values to be written in the 2 register to obtain the required I C SCL line frequency 312 595 DoclD14587 Rev 12 d 0016 Inter integrated circuit PC interface 21 7 13 TRISE register 2 TRISER Address offset Ox0D Reset value 0x02 7 6 5 4 3 2 1 0 Reserved TRISE 5 0 r nw Bits 7 6 Reserved Bits 5 0 TRISE 5 0 Maximum rise time in Fast Standard mode Master mode 3 These bits should provide the maximum duration of the SCL feedback loop in master mode purpose is to keep a stable SCL frequency whatever the SCL rising edge duration These bits must be programmed with the maximum SCL rise time given in the I2C bus specification incremented by 1 For instance in standard mode the maximum allowed SCL rise time is 1000 ns If the value in the I2C FREQR register 08h then 125 ns therefore the TRISE 5 0 bits must be programmed with 0 09 1000 ns 125 ns 8 1 The filter value can also be added to TRISE 5 0 If the result is not an integer TRISE 5 0 must be programmed with the integer part in order to respect the tyigy parameter Note TRISE 5 0 must be configured only when the I2C is disabled PE 0 DoclD14587 Rev 12 313 595
198. 4 error detection flags Overrun error 3 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART 22 3 d Noise error Frame error Parity error e 6 interrupt sources with flags Transmit data register empty Transmission complete Receive data register full idle line received Overrun error Framing error or noise flag e 2interrupt vectors Transmitter interrupt A Receiver interrupt when register is full e Reduced power consumption mode e Multi Processor communication enter into mute mode if address match does not e Wakeup from mute mode by idle line detection or address mark detection e 2 receiver wakeup modes A Address bit MSB Idle line UART functional description The interface is externally connected to another device by two or three pins see Figure 110 UART1 block diagram Figure 111 UART2 block diagram and Figure 112 UARTS block diagram Any UART bidirectional communication requires a minimum of two pins UART Receive data input UART RX and UART transmit data output UART TX UART RX is the serial data input Over sampling techniques are used for data recovery by discriminating between valid incoming data and noise UART TX is the serial data output When the transmitter is disabled the output pin returns to its port configuration When the transmitter is enabled and nothing is to be transmitted the p
199. 4 register 1 372 Example of filter numbering 4 44 387 Transmit mailbox 0 389 Receive mailbox 390 beCAN behavior in low power 0 5 395 beCAN control and status page register map and reset 421 beCAN mailbox pages register map and reset 421 beCAN filter configuration page register map and reset 422 ADC ed 426 Low power 0 432 ADC Interrupts in single and non buffered continuous mode ADC1 and ADC2 432 ADC interrupts in buffered continuous mode 1 433 ADC interrupts in scan mode 1 434 ADC1 register map and reset values 448 ADC2 register map and reset values 449 Document revision history 1 450 d DoclD14587 Rev 12 RM0016 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figu
200. 4587 Rev 12 2 0016 Clock control CLK Figure 23 Clock switching flowchart manual mode example HARDWARE ACTION SOFTWARE ACTION Y MCU in Run mode with HSI 8 l Set SWIEN bit in CLK_SWCR to enable interrupt if suitable Write target clock source in CLK_SWR Switch busy SWBSY gt 1 Target clock source powered on Target clock source ready after stabilization time Ready for the switch SWIF gt 1 Interrupt if activated Clear SWIF flag Set SWEN bit in CLK_SWCR to execute switch auus Update clock master status CLK SWR gt CLK_CMSR Reset switch busy flag SWBSY gt 0 MCU in Run mode with new master clock source 9 3 Low speed clock selection The Low speed clock source for the AWU or the independent watchdog can be LSI or HSE divided according to the CKAWUSEL option bit Refer to option bytes section in the datasheet The division factor for HSE has to be programmed in the HSEPRSC 1 0 option bits Refer to in the option bytes section of the datasheet The goal is to get 128 kHz at the output of the HSE prescaler 9 4 CPU clock divider The CPU clock fep is derived from the master clock fyasteR divided by a factor programmed in the CPUDIV 2 0 bits in the Clock divider register CLK CKDIVH Seven division factors 1 to 128 in steps of power of 2
201. 4S1 CC4S0 output mode Reset value 0 0 0 0 0 0 0 0 0x0B TIM1_CCMR4 IC4F3 2 IC4F1 IC4FO ICAPSC1 ICAPSCO CC4S1 CC4S0 input mode Reset value 0 0 0 0 0 0 0 0 0x0C TIM1 CCER1 CC2NP CC2NE CC2P CC2E 1 Reset value 0 0 0 0 0 0 0 0 CCER2 CC4E CC3NP CC3NE CC3P CC3E E Reset value 0 0 0 0 0 0 0 0 Ox0E TIM1_CNTRH CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 2 Reset value 0 0 0 0 0 0 0 0 OxOF TIM1 CNTRL CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO Reset value 0 0 0 0 0 0 0 0 0x10 TIM1_PSCRH PSC15 PSC14 PSC13 PSC12 PSC11 PSC10 PSC9 PSC8 Reset value 0 0 0 0 0 0 0 0 0 11 TIM1 PSCRL PSC7 PSC6 PSC5 5 4 5 5 2 PSC1 PSCO Reset value 0 0 0 0 0 0 0 0 Ly DoclD14587 Rev 12 217 595 16 bit advanced control timer TIM1 RM0016 Table 39 TIM1 register map continued Address offset Register name 7 6 5 4 3 2 1 0 TIM1_ARRH ARR15 ARR14 ARR13 ARR12 ARR11 ARR10 ARR9 ARR8 0x12 Reset value 1 1 1 1 1 1 1 1 ds TIM1_ARRL ARR ARR6 ARR5 ARRA ARR2 ARR1 ARRO Reset value 1 1 1 1 1 1 1 1 iu REP7 REP6 REP5 REP4 REP3 REP2 REPO Reset value 0 0 0 0 0 0 0 0 CCR1H 115 CCR114 CCR113 CCR112 111 CCR110 CCR19 CCR18 Reset value 0 0 0 0 0 0 0 0 d CCR1L CCR17 CCR16 CCR15 CCR14 CCR13 CCR12 CCR11 CCR10 Reset value 0 0 0 0 0 0 0 0
202. 5555 Bee Seg eke Bek hee 57 5 2 M in featur s Re PED 57 5 3 SWINMLITIDUBS ORE Sb YEE REESE 57 6 Interrupt controller 58 6 1 ea e 58 6 2 Interrupt masking and processing 58 6 2 1 Servicing pending interrupts 59 6 2 2 Interrupt sources 60 6 3 Interrupts and low power modes 62 6 4 X Activation level low power mode control 62 6 5 Concurrent and nested interrupt 63 6 5 1 Concurrent interrupt management mode 63 6 5 2 Nested interrupt management mode 64 6 6 External interrupts 65 6 7 Interrupt 5 5 65 Ky DoclD14587 Rev 12 3 462 Contents RM0016 6 8 Interrupt mapping 66 6 9 ITC and EXTI registers issues uh eee 67 6 9 1 CPU condition code register interrupt bits CCR 67 6 9 2 Software priority register x ITC 68 6 9 3 External interrupt control register 1 EXTI 1 69 6 9 4 Extern
203. 587 Rev 12 16 bit general purpose timers TIM2 TIM3 TIM5 0016 Figure 83 TIM5 block diagram MASTER TIM1_ETR ETR TRGO to 6 timers CLOCK TRIGGER CONTROLLER TRGO from other TIM timers NTX y TRC gt Clock reset enable TIME BASE UNIT oS nece JP UP DOWN COUNTER Auto reload register v CAPTURE COMPARE ARRAY pu TH EA 1 5 CH1 __ gt Prescaler gt Capture Compare 1 Register AS P 5 CH1 2 OUTPUT INPUT UEV Ic2 Ic2ps UE 2 TIM5 cH2 L gt STAGE gt Prescaler P Capture Compare 2 Register 22 STAGE 902 yrs cu AS ic ps VE Prescaler p Capture Compare 3 Register gt gt P TIM5_CH3 fo shadow registers on undae event UEV according to control bit event Ved interrupt 18 4 1 Time base unit The timer has a time base unit that includes e 16 bit up counter e 16 bit auto reload register e 4 bit programmable prescaler There is no repetition counter The clock source for is the internal clock faster It is connected directly to the PSC clock that feeds the prescaler driving the counter clock CK CONT Figure 84 Time base unit
204. 6 SMCR MSM TS2 TS1 TSO SMS2 SMS1 SMSO Reset value 0 0 0 0 0 0 0 0 6 IER 4 TIE E z 5 2 Reset value 0 0 0 0 0 0 0 0 6 SR1 5 E UIF Reset value 0 0 0 0 0 0 0 0 TIM6 EGR TG UG DXUS Reset value 0 0 0 0 0 0 0 0 0x06 6 CNTR CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO Reset value 0 0 0 0 0 0 0 0 0x07 6 PSCR E PSC2 PSC1 PSCO Reset value 0 0 0 0 0 0 0 0 0x08 6 ARR ARR7 ARR6 5 ARR4 ARR3 ARR2 ARR1 ARRO Reset value 1 1 1 1 1 1 1 1 256 595 DoclD14587 Rev 12 ky RM0016 Serial peripheral interface SPI 20 Serial peripheral interface SPI 20 1 Introduction The serial peripheral interface SPI allows half full duplex synchronous serial communication with external devices The interface can be configured as the master and in this case it provides the communication clock SCK to the external slave device The interface is also capable of operating in multi master configuration It may be used for a variety of purposes including simplex synchronous transfers on 2 lines with a possible bidirectional data line or reliable communication using CRC checking 20 2 SPI main features 2 Full duplex synchronous transfers on 3 lines Simplex synchronous transfers on 2 lines with or without a bidirectional data line Master or slave operation 8 Master mode frequencies fmaster 2 max Slave mode frequency fuAsrER 2 max Faster communication Maximum
205. 7 0 CCR2 15 8 Capture compare 2 value MSB If the CC2 channel is configured as output CC2S bits in TIMx_CCMR2 register The value of CCR2 is loaded permanently into the actual capture compare 2 register if the preload feature is not enabled OC2PE bit in 2 Otherwise the preload value is copied in the active capture compare 2 register when a UEV occurs The active capture compare register contains the value which is compared to the counter register TIMx CNT and signalled on the OC2 output If the CC2 channel is configured as input CC2S bits in TIMx CCMR2 register The value of CCR2 is the counter value transferred by the last input capture 2 event IC2 18 6 24 Capture compare register 2 low TIMx CCR2L Address offset 00x12 or 0x14 TIM2 0x10 0x14 TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 CCR2 7 0 rw rw rw rw rw rw rw rw Bits 7 0 CCR2 7 0 Capture compare value LSB Ly DoclD14587 Rev 12 243 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 6 22 Capture compare register 3 high TIMx CCR3H Address offset 00x13 or 0x15 TIM2 0x15 5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 CCR3 15 8 rw rw rw rw rw rw rw rw Note This register is not available in TIM3 Bits 7 0 CCR3 15 8 Capture compare value MSB If the CC3 channel is configured as output CC3S b
206. 8 OCiREF CCRx 4 OCiREF CCRx 7 8 OCiREF gt 8 OC REF CCRx 0 5 01 5 10 5 11 COUNTER REGISTER 1 2 4 5 6 7 5 4 2 1 0 1 7 CMS 10 or 11 CMS 01 CMS 10 CMS 11 CMS 01 CMS 10 CMS 11 ACA 5 01 A CMS 10 A CMS 11 DoclD14587 Rev 12 3 RM0016 16 bit advanced control timer TIM1 2 One pulse mode One pulse mode OPM is a particular case of the previous modes It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay Starting the counter can be controlled through the clock trigger controller Generating the waveform can be done in output compare mode or PWM mode Select one pulse mode by setting the OPM bit in the TIM1 register This makes the counter stop automatically at the next UEV A pulse can be correctly generated only if the compare value is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be e up counting CNT CCRi lt ARR in particular 0 lt e down counting CNT gt CCRi Figure 72 Example of one pulse mode 2 OC1REF OC1 A TIMx_ARR TIMx_CCR1
207. 8 bytes each The Flash program memory is divided into 2 areas the user boot code area UBC which size can be configured by option byte and the main program memory area The Flash program memory is mapped in the upper part of the STM8S addressing space and includes the reset and interrupt vectors Up to 2 Kbytes of data EEPROM DATA organized in up to 4 pages of 4 blocks of 128 bytes each The size of the DATA area is fixed for a given microcontroller One block 128 bytes contains the option bytes of which 15 are used to configure the DoclD14587 Rev 12 Ly RM0016 Flash program memory and data EEPROM Note 2 device hardware features The options bytes be programmed in user IAP and ICP SWIM modes e High density STM8AF devices From 32 to 128 Kbytes of Flash program memory organized in up to 256 pages of 4 blocks of 128 bytes each The Flash program memory is divided into 2 areas the user boot code area UBC which size can be configured by option byte and the main program memory area The Flash program memory is mapped in the upper part of the STM8AF addressing space and includes the reset and interrupt vectors Up to 2 Kbytes of data EEPROM DATA organized in up to 4 pages of 4 blocks of 128 bytes each The size of the DATA area is fixed for a given microcontroller One block 128 bytes contains the option bytes of which 15 are used to configure the device hardware features The options bytes can be program
208. 87 Rev 12 215 595 16 bit advanced control timer TIM1 RM0016 17 7 32 7 Output idle state register TIM1 OISR Address offset Ox1F Reset value 0x00 Reserved 0154 OIS3N 0153 OIS2N 0152 OIS1N 0151 r Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 216 595 Reserved forced by hardware to 0 0154 Output idle state 4 OC4 output Refer to OIS1 bit OIS3N Output idle state 3 OC3N output Refer to OIS1N bit OIS3 Output idle state 3 OC3 output Refer to OIS1 bit OIS2N Output idle state 2 OC2N output Refer to OIS1N bit OIS2 Output idle state 2 OC2 output Refer to OIS1 bit OIS1N Output idle state 1 OC1N output 0 OCAN 0 after a deadtime when MOE 0 1 1 1 after a deadtime when MOE 0 Note This bit can no longer be modified while LOCK level 1 2 or 3 have been programmed LOCK bits in the TIM1 register OIS1 Output idle state 1 OC1 output 0 OC1 0 after a deadtime if OC1N is implemented when 0 1 OC1 1 after a deadtime if OC1N is implemented when 0 Note This bit can no longer be modified while LOCK level 1 2 or 3 have been programmed LOCK bits in the TIM1 register DoclD14587 Rev 12 d RM0016 16 bit advanced control timer TIM1 17 7 33 TIM1 register map and reset values Table 39 TIM1 register map
209. 9 595 Inter integrated circuit 2 interface 0016 290 595 register see Figure 104 amp Figure 105 Transfer sequencing EV6 In 7 bit addressing mode one address byte is sent As soon as the address byte is sent The ADDR bit is set by hardware and an interrupt is generated if the ITEVTEN bit is set Then the master waits for a read of the SR1 register followed by a read in the SR3 register see Figure 104 amp Figure 105 Transfer sequencing EV6 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent In 7 bit addressing mode enter Transmitter mode a master sends the slave address with LSB reset enter Receiver mode a master sends the slave address with LSB set In 10 bit addressing mode enter Transmitter mode a master sends the header 11110xx0 and then the slave address where xx denotes the two most significant bits of the address To enter Receiver mode a master sends the header 11110xx0 and then the slave address Then it should send a repeated Start condition followed by the header 11110xx1 where xx denotes the two most significant bits of the address The TRA bit indicates whether the master is in Receiver or Transmitter mode 2 DoclD14587 Rev 12 0016 Inter integrated circuit PC interface Master transmitter Following the address transmission and after clearing ADDR the master sends byt
210. AN register cleared the last message stored in the FIFO will be overwritten by the new incoming message As a result the last message is always available to the application The previously received messages will stay in their positions in the FIFO only the last one will be overwritten Ifthe FIFO lock function is enabled RFLM bit in the CAN register set the most recent message will be discarded and the software will have the three oldest messages in the FIFO available Reception related interrupts On the storage of the first message in the FIFO FMP 1 0 bits change from 0000 to 0b01 an interrupt is generated if the FMPIE bit in the CAN IER register is set When the FIFO becomes full i e a third message is stored the FULL bit in the CAN RFR register is set and an interrupt is generated if the FFIE bit in the CAN IER register is set On overrun condition the FOVR bit is set and an interrupt is generated if the FOVIE bit in the CAN IER register is set Identifier filtering In the CAN protocol the identifier of a message is not associated with the address of a node but related to the content of the message Consequently a transmitter broadcasts its message to all receivers On message reception a receiver node decides depending on the identifier value whether the software needs the message or not If the message is needed it is copied into the RAM If not the message must be discarded without intervention b
211. ART 0016 344 462 LIN break and delimiter detection The UART features a break detection circuit which is totally independent from the normal UART receiver A break can be detected whenever it occurs during idle state or during a frame When the receiver is enabled REN 1 in UART CR2 the circuit looks at the UART input for a start signal The method for detecting start bits is the same when searching break characters or data After a start bit has been detected the circuit samples the next bits exactly like for the data on the 8th 9th and 10th samples If 10 bits when the LBDL 0 in CR4 or 11 bits when LBDL 1 in CR4 are detected as 0 and are followed by a delimiter character the LBDF flag is set in UART If the LBDIEN bit 1 an interrupt is generated If a 1 is sampled before the 10 or 11 have occurred the break detection circuit cancels the current detection and searches for a start bit again If LIN mode is disabled LINEN 0 the receiver continues working as a normal UART without taking into account the break detection If LIN mode is enabled LINEN 1 as soon as a framing error occurs i e stop bit detected at 0 which will be the case for any break frame the receiver stops until the break detection circuit receives either a 1 if the break word was not complete or a delimiter character if a break has been detected The behavior of the break detector state mac
212. BOFF bit in ESR register In Bus Off state the beCAN is no longer able to transmit and receive messages Depending on the ABOM bit in the CAN register will recover from Bus Off become error active again either automatically or on software request But in both cases the beCAN has to wait at least for the recovery sequence specified in the CAN standard 128 x 11 consecutive recessive bits monitored on CANRX If ABOM is set the will start the recovering sequence automatically after it has entered Bus Off state If ABOM is cleared the software must initiate the recovering sequence by requesting beCAN to enter initialization mode Then beCAN starts monitoring the recovery sequence when the beCAN is requested to leave the initialization mode In initialization mode beCAN does not monitor the signal therefore it cannot complete the recovery sequence To recover beCAN must be in normal mode Figure 153 CAN error state diagram When TEC or REC 127 ERROR ACTIVE ERROR PASSIVE When TEC and REC 128 When 128 11 recessive bits occur When TEC 255 DoclD14587 Rev 12 391 462 Controller area network beCAN 0016 23 6 6 Bit timing The bit timing logic monitors the serial bus line and performs sampling and adjustment of the sample point by synchronizing on the start bit edge and resynchronizing on the following edges Its operation may be explained simpl
213. BSY bit will never be reset between each data transfer On the contrary if the software is not fast enough this can lead to some discontinuities in the communication In this case the BSY bit is reset between each data transmission see Figure 99 In master receive only mode BDM 0 and RXONLY 1 or in bidirectional receive mode BDM 1 and BDOE 0 the communication is always continuous and the BSY flag is always read at 1 In slave mode the continuity of the communication is decided by the SPI master device But even if the communication is continuous the BSY flag goes low between each transfer for a minimum duration of one SPI clock cycle see Figure 95 DoclD14587 Rev 12 269 595 Serial peripheral interface SPI 0016 Figure 99 TXE BSY behavior when transmitting BDM 0 RXLONY 0 Case of discontinuous transfers vost ou oo e es ese e Teo gu water Lay oF Example with CPOL 1 CPHA 1 SCK DATA 1 OxF1 DATA 2 OxF2 DATA 3 OxF3 TXE flag BSY flag software writes OxF1 software waits until 1 software waits until 1 Software waits software waits until into SPI DR but is late to write OxF2 into but is late to writes OXF3 until 1 BSY 0 SPI DR into SPI DR 20 3 6 CRC calculation 270 595 A CRC calculator has been implemented for communication reliability
214. C clock The clock supplied to the ADC can by a prescaled fyyaster clock The prescaling factor of the clock depends on the SPSEL 2 0 bits in the CR1 register 2 DoclD14587 Rev 12 RM0016 Analog digital converter ADC 24 5 3 24 5 4 Note d Channel selection There are up to 16 external input channels that can be selected through CH 0 3 bits of the ADC_CSR register The number of external channels depends on the device refer to the product datasheets If the channel selection is changed during a conversion the current conversion is reset and a new start pulse is sent to the ADC Conversion modes The ADC supports five conversion modes single mode continuous mode buffered continuous mode single scan mode continuous scan mode ADC1 AIN12 channel cannot be selected in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only in the ADC_DRH ADC_DRL registers Refer to product datasheet for AIN12 availability Single mode In Single conversion mode the ADC does one conversion on the channel selected by the CH 3 0 bits in the register This mode is started by setting the ADON bit in the ADC CR1 register while the CONT bit is 0 Once the conversion is complete the converted data are stored in the ADC_DR register the EOC End of Conversion flag is set and an interrupt is generated if the EOCIE bit is set Continuous and buffered continuous modes In con
215. CC4IE Capture compare 4 interrupt enable 0 CCA interrupt disabled 1 CC4 interrupt enabled CC3IE Capture compare 3 interrupt enable 0 CC3 interrupt disabled 1 CC3 interrupt enabled CC2IE Capture compare 2 interrupt enable 0 CC2 interrupt disabled 1 CC2 interrupt enabled Capture compare 1 interrupt enable 0 CC1 interrupt disabled 1 CC1 interrupt enabled UIE Update interrupt enable 0 Update interrupt disabled 1 Update interrupt enabled DoclD14587 Rev 12 d RM0016 16 bit advanced control timer TIM1 17 7 6 Status register 1 TIM1_SR1 Address offset 0x05 Reset value 0x00 6 5 BIF TIF COMIF CCAIF CCSIF CC2IF CC1IF UIF rc wO rc 0 rc 0 0 rc 0 rc wO rc wO rc wO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 3 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active It can be cleared by software if the break input is not active 0 No break event has occurred 1 An active level has been detected on the break input TIF Trigger interrupt flag This flag is set by hardware on a trigger event the active edge is detected on a TRGI signal both edges are detected if trigger gated mode is selected It is cleared by software 0 No trigger event has occurred 1 Trigger interrupt pending COMIF Commutation interrupt flag This flag is set by hardware on a COM
216. CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 Reset value 0 0 0 0 0 0 0 0 0x0B 2 CNTRL CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO Reset value 0 0 0 0 0 0 0 0 TIM2_PSCR PSC3 PSC2 5 5 0 0x0C Reset value 0 0 0 0 0 0 0 0 0x0D OxOF TIM2 ARRH ARR15 ARR14 ARR13 ARR12 ARR11 ARR10 ARR9 ARR8 5 2 Reset value 1 1 1 1 1 1 1 1 Ox0E 0x10 TIM2 ARRL ARR7 ARR6 ARR5 ARR4 ARR3 ARR2 ARR1 ARRO 2 Reset value 1 1 1 1 1 1 1 1 OxOF 0 11 2 CCR1H CCR115 CCR114 CCR113 CCR112 CCR111 CCR110 19 CCR18 5 Reset value 0 0 0 0 0 0 0 0 0x10 0x12 TIM2 CCR1L CCR17 CCR16 CCR15 CCR14 CCR13 CCR12 CCR11 CCR10 E Reset value 0 0 0 0 0 0 0 0 0 11 0x13 TIM2 CCR2H CCR215 CCR214 CCR213 CCR212 CCR211 CCR210 CCR29 CCR28 Reset value 0 0 0 0 0 0 0 0 0x12 0x14 TIM2 CCR2L CCR27 CCR26 CCR25 CCR24 CCR23 CCR22 CCR21 CCR20 Reset value 0 0 0 0 0 0 0 0 0x13 0x15 2 CCR3H CCR315 CCR314 CCR313 CCR312 CCR311 CCR310 CCR39 CCR38 Reset value 0 0 0 0 0 0 0 0 0x14 0x16 TIM2 CCR3L CCR37 CCR36 CCR35 CCR34 CCR33 CCR32 CCR31 CCR30 Reset value 0 0 0 0 0 0 0 0 ky DoclD14587 Rev 12 245 595 16 bit general purpose timers TIM2 TIM3 TIM5 RM0016 Table 41 TIM3 register map Address offset Register name 7 6 5 4 3 2 1 0 m CR1 ARPE 2 URS UDIS CEN Reset value 0 0 0 0 0 0 0 0 did TIM3 IER gt s CC2IE 1
217. CR34 CCR33 CCR32 CCR31 CCR30 Reset value 0 0 0 0 0 0 0 0 DoclD14587 Rev 12 247 595 8 bit basic timer TIM4 TIM6 RM0016 19 8 bit basic timer TIM4 TIM6 19 1 Introduction The timer consists of an 8 bit auto reload up counter driven by a programmable prescaler It can be used for time base generation with interrupt generation on timer overflow TIM6 is implemented with the clock trigger controller for timer synchronization and chaining Refer to Section 17 3 on page 140 for the general description of the timer features Figure 89 TIM4 block diagram TIME BASE UNIT UEV b Auto reload register UIF Stop or Clear UEV 5 CK CNT MASTER rescaler UP COUNTER Legend Preload registers transferred to shadow registers on update event UEV according to control bit event nena Figure 90 TIM6 block diagram fMASTER M ye CLOCK TRIGGER CONTROLLER TIM1 TIMS timers TRGO from TIMS ITR2 ITR TRC TRGI TRGO from TIM1 ITR3 TIME BASE UNIT UEV Auto reload register UIF Legend t Preload registers transferred UEV 10 shadow registers on update event UEV according to CK PSC CK CNT UP COUNTER control bit event enun 3 248 595 DoclD14587 Rev 12 0016 8
218. CRC error This flag is used to verify the correctness of the value received when the CRCEN bit in the SPI CR register is set The CRCERR flag in the SPI SR register is set if the value received in the shift register after the SPI TXCRCR value transmission does not match the SPI RXCRCR value Refer to Chapter 20 3 6 CRC calculation 2 DoclD14587 Rev 12 RM0016 Serial peripheral interface SPI 20 3 10 SPI low power modes 20 3 11 d Table 45 SPI behavior in low power modes Mode Description No effect on SPI wen SPI interrupt events cause the device to exit from Wait mode SPI registers are frozen In Halt mode the SPI is inactive If the SPI is in master mode then communication resumes when the device is woken up by an interrupt with wakeup from Halt mode capability If the SPI is in slave mode then it can wake up the MCU from Halt mode after Halt detecting the first sampling edge of data Using the SPI to wake up the device from Halt mode When the microcontroller is in Halt mode the SPI is still capable of responding as a slave provided the NSS pin is tied low or the SSI bit is reset before entering Halt mode When the first sampling edge of data as defined by the CPHA bit is detected e The WKUP bit is set in the SPI SR register e An interrupt is generated if the WKIE bit in the SPI ICR register is set e This interrupt wakes up the device from Halt mode e Due to the time
219. Depending on the frequency and prescaler value the period in the TIM1 1 register can be measured and the duty cycle in the TIM1 CCR2 register of the PWM can be applied on TI1 using the following procedure 1 Selectthe active input capture or trigger input for TIM1 by writing the CC1S bits to 01 in the TIM1_CCMR1 register selected 2 Select the active polarity for used for both capture and counter clear in TIMx 1 by writing the CC1P bit to 0 active on rising edge 3 Select the active input for TIM1 CCR2 by writing the CC2S bits to 10 in the TIM1 CCMR2 register TI1FP2 selected 4 Select the active polarity for TI1FP2 used for capture in TIM1 CCR2 by writing the CC2P bit to 1 TI1FP2 active on falling edge 5 Select the valid trigger input by writing the TS bits to 101 in the TIM1 SMCR register TH FP1 selected 6 Configure the clock trigger controller in reset mode by writing the SMS bits to 100 in the TIM1 SMCR register 7 Enable the captures by writing the CC1E and CC2E bits to 1 in the TIM1 CCER1 register 168 595 DoclD14587 Rev 12 2 0016 16 bit advanced control timer TIM1 Figure 66 PWM input signal measurement example TH CNT 0004 oo X 00 X 002 Jloos X X 0000 X CCR1 i 0004 TIM1_CCR2 0002 Capture 2 Capture period measurement pulse width measu
220. EVTEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing the DR register EV6 ADDR1 cleared by reading SR1 register followed by reading SR3 In 10 bit master receiver mode this sequence should be followed by writing CR2 with START 1 EV6 1 No associated flag event The acknowledge should be disabled just after EV6 that is after ADDR is cleared EV7 3 BTF 1 program STOP 1 read DR twice Read Data1 and Data2 just after programming the STOP EV9 ADD10 1 cleared by reading SR1 register followed by writing DR register EV5 EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence 3 EV6 1 software sequence must be completed before the ACK pulse of the current byte transfer Figure 108 Method 2 transfer sequence diagram for master receiver when 1 7 bit master receiver S Address A Data1 P EV6 3 EV7 10 bit master receiver 5 Header A Address A EV5 EV9 EV6 5 Header A Data1 5 6 3 1 Legend S Start S Repeated Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITEVTEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing the DR register EV6 ADDR 1 cleared by reading SR1 resister followed by reading SR3 register EV6 3 ADDR 1 program
221. FP4 10 CC4 channel is configured as input IC4 is mapped on TI3FP4 11 Reserved Note CCAS bits are writable only when the channel is off and CC4NE 0 and updated in CCER2 2 202 595 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 17 7 13 Capture compare enable register 1 TIM1 1 Address offset 0 0 Reset value 0x00 7 6 5 4 3 2 1 0 CC2NP CC2NE CC2P CC2E 1 rw rw rw rw rw rw rw rw Bit 7 CC2NP Capture compare 2 complementary output polarity Refer to CC1NP description Bit 6 CC2NE Capture compare 2 complementary output enable Refer to CC1NE description Bit 5 CC2P Capture compare 2 output polarity Refer to CC1P description Bit 4 CC2E Capture compare 2 output enable Refer to CC1E description Bit 3 CC1NP Capture compare 1 complementary output polarity 3 0 OCAN active high 1 OCIN active low Note This bit is no longer writable while LOCK level 2 or 3 have been programmed LOCK bits in TIM1 BKR register and 15 00 the channel is configured in output On channels that have a complementary output this bit is preloaded If the CCPC bit is set in the 2 register the CC1NP active bit takes the new value from the preload bit only when a COM is generated DoclD14587 Rev 12 203 595 16 bit advanced control timer TIM1 0016 Bit 2 CC1NE Capture compare 1 comple
222. IDR3 5 F2R5 F4R5 0 05 MIDR4 MIDR4 FOR6 CAN F2R6 CAN F4R6 0x06 MDAR1 CAN MDAR1 CAN FOR7 CAN F2R7 CAN 0x07 MDAR2 MDAR5 CAN 8 CAN F2R8 CAN F4R8 0 08 MDAR3 MDAR6 CAN F1R1 CAN F3R1 CAN F5R1 0x09 MDAR4 CAN MDAR4 CAN F1R2 CAN F3R2 CAN F5R2 0x0A MDARS5 5 CAN F1R3 CAN F3R3 CAN F5R3 0 08 MDAR6 MDAR6 1 4 CAN F3R4 CAN F5R4 Ox0C MDAR7 MDAR7 1 5 CAN F3R5 CAN F5R5 0 00 MDARB MDAR8 CAN F1R6 CAN F3R6 CAN F5R6 0 0 MTSRL MTSRL CAN F1R7 CAN F3R7 CAN F5R7 Ox0F CAN_MTSRH CAN_MTSRH CAN_F1R8 CAN_F3R8 CAN_F5R8 Tx Mailbox 0 Tx Mailbox 1 Acceptance Filter 0 1 Acceptance Filter 2 3 Acceptance Filter 4 5 PAGE 5 PAGE 6 PAGE 7 0x00 CAN_MCSR CAN_ESR CAN_MFMIR MDLCR EIER MDLCR Une CAN MIDR1 TECR CAN MIDR1 0x03 MIDR2 CAN RECR CAN MIDR2 0x04 CAN MIDR3 CAN BTR1 CAN MIDR3 0x05 MIDRA CAN BTR2 MIDR4 0x06 MDAR Reserved MDAR1 0x07 MDAR2 Reserved MDAR2 0x08 MDAR3 FMR1 CAN MDAR3 099 MDAR4 FMR2 MDAR4 MDARS FCRI MDARS 0x0B CAN_MDAR6 CAN_FCR2 CAN MDARG 0x0C MDAR7 FCR3 MDAR7 0 00 MDAR8 Reserved MDARB Ox0E MTSRL Reserved CAN MTSRL Ox0F MTSRH Reserved
223. IFO This bit can be cleared by software writing 1 or by releasing the FIFO by means of RFOM Bit 2 Reserved Bits 1 0 FMP 1 0 FIFO Message Pending These bits indicate how many messages are pending in the receive FIFO FMP is increased each time the hardware stores a new message in to the FIFO FMP is decreased each time the FIFO output mailbox has been released by hardware RFOM bit has been cleared after prior setting by software 3 DoclD14587 Rev 12 401 462 Controller area network beCAN 0016 23 11 6 CAN interrupt enable register CAN IER Address offset 0x05 Reset value 0x00 7 6 5 4 3 2 1 0 WKUIE Reserved FOVIE FFIE FMPIE TMEIE rw r rw rw rw rw Bit 7 WKUIE Wakeup Interrupt Enable 0 No interrupt when WKUI is set 1 Interrupt generated when WKUI bit is set Bit 6 4 Reserved Bit 3 FOVIE FIFO Overrun Interrupt Enable 0 No interrupt when FOVR bit is set 1 Interrupt generated when FOVR bit is set Bit 2 FFIE FIFO Full Interrupt Enable 0 No interrupt when FULL bit is set 1 Interrupt generated when FULL bit is set Bit 1 FMPIE FIFO Message Pending Interrupt Enable 0 No interrupt on FMP 1 0 bits transition from 0600 to 0001 1 Interrupt generated on FMP 1 0 bits transition from 0000 to 0601 BitO TMEIE Transmit Mailbox Empty Interrupt Enable 0 No interrupt when RQCPx bit is set 1 Interrupt generated when bit is set 402 462 DoclD14587 Rev 12 Ly 0016 Co
224. IM1 SR1 register and an interrupt request can be sent if enabled depending on the TIE bit in the TIM1 IER register The delay between the rising edge on TI2 and the actual reset of the counter is due to the resynchronization circuit on TI2 input Figure 46 Control circuit in external clock mode 1 T2 0 COUNTER CLOCK CK CONT CK PSC COUNTER REGISTER 34 35 36 Write TIF 0 LE M TIF 3 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 4 4 d External clock source mode 2 The counter can count at each rising or falling edge on the ETR This mode is selected by writing 1 in the ETR register The Figure 47 gives an overview of the external trigger input block Figure 47 External trigger input block diagram or A orv io TIF TRGI A external clock _ 5 ETR 0 P divider EIRP filter ETRF external clock A 2 4 8 fwaster _ down counter 1 linternal clock _ mode internal clock ETP ETPS 1 0 ETF 3 0 TIM1 ETR TIM1 ETR TIM1 ETR SMS 2 0 TIM1 TIM1 SMCR Procedure Use the following procedure to configure the up counter and for example to count once every two rising edges o
225. In case software sequence can not be managed before the end of the current byte transfer it is recommended to use BTF instead of TXE with the drawback of slowing the communication Slave receiver Following the address reception and after clearing ADDR the slave receives bytes from the SDA line into the DR register via the internal shift register After each byte the interface generates in sequence e Anacknowledge pulse if the ACK bit is set e The RXNE bit is set by hardware and an interrupt is generated if the ITEVTEN and ITBUFEN bit is set If RXNE is set and the data in the DR register is not read before the end of the next data reception the BTF bit is set and the interface waits until BTF is cleared by reading the SR1 register and then reading the DR register stretching SCL low see Figure 103 DoclD14587 Rev 12 287 595 Inter integrated circuit 2 interface 0016 21 4 2 288 595 Figure 103 Transfer sequence diagram for slave receiver T bit slave receiver 5 Address A Data A Data2 A Datan A P EV2 EV2 Ev2 4 10 bit slav e receiver s Header A Address A Data1 A DataN A P Ev2 0 EV2 Ev4 MS37719V1 1 Legend S Start S Repeated Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITEVTEN 1 EV1 ADDR 1 cleared
226. Interrupt register map Add Register 3 7 6 5 4 3 2 1 0 offset name ITC SPR block SPR1 VECT3 VECT3 VECT2 VECT2 VECT1 VECT1 Reserved Reserved 0x00 SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 SPR2 VECT7 VECT7 VECT6 VECT6 VECT5 VECT5 VECT4 VECT4 0x01 SPR1 SPRO SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 VECT11 VECT11 VECT10 VECT10 VECT9 VECT9 VECT8 VECT8 0x02 SPR1 SPRO SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 ITC_SPR4 VECT15 VECT15 VECT14 VECT14 VECT13 VECT13 VECT12 VECT12 0x03 SPR1 SPRO SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 SPR5 VECT19 VECT19 VECT18 VECT18 VECT17 VECT17 VECT16 VECT16 0x04 SPR1 SPRO SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 SPR6 VECT23 VECT23 VECT22 VECT22 VECT21 VECT21 VECT20 VECT20 0x05 SPR1 SPRO SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 SPR7 VECT27 VECT27 VECT26 VECT26 VECT25 VECT25 VECT24 VECT24 0x06 SPR1 SPRO SPR1 SPRO SPR1 SPRO SPR1 SPRO Reset value 1 1 1 1 1 1 1 1 SPR8 VECT28 VECT28 0x07 SPR1 SPRO Reset value 1 1 ITC EXTI block 2 0 00 CR1 PDIS1 PDISO PCIS1 PCISO PBIS1 PBISO PAIS1 PAISO Reset value 0 0 0 0 0 0 0 0 Ox01 EXTI CR2 TLIS PEIS1 PEISO Reset value 0 0 0 0 0 0 0 0 1 The address offsets are expressed for the ITC SPR block base address see CPU SWIM
227. LT WFI IRET or PUSH POP instructions see Figure 16 Nested interrupt management l1 10 Priority Level 1 0 Level 0 main Low 0 1 Level 1 0 0 Level 2 High 1 1 Level 3 2 software priority disabled 1 Refer to the central processing section for details on the other CCR bits 2 TLI TRAP and RESET events can interrupt a level 3 program 3 DoclD14587 Rev 12 67 595 Interrupt controller ITC 0016 6 9 2 Software priority register x SPRx Address offset 0x00 to 0x07 Reset value OxFF 7 6 5 4 3 2 1 0 ITC SPR1 VECTSSPR 1 0 VECT2SPR 1 0 VECTI1SPR 1 0 VECTOSPR 1 0 ITC_SPR2 VECT7SPR 1 0 VECT6SPR 1 0 VECTSSPR 1 0 VECT4SPR 1 0 ITC_SPR3 VECT11SPR 1 0 VECT10SPR 1 0 VECT9SPR 1 0 VECT8SPR 1 0 ITC_SPR4 VECT15SPR 1 0 VECT14SPR 1 0 VECT13SPR 1 0 VECT12SPR 1 0 ITC SPR5 VECT19SPR 1 0 VECT18SPR 1 0 VECT17SPR 1 0 VECT16SPR 1 0 SPR6 VECT23SPR 1 0 VECT22SPR 1 0 VECT21SPR 1 0 VECT20SPR 1 0 SPR7 VECT27SPR 1 0 VECT26SPR 1 0 VECT25SPR 1 0 VECT24SPR 1 0 ITC SPR8 Reserved VECT29SPR 1 0 VECT28SPR 1 0 rw rw rw rw rw Bits 7 0 VECTXSPR 1 0 Vector x software priority bits These eight read write registers SPR1 to SPR8 are written by software to define the software priority of each interrupt vector The list of vectors is given in Table 10 Vector address map versus software priority bits Refer to Section 6
228. LT WAIT 1 The 15 clock source is selected by programming the CKAWUSEL option bit as explained in the clock controller chapter DoclD14587 Rev 12 113 462 Auto wakeup AWU 0016 12 3 12 3 1 Note 114 462 AWU functional description AWU operation To use the AWU perform the following steps in order 1 Measure the LS clock frequency using the bit in AWU register and TIM3 or TIM1 input capture 1 2 Define the appropriate prescaler value by writing to the APR 5 0 bits in the Asynchronous prescaler register AWU APR 3 Select the desired auto wakeup delay by writing to the AWUTB S3 0 bits in the Timebase selection register 4 Setthe AWUEN bit in the Control status register 5 Execute the HALT instruction AWU counters are reloaded and start to count a new AWU time interval The counters only start when the MCU enters Active halt mode after a HALT instruction refer to the Active halt mode section in the power management chapter The AWU interrupt is then enabled at the same time The prescaler counter starts to count only if APR 5 0 value is different from its reset value Idle mode If the AWU is not in use then the AWUTB 3 0 bits the Timebase selection register AWU_TBR should be loaded with 000000 to reduce power consumption DoclD14587 Rev 12 2 RM0016 Auto wakeup AWU 12 3 2 Note d Time base sele
229. MCR registers are not implemented in 2 only in TIM5 Refer to Section 17 4 TIM1 clock trigger controller on page 150 2 DoclD14587 Rev 12 0016 16 bit general purpose timers 2 TIM3 5 18 4 3 Capture compare channels Input stage Refer to Section 17 5 TIM1 capture compare channels on page 164 There are two input channels as shown in Figure 85 Input stage block diagram Figure 85 Input stage block diagram TMF ED TRC to clock trigger controller TH Filter amp CH1 3L Filter THEP2 Edge Detector TRC TI2FP1 H h IC2 TI2 Input Filter amp TIMx CH2 gt Edge Detector TI2FP2 t to capture compare channels N Ica Input Filter amp TIMx CH8 O gt x Edge Detector Figure 86 Input stage of TIM 2 channel 1 THF ED to the clock trigger controller TH THF rising filter THF Edge down counter Detector TIF falling divider 1 12 14 18 ICF 3 0 2 CCMR1 TIM2 CCER1 TI2F rising uve ee f from channel 2 7 7 TI2F_falling 15 1 0 ICPS 1 0 CC1E from channel 2 TIM2 CCMR1 2 CCER1 2 DoclD14587 Rev 12 223 595 16 bit general purpose timers TIM2 TIM3 TIM5
230. Only the receiver is activated and the received data on MISO pin is shifted in serially to the 8 bit shift register and then parallel loaded into the SPI DR register Rx Buffer In bidirectional mode when transmitting BDM 1 and BDOE 1 The sequence begins when a data is written into the SPI DR register Tx buffer The data is then parallel loaded from the Tx buffer into the 8 bit shift register during the first bit transmission and then shifted out serially to the MOSI pin No data is received In bidirectional mode when receiving BDM 1 and BDOE 0 The sequence begins as soon as SPE 1 and BDOE 0 The received data on MOSI pin is shifted in serially to the 8 bit shift register and then parallel loaded into the SPI DR register Rx Buffer The transmitter is not activated and no data is shifted out serially to the MOSI pin Start sequence in slave mode In full duplex BDM 0 and RXONLY 0 264 595 The sequence begins when the slave device receives the clock signal and the first bit of the data on its MOSI pin The remaining 7 bits are loaded into the shift register At the same time the data is parallel loaded from the Tx buffer into the 8 bit shift register during the first bit transmission and then shifted out serially to the MISO pin The software must have written the data to be sent before the master device initiates the transfer In unidirectional receive only mode BDM 0 and RXONLY 1 The sequ
231. Over sampling techniques are used for data recovery by discriminating between valid incoming data and noise 3 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Figure 118 Data sampling for noise detection RX LINE LOT Wow L X db od d sampled values we4ltttttt1A3t amp th St sh 6 16 gt 7 16 7 16 One bit time gt Note The sample clock frequency is 16x baud rate Ly DoclD14587 Rev 12 329 462 Universal asynchronous receiver transmitter UART 0016 330 462 Table 53 Noise detection from sampled data Sampled value NF status Received bit value Data validity 000 0 0 Valid 001 1 0 Not Valid 010 1 0 Not Valid 011 1 1 Not Valid 100 1 0 Not Valid 101 1 1 Not Valid 110 1 1 Not Valid 111 0 1 Valid When noise is detected in a frame e The NF is set at the rising edge of the RXNE bit e invalid data is transferred from the Shift register to the UART DR register This bit rises at the same time as the RXNE bit which generates an interrupt The NF bit is reset by a UART SR register read operation followed by a UART DR register read operation Framing error A framing error is detected when The stop bit is not recognized on reception at the expected time following either a de synchronization or excessive noise When the framing error is detected e T
232. R page 55 Added note to Section 9 1 2 HSI Updated Table 17 UART peripheral clock gating bit description moved to datasheet Updated Table 20 Low power mode management on page 101 Updated management of hardware interrupts in Section 6 1 ITC introduction Removed interrupt vector table moved to datasheet d DoclD14587 Rev 12 451 462 Revision history RM0016 452 462 Table 79 Document revision history continued Date 10 Aug 2009 Revision Changes Changed note in Section 6 9 2 Software priority register x ITC_SPRx on page 68 Updated AWU Section 12 3 2 Time base selection Removed description of timer input feature TI1S bit in Section 17 and Section 18 Updated trigger selection for and ETR description for TIM5 in Section 18 Updated MMS bits in Control register 2 TIM5 CR2 and Control register 2 TIMG CR2 Updated TG bit of Event generation register TIMx EGR Added note on TIM2 and TIM4 register offsets inSection on page 244 and Section 19 6 10 on page 255 Section 21 4 3 Acknowledge failure AF Added repeated start to master condition Modified Section 21 7 3 Frequency register I2C_FREQR on page 302 Added 6th step to UART Character transmission Updated UART Single byte communication Added Figure 116 TC TXE behavior when transmitting Updated TC bit description in Section 22 7 1 Status register UART_SR Added Siart bit det
233. R DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO Reset Value x x x x x x x 0 02 UART2 UART DIV 11 4 Reset Value 00000000 0x03 UART2_BRR2 UART_DIV 15 12 UART_DIV 3 0 x Reset Value 0000 0000 0 04 UART2 CR1 R8 T8 UARTD M WAKE PCEN PS PIEN Reset Value 0 0 0 0 0 0 0 0 ids UART2 CR2 TIEN TCIEN RIEN ILIEN TEN REN RWU SBK i Reset Value 0 0 0 0 0 0 0 0 UART2 LINEN STOP CKEN CPOL CPHA LBCL x Reset Value 0 0 00 0 0 0 0 370 462 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART Table 62 UART2 register map continued Register Address g 7 6 5 4 3 2 1 0 0 07 UART2 CR4 LBDIEN LBDL LBDF ADD 3 0 Reset Value 0 0 0 0 0000 0908 UART2 CR5 SCEN NACK IRLP IREN Reset Value 0 0 0 0 0 0 0 0 0x09 UART2 CR6 LDUM LSLV LASE LHDIEN LHDF LSF Reset Value 0 0 0 0 0 0 0 0 Ox0A UART2 GTR GT7 GT6 GT5 GT4 GT3 GT2 GT1 GTO Reset Value 0 0 0 0 0 0 0 0 0x0B UART2 PSCR PSC7 PSC6 PSC5 PSC4 PSC3 PSC2 PSC1 PSCO Reset Value 0 0 0 0 0 0 0 0 Table 63 UART3 register map Register Address 9 7 6 5 4 3 2 1 0 name 0x00 UART3_SR TXE TC RXNE IDLE OR NF FE PE Reset Value 1 1 0 0 0 0 0 0 UART3 DR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO i Reset Value x x x x x x x 0x02 UART3_BRR1 UART_DIV 11 4 Reset Value 00000000 0x03 UART3_BRR2 UART_DIV 15 12 UART_DIV 3 0 i Reset V
234. R4 ODR3 ODR2 ODR1 ODRO Reset value 0 0 0 0 0 0 0 0 Px IDR IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDRO 0x01 Reset value x x x x x x X x Px DDR DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDRO Reset value 0 0 0 0 0 0 0 0 ds Px_CR1 C17 C16 C15 C14 C13 C12 c11 C10 Reset value 0 0 0 0 0 0 0 0 T Px CR2 C27 C26 C25 C24 C23 C22 C21 C20 Reset value 0 0 0 0 0 0 0 0 1 PD reset value is 0x02 112 595 DoclD14587 Rev 12 3 RM0016 Auto wakeup AWU 12 12 1 12 2 d Auto wakeup AWU Introduction The AWU is used to provide an internal wakeup time base that is used when the MCU goes into Active halt power saving mode This time base is clocked by the low speed internal LSI RC oscillator clock or the HSE crystal oscillator clock divided by a prescaler LSI clock measurement To ensure the best possible accuracy when using the LSI clock its frequency can be measured with or TIM1 timer input capture 1 see datasheet for information on which timer is connected in the specific product Figure 25 AWU block diagram CKAWUSEL PRSC 1 0 3 OPTION bits PE MON Bit HSE clock N 1 24 MHz Prescaler MSR 128 kHz LS clock To timer input capture LSI RC for measurement 128 kHz 15 APR 5 0 15 6 BIT PROG COUNTER Y AWUTB 3 0 AWU COUNTERS AWU interrupt 15 time bases AWUEN amp HA
235. RM0016 20 4 2 SPI control register 2 SPI_CR2 Address offset 0x01 Reset value 0x00 4 3 BDM BDOE CRCEN CRCNEXT Reserved RXOnly SSM SSI rw rw rw rw Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 278 595 BDM Bidirectional data mode enable 0 2 line unidirectional data mode selected 1 1 line bidirectional data mode selected BDOE Input Output enable in bidirectional mode This bit selects the direction of transfer in bidirectional mode when BDM is setto 1 0 Input enabled receive only mode 1 Output enabled transmit only mode In master mode the MOSI pin is used and in slave mode the MISO pin is used CRCEN Hardware CRC calculation enable 0 CRC calculation disabled 1 CRC calculation Enabled Note This bit should be written only when SPI is disabled SPE 0 for correct operation CRCNEXT Transmit CRC next 0 Next transmit value is from Tx buffer 1 Next transmit value is from Tx CRC register Reserved RXONLY Receive only 0 Full duplex Transmit and receive 1 Output disabled Receive only mode This bit combined with BDM bit selects the direction of transfer in 2 line uni directional mode This bit is also useful in a multi slave system in which this particular slave is not accessed the output from the accessed slave is not corrupted SSM Software slave management 0 Software slave management disabled 1 So
236. Reserved x x x x X X x x 0x08 CAN_FMR1 FMH3 FML3 FMH2 FML2 FMH1 FML1 FMHO FMLO Reset Value 0 0 0 0 0 0 0 0 CAN FMR2 FMH5 FML5 FMH4 FML4 0x09 Reset Value 9 9 0 0 0 0 0 Ox0A 1 0 FSC11 FSC10 FACT1 0 FSCO01 5 00 Reset Value 0 0 0 0 0 0 0 2 0 FSC31 FSC30 FACT3 0 FSC21 FSC20 FACT2 Reset Value 0 0 0 0 0 0 0x0C CAN FCR3 0 FSC51 FSC50 5 0 FSC41 FSC40 FACT4 Reset Value 0 0 0 0 0 0 422 462 DoclD14587 Rev 12 2 RM0016 Analog digital converter ADC 24 24 1 24 2 24 3 d Analog digital converter ADC Introduction ADC1 and ADC2 are 10 bit successive approximation Analog to Digital Converters They have up to 16 multiplexed input channels the exact number of channels is indicated in the datasheet pin description A D Conversion of the various channels can be performed in single and continuous modes ADC1 has extended features for scan mode buffered continuous mode and analog watchdog Refer to the datasheet for information about the availability of ADC1 and ADC2 in specific product types ADC main features These features are available in ADC1 and ADC2 e 10 bit resolution e Single and continuous conversion modes e Programmable prescaler fyasterR divided by 2 to 18 e External trigger option using external interrupt ADC_ETR or timer trigger TRGO e Analog zooming in devices with pins e Interrupt generat
237. S 44 2 462 DoclD14587 Rev 12 Ly RM0016 Contents 4 5 3 Enabling write access to option bytes 46 4 6 Memory programming 46 4 6 1 Read while write RWW 46 4 6 2 Byte programming 46 4 6 3 Word programming 1 47 4 6 4 Block programming 4 47 4 6 5 Option byte programming 49 4 7 25624 NES EA CE EE RC ER 49 4 8 Flash registers 51 4 8 1 Flash control register 1 FLASH CR1 51 4 8 2 Flash control register 2 FLASH CR2 52 4 8 3 Flash complementary control register 2 FLASH NCR2 53 4 8 4 Flash protection register FLASH FPR 54 4 8 5 Flash protection register FLASH NFPR 54 4 8 6 Flash program memory unprotecting key register FLASH PUKR 54 4 8 7 Data EEPROM unprotection key register FLASH DUKR 55 4 8 8 Flash status register FLASH 55 4 8 9 Flash register map and reset values 56 5 Single wire interface module SWIM and debug module DM 57 5 1 5
238. SC1 IC2PSCO 251 CC2S0 input mode Reset value 0 0 0 0 0 0 0 0 5 CCMR3 OC3M2 OC3M1 CC3S1 CC3S0 output mode Reset value 0 0 0 0 0 0 0 0 0x09 TIM5_CCMR3 IC3F3 IC3F2 IC3F1 IC3PSC1 IC3PSCO CC3S1 CC3S0 input mode Reset value 0 0 0 0 0 0 0 0 Guan TIM5 CCER1 CC2P CC2E 1 1 5 Reset value 0 0 0 0 0 0 0 0 0x08 TIM5 CCER2 2 s Reset value 0 0 0 0 0 0 0 0 06 5 CNTRH CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 z Reset value 0 0 0 0 0 0 0 0 5 CNTRL CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNTO Reset value 0 0 0 0 0 0 0 0 Ox0E 5 PSCR 2 PSC3 PSC2 PSC1 PSCO Reset value 0 0 0 0 0 0 0 0 0 0 5 ARR15 ARR14 ARR13 ARR12 11 10 ARRQ ARR8 Reset value 1 1 1 1 1 1 1 1 du TIM5 ARRL ARR7 ARR6 ARR5 ARR4 ARR3 ARR2 ARR1 ARRO Reset value 1 1 1 1 1 1 1 1 oxi 5 CCR1H 115 CCR114 CCRI13 CCR112 CCR111 110 CCR19 CCR18 Reset value 0 0 0 0 0 0 0 0 0x2 5 CCR1L CCR17 CCR16 CCR15 CCR14 CCR13 CCR12 CCR11 CCR10 x Reset value 0 0 0 0 0 0 0 0 duda 5 CCR2H CCR215 CCR214 CCR213 CCR212 CCR211 CCR210 CCR29 CCR28 Reset value 0 0 0 0 0 0 0 0 oA TIM5 CCR2L CCR27 CCR26 CCR25 CCR24 CCR23 CCR22 CCR21 CCR20 Reset value 0 0 0 0 0 0 0 0 0 15 5 CCR3H CCR315 CCR314 CCR313 CCR312 CCR311 CCR310 CCR39 CCR38 Reset value 0 0 0 0 0 0 0 0 5 CCR3L CCR37 CCR36 CCR35 C
239. SCAN E Reset value 0 0 0 0 0 0 0 0 ADC1 DBUF OVR 2 Reset value 0 0 0 0 0 0 0 0 ADC1 DRH DATA9 DATA8 0x24 Reset value x x x x x x x x jiu ADC1_DRL DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATAO Reset value x x x x x x x x Gk ADC1 TDRH TD15 TD14 TD13 TD12 TD11 TD10 TD9 TD8 Reset value 0 0 0 0 0 0 0 0 ADC1_TDRL TD7 TD6 TD5 TD4 TD3 TD2 TD1 TDO Reset value 0 0 0 0 0 0 0 0 ADC1_HTRH HT9 HT8 HT7 HT6 HT5 HT4 HT3 HT2 0x28 Reset value 1 1 1 1 1 1 1 1 ADC1 HT1 HTO Reset value 0 0 0 0 0 0 1 1 T ADC1_LTRH LT9 LT8 LT7 LT6 LT5 LT4 LT3 LT2 Reset value 0 0 0 0 0 0 0 0 B ADC1_LTRL LT1 LTO Reset value 0 0 0 0 0 0 0 0 imo ADC1 AWSRH 59 AWS8 Reset value 0 0 0 0 0 0 0 0 448 462 DoclD14587 Rev 12 RM0016 Analog digital converter ADC Table 77 ADC1 register map and reset values continued Address Register name 7 6 5 4 3 2 1 0 offset Ox2D ADC1 AWSRL AWS7 AWS6 AWS5 AWS4 AWS3 AWS2 AWS1 AWSO Reset value 0 0 0 0 0 0 0 0 T ADC1 AWCRH AWENS AWEN8 Reset value 0 0 0 0 0 0 0 0 ADC1_AWCRL AWEN7 AWEN6 AWEN5 AWEN4 AWENS3 AWEN2 AWEN1 AWENO Ox2F Reset value 0 0 0 0 0 0 0 0 1 This register is reserved in devices with buffer size 8 x 10 bits 2 This register is reserved in devices without ADC channels 8 and 9 Table 78 ADC2 register map and reset values Addr
240. SH IAPSR register can be checked to determine if the fast block programming operation has been correctly completed The data programmed in the block are not guaranteed when the block is not blank before the fast block program operation Block erasing A block erase allows a whole block to be erased To erase a whole block the ERASE NERASE bits in the FLASH CR2 and FLASH NCR2 registers must be previously set cleared to enable block erasing see Section 4 8 2 Flash control register 2 FLASH 2 and Section 4 8 3 Flash complementary control register 2 FLASH 2 The block is then erased by writing 0 00 00 00 00 to any word inside the block The word start address must end with 0 4 8 or C EOP and the WR PG DIS control flags of the FLASH IAPSR together with the Flash interrupt can be used to determine if the operation has been correctly completed Table 5 Block size STM8 microcontroller family Block size Low density STM8S and STM8AF 64 bytes Medium density STM8S and 5 up to 32 Kbytes 128 bytes High density STM8S and 5 up to 128 Kbytes 128 bytes Option byte programming Option byte programming is very similar to data EEPROM byte programming The application writes directly to the target address The program does not stop and the write operation is performed using the RWW capability Refer to the datasheet for details of the option byte cont
241. SLV LASE LHIEN LHDF LSF REN CONTROL DoclD14587 Rev 12 319 462 Universal asynchronous receiver transmitter UART 0016 Figure 112 UART3 block diagram Write Read N DATA REGISTER UART3_DR Transmit Data Register TDR Receive Data Register RDR UART3_TX 2 Transmit Shift Register gt Receive Shift Register UART3 i UART3 CR4 UART3 LBDIEN LBDL LBDF ADD 3 0 LINEN STOP 1 0 UART2 CR1 R8 T8 UARTD M WAKE PCEN PS PIEN v A WAKE TRANSMITTER TRANSMIT up gt RECEIVER RECEIVER gt eS GEOG CONTROL UNIT CONTROL CLOCK t 7 UART3_CR2 v iv wv Y 4 TC RXNE IDLE FE PE UART3 SR INTERRUPT CONTROL 4 2 TEN J TRANSMITTER RATE CONTROL UART3 1 UARTDIV 4 UARTDIV 1 1 4 UART3 BRR2 AUTOMATIC RESYNCHRONIZATION UARTDIV 15 12 UARTDIV 3 0 UNIT 7 43 0 UART3 CR6 RECEIVER RATE REN CON
242. T The decoder input is normally HIGH marking state in the idle state The transmit encoder output has the opposite polarity to the decoder input A start bit is detected when the decoder input is low e IrDA is a half duplex communication protocol If the Transmitter is busy i e the UART is sending data to the IrDA encoder any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy UART is receiving decoded data from the UART data on the TX from the UART to IrDA will not be encoded by IrDA While receiving data transmission should be avoided as the data to be transmitted could be corrupted e A 0O is transmitted as a high pulse and a 1 is transmitted as a 0 The width of the pulse is specified as 3 16th of the selected bit period in normal mode see Figure 129 e SIR decoder converts the IrDA compliant receive signal into a bit stream for the UART e SIR receive logic interprets a high state as a logic one and low pulses as logic zeros e transmit encoder output has the opposite polarity to the decoder input The SIR output is in low state when idle specification requires the acceptance of pulses greater than 1 41 us The acceptable pulse width is programmable Glitch detection logic on the receiver end filters out pulses of width less than 2 PSC periods PSC is the prescaler value programmed in UART_PSCR Pulses of width less than 1 PSC period are
243. TIM1 CCR2H CCR215 CCR214 CCR213 CCR212 CCR21 CCR210 CCR29 CCR28 Reset value 0 0 0 0 0 0 0 0 oi TIM1 CCR2L CCR27 CCR26 CCR25 CCR24 CCR23 CCR22 CCR 1 CCR20 x Reset value 0 0 0 0 0 0 0 0 Diis CCR3H CCR315 CCR314 CCR313 CCR312 CCR311 CCR310 CCR39 CCR38 Reset value 0 0 0 0 0 0 0 0 T TIM1 CCR3L CCR37 CCR36 CCR35 CCR34 CCR33 CCR32 CCR31 CCR30 Reset value 0 0 0 0 0 0 0 0 DUE TIM1_CCR4H ccr4i5 414 CCR413 CCR412 CCR411 CCR410 CCR49 CCR48 Reset value 0 0 0 0 0 0 0 0 ede TIM1 CCR4L CCR47 CCR46 CCR45 CCR44 CCR43 CCR42 CCR41 CCR40 T Reset value 0 0 0 0 0 0 0 0 SaD TIM1_BKR MOE AOE BKP BKE OSSR OSSI LOCK LOCK Reset value 0 0 0 0 0 0 0 0 s TIM1 DTR DTG7 DTG6 DTG5 DTG4 DTG3 DTG2 DTG1 DTGO Reset value 0 0 0 0 0 0 0 0 Gee TIM1_OISR 0194 OIS3N OIS3 OIS2N 0182 OIS1N OIS1 Reset value 0 0 0 0 0 0 0 0 218 595 DoclD14587 Rev 12 d RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 18 1 18 2 d 16 bit general purpose timers TIM2 TIM3 TIM5 Introduction This chapter describes TIM2 and TIM3 which are identical timers with the exception that TIM2 has three channels and TIM3 has two channels TIM5 is also described below It is identical to TIM2 except that it has two additional registers to support timer synchronization and chaining Each timer consists of a 16 bit up counting auto reload counter driven by a programmable prescaler It may be used for a vari
244. TROL LDUM LSLV LASE LHIEN LHDF LSF 3 320 462 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART Figure 113 UART4 block diagram MCU bus Write Read b 4 UART4_DR DATA REGISTER Transmit Data Register TDR Receive Data Register RDR UART4_TX Transmit Shift Register Receive Shift Register UART4_RX gai UARTA UART4 CK CONTROL UART4_GTR H gt GUARD TIME REGISTER UART4_CR UART4_CR3 v v SCEN HDSEL IRLP IREN LINEN STOP BITS CLKEN CPOL CPHA LBCL IrDA SIR BLOCK 4 UART4_CR4 4 CR1 T T T LBDIEN LBDL LBDF ADD Lp R8 T8 UARTD WAKE PCEN PS PIEN 7 v v v TRANSMIT WAKE UP t RECEIVER CONTROL UNIT CONTROL NEN UART4_CR2 Yyy
245. The FMHx and FMLx bits are located in the CAN FMR1 and CAN FMR2 registers Figure 151 8 bit filter bank configuration FSCx bits 0000 CAN FCRx register Filter registers Filter mode STID 10 3 FMHx 0 FMHx 0 FMHx 1 FMHx 1 pping EXID 28 21 FMLx 0 FMLx 1 FMLx 0 FMLx 1 Identifier CAN 1 D ID n ID ID n n n Identifier Mask CAN FxR2 M ID n1 M ID n1 Identifier CAN FxR3 D ID 2 ID ID 2 n 1 n 1 Identifier Mask CAN_FxR4 M ID n 3 M ID n 3 Identifier CAN_FxR5 D ID ID n 2 ID n 4 n 2 n 4 Identifier Mask CAN FxR6 M M ID n 3 ID n 5 Identifier CAN_FxR7 D ID ID n 4 ID n 6 n 3 n 5 Identifier Mask CAN_FxR8 M M ID n 5 ID n 7 ID Identifier n Filter number M Mask x Filter bank number 1 The FMHx and FMLx bits are located in the CAN_FMR1 and CAN FMR2 registers 3 386 462 DoclD14587 Rev 12 0016 Controller area network beCAN Filter match index Once a message has been received in the FIFO it is available to the application Typically application data are copied into RAM locations To copy the data to the right location the application has to identify the data by means of the identifier To avoid this and to ease the access to the RAM locations the CAN controller provides a Filter Match Index This index is stored in the mailbox together with the message according t
246. WEN bit in the Switch control register CLK_SWCR 2 Write the 8 bit value used to select the target clock source in the Clock master switch register CLK_SWR The SWBSY bit in the CLK_SWCR register is set by hardware and the target source oscillator starts The old clock source continues to drive the CPU and peripherals DoclD14587 Rev 12 Ly RM0016 Clock control CLK 2 As soon as the target clock source is ready stabilized the content of the SWR register is copied to the Clock master status register CLK CMSR The SWBSY bit is cleared and the new clock source replaces the old one The SWIF flag in the CLK SWCR is set and an interrupt is generated if the SWIEN bit is set Manual switching The manual switching is not as immediate as the automatic switching but it offers to the user a precise control of the switch event time To enable manual switching follow the sequence below refer to the flowchart in Figure 23 1 Write the 8 bit value used to select the target clock source in the Clock master switch register SWR Then the SWBSY bit is set by hardware and the target source oscillator starts The old clock source continues to drive the CPU and peripherals 2 software has to wait until the target clock source is ready stabilized This is indicated by the SWIF flag in the SWCR register and by an interrupt if the SWIEN bit is set 3 The final software action is to set at the chose
247. Wakeup from Halt mode is triggered by an external interrupt sourced by a GPIO port configured as interrupt input or an Alternate Function pin capable of triggering a peripheral interrupt In this mode the MVR regulator is switched off to save power Only the LPVR regulator and brown out reset is active Fast clock wakeup The HSI RC start up time is much faster than the HSE crystal start up time refer to the Electrical Parameters in the datasheet Therefore to optimize the MCU wakeup time it is recommended to select the HSI clock as the fyyasterR clock source before entering Halt mode This selection can be done without clock switching using the FHWU bit in the nternal clock register CLK ICKR Refer to the Clock control CLK chapter Active halt modes Active halt mode is similar to Halt mode except that it does not require an external interrupt for wakeup It uses the AWU to generate a wakeup event internally after a programmable delay In Active halt mode the main oscillator the CPU and almost all the peripherals are stopped Only the LSI RC or HSE oscillators are running to drive the AWU counters and IWD counter if enabled To enter Active halt mode first enable the AWU as described in the AWU section Then execute a HALT instruction 2 DoclD14587 Rev 12 RM0016 Power management 10 3 10 3 1 10 3 2 d Main voltage regulator MVR auto power off By default the main voltage regulator is kept o
248. Y bit is set They are set to the reset value HSI if the AUX bit is set in the CLK CSSR register If Fast Halt wakeup mode is selected FHW bit 1 in CLK ICKR register then these bits are set by hardware to E1h HSI selected when resuming from Halt Active halt mode OxE1 HSI selected as master clock source reset value 0 02 LSI selected as master clock source only if LSI EN option bit is set OxB4 HSE selected as master clock source d DoclD14587 Rev 12 91 462 Clock control CLK 0016 9 9 5 Switch control register SWCR Address offset 0x05 Reset value 0 ri 6 5 4 3 2 1 0 Reserved SWIF SWIEN SWEN SWBSY r wO rw rw rw Bits 7 4 Reserved Bit 3 SWIF Clock switch interrupt flag This bit is set by hardware and cleared by software writing 0 Its meaning depends on the status of the SWEN bit Refer to Figure 22 and Figure 23 n manual switching mode SWEN 0 0 Target clock source not ready 1 Target clock source ready In automatic switching mode SWEN 1 0 No clock switch event occurred 1 Clock switch event occurred Bit 2 SWIEN Clock switch interrupt enable This bit is set and cleared by software 0 Clock switch interrupt disabled 1 Clock switch interrupt enabled Bit 1 SWEN Switch start stop This bit is set and cleared by software Writing a 1 to this bit enables switching the master clock to the source defined in the CLK SWR register 0 Dis
249. a manipulation is negative i e the most significant bit is a logic 1 Z Zero When set to 1 this bit indicates that the result of the last arithmetic logical or data manipulation is zero e C Carry When set C indicates that a carry or borrow out of the ALU occurred during the last arithmetic operation on the MSB operation result bit This bit is also affected during bit test branch shift rotate and load instructions See the ADD ADC SUB and SBC instructions In a division operation C indicates if trouble occurred during execution quotient overflow or zero division See the DIV instruction In bit test operations C is the copy of the tested bit See the BTJF and BTJT instructions In shift and rotate operations the carry is updated See the RRC RLC SRL SLL and SRA instructions This bit can be set reset or complemented by software using the SCF RCF and CCF instructions Example Addition B5 94 49 149 7 0 0 1101111401011 7 0 10 1 1 7 0 1 1 1 1 d DoclD14587 Rev 12 RM0016 Central processing unit CPU 1 2 2 STM8 CPU register map The CPU registers are mapped in the STM8 address space as shown in Table 2 These registers can only be accessed by the debug module but not by memory access instructions executed in the core Table
250. a read to the UART DR register 0 No noise is detected 1 Noise is detected Bit 1 FE Framing error This bit is set by hardware when a de synchronization excessive noise or a break character is detected It is cleared by a software sequence a read to the UART SR register followed by a read to the UART DR register 0 No Framing error is detected 1 Framing error or break character is detected Note For the UART2 and UARTS in LIN slave mode bits LINE and LSLV are set when a framing error is detected in the Synch or Identifier Fields the FE bit is set But the FE bit will not be set when a Break reception is detected Bit 0 PE Parity error This bit is set by hardware when a parity error occurs in receiver mode It is cleared by a software sequence a read to the status register followed by a read to the UART_DR data register You to wait for the RXNE flag to be set before clearing it An interrupt is generated if PIEN 1 in the UART_CR1 register 0 No parity error 1 Parity error or in LIN slave mode identifier parity error The IDLE bit will not be set again until the RXNE bit has been set itself i e a new idle line occurs When this bit is set the RDR register content will not be lost but the shift register will be overwritten This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupt This bit does not generate interrupt as it appears at the sa
251. able an page 142 INIT Co nter initialize Figure 45 TI2 external clock connection example on page 151 External trigger from ai TIMx ETR ETRF External trigger filtered Figure 47 External trigger input block diagram on page 153 ETRP External trigger prescaled Timer peripneral edes Figure 20 Clock tree and Figure 12 fMASTER from clock controller Clock structure on page 61 CLK ICi IC1 IC2 Input capture ICiPS IC1PS IC2PS Input capture prescaled Figure 64 Input stage of TIM 1 channel 1 on page 166 MATCH1 OC2 Compare match Timer output channel OC1REF OC2REF Output compare reference signal Figure 54 Trigger master mode selection blocks on page 159 and Section 17 7 2 Control register 2 TIM1_CR2 on page 188 Figure 68 Detailed output stage of channel with complementary output channel 1 on page 170 Figure 43 Clock trigger controller block TGI Trigger interrupt diagram on page 150 Ti TH 2 Timer input THF THF 2 Timer input filtered Timer input edge detector TIFPn THFP1 THFP2 TI2FP1 TI2FP2 4 TI4FP3 TI4FP4 Timer input filtered prescaled TRC TRGI Trigger capture Trigger input to clock trigger slave mode controller Figure 64 Input stage of TIM 1 channel 1 on page 166 Figure 44 Control circuit in normal mode 5 fMASTER on page 151
252. able clock switch execution 1 Enable clock switch execution Bit 0 SWBSY Switch busy This bit is set and cleared by hardware It can be cleared by software to reset the clock switch process 0 No clock switch ongoing 1 Clock switch ongoing 2 92 462 DoclD14587 Rev 12 0016 Clock control CLK 9 9 6 Clock divider register CLK CKDIVR Address offset 0x06 Reset value 0x18 7 6 5 4 3 2 1 0 Reserved HSIDIV 1 0 CPUDIV 2 0 r rw rw rw rw rw Bits 7 5 Reserved must be kept cleared Bits 4 3 HSIDIV 1 0 High speed internal clock prescaler These bits are written by software to define the HSI prescaling factor 00 fusi fusi RC output 01 fusi fusi RC output 2 10 fusi fusi RC 4 11 fusi fusi RC 8 Bits 2 0 CPUDIV 2 0 CPU clock prescaler These bits are written by software to define the CPU clock prescaling factor 000 fcpu fasTER 001 fcpu faster 2 010 fcpu fwaster 4 011 fcpu fmaster 8 100 fcpu fmasteR 16 101 2 110 fopu fuaster 64 111 1 28 2 DoclD14587 Rev 12 93 462 Clock control CLK 0016 9 9 7 Peripheral clock gating register 1 PCKENR 1 Address offset 0x07 Reset value OxFF PCKEN1 7 0 Bits 7 0 PCKEN1 7 0 Peripheral clock enable These bits are written by software to enable or disable the fmaster clock to the corresponding peripheral
253. able register 2 TIMx CCER2 Address offset 0x09 or OxOB TIM2 OxOB 5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 Reserved CC3P CC3E r rw rw Note This register is not available in TIM3 Bits 7 2 Reserved Bit 1 CC3P Capture compare 3 output polarity Refer to CC1P description Bit CC3E Capture compare 3 output enable Refer to CC1E description 18 6 13 Counter high TIMx CNTRH Address offset or 0 0 TIM2 0x08 OxOC TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 CNT 15 8 rw rw rw rw rw rw rw rw Bits 7 0 CNT 15 8 Counter value MSB Ly DoclD14587 Rev 12 239 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 6 14 Counter low CNTRL Address offset OxOB or OxOD TIM2 0x09 TIM3 OxOD 5 for TIM2 address see Section Reset value 0x00 ONT 7 0 Bits 7 0 CNT 7 0 Counter value LSB 240 595 DoclD14587 Rev 12 d RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 6 15 Prescaler register TIMx_PSCR Address offset 0 0 or OxOE 2 TIM3 OxOE TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 Reserved PSC 3 0 r rw rw rw rw Bits 7 3 Reserved Bits 2 0 PSC 3 0 Prescaler value The prescaler value divides the CK_PSC clock frequency The cou
254. al HSI calibration register value The width of the trimming steps with 4 bits is half the trimming step width with 3 bits Table 14 Devices with 4 trimming bits Trimming bits value Trimming steps Trimming bits value Trimming steps 01110 7 11116 1 01106 6 11106 2 01016 5 11016 3 0100b H4 1100b 4 00110 3 10110 5 00106 2 10106 6 00016 1 10016 7 00006 0 10006 8 Table 15 Devices with 3 trimming bits Trimming bits value Trimming steps Trimming bits value Trimming steps 011b 43 1116 1 010b 2 110b 2 001b 1 101b 3 000b 0 1000 4 As the trimming step width depends on the absolute frequency of the RC oscillator successive approximation method needs to be applied for the trimming This method is described in a separate technical document 9 1 3 LSI d The 128 kHz LSI RC acts as a low power low cost alternative master clock source as well as a low power clock source that can be kept running in Halt mode for the independent watchdog IWDG and auto wakeup unit AWU DoclD14587 Rev 12 81 462 Clock control CLK 0016 Note 9 2 9 2 1 9 2 2 82 462 The LSI RC can be switched on and off using the LSIEN bit in the nternal clock register CLK ICKR The LSIRDY flag in the nternal clock register CLK ICKR indicates if the low speed internal oscillator is stable or not At startup the clock is not released until this bit is set by hardware Calibration Like the HSI RC the LSI RC device is facto
255. al interrupt control register 1 EXTI 2 70 6 9 5 ITC and register and reset values 71 7 Power Supply sa RE KK E RR da ao RR ae 72 8 Reset nse e n Cosa ca E ER ar e e 73 8 1 Reset state and under reset definitions 73 8 2 Reset circuit description 73 8 3 Internal reset 74 8 3 1 Power on reset POR and brown out reset 74 8 3 2 Watchdog reset 74 8 3 3 Software reset 75 8 3 4 SWIM reset 75 8 3 5 Illegal opcode reset 75 8 3 6 EMG CSE 75 8 4 RST register 76 8 4 1 Reset status register RST SR 76 8 5 RST register map 76 9 Clock control ERE 77 9 1 Master clock sources 79 9 1 1 HOE PPP 79 9 1 2 ph EL 80 9 1 3 E E EE eee ee ee ag 81 9 2 Master clock switching 82 9 2 1 System x 222525 ee
256. alue 0000 0000 doi UART3_CR1 R8 T8 UARTD M WAKE PCEN PS PIEN Reset Value 0 0 0 0 0 0 0 0 iis UART3 CR2 TIEN TCIEN RIEN ILIEN TEN REN RWU SBK Reset Value 0 0 0 0 0 0 0 0 UART3 CR3 LINEN STOP B Reset Value 0 0 00 0 0 0 0 0x07 UART3 CR4 LBDIEN LBDL LBDF ADD 3 0 Reset Value 0 0 0 0 0000 0x08 Reserved 0x09 UART2 CR6 LDUM LSLV LASE LHDIEN LHDF LSF Reset Value 0 0 0 0 0 0 0 0 d DoclD14587 Rev 12 371 462 Universal asynchronous receiver transmitter UART 0016 Table 64 UARTA register Register Address 9 7 6 5 4 3 2 1 0 name UART4_SR TXE TC RXNE IDLE OR NF FE PE Reset Value 1 1 0 0 0 0 0 0 A UART4_DR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO Reset Value x x x x x x x x 0x02 UART4_BRR1 UART_DIV 11 4 Reset Value 00000000 0x03 UART4_BRR2 UART DIV 15 12 UART_DIV 3 0 Reset Value 0000 0000 0x04 UART4_CR1 R8 T8 UARTD M WAKE PCEN PS PIEN Reset Value 0 0 0 0 0 0 0 0 05 UART4_CR2 TIEN TCIEN RIEN ILIEN TEN REN RWU SBK m Reset Value 0 0 0 0 0 0 0 0 Bs UART4_CR3 LINEN STOP CKEN CPOL CPHA LBCL Reset Value 0 0 00 0 0 0 0 UART4_CR4 LBDIEN LBDL LBDF ADD 3 0 Reset Value 0 0 0 0 0000 ad UART4_CR5 5 HDSEL IRLP IREN 5 Reset Value 0 0 0 0 0 0 0 0 UART4_CR6 LDUM LSLV LASE LHDIEN LHDF LSF Reset Value 0 0 0 0 0 0 0 0 Gen UART4_GTR GT7 GT6 GT5 GT4 GT3 GT2 GT1 GTO
257. always rejected but those of width greater than one and less than two periods may be accepted or rejected those greater than 2 periods will be accepted as a pulse The IrDA encoder decoder doesn t work when PSC 0 e Thereceiver can communicate with a low power transmitter e In IrDA mode the STOP bits in the UART_CR2 register must be configured to 1 stop bit IrDA low power mode The IrDA can be used either in normal mode or in Low Power mode The Low Power mode is selected by setting the IRLP bit in CR5 register Transmitter In low power mode the pulse width is not maintained at 3 16 of the bit period Instead the width of the pulse is 3 times the low power baud rate which can be a minimum of 1 42 MHz Generally this value is 1 8432 MHz 1 42 MHz PSC 2 12 MHz A low power mode programmable divisor divides the system clock to achieve this value Receiver Receiving in low power mode is similar to receiving in normal mode For glitch detection the UART should discard pulses of duration shorter than 1 PSC A valid low is accepted only if its duration is greater than 2 periods of the IrDA low power Baud clock PSC value in UART PSCR A pulse of width less than two and greater than one PSC period s may or may not be rejected The receiver set up time should be managed by software The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception IrDA is a half duplex prot
258. ample of the behavior of the outputs in response to a break Figure 77 Behavior of outputs in response to a break channel without complementary output BREAK MOE 7 OCiREF 0 0151 0 015 0 1 OISi 1 1 015 0 2 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Figure 78 shows an example of behavior of the complementary outputs TIM1 only in response to a break Figure 78 Behavior of outputs in response to a break TIM1 complementary outputs BREAK OCi OCW not implemented 1 OIS 0 OCi gt OCN delay delay delay 1 0 015 0 1 0 OISiN 1 con del del del 1 0 OISi 1 1 ciay Giay CCNP 1 5 1 OCN delay CCiE 1 0 015 0 CCiNE 0 CCNP 0 OISN 1 q OCN delay CCiE 1 0 015 1 0 0 OISiN 0 OCN CCiE 1 0 0 CCiNP 0 5 0 or OIS OISiN 1 00 1014587 Rev 12 181 595 16 bit advanced control timer TIM1 0016 17 5 9 182 595 Clearing the OC REF signal on an exter
259. and available Bit 0 HSEEN High speed external crystal oscillator enable This bit is set and cleared by software It can be used to switch the external crystal oscillator on or off It is set by hardware in the following cases When switching to HSE clock see CLK SWR register When HSE is selected as the active source see CLK CCOR register It cannot be cleared when HSE is selected as clock master indicated in CLK CMSR register or as the active CCO source 0 HSE clock off 1 HSE clock on 3 90 462 DoclD14587 Rev 12 0016 Clock control CLK 9 9 3 Clock master status register CLK CMSR Address offset 0x03 Reset value OxE1 CKM7 0 Bits 7 0 CKM 7 0 Clock master status bits These bits are set and cleared by hardware They indicate the currently selected master clock source An invalid value occurring in this register will automatically generate an MCU reset OxE1 HSI selected as master clock source reset value 0 02 LSI selected as master clock source only if LSI EN option bit is set 0 4 HSE selected as master clock source 9 9 4 Clock master switch register CLK SWR Address offset 0x04 Reset value OxE1 SWI 7 0 Bits 7 0 SWI 7 0 Clock master selection bits These bits are written by software to select the master clock source Its contents are write protected while a clock switch is ongoing while the SWBS
260. ange See Electrical parameters section of the datasheet for more details The BOR also generates a reset when the supply voltage drops below the Vr threshold When this occurs the POR is re armed for the next power on phase An hysteresis is implemented to ensure clean detection of voltage rise and fall The BOR always remains active even when the MCU is put into Low Power mode Figure 19 Vpp Vppio Voltage detection POR BOR threshold 1 NRST 8 3 2 Watchdog reset Refer to Section 15 Window watchdog WWDG and Section 14 Independent watchdog IWDG for details 74 462 DoclD14587 Rev 12 Ly RM0016 Reset RST 8 3 3 8 3 4 8 3 5 Note 8 3 6 d Software reset The application software can trigger reset by clearing bit T6 in the WWDG CR register Refer to Section 15 Window watchdog WWDG SWIM reset An external device connected to the SWIM interface can request the SWIM block to generate an MCU reset Illegal opcode reset In order to provide enhanced robustness to the device against unexpected behavior a system of illegal opcode detection is implemented If a code to be executed does not correspond to any opcode or prebyte value a reset is generated This combined with the Watchdog allows recovery from an unexpected fault or interference A valid prebyte associated with a valid opcode forming an unauthorized combination does not gener
261. ants of the outputs see Figure 31 TIM1 general block diagram on page 139 This time is generally known as deadtime Deadtimes must be adjusted depending on the characteristics of the devices connected to the outputs example intrinsic delays of level shifters delays due to power switches The polarity of the outputs can be selected main output OCi or complementary independently for each output This is done by writing to the and CCi NP bits in the TIM1 CCERi registers The complementary signals OC and OCi are activated by a combination of several control bits The CC E and CCi NE bits in the TIM1 CCERiregister and if the break feature is implemented the MOE OIS OISi OSSI and OSSR bits in the TIM1 BKR register Refer to Table 38 Output control for complementary OCi and OCiN channels with break feature on page 205 for more details In particular the deadtime is activated when switching to the IDLE state when MOE falls to 0 2 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 d Deadtime insertion is enabled by setting the CC E and bits and the MOE bit if the break circuit is present Each channel embeds an 8 bit deadtime generator It generates two outputs OC and OCi N from a reference waveform OC REF If and OCiN are active high e OCioutput signal is the same as the reference signal except for the rising edge which is delayed relative to t
262. any power of 2 from 1 to 32768 3 independent channels for Input capture Output compare PWM generation edge aligned mode One pulse mode output Synchronization circuit to control the timer with external signals and to interconnect several timers See Section 17 4 6 on page 158 External trigger input TIM1 ETR shared with TIM1 Interrupt generation on the following events Update counter overflow counter initialization by software Input capture Output compare TIM2 TIM3 TIM5 functional description Figure 82 TIM2 TIM3 block diagram uasTER TIME BASE UNIT Auto reload register UP DOWN COUNTER PSI CK v CAPTURE COMPARE ARRAY CH1 TIMx CH2 CH3 2 UEV M IC1PS _ OC1REF gt Capture Compare 1 Register cca E y OC2REF Capture Compare 2 Register H gt UE IC3PS ce Capture Compare 3 Register Prescaler CH1 OUTPUT STAGE INPUT STAGE Prescaler TIMx CH2 IC3 Prescaler CH3 Legend RN Preload registers transferred 10 shadow registers on update event UEV according to control bit event interrupt 220 595 3 DoclD14
263. apped on TRC This mode works only if an internal trigger input is selected through the TS bit 5 SMCR register Note 15 bits are writable only when the channel is off CC1E 0 and is updated in TIMx 1 2 234 595 DoclD14587 Rev 12 0016 16 bit general purpose timers 2 TIM3 5 Channel configured in input IC1F 3 0 IC1PSC 1 0 CC1S 1 0 Bits 7 4 IC1F 3 0 Input capture 1 filter This bitfield defines the frequency used to sample TI1 input and the length of the digital filter applied to 1 The digital filter is made of an event counter in which events are needed to validate a transition on the output 0000 No filter sampling is done at fyaster 0001 fgamPLinG fmasTerR N 2 0010 fsamPLING faster N 4 0011 fgamPLinc faster 8 0100 fsaupLiNG7 fuAsTER 2 N 6 0101 fsamPLING fuaster 2 N 8 0110 fgamPLinc fmasteR 4 N 6 0111 fsaupLING7 4 N 8 1000 fgamPLinc fuaster 8 N 6 1001 fsaupLiNG7 fmaster 8 N 8 1010 fsAMPLING fuAsTER 16 N25 1011 fgamPLING fmasteR 16 N 6 1100 fsaupLiNG7 fuAsTER 16 N 8 1101 fsaupLiNG7 2 N 5 1110 fgamPLING fwaster 32 N 6 1111 fsaupLiNG7 fuasrER 32 N 8 Bits 3 2 IC1PSC 1 0 Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on CC1 input IC1 The prescaler is reset as soon as CC1E 0 TIMx CCER regist
264. are enabled or disabled by software The interface is connected to the I C bus by a data pin SDA and by a clock pin SCL It can be connected with a standard up to 100 kHz or fast up to 400 kHz 2 bus Mode selection The interface can operate in one of the four following modes e Slave transmitter e Slave receiver e Master transmitter e Master receiver By default it operates in slave mode The interface automatically switches from slave to master after it generates a START condition and from master to slave if an arbitration loss or a STOP generation occurs allowing Multi Master capability Communication flow In Master mode the 2 interface initiates a data transfer and generates the clock signal A serial data transfer always begins with a start condition and ends with a stop condition Both start and stop conditions are generated in master mode by software In Slave mode the interface is capable of recognizing its own addresses 7 or 10 bit and the General Call address The General Call address detection may be enabled or disabled by software Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the start condition contain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in Master mode A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must send an acknowledge bit to the transmitter Refer to the
265. are register 3 low CCR3L 211 17 7 28 Capture compare register 4 high 212 17 7 29 Capture compare register 4 low TIM1_CCR4L 212 17 7 30 Break register 213 17 7 34 Deadtime register DTR 215 17 7 32 Output idle state register OISR 216 17 7 33 TIM 1 register map and reset values 217 18 16 bit general purpose timers TIM2 TIM3 TIM5 219 acce Kc Cb mn x Roe ee 219 182 2 main features 219 18 3 TIM5 main features 220 18 4 2 5 functional description 220 18 4 1 Time base 2 221 18 4 2 222 18 4 3 channels 223 185 TIM2Z TIMS TIM5 interrupts 225 186 TIM2 TIMS TIM5 registers 226 18 6 1 Control register 1 TIMx 1 226 18 6 2 Control register 2 5 CR2 227 Ky DoclD14587 Rev 12 9 462 Contents RM00
266. as shown in Figure 161 These thresholds are programmed the and ADC LTR 10 bit registers An interrupt can be enabled by setting the AWDIE bit in the ADC_CSR register For Scan mode the analog watchdog can be enabled on selected channels using the AWENx bits in the ADC_AWCRH and ADC_AWCRL registers The watchdog status for each channel is obtained by reading the AWSx bits in the ADC_AWSRH and ADC AWSRL registers If any of the AWS flags are set this also sets the AWD flag Depending on the AWDIE interrupt enable bit an interrupt is generated at the end of the SCAN sequence The interrupt routine should then clear the AWS flag and the global AWD flag in the register For Buffered continuous mode the analog watchdog can be enabled on selected buffers and is managed as described for scan mode with the difference the buffers contain the results of continuous conversions performed on a single channel Refer to Section 24 7 for more details on interrupts To optimize analog watchdog interrupt latency in scan or buffered continuous mode it recommended to use the last channels in the conversion sequence Figure 161 Analog watchdog guarded area Analog voltage HTR High threshold Low threshold LTR DoclD14587 Rev 12 429 462 Analog digital converter ADC 0016 24 5 7 Note 24 5 8 24 5 9 430 462 1 Conversion on external trigger Conversion can be tri
267. ase of a slave listening to the response of another slave DMEAS Error due to the LIN Synch measurement performed by the receiver e DQUANT Error due to the baud rate quantization of the receiver e DREC Deviation of the local oscillator of the receiver This deviation can occur during the reception of one complete LIN message assuming that the deviation has been compensated at the beginning of the message e DTCL Deviation due to the transmission line generally due to the transceivers e All the deviations of the system should be added and compared to the UART clock tolerance DTRA DQUANT DTCL lt 3 75 Error due to LIN synch measurement The LIN Synch Field is measured over eight bit times This measurement is performed using a counter clocked by the CPU clock The edge detections are performed using the CPU clock cycle This leads to a precision of 2 CPU clock cycles for the measurement which lasts 8 UARTDIV clock cycles Consequently this error DMEAS is equal to 2 amp UARTDIVMIN UARTDIVMIN corresponds to the minimum LIN prescaler content leading to the maximum baud rate taking into account the maximum deviation of 14 Error due to baud rate quantization The baud rate can be adjusted in steps of 1 UARTDIV The worst case occurs when the real baud rate is in the middle of the step This leads to a quantization error DQUANT equal to 1 2 UARTDIVMIN 2
268. ask two identifiers are specified doubling the number of single identifiers All bits of the incoming identifier must match the bits specified in the filter registers Filter bank scale and mode configuration The filter banks are configured by means of the corresponding CAN FCRx register To configure a filter bank this must be deactivated by clearing the FACT bit the CAN FCRx register The filter scale is configured by means of the FSC 1 0 bits in the corresponding CAN FCRx register The identifier list or identifier mask mode for the corresponding Mask Identifier registers is configured by means of the FMLx and FMHx bits in the CAN FMRx register The FMLx bit defines the mode for the lower half registers CAN FxHR1 4 and the FMHx bit the mode for the upper half registers CAN FxR5 8 of filter bank x Refer to Figure 148 through Figure 151 for details Examples If filter bank 1 is configured as two 16 bit filters then the FML1 bit defines the mode of the CAN F1R3 and CAN F1R4 registers and the FMH1 bit defines the mode of the CAN F1R7 CAN F1R68 registers ffilter bank 1 is configured as four 8 bit filters then the FML1 bit defines the mode ofthe CAN F1R2 and CAN F1R4 registers and the FMH1 bit defines the mode of the F1R6 CAN F1R68 registers 2 DoclD14587 Rev 12 RM0016 Controller area network beCAN Note In 32 bit configuration the FMLx and FMHx bits must have the same value to
269. assical NSS input The slave is selected when the NSS line is in low level and is not selected if the NSS line is in high level Note When the master is communicating with SPI slaves which need to be deselected between transmissions the NSS pin must be configured as a GPIO d DoclD14587 Rev 12 259 595 Serial peripheral interface SPI 0016 Note Note 260 595 Clock phase and clock polarity Four possible timing relationships may be chosen by software using the CPOL and CPHA bits The CPOL clock polarity bit controls the steady state value of the clock when no data is being transferred This bit affects both master and slave modes If CPOL is reset SCK pin has a low level idle state If CPOL is set SCK pin has a high level idle state Make sure the SPI pin is configured at the idle state level of the SPI in order to avoid generating an edge on the SPI clock pin when enabling or disabling the SPI cell If CPHA clock phase bit is set the second edge on the SCK pin falling edge if the CPOL bit is reset rising edge if the CPOL bit is set is the MSBit capture strobe Data is latched on the occurrence of the first clock transition If CPHA bit is reset the first edge on the SCK pin falling edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data is latched on the occurrence of the second clock transition The combination of the CPOL clock polarity and CPHA clock phase bits sel
270. aster slave mode by writing MSM 1 SMCR register 5 Configure timer B to get the input trigger from timer A see TS 2 0 bit definitions in TIMx SMCR register 6 Configure timer B in trigger mode SMS 110 in the TIMx SMCR register When a rising edge occurs TI1 timer A both counters start counting synchronously on the internal clock and both TIF flags are set In this example both timers are initialized before starting by setting their respective UG bits Both counters start from 0 but an offset can easily be inserted between them by writing to any of the counter registers TIMx It can be seen that the master slave mode inserts a delay between CNT EN and CK PSC on timer A DoclD14587 Rev 12 163 595 16 bit advanced control timer TIM1 RM0016 Figure 60 Triggering Timer A and B with Timer A TI1 input uASTER Timer A TI1 Timer A CEN CNT EN Timer PSC Timer A CNT gt 405 6 07 08 09 Timer A TIF Timer B CEN 5 gt 405 06 07 08 09 Timer B TIF 17 5
271. ata Alignment These bits contain the eight LSB bits of the converted data DoclD14587 Rev 12 437 462 Analog digital converter ADC 0016 24 11 3 ADC control status register Address offset 0x20 Reset value 0x00 7 6 5 4 3 2 1 0 EOC AWD EOCIE AWDIE CH 3 0 rw rc_w0 rw rw rw rw rw rw Bit 7 EOC End of conversion This bit is set by hardware at the end of conversion It is cleared by software by writing 0 0 Conversion is not complete 1 Conversion complete Bit6 AWD Analog Watchdog flag 0 No analog watchdog event 1 An analog watchdog event occurred In buffered continuous or scan mode you can read the ADC_AWSR register to determine the data buffer register related to the event An interrupt request is generated if AWDIE 1 Note This bit is not available for ADC2 Bit 5 EOCIE Interrupt enable for EOC This bit is set and cleared by software It enables the interrupt for End of Conversion 0 EOC interrupt disabled 1 EOC interrupt enabled An interrupt is generated when the EOC bit is set Bit 4 AWDIE Analog watchdog interrupt enable 0 AWD interrupt disabled 1 AWD interrupt enabled Note This bit is not available for ADC2 Bits 3 0 CH 3 0 Channel selection bits 438 462 These bits are set and cleared by software They select the input channel to be converted 0000 Channel AINO 0001 Channel AIN1 1111 Channel AIN15 d DoclD14587 Rev 12 RM0016 Ana
272. ate a reset EMC reset To protect the application against spurious write access or system hang up possibly caused by electromagnetic disturbance the most critical registers are implemented as two bitfields that must contain complementary values Mismatches are automatically detected by this mechanism triggering an EMC reset and allowing the application to cleanly recover normal operations DoclD14587 Rev 12 75 462 Reset RST RM0016 8 4 RST register description 8 4 1 Reset status register RST_SR Address offset 0x00 Reset value 0 7 6 5 4 3 2 1 0 Reserved EMCF SWIMF ILLOPF IWDGF WWDGF r rc w1 rc w1 rc w1 rc w1 rc w1 Bits 7 5 Reserved Bit 4 EMCF EMC reset flag This bit is set by hardware and cleared by software writing 1 0 No EMC reset occurred 1 An EMC reset occurred possible cause complementary register or option byte mismatch Bit3 SWIMF SWIM reset flag This bit is set by hardware and cleared by software writing 1 0 No SWIM reset occurred 1 A SWIM reset occurred Bit 2 ILLOPF Illegal opcode reset flag This bit is set by hardware and cleared by software writing 1 0 No ILLOP reset occurred 1 An ILLOP reset occurred Bit 1 IWDGF Independent Watchdog reset flag This bit is set by hardware and cleared by software writing 1 0 No IWDG reset occurred 1 An IWDG reset occurred Bit WWDGF Window Watchdog reset flag This bit is set by hardware and clea
273. ation on MOE the deadtime duration is a bit longer than usual around two 2 ck tim clock cycles e break status flag BIF bit in the TIM1 SR1 register is set An interrupt can be generated if the BIE bit in the TIM1 IER register is set e I fthe AOE bit in the TIM1 register is set the MOE bit is automatically set again at the next UEV This can be used to perform a regulation Otherwise MOE remains low until it is written to 1 again In this case it can be used for security and the break input can be connected to an alarm from power drivers thermal sensors or any security components The break inputs act on signal level Thus the MOE bit cannot be set while the break input is active neither automatically nor by software In the meantime the status flag BIF cannot be cleared The break can be generated by the break input BKIN which has a programmable polarity and can be enabled or disabled by setting or resetting the BKE bit in the TIM1 BKR register In addition to the break inputs and the output management a write protection has been implemented inside the break circuit to safeguard the application It allows the configuration of several parameters OC polarities and state when disabled OCM configurations break enable and polarity to be frozen Three levels of protection can be selected using the LOCK bits in the TIM1 BKR register The LOCK bits can be written only once after an MCU reset Figure 77 shows an ex
274. ator The receiver and transmitter Rx and Tx are both set to the same baud rate programmed by a 16 bit divider UART_DIV according to the following formula MASTER Tx Rx baud rate UART DIV The UART_DIV baud rate divider is an unsigned integer coded in the BRR1 and BRR2 registers as shown in Figure 119 Refer to Table 54 for typical baud rate programming examples Figure 119 How to code UART DIV in the BRR registers Example To obtain 9600 baud with fmaster 10 MHz UART_DIV 10 000 000 9600 UART_DIV 1042d 0 041 2 See Table 54 d 0x41 0 0 0 2 Y Y Y UART DIV 11 4 UART DIV 15 12 UART DIV 3 0 7 0 7 43 0 UART_BRR1 UART_BRR2 register 0x41 register 0x02 The Baud Counters will be updated with the new value of the Baud Registers after a write to BRH1 Hence the Baud Register value should not be changed during a transaction The BRR2 should be programmed before UART_DIV must be greater than or equal to 16d DoclD14587 Rev 12 331 462 Universal asynchronous receiver transmitter UART RM0016 Table 54 Baud rate programming and error calculation pins fuAsrER 10 MHz 16 MHz Actual Error UART DIV BRR1 BRR2 Actual Error UART DIV BRR1 BRR2 2 4 2 899 0 008 0 1047 0x04 Ox17 2 399 0 005 0x1A0B OxAO Ox1B 9 6
275. be selected refer to Figure 20 The fcpy signal is the clock for both the CPU and the window watchdog d DoclD14587 Rev 12 85 462 Clock control CLK 0016 9 5 86 462 Peripheral clock gating PCG Gating the clock to unused peripherals helps reduce power consumption Peripheral clock Gating PCG mode allows you to selectively enable or disable the fmaster clock connection to the following peripherals at any time in Run mode e ADC e l2C e AWU register clock not counter clock e SPI e TIM 4 1 e UART e register clock not CAN clock After a device reset all peripheral clocks are enabled You can disable the clock to any peripheral by clearing the corresponding PCKEN bit in the Peripheral clock gating register 1 CLK 1 and in the Peripheral clock gating register 2 PCKENR2 But you have to disable properly the peripheral using the appropriate bit before stopping the corresponding clock To enable a peripheral you must first enable the corresponding PCKEN bit in the CLK PCKENR registers and then set the peripheral enable bit in the peripheral s control registers The AWU counter is driven by an internal or external clock LSI or HSE independent from faster SO that it continues to run even if the register clock to this peripheral is switched off 2 DoclD14587 Rev 12 RM0016 Clock control CLK 9 6 d Clock security system CSS The Clock Security S
276. becomes pending 1 The hardware signals the event setting the FMP 1 0 bits in the register to the value 0601 The message is available in the FIFO output mailbox The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN RFR register The FIFO becomes empty again If a new valid message has been received in the meantime the FIFO stays in pending 1 state and the new message is available in the output mailbox DoclD14587 Rev 12 Ly RM0016 Controller area network beCAN Note 23 6 3 2 If the application does not release the mailbox the next valid message will be stored in the FIFO which enters pending 2 state FMP 1 0 0010 The storage process is repeated for the next valid message putting the FIFO into pending 3 state FMP 1 0 0b11 At this point the software must release the output mailbox by setting the RFOM bit so that a mailbox is free to store the next valid message Otherwise the next valid message received will cause a loss of message Refer also to Section 23 6 4 Message storage Overrun Once the FIFO is in pending 3 state i e the three mailboxes are full the next valid message reception will lead to an overrun and a message will be lost The hardware signals the overrun condition by setting the FOVR bit in the CAN RFR register Which message is lost depends on the configuration of the FIFO If the FIFO lock function is disabled RFLM bit the C
277. bit basic timer TIM4 TIM6 19 2 TIM4 main features The main features include e 8 bit auto reload up counter e 3 0 programmable prescaler which allows dividing also on the fly the counter clock frequency by 1 2 4 8 16 32 64 and 128 e Interrupt generation counter update Counter overflow 19 3 TIM6 main features The main features include e 8 bit auto reload up counter e 3 0 programmable prescaler which allows dividing also on the fly the counter clock frequency by 1 2 4 8 16 32 64 and 128 e Synchronization circuit to control the timer with external signals and to interconnect several timers See Section 17 4 6 on page 158 e Interrupt generation Oncounter update Counter overflow Ontrigger input 19 4 TIMA TIMG interrupts The timer has 2 interrupt request sources e Update interrupt overflow counter initialization e Trigger input TIM6 only 19 5 TIM4 TIM6 clock selection 2 The clock source for the timer is the internal clock It is connected directly to the PSC clock that feeds the prescaler driving the counter clock CK Prescaler The prescaler implementation is as follows e prescaler is based on a 7 bit counter controlled through a 3 bit register in the TIMx register It can be changed on the fly as this control register is buffered It can divide the counter clock frequency by any power of 2 from 1 to 128 The counter clock frequency i
278. ble by option byte WWDG functional description If the watchdog is activated the WDGA bit is set and when the 7 bit downcounter T 6 0 bits rolls over from 0x40 to Ox3F T6 becomes cleared it initiates a reset cycle pulling low the reset pin If the software refreshes the counter while the counter is greater than the value stored in the window register then a reset is generated DoclD14587 Rev 12 127 595 Window watchdog WWDG 0016 Note 128 595 Figure 28 Watchdog block diagram RESET WATCHDOG WINDOW REGISTER WWDG WR We W5 Ww4 2 1 comparator 1 when T6 0 W6 0 CMP dane Write WWDG_CR WATCHDOG CONTROL REGISTER wWDG_CR WDGA 6 T5 T4 T3 2 T1 TO 7 BIT DOWNCOUNTER CNT A fopu from clock WDG PRESCALER gt DIV 12288 The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset This operation must occur only when the counter value is lower than the window register value The value to be stored in the WWDG_CR register must be between OxFF and 0 0 see Figure 29 Enabling the watchdog When software watchdog is selected by option byte the watchdog is disabled after a reset It is enabled by setting the WDGA bit in the WWDG_CR register th
279. cies up to 24 MHz one wait state is necessary In this case the device option byte should be programmed to insert this wait state Refer to the datasheet option byte section 4 4 3 User boot area UBC The user boot area UBC contains the reset and the interrupt vectors It can be used to store the IAP and communication routines The UBC area has a second level of protection to prevent unintentional erasing or modification during IAP programming This means that it is always write protected and the write protection cannot be unlocked using the MASS keys The size of the UBC area can be obtained by reading the UBC option byte 40 595 DoclD14587 Rev 12 Ly 0016 Flash program memory and data EEPROM The size of the UBC area can be configured in ICP mode using the SWIM interface through the UBC option byte The UBC option byte specifies the number of pages allocated for the UBC area starting from address 0x00 8000 Refer to Figure 9 Figure 10 and Figure 11 for a description of the UBC area memory mapping and to the option byte section in the datasheets for more details on the UBC option byte Figure 9 UBC area size definition on low density STM8S devices 0x00 8000 E 64 bytes Page 0 ig Interrupt vectors 0x00 e gt 64 bytes Page 1 a 0x00 8080 5 64 bytes Page2 x gt lt 0 00 80 0 64 bytes Pags d 8 g 0x00 8100 E 2 a gt LL N 5 64 bytes to 8 Kbytes 2 9 user
280. ck period expressed in ms Warning When writing to the WWDG CR register always write 1 in the T6 bit to avoid generating an immediate reset Figure 29 Approximate timeout duration 7F 78 70 68 60 58 CNT value hex 50 48 40 0 768 6 144 12 288 18 432 24 576 30 72 36 864 43 008 49 152 Watchdog timeout ms 16 MHz fcpu d DoclD14587 Rev 12 129 595 Window watchdog WWDG 0016 Figure 30 Window watchdog timing diagram T 5 0 CNT downcounter A WDGWRE Ox7F 4 gt lt gt time gt Refresh not allowed Refresh Window step 12288 fok wwag ck T6 bit Reset Table 30 Window watchdog timing example fcpu MHz T 6 0 2 16 40h 6 144 0 768 7Fh 393 216 49 152 15 5 WWDG low power modes Table 31 Effect of low power modes on WWDG Mode Description Wait No effect on watchdog The downcounter continues to decrement WWDG HALT in option byte No watchdog reset is generated The MCU enters Halt mode The watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset Halt 0 If an interrupt is received refer to interrupt table mapping to see interrupts which can occur in Halt mode the watchdog restarts counting after the stab
281. ck timing diagram 261 TXE RXNE BSY behavior in full duplex mode RXONLY 0 Case of continuous transfers 266 TXE RXNE BSY behavior in slave full duplex mode 0 RXONLY 0 Case of continuous transfers 266 TXE BSY in master transmit only mode DoclD14587 Rev 12 Ly RM0016 List of figures Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Figure 106 Figure 107 Figure 108 Figure 109 Figure 110 Figure 111 Figure 112 Figure 113 Figure 114 Figure 115 Figure 116 Figure 117 Figure 118 Figure 119 Figure 120 Figure 121 Figure 122 Figure 123 Figure 124 Figure 125 Figure 126 Figure 127 Figure 128 Figure 129 Figure 130 Figure 131 Figure 132 Figure 133 Figure 134 Figure 135 Figure 136 Figure 137 Figure 138 Figure 139 Figure 140 Figure 141 Figure 142 Figure 143 Figure 144 Ly 0 and RXONLY 0 Case of continuous transfers 267 TXE BSY in slave transmit only mode BDM 0 and RXONLY 0 Case of continuous transfers 268 RXNE behavior in receive only mode BDM 0 and RXONLY 1 Case of continuous transfers 269 TXE BSY behavior when transmitting
282. cked directly by the internal clock 001 Reserved 010 Reserved 011 Reserved 100 Trigger reset mode The rising edge of the selected trigger signal TRGI reinitializes the counter and generates an update of the registers 101 Gated mode The counter clock is enabled when the trigger signal TRGI is high The counter stops but is not reset as soon as the trigger becomes low Both start and stop of the counter are controlled 110 Trigger mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 111 External clock mode 1 Rising edges of the selected trigger TRGI clock the counter 3 DoclD14587 Rev 12 RM0016 8 bit basic timer TIM4 TIM6 19 6 4 Interrupt enable register TIMx_IER Address offset 0x01 or 0x03 TIM4 0x03 TIM6 for TIM4 address see Section 19 6 10 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved TIE Reserved UIE r rw r rw Bit 7 Reserved must be kept cleared Bit 6 TIE Trigger interrupt enable 0 Trigger Interrupt disabled 1 Trigger Interrupt enabled Note In TIMA this bit is reserved Bits 5 1 Reserved must be kept cleared Bit Update interrupt enable 0 Update interrupt disabled 1 Update interrupt enabled 19 6 5 Status register 1 TIMx SR Address offset 0x02 or 0x04 TIM4 0x04 TIM6 for TIM4 address see Section 19 6 10 Reset value 0x00 7 6 5 4 3 2 1 0 TIF UIF Re
283. communication on the LIN bus is triggered by the Master sending a Header followed by the response The Header is transmitted by the Master Task master node while the data are transmitted by the Slave task of a node master node or one of the slave nodes Procedure without error monitoring 1 Request Break Delimiter transmission 13 dominant bits and 1 recessive bit by setting the SBK bit in the UART CR2 register 2 Request Synch Field transmission by writing 0x55 in the UART_DR register 3 Wait for the TC flag in the UART SR register 4 Request Identifier Field transmission by writing the protected identifier value in the DR register 5 Wait for the TC flag in the UART SR register Procedure with error monitoring 1 Request Break Delimiter transmission 13 dominant bits and 1 recessive bit by setting the SBK bit in the UART_CR2 register Wait for the LBDF flag in the UART_CR4 register Request Synch Field transmission by writing 0x55 into UART_DR register Wait for the RXNE flag in the UART_SR register and read back the UART_DR register Request Identifier Field transmission by writing the protected identifier value in the UART_DR register 6 Wait for the RXNE flag in the UART_SR register and read back the UART_DR register The LBDF flag is set only if a valid Break Delimiter has been received back on the UART_RX pin eE DoclD14587 Rev 12 343 462 Universal asynchronous receiver transmitter U
284. compare value MSB If the CC4 channel is configured as output CC4S bits TIM1 CCMR4 register The value of CCR4 is loaded permanently into the actual capture compare 4 register if the preload feature is not enabled OC4PE bit in TIM1 CCMR4 Otherwise the preload value is copied in the active capture compare 4 register when UEV occurs The active capture compare register contains the value which is compared to the counter register TIM1_CNT and signalled on the OC4 output If the CC4 channel is configured as input CC4S bits in TIM1_CCMR4 register The value of CCR4 is the counter value transferred by the last input capture 4 event 4 17 7 29 register 4 low TIM1_CCR4L Address offset 0x1C Reset value 0x00 CCR4 7 0 Bits 7 0 CCR4 7 0 Capture compare value LSB 212 595 d DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 7 30 Break register TIM1_BKR Address offset 0x1D Reset value 0x00 MOE AOE BKP BKE OSSR OSSI LOCK rw rw rw rw rw rw rw Bit 7 Bit 6 Bit 5 Bit 4 d MOE Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active It is set by software or automatically depending on the AOE bit It acts only on the channels which are configured in output 0 OC and OCN outputs are disabled or forced to idle stat
285. compared with the filters configured in mask mode If the identifier does not match any of the identifiers configured in the filters the message is discarded by hardware without disturbing the software 2 DoclD14587 Rev 12 RM0016 Controller area network beCAN 23 6 4 2 Message storage The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes A mailbox contains all information related to a message identifier data control status and time stamp information Transmit mailbox The software sets up the message to be transmitted in an empty transmit mailbox The status of the transmission is indicated by hardware in the CAN MCSR register Table 66 Transmit mailbox mapping Offset to Transmit Mailbox base Register name address bytes 0 CAN MCSR 1 CAN MDLCR 2 CAN MIDR1 3 CAN MIDR2 4 CAN MIDRS3 5 CAN MIDR4 6 CAN MDAR1 7 CAN MDAR2 8 CAN MDAR3 9 CAN MDAR4 10 CAN MDAR5 11 CAN MDAR6 12 CAN MDAR7 13 CAN MDAR8 14 CAN MTSRL 15 CAN MTSRH DoclD14587 Rev 12 389 462 Controller area network beCAN RM0016 390 462 Receive mailbox When a message has been received it is available to the software in the FIFO output mailbox Once the software has handled the message e g read it the software must release the FIFO output mailbox by means of the RFOM bit in the CAN_RFR register to make the next incoming
286. ction Please refer to the Asynchronous prescaler register AWU and Timebase selection register AWU_TBR descriptions The AWU time intervals depend on the values of e AWUTBJ8 0 bits This gives the counter output rank e APR 5 0 bits This gives the prescaler division factor 15 non overlapped ranges of time intervals can be defined as follows Table 25 Time base calculation table Interval range formula for AWUTB 3 0 time interval pn fis f fj s 128kHz calculation 2 64 f 0 015625 ms 0 5 ms 0001 APRpiv f s 2 to 64 2x32 f 2x2x32 f 0 5 ms 1 0 ms 0010 2 x APRpi fi 32 to 64 2x64 f 2x2x64 f 1 ms 2 ms 0011 2 x APRpiv fLs 32 to 64 2 x64 f 22x128 f 2ms 4ms 0100 23 x APRpiv fi s 32 to 64 23x64 f 29x128 f 4ms 8ms 0101 2 5 32 to 64 2 x64 t 2 x128 f 8 ms 16 ms 0110 2 x APRpiv fi 5 32 to 64 2 x64 f 25 128 16 ms 32 ms 0111 26 x APRpiv f 5 32 to 64 26x64 t 26x128 t 32 ms 64 ms 1000 27 x APRpiv fi s 32 to 64 27x64 f 2 x128 f 64 ms 128 ms 1001 28 x APRpiv fi s 32 to 64 28 64 28 128 128 ms 256 ms 1010 29 x APRpiv fi 5 32 to 64 29x64 t 29 128 256 ms 512 ms 1011 210 x APRpiv fLs 32 to 64 210x64 f 210x128 f 512 ms 1 024 s 1100 211 x APRpiv fLs 32 to 64 211x64 f 211x128 f 1 024 s 2 048 s 1101 212 x APRpiv fLs 32 to 64 211x130 f 211x320 f 2 080 s 5 120 s 1110 5x211 x APRpyf
287. ction 21 7 9 Status register 3 I2C_SR3 on page 308 Modified title of Table 55 UART receiver tolerance when UART DIV S3 0 is zero on page 332 and Table 56 UART receiver s tolerance when DIV 3 0 is different from zero on page 333 Modified RWU bit description in Section 22 7 6 Control register 2 CR2 on page 362 Modified Section 23 4 2 Normal mode on page 377 Added note to FE bit description in Section 22 7 1 Status register SR on page 358 Modified Section 24 9 Reading the conversion result on page 435 and Section 24 11 2 ADC data buffer register x low DBxRL x or 0 7 or 0 9 DBL 7 0 instead of DB 7 0 2 DoclD14587 Rev 12 0016 Revision history Table 79 Document revision history continued Date Revision Changes Added low density STM8AF devices Replaced all references of STM8A with STM8AF Updated Table 14 Devices with 4 trimming bits Updated Section 11 5 Unused I O pins 07 May 2013 9 Updated Halt Active halt description in Table 68 beCAN behavior in low power modes Added UARTA in Section 22 Universal asynchronous receiver transmitter UART Updated Section 23 4 4 Time triggered communication mode Introduction updated the description of the medium and high density STM8AF devices Section 4 4 1 STM8S and STM8AF memory organization updated the description of Medium density STM8AF devices Section 23 Controller area n
288. d of BSIZE conversions 1 1 1 set In interrupt is Yes and an interrupt is generated and eherated continuous conversion 9 is stopped d DoclD14587 Rev 12 433 462 Analog digital converter ADC 0016 Table 76 ADC interrupts scan mode ADC1 Control bits Status bits Exit Exit 5 from from 5 AWD EOC Wait Halt ul 0 Don t 0 0 0 The flag is set at the end No No care of the scan sequence The flag is set at the end 0 Don t 1 0 0 of the scan sequence Yes No care and an interrupt is generated The flag is set at the end 1 0 0 of the scan sequence if The flag is set at the end at least one of the of the scan sequence AWSXx bits is set The flag is set and an interrupt is generated at the end of the SCAN The flag is set to 1 at the 1 1 0 sequence if at least one end of the scan Yes No Flag is set if conversion of the AWSx bits is set sequence on channel x crosses SCAN conversion is not the thresholds stopped programmed in the ADC HTR and The flag is set atthe end The flag is setto 1 atthe 1 0 1 ADC LTR registers of the scan sequence if end of the scan Yes No at least one of the sequence and an AWSXx bits is set interrupt is generated The flag is set immediately as soon as The flag is set at the end 1 1 1 one of the AWSx bits is ofthe scan sequence Yes No set
289. d counter overflow underflow Bit 1 UDIS Update disable 0 A UEV is generated as soon as a counter overflow occurs or a software update is generated or an hardware reset is generated by the clock trigger mode controller Buffered registers are then loaded with their preload values 1 A UEV is not generated shadow registers keep their value ARR PSC The counter the prescaler are re initialized if the UG bit is set Bit 0 CEN Counter enable 0 Counter disabled 1 Counter enabled 1 One pulse mode is not available on 2 but the OPM bit can be used for other purposes for example to stop the counter properly 3 226 595 DoclD14587 Rev 12 RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 6 2 Control register 2 TIM5_CR2 Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved MMS 2 0 Reserved r rw rw rw r Note This register is only available in TIM5 see Table 42 on page 246 Bit 7 Reserved must be kept cleared Bits 6 4 MMS 2 0 Master mode selection These bits select the information to be sent in master mode to TIM1 and TIM2for synchronization TRGO The combination is as follows 000 Reset the UG bit from the TIM5 EGR register is used as a trigger output TRGO If the reset is generated by the trigger input clock trigger mode controller configured in trigger reset mode the signal on TRGO is delayed compared to the actual reset
290. d by means of the CAN Interrupt Enable Register CAN_IER and CAN Error Interrupt Enable register CAN_EIER Figure 156 Event flags and interrupt generation CAN MSR WKUI gt CAN IER CAN EIER E EEH FIFO INTERRUPT i FFE H x CAN FULL i FOVR gt ERRIE Ewa H EWGFH gt EPVIE 9 CAN ESR EPVF gt p ERRAT H i H MSR STATUS CHANGE ERROR ELEC E gt INTERRUPT prc i TROCPOL TMEIE hH CAN e TheFIFO interrupt can be generated by the following events Reception of a new message FMP bits the CAN register incremented FIFO full condition FULL bit in the CAN RFR register set FIFO overrun condition FOVR bit in the CAN register set e Thetransmit error and status change interrupt can be generated by the following events Transmit mailbox 0 becomes empty RQCPO bit the TSR register set Transmit mailbox 1 becomes empty RQCP1 bit the CAN register set Transmit mailbox 2 becomes empty 2 bit in the TSR register set Error conditi
291. d interrupt subroutines launched at each rising edge of the RXNE flag If it is required to disable the after the last transfer follow the recommendation described in Section 20 3 8 Disabling the SPI on page 272 DoclD14587 Rev 12 2 Serial peripheral interface SPI Figure 98 RXNE behavior in receive only mode BDM z 0 and RXONLY 1 Case of continuous transfers Example with CPOL 1 CPHA 1 RXONLY 1 SCK DATA 1 1 DATA 2 0xA2 DATA 3 OxA3 MISOMMOSI in oo Jor oe eo ve s re or o re o ses Doro fr Fe Jes Jos fes se ae eS RXNE flag read SPI DR Software waits until Software waits until Software waits until RXNE 1 and reads OxA1 RXNE 1 and reads OxA2 RXNE 1 and reads 0xA3 from SPI DR from SPI DR rom SPI DR 3 Bidirectional receive procedure BDM 1 and BDOE 0 In this mode the procedure is similar to the Receive only procedure except that the BDM bit must be set and the BDOE bit must be reset in the SPI CR2 register before enabling the SPI Continuous and discontinuous transfers When transmitting data in master mode if the software is fast enough to detect each TXE rising edge or TXE interrupt and to immediately write the SPI DR register before the ongoing data transfer is complete the communication is said to be continuous In this case there is no discontinuity in the generation of the SPI clock between each data and the
292. d the high to low transition timing DTRA DQUANT DREC DTCL UART receiver s tolerance The UART receiver s tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices 10 or 11 bit character length defined by the M bit in the UART CR1 register Use of fractional baud rate or not Table 55 UART receiver tolerance when UART DIV 3 0 is zero M bit NF is an error NF is don t care 0 3 75 4 375 1 3 41 3 97 DoclD14587 Rev 12 2 RM0016 Universal asynchronous receiver transmitter UART Note 22 3 6 Note 2 Table 56 UART receiver s tolerance when UART DIV 3 0 is different from zero M bit NF is an error NF is don t care 0 3 33 3 88 1 3 03 3 53 The values specified in Table 55 and Table 56 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10 bit times when M 0 11 bit times when 1 Parity control Parity control generation of parity bit in transmission and parity checking in reception can be enabled by setting the PCEN bit in the UART CR1 register Depending on the frame length defined by the M bit the possible UART frame formats are as listed in Table 57 Table 57 Frame format M bit PCEN bit UART frame 0 0 SB 8 bit data STB 0 1 SB 7 bit data PB STB 1 0 SB 9 bit data STB 1 1 SB 8 bit data PB STB
293. d to store the address of the next instruction to be executed by the CPU It is automatically refreshed after each processed instruction As a result the STM8 core can access up to 16 Mbytes of memory DoclD14587 Rev 12 23 595 Central processing unit CPU 0016 Note 24 595 Figure 1 Programming model 7 0 LL TT LT A ACCUMULATOR 15 8 7 0 1 2b V gy INDEX 15 8 7 0 0 Y INDEX 15 8 7 0 EN EE mur pee SP STACK POINTER 23 16 15 8 7 0 PCH O O PEL PC PROGRAM COUNTER 7 0 It HLIOIN Z C CC CODE CONDITION Stack pointer SP The stack pointer is a 16 bit register It contains the address of the next free location of the stack Depending on the product the most significant bits can be forced to a preset value The stack is used to save the CPU context on subroutine calls or interrupts The user can also directly use it through the POP and PUSH instructions The stack pointer can be initialized by the startup function provided with the C compiler For applications written in C language the initialization is then performed according to the address specified in the linker file for C users If you use your own linker file or startup file make sure the stack pointer is initialized properly with the address given in the datasheets For applications written in assembler you can use either the startup function p
294. de fault event MODF Yes No Overrun error OVR ERRIE Yes No CRC error flag CRCERR Yes No 276 595 DoclD14587 Rev 12 d RM0016 Serial peripheral interface SPI 20 4 20 4 1 7 SPI registers SPI control register 1 SPI_CR1 Address offset 0x00 Reset value 0x00 6 5 4 3 2 LSBFIRST SPE BR 2 0 MSTR CPOL CPHA rw rw rw rw rw Bit 7 Bit 6 Bits 5 3 Bit 2 Bit1 Bit 0 LSBFIRST Frame format 7 0 MSB is transmitted first 1 LSB is transmitted first SPE SPI enable 2 0 Peripheral disabled 1 Peripheral enabled BR 2 0 Baud rate control 000 fuAsTER 2 001 4 010 8 011 1 6 100 2 101 fuAsTER 64 110 fmaster 1 28 111 fmaster 256 Note These bits should not be changed when the communication is ongoing Master selection 1 0 Slave configuration 1 Master configuration CPOL Clock polarity 1 0 SCK to 0 when idle 1 SCK to 1 when idle Clock phase 0 The first clock transition is the first data capture edge 1 The second clock transition is the first data capture edge 1 This bit should not be changed when the communication is ongoing 2 When disabling the SPI follow the procedure described in Section 20 3 8 Disabling the SPI on page 272 3 DoclD14587 Rev 12 277 595 Serial peripheral interface SPI
295. debug module interrupt controller registers table in the datasheet 2 The address offsets are expressed for the ITC EXTI block base address see General hardware register map table in the datasheet d DoclD14587 Rev 12 71 595 Power supply 0016 7 72 462 Power supply The MCU has four distinct power supplies e Vpp Vss Main power supply 3 V to 5 5 V e Vppio Vssio power supply 3 V to 5 5 V e Vppa Vssa Power supply for the analog functions e VRef Vrer Reference supply for Analog Digital Converter The Vpp Vss pins are used to supply the internal Main Voltage Regulator MVR and the internal Low Power Voltage Regulator LPVR The 2 regulator outputs are connected and provide the 1 8 V supply to the MCU core CPU Flash RAM In low power modes the system automatically switches from the MVR to the LPVR in order to reduce current consumption To stabilize the MVR a capacitor must be connected to the VCAP pin for more details refer to the datasheet electrical characteristics section Depending on the package size there are one or two pairs of dedicated pins for Vppio Vssio to supply power to the 1 VppA VssA and Vngr Vngr are connected to the Analog to Digital Converter ADC Figure 17 Power supply overview 3V 5 5V VDDA I 1 ssa 1 7 Vere A D converter Vne
296. description Bit 1 CC3P 3 output polarity Refer to CC1P description Bit CC3E Capture compare 3 output enable Refer to CC1E description 17 7 15 Counter high TIM1 CNTRH Address offset OXOE Reset value 0x00 CNT 15 8 Bits 7 0 CNT 15 8 Counter value MSB 206 595 DoclD14587 Rev 12 2 RM0016 16 bit advanced control timer TIM1 17 7 16 Counter low TIM1 CNTRL Address offset 0 0 Reset value 0x00 7 6 5 4 3 2 1 0 CNT 7 0 rw rw rw rw rw rw rw rw Bits 7 0 CNT 7 0 Counter value LSB 17 7 17 Prescaler high TIM1 PSCRH Address offset 0x10 Reset value 0x00 7 6 5 4 3 2 1 0 PSC 15 8 rw rw rw rw rw rw rw rw PSC 15 8 Prescaler value MSB The prescaler value divides the CK_PSC clock frequency The counter clock frequency is Bits 7 0 equal to fox psc PSCR 15 0 1 PSCR contain the value which is loaded in the active prescaler register at each UEV including when the counter is cleared through the UG bit of the TIM1 EGR register or through the trigger controller when configured in trigger reset mode A UEV must be generated so that a new prescaler value can be taken into account 17 7 18 Prescaler low TIM1 PSCRL Address offset 0x11 Reset value 0x00 7 6 5 4 3 2 1 0 PSC 7 0 rw rw rw rw rw rw rw rw Bits 7 0 PSC 7 0 Prescaler
297. ding IDR bit returns the digital value from the corresponding I O pin Using the CR1 CR2 registers different output modes can be configured by software Push pull output Open drain output Refer to Section 11 8 Output mode details on page 109 for more information Reset configuration All I O pins are generally input floating under reset i e during the reset phase and at reset state i e after reset release However a few pins may have a different behavior Refer to the datasheet pinout description for all details Unused pins Unused I O pins must not be left floating to avoid extra current consumption They must be put into one of the following configurations e connected to Vpp or Vss by external pull up or pull down resistor and kept as input floating reset state e configured as input with internal pull up down resistor e configured as output push pull low The ports not present on smaller packages are automatically configured by a factory setting unless otherwise specified in the datasheet As a consequence no configuration is required on these ports bits corresponding to these ports in the configuration registers Px ODR PxDDR PxCR1 and PxCR2 can be written but this will have no effect The value read in the corresponding bits of the PxIDR register will be 0 Low power modes Table 22 Effect of low power modes on GPIO ports Mode Description No effect on ports External interr
298. ding on the value of the LSBFIRST bit in the SPI CR1 Register 2 DoclD14587 Rev 12 261 595 Serial peripheral interface SPI 0016 20 3 2 Note 20 3 3 262 595 Configuring the SPI in slave mode In slave configuration the serial clock is received on the SCK pin from the master device The value set in the BR 2 0 bits in the CR1 register does not affect the data transfer rate Follow the procedure below to configure the SPI in slave mode 1 Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 93 For correct data transfer the CPOL and CPHA bits must be configured in the same way in the slave device and the master device 2 Theframe format MSB first or LSB first depending on the value of the LSBFIRST bit in the SPI CR1 register must be the same as the master device 3 Hardware mode refer to Slave select NSS pin management on page 259 the NSS pin must be connected to a low level signal during the complete data transmit sequence In NSS Software mode set the SSM bit and clear the SSI bit in the SPI CR2 register 4 Clear the MSTR bit and set the SPE bit to assign the pins to alternate functions In this configuration the MOSI pin is a data input and the MISO pin is a data output In applications with a parallel multi slave structure with separate NSS signals and the slave MISO outputs connected together the correspo
299. dog is started by writing the value OxCC in the key register IWDG KR the counter starts counting down from the reset value of OXFF When it reaches the end of count value 0x00 a reset signal is generated IWDG RESET Once enabled the independent watchdog can be configured through the IWDG PR and IWDG registers The IWDG register is used to select the prescaler divider feeding the counter clock Whenever the KEY REFRESH value 0xAA is written in the IWDG KR register the IWDG is refreshed by reloading the IWDG RLR value into the counter and the watchdog reset is prevented The IWDG PR and IWDG RLR registers are write protected To modify them first write the KEY ACCESS code 0x55 in the IWDG KR register The sequence can be aborted by writing OxAA in the IWDG KR register to refresh it Refer to Section 14 3 IWDG registers for details on the IWDG registers Figure 27 Independent watchdog IWDG block diagram 128 kHz LSI IWDG PR IWDG_RLR IWDG_KR lock register reload register key register ee S SSS IT 4 7 bit WDG reset 2 L 8 bit down counter prescaler Hardware watchdog feature If the hardware watchdog feature has been enabled through the IWDG HW option byte the watchdog is automatically enabled at power on and generates a reset unless the key register is written by the software before the counter reaches end of count
300. down mode Conversion starts when this bit holds a value of 1 and a 1 is written to it As soon as the ADC is powered on the output stage of the selected channel is disabled 0 Disable ADC conversion calibration and go to power down mode 1 Enable ADC and to start conversion Note If any other bit in this register apart from ADON is changed at the same time then conversion is not triggered This is to prevent triggering an erroneous conversion DoclD14587 Rev 12 439 462 Analog digital converter ADC RM0016 24 11 5 T ADC configuration register 2 ADC_CR2 Address offset 0x22 Reset value 0x00 6 2 0 Reserved EXTTRIG EXTSEL 1 0 ALIGN Reserved SCAN Reserved r rw rw r r Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 440 462 Reserved must be kept cleared EXTTRIG External trigger enable This bit is set and cleared by software It is used to enable an external trigger to trigger a conversion 0 Conversion on external event disabled 1 Conversion on external event enabled Note To avoid a spurious trigger event use the BSET instruction to set EXTTRIG without changing other bits in the register EXTSEL 1 0 External event selection The two bits are written by software They select one of four types of event used to trigger the start of ADC conversion 00 Internal TIM1 TRGO event 01 External interrupt on ADC_ETR 10
301. dware into normal mode Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception Hardware signals this event by clearing the INAK bit in the CAN MSR register Software sets this bit to request the CAN hardware to enter initialization mode Once software has set the INRQ bit the CAN hardware waits until the current CAN activity transmission or reception is completed before entering the initialization mode Hardware signals this event by setting the INAK bit in the register 23 11 2 master status register CAN Address offset 0x01 Reset value 0x02 7 6 5 4 3 2 1 0 Reserved RX TX WKUI ERRI SLAK INAK r r r rc w1 rc w1 r r Bits 7 6 Reserved Bit 5 RX Receive 1 The CAN hardware is currently receiver Bit4 TX Transmit 1 The CAN hardware is currently transmitter Bit 3 WKUI Wakeup Interrupt This bit is set by hardware to signal that a SOF bit has been detected while the CAN hardware was in sleep mode Setting this bit generates a status change interrupt if the WKUIE bit in the IER register is set This bit is cleared by software writing 1 d DoclD14587 Rev 12 397 462 Controller area network beCAN RM0016 Bit 2 ERRI Error Interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in
302. e Eee ee ec RE Ve Ea 82 9 2 2 Master clock switching procedures 82 9 3 Low speed clock selection 85 9 4 85 9 5 Peripheral clock gating PCG 86 9 6 Clock security system CSS 87 4 462 DoclD14587 Rev 12 Ky RM0016 Contents 9 7 Clock out capability 88 9 8 CLK interrupts hd acera NOS ag 88 9 9 CLK register description 89 9 9 1 Internal clock register CLK ICKR 89 9 9 2 External clock register CLK 90 9 9 3 Clock master status register CLK 91 9 9 4 Clock master switch register CLK 5 91 9 9 5 Switch control register CLK SWCR 92 9 9 6 Clock divider register CLK CKDIVR 93 9 9 7 Peripheral clock gating register 1 CLK_PCKENR1 94 9 9 8 Peripheral clock gating register 2 CLK PCKENR2 95 9 9 9 Clock security system register CLK 5 96 9 9 10 Configurable clock output register CLK CCOR 97 9 9 11 clock calibration trimming register
303. e In down counting mode the counter counts from the auto reload value content of the TIM1 ARR register down to O It then restarts from the auto reload value and generates a counter underflow and UEV if the UDIS bit is 0 in the TIM1 register Figure 37 shows an example of this counting mode Figure 37 Counter in down counting mode Counter TIMx ARR gt 0 Underflow Underflow Underflow Underflow An update event can also be generated by setting the UG bit in the EGR register by software or by using the clock trigger mode controller The UEV update event can be disabled by software by setting the UDIS bit in TIM1_CR1 register This is to avoid updating the shadow registers while writing new values in the preload registers No update event occurs until the UDIS bit has been written to O However the counter restarts from the current auto reload value whereas the counter of the prescaler restarts from 0 without any change to the prescale rate In addition if the URS bit update request selection in the TIM1 CR1 register is set setting the UG bit generates a UEV without setting the UIF flag thus no interrupt request is sent This avoids generating both update and capture interrupts when clearing the counter on the capture event When an update event occurs all the registers are updated and the update flag UIF bit in SR1 register is set depending on the URS bit
304. e write DR i 1 BSY flag get by hw reset by hw DATA 1 OxA1 DATA 2 0xA2 DATA 3 0xA3 wsomosi my ep oa oe os oo 7 ober Te Le fes Tor o Te a es Jos er RXNE emp m Rx Buffer read SPI DR 7 2 Yi software Software waits Software waits software waits software waits until Software waits until rites OxF1 until 1 and until RXNE 1 until TXE 1 and RXNE 1 and reads 0 2 RXNE 1 and reads in SPI DR writes OxF2 in and reads OxA1 writes OXF3 from SPI DR from SPI DR SPI DR rom SPI DR SPI DR 266 595 DoclD14587 Rev 12 ky RM0016 Serial peripheral interface SPI Note 1 Transmit only procedure BDM 0 RXONLY 0 In this mode the procedure can be reduced as described below and the BSY bit can be used to wait until the effective completion of the transmission see Figure 94 and Figure 95 1 Enable the SPI by setting the SPE bit 2 Write the first data to send in the SPI_DR register this clears the TXE bit 3 Wait until TXE 1 and write the next data to be transmitted Repeat this step for each data to be transmitted 4 After writing the last data in the SPI DR register wait until 1 and then wait until BSY 0 which indicates that the transmission of the last data is complete This procedure can be also implemented using dedicated interru
305. e 1 OC and outputs are enabled if their respective enable bits are set CC E in CCERi registers See OC OCN enable description for more details Section 17 7 13 on page 203 AOE Automatic output enable 0 MOE can be set only by software 1 MOE can be set by software or automatically at the next UEV if the break input is not active Note This bit can no longer be modified while LOCK level 1 has been programmed LOCK bits in the register Break polarity 0 Break input BKIN is active low 1 Break input BKIN is active high Note This bit can no longer be modified while LOCK level 1 has been programmed LOCK bits in the register BKE Break enable 0 Break input BKIN disabled 1 Break input BKIN enabled Note This bit can no longer be modified while LOCK level 1 has been programmed LOCK bits in the TIM1 register DoclD14587 Rev 12 213 595 16 bit advanced control timer TIM1 0016 Bit 3 OSSR state selection for Run mode This bit is used when 1 on channels with a complementary output which are configured as outputs See OC OCN enable description for more details Section 17 7 13 0 When inactive OC OCN outputs are disabled OC OCN enable output signal 0 1 When inactive outputs are enabled with their inactive level as soon as CCE 1 or CONE 1 after which the OC OCN enable output signal 1 Note This bit can no longer be
306. e 136 and Figure 137 UARTDIV can be updated by two concurrent actions a transfer from UARTDIV MEAS at the end of the LIN Sync Field and a transfer from UARTDIV NOM due to a software write to BRR1 If both operations occur at the same time the transfer from UARTDIV NOM has priority Figure 136 UARTDIV read write operations when LDUM 0 Write UART2 BRR1 Write UART2 BRR2 LIN Sync Field UARTDIV 15 2 UARTDIV 3 0 UARTDIV NOM Measurement wo UART2 BRR 4 VARTDIV 15 12 uaRTDIV MEAS UARTDIV 3 0 Update at end of et ynch Field v UARTDIV 1 1 4 UARTDIV 15 12 UARTDIV UARTDIV 7 0 Baud Rate Generation Read UART2_BRR1 Read UART2 BRR2 DoclD14587 Rev 12 351 462 Universal asynchronous receiver transmitter UART 0016 352 462 Figure 137 UARTDIV read write operations when LDUM 1 Write UART2 BRR1 Write UART2 BRR2 LIN Sync Field 41 UARTDIV 15 12 UARTDIV 1 1 4 UARTDIV 3 0 UARTDIV NOM Measurement UARTDIV 11 4 TRETORN 1 UARTDIV_MEAS Update at end of LDUM is reset Synch Field v 4 UARTDIV 15 12 UARTDIV Baud Rat UARTDIV 1 1 4 UARTDIV 3 0 DV 2 K Read UART2_BRR1 Read UART2 BRR2 Deviation error on the synch field The deviation error is checked by comparing the current baud rate relative to the slave osc
307. e BTF bit is set by hardware and the interface waits for the BTF bit to be cleared by reading I2C SR1 and then 2 DR stretching SCL low Closing the communication Method 1 This method is for the case when the I2C is used with interrupts that have the highest priority in the application The master sends a NACK for the last byte received from the slave After receiving this NACK the slave releases the control of the SCL and SDA lines Then the master can send a Stop Re Start condition e order to generate the non acknowledge pulse after the last received data byte the ACK bit must be cleared just after reading the second last data byte after second last RXNE event e order to generate the Stop Re Start condition software must set the STOP START bit just after reading the second last data byte after the second last RXNE event e Incase a single byte is to be received the Acknowledge deactivation and the STOP condition generation are made just after EV6 in EV6 7 just after ADDR is cleared After the Stop condition generation the interface goes automatically back to slave mode MSL bit cleared Method 1 This method is for the case when the I2C is used with interrupts that have the highest priority in the application Figure 105 Method 1 transfer sequence diagram for master receiver 7 bit Master Receiver 5 Address Data1 A Data2 AO DataN NA P 1 10 bit Master Rec
308. e a read or write access to the SPI SR register while the MODF bit is set 2 Then write to the SPI CR1 register To avoid any multiple slave conflicts in a system comprising several MCUs the NSS must be pulled high during the MODF bit clearing sequence The SPE and MSTR bits can be restored to their original state after this clearing sequence As a security hardware does not allow you to set the SPE and MSTR bits while the MODF bit is set In a slave device the MODF bit cannot be set However in a multi master configuration the device can be in slave mode with this MODF bit set In this case the MODF bit indicates that there might have been a multimaster conflict for system control You can use an interrupt routine to recover cleanly from this state by performing a reset or returning to a default state Overrun condition An overrun condition occurs when the master device has sent data bytes and the slave device has not cleared the RXNE bit resulting from the previous data byte transmitted When an overrun condition occurs e OVR bit is set and an interrupt is generated if the ERRIE bit is set In this case the receiver buffer contents will not be updated with the newly received data from the master device A read to the SPI DR register returns this byte All other subsequently transmitted bytes are lost Clearing the OVR bit is done by a read access to the SPI DR register followed by a read access to the SPI SR register
309. e asynchronous a resynchronization circuit has been inserted between the actual signal acting on the outputs and the synchronous control bit accessed in the TIM1_BKR register It results in some delays between the asynchronous and the synchronous signals For example if MOE is written to 1 after it has been low a delay dummy instruction must be inserted before it can be read correctly d DoclD14587 Rev 12 179 595 16 bit advanced control timer TIM1 0016 Note 180 595 When a break occurs selected level on the break input e MOE bitis cleared asynchronously putting the outputs in inactive state idle state or reset state selected by the OSSI bit This happens even if the MCU oscillator is off e Each output channel is driven with the level programmed in the OISibits in the TIM1 OISR register as soon as 0 If OSSI 0 the timer releases the enable output otherwise the enable output remains high e When complementary outputs are implemented outputs are first put in inactive state depending on the polarity This is done asynchronously so that it works even if no clock is provided to the timer Ifthe timer clock is still present the deadtime generator is reactivated to drive the outputs with the level programmed in the OIlS and OISi bits after a deadtime Even in this case OCi and OCi cannot be driven to their active level together Note that because of the resynchroniz
310. e communication In case of slave to slave communication and if the master does not need to check errors in the response the application can ignore the RXNE flag till the next frame slot The RXNE and OR flags should be cleared before starting the next Break transmission Receiving back a Break will also set the RXNE and FE flags before setting the LBDF flag Therefore if the RX interrupt is used it s better to disable it by clearing the RIEN bit in the UART_CR2 register before sending the Break to avoid an additional interrupt In case of slave to slave communication RIEN bit can be cleared once the header has been transmitted d DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART 22 4 2 Note Note d Slave mode with automatic resynchronization disabled This feature is only available in UART2 UART3 and UAHTA UART initialization Procedure 1 Selectthe desired baudrate by programming UART BRR2 and UART BRH1 registers 2 Enable transmitter and receiver by setting TEN and REN bits in UART_CR2 register 3 Enable LSLV bit in UART CR6 register 4 Enable LIN mode by setting LINEN bit in UART_CR3 register LIN Header reception According to the LIN protocol a slave node must wait for a valid header coming from the master node Then application has to take following action depending on the header Identifier value e Receive the response e Transmit the response e ignore the respo
311. e compare 1 interrupt Update interrupt Trigger interrupt TIM5 only To use the interrupt features for each interrupt channel used set the desired CC3IE and or CC2IE and or CC1IE bits in the TIMx IER register to enable interrupt requests The different interrupt sources can be also generated by software using the corresponding bits in the TIMx EGR register DoclD14587 Rev 12 225 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 6 TIM2 TIMS TIMS registers 18 6 1 Control register 1 TIMx CR1 Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 ARPE Reserved OPM URS UDIS CEN rw r rw rw rw rw Bit 7 ARPE Auto reload preload enable 0 TIMx_ARR register is not buffered through a preload register It can be written directly 1 TIMx_ARR register is buffered through a preload register Bits 6 4 Reserved Bit 3 OPM One pulse mode 7 0 Counter is not stopped at update event 1 Counter stops counting at the next update event clearing the CEN bit Bit 2 URS Update request source 0 When enabled by the UDIS bit the UIF bit is set and an update interrupt request is sent when one of the following events occurs Registers are updated counter overflow underflow UG bit is set by software Update event is generated through the clock trigger controller 1 When enabled by the UDIS bit the UIF bit is set and an update interrupt request is sent only when registers are update
312. e corresponding software sequence EV7 software sequence must be completed before the end of the current byte transfer In case EV7 software sequence can not be managed before the current byte end of transfer it is recommended to use BTF instead of RXNE with the drawback of slowing the communication The EV6 1 or EV7 1 software sequence must be completed before the ACK pulse of the current byte transfer See also Note 8 on page 306 Method 2 This method is for the case when the 2 is used with interrupts that do not have the highest priority in the application or when the I2C is used with polling With this method DataN 2 is not read so that after DataN 1 the communication is stretched both RxNE and BTF are set Then the ACK bit must be cleared before reading DataN 2 in DR to make sure this bit has been cleared before the DataN Acknowledge pulse After that just after reading DataN 2 software must set the STOP START bit and read DataN 1 After RxNE is set read DataN This is illustrated in the following figure Figure 106 Method 2 transfer sequence diagram for master receiver when gt 2 7 bit master receiver 5 Address Data1 A Data2 A DataN 2 DataN 1 A DataN NA P EV5 EV6 EV7 EV7 2 EV7 10 bit master receiver
313. e error passive state When the counter value exceeds 255 the CAN controller enters the bus off state DoclD14587 Rev 12 405 462 Controller area network beCAN 0016 23 11 12 CAN receive error counter register CAN RECR Address offset See Table 71 Reset value 0000 0000 00h 7 6 5 4 3 2 1 0 REC 7 0 Bits 7 0 REC 7 0 Receive error counter This is the Receive Error Counter implementing part of the fault confinement mechanism of the CAN protocol In case of an error during reception this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN standard After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128 When the counter value exceeds 127 the CAN controller enters the error passive state 23 11 13 CAN bit timing register 1 CAN 1 Address offset See Table 71 Reset value 0100 0000 40h 7 6 5 4 3 2 1 0 SJW 1 0 BRP 5 0 rw rw rw rw rw rw rw rw This register can only be accessed by the software when the CAN hardware is in initialization mode Bits 7 6 SJW 1 0 Resynchronization jump width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization Resynchronization Jump Width SUW 1 Bits 5 0 BRP 5 0 Baud rate prescaler These bits define the length of a time quantum tq
314. e is written in the counter that is greater than the auto reload value TIM1 gt ARR For example if the counter is counting up it continues to do so direction is updated if 0 or the TIM1 ARR value are written in the counter but no UEV is generated e safest way to use center aligned mode is to generate an update by software setting the UG bit in the TIM1 EGR register just before starting the counter Avoid writing to the counter while it is running d DoclD14587 Rev 12 147 595 16 bit advanced control timer TIM1 0016 17 3 7 148 595 Repetition down counter Section 17 3 TIM1 time base unit describes how the UEV is generated with respect to counter overflows underflows It is generated only when the repetition down counter reaches zero This can be useful while generating PWM signals This means that data are transferred from the preload registers to the shadow registers TIM1 ARR auto reload register TIM1 PSCR prescaler register and TIM1 CCRx capture compare registers in compare mode every n counter overflow or underflow where N is the value in the TIM1 RCR repetition counter register The repetition down counter is decremented e At each counter overflow in up counting mode e At each counter underflow in down counting mode e At each counter overflow and at each counter underflow in center aligned mode Although this limits the maximum number of repetitions to 128 PWM cycle
315. e line detection 4 Address Mark Detection wakeup configuration WAKE bit 1 the RWU bit cannot be modified by software while the RXNE bit is set 3 DoclD14587 Rev 12 363 462 Universal asynchronous receiver transmitter UART 0016 22 7 7 Control register 3 UART CR3 Address offset 0x06 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved LINEN STOP 1 0 CLKEN CPOL CPHA LBCL r rw rw rw rw rw rw rw Bit7 Reserved must be kept cleared Bit 6 LINEN LIN mode enable This bit is set and cleared by software 0 LIN mode disabled 1 LIN mode enabled Bits 5 4 STOP STOP bits These bits are used for programming the stop bits 00 1 Stop bit 01 Reserved 10 2 Stop bits 11 1 5 Stop bits Note For LIN slave mode both bits should be kept cleared Bit 3 CLKEN Clock enable This bit allows the user to enable the SCLK pin 0 SLK pin disabled 1 SLK pin enabled Note This bit is not available for UARTS Bit 2 CPOL Clock polarity 7 This bit allows the user to select the polarity of the clock output on the SCLK pin It works in conjunction with the CPHA bit to produce the desired clock data relationship 0 SCK to 0 when idle 1 SCK to 1 when idle Note This bit is not available for UARTS Bit 1 Clock phase This bit allows the user to select the phase of the clock output on the SCLK pin It works in conjunction with the CPOL bit to produce the desired clock data relatio
316. ears all the status bits ALST and TERR in the CAN MCSR register and the corresponding RQCPx and TXOKx bits in the register Bit 1 ABRQ Abort request for mailbox Set by software to abort the transmission request for the corresponding mailbox Cleared by hardware when the mailbox becomes empty Setting this bit has no effect when the mailbox is not pending for transmission Bit TXRQ Transmit mailbox request Set by software to request the transmission for the corresponding mailbox Cleared by hardware when the mailbox becomes empty CAN mailbox filter match index register CAN MFMIR Address offset See Table 66 and Table 67 Reset value 0 FMI 7 0 r r r r r r r r Note This register is implemented only in receive mailboxes In transmit mailboxes the CAN MCSR register is mapped at this location Bits 7 0 FMI 7 0 Filter match index This register contains the index of the filter the message stored in the mailbox passed through For more details on identifier filtering please refer to Section 23 6 3 Identifier filtering Filter Match Index paragraph 2 DoclD14587 Rev 12 409 462 Controller area network beCAN RM0016 7 CAN mailbox identifier register 1 CAN MIDR1 Address offset See Table 66 and Table 67 Reset value 0 6 5 4 3 2 1 0 Reserved IDE RTR STID 10 6 EXID 28 24 r rw rw rw Bit 7 Bit 6 Bit 5
317. ection and Section 22 3 5 Clock deviation tolerance of the UART receiver in Section 22 3 3 Receiver Added a caution to Section 23 11 15 Mailbox registers Updated description of TGT in CAN mailbox data length control register CAN_MDLCR Changed alignment of threshold registers and added note for data buffer base address in Section 24 11 ADC registers 08 Dec 2009 Peripheral clock gating register 2 CLK_PCKENR2 Replaced address offset Table 20 Low power mode management Updated peripheral information for Active halt Active halt with MVR auto power off and Halt Repetition counter register TIM1 RCR Replaced the reset value Interrupt enable register TIMx IER Corrected name of bit 3 in register table Status register 1 TIMx SH1 Added description of bit 3 CC3IF to register description table Figure 93 Data clock timing diagram Removed from master and from slave beneath MISO and MOSI respectively Section 20 3 5 Data transmission and reception procedures timing diagrams revised and description of receive only mode expanded Added Section 20 3 8 Disabling the SPI Master mode fault MODF SPE and MSTR bits can be returned to their original state only after a MODF bit clearing sequence interrupt control register SPI ICR Removed notes relating to the TXIE and RXIE bits DoclD14587 Rev 12 Ly RM0016 Revision history d Table 79 Docu
318. ects the data capture clock edge Figure 93 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The diagram may be interpreted as a master or slave timing diagram where the SCK pin the MISO pin the MOSI pin are directly connected between the master and the slave device Prior to changing the CPOL CPHA bits the SPI must be disabled by resetting the SPE bit Master and slave must be programmed with the same timing mode The idle state of SCK must correspond to the polarity selected in the SPI 1 register by pulling up SCK if CPOL 1 or pulling down SCK if CPOL 0 d DoclD14587 Rev 12 0016 Serial peripheral interface SPI Figure 93 Data clock timing diagram CPHA 1 CPOL 1 A 0 Y EUOPTTCSPSEDEJQUSERUC vos AM Bit 6 Bit 5 4 Bit3 2 2 m P to slave CAPTURE STROBE CPOL 1 _ LLLI LI Lo CPOL 0 A MISO AM m Bit 6 Bit 5 Bit 4 Bits Bit 2 Bit 1 Bit 6 Bits Bits 2 Bit 1 to slave i CAPTURE STROBE 1 These timings are shown with the LSBFIRST bit reset in the SPI CR1 register Frame format Data can be shifted out either MSB first or LSB first depen
319. ed Set by hardware when the interface loses the arbitration of the bus to another master Cleared by software writing 0 or by hardware when PE 0 After an ARLO event the interface switches back automatically to Slave mode MSL 0 BitO BERR Bus error 0 No misplaced Start or Stop condition 1 Misplaced Start or Stop condition Set by hardware when the interface detects a SDA rising or falling edge while SCL is high occurring in a non valid position during a byte transfer Cleared by software writing 0 or by hardware when PE 0 2 DoclD14587 Rev 12 307 595 Inter integrated circuit 2 interface 0016 21 7 9 Status register 3 2 SR3 Address offset 0x09 Reset value 0x00 6 5 4 3 2 1 0 DUALF Reserved GENCALL Reserved TRA BUSY MSL r r r r r r Bit 7 Bits 6 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note 308 595 DUALF Dual flag Slave mode 0 Received address matched with OAR1 1 Received address matched with OAR2 Cleared by hardware after a Stop condition or repeated Start condition or when PE 0 Reserved GENCALL General call header Slave mode 0 No general call 1 General call header received when ENGC 1 Cleared by hardware after a Stop condition or repeated Start condition or when PE 0 Reserved TRA Transmitter Receiver 0 Data bytes received 1 Data bytes transmitted This bit is set depending on R W bit of address by
320. ed in the acknowledge slot of a data remote frame in Loop Back Mode In this mode the beCAN performs an internal feedback from its Tx output to its Rx input The actual value of the CANRX input pin is disregarded by the beCAN The transmitted messages can be monitored on the pin DoclD14587 Rev 12 Ly 0016 Controller area network beCAN Note As the Tx line is still active in this mode be aware that it can disturb the communication on the CAN bus 23 5 3 Loop back combined with silent mode It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and SILM bits in the CAN DGR register This mode can be used for a Hot Selftest meaning the beCAN can be tested like in Loop Back mode but without affecting a running CAN system connected to the CANTX and CANRX pins In this mode the CANRX pin is disconnected from the beCAN and the CANTX pin is held recessive Figure 145 beCAN in combined mode beCAN Tx Rx 23 6 Functional description 23 6 1 Transmission handling 2 order to transmit a message the application must select empty transmit mailbox set up the identifier the data length code DLC and the data before requesting the transmission by setting the corresponding TXRQ bit in the MCSR register Once the mailbox has exited empty state the software no longer has write access to the mailbox registers
321. egister as active CCO source or as clock source for the AWU peripheral or independent Watchdog 0 Low speed internal RC off 1 Low speed internal RC on DoclD14587 Rev 12 89 462 Clock control CLK 0016 Bit 2 FHWU Fast wakeup from Halt Active halt modes This bit is set and cleared by software 0 Fast wakeup from Halt Active halt modes disabled 1 Fast wakeup from Halt Active halt modes enabled Bit 1 HSIRDY High speed internal oscillator ready This bit is set and cleared by hardware 0 HSI clock not ready 1 HSI clock ready Bit 0 HSIEN High speed internal RC oscillator enable This bit is set and cleared by software It is set by hardware whenever the HSI oscillator is required for example When activated as safe oscillator by the CSS When switching to HSI clock see CLK SWR register When HSI is selected as the active source see CLK CCOR register It cannot be cleared when HSI is selected as clock master CLK CMSR register as active CCO source or if the safe oscillator AUX is enabled 0 High speed internal RC off 1 High speed internal RC on 9 9 2 External clock register CLK ECKR Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved HSERDY HSEEN r r rw Bits 7 2 Reserved must be kept cleared Bit 1 HSERDY High speed external crystal oscillator ready This bit is set and cleared by hardware 0 HSE clock not ready 1 HSE clock ready HSE clock is stabilized
322. eiver EV5 6 EV6 1 EV7 EV7 EV7 1 EV7 In case of a single byte to be received it is a S Header A Address A EV5 EV9 Eve gt S Header A Data1 A DataN NA P EV5 6 EV6_1 EV7 7 EV7_1 EV7 1 Legend S Start S Repeated Start P Stop A Acknowledge NA Non acknowledge EVx Event with interrupt if ITEVTEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing DR register EV6 ADDR 1 cleared by reading SR1 register followed by reading SR3 In 10 bit master receiver mode this sequence should be followed by writing CR2 with START 1 292 595 DoclD14587 Rev 12 Ly RM0016 Inter integrated circuit PC interface d 6 7 EV6 1 no associated flag event used for 1 byte reception only Program ACK 0 STOP 1 after clearing ADDR EV7 RxNE 1 cleared by reading DR register 1 RxNE 1 cleared by reading DR register program 0 and STOP request EV9 ADD10 1 cleared by reading SR1 register followed by writing DR register If the DR and shift registers are full the next data reception 2 clock generation for slave is performed after the EV7 event is cleared In this case EV7 does not overlap with data reception If a single byte is received it is NA EV5 EV6 and EV9 events stretch SCL low until the end of th
323. elect SCAN Scan mode DBUF Buffered mode Internal TRGO trigger from TIM1 Refer to the product datasheet for AIN12 availability DoclD14587 Rev 12 ADON Start conversion software CONT Single continuous mode Address data bus d RM0016 Analog digital converter ADC Figure 160 ADC2 block diagram 80 64 1 oo devices REF only VppA Vssa ANALOG MUX 5 ANI 3 AIN15 L 4 GPIO Ports EOC Interrupt to CPU DATA REGISTER 1 x 10 bit po Address data bus ANALOG TODIGITAL fapc Prescaler fMASTER lt CONVERTER 2 13 4 18 3 CH 2 0 Channel select CONT Single Continuous ADON Power on Start conversion Internal TRGO trigger from TIM1 d DoclD14587 Rev 12 425 462 Analog digital converter ADC 0016 24 4 24 5 24 5 1 24 5 2 426 462 ADC pins Table 72 ADC pins Name Signal type Remarks V Input Analog Analog power supply This input is bonded to Vpp in supply devices that have no external Vppa pin V Input Analog Ground for analog power supply This input is bonded to 55 supply ground Vss in devices that have no external pin The lower negative reference voltage for the ADC V Input Anal
324. ely on the initial setup and should always fill all the configuration bits accordingly CAN message control status register CAN_MCSR Address offset See Table 66 and Table 67 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved TERR ALST TXOK RQCP ABRQ TXRQ r r r r rc w1 rs rs Note This register is implemented only in transmit mailboxes In receive mailboxes the CAN_MFMIR register is mapped at this location Bits 7 6 Reserved Bit 5 TERR Transmission error This bit is updated by hardware after each transmission attempt 0 The previous transmission was successful 1 The previous transmission failed due to an error Bit 4 ALST Arbitration lost This bit is updated by hardware after each transmission attempt 0 The previous transmission was successful 1 The previous transmission failed due to an arbitration lost Bit3 TXOK Transmission OK 408 462 The hardware updates this bit after each transmission attempt 0 The previous transmission failed 1 The previous transmission was successful Note This bit has the same value as the corresponding TXOKx bit in the CAN register d DoclD14587 Rev 12 0016 Controller area network beCAN Bit 2 RQCP Request completed Set by hardware when the last request transmit or abort has been performed Cleared by software writing a 1 or by hardware on transmission request Note This bit has the same value as the corresponding RQCPx bit of the CAN register Clearing this bit cl
325. en an input capture occurs e The TIM1_CCR1 register gets the value of the counter on the active transition e input capture flag CC1IF is set The overcapture flag CC1OF is also set if at least two consecutive captures occur while the flag remains uncleared e An interrupt is generated depending on the CC1IE bit To handle the overcapture event CC1OF flag it is recommended to read the data before the overcapture flag This avoids missing an overcapture which could occur after reading the flag and before reading the data Note IC interrupts can be generated by software by setting the corresponding CCiG bits in the d TIM1_EGR register DoclD14587 Rev 12 167 595 16 bit advanced control timer TIM1 0016 PWM input signal measurement This mode is a particular case of input capture mode see Figure 65 The procedure is the same except e Two ICisignals are mapped on the same Tli input e These two signals are active on edges with opposite polarity e One of the two TI FP signals is selected as trigger input and the clock trigger controller is configured in trigger reset mode Figure 65 PWM input signal measurement PWM Input Signal TIM1 ARR value g c o os A A A Time Period measurement IC2 duty cycle imd CCR1 register 2 2 measurement in Reset counter CCR2 register Procedure
326. en it cannot be disabled again except by a reset When hardware watchdog is selected by option byte the watchdog is always active and the WDGA bit is not used Controlling the downcounter This downcounter is free running It counts down even if the watchdog is disabled When the watchdog is enabled the T6 bit must be set to prevent generating an immediate reset The T 5 0 bits contain the number of increments which represents the time delay before the watchdog produces a reset see Figure 29 Approximate timeout duration The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register see Figure 30 The window register WWDG_WR contains the high limit of the window To prevent a reset the downcounter must be reloaded when its value is lower than the window register value and greater than Ox3F Figure 30 describes the window watchdog process The T6 bit can be used to generate a software reset the WDGA bit is set and the T6 bit is cleared Watchdog reset on halt option If the watchdog is activated and the watchdog reset on halt option is selected then the HALT instruction will generate a reset d DoclD14587 Rev 12 RM0016 Window watchdog WWDG 15 4 How to program the watchdog timeout The formula below can be used to calculate the WWDG timeout twwpe expressed in ms twwpa Topu 12288 x T 5 0 1 where Tcpy is the peripheral clo
327. ence begins when the slave device receives the clock signal and the first bit of the data on its MOSI pin The remaining 7 bits are loaded into the shift register The transmitter is not activated and no data is shifted out serially to the MISO pin In bidirectional mode when transmitting 1 BDOE 1 The sequence begins when the slave device receives the clock signal and the first bit of the Tx buffer is transmitted to the MISO pin The data is then parallel loaded from the Tx buffer into the 8 bit shift register during the first bit transmission and then shifted out serially to the MISO pin The software must have written the data to be sent before the SPI master device starts the transfer no data is received In bidirectional mode when receiving BDM 1 and BDOE 0 The sequence starts when the slave device receives the clock signal and the first bit of the data to its MISO pin The data received on MISO pin is shifted in serially to the 8 bit shift register and then parallel loaded into the SPI_DR register Rx Buffer The transmitter is not activated and no data is shifted out serially to the MISO pin DoclD14587 Rev 12 Ly 0016 Serial peripheral interface SPI Handling data transmission and reception The TXE flag Tx buffer empty is set when the data is transferred from the Tx buffer to the shift register It indicates that the internal Tx buffer is ready to be loaded with the next data An in
328. ensure that the four Mask ldentifier registers are in the same mode When a standard identifier is received IDE bit is zero the extended part of 32 bit or 16 bit filters is not compared To filter a group of identifiers configure the Mask Identifier registers in mask mode To select single identifiers configure the Mask Identifier registers in identifier list mode Filters not used by the application should be left deactivated Each filter within a filter bank is numbered called the Filter Number from 0 to a maximum dependent on the mode and the scale of each of the 6 filter banks For the filter configuration refer to Figure 148 through Figure 151 Figure 148 32 bit filter bank configuration FSCx bits 0b11 in CAN FCRx register Filter registers Filter mode STID 10 3 STID 2 0 EXID FMHx 2 0 FMHx 1 Identifier Mask CAN FxR5 T T Mapping Ex p 28 21 EXID 20 18 17 15 0 14 7 EXID 6 0 FMLx 0 FMLx 1 Identifier FxR1 FxR2 FxR3 FxR4 ID ID n n FxR6 FxR7 FxRB M ID 1 ID Identifier M Mask n Filter number x Filter bank number The FMHx and FMLx bits are located in the CAN FMR1 and FMR2 registers Figure 149 16 bit filter bank configuration FSCx bits 0610 in CAN FCRx register
329. ents ICP and IAP The in circuit programming ICP method is used to update the entire content of the memory using the SWIM interface to load the user application into the microcontroller ICP offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices The SWIM interface single wire interface module uses the SWIM pin to connect to the programming tool In contrast to the ICP method in application programming IAP can use any communication interface supported by the microcontroller I Os I C SPI USART to download the data to be programmed in the memory IAP allows the Flash program memory content to be reprogrammed during application execution Nevertheless part of the application must have been previously programmed in the Flash program memory using ICP Refer to the STM8S and STM8AF Flash programming manual PM0051 STM8 SWIM protocol and debug manual 0 0470 for more information on programming procedures DoclD14587 Rev 12 49 595 Flash program memory and data EEPROM 0016 Table 6 Memory access versus programming method Mode ROP Memory Area Access from core User boot code area UBC R E Readout Main program R W EO protection enabled Data EEPROM area DATA R w User IAP and bootloader Option bytes R if available User boot code area UBC R E Readout Main program R W E protection di
330. ents and set write protection or configure specific low power modes The application can also program the device option bytes 4 2 Glossary e Block A block is a set of bytes that can be programmed or erased in one single programming operation Operations that are performed at block level are faster than standard programming and erasing Refer to Table 5 for the details on block size e Page A page is a set of blocks A dedicated option byte can be used to configure by increments of one page the size of the user boot code d 34 595 DoclD14587 Rev 12 RM0016 Flash program memory and data EEPROM 4 3 d Main Flash memory features 5 85 and STM8AF EEPROM is divided into two memory areas Upto 128 Kbytes of Flash program memory The density differs according to the device Refer to Section 4 4 Memory organization for details Upto 2 Kbytes of data EEPROM including option bytes Data EEPROM density differs according to the device Refer to Section 4 4 Memory organization for details Programming modes Byte programming and automatic fast byte programming without erase operation Word programming Block programming and fast block programming mode without erase operation Interrupt generation on end of program erase operation and on illegal program operation Read while write capability RWW This feature is not available on all devices Refer to the datasheets for details In applicati
331. er 00 no prescaler capture is done each time an edge is detected on the capture input 01 Capture is done once every 2 events 10 Capture is done once every 4 events 11 Capture is done once every 8 events Note The internal event counter is not reset when IC1PSC is changed on the fly In this case the old value is used until the next capture occurs To force a new value to be taken in account immediately the CC1E bit can be cleared and set again Bits 1 0 CC1S 1 0 Capture compare 1 selection This bitfield defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is configured as input IC1 is mapped on 10 CC1 channel is configured as input IC1 is mapped on 2 1 11 Reserved Note CC1S bits are writable only when the channel is OFF CC1E 0 in TIMx_CCER1 updated d DoclD14587 Rev 12 235 595 16 bit general purpose timers TIM2 TIM5 0016 18 6 9 Note Capture compare mode register 2 TIMx CCMR2 Refer to Capture compare mode register 1 TIMx CCMH 1 on page 233 for details on using these bits Address offset 0x06 or 0x08 TIM2 0x06 0x08 5 for TIM2 address see Section Reset value 0x00 Channel configured in output 7 6 5 4 3 2 1 0 Reserved OC2M 2 0 OC2PE Reserved CC2S 1 0 r rw rw rw rw r rw Bit 7 Reserved Bits 6 4 OC2M 2 0
332. er SPI_TXCRCR Address offset 0x07Reset value 0x00 TxCRC 7 0 r Bits 7 0 TxCRC 7 0 Tx CRC register When CRC calculation is enabled the TxCRC 7 0 bits contain the computed CRC value of the subsequently transmitted bytes This register is reset when the CRCEN bit of SPI CR2 is written to 1 The CRC is calculated serially using the polynomial programmed in the SPI CRCPR register Note A read to this register when the BSY flag is set could return a incorrect value 20 5 SPI register map and reset values Table 47 SPI register map and reset values Address Register 9 7 6 5 4 3 2 1 0 offset name 0x00 SPI CR1 LSB FIRST SPE BR2 BR1 BRO MSTR CPOL CPHA Reset value 0 0 0 0 0 0 0 0 0x01 SPI CR2 BDM BDOE CRCEN CRCNEXT RXONLY SSM SSI Reset value 0 0 0 0 0 0 0 0 0x03 SPI SR BSY OVR MODF CRCERR WKUP TXE RXNE Reset value 0 0 0 0 0 0 1 0 SPI DR DR 7 0 0 04 Reset value 0 SPI CRCPR MSB LSB 0 05 reset value 0 0 0 0 0 1 1 1 0x06 SPI RXCRCR MSB LSB reset value 0 0 0 0 0 0 0 0 0x07 SPI TXCRCR MSB LSB reset value 0 0 0 0 0 0 0 0 282 595 DoclD14587 Rev 12 RM0016 Inter integrated circuit PC interface 21 21 1 21 2 2 Inter integrated circuit 2 interface Introduction 2 inter integrated circuit bus interface serves as an interface between the microcontroller and the serial 2 bus It provides multi ma
333. er 256 2 DoclD14587 Rev 12 133 595 Timer overview 0016 16 1 Timer feature comparison Table 34 Timer feature comparison Counter Capture Comple Repet External External Timer Counter Prescaler compare isl _ synchro Timer resol mentary ition trigger break type factor chan nization ution outputs counter input input 1 nels chaining TIM1 Any integer With Up down from 1 to 4 3 Yes 1 1 TIM5 65536 6 timer TIM2 genera i amp pi 3 purpose timer Any power of 2 from 1 to 32768 2 0 0 purpose timer TIM4 Any power of basic 8 bit 2 from 1 to 0 timer 128 TMS Any power of 1 general 16 bit 2 from 1 to 3 shared purpose with 32768 timer Up None No 0 Yes 6 Any power of basic 8 bit 2 from 1 to 0 0 timer 128 134 595 DoclD14587 Rev 12 Ly RM0016 Timer overview 16 2 d Glossary of timer signal names Table 35 Glossary of internal timer signals Internal signal name Description Break interrupt Related figures Figure 31 TIM1 general block diagram on CCA CC1I CC2I CCal CaPture compare page 139 interrupt Figure 35 Counter update when CK PSC Prescaler clock 0 ARR not preloaded with prescaler 2 CNT EN Counter en
334. er and ARPE 0 in the TIM1 CR 1 register optional In this case write the compare value in the register and write the auto reload value in the TIM1 ARR register Then generate an update by setting the UG bit and wait for an external trigger event on TI2 CC1P is written to 0 in this example In the example outlined above the DIR and CMS bits in the TIM1_CR1 register should be low As only one pulse is required write 1 in the OPM bit the TIM1 CR1 register to stop the counter at the next UEV when the counter rolls over from the auto reload value back to 0 Particular case OCi fast enable In one pulse mode the edge detection on the Tli input sets the CEN bit which enables the counter Then a comparison between the counter and the compare value makes the output toggle However several clock cycles are needed for these operations and this affects the the minimum delay Ay min that can be obtained To output a waveform with the minimum delay set the OC FE bits in the TIM1 CCMRi registers OC REF and are forced in response to the stimulus without taking the comparison into account The new level of OCiREF and is the same as if a compare match had occured The bits acts only if the channel is configured in PWM1 or 2 mode Complementary outputs and deadtime insertion TIM1 can output two complementary signals per channel It also manages the switching off and switching on inst
335. eration 114 12 3 2 Time base selection 115 12 3 8 LSI clock frequency measurement 116 124 AWU IGOISIGIS wile da a a aa ROS ex 117 12 4 1 Control status register 117 12 4 2 Asynchronous prescaler register APR 118 12 4 3 Timebase selection register 118 12 4 A AWU register map and reset values 119 13 Beeper BEEP wena RR ERR AN RR REOR RE ARE 120 18 1 ntrod clion 252532525544 ewe edle NU os 120 13 2 Beeper functional description 120 13 2 1 operation 120 13 2 2 Beeper calibration 121 6 462 DoclD14587 Rev 12 Ky 0016 Contents 19 3 lt 121 13 3 1 Beeper control status register CSR 121 13 3 2 Beeper register and 122 14 Independent watchdog IWDG 123 141 Introduction 123 14 2 IWDG functional description 123 14 3 IWDG egisS
336. ered Communication mode disabled 1 Time Triggered Communication mode enabled Note For more information on Time Triggered Communication mode please refer to Section 23 4 4 Time triggered communication mode Bit 6 ABOM Automatic Bus Off Management This bit controls the behavior of the CAN hardware on leaving the Bus Off state 0 The Bus Off state is exited on software request Refer to Section 23 6 5 Error management Bus Off recovery 1 The Bus Off state is exited automatically by hardware once 128 x 11 recessive bits have been monitored Note For detailed information on the Bus Off state please refer to Section 23 6 5 Error management Bit 5 AWUM Automatic wakeup Mode This bit controls the behavior of the CAN hardware when a message is received in Sleep mode 0 The sleep mode is exited on software request by clearing the SLEEP bit in the register 1 The sleep mode is exited automatically by hardware when a CAN message is detected In this case the SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR register are cleared by hardware while the WKUI bit of the CAN_MSR register is set If the CAN bus is active when the Sleep automatic wakeup request occurs it does not enter Sleep mode The AWUM and the SLEEP bits must be set simultaneously Bit 4 NART No Automatic Retransmission 0 The CAN hardware will automatically retransmit the message until it has been successfully transmitted according to
337. ernal clock 001 Encoder mode 1 Counter counts up or down on 2 2 edge depending on TI1FP1 level 010 Encoder mode 2 Counter counts up or down edge depending on 2 2 level 011 Encoder mode 3 Counter counts up or down on both TI1FP1 and TI2FP2 edges depending on the level of the other input 100 Reset mode Rising edge of the selected trigger signal TRGI re initializes the counter and generates an update of the registers 101 Trigger gated mode The counter clock is enabled when the trigger signal TRGI is high The counter stops but is not reset as soon as the trigger becomes low Both start and stop of the counter are controlled 110 Trigger standard mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 111 External clock mode 1 Rising edges of the selected trigger TRGI clock the counter Note Trigger gated mode must not be used if ED is selected as the trigger input TS 100 ED outputs 1 pulse for each transition on TI1F whereas trigger gated mode checks the level of the trigger signal 2 DoclD14587 Rev 12 189 595 16 bit advanced control timer TIM1 0016 17 7 4 External trigger register TIM1 Address offset 0 03 Reset value 0x00 7 6 5 4 3 2 1 0 ETP ECE ETPS 1 0 ETF 3 0 rw rw rw rw rw rw rw rw Bit 7 ETP External trigger polar
338. erved 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved 8K low density devices unless otherwise specified Note These bits must only be changed when they are not used e g when SMS 000 to avoid wrong edge detections at the transition Bit3 Reserved Bits 2 0 SMS 2 0 Clock trigger slave mode selection 228 595 When external signals are selected the active edge of the trigger signal TRGI is linked to the polarity selected on the external input see Input Control register and Control Register description 000 Clock trigger controller disabled if CEN 1 then the prescaler is clocked directly by the internal clock 001 010 and 011 Reserved 100 Trigger reset mode Rising edge of the selected trigger signal TRGI reinitializes the counter and generates an update of the registers 101 Gated mode The counter clock is enabled when the trigger signal TRGI is high The counter stops but is not reset as soon as the trigger becomes low Both the start and stop of the counter are controlled 110 Trigger mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 111 External clock mode 1 Rising edges of the selected trigger TRGI clock the counter 3 DoclD14587 Rev 12 RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 6 4 7 Interrupt enable register TIMx IER Address offset 0x01 or 0x03 TIM
339. es from the DR register to the SDA line via the internal shift register The master waits until the first data byte is written in the DR register see Figure 104Transfer sequencing EV8 1 When the acknowledge pulse is received e TXE bit is set by hardware and an interrupt is generated if the ITEVTEN and ITBUFEN bits are set If TXE is set and a data byte was not written in the DR register before the end of the next data transmission BTF is set and the interface waits until BTF is cleared by reading the SR1 register and then writing to the DR register stretching SCL low Closing the communication After writing the last byte to the DR register the STOP bit is set by software to generate a Stop condition see Figure 104 Transfer sequencing EV8 2 The interface goes automatically back to slave mode MSL bit cleared Note Stop condition should be programmed during EV8 2 event when either TXE or BTF is set Figure 104 Transfer sequence diagram for master transmitter 7 bit master transmitter S Address A Data1 EV5 10 bit master transmitter A Data2 DataN EV8 EV8 EV8 2 EV6 Eva 1 EV8 S EV5 Header A Address A Data A A P EV9 EV6 EV8 1 EV8 EV8 EV8 2 MS37720V1 3 1 Legend S Start S Repeated Start P Stop A Acknowledge NA Non acknowledge Event with
340. es of Flash program memory organized in up to 64 pages of 4 blocks of 128 bytes each The Flash program memory is divided into 2 areas the user boot code area UBC which size can be configured by option byte and the main program memory area The Flash program memory is mapped in the upper part of the STM8S addressing space and includes the reset and interrupt vectors Up to 1 Kbyte of data EEPROM DATA organized in up to 2 pages of 4 blocks of 128 bytes each One block 128 bytes contains the option bytes of which 13 are used to configure the device hardware features The options bytes can be programmed in user IAP and ICP SWIM modes Medium density STM8AF devices From 16 to 32 Kbytes of Flash program memory organized in up to 64 pages of 4 blocks of 128 bytes each The Flash program memory is divided into 2 areas the user boot code area UBC which size can be configured by option byte and the main program memory area The Flash program memory is mapped in the upper part of the STM8AF addressing space and includes the reset and interrupt vectors Up to 1 Kbyte of data EEPROM DATA organized in up to 2 pages of 4 blocks of 128 bytes each One block 128 bytes contains the option bytes of which 13 are used to configure the device hardware features The options bytes can be programmed in user IAP and ICP SWIM modes High density STM8S devices From 32 to 128 Kbytes of Flash program memory organized in up to 256 pages of 4 blocks of 12
341. eset Value x x x x x x x x CAN MIDR2 STID5 STID4 STID3 STID2 STID1 STIDO EXID17 EXID16 0x03 EXID23 EXID22 EXID21 EXID20 EXID19 EXID18 Reset Value x x x x x x x x CAN MIDR3 EXID15 EXIDi4 EXID13 EXID12 EXID11 EXID10 EXID9 EXID8 x Reset Value x x x x x x x x MIDR4 EXID7 EXID6 EXID5 EXID4 EXID3 EXID2 EXID1 EXIDO x Reset Value x x x x x x x x CAN MDAR1 8 MDAR7 MDAR6 MDARS5 MDAR4 MDAR3 MDAR2 MDARi MDARO 0x06 0D Reset Value x x x x x x x x Ge CAN_MTSRL TIME7 TIME6 5 4 2 TIME1 TIMEO X Reset Value x x x x x x x x MTSRH TIME15 TIME14 TIME13 TIME12 TIME11 TIME10 9 TIME8 x Reset Value x x x x x x x x DoclD14587 Rev 12 421 462 Controller area network beCAN 0016 Table 71 beCAN filter configuration page register map and reset values Address Register name 7 6 5 4 3 2 1 0 Offset 0x00 CAN_ESR 0 LEC2 LEC1 LECO 0 BOFF EPVF EWGF Reset Value 0 0 0 0 0 0 0 01 CAN EIER ERRIE 0 0 LECIE 0 BOFIE EPVIE EWGIE Reset Value 0 0 0 0 0 0x02 CAN TECR TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TECO Reset Value 0 0 0 0 0 0 0 0 0x03 CAN_RECR REC7 REC6 REC5 REC4 REC3 REC2 REC1 RECO Reset Value 0 0 0 0 0 0 0 0 0x04 CAN_BTR1 SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO Reset Value 0 q 0 0 0 0 0 0 0x05 CAN BTR2 0 BS22 BS21 BS20 BS13 BS12 BS11 BS10 Reset Value 0 1 0 0 0 1 1 0x06 Reserved X x x x X X x x 0x07
342. ess Register name 7 6 5 4 3 2 1 0 offset ADC2 CSR EOC AWD EOCIE AWDIE CH3 CH2 CH1 CHO Reset value 0 0 0 0 0 0 0 0 0x21 ADC2_CR1 SPSEL2 SPSEL1 SPSELO ADON Reset value 0 0 0 0 0 0 0 0 0x22 ADC2 CR2 EXTTRIG EXTSEL1 EXTSELO ALIGN Reset value 0 0 0 0 0 0 0 0 0x23 ADC2 CR3 DBUF OVR E Reset value 0 0 0 0 0 0 0 0 0x24 ADC2_DRH DATA9 DATA8 Reset value 0 0 0 0 0 0 0 0 0x25 ADC2 DRL DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATAO Reset value 0 0 0 0 0 0 0 0 0x26 ADC2_TDRH TD15 TD14 TD13 TD12 TD11 TD10 9 TD8 Reset value 0 0 0 0 0 0 0 0 0x27 ADC2 TDRL TD7 TD6 TD5 TD4 TD3 TD2 TD1 TDO Reset value 0 0 0 0 0 0 0 0 d DoclD14587 Rev 12 449 462 Revision history 0016 25 Revision history Table 79 Document revision history Date Revision Changes 27 May 2008 1 Initial release Updated Section 2 Memory and register map on page 27 introduced high medium and low density categories modified end address for option bytes updated RAM data EEPROM and Flash program memory densities Updated Figure 18 Reset circuit on page 73 Update min reset pulse from 300 to 500 ns in Section 8 2 Reset circuit description on page 73 Updated Table 6 Memory access versus programming method on 13 Aug 2008 2 page 50 Reorganized Section 16 on page 133 to Section 19 on page 248 Renamed USART and LINUART to UART1 UART2 and UART3 combined in new
343. et some pin configurations may be different from their reset state configuration Reset circuit description The NRST pin is both an input and an open drain output with integrated Rpy weak pull up resistor The low pulse of duration tinFpnrsT on the NRST pin generates an external reset The reset detection is asynchronous and therefore the MCU can enter reset even in Halt mode The NRST pin also acts as an open drain output for resetting external devices DoclD14587 Rev 12 73 462 Reset RST RM0016 An internal temporization maintains a pulse of duration top ygsr whatever the internal reset Source An additional internal weak pull up ensures a high level on the reset pin when the reset is not forced 8 3 Internal reset sources Each internal reset source is linked to a specific flag bit in the Reset status register RST SR except POR BOR which have no flag These flags are set respectively at reset depending on the given reset source So they are used to identify the last reset source They are cleared by software writing the logic value 1 8 3 1 Power on reset POR and brown out reset BOR During power on the POR keeps the device under reset until the supply voltages Vpp ang Vppio reach the voltage level at which the BOR starts to function At this point the BOR reset replaces the POR and the POR is automatically switched off The BOR reset is maintained till the supply voltage reaches the operating voltage r
344. etection 1 11 bit break detection LBDF LIN Break Detection Flag LIN Break Detection Flag Status flag This bit is set by hardware and cleared by software writing 0 0 LIN Break not detected 1 LIN Break detected An interrupt is generated when LBDF 1 if LBDIEN 1 ADD 3 0 Address of the UART node This bitfield gives the address of the UART node This is used in multi processor communication during mute mode for wakeup with address mark detection DoclD14587 Rev 12 365 462 Universal asynchronous receiver transmitter UART RM0016 22 7 9 Control register 5 5 Address offset 0x08 Reset value 0x00 0 Reserved SCEN NACK HDSEL IRLP IREN Reserved r r r rw rw rw r Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 366 462 Reserved must be kept cleared SCEN Smartcard mode enable This bit is used for enabling Smartcard mode 0 Smartcard Mode disabled 1 Smartcard Mode enabled Note This bit is not available for UARTS NACK Smartcard NACK enable 0 NACK transmission in case of parity error is disabled 1 NACK transmission during parity error is enabled Note This bit is not available for UARTS HDSEL Half Duplex Selection Selection of Single wire Half duplex mode 0 Half duplex mode is not selected 1 Half duplex mode is selected Note This bit is not available for UART2 and UARTS IRLP IrDA Low Power This bit is used
345. etting the UG bit in the TIM1_EGR register by software or by using the clock trigger mode controller also generates an update event In this case the counter and the prescaler restart counting from 0 The UEV can be disabled by software by setting the UDIS bit in the TIM1_CR1 register This is to avoid updating the shadow registers while writing new values in the preload registers In this way no update event occurs until the UDIS bit is written to 0 However the counter continues counting up and down based on the current auto reload value In timers with a repetition counter the new update rate is used because the repetition register is not double buffered For this reason care must be taken when changing the update rate In addition if the URS bit in the TIM1 CR1 register is set setting the UG bit generates a UEV without setting the UIF flag Consequently no interrupt request is sent This avoids generating both update and capture interrupts when clearing the counter on the capture event When an update event occurs all registers are updated and the update flag the UIF bit in the TIM1 SR1 register is set depending on the URS bit e The buffer of the prescaler is reloaded with the preload value content of the TIM1 PSCR register e auto reload shadow register is updated with the preload value content of the TIM1 ARR register Note that if the update source is a counter overflow the auto reload is updated before the coun
346. etwork beCAN changed the default reset value for CAN MSR Section 6 Interrupt controller ITC replaced IRS CC with ISR CC in the footnote of Table 9 Interrupt enabling disabling inside an ISR Section 11 General purpose I O ports GPIO removed the 19 Jun 2014 10 footnote 1 in Table 21 port configuration summary Section 24 Analog digital converter ADC replaced the first sentence in Section 24 5 6 Analog watchdog and replaced AWDENXx with AWENx in the heading of Table 74 Section 21 Inter integrated circuit I2C interface added the section SCL master clock generation and updated Section 21 4 2 2 master mode Section 21 7 3 Frequency register FREQR and Section 21 7 13 TRISE register I2C TRISER Section 24 5 3 Channel selection corrected a typo on ACD CSR Updated Section 11 7 4 Schmitt trigger Updated the document title and the ntroduction on the cover page the very first sentence in Section 17 4 6 Synchronization between TIM1 TIM5 and 6 timers TS 2 0 bit definitions in Section 17 7 3 Slave mode control register TIM1 5 TS 2 0 bit definitions in Section 18 6 3 Slave mode control 23 Mar 2015 11 register TIM5_SMCR TS 2 0 bit definitions in Section 19 6 3 Slave mode control register 6 SMCHR Section 17 4 6 Synchronization between TIM1 TIM5 and 6 timers replaced TS 001 in the TIMx SMCR register
347. ety of purposes including e base generation e Measuring the pulse lengths of input signals input capture e Generating output waveforms output compare PWM and One pulse mode e Interrupt capability on various events capture compare overflow e Synchronization with other timers or external signals external clock reset trigger and enable in devices with TIM5 The timer clock can be sourced from internal clocks Only the main features of the general purpose timers are given in this chapter Refer to the corresponding paragraphs of Section 17 16 bit advanced control timer TIM1 on page 137 for more details on each feature 2 main features TIM2 TIMS features include e 16 bit up counting auto reload counter e 4 bit programmable prescaler allowing the counter clock frequency to be divided the fly by any power of 2 from 1 to 32768 e 3independent channels for Input capture Output compare PWM generation edge aligned mode e interrupt request generation on the following events Update counter overflow counter initialization by software Input capture Output compare DoclD14587 Rev 12 219 595 16 bit general purpose timers TIM2 TIM3 TIM5 RM0016 18 3 TIM5 main features TIM5 features include 18 4 16 bit up counting auto reload counter 4 bit programmable prescaler allowing the counter clock frequency to be divided the fly by
348. eviations In the register descriptions of each chapter in this reference manual the following abbreviations are used Table 4 List of abbreviations Abbreviation read write rw Description Software can read and write to these bits read only r Software can only read these bits write only w Software can only write to this bit Reading the bit returns a meaningless value read write once rwo Software can only write once to this bit but can read it at any time Only a reset can return this bit to its reset value read clear w1 Software can read and clear this bit by writing 1 Writing 0 has no effect on the bit value read clear rc w0 Software can read and clear this bit by writing 0 Writing 1 has no effect on the bit value read set rs Software can read and set this bit Writing 0 has no effect on the bit value read clear by read rc r Software can read this bit Reading this bit automatically clears it to 0 Writing 0 has no effect on the bit value Reserved Res Reserved bit must be kept at reset value DoclD14587 Rev 12 33 595 Flash program memory and data EEPROM 0016 4 Flash program memory and data EEPROM 4 1 Introduction The embedded Flash program memory and data EEPROM memories are controlled by a common set of registers Using these registers the application can program or erase memory cont
349. f Flash memory The performance line high density STM8S devices are the STM8S207xx and STM8S208xx microcontrollers with 32 to 128 Kbytes of Flash memory Refer to the product datasheet for ordering information pin description mechanical and electrical device characteristics and for the complete list of available peripherals Reference documents September 2015 For information on programming erasing and protection of the internal Flash memory please refer to the STM8S and STM8AF Flash programming manual 0051 and to the STM8 SWIM communication protocol and debug module user manual UM0470 For information on the STM8 core refer to STM8 CPU programming manual 0044 The bootloader user manual 0 0560 describes the usage of the integrated ROM bootloader DoclD14587 Rev 12 1 462 www st com Contents 0016 Contents 1 Central processing unit 23 1 1 Introduction 23 1 2 GPL TEGISIOlS i o Re eR OR ne Rl C CR CR RR ca 23 1 2 1 Description of CPU registers 23 1 2 2 STM8 CPU register map 27 1 3 Global configuration register CFG 27 1 3 1 Activation 27 1 3 2 SWIM 27 1 3 3 Description of global configuration regi
350. ffset 0x03 or 0x05 TIM2 0x03 TIM3 0x05 TIM5 for TIM2 address see Section Reset value 0x00 6 5 4 3 2 1 0 Reserved CC30F 2 CC1OF Reserved r rc wO rc wO rc wO r Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 3 Reserved Capture compare 3 overcapture flag Refer to CC1OF description CC20OF Capture compare 2 overcapture flag Refer to CC1OF description Capture compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode It is cleared by software by writing it to O 0 No overcapture has been detected 1 The counter value has been captured in TIMx CCR1 register while CC1IF flag was already set Reserved forced by hardware to 0 DoclD14587 Rev 12 231 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 18 6 7 Event generation register TIMx EGR Address offset 0x04 or 0x06 TIM2 0x04 TIM3 0x06 TIM5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 Reserved TG Reserved CC3G CC2G CC1G UG r Ww r w Ww Bit 7 Reserved Bit 6 TG Trigger generation This bit is set by software to generate an event It is automatically cleared by hardware 0 No action 1 The TIF flag is set in 5 SR1 register An interrupt is generated if enabled by the TIE bit Note TIMZ TIMG this bit is reserved Bits 5 4 Reserved Bit 3 CC3G Captu
351. followed by a read of the UART_DR register 2 348 462 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART Note d LHE is set if one of the following conditions occurs e Break Delimiter is too short e Synch Field is different from 55h e Framing error in Synch Field or Identifier Field e ALIN header reception time out If a LIN header error occurs the LSF bit in the UART_CR6 register must be cleared by software LIN header time out error The UART automatically monitors the THEADER_MAX condition given by the LIN protocol If the entire Header up to and including the STOP bit of the LIN Identifier Field is not received within the maximum time limit of 57 bit times then a LIN Header Error is signaled and the LHE bit is set in the UART_SR register Figure 134 LIN header reception time out LIN Synch LIN Synch Identifier Break Field Field THEADER The time out counter is enabled at each break detection It is stopped in the following conditions e ALIN Identifier Field has been received e An LHE error occurred other than a time out error e A software reset of LSF bit transition from high to low occurred during the analysis of the LIN Synch Field If LHE bit is set due to this error during the LIN Synch Field if LASE bit 1 then the UART goes into a blocked state
352. ftware slave management enabled When the SSM bit is set the NSS pin input is replaced with the value coming from the SSI bit SSI Internal slave select This bit has effect only when SSM bit is set The value of this bit is forced onto the NSS pin and the I O value of the NSS pin is ignored 0 Slave mode 1 Master mode 3 DoclD14587 Rev 12 RM0016 Serial peripheral interface SPI 20 4 3 SPI interrupt control register SPI_ICR Address offset 0x02 Reset value 0x00 7 6 5 4 3 2 1 0 RXIE ERRIE WKIE Reserved rw rw rw rw r Bit 7 TXIE Tx buffer empty interrupt enable 0 TXE interrupt masked 1 TXE interrupt not masked This allows an interrupt request to be generated when the TXE flag is set Bit6 RXIE RX buffer not empty interrupt enable 0 RXNE interrupt masked 1 RXNE interrupt not masked This allows an interrupt request to be generated when the RXNE flag is set Bit 5 ERRIE Error interrupt enable 0 Error interrupt is masked 1 Error interrupt is enabled This allows an interrupt request to be generated when an error condition occurs CRCERR OVR MODF Bit 4 WKIE Wakeup interrupt enable 0 Wakeup interrupt masked 1 Wakeup interrupt enabled This allows an interrupt request to be generated when the WKUP flag is set Bits 3 0 Reserved 3 DoclD14587 Rev 12 279 595 Serial peripheral interface SPI RM0016 20 4 4 SPI status register SPI_SR Address offset
353. ger Synchronization with TIM5 TIM6 timers or external signals external clock reset trigger and enable This timer is ideally suited for a wide range of control applications including those requiring center aligned PWM capability with complementary outputs and deadtime insertion The timer clock can be sourced from internal clocks or from an external source selectable through a configuration register DoclD14587 Rev 12 137 595 16 bit advanced control timer TIM1 0016 17 2 138 595 TIM1 main features TIM1 features include 16 bit up down up down counter auto reload counter Repetition counter to update the timer registers only after a given number of cycles of the counter 16 bit programmable prescaler allowing the counter clock frequency to be divided the fly by any factor between 1 and 65536 Synchronization circuit to control the timer with external signals and to interconnect several timers timer interconnection not implemented in some devices 4 independent channels that can alternately be configured as Input capture Output compare PWM generation edge and center aligned mode 6 step PWM generation mode output Complementary outputs on three channels with programmable deadtime insertion Break input to put the timer output signals in reset state or in a known state External trigger input pin ETR Interrupt generation on the following event
354. ggered by an rising edge event on the ADC_ETR pin or a TRGO event from a timer Refer to the datasheet for details on the timer trigger as this is product depend ent If the EXTTRIG control bit is set then either of the external events can be used to trigger a conversion The EXTSEL 1 0 bits are used to select the two possible sources of events that can trigger conversion To use external trigger mode 1 The ADC is in off state ADON 0 and EOC bit is cleared 2 Select trigger source EXTSEL 1 0 3 Set external trigger mode EXTTRIG 1 using a BSET instruction in order not to change other bits in the register 4 Ifthe trigger source is in high state this switches on the ADC For this reason test if ADC is switched off ADON 0 then switch on ADC ADON 1 5 Wait for the stabilization time If an external trigger occurs before elapses the result will not be accurate 6 Conversion starts when an external trigger event occurs If timer trigger mode is selected timer event as trigger source not external pin it is recommended to start the timer only when the ADC is completely set and stop the timer before the ADC is switched off External trigger mode must be disabled EXTTRIG 0 before executing a HALT instruction Analog zooming Analog zooming is supported in devices with external reference voltage pins Vngr In analog zooming the reference voltage is chosen to allow increased
355. gram continues after the WFI instruction 1 Interrupt only activation level An IRET instruction causes the CPU to go back to WFI Halt mode without restoring the context SWD SWIM disable 0 SWIM mode enabled 1 SWIM mode disabled When SWIM mode is enabled the SWIM pin cannot be used as general purpose I O 1 3 4 Global configuration register map and reset values The CFG_GCR is mapped the STM8 address space Refer to the corresponding datasheets for the base address Table 3 CFG_GCR register map Address Register name 7 6 5 4 3 2 1 0 offset 0x00 CFG_GCR AL SWD Reset value 0 0 0 0 0 0 0 0 28 595 DoclD14587 Rev 12 0016 Boot ROM 2 Boot ROM The internal 2 Kbyte boot ROM available in some devices contains the bootloader code Its main tasks are to download the application program to the internal Flash EEPROM through the SPI CAN or UART interface and to program the code data option bytes and interrupt vectors in internal Flash EEPROM To perform bootlloading in LIN mode a different bootloader communication protocol is implemented UART2 UART3 and UART1 The boot loader starts executing after reset Refer to the STM8 bootloader user manual 0 0560 for more details DoclD14587 Rev 12 29 595 2 Memory and register map 0016 3 3 1 3 1 1 30 595 Memory and register map For details on the memory map port
356. h 110 PWM mode 1 In up counting channel 1 is active as long as lt TIM1 1 otherwise the channel is inactive In down counting channel 1 is inactive OC1REF 0 as long as TIM1 gt TIM1 CCR1 otherwise the channel is active OC1REF 1 111 PWM mode 2 In up counting channel 1 is inactive as long as CNT lt TIM1 CCR1 otherwise the channel is active In down counting channel 1 is active as long as TIM1 CNT TIM1 CCR1 otherwise the channel is inactive Note These bits can no longer be modified while LOCK level 3 has been programmed LOCK bits in TIM1 register and CC1S 00 the channel is configured in output PWM mode 1 or 2 the OCiREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode refer to PWM mode on page 172 for more details On channels that have a complementary output this bitfield is preloaded If the CCPC bit is set in the TIM1_CR2 register the OCM active bits take the new value from the preload bits only when a COM is generated DoclD14587 Rev 12 197 595 16 bit advanced control timer TIM1 0016 Bit 3 OC1PE Output compare 1 preload enable 0 Preload register on TIM1 CCR 1 disabled TIM1 CCR 1 can be written at anytime The new value is taken into account immediately 1 Preload register on TIM1 CCR1 enabled Read write operations access the preload
357. hardware register map and CPU SWIM debug module interrupt controller registers refer to the product datasheets Memory layout Memory map Figure 3 Memory map 00 000h RAM RAM upper limit Data EEPROM lower limit Reserved Data EEPROM Data EEPROM upper limit 00 4800h Option bytes Option bytes upper limit 00 5000h HW registers HW registers upper limit LL Stac Reserved 00 6800h 00 7FOOh Registers for CPU SWIM ITC DM 00 8000h 00 8080h Interrupt vectors 00 6000h opti Program EEPROM Program memory upper limit 3118468 The RAM upper limit data EEPROM upper and lower limit Option Byte upper limit hardware HW registers upper limit and the program memory upper limit are specific to the device configuration Please refer to the datasheets for quantitative information DoclD14587 Rev 12 Ly RM0016 Memory and register map 3 1 2 d Stack handling Default stack model The stack of the STM8S and STM8AF microcontrollers is implemented in the user RAM area The default stack model is shown in Figure 4 Figure 4 Default stack model RAM Start address Stack roll over limit End address Stack pointer initialization value Default stack model ai15055 1 The stack roll over limit is not implemented on all devices Refer to the datasheets for detailed information Stack pointer initialization value This is the default value of the stack
358. has a faster startup time than the HSE crystal oscillator however even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator The HSIRDY flag in the nternal clock register CLK_ICKR indicates if the HSI RC is stable or not At startup the HSI RC output clock is not released until this bit is set by hardware The HSI RC can be switched on and off using the HSIEN bit in the nternal clock register CLK ICKR Backup source The HSI 8 signal can also be used as a backup source Auxiliary clock if the HSE crystal oscillator fails Refer to Section 9 6 Clock security system CSS 2 DoclD14587 Rev 12 0016 Clock control CLK Fast wakeup feature If the FHWU bit in the nternal clock register CLK ICKH is set this automatically selects the HSI clock as master clock after MCU wakeup from Halt or Active halt see Low power chapter Calibration Each device is factory calibrated by ST After reset the factory calibration value is automatically loaded in an internal calibration register If the application is subject to voltage or temperature variations this may affect the RC oscillator speed You can trim the HSI frequency in the application using the HS clock calibration trimming register CLK HSITRIMR In this register there are 3 or 4 bits providing an additional trimming value that is added to the intern
359. he FE bit is set by hardware e invalid data is transferred from the Shift register to the UART DR register e interrupt is generated in case of single byte communication However this bit rises at the same time as the RXNE bit which itself generates an interrupt The FE bit is reset by a UART SR register read operation followed by a UART DR register read operation Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 3 it can be either 1 or 2 in normal mode 1 in IrDA mode and 1 5 in Smartcard mode 1 1 Stop Bit Sampling for 1 stop Bit is done on the 8th 9th and 10th samples 2 1 5 Stop Bits Smartcard mode only Sampling for 1 5 stop bits is done on the 16th 17th and 18th samples An NACK signal received from the Smartcard forces the data signal low during the sampling flagged as a framing error Then the FE flag is set with the RXNE at the end of the 1 5 stop bit 3 2 Stop Bits Sampling for 2 stop bits is done on the 8th 9th and 10th samples of the first stop bit If a framing error is detected during the first stop bit the framing error flag will be set The second stop bit is not checked for framing error The RXNE flag will be set at the end of the first stop bit DoclD14587 Rev 12 Ly RM0016 Universal asynchronous receiver transmitter UART 22 3 4 Note Note d High precision baud rate gener
360. he clock trigger controller or as the capture command The signal is prescaled before entering the capture register IC PS Figure 64 Input stage of TIM 1 channel 1 rising TH MASTER filter down counter THE Edge detector TI1F_falling TIMx CCMR1 CCER1 2 rising from channel 2 TI2F falling from channel 2 THMF ED to clock trigger controller divider 1 1 2 4 8 from clock trigg controller CC1S 1 0 ICPS 1 0 CCIE ICPS TIMx_CCMR1 TIMx_CCER1 DoclD14587 Rev 12 d 0016 16 bit advanced control timer TIM1 17 5 3 Input capture mode In input capture mode the capture compare registers TIM1 CCRi are used to latch the value of the counter after a transition detected on the corresponding IC signal When a capture occurs the corresponding CC IF flag TIM1 SR1 register is set An interrupt can be sent if it is enabled by setting the bits in the TIM1 IER register If a capture occurs while the flag is already high the over capture flag CCiOF TIM1 SR2 register is set can be cleared by software by writing it to 0 or by reading the captured data stored in the registers CC OF is cleared by writing it to 0 Procedure The following procedure shows how to capture the counter value in
361. he device to exit from Wait mode UART registers are frozen Halt 5 In Halt mode the UART stops transmitting receiving until Halt mode is exited 22 6 UART interrupts Table 60 UART interrupt requests Event Enable Exit Exit Interrupt event flag control from from bit Wait Halt Transmit data register empty TXE TIEN Yes No Transmission complete TC TCIEN Yes No Received data ready to be read RXNE Yes No Overrun error detected LIN header error OR LHE ind Yes No Idle line detected IDLE ILIEN Yes No Parity error PE PIEN Yes No Break flag LBDF LBDIEN Yes No Header Flag LHDF LHDIEN Yes No Note 1 The UART interrupt events are connected to two interrupt vectors see Figure 139 a Transmission Complete or Transmit Data Register empty interrupt b Idle Line detection Overrun error Receive Data register full Parity error interrupt and Noise Flag 2 These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset RIM instruction 3 356 462 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Figure 139 UART interrupt mapping diagram TC J TCIEN TXE gt Transmitter Interrupt TIEN d gt IDLE ILIEN RIEN N OR LHE RIEN N D Receiver Interrupt PE PIEN LBDF
362. he following procedure to clear the up counter in response to rising edge on TI1 input 1 Configure channel 1 to detect rising edges on TI As no filter is required in this example configure an input filter duration of 0 IC2F 0000 The capture prescaler is not used for triggering and does not need to be configured The 15 bits select the input capture source and do not need to be configured either Write CC1P 0 in TIM1 register to validate the polarity and detect rising edges 2 Configure the timer in reset mode by writing SMS 100 in TIM1 SMCR register Select TI1 as the input source by writing TS 101 in the TIM1 register 3 Start the counter by writing CEN 1 in the TIM1 1 register The counter starts counting on the internal clock and behaves normally until the TI1 rising edge When TI1 rises the counter is cleared and restarts from 0 In the meantime the trigger flag is set TIF bit in the TIM1 SR1 register and an interrupt request can be sent if enabled depending on the TIE in the TIM1 IER register Figure 50 shows this behavior when the auto reload register TIM1 ARR 36h The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on 1 input Figure 50 Control circuit in trigger reset mode UG COUNTER CLOCK CK_CNT CK_PSC
363. he interrupt x is executed the device operates as follows if the interrupt x is still pending new interrupt or flag not cleared and the new software priority is higher than the previous one then the interrupt x is re entered Otherwise the software priority remains unchanged till the next interrupt request after the IRET of the interrupt x During the execution of an interrupt routine the HALT POPCC RIM SIM and WFI instructions change the current software priority till the next IRET instruction or one of the previously mentioned instructions is issued See Section 6 7 for the list of dedicated interrupt instructions Figure 16 shows an example of nested interrupt management mode Warning A stack overflow may occur without notifying the software of the failure Table 10 Vector address map versus software priority bits Vector address ITC SPRx bits 0x00 8008h I1 and IO 0 bits 0x00 800Ch I1 1 10 1 bits 0x00 807Ch 1 29 and IO 29 bits 1 SPRx register bits corresponding to the TLI be read and written However they are not significant in the interrupt process management d DoclD14587 Rev 12 0016 Interrupt controller ITC Figure 16 Nested interrupt management n lt SOFTWARE PRIORITY n i tte ted LEVEL 4 sd E des 1108 gt 0 3 1
364. he main program memory and the DATA area can be programmed at byte level To program one byte the application writes directly to the target address e nthe main program memory The application stops for the duration of the byte program operation e In DATA area Devices with RWW capability Program execution does not stop and the byte program operation is performed using the read while write RWW capability in IAP mode Devices without RWW capability The application stops for the duration of the byte program operation To erase a byte simply write 0 00 at the corresponding address The application can read the FLASH IAPSR register to verify that the programming or erasing operation has been correctly executed e EOP flag is set after a successful programming operation e WR PG DIS is set when the software has tried to write to a protected page In this case the write procedure is not performed As soon as one of these flags are set a Flash interrupt is generated if it has been previously enabled by setting the IE bit of the FLASH CR 1 register d DoclD14587 Rev 12 RM0016 Flash program memory and data EEPROM Note 4 6 3 4 6 4 2 Automatic fast byte programming The programming duration can vary according to the initial content of the target address If the word 4 bytes containing the byte to be programmed is not empty the whole word is automatically erased before the program operation On the contrar
365. he memory again by resetting the DUL bit in the FLASH IAPSR register If incorrect keys are provided another key program sequence can be performed without resetting the device When ROP is removed the whole memory is erased including the option bytes 2 RM0016 Flash program memory and data EEPROM 4 8 Flash registers 4 8 1 Flash control register 1 FLASH_CR1 Address offset 0x00 Reset value 0x00 Reserved HALT AHALT FIX r Bits 7 4 Reserved Bit 3 HALT Power down in Halt mode This bit is set and cleared by software 0 Flash in power down mode when MCU is in Halt mode 1 Flash in operating mode when MCU is in Halt mode Bit 2 AHALT Power down in Active halt mode This bit is set and cleared by software 0 Flash in operating mode when MCU is in Active halt mode 1 Flash in power down when MCU is in Active halt mode Bit 1 IE Flash Interrupt enable This bit is set and cleared by software 0 Interrupt disabled 1 Interrupt enabled An interrupt is generated if the EOP or WR PG DIS flag in the FLASH IAPSR register is set Bit 0 FIX Fixed Byte programming time This bit is set and cleared by software 0 Standard programming time of 1 2 torog if the memory is already erased and t otherwise 1 Programming time fixed at t d prog DoclD14587 Rev 12 prog 51 595 Flash program memory and data EEPROM 0016 4 8 2 Flash control register 2 FLASH CR
366. he reference rising edge e The output signal is the opposite of the reference signal except for the rising edge which is delayed relative to the reference falling edge If the delay is greater than the width of the active output OC or OCi the corresponding pulse is not generated Figure 73 Figure 74 and Figure 75 show the relationships between the output signals of the deadtime generator and the reference signal REF where CCi P 0 CCiNP 0 1 CCi E 1 and CCi NE 1 in these examples Figure 73 Complementary output with deadtime insertion OCiREF OCi pis delay c delay Figure 74 Deadtime waveforms with a delay greater than the negative pulse OCiREF OCi lt delay Figure 75 Deadtime waveforms with a delay greater than the positive pulse OCiREF delay The deadtime delay is the same for each of the channels and is programmable with the DTG bits in the DTR register Refer to Section 17 7 31 Deadtime register DTHR on page 215 for delay calculation DoclD14587 Rev 12 177 595 16 bit advanced control timer 0016 Note 178 595 Re directing OC REF to OCi or OCiN In output mode forced output compare or PWM OC REF can be re directed to the OC or outputs by configuring the CC E and
367. he software sets this bit to activate Filter 4 To modify the Filter 4 registers CAN the FACTA bit must be cleared 0 Filter 4 is not active 1 Filter 4 is active DoclD14587 Rev 12 417 462 Controller area network beCAN 0016 CAN filter bank i register x FiRx i 0 5 x 1 8 Address offset See Figure 158 Reset value 0 FB 7 0 Bits 7 0 FB 7 0 Filter bits Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier 0 Dominant bit is expected 1 Recessive bit is expected Mask Each bit of the register specifies whether the bit of the associated identifier register must match with the corresponding bit of the expected identifier or not 0 Don t care the bit is not used for the comparison 1 Must match the bit of the incoming identifier must have the same level has specified in the corresponding identifier register of the filter Note Each filter i is composed of 8 registers CAN FiR1 8 Depending on the scale and mode configuration of the filter the function of each register can differ For the filter mapping functions description and mask registers association refer to Section Figure 23 6 3 Identifier filtering A Mask ldentifier register in mask mode has the same bit mapping as in identifier list mode Note To modify these registers the corresponding FACT bit in the CAN FCRx register
368. he update event is selected as trigger output TRGO 011 Reserved 100 Reserved 101 Reserved 111 Reserved Bits 3 0 Reserved must be kept cleared 19 6 3 Slave mode control register TIM6_SMCR Address offset 0x02 Reset value 0x00 7 6 5 4 3 2 1 0 MSM TS 2 0 Reserved SMS 2 0 Note This register is not available in TIM4 d DoclD14587 Rev 12 251 595 8 bit basic timer TIM4 TIM6 RM0016 Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between timers through TRGO Bits 6 4 TS 2 0 Trigger selection This bit field selects the trigger input to be used to synchronize the counter 000 Reserved 001 Internal trigger ITR1 connected to TIM1 TRGO 010 Reserved 011 Internal trigger ITR3 connected to TIM5 TRGO 100 Reserved 101 Reserved 110 Reserved 111 Reserved 8K low density devices unless otherwise specified Note These bits must only be changed when they are not used e g when SMS 000 to avoid wrong edge detections at the transition Bit 3 Reserved Bits 2 0 SMS 2 0 Clock trigger slave mode selection 252 595 When external signals are selected the active edge of the trigger signal TRGI is linked to the polarity selected on the external input see Input control register and control register description 000 Clock trigger controller disabled If CEN 1 the prescaler is clo
369. hed on In this case the LSI clock is forced to run 3 Including communication peripheral interrupts Ly DoclD14587 Rev 12 101 462 Power management 0016 10 2 1 10 2 2 10 2 3 102 462 Wait mode Wait mode is entered from Run mode by executing a WFI wait for interrupt instruction this stops the CPU but allows the other peripherals and interrupt controller to continue to run Therefore the consumption decreases accordingly Wait mode can be combined with PCG peripheral clock gating reduced CPU clock frequency and low mode clock source selection LSI HSI to further reduce the power consumption of the device Refer to the Clock control CLK description In Wait mode all the registers and RAM contents are preserved the previously defined clock configuration remains unchanged Clock master status register CLK_CMSR When an internal or external interrupt request occurs the CPU wakes up from Wait mode and resumes processing Halt mode In this mode the master clock is stopped This means that the CPU and all the peripherals clocked by Or by derived clocks are disabled As a result none of the peripherals are clocked and the digital part of the MCU consumes almost no power In Halt mode all the registers and RAM contents are preserved by default the clock configuration remains unchanged Clock master status register CMSR The MCU enters Halt mode when a HALT instruction is executed
370. hese bits are set by hardware and cleared by software In buffered continuous mode DBUF 1 1 AWS flags behave as described in Table 75 n scan mode 5 1 AWS flags behave as described in Table 76 0 No analog watchdog event in data buffer register x 1 Analog watchdog event occurred in data buffer register x 2 446 462 DoclD14587 Rev 12 0016 Analog digital converter ADC 24 11 17 ADC watchdog control register high ADC_AWCRH Address offset 0 2 Reset value 0x00 7 6 5 4 3 2 Reserved AWEN 9 8 r Note This register is not available for ADC2 Bits 7 2 Reserved must be kept cleared Bits 1 0 AWEN 9 8 Analog watchdog enable bits 9 8 These bits are set and cleared by software In buffered continuous mode DBUF 1 CONT 1 and in scan mode SCAN 1 the AWENx bits enable the analog watchdog function for each of the 10 data buffer registers 0 Analog watchdog disabled in data buffer register x 1 Analog watchdog enabled in data buffer register x 24 11 18 ADC watchdog control register low ADC AWCRL Address offset 0x2F Reset value 0x00 7 6 5 4 3 2 0 AWEN 7 0 rw rw rw rw rw rw rw Note This register is not available for ADC2 Bits 7 0 AWEN 7 0 Analog watchdog enable bits 7 0 These bits are set and cleared by software In buffered continuous mode DBUF 1 CONT 1 and in scan mode SCAN 1 the AWENXx bits enable the anal
371. hine and the break flag is shown in Figure 130 Break detection in LIN mode 11 bit break length LBDL bit is set on page 345 The LBDF flag is used in master mode in slave mode the LHDF flag is used instead Examples of break frames are given on Figure 131 Break detection in LIN mode vs framing error detection on page 346 2 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Figure 130 Break detection in LIN mode 11 bit break length LBDL bit is set Case 1 break signal not long enough gt break discarded LBDF is not set RX line Short Break Frame Capture Strobe Lb oL Break State machine Bito Bit Bits Bits Idle Read Samples 0 0 0 0 0 0 0 0 0 0 1 delimiter Case 2 break signal just long enough gt break detected LBDF is set RX line Break Frame Capture Strobe delimiter is immediate 1 Break State machine idle Bito Bit Bita Bits Bite Bits Bito B10 Idle Read Samples 0 0 0 0 0 0 0 0 0 0 0 LBDF Case 3 break signal long enough gt break detected LBDF is set RX line Break Frame Capture Strobe Break State machine Idle Bito Bit Bit2 Bits Bite
372. ial data format UART mode The 5 8 UARTs offer a very wide range of baud rates and can also be used for multi processor communication They also support LIN Local Interconnection Network protocol version 1 3 2 0 2 1 2 2 and J2602 UART1 UART2 and UARTA have extended features see Table 52 e LIN slave mode is supported in UART2 UART3 and UART4 e Synchronous one way communication Smartcard Protocol and IrDA Infrared Data Association SIR ENDEC specifications are supported in UART1 UART2 and UARTA e Half duplex single wire communication is supported in UART1 and UARTA Refer to the datasheet for information on the availability of the UART configurations UART1 UART2 UARTS or UARTA in each microcontroller type Table 52 UART configurations Feature UART1 UART2 UART3 UART4 Asynchronous mode X X X X Multiprocessor communication X X X X Synchronous communication X X NA X Smartcard mode X X NA X IrDA mode X X NA X Single wire Half duplex mode X NA NA X LIN master mode X X X LIN slave mode NA X 1 supported not applicable Ky DoclD14587 Rev 12 315 462 Universal asynchronous receiver transmitter UART 0016 22 2 316 462 UART main features Full duplex asynchronous communications NRZ standard format Mark Space High precision baud rate generator system Common programmable transmit and receive baud rates up to fMASTER 16 Programmable data wo
373. ically see Figure 33 This buffered value remains unchanged until the 16 bit read sequence is completed Do not use the LDW instruction to read the 16 bit counter It reads the LS byte first and returns an incorrect result Figure 33 16 bit read sequence for the counter TIM1 CNTR Beginning of the sequence Read LS byte At 10 MS byte is buffered Y Other instructions Read gt Returns the buffered At t0 Dt LS byte LS byte value at t0 Sequence completed Write sequence for 16 bit TIM1 ARR register 16 bit values are loaded in the TIM1 ARR register through preload registers This must be performed by two write instructions one for each byte The MS byte must be written first The shadow register update is blocked as soon as the MS byte has been written and stays blocked until the LS byte has been written Do not use the LDW instruction as this writes the LS byte first which produces incorrect results Prescaler The prescaler implementation is as follows The TIM1 prescaler is based on a 16 bit counter controlled through a 16 bit register in TIM1 PSCR register It can be changed on the fly as this control register is buffered It can divide the counter clock frequency by any factor between 1 and 65536 The counter clock frequency is calculated as follows Psc PSCR 15 0 1 The prescaler value is loaded through a preload register The shadow registe
374. igured as input CC1S bits in TIM1 CCMH 1 register The value of CCR1 is the counter value transferred by the last input capture 1 event IC1 In this case these bits are read only Reset value 0x00 CCR1 7 0 Bits 7 0 CCR1 7 0 Capture compare 1 value LSB 2 DoclD14587 Rev 12 209 595 16 bit advanced control timer TIM1 0016 17 7 24 register 2 high TIM1 CCR2H Address offset 0x17 Reset value 0x00 CCR2 15 8 Bits 7 0 CCR2 15 8 Capture compare 2 value MSB If the CC2 channel is configured as output CC2S bits TIM1 2 register The value of CCR2 is loaded permanently into the actual capture compare 2 register if the preload feature is not enabled OC2PE bit in TIM1 CCMR2 Otherwise the preload value is copied in the active capture compare 2 register when a UEV occurs The active capture compare register contains the value which is compared to the counter register TIM1 and signalled on the OC2 output If the CC2 channel is configured as input CC2S bits in TIM1_CCMR2 register The value of CCR2 is the counter value transferred by the last input capture 2 event IC2 In this case these bits are read only 17 7 25 register 2 low TIM1 CCR2L Address offset 0x18 Reset value 0x00 CCR2 7 0 Bits 7 0 CCR2 7 0 Capt
375. ile is in Initialization mode Once a test mode has been selected the INRQ bit in the CAN MCR register must be reset to enter Normal mode Silent mode The beCAN can be put in Silent mode by setting the SILM bit in the DGR register In Silent mode the beCAN is able to receive valid data frames and valid remote frames but it sends only recessive bits on the CAN bus and it cannot start a transmission If the has to send a dominant bit ACK bit overload flag active error flag the bit is rerouted internally so that the CAN Core monitors this dominant bit although the CAN bus may remain in recessive state Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits Acknowledge Bits Error Frames Figure 143 beCAN in silent mode beCAN Tx Rx 1 k 1 Loop back mode beCAN can be set in Loop Back Mode by setting the LBKM bit in the DGR register In Loop Back Mode the beCAN treats its own transmitted messages as received messages and stores them if they pass acceptance filtering in the FIFO Figure 144 beCAN in loop back mode beCAN Tx Rx d CANTX CANRX This mode is provided for self test functions To be independent of external events the CAN Core ignores acknowledge errors no dominant bit sampl
376. ility DATA block operations can be executed from the main program memory However the data loading phase see below has to be executed from RAM Devices without RWW capability Block program operations must be executed totally from RAM There are three possible block operations e Block programming also called standard block programming The block is automatically erased before being programmed e Fast block programming No previous erase operation is performed e Block erase During block programming interrupts are masked by hardware Standard block programming A standard block program operation allows a whole block to be written in one shot The block is automatically erase before being programmed To program a whole block in standard mode the PRG NPRG bits in the FLASH CR2 and FLASH NCR2 registers must be previously set cleared to enable standard block programming see Section 4 8 2 Flash control register 2 FLASH 2 and Section 4 8 2 Flash control register 2 FLASH 2 Then the block of data to be programmed must be loaded sequentially to the destination addresses in the main program memory or DATA area This causes all the bytes of data to be latched To start programming the whole block all bytes of data must be written All bytes written in a programming sequence must be in the same block This means that they must have the same high address Only the six least significant bits of the address can change When
377. ilization delay If a reset is generated the watchdog is disabled reset state unless hardware watchdog is selected by option byte For application recommendations see Section 15 8 below 1 A reset is generated instead of entering Halt mode No reset is generated The MCU enters Active halt mode The watchdog counter is not Active x decremented It stops counting When the MCU receives an oscillator interrupt or external halt interrupt the watchdog restarts counting immediately When the MCU receives a reset the watchdog restarts counting after the stabilization delay 130 595 d DoclD14587 Rev 12 RM0016 Window watchdog WWDG 15 6 Hardware watchdog option If hardware watchdog is selected by option byte the watchdog is always active and the WDGA bit in the WWDG CR register is not used Refer to the option byte description in the datasheet 15 7 Using Halt mode with the WWDG WWDGHALT option The following recommendation applies if Halt mode is used when the watchdog is enabled Before executing the HALT instruction refresh the WDG counter to avoid an unexpected WWDG reset immediately after waking up the microcontroller 15 8 WWDG interrupts None 15 9 WWDG registers 15 9 1 Control register WWDG CR Address offset 0x00 Reset value Ox7F 7 6 5 4 3 2 1 0 WDGA T6 T5 T4 T3 T2 T1 TO rs rw rw rw rw rw rw rw Bit 7 WDGA Activation bit This bit is set by software and only cleared
378. illator with the received LIN Synch Field relative to the master oscillator Two checks are performed in parallel The first check is based on a measurement between the first falling edge and the last falling edge of the Synch Field e If D1 gt 14 84 LHE is set e f D1 lt 14 06 is not set e If 14 06 lt D1 lt 14 84 be either set or reset depending on the dephasing between the signal on UART pin and the fmaster clock The second check is based on a measurement of time between each falling edge of the Synch Field e If D2 gt 18 75 is set e 02 lt 15 62 is not set If 15 62 lt 02 lt 18 75 can be either set or reset depending on dephasing between the signal on UART_RX pin and the fyaster clock Note that the UART does not need to check if the next edge occurs slower than expected This is covered by the check for deviation error on the full synch byte 2 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART Note d Deviation checking is based on the current baudrate and not on the nominal one Therefore in order to guarantee correct deviation checking the baudrate generator must reload the nominal value before each new Break reception This nominal value is programmed by the application during initialization To do this software must set the LDUM bit before checksum reception If LDUM bit is set the next character recept
379. in Section 4 4 1 STM8S STM8AF memory organization Added Note 1 below Figure 7 Flash memory and data EEPROM organization on medium density STM8S and STM8AF Added 32 Kbyte and 128 Kbyte STM8A devices and Section 4 4 2 Memory access wait state configuration Section 4 5 1 Readout protection added DM mode when readout protection is enabled and Section Temporarily removing the readout protection Added case of FLASH_CR1 FLASH_CR2 access during memory write operation in Section 4 6 1 Read while write RWW Moved all information related to temporary memory unprotection to dedicated application note Section 7 Power supply Removed minimum VCAP value in Power section overview Section 8 Reset RST Changed EMS to EMC Added Section 8 1 Reset state and under reset definitions Replace numerical values by top NRsT and tiNFP NRST in Section 8 2 Reset circuit description Section 9 Clock control CLK Added Table 14 Devices with 4 trimming bits and Table 15 Devices with 3 trimming bits in Section 9 1 2 HSI Updated CLK_HSITRIMR CLK_SWIMCCR and CLK_SWCR reset values Section 10 Power management Updated Fast clock wakeup in Section 10 2 3 Active halt modes Section 6 Interrupt controller Added caution note concerning interrupt disabling inside an ISR in Section 6 2 Interrupt masking and processing flow Added Push CC instruc
380. in Sleep mode Therefore the PG and PG registers must be configured in order to maintain a recessive state on CAN TX pin Initialization mode The software initialization can be done while the hardware is in Initialization mode To enter this mode the software sets the INRQ bit in the CAN MCR register and waits until the hardware has confirmed the request by setting the INAK bit in the CAN MSR register To leave Initialization mode the software clears the INQR bit beCAN has exit Initialization mode once the INAK bit has been cleared by hardware However the Rx line has to be in recessive state to leave this mode While in Initialization mode all message transfers to and from the CAN bus are stopped and the status of the CAN bus output CANTX is recessive high Entering Initialization Mode does not change any of the configuration registers To initialize the CAN Controller software has to set up the Bit Timing registers and the filter banks If a filter bank is not used it is recommended to leave it non active leave the corresponding FACT bit in the CAN FCRx register cleared DoclD14587 Rev 12 Ly RM0016 Controller area network beCAN 23 4 2 23 4 3 Note Note 23 4 4 2 Normal mode Once the initialization has been done the software must request the hardware to enter Normal mode to synchronize on the CAN bus and start reception and transmission This request to enter Normal mode is done by
381. in is at high level Through these pins serial data is transmitted and received in normal UART mode as frames comprising e An idle Line prior to transmission or reception e A Start bit A data word 8 or 9 bits least significant bit first e 1 1 5 and 2 Stop bits indicating that the frame is complete e A status register UART_SR e Data Register UART_DR e 16 bit baud rate prescaler UART_BRR e Guard time Register for use in Smartcard mode Refer to the register description for the definitions of each bit DoclD14587 Rev 12 317 462 Universal asynchronous receiver transmitter UART 0016 The following pin is required to interface in synchronous mode UART CK Transmitter clock output This pin outputs the transmitter data clock for synchronous transmission no clock pulses on start bit and stop bit and a software option to send a clock pulse on the last data bit This can be used to control peripherals that have shift registers e g LCD drivers The clock phase and polarity are software programmable The UART RX and UART TX pins are used in IrDA mode as follows UART_RX IrDA RDI Receive Data Input in IrDA mode UART_TX IrDA TDO Transmit Data Output in IrDA mode Figure 110 UART1 block diagram
382. in mask mode 1 High registers are in identifier list mode FMLA Filter 4 mode low Mode of the low identifier mask registers of filter 4 0 Low registers are in mask mode 1 Low registers are in identifier list mode DoclD14587 Rev 12 d 0016 Controller area network beCAN CAN filter configuration register 1 CAN FCR1 Address offset See Table 71 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved FSC11 FSC10 FACT1 Reserved FSCO1 5 00 FACTO r rw rw rw r rw rw rw Bit 7 Reserved Bits 6 5 FSC1 1 0 Filter scale configuration These bits define the scale configuration of Filter 1 Bit 4 FACTI Filter Active The software sets this bit to activate Filter 1 To modify the Filter 1 registers CAN_F1Rx the FACT1 bit must be cleared 0 Filter 1 is not active 1 Filter 1 is active Bit3 Reserved Bits 2 1 FSCO 1 0 Filter scale configuration These bits define the scale configuration of Filter 0 0 FACTO Filter active d The software sets this bit to activate Filter 0 To modify the Filter 0 registers CAN FOR the FACTO bit must be cleared 0 Filter O is not active 1 Filter 0 is active DoclD14587 Rev 12 415 462 Controller area network beCAN RM0016 7 filter configuration register 2 CAN FCR2 Address offset See Table 71 Reset value 0x00 6 5 4 3 2 Reserved FSC31 FSC30 FACT3 Reserved FSC21 FSC20 FACT2 r rw rw rw r w
383. ine detection RXNE RXNE m RX Data 1 Data 2 Data 3 Data 4 IDLE Data5 Data6 RWU Mute Mode Normal Mode RWU written to 1 Idle frame detected Address mark detection WAKE 1 In this mode bytes are recognized as addresses if their MSB is a 1 else they are considered as data In an address byte the address of the targeted receiver is put on the 4 LSB This 4 bit word is compared by the receiver with its own address which is programmed in the ADD bits in the UART register The UART enters mute mode when an address character is received which does not match its programmed address The RXNE flag is not set for this address byte and no interrupt request is issued as the UART would have entered mute mode DoclD14587 Rev 12 Ly RM0016 Universal asynchronous receiver transmitter UART Note 22 3 8 d It exits from mute mode when an address character is received which matches the programmed address Then the RWU bit is cleared and subsequent bytes are received normally The RXNE bit is set for the address character since the RWU bit has been cleared RWU bit can be written to 0 or 1 when the receiver buffer contains no data RXNE 0 in the SR register Otherwise the write attempt is ignored An example of mute mode behavior using address mark detection is given in Figure 121 Figure 121 Mute mode using Address mark detection In th
384. instruction just executed as well as the state of the processor The 6th bit MSB of this register is reserved These bits can be individually tested by a program and specified action taken as a result of their state The following paragraphs describe each bit e V Overflow When set V indicates that an overflow occurred during the last signed arithmetic operation on the MSB result bit See the INC INCW DEC DECW NEG NEGW ADD ADDW ADC SUB SUBW 5 CP and CPW instructions e 11 Interrupt mask level 1 The 11 flag works in conjunction with the 10 flag to define the current interruptability level as shown in Table 1 These flags can be set and cleared by software through the RIM SIM HALT WFI IRET TRAP and POP instructions and are automatically set by hardware when entering an interrupt service routine DoclD14587 Rev 12 25 595 Central processing unit CPU 0016 26 595 Table 1 Interrupt levels Interruptability Priority l1 10 Interruptable main Lowest 1 0 Interruptable level 1 0 1 Interruptable level 2 0 0 Non interruptable Highest 1 1 e H Half carry bit The H bit is set to 1 when carry occurs between the bits 3 and 4 of the ALU during an ADD or ADC instruction The H bit is useful in BCD arithmetic subroutines 4 10 Interrupt mask level 0 See Flag 11 e N Negative When set to 1 this bit indicates that the result of the last arithmetic logical or dat
385. interrupt if ITEVTEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing DR register with Address EV6 ADDR 1 cleared by reading SR1 register followed by reading SR3 EV8 1 TXE 1 shift register empty data register empty write DR register EV8 TXE 1 shift register not empty data register empty cleared by writing DR register EV8 2 TXE 1 BTF 1 Program STOP request TXE and BTF are cleared by HW by stop condition EV9 ADD10 1 cleared by reading SR1 register followed by writing DR register See also Note 8 on page 306 2 8 software sequence must be performed before the end of the current byte transfer In case EV8 software sequence can not be managed before the end of the current byte transfer it is recommended to use BTF instead of TXE with the drawback of slowing the communication DoclD14587 Rev 12 291 595 Inter integrated circuit 2 interface 0016 Master receiver Following the address transmission and after clearing ADDR the I C interface enters Master Receiver mode In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register After each byte the interface generates in sequence e Anacknowledge pulse if the ACK bit is set e RXNE bit is set and an interrupt is generated if the and ITBUFEN bits are set If the RXNE bit is set and the data in the DR register was not read before the end of the next data reception th
386. interrupt mask 0 LIN header detection interrupt disabled 1 LIN header detection interrupt enabled LHDF LIN Header Detection Flag This bit is set by hardware when a LIN header is detected in LIN slave mode and cleared by software writing O 0 LIN Header not detected 1 LIN Header detected Break Sync Ident An interrupt is generated when LHDF 1 if LHDIEN 1 LSF LIN Sync Field This bit indicates that the LIN Synch Field is being analyzed It is only used in LIN Slave mode In automatic resynchronization mode LASE bit 1 when the UART is in the LIN Synch Field State it waits or counts the falling edges on the RDI line It is set by hardware as soon as a LIN Break is detected and cleared by hardware when the LIN Synch Field analysis is finished This bit can also be cleared by software writing O to exit LIN Synch State and return to idle mode 0 The current character is not the LIN Synch Field 1 LIN Synch Field State LIN Synch Field undergoing analysis DoclD14587 Rev 12 367 462 Universal asynchronous receiver transmitter UART 0016 22 7 11 Guard time register UART Address offset 0x09 UART1 OxOA UART2 and UART4 Reset value 0x00 GT 7 0 Bits 7 0 GT 7 0 Guard time value This register gives the Guard time value in terms of number of baud clocks This is used in Smartcard mode The Transmission Complete flag is set after this guard time value Note These bits are no
387. ion at End of Conversion e Data alignment with in built data coherency e input range Vssa lt Vin lt VppA ADC extended features These features are available in ADC1 e Buffered continuous conversion mode 8 e Scan mode for single and continuous conversion e Analog watchdog with upper and lower thresholds e Interrupt generation at analog watchdog event The block diagrams of ADC1 and ADC2 are shown in Figure 159 and Figure 160 a Data buffer size is product dependent 10 x 10 bits or 8 x 10 bits Please refer to the datasheet DoclD14587 Rev 12 423 462 Analog digital converter ADC RM0016 Figure 159 ADC1 block diagram 1 10 Analog Watchdog Event EOC EOCIE End of Conversion Flags Meee AWEN Enable bits 10 channels AWS status bits 10 channels ANALOG WATCHDOG High Threshold 10 bits p ADC Interrupt to ITC Low Threshold 10 bits p DATA BUFFER 10 x 10 bits or 8 x 10 bits 424 462 VppA H Vssa AINO ANALOG MUX DATA REGISTER gt AINT 9 p 1 x 10 bits ANALOG TO DIGITAL f ADC Prescaler MASTER CONVERTER 2 13 14 18 AIN12 LIH GPIO Ports SPSEL Channel s
388. ion does not stop and the byte program operation is performed using the read while write RWW capability in IAP mode Devices without RWW capability The application stops for the duration of the byte program operation To program a word the WPRG NWPRGi bits in the FLASH CR2 and FLASH NCR2 registers must be previously set cleared to enable word programming mode see Section 4 8 2 Flash control register 2 FLASH 2 and Section 4 8 2 Flash control register 2 FLASH 2 Then the 4 bytes of the word to be programmed must be loaded starting with the first address The programming cycle starts automatically when the 4 bytes have been written As for byte operation the EOP and the WR DIS control flags of FLASH IAPSR together with the Flash interrupt can be used to determine if the operation has been correctly completed Block programming Block program operations are much faster than byte or word program operations In a block program operation a whole block is programmed or erased in a single programming cycle Refer to Table 5 for details on the block size according to the devices DoclD14587 Rev 12 47 595 Flash program memory and data EEPROM 0016 48 595 Block operations be performed both to the main program memory DATA area e nthe main program memory Block program operations to the main program memory have to be executed totally from RAM e Inthe DATA area Devices with RWW capab
389. ion will automatically reload the baudrate generator with nominal value You can also reload the nominal value by writing to BRR2 and 1 This second method is typically used when an error occurs during response transmission or reception If for any reason the LDUM bit is set when UAHT is receiving a new Break and a Synch Field this bit will be ignored and cleared UART will adjust the baudrate generator with a value calculated from the synch field LIN header error detection LHE is set if one of the following conditions occurs e Break Delimiter is too short e Deviation error on the Synch Field is outside the LIN specification which allows up to 14 of period deviation between the slave and master oscillators e Framing error in Synch Field or Identifier Field e ALIN header reception time out e An overflow during the Synch Field Measurement which leads to an overflow of the divider registers LIN header time out error The description in the section L N header time out error on page 349 applies also when automatic resynchronization is enabled UART clock tolerance when synchronized When synchronization has been performed following reception of a LIN Break the UART has the same clock deviation tolerance as in UART mode which is explained below During reception each bit is oversampled 16 times The mean of the 8th 9th and 10th samples is considered as the bit value Consequently the clock frequency should not vary mo
390. is 261064 211x330 f 2 x960 f 5 280 s 30 720 s 1111 30 x 211 x APRpiv fLs 11 to 64 In order to obtain the right values for AWUTB 3 0 and you have to e First search the interval range corresponding to the desired time interval This gives the AWUTB S 0 value e Then can be chosen to obtain a time interval value as close as possible to the desired one This can be done using the formulas listed in the table above If the target value is between 2 x1 28 f s and 211x130 f s or between 21 x320 f sand 211x330 f s the value closer to the target one must be chosen DoclD14587 Rev 12 115 462 Auto wakeup AWU RM0016 12 3 3 116 462 Example 1 e fig 128 kHz e Target time interval 6 ms The appropriate interval range is 4 ms 8 ms so the AWUTB 3 0 value is 0x5 The APRpyy value is 6 ms 2 x APRpyy fLs gt APRpyy 610 x fig 2 48 so the APR 5 0 value is 48 0x30 Example 2 e fig 128 kHz e Target time interval 3 s The appropriate interval range is 2 080 s 5 120 s So the AWUTB 3 0 value is OxE The APRpyy value is 3s 5x2 x APRpy fig gt APRp 3 x fig 5 x 2 2 37 5 So the AWUTB 3 0 can be either 37 or 38 which gives a time base of 2 96s or 3 045 respectively This is not exactly 3s LSI clock frequency measurement The frequency dispersion of the low speed internal RC LSI oscillator after RC factory trimming is 128 kHz
391. is example the current address of the receiver is 1 RXNE RXNE programmed in the UART CR4 register A A RX IDLE Addr 0 Data 1 Data 2 IDLE Addr 1 Data 3 Data 4 Addr 2 Data 5 RWU Mute Mode Normal Mode Mute Mode 4 Non matching address Matching address Non matching address RWU written to 1 RXNE was cleared If parity control is enabled the parity bit remains in the MSB and the address bit is put in the MSB 1 bit For example with 7 bit data address mode and parity control SB I 7 bit data I ADD I PB I STB where SB Start Bit STB Stop Bit ADD Address bit PB Parity Bit LIN local interconnection network mode The UART supports LIN break and delimiter generation in LIN master mode Refer to Section 22 4 1 Master mode on page 343 for details LIN slave mode is supported by the UART2 UART3 and UART4 only not by UART1 LIN mode is selected by setting the LINEN bit the register In LIN mode the following bits must be kept cleared e STOP 1 0 in the UART register e SCEN HDSEL and IREN the UART CR5 register DoclD14587 Rev 12 335 462 Universal asynchronous receiver transmitter UART 0016 22 3 9 Note Note 336 462 UART synchronous communication The UART transmitter allows the user to control bidirectional synchronous serial communications in master mode
392. is inactive OC1REF 0 as long as TIMx gt TIMx 1 Otherwise channel 1 is active OC1REF 1 111 PWM mode 2 In up counting channel 1 is inactive as long as TIMx CNT TIMx CCR1 Otherwise channel 1 is active Note In PWM mode 1 or 2 the OCiREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode Refer to Section 17 5 7 on page 172 for more details DoclD14587 Rev 12 233 595 16 bit general purpose timers TIM2 TIM3 TIM5 0016 Bit 3 OC1PE Output compare 1 preload enable 0 Preload register on TIMx CCR 1 disabled TIMx CCR1 can be written at anytime The new value is taken into account immediately 1 Preload register on TIMx CCR1 enabled Read write operations access the preload register TIMx 1 preload value is loaded in the shadow register at each update event Note For correct operation preload registers must be enabled when the timer is in PWM mode This is not mandatory in one pulse mode OPM bit set in TIMx 1 register Bit 2 Reserved Bits 1 0 CC1S 1 0 Capture compare 1 selection This bitfield defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is configured as input is mapped on 10 CC1 channel is configured as input IC1 is mapped on 2 11 CC1 channel is configured as input IC1 is m
393. is mapped on TRC This mode works only if an internal trigger input is selected through the TS bit 1 SMCR register Note CC1S bits are writable only when the channel is off CC1E 0 in TIM1 1 d DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 Channel configured in input IC1F 3 0 IC1PSC 1 0 CC1S 1 0 rw rw rw rw rw rw rw Bits 7 4 IC1F 3 0 Input capture 1 filter This bitfield defines the frequency used to sample 1 input and the length of the digital filter applied to TI1 The digital filter is made of an event counter in which events are needed to validate a transition on the output 0000 No filter SAMPLING fMASTER 0001 fsaupLiNG7fMAsTER 2 0010 N 4 0011 fgampLinc fmaster N 8 0100 fsaupLiNG7fMAsTER 2 N 6 0101 fsampLinc fuaster 2 8 0110 4 N 6 0111 4 N 8 1000 8 N 6 1001 8 N 8 1010 16 N 5 1011 16 N 6 1100 16 8 1101 32 5 1110 lt 32 N 6 1111 15 32 N 8 Note Even on channels that have a complementary output this bit fie
394. its TIMx_CCMR3 register The value of CCR3 is loaded permanently into the actual capture compare 3 register if the preload feature is not enabled OC3PE bit in TIMx CCMR3 Otherwise the preload value is copied in the active capture compare 3 register when a UEV occurs The active capture compare register contains the value which is compared to the counter register TIMx and signalled on the output If the channel is configured as input CC3S bits TIMx CCMRS register The value of CCR3 is the counter value transferred by the last input capture event IC3 18 6 23 Capture compare register low TIMx Address offset 00x14 or 0x16 TIM2 0x16 5 for TIM2 address see Section Reset value 0x00 7 6 5 4 3 2 1 0 CCR3 7 0 rw rw rw rw rw rw rw rw Note This register is not available in TIM3 Bits 7 0 CCR3 7 0 Capture compare value LSB TIM2 TIM3 TIM5 register map and reset values In some STM8S and STMBAF devices TIM2 register locations at offset 0x01 and 0x02 are reserved In this case the TIM2_IER and subsequent registers in the TIM2 block are offset by 2 more bytes Refer to the datasheet for the product specific register map Table 40 TIM2 register map Address offset product Register name 7 6 5 4 3 2 1 0 dependent TIM2 CR1 ARPE URS UDIS CEN 000 0x00 Reset value 0 0 0 0 0 0 0 0 0 01 Reserved 0x02 Reserved TIM2 IER
395. ity This bit selects whether ETR or ETR is used for trigger operations 0 ETR is non inverted active at high level or rising edge 1 ETR is inverted active at low level or falling edge 2 190 595 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Bit 6 ECE External clock enable This bit enables external clock mode 2 0 External clock mode 2 disabled 1 External clock mode 2 enabled The counter is clocked by any active edge on the ETRF signal Note Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF SMS 111 and TS 111 in the SMCR register It is possible to simultaneously use external clock mode 2 with the following modes Trigger standard mode trigger reset mode and trigger gated mode Nevertheless TRGI must not be connected ETRF in these cases TS bits must not be 111 in the TIM1 5 register If external clock mode 1 and external clock mode 2 are enabled at the same time the external clock input is ETRF Bits 5 4 ETPS External trigger prescaler The frequency must be at most 1 4 of fyaster frequency A prescaler can be enabled to reduce ETRP frequency It is useful when inputting fast external clocks 00 Prescaler off 01 ETRP frequency divided by 2 10 ETRP frequency divided by 4 11 ETRP frequency divided by 8 Bits 3 0 ETF External trigger filter This bitfield defines the frequency used to sample the ETRP signa
396. iver if the NACK control bit is set otherwise a NACK is not transmitted e TE bit must be set to enable Data transmission Transmission of acknowledgements in case of parity error Software must manage the timing of data transmission to avoid conflicts on the data line when it writes new data in the data register e The RE bit must be set to enable Data reception sent by the Smartcard as well as by the UART Detection of acknowledgements in case of parity error e assertion of the TC flag can be delayed by programming the Guard Time register In normal operation TC is asserted when the transmit shift register is empty and no further transmit requests are outstanding In Smartcard mode an empty transmit shift register triggers the guard time counter to count up to the programmed value in the Guard Time register TC is forced low during this time When the guard time counter reaches the programmed value TC is asserted high e de assertion of TC flag is unaffected by Smartcard mode e lfaframing error is detected on the transmitter end due to from the receiver the NACK will not be detected as a start bit by the receive block of the transmitter According to the ISO protocol the duration of the received NACK can be 1 or 2 baud clock periods e On the receiver side if a parity error is detected and a is transmitted the receiver will not detect the NACK as a start bit d DoclD
397. l ai15056 1 The stack roll over limit is not implemented on all devices 2 The guard cells are RAM locations that have to be continuously polled by the application program to detect whether a stack overflow has taken place In this stack model the initial stack pointer must be placed beyond the stack roll over limit Consequently the growing stack never reaches the stack roll over limit It is clear that in this implementation the stack size is not limited by the roll over mechanism Nevertheless the user has to define the stack position and stack size in the link file and he has to ensure that the stack pointer does not exceed the defined stack area stack overflow or under run The RAM locations above and below the customized stack can be regularly used as RAM to store variables or other information Guard cells can be implemented at the lower end of the stack to detect if the stack pointer exceeds the defined limit These cells are standard RAM locations initialized with fixed values that the stack overwrites if an overflow occurs The user software can regularly poll these cells detect the overflow condition and put the application in a fail safe state During the software validation phase hardware breakpoints can be set at both limits of the stack to validate that neither a stack overflow nor an under run happens 2 DoclD14587 Rev 12 RM0016 Memory and register map 3 2 2 Register description abbr
398. l and the length of the digital filter applied to it The digital filter is made of an event counter in which N events are needed to validate a transition on the output 0000 No filter sampling is done at fMASTER 0001 fsampLina fmaster 2 0010 fsaupuING7fMASTER N 4 0011 fsampLina fmasTeR N 8 0100 fsaupi ING MAsTER 2 N 6 0101 2 N 8 0110 4 N 6 0111 fgampLina fmasTeR 4 N 8 1000 1 8 N 6 1001 15 8 8 1010 16 N 5 1011 fgampLinc fmasteR 16 N 6 1100 16 N 8 N 5 N 6 N 8 1101 SAMPLING MASTER 32 1110 SAMPLING MASTER 32 1111 SAMPLING MASTEP 32 d DoclD14587 Rev 12 191 595 16 bit advanced control timer TIM1 RM0016 17 7 5 Interrupt enable register TIM1 IER Address offset 0x04 Reset value 0x00 BIE TIE COMIE CC4IE CC2IE CC1IE UIE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 192 595 BIE Break interrupt enable 0 Break interrupt disabled 1 Break interrupt enabled TIE Trigger interrupt enable 0 Trigger interrupt disabled 1 Trigger interrupt enabled COMIE Commutation interrupt enable 0 Commutation interrupt disabled 1 Commutation interrupt enabled
399. ld is not preloaded and does not take into account the content of the CCPC bit in the TIM1 2 register Bits 3 2 IC1PSC 1 0 Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on CC1 input IC1 The prescaler is reset as soon as 1 0 TIM1 CCER register 00 No prescaler capture is made each time an edge is detected on the capture input 01 Capture is made once every 2 events 10 Capture is made once every 4 events 11 Capture is made once every 8 events Bits 1 0 CC1S 1 0 Capture compare 1 selection d This bitfield defines the direction of the channel input output and the used input 00 CC1 channel is configured as output 01 CC1 channel is configured as input IC1 is mapped on 10 CC1 channel is configured as input is mapped on 2 1 11 CC1 channel is configured as input IC1 is mapped on TRC This mode works only if an internal trigger input is selected through the TS bit TIM1 SMCR register Note 15 bits are writable only when the channel is OFF CC1E 0 in TIM1 1 DoclD14587 Rev 12 199 595 16 bit advanced control timer TIM1 0016 17 7 10 mode register 2 TIM1 2 Address offset 0x09 Reset value 0x00 Channel configured in output 7 6 5 4 3 2 1 0 OC2CE 2 2 0 2 2 CC2S 1 0 nw rw nw rw nw nw nw nw Bit 7 OC2CE Output compa
400. lection These bits are set and cleared by software to select 1 2 or 4 kHz beep output when calibration is done 00 fLs 8 x BEEPp y kHz output 01 fi g 4 X kHz output 1x fi g 2 X kHz output Bit5 BEEPEN Beep enable This bit is set and cleared by software to enable the beep feature 0 Beep disabled 1 Beep enabled Bits 4 0 BEEPDIV 4 0 Beep prescaler divider These bits are set and cleared by software to define the Beeper prescaler dividing factor BEEPpjy 0x00 2 0x01 OxOE BEEPpy 16 OxOF 17 Ox1E BEEPp y 32 Note This register must not be kept at its reset value 0x1F 2 DoclD14587 Rev 12 121 462 Beeper BEEP RM0016 13 3 2 Beeper register map and reset values Table 27 Beeper register map Address Register 7 6 5 4 3 2 1 0 offset name BEEP CSR BEEPSEL 2 0 BEEPEN BEEPDIV 4 0 Reset value 00 0 11111 ky 122 462 DoclD14587 Rev 12 0016 Independent watchdog IWDG 14 Independent watchdog IWDG 14 1 Introduction The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus stays active even if the main clock fails 14 2 IWDG functional description d Figure 27 shows the functional blocks of the independent watchdog module When the independent watch
401. led which can be done by setting the SCEN bit in the UART CR5 the UART can communication with an asynchronous Smartcard 2 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Figure 126 ISO 7816 3 asynchronous protocol Guard time sl 0 11 213 4 15 6 7 Start Lihe pulled low bit by receiver during stop in case of parity error When connected to a smartcard the UART TX output drives a bidirectional line that is also driven by the smartcard Smartcard is a single wire half duplex communication protocol e Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1 2 baud clock In normal operation a full transmit shift register will start shifting on the next baud clock edge In Smartcard mode this transmission is further delayed by a guaranteed 1 2 baud clock e If a parity error is detected during reception of a frame programmed with a 1 5 stop bit period the transmit line is pulled low for a baud clock period after 1 2 baud clock period This is to indicate to the Smartcard that the data transmitted to the UART has not been correctly received This NACK signal pulling transmit line low for 1 baud clock will cause a framing error on the transmitter side configured with 1 5 stop bits The application can handle re sending of data according to the protocol A parity error is NACK ed by the rece
402. lementary outputs d DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 17 7 3 Slave mode control register TIM1 SMCR Address offset 0x02 Reset value 0x00 7 6 5 4 3 2 1 0 MSM TS 2 0 Reserved SMS 2 0 rw rw rw rw r rw rw rw Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between TIM1 and another timer through TRGO Bits 6 4 TS 2 0 Trigger selection This bit field selects the trigger input TRGI to be used to synchronize the counter 000 Internal trigger ITRO connected to 6 TRGO 001 Reserved 010 Reserved 011 Internal trigger ITR3 connected to 5 TRGO 100 1 edge detector ED 101 Filtered timer input 1 TI1FP1 110 Filtered timer input 2 TI2FP2 111 External trigger input ETRF 8K low density devices only otherwise reserved Note These bits must only be changed when they are not used e g when SMS 000 to avoid incorrect edge detections at the transition Bit 3 Reserved Bits 2 0 SMS 2 0 Clock trigger slave mode selection When external signals are selected the active edge of the trigger signal TRGI is linked to the polarity selected on the external input see input control register and control register description 000 Clock trigger controller disabled If CEN 1 the prescaler is clocked directly by the int
403. lock tif risi 101 mode 1 CK PSC rising p TI2 Filter Edge 3 TI2FP2 Detector ti2f falling 1 ETRF External clock mode ICF 3 0 1 5 Internal clock TIM1 CCMR2 TIM1_CCER1 od mode internal clock pem ECE SMS 2 0 SMCR DoclD14587 Rev 12 151 595 16 bit advanced control timer TIM1 RM0016 152 595 Procedure Use the following procedure to configure the up counter and for example to count in response to a rising edge on the TI2 input 1 4 5 6 Configure channel 2 to detect rising edges on the TI2 input by writing CC2S 01 in the TIM1_CCMRz2 register Configure the input filter duration by writing the IC2F 3 0 bits in the TIM1_CCMR2 register if no filter is needed keep IC2F 0000 Note The capture prescaler is not used for triggering so it does not need t o be configured The CC2S bits do not need to be configured either as they only select the input capture source Select rising edge polarity by writing CC2P 0 in the TIM1 CCER 1 register Configure the timer in external clock mode 1 by writing SMS 111 in the SMCR register Select 2 as the input source by writing TS 110 in the TIM1 SMCR register Enable the counter by writing CEN 1 in the TIM1 CR1 register When a rising edge occurs on TI2 the counter counts once and the trigger flag is set TIF bit the T
404. log digital converter ADC 24 11 4 7 ADC configuration register 1 ADC CR1 Address offset 0x21 Reset value 0x00 6 5 4 3 2 1 0 Reserved SPSEL 2 0 Reserved CONT ADON r rw rw rw r rw rw Bit 7 Bits 6 4 Bits 3 2 Bit 1 Bit 0 d Reserved always read as 0 SPSEL 2 0 Prescaler selection These control bits are written by software to select the prescaler division factor 000 fanc fuAsTER 2 001 fanc 3 010 fanc fuAsTER A 011 fanc fmasteR 6 100 fanc 8 101 1 0 110 fADC fuAsTER 1 2 111 fADC 8 See Section 24 5 2 page 426 Note It is recommended to change the SPSEL bits when ADC is in power down This is because internally there can be a glitch in the clock during this change Otherwise the user is required to ignore the 1st converted result if the change is done when ADC is not in power down Reserved always read as 0 CONT Continuous conversion This bit is set and cleared by software If set conversion takes place continuously till this bit is reset by software 0 Single conversion mode 1 Continuous conversion mode ADON A D Converter on off This bit is set and reset by software This bit must be written to wake up the ADC from power down mode and to trigger the start of conversion If this bit holds a value of 0 and a 1 is written to it then it wakes the ADC from power
405. me time as the RXNE bit which itself generates an interrupt If the word currently being transferred causes both frame error and overrun error it will be transferred and only the OR bit will be DoclD14587 Rev 12 359 462 Universal asynchronous receiver transmitter UART 0016 22 7 2 Data register UART DR Address offset 0x01 Reset value OxXX 7 6 5 4 3 2 1 0 DR 7 0 rw rw rw rw rw rw rw rw Bits 7 0 DR 7 0 Data value Contains the Received or Transmitted data character depending on whether it is read from or written to The Data register performs a double function read and write since it is composed of two registers one for transmission TDR and one for reception RDR The TDR register provides the parallel interface between the internal bus and the output shift register The RDR register provides the parallel interface between the input shift register and the internal bus 22 7 3 Baud rate register 1 UART BRR1 The Baud Rate Registers are common to both the transmitter and the receiver The baud rate is programmed using two registers BRR1 and BRR2 Writing of BRR2 if required should precede BRR1 since a write to BRR1 will update the baud counters See Figure 119 How to code UAHT DIV in the registers on page 331 and Table 54 Baud rate programming and error calculation on page 332 Note 1 The baud counters stop counting if the TEN or REN bits are disabled respectively Address offse
406. med in user IAP and ICP SWIM modes The page defines the granularity of the user boot code area as described in Section 4 4 3 User boot area UBC Figure 6 Figure 7 and Figure 8 show the Flash memory and data EEPROM organization for STM8S and STMB8AF devices Refer to the STM8S and STM8AF programming manual 0051 for more information The EEPROM access time allows the device to run up to 16 MHz For clock frequencies above 16 MHz Flash data EEPROM access must be configured for 1 wait state This is enabled by the device option byte refer to the option bytes section of the STM8S and STMS8AF datasheets DoclD14587 Rev 12 37 595 Flash program memory and data EEPROM RM0016 Figure 6 Flash memory and data EEPROM organization on low density STM8S and STM8AF DATA EEPROM Programmable size from 2 pages 1 Kbytes up to 8 Kbytes 1 page steps 0x00 9FFF 1 page 1 block 64 bytes 0x00 4000 DATA MEMORY up to 640 bytes 0x00 427F 0x00 4800 OPTION BYTES 1 block 0x00 483F 0x00 8000 interrupt vectors 128 bytes USER BOOT CODE UBC permanently write protected Flash program memory MAIN PROGRAM write access possible for IAP and using MASS mechanism 8 Kbytes of FLASH PROGRAM MEMORY ai15503 38 595 DoclD14587 Rev 12 d 0016 Flash program memory and data EEPROM Figure 7 Flash memory and data EEPROM organization on medium density STM8S a
407. ment revision history continued Date 08 Dec 2009 Revision Changes Figure 105 Method 1 transfer sequence diagram for master receiver Added footnote concerning the next data reception and the EV7event Bus error Updated Updated Figure 116 TC TXE behavior when transmitting and removed note concerning IDLE preamble Updated Section 24 9 Reading the conversion result to account for the fact that the reading order of the ADC results from the buffer registers has no impact on data coherency Section 24 11 1 and Section 24 11 2 Removed sentence about the reading order of the MSB and LSB bits respectively Section 24 11 5 Added note about the ALIGN bit reading order DoclD14587 Rev 12 453 462 Revision history RM0016 454 462 Table 79 Document revision history continued Date 31 Jan 2011 Revision Changes Merge with STM8A reference manual RM0009 Renamed low power modes Halt Active halt Wait and Run in the whole document Added overview of STM8S and STMB8A device families on coverpage Section 2 Boot ROM added LIN mode configuration Section 3 Memory and register map Updated Section 3 1 1 Memory map to cover both STM8A and STM8S devices Added Section 3 1 2 Stack handling Section 4 Flash program memory and data EEPROM Updated Flash program memory and SRAM size for medium density STM8S and 5 devices
408. mentary output enable 0 Off OC1N is not active OC1N level is then a function of the OSSI OSSR OIS1 OIS1N and 1 bits 1 On 1 signal is output on the corresponding output pin depending on the MOE OSSI OSSR OIS1 OIS1N and bits Note On channels that have a complementary output this bit is preloaded If the CCPC bit is set in the TIM1 register the CC1NE active bit takes the new value from the preload bit when a COM is generated Bit 1 CC1P Capture compare 1 output polarity 204 595 CC1 channel configured as output 0 OC1 active high 1 OC1 active low CC1 channel configured as input for trigger function see Figure 64 0 Trigger on a high level or rising edge of TI1F 1 Trigger on a low level or falling edge of TI1F CC1 channel configured as input for capture function see Figure 64 0 Capture on a rising edge of TI1F or TI2F 1 Capture on a falling edge of TI1F or TI2F Note This bit is no longer writable while LOCK level 2 or 3 have been programmed LOCK bits in register On channels that a complementary output this bit is preloaded If the CCPC bit is set in the TIM1 CR register the CC1P active bit takes the new value from the preload bit when COM is generated Bit 0 CC1E Capture compare 1 output enable CC1 channel is configured as output 0 Off OC1 is not active OC1 level is then a function of the MOE OSSI OSSR OIS1 OIS1N and
409. mit Mailbox 0 Empty This bit is set by hardware when no transmit request is pending for mailbox O Bits 1 0 CODE 1 0 Mailbox Code When at least one transmit mailbox is free this field contains the number of the next free transmit mailbox When all transmit mailboxes are pending this field contains the number of the transmit mailbox with the lowest priority Note CODE is always 0 5 7 beCAN compatibility mode TXM2E bit 0 in register 2 400 462 DoclD14587 Rev 12 0016 Controller area network beCAN 23 11 5 CAN receive FIFO register CAN RFR Address offset 0x04 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved RFOM FOVR FULL Reserved FMP 1 0 r rs rc w1 rc w1 r r r Bit 7 6 Reserved Bit 5 RFOM Release FIFO Output Mailbox Set by software to release the output mailbox of the FIFO The output mailbox can only be released when at least one message is pending in the FIFO Setting this bit when the FIFO is empty has no effect If more than one message is pending in the FIFO the software has to release the output mailbox to access the next message Cleared by hardware when the output mailbox has been released Bit 4 FOVR FIFO Overrun This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full This bit is cleared by software writing 1 Bit 3 FULL FIFO Full Set by hardware when three messages are stored in the F
410. modified while LOCK level 2 has been programmed LOCK bits in TIM1 register Bit 2 OSSI Off state selection for idle mode This bit is used when MOE 0 on channels configured as outputs See OC enable description for more details Section 17 7 13 0 When inactive OC outputs are disabled OC enable output signal 0 1 When inactive OC outputs are forced first with their idle level as soon as CCE 1 OC enable output signal 1 Note This bit can no longer be modified while LOCK level 2 has been programmed LOCK bits in the register Bits 1 0 LOCK 1 0 Lock configuration These bits offer a write protection against software errors 00 LOCK off No bits are write protected 01 LOCK level 1 OlSibitin TIM1 OISR register and BKE BKP AOE bits in TIM1 BKR register can no longer be written 10 LOCK level 2 LOCK level 1 CC polarity bits bits in TIM1 CCERi registers as long as the related channel is configured in output through the 5 bits as well as the OSSR and OSSI bits can no longer be written 11 LOCK Level 3 LOCK level 2 CC control bits and OC PE bits in TIM1_CCMRi registers as long as the related channel is configured in output through the 5 bits can no longer be written Note The LOCK bits can be written only once after reset Once the TIM1_BKR register has been written their content is frozen until the next reset Note As the bits AOE BKP BKE OSSR and OSSI ca
411. n 0 The interrupt will be generated when DR is copied into shift register after an ACK pulse If a NACK is received copy is not done and TXE is not set The interrupt will be generated when Shift register is copied into DR after an ACK pulse RXNE is not set in case of ARLO event The STOPF bit is not set after a NACK reception It is recommended to perform the complete clearing sequence READ SR1 then WRITE 2 after STOPF is set Refer to Figure 103 Transfer sequence diagram for slave receiver on page 288 The ADD10 bit is not set after a NACK reception The BTF bit is not set after a NACK reception or in case of an ARLO event Due to timing constraints when in standard mode if CCR is less than 9 i e with peripheral clock below 2 MHz with fMASTER fcpu and the event interrupt disabled the following procedure must be followed modily the reset sequence in order to insert at least 5 cycles between each operations in the flag clearing sequence For example when fyaster 1 MHz use the following sequence to poll the SB bit label wait BTJF BB label wait LD 12 DR once executed the SB bit is then cleared In slave mode it is recommended to perform the complete clearing sequence READ SR1 then READ SR3 after ADDR is set Refer to Figure 103 Transfer sequence diagram for slave receiver on page 288 306 595 DoclD14587 Rev 12 Ly 0016 Inter
412. n Active halt mode Keeping it active ensures fast wakeup from Active halt mode However the current consumption of the MVR is non negligible To further reduce current consumption the MVR regulator can be powered off automatically when the MCU enters Active halt mode To configure this feature set the REGAH bit in the Internal clock register CLK ICKR register In this mode e MCU core is powered only by the LPVR regulator same as in Halt mode e Only the LSI clock source can be used as the HSE clock current consumption is too high for the LPVR The Main voltage regulator is powered on again at wakeup and it requires a longer wakeup time refer to the datasheet electrical characteristics section for wakeup timing and current consumption data Fast clock wakeup As described for Halt mode in order to get the shortest wakeup time it is recommended to select HSI as the clock source The FHWU bit is also available to save switching time A fast wakeup time is very important in Active halt mode It supplements the effect of CPU processing performance by helping to minimize the time the MCU stays in Run mode between two periods in low power mode and thus reduces the overall average power consumption Since the clock is not automatically switched to the original master clock the application must restore the clock source before entering Halt Active halt mode as soon as it is ready Additional analog power cont
413. n DR and DataN 1 in the shift register gt SCL tied low no other data will be received on the bus Clear ACK bit Read DataN 2 in DR gt This launches the DataN reception in the shift register DataN received with a NACK Program START STOP Read DataN 1 RxNE 1 Read DataN The procedure described above is valid for N22 The cases where a single byte or two bytes are to be received should be handled differently as described below Case of a single byte to be received nthe ADDR event clear the ACK bit Clear ADDR Program the STOP START bit Read the data after the RxNE flag is set Case of two bytes to be received Set POS and ACK Wait for the ADDR flag to be set Clear ADDR Clear ACK Wait for BTF to be set Program STOP Read DR twice d DoclD14587 Rev 12 0016 Inter integrated circuit PC interface Figure 107 Method 2 transfer sequence diagram for master receiver when N 2 7 bit master receiver S Address A Data1 A Data2 NA P EV5 EV6e EV6 1 EV7 3 10 bit master receiver S Header A Address A EV5 EV9 EV6 S Header A Data A Data2 NA P EV5 EV6 EV6 1 EV7 3 1 Legend S Start S Repeated Start P Stop A Acknowledge Non acknowledge EVx Event with interrupt if IT
414. n be write locked depending on the LOCK configuration it is necessary to configure all of them during the first write access to the register d 214 595 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 7 31 Deadtime register TIM1 DTR Address offset Ox1E Reset value 0x00 7 6 5 4 3 2 1 0 DTG7 0 nw rw rw rw rw nw nw nw Bits 7 0 DTG 7 0 Deadtime generator set up 3 This bitfield defines the duration of the deadtime inserted between the complementary outputs DT corresponds to this duration psc is the TIM1 clock pulse DTG 7 5 0xx gt DT DTG 7 0 x tatg With tatg f1 DTG 7 5 10x gt DT 64 5 0 x tatg with 2 x tc psc f2 DTG 7 5 110 gt DT 32 DTG 4 0 x tatg with tatg 8 x psc f3 DTG 7 5 111 gt DT 32 4 0 x tatg with tatg 16 x psc f4 Example 125 ns 8 MHz deadtime possible values are DTG 7 0 0 x 0 to 0 x 7F from 0 to 15875 ns in 125 ns steps refer to f1 DTG 7 0 0 x 80 to 0 x BF from 16 us to 31750 ns in 250 ns steps refer to 12 DTG 7 0 0 x CO to 0 x DF from 32 us to 63 us in 1us steps refer to f3 DTG 7 0 0 x EO to 0 x FF from 64 us to 126 us in 2 us steps refer to 14 Note This bitfield can not be modified while LOCK level 1 2 or 3 have been programmed LOCK bits in the TIM1 register DoclD145
415. n master mode e Program the peripheral input clock in 2 FREQR Register in order to generate correct timings e Configure the clock control registers e Configure the rise time register e Program the 2 CHR1 register to enable the peripheral e Setthe START bit in the 12C_CR2 register to generate a Start condition 3 DoclD14587 Rev 12 RM0016 Inter integrated circuit PC interface Note 2 The peripheral input clock frequency must be at least e 1MHzin Standard mode 4MHzin Fast mode SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock starting from the generation of the rising and falling edge respectively As a slave may stretch the SCL line the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after the rising edge generation e fthe SCL line is low it means that a slave is stretching the bus and the high level counter stops until the SCL line is detected high This allows to guarantee the minimum HIGH period of the SCL clock parameter e fthe SCL line is high the high level counter keeps on counting Indeed the feedback loop from the SCL rising edge generation by the peripheral to the SCL rising edge detection by the peripheral takes time even if no slave stretches the clock This loopback duration is linked to SCL rising time impacting SCL V input detection plus delay due to the analog noise filter p
416. n the ETR 1 As no filter is needed in this example write ETF 3 0 0000 in the TIM1 ETR register 2 Setthe prescaler by writing ETPS 1 0 01 in the TIM1 ETR register 3 Select rising edge detection on the ETR pin by writing ETP 0 in the TIM1 ETR register 4 Enable external clock mode 2 by writing 1 in the TIM1 ETR register 5 Enable the counter by writing CEN 1 in the TIM1_CR1 register The counter counts once every two ETR rising edges The delay between the rising edge on the ETR and the actual reset of the counter is due to the resynchronization circuit on the external trigger signal ETRP Figure 48 Control circuit in external clock mode 2 fMASTER CNT_EN ETR ETRP ETRF COUNTER CLOCK CK CNT CK_PSC COUNTER REGISTER 34 35 36 DoclD14587 Rev 12 153 595 16 bit advanced control timer TIM1 RM0016 17 4 5 154 595 Trigger synchronization There are four trigger inputs refer to Table 35 Glossary of internal timer signals on page 135 ETR TH 2 e TRGO from 6 TIM1 timer can be synchronized with an external trigger three modes Trigger standard mode trigger reset mode and trigger gated mode Trigger standard mode The counter can start in response to an event on a selected input Procedure Use the following pr
417. n time the SWEN bit in the CLK_SWCR register to execute the switch In both manual and automatic switching modes the old master clock source will not be powered off automatically in case it is required by other blocks the LSI RC may be used to drive the independent watchdog for example The clock source can be powered off using the bits in the nternal clock register ICKR and External clock register CLK If the clock switch does not work for any reason software can reset the current switch operation by clearing the SWBSY flag This will restore the CLK SWR register to its previous content old master clock DoclD14587 Rev 12 83 462 Clock control CLK RM0016 Figure 22 Clock switching flowchart automatic mode example HARDWARE ACTION MCU in Run mode with HSI 8 SOFTWARE ACTION Set SWEN bit in SWCR Set SWIEN bit in CLK SWCR to enable interrupt if suitable Write target clock source in CLK_SWR Switch busy SWBSY gt 1 Target clock source powered on Target clock source ready after stabilization time Update clock master status SWR gt CLK_CMSR Reset switch busy flag SWBSY gt 0 Switch done SWIF gt 1 Interrupt if activated MCU in Run mode with new master clock source Clear SWIF flag 84 462 DoclD1
418. nal event The OCiREF signal of a given channel be cleared when a high level is detected on ETRF if 1 in the TIM1 CCMRiregisters one enable bit per channel The OCiREF signal remains low until the next UEV occurs This function can be used in output compare mode and PWM mode only It does not work in forced mode The OCiREF signal can be connected to the output of a comparator and be used for current handling by configuring the external trigger as follows 1 Switch off the external trigger prescaler by setting bits ETPS 1 0 in the TIM1 ETR register to 00 2 Disable external clock mode 2 by setting the ECE bit in the TIM1 ETR register to 0 3 Configure the external trigger polarity ETP and the external trigger filter ETF as desired Refer to Figure 47 External trigger input block diagram Figure 79 shows the behavior of the OC REF signal when the ETRF input becomes high for both values of the enable bits OC CE In this example the timer is programmed in PWM mode Figure 79 ETR activation CCRx counter P ETRF _ LLL OC REF OCiCE 0 OCiREF pe OCiCE 1 4 4 ETRF ETRF becomes high still high d DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 5 10 2 Encoder interface mode Encoder interface mode is typically used for motor control It can be selected by
419. nd STM8AF 1 page 512 bytes 1 block 128 bytes 00 4000h DATA MEMORY up to 1 Kbyte DATA EEPROM 00 43FFh 00 4800h OPTION BYTES 1 block 00 487Fh 00 8000h Interrupt vectors 128 bytes Programmable size USER BOOT CODE UBC from 2 pages 1 Kbyte permanently write protected up to 32 Kbytes 1 page steps Flash program memory MAIN PROGRAM write access possible for IAP and using MASS mechanism 00 FFFFh ai15502 1 memory mapping is given for the STM8AF devices featuring 32 Kbytes of Flash program memory and 1 Kbytes of SRAM d DoclD14587 Rev 12 39 595 Flash program memory and data EEPROM 0016 Figure 8 Flash memory and data EEPROM organization high density STM8S and STM8AF 1 page 512 bytes 1 block 128 bytes 0x00 4000 DATA MEMORY up to 2 Kbytes DATA EEPROM 0x00 47FF OPTION BYTES 1 block 0x00 487F 0x00 80001 Interrupt vectors 128 bytes Programmable size USER BOOT CODE UBC from 2 pages 1 Kbytes permanently write protected up to 64 or 128 Kbytes 1 page steps 32 to 128 Kbytes of Flash Program Memory Flash program memory MAIN PROGRAM write access possible for IAP and using MASS mechanism 0x02 7FFF ai15501b 4 4 2 Memory access wait state configuration The Flash data EEPROM access time allows the device to run at up to 16 MHz without wait states When using the high speed external clock HSE at higher frequen
420. nd extended identifiers 29 bit are fully supported by hardware Control status and configuration registers The application uses these registers to e Configure CAN parameters e g baud rate e Request transmissions e Handle receptions e Manage interrupts e Get diagnostic information 2 DoclD14587 Rev 12 RM0016 Controller area network beCAN 23 3 3 23 3 4 d Tx mailboxes Three transmit mailboxes are provided to the software for setting up messages The Transmission Scheduler decides which mailbox has to be transmitted first Acceptance filters The beCAN provides six scalable configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others Receive FIFO The receive FIFO is used by the CAN controller to store the incoming messages Three complete messages can be stored in the FIFO The software always accesses the next available message at the same address The FIFO is managed completely by hardware Figure 141 beCAN block diagram Control Status Configuration Master Control Master Status Transmit Control Transmit Status Transmit Priority Receive FIFO Interrupt Enable Error Status Error Int Enable Tx Error Counter Rx Error Counter Diagnostic Bit Timing Filter Mode Filter Config Tx Mailboxes Mailbox 2
421. nding GPIO registers must be configured correctly The SPI MISO pin is controlled by the SPI peripheral only when the NSS signal is active and the device is selected as slave When the NSS signal is released the pin is driven by GPIO register settings only To function correctly the GPIO has to be configured in input pull up mode with no interrupt This configuration is done using the GPIO DDR GPIO CH 1 and GPIO registers see Section 11 8 1 Alternate function output Configuring the SPI master mode In a master configuration the serial clock is generated on the SCK pin Follow the procedure below to configure the SPI in master mode 1 Select the BR 2 0 bits to define the serial clock baud rate see SPI CR1 register 2 Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock see Figure 93 3 Configure the LSBFIRST bit in the SPI CR1 register to define the frame format 4 n Hardware mode connect the NSS pin to a high level signal during the complete data transmit sequence In software mode set the SSM and SSI bits in the SPI CR2 register 5 Setthe MSTR and SPE bits they remain set only if the NSS pin is connected to a high level signal In this configuration the MOSI pin is a data output and to the MISO pin is a data input d DoclD14587 Rev 12 RM0016 Serial peripheral interface SPI 20 3 4 20 3 5 2 Configuring the SPI for simple
422. ned format depending on the ALIGN bit Left Data Alignment These bits contain the ADC data width 8 LSB bits of the converted data remaining bits of the register are tied to zero See Figure 165 Right Data Alignment These bits contain the 8 LSB bits of the converted data The LSB must be read first before reading the MSB see Section 24 9 Reading the conversion result and Figure 164 2 DoclD14587 Rev 12 0016 Analog digital converter ADC 24 11 9 ADC Schmitt trigger disable register high Address offset 0x26 Reset value 0x00 TD 15 8 Bits 7 0 TD 15 8 Schmitt trigger disable high These bits are set and cleared by software When a TDx bit is set it disables the port input Schmitt trigger of the corresponding ADC input channel x even if this channel is not being converted This is needed to lower the static power consumption of the I O port 0 Schmitt trigger enabled 1 Schmitt trigger disabled 24 11 10 ADC Schmitt trigger disable register low ADC TDRL Address offset 0x27 Reset value 0x00 TD 7 0 Bits 7 0 TD 7 0 Schmitt trigger disable low These bits are set and cleared by software When a TDx bit is set it disables the I O port input Schmitt trigger of the corresponding ADC input channel x even if this channel is not being converted This is needed to lower the static power consumption of the I O port 0 Schmit
423. neration register TIM1 EGR Address offset 0x07 Reset value 0x00 BG TG COMG CC4G CC3G CC2G UG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 d BG Break generation This bit is set by software to generate an event It is automatically cleared by hardware 0 No action 1 A break event is generated The MOE bit is cleared and the BIF flag is set An interrupt is generated if enabled by the BIE bit TG Trigger generation This bit is set by software to generate an event It is automatically cleared by hardware 0 No action 1 The TIF flag is set in TIM1 SR1 register An interrupt is generated if enabled by the TIE bit Capture compare control update generation This bit can be set by software and is automatically cleared by hardware 0 No action 1 When the CCPC bit in the TIM1 2 register is set it allows the CC E CCNP and bits to be updated Note This bit acts only on channels that have a complementary output CC4G Capture compare 4 generation Refer to CC1G description CC3G Capture compare 3 generation Refer to CC1G description DoclD14587 Rev 12 195 595 16 bit advanced control timer TIM1 0016 17 7 9 196 595 Bit 2 CC2G Capture compare 2 generation Refer to CC1G description Bit 1 CC1G Capture compare 1 generation This bit is set by software to generate an event It is automatically cleared by hardware
424. ng of program memory In devices with boot ROM the reset initialization routine is programmed in ROM by STMicroelectronics e Fixed interrupt vector addresses located at the high addresses of the memory map 0x00 8004 to 0x00 807C sorted by hardware priority order Interrupt masking and processing flow The interrupt masking is managed by bits 11 and 10 of the register and by the SPRx registers which set the software priority level of each interrupt vector see Table 8 The processing flow is shown in Figure 13 When an interrupt request has to be serviced 1 Normal processing is suspended at the end of the current instruction execution 2 The X Y A and CCR registers are saved onto the stack 3 Bits 11 and l0 of CCR register are set according to the values in the ITC SPRx registers corresponding to the serviced interrupt vector 4 The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched The interrupt service routine should end with the IRET instruction which causes the content of the saved registers to be recovered from the stack As a consequence of the IRET instruction bits 11 and 10 are restored from the stack and the program execution resumes 2 DoclD14587 Rev 12
425. nse and wait for next header When a LIN Header is received e The LHDF flag in the UART CR6 register indicates that LIN Header has been detected e An interrupt is generated if the LHDIEN bit in the UART CR6 register is set e The LIN Identifier is available in the UART DR register It is recommended to put UART in mute mode by setting RWU bit This mode allows detection of headers only and prevents the reception of any other characters Setting the PCEN bit in the UART CR2 register while LIN is in slave mode enables the Identifier parity check The PE flag in the CR6 register is set together with the LHDF flag in the CR6 register if the Identifier parity is not correct Response transmission slave is the publisher of the response In order to send n data bytes the application must repeat following sequence n times 1 Write data in the UART register 2 Wait for the RXNE flag in the UART SR register 3 Check for readback value by reading the UART DR register Once response transmission is completed software can set the RWU bit Response reception slave is the subscriber of the response In order to receive n data bytes the application must repeat following sequence n times 1 Wait for the RXNE flag in the UART SR register 2 Read the UART DR register Once response reception is completed software can set the RWU bit DoclD14587 Rev 12 347 462 Universal asynchronous receiver transmitter UART
426. nship 0 The first clock transition is the first data capture edge 1 The second clock transition is the first data capture edge Note This bit is not available for UARTS BitO LBCL Last bit clock pulse 1 This bit allows the user to select whether the clock pulse associated with the last data bit transmitted MSB has to be output on the SCLK pin 0 The clock pulse of the last data bit is not output to the SCLK pin 1 The clock pulse of the last data bit is output to the SCLK pin Note This bit is not available for UARTS 1 These bits CPOL LBCL should not be written while the transmitter is enabled 2 The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by the M bit in the UART CR1 register 364 462 DoclD14587 Rev 12 Ly RM0016 Universal asynchronous receiver transmitter UART 22 7 8 7 Control register 4 UART CR4 Address offset 0x07 Reset value 0x00 6 5 4 3 2 Reserved LBDIEN LBDL LBDF ADD 3 0 r rw rw rw rw rw Bit 7 Bit 6 Bit 5 Bit 4 Bits 3 0 d Reserved must be kept cleared LBDIEN LIN Break Detection Interrupt Enable Break interrupt mask break detection using break delimiter 0 LIN break detection interrupt disabled 1 LIN break detection interrupt enabled LBDL LIN Break Detection Length This bit is for selection between 11 bit or 10 bit break detection 0 10 bit break d
427. nsmission request on mailbox 2 has been completed successfully Please refer to Figure 146 This bit is cleared by hardware when mailbox 2 is requested for transmission or when the software clears the RQCP2 bit Bit 5 TXOK1 Transmission OK for mailbox 1 This bit is set by hardware when the transmission request on mailbox 1 has been completed successfully Please refer to Figure 146 This bit is cleared by hardware when mailbox 1 is requested for transmission or when the software clears the 1 bit Bit 4 TXOKO Transmission OK for mailbox 0 This bit is set by hardware when the transmission request on mailbox 0 has been completed successfully Please refer to Figure 146 This bit is cleared by hardware when mailbox 1 is requested for transmission or when the software clears the RQCPO bit Bit 3 Reserved 398 462 DoclD14587 Rev 12 Ly 0016 Controller area network beCAN Bit2 RQCP2 Request Completed for Mailbox 2 This bit is set by hardware to signal that the last request for mailbox 2 has been completed The request could be a transmit or an abort request This bit is cleared by software writing 1 Bit 1 RQCP1 Request Completed for Mailbox 1 This bit is set by hardware to signal that the last request for mailbox 1 has been completed The request could be a transmit or an abort request This bit is cleared by software writing 1 Bit RQCPO Request Completed for Mailbox 0 This bit is set by hardware
428. nter clock frequency fox is equal to fox psc 2 3 0 PSC 7 4 are forced to 0 by hardware PSCR contains the value which is loaded in the active prescaler register at each update event including when the counter is cleared through the UG bit of the TIMx EGR register This means that a UEV must be generated so that a new prescaler value can be taken into account 18 6 16 Auto reload register high TIMx ARRH Address offset 00 00 or OxOF 2 0xOB OxOF TIM5 for TIM2 address see Section Reset value OxFF 7 6 5 4 3 2 1 0 ARR 15 8 rw rw rw rw rw rw rw rw Bits 7 0 ARR 15 8 Auto reload value MSB d ARR is the value to be loaded in the actual auto reload register Refer to the Section 17 3 TIM1 time base unit on page 140 for more details about ARR update and behavior The counter is blocked while the auto reload value is 0 DoclD14587 Rev 12 241 595 16 bit general purpose timers TIM2 TIM3 TIM5 RM0016 18 6 17 Auto reload register low TIMx ARRL Address offset OOxOE or 0x10 TIM2 0 0 TIM3 0x10 5 for TIM2 address see Section Reset value OxFF 7 6 5 4 3 2 1 0 ARR 7 0 rw rw rw rw rw rw rw rw Bits 7 0 ARR 7 0 Auto reload value LSB 18 6 18 Capture compare register 1 high TIMx CCR1H Address offset 00x0F or 0x11 2 OxOD TIM3 0x11 TIM5 for TIM2 address see Section Reset value 0x0
429. nterface 257 20 1 Introduction ssa e CEP RE RR REDE es 257 20 2 1 257 20 3 SPI functional 258 20 3 1 General description 258 20 3 2 Configuring the SPI in slave mode 262 20 3 8 Configuring the SPI master mode 262 20 3 4 Configuring the SPI for simplex communications 263 20 3 5 Data transmission and reception procedures 263 20 3 6 calculation 270 20 8 7 Status flags 272 20 8 8 Disabling the 272 20 3 8 ErortlagsS 22522 42 oed e edo Pearce RR EO 274 20 3 10 SPI low power modes 275 20 3 11 SPlinterrupts 275 20 4 SPI registers cides ae sek xRawex Va Rak oie dono 277 20 4 1 control register 1 SPI 1 277 20 4 2 SPI control register 2 SPI 2 278 20 4 3 SPlinterrupt control register SPI 279 20 4 4 SPI status register SPI SR
430. ntroller area network beCAN 23 11 7 diagnostic register CAN DGR Address offset 0x06 Reset value 0 0 7 6 5 4 3 2 1 0 Reserved TXM2E RX SAMP SILM LBKM r rw r r rw rw Bit 7 5 Reserved Bit 4 2 TX Mailbox 2 enable 0 Force compatibility with ST7 beCAN 2 TX Mailboxes reset value 1 Enables the third TX Mailbox Mailbox number 2 Bit 8 RX CAN Rx Signal Monitors the actual value of the CAN RX Pin Bit2 SAMP Last sample point The value of the last sample point Bit 1 SILM Silent mode 0 Normal operation 1 Silent mode Bit LBKM Loop back mode 0 Loop back mode disabled 1 Loop back mode enabled 23 11 8 CAN page select register CAN PSR Address offset 0x07 Reset value 0x00 7 6 5 4 3 2 1 0 mem r rw rw rw Bits 7 3 Reserved Bits 2 0 PS 2 0 Page select This register is used to select the register page 000 Tx Mailbox 0 001 Tx Mailbox 1 010 Acceptance Filter 0 1 011 Acceptance Filter 2 3 100 Acceptance Filter 4 5 101 Tx Mailbox 2 110 Configuration Diagnostic 111 Receive FIFO Refer to Figure 158 for more details d DoclD14587 Rev 12 403 462 Controller area network beCAN RM0016 23 11 9 CAN error status register CAN ESR 7 Address offset See Table 71 Reset value 0000 0000 00h 6 5 3 Reserved LEC 2 0 Reserved BOFF EPVF EWGF r rw rw r
431. o the filter priority rules Thus each received message has its associated Filter Match Index The Filter Match Index can be used in two ways Compare the Filter Match Index with a list of expected values Use the Filter Match Index as an index on an array to access the data destination location For non masked filters the software no longer has to compare the identifier If the filter is masked the software reduces the comparison to the masked bits only Note The index value of the filter number does not take into account the activation state of the filter banks Table 65 Example of filter numbering Filter bank Filter number Number FCS FMH FML FACT Configuration 0 0b11 1 1 1 Identifier list 32 bit i 1 0b11 0 0 1 Identifier mask 32 bit 2 3 2 0010 1 1 1 Identifier list 16 bit E 6 7 Deactivated 3 0b00 0 1 0 Identifier List Identifier 10 mask 8 bit 11 12 4 0b10 0 0 0 Deactivated 13 Identifier Mask 16 bit 14 15 5 0601 0 0 1 Identifier Mask 16 8 bit 16 17 DoclD14587 Rev 12 387 462 Controller area network beCAN 0016 388 462 Filter priority rules Depending on the filter combination it may occur that an identifier passes successfully through several filters In this case the filter match value stored in the receive mailbox is chosen according to the following rules 82 bit filter takes priority over 16 bit filter which takes itself p
432. ocedure to start the up counter in response for example to a rising edge on the TI2 input 1 Configure channel 2 to detect rising edges on 2 As no filter is required in this example configure an input filter duration of 0 IC2F 0000 The capture prescaler is not used for triggering and does not need to be configured The CC2S bits select the input capture source and do not need to be configured either Write CC2P 0 in the TIM1 CCER1 register to select rising edge polarity 2 Configure the timer in trigger mode by writing SMS 110 in the TIM1 SMCR register Select 2 as the input source by writing TS 110 in the SMCR register When a rising edge occurs on TI2 the counter starts counting on the internal clock and the TIF flag is set The delay between the rising edge on TI2 and the actual reset of the counter is due to the resynchronization circuit on TI2 input Figure 49 Control circuit in trigger mode T2 CNT EN COUNTER CLOCK CK CNT PSC COUNTER REGISTER 34 TIF 2 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 d Trigger reset mode The counter and its prescaler can be re initialized in response to an event on a trigger input Moreover if the URS bit from the TIM1 CR 1 register is low UEV is generated Then all the preloaded registers TIM1 ARR TIM1 are updated Example Use t
433. oclD14587 Rev 12 RM0016 Central processing unit CPU 1 1 1 2 1 2 1 2 Central processing unit CPU Introduction The CPU has an 8 bit architecture Six internal registers allow efficient data manipulations The CPU is able to execute 80 basic instructions It features 20 addressing modes and can address six internal registers For the complete description of the instruction set refer to the STM8 microcontroller family programming manual PM0044 CPU registers The six CPU registers are shown in the programming model in Figure 1 Following an interrupt the registers are pushed onto the stack in the order shown in Figure 2 They are popped from stack in the reverse order The interrupt routine must therefore handle it if needed through the POP and PUSH instructions Description of CPU registers Accumulator A The accumulator is an 8 bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations Index registers X and Y These are 16 bit registers used to create effective addresses They may also be used as a temporary storage area for data manipulations and have an inherent use for some instructions multiplication division In most cases the cross assembler generates a PRECODE instruction PRE to indicate that the following instruction refers to the Y register Program counter PC The program counter is a 24 bit register use
434. ocol DoclD14587 Rev 12 341 462 Universal asynchronous receiver transmitter UART 0016 342 462 Figure 128 IrDA SIR ENDEC block diagram IREN bit IrDA UART TX pin IrDA TX p Transmit Encoder TX UART IREN bit IrDA IrDA Bx Receive 4 UART RX pin Decoder Figure 129 IrDA data modulation 3 16 normal mode Start stop bit lo j 1 0 1 0 0 1 1 0 1 bit period IrDA TDO P mm IrDA RDI RX 1 ol 0 0 lol 1 d DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART 22 4 22 4 1 2 LIN mode functional description In LIN mode 8 bit data format with 1 stop bit is required in accordance with the LIN standard To configure these settings clear the M bit in UART_CR1 register and clear the STOP 1 0 bits in the UART_CR3 register Master mode UART initialization Procedure 1 Select the desired baudrate by programming the UART_BRR2 and UART_BRR1 registers 2 Enable LIN mode by setting the LINEN bit in the UART_CR3 register 3 Enable the transmitter and receiver by setting the TEN and REN bits in the UART_CR2 register LIN header transmission According to the LIN protocol any
435. ode while the counter is enabled CEN 1 Encoder mode SMS 001 010 or 011 in TIM1 SMCR register must be disabled in center aligned mode Bit 4 DIR Direction 0 Counter used as up counter 1 Counter used as down counter Note This bit is read only when the timer is configured in center aligned mode or encoder mode Bit 3 OPM One pulse mode 186 595 0 Counter is not stopped at update event 1 Counter stops counting at the next update event clearing the CEN bit d DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Bit 2 URS Update request source 0 When enabled by the UDIS bit the UIF bit is set and an update interrupt request is sent when one of the following events occurs Registers are updated counter overflow underflow UG bitis set by software Update event is generated through the clock trigger controller 1 When enabled by the UDIS bit the UIF bit is set and an update interrupt request is sent only when registers are updated counter overflow underflow Bit 1 UDIS Update disable 0 A UEV is generated as soon as a counter overflow occurs a software update is generated or a hardware reset is generated by the clock trigger mode controller Buffered registers are then loaded with their preload values 1 A UEV is not generated and shadow registers keep their value ARR PSC CCR The counter and the prescaler are re initialized if the UG bit is set or if a hardware reset is received
436. oes not wake up from mute mode In this case the current header analysis is discarded If needed the software has to reset the LSF bit Then the UART searches for a new LIN header In mute mode if a framing error occurs on a data which is not a break it is discarded and the FE bit is not set Any LIN header which respects the following conditions causes a wake up from mute mode e Avalid LIN Break and Delimiter e Avalid LIN Synch Field without deviation error e ALIN Identifier Field without framing error Note that a LIN parity error on the LIN Identifier Field does not prevent wake up from mute mode e Header Time out should occur during Header reception 22 4 3 Slave mode with automatic resynchronization enabled This mode is similar to slave mode as described in Section 22 4 2 Slave mode with automatic resynchronization disabled with the addition of automatic resynchronization enabled by the LASE bit In this mode UART adjusts the baudrate generator after each Synch Field reception Note This feature is only available in UART2 and UARTS Automatic resynchronization When automatic resynchronization is enabled after each LIN Break the time duration between 5 falling edges RDI is sampled on fyasterR and the result of this measurement is stored in an internal 19 bit register called SM not user accessible See Figure 135 Then the UARTDIV value and its associated BRR1 and BRR2 registers are automatically u
437. of STM8S option byte area in Section 4 4 Memory organization and Figure 6 Figure 7 and Figure 8 Updated maximum value of UBC in Figure 11 Added information on DATA area programming on devices with and without RWW capability in Section 4 6 2 Byte programming and Section 4 6 4 Block programming Added HVOFF in Fast block programming Fast block programming and Section 4 8 8 Flash status register FLASH IAPSR Updated bitfield access types in Section 4 8 8 Flash status register FLASH IAPSR on page 55 Table 6 Memory access versus programming method removed NMI and TRAP vectors modified access for option bytes in ICP SWIM mode ROP enabled and UBC ROP disabled Updated Table 28 Watchdog timeout period LSI clock frequency 128 kHz on page 124 Updated Table 29 Approximate timeout duration on page 129 Table 30 Window watchdog timing diagram on page 130 Updated Note 8 on page 306 15 Jan 2009 4 Added note to Section 4 4 Memory organization Added Section 4 4 2 Memory access wait state configuration Updated maximum value of UCB 7 0 in Figure 2 Page 255 is reserved for data EEPROM Added note 1 below Figure 10 Added note 1 and updated note 3 below Figure 11 Check in PUL DUL bits made mandatory in Section 4 5 2 Memory access security system MASS Added details in Section 4 6 Memory programming on word 10 Aug 2009 5 programming in main program and DATA Updated Section 4 8 8 Flash status register FLASH IAPS
438. og ranging from to 500 mV Reference negative This input is bonded to VSSA devices that have no external VREF pin packages with 48 pins or less The higher positive reference voltage for the ADC V Input Analog ranging from 2 75 V to This input is bonded to VppA REF Reference positive in devices that have no external VREF pin packages with 48 pins or less Up to 16 analog input channels which are converted by AIN 15 0 Analog input signals the ADC one at a time ADC_ETR Digital input signals External trigger ADC functional description ADC on off control The ADC can be powered on by setting the ADON bit in the ADC_CR1 register When the ADON bit is set for the first time it wakes up the ADC from power down mode To start conversion set the ADON bit in the ADC_CR1 register with a second write instruction At the end of conversion the ADC remains powered on and you have to set the ADON bit only once to start the next conversion If the ADC is not used for a long time it is recommended to switch it to power down mode to decrease power consumption This is done by clearing the ADON bit When the ADC is powered on the digital input and output stages of the selected channel are disabled independently on the GPIO pin configuration It is therefore recommended to select the analog input channel before powering on the ADC see Section 24 5 3 Channel selection AD
439. og watchdog function for each of the 10 data buffer registers 0 Analog watchdog disabled in data buffer register x 1 Analog watchdog enabled in data buffer register x 2 DoclD14587 Rev 12 447 462 Analog digital converter ADC 0016 24 12 ADC register and reset values Table 77 ADC1 register map and reset values Address i Register name 7 6 5 4 3 2 1 0 offset sd ADCi DBORH DATA9 DATA8 Reset value 0 0 0 0 0 0 0 0 T ADC1 DBORL DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATA1 DATAO Reset value 0 0 0 0 0 0 0 0 0 02 to Ox0D Reserved 0 ADC1 DB7RH i DATA9 DATA8 Reset value 0 0 0 0 0 0 0 0 OxOFh ADC1 DB7RL DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATA1 DATAO Reset value 0 0 0 0 0 0 0 0 1 ADC1 DATA9 DATA8 Reset value 0 0 0 0 0 0 0 0 ADC1 DB8RL DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATA1 DATAO Reset value 0 0 0 0 0 0 0 0 db ADC1 DB9RH gt DATA9 DATA8 Reset value 0 0 0 0 0 0 0 0 ADC1_DB9RL DATA7 DATA6 DATAS DATA4 DATA3 DATA2 DATA1 DATAO Reset value 0 0 0 0 0 0 0 0 0x14 to Ox1F Reserved ies ADC1_CSR EOC AWD EOCIE AWDIE CH3 CH2 CH1 CHO Reset value 0 0 0 0 0 0 0 0 d ADC1 CR1 SPSEL2 SPSEL1 SPSELO z CONT ADON Reset value 0 0 0 0 0 0 0 0 id ADC1_CR2 EXTTRIG EXTSEL1 EXTSELO ALIGN
440. on Abort A transmission request can be aborted by the user setting the ABRQ bit in the CAN MCSR register In pending or scheduled state the mailbox is aborted immediately An abort request while the mailbox is in transmit state can have two results If the mailbox is transmitted successfully the mailbox becomes empty with the TXOK bit set in the CAN MCSR and CAN TSR registers If the transmission fails the mailbox becomes scheduled the transmission is aborted and becomes empty with TXOK cleared In all cases the mailbox will become empty again at least at the end of the current transmission Non automatic retransmission mode This mode has been implemented in order to fulfil the requirement of the Time Triggered Communication option of the CAN standard To configure the hardware in this mode the NART bit in the CAN MCR register must be set In this mode each transmission is started only once If the first attempt fails due to an arbitration loss or an error the hardware will not automatically restart the message transmission At the end of the first transmission attempt the hardware considers the request as completed and sets the RQCP bit in the MCSR register The result of the transmission is indicated in the CAN MCSR register by the TXOK ALST and TERR bits 2 DoclD14587 Rev 12 RM0016 Controller area network beCAN d Figure 146 Transmit mailbox states TXRQ 1 PENDING RQCP 0 Mailbox
441. on for more details on error conditions please refer to the CAN Error Status register CAN ESR Wakeup condition SOF monitored on the CAN Rx signal DoclD14587 Rev 12 Ly RM0016 Controller area network beCAN 23 8 23 9 Note 23 10 Note d Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network Therefore the following registers can be modified by software only while the hardware is in initialization mode CAN 1 CAN BTR2 CAN FCR1 FCR2 CAN 1 CAN FMR2 and CAN DGR registers Although the transmission of incorrect data will not cause problems at the CAN network level it can severely disturb the application A transmit mailbox can be only modified by software while it is in empty state refer to Figure 146 Transmit mailbox states The filters must be deactivated before their value can be modified by software The modification of the filter configuration scale or mode can be done by software only in initialization mode Clock system The clock tolerance limit as specified in CAN protocol is 1 58 96 at speeds of up to 125 Kbps For higher baud rates it is suggested to use a crystal oscillator If the clock security system feature is enabled in the CLK controller Refer to the description of the CSSEN bit in the Clock security system register CLK CSSH on page 96 there is a way to put CAN
442. on programming IAP and in circuit programming ICP capabilities Protection features Memory readout protection ROP Program memory write protection with memory access security system MASS keys Data memory write protection with memory access security system MASS keys Programmable write protected user boot code area UBC Memory state configurable to operating or power down Ippo in Halt and Active halt modes DoclD14587 Rev 12 35 595 Flash program memory and data EEPROM 0016 4 4 4 4 1 36 595 Memory organization STM8S and STM8AF memory organization STM8S and STM8AF EEPROM is organized in 32 bit words 4 bytes per word The memory organization differs according to the devices Low density STM8S and STM8AF devices 8 Kbytes of Flash program memory organized in 128 pages or blocks of 64 bytes each The Flash program memory is divided into 2 areas the user boot code area UBC which size can be configured by option byte and the main program memory area The Flash program memory is mapped in the upper part of the STMBS addressing space and includes the reset and interrupt vectors Up to 640 bytes of data EEPROM DATA organized in pages or blocks of 64 bytes each One block 64 bytes contains the option bytes of which 11 are used to configure the device hardware features The options bytes can be programmed in user IAP and ICP SWIM modes Medium density STM8S devices From 16 to 32 Kbyt
443. option byte description the KEY_ENABLE value is the first value to be written in this register KEY ENABLE value 0xCC Writing the KEY_ENABLE value starts the IWDG KEY REFRESH value 0xAA Writing the KEY_REFRESH value refreshes the IWDG KEY_ACCESS value 0x55 Writing the KEY ACCESS value enables the access to the protected IWDG_PR and IWDG_RLR registers see Section 14 2 Prescaler register INDG PR Address offset 0x01 Reset value 0x00 6 5 4 3 2 1 0 Reserved PR 2 0 r rw Bits 7 3 Bits 2 0 d Reserved PR 2 0 Prescaler divider These bits are write access protected see Section 14 2 They can be written by software to select the prescaler divider feeding the counter clock 000 divider 4 001 divider 8 010 divider 16 011 divider 32 100 divider 64 101 divider 128 110 divider 256 111 Reserved DoclD14587 Rev 12 125 595 Independent watchdog IWDG 0016 14 3 3 Reload register IWDG RLR Address offset 0x02 Reset value OxFF 7 6 5 4 3 2 1 0 RL 7 0 rw Bits 7 0 RL 7 0 Watchdog counter reload value These bits are write access protected see Section 14 2 They are written by software to define the value to be loaded in the watchdog counter each time the value OxAA is written in the IWDG KR register The watchdog counter counts down from this value The timeout period is a function of this value and the clock prescaler Refer
444. ositive pulse 177 Six step generation COM example OSSR 1 179 Behavior of outputs in response to a break channel without complementary output 180 Behavior of outputs in response to a break TIM1 complementary outputs 181 Activation uox a prese ae ex eu ART ER Y ede 182 Example of counter operation in encoder interface mode 184 Example of encoder interface mode with polarity 184 TIM2 TIMS3 block 0 55 220 5 block diagram 221 gyak ey ERELT een ene ER ee Fr RUD 221 Input stage block 223 Input stage of TIM 2 channel 1 2 223 Output stage tene ehe i e ae mE de ades E eid PE ce 224 Output stage of channel 1 1 224 4 block diagram 0 248 TIM6 block diagram 2 248 SPI block 258 Single master single slave 259 Data clo
445. out protection can be disabled on the program memory UBC and DATA areas by reprogramming the ROP option byte in ICP mode In this case the Flash program memory the DATA area and the option bytes are automatically erased and the device can be reprogrammed Refer to Table 6 Memory access versus programming method for details on memory access when readout protection is enabled or disabled Memory access security system MASS After reset the main program and DATA areas are protected against unintentional write operations They must be unlocked before attempting to modify their content This unlock mechanism is managed by the memory access security system MASS The UBC area specified in the UBC option byte is always write protected see Section 4 4 3 User boot area UBC Once the memory has been modified it is recommended to enable the write protection again to protect the memory content against corruption Enabling write access to the main program memory After a device reset it is possible to disable the main program memory write protection by writing consecutively two values called MASS keys to the FLASH PUKR register see Section 4 8 6 Flash program memory unprotecting key register FLASH PUKR These programmed keys are then compared to two hardware key values e First hardware key 000101 0110 0x56 e Second hardware key 001010 1110 OxAE 3 DoclD14587 Rev 12 RM0016 Flash program memory and data EEPROM
446. ow wsciL See device datasheet for the definitions of parameters The real frequency may differ due to the analog noise filter input delay The CCR registers must be configured only when the is disabled PE 0 fMAsTER multiple of 10 MHz is required to generate Fast clock at 400 kHz fMAsTER 2 1 MHz is required to generate Standard clock at 100 kHz DoclD14587 Rev 12 311 595 Inter integrated circuit I2C interface 0016 Table 50 2 values for SCL frequency table fmaster 10 MHz or 16 2 1 2 frequency fmaster 10 MHz fmaster 16 MHz 12C fsc Speed Duty in Hz Actual Error 12C_CCR cycle Actual Error 126 Duty cycle Hz bit Hz h bit 400000 400000 0 1 1 410256 41 2 56 D 0 370000 370370 37 0 10 9 0 380952 38 2 96 E 0 350000 370370 37 5 82 9 0 355555 56 1 59 F 0 320000 333333 33 4 17 A 0 320000 0 2 1 300000 303030 30 1 01 B 0 313725 49 4 57 11 0 Fast 270000 277777 78 2 88 C 0 280701 75 3 96 13 0 speed 250000 256410 26 2 56 D 0 253968 25 1 59 15 0 220000 22222222 1 01 F 0 222222 22 1 01 18 0 200000 200000 0 2 1 205128 20 2 56 1A 0 170000 175438 60 3 20 13 0 172043 01 1 20 1 0 150000 151515 15 1 01 16 0 152380 95 1 59 23 0 120000 123456 79 2 88 1B 0 121212 12 1 01 2C 0 100000 100000 0 32 100000 0 50 Standard 50000 50000 0 64 50000 0 0 TOW speed
447. ow registers keep their value ARR PSC The counter and the prescaler are re initialized if the UG bit is set Bit CEN Counter enable 0 Counter disable 1 Counter enable 250 595 DoclD14587 Rev 12 Ly RM0016 8 bit basic timer TIM4 TIM6 19 6 2 Control register 2 TIM6_CR2 Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved MMS 2 0 Reserved r rw rw rw r Note This register is not available in TIM4 Bit 7 Reserved must be kept cleared Bits 6 4 MMS 2 0 Master mode selection These bits are used to select the information to be sent in master mode to for synchronization TRGO The combination is as follows 000 Reset the UG bit from the TIM6_EGR register is used as a trigger output TRGO If the reset is generated by the trigger input clock trigger mode controller configured in trigger reset mode the signal on the TRGO is delayed compared to the actual reset 001 Enable the counter enable signal is used as a trigger output TRGO It is used to start several timers at the same time or to control a window in which a slave timer is enabled The counter enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in gated mode When the counter enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode is selected see the MSM bit description in the TIM6_SMCR register 010 Update T
448. owing bits must be kept cleared e LINEN and CLKEN bits in the UART register e SCEN and IREN bits in the UART 5 register This feature is only available in UART1 and UART4 As soon as HDSEL is set e UART is no longer used e UART TX is always released when no data is transmitted Thus it acts as a standard I O in idle or in reception This means that the I O must be configured so that UART TX is configured as floating input or output high open drain when not driven by the UART Apart from this the communications are similar to what is done in normal UART mode The conflicts on the line must be managed by the software by the use of a centralized arbiter for instance In particular the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TEN bit is set Smartcard Smartcard mode is selected by setting the SCEN bit in the UART CR5 register In smartcard mode the following bits must be kept cleared LINEN bit in the register e HDSEL and IREN bits in the UART CR5 register Moreover the CKEN bit may be set in order to provide a clock to the smartcard This feature is only available in UART1 UART2 and UAHTA The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO7816 3 standard The UART should be configured as eight bits plus parity and 1 5 stop bits With Smartcard mode enab
449. pare register 3 high CCR3H 244 18 6 23 Capture compare register low CCR3L 244 19 8 bit basic timer TIM4 6 248 MWOOUCHON eden I eee Pac eed DEG RUE Se 248 192 TIM4 main features 249 19 3 main features 249 19 4 TIM4 TIMG interrupts 249 19 5 TIM4 TIM6 clock selection 249 196 TIM4 TIMG registers 250 19 6 1 Control register 1 TIMx 1 250 19 6 2 Control register 2 TIM6_CR2 251 19 6 3 Slave mode control register 6 251 19 6 4 Interrupt enable register TIMx IER 253 19 6 5 Status register 1 SR 253 19 6 6 Event generation register TIMx EGR 254 19 6 7 Counter TIMx 254 10 462 DoclD14587 Rev 12 Ky RM0016 Contents 19 6 8 Prescaler register 254 19 6 9 Auto reload register TIMx ARR 255 19 6 10 TIM4 TIM6 register map and reset values 255 20 Serial peripheral i
450. pdated at the end of the fifth falling edge During LIN Synch field measurement the UART state machine is stopped and no data is transferred to the data register 2 350 462 DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART d Figure 135 LIN synch field measurement Master clock period Baud Rate period UARTDIV TyAsTER SM Synch Measurement Register 19 bits LIN Break NE LIN Synch Field 7 Start EC Breaky si Bito Y Bit2 Y Bits Y Bits Bite Y Bit7A Stop BF Hf M Bit UARTDIV n y UARTDIV n 1 1 1 Measurement 8 SM TyAsTER UARTDIV Tar TMASTER Rounding SM 128 UARTDIV is an unsigned integer coded in the BRR1 and BRR2 registers as shown in Figure 119 If LASE bit 1 then UARTDIV is automatically updated at the end of each LIN Synch Field Three registers are used internally to manage the auto update of the LIN divider UARTDIV e UARTDIV_NOM nominal value written by software at UART_BRR1 and UART_BRR2 addresses e UARTDIV MEAS results of the Field Synch measurement e UARTDIV used to generate the local baud rate The control and interactions of these registers are explained in Figure 136 and Figure 137 They depend on the LDUM bit setting LIN Divider Update Method As explained in Figur
451. pt subroutines launched at each rising edge of TXE flag In master mode during discontinuous communications there is a 2 CPU clock period delay between the write operation to SPI DR and the BSY bit setting As a consequence in transmit only mode it is mandatory to wait first until TXE is set and then until BSY is reset after having written the last data After transmitting two data in transmit only mode the OVR flag is set in the SPI_SR register since the received data are never read Figure 96 TXE BSY in master transmit only mode BDM 0 and RXONLY 0 Case of continuous transfers Example in master mode with CPOL 1 CPHA 1 MISO MOSI out write SPI DR SCK DATA 1 OxF1 DATA 2 OxF2 DATA 3 OxF3 Te od fs rf e senor ees fos D set by hw 36 MX HL TXE flag Tx Buffer reset by hw BSY a software oftware waits until software waits until writes OxF1 in TXE 1 and writes TXE 1 and writes OxF3 Software waits until software waits until BSY 0 SPI DR xF2 in SPI DR in SPI DR 1 d DoclD14587 Rev 12 267 595 Serial peripheral interface SPI RM0016 Figure 97 TXE BSY in slave transmit only mode BDM 0 and RXONLY 0 Case of continuous transfers Example in slave mode with CPOL 1 CPHA 1 MISO MOSI out TXE flag Tx Buffer write SPI_DR BSY flag DATA 1 OxF1
452. put register Px_IDR Address offset 0x01 Reset value OxXX 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDRO r r r r r r r r Bits 7 0 IDR 7 0 Pin input values The pin register can be used to read the pin value irrespective of whether port is in input or output mode This register is read only 0 Low logic level 1 High logic level Note Px IDH reset value depends on the external circuitry 110 595 DoclD14587 Rev 12 Ly RM0016 General purpose ports GPIO 11 9 3 Port x data direction register Px_DDR Address offset 0x02 Reset value 0x00 7 6 5 4 3 2 1 0 DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDRO rw rw rw rw rw rw rw rw Bits 7 0 DDR 7 0 Data direction bits These bits are set and cleared by software to select input or output mode for a particular pin of a port 0 Input mode 1 Output mode 11 9 4 Port x control register 1 Px CR1 Address offset 0x03 Reset value 0x00 except for PD CR1 which reset value is 0x02 7 6 5 4 3 2 1 0 C17 C16 C15 C14 C13 C12 Ct C10 rw rw rw rw rw rw rw rw Bits 7 0 C1 7 0 Control bits d These bits are set and cleared by software They select different functions in input mode and output mode see Table 21 n input mode DDR 0 0 Floating input 1 Input with pull up In output mode DDR 1 0 Pseudo open drain 1 Push pull slope control for the output depends on the corresponding CR2 bit
453. quency register 2 302 21 7 4 Own address register LSB 2 OARL 303 21 7 55 Own address register MSB I2C OARH 303 21 7 6 Data register IBC DR 304 21 7 7 Status register 1 2 1 305 21 7 8 Status register 2 2 5 2 307 21 7 9 Status register 3 2 308 21 7 10 Interrupt register IC ITR 309 21 7 11 Clock control register low 126 CCRL 310 21 7 12 Clock control register high 126 311 21 7 18 TRISE register 2 313 21 7 14 1 C register map and reset values 314 22 Universal asynchronous receiver transmitter UART 315 ME Cruce 315 22 2 UART main features 316 22 3 UART functional description 317 22 3 1 UART character description 322 22 3 3 323 22 33 BeGelVOr ooi osse A a ERR A 326 22 3 4 High precision baud rate generator 331 22 3 5 Clock deviation tolerance of the UART receiver
454. r and timer B synchronized Timer is the master starts from 0 Timer B is the slave and starts from E7h The prescaler ratio is the same for both timers Timer B stops when timer A is disabled by writing 0 to the CEN bit in the TIMx CR1 register 1 c DU sso Or a Configure timer A master mode to send its output compare 1 reference OC1REF signal as trigger output MMS 100 in the TIMx 2 register Configure the timer A OC1REF waveform TIMx_CCMR1 register Configure timer B to get the input trigger from timer A see TS 2 0 bit definitions in TIMx SMCR register Configure timer B in trigger gated mode SMS 101 in SMCR register Reset timer A by writing 1 in UG bit TIMx EGR register Reset timer B by writing 1 in UG bit TIMx EGR register Initialize timer B to OxE7 by writing E7h in the timer B counter TIMx CNTRL Enable timer B by writing 1 in the CEN bit TIMx CR 1 register Start timer A by writing 1 in the CEN bit TIMx CR1 register Stop timer A by writing 0 in the CEN bit TIMx CR1 register Figure 57 Gating timer B with the counter enable signal of timer A CNT EN uASTER Timer A CEN CNT Timer A UG Timer A CNT 75 X 00 X o1 X 02 Timer B CNT AB X oo X E7 X es X E9
455. r C MCU core Susa Main Voltage Regulator 18y CPU Vig RAM Flash Low Power Voltage Regulator 3V 5 5V Vppio l O buffers d DoclD14587 Rev 12 RM0016 Reset RST 8 8 1 8 2 d Reset RST There are 9 reset sources e External reset through the NRST pin e Power on reset POR Brown out Reset BOR e Independent watchdog reset IWDG e Window watchdog reset WWDG e Software reset e SWIM reset e opcode reset e reset generated if critical registers are corrupted or badly loaded These sources act on the RESET pin and it is always kept low during the delay phase The RESET service routine vector is fixed at address 6000h in the memory map Figure 18 Reset circuit Vpp io Rey typ 45 kQ EXTERNAL RESET Filter SYSTEM NRESET NRST POR BOR RESET PULSE IWDG WWDG SOFTWARE RESET Ie GENERATOR SWIM RESET min 20 us X ILLEGAL OPCODE RESET EMC RESET Reset state and under reset definitions When a reset occurs there is a reset phase from the external pin pull down to the internal reset signal release During this phase the microcontroller sets some hardware configurations before going to the reset vector At the end of this phase most of the registers are configured with their reset state values During the reset phase i e under res
456. r TIM1 17 4 2 17 4 3 d Internal clock source fMASTER If both the clock trigger mode controller and the external trigger input are disabled SMS 000 in TIM1 SMCR and ECE 0 the TIM1 ETR register the CEN DIR and UG bits behave as control bits and can be changed only by software except UG which remains cleared automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock The figure below shows the behavior of the control circuit and the up counter in normal mode without the prescaler Figure 44 Control circuit in normal mode fck psc fyAsTER fMASTER CEN CNT_EN UG CNT_INIT UG synchronized UG or UG 1 clock COUNTER CLOCK CK_CNT CK_PSC COUNTER REGISTER 31 32 33 4 36 36 00 01 02 3 04 05 06 07 External clock source mode 1 The counter can count at each rising or falling edge on a selected timer input This mode is selected when SMS 111 in the TIM1 SMCR register see Figure 45 Figure 45 TI2 external clock connection example SMCR TS 2 0 or 2F A orv TRGO from other timers ory Encoder mode TI1F_ED THFP1 100 External c
457. r which contains the current value to be used is loaded as soon as the LS byte has been written To update the 16 bit prescaler load two bytes in separate write operations starting with the MSB Do not use the LDW instruction for this purpose as it writes the LSB first The new prescaler value is taken into account in the following period after the next counter update event DoclD14587 Rev 12 141 595 16 bit advanced control timer TIM1 0016 17 3 4 142 595 Read operations to the PSCR registers access the preload registers so no special care needs to be taken to read them Up counting mode In up counting mode the counter counts from 0 to a user defined compare value content of the TIM1 ARR register It then restarts from 0 and generates a counter overflow event and a UEV if the UDIS bit is 0 in the TIM1 register Figure 34 shows an example of this counting mode Figure 34 Counter in up counting mode Counter A TIMx_ARR Overflow Overflow Overflow Overflow Time An update event can also be generated by setting the UG bit in the TIM1 EGR register either by software or by using the trigger controller The UEV can be disabled by software by setting the UDIS bit in the TIM1 register This is to avoid updating the shadow registers while writing new values in the preload registers No UEV occurs until the UDIS bit has been written to 0 Note that the counter and the p
458. r 16 bit TIM1_CCRi registers 165 175 2 np t stage essen eer E dex oe gs 166 17 5 3 Inputcapture mode 167 17 5 4 Output stage 169 17 5 5 Forced output 170 17 5 6 Output compare mode 170 175 7 PWM MOUE Sce ris nu tpa E Rr br apu psu va Rs 172 17 5 8 Using the break function 179 17 5 9 Clearing the OCiREF signal an external 182 17 5 10 Encoder interface 183 17 5 UMT interrupts reise F R Rr e eric bias 185 17 7 TIM1 registers 186 17 7 1 Control register 1 TIM1_CR1 186 17 7 2 Control register 2 CR2 188 17 7 8 Slave mode control register 189 17 7 4 External trigger register 190 17 7 5 Interrupt enable register 192 17 7 6 Status register 1 SR1 193 17 7 7 Status register 2 SR2 194 17 7 8 Event generation register TIM
459. r after a programmable time delay 0 AWU Auto wakeup disabled 1 AWU Auto wakeup enabled Bits 3 1 Reserved Bit MSR Measurement enable This bit connects the fj s clock to a timer input capture This allows the timer to be used to measure the LS frequency f s 0 Measurement disabled 1 Measurement enabled Note Refer to the datasheet for information on which timer input capture be connected to the LSI clock in the specific product d DoclD14587 Rev 12 117 462 Auto wakeup AWU 0016 12 4 2 Asynchronous prescaler register AWU Address offset 0x01 Reset value Ox3F 7 6 5 4 3 2 1 0 Reserved APR 5 0 r rw Bits 7 6 Reserved Bits 5 0 APR 5 0 Asynchronous prescaler divider These bits are written by software to select the prescaler divider feeding the counter clock 0x00 APRpy 2 Ox0E APRpy 16 0x01 OxOF APRpiy 17 0x06 APRpiy 8 Ox3E APRpyy 64 Note This register must not be kept at its reset value Ox3F 12 4 3 Timebase selection register AWU TBR Address offset 0x02 Reset value 0x00 Reserved AWUTB S 0 r rw Bits 7 4 Reserved Bits 3 0 AWUTB 3 0 Auto wakeup timebase selection These bits are written by software to define the time interval between AWU interrupts AWU interrupts are enabled when AWUEN 1 0000 No interrupt 0001 APRpiv fLs 0010 2xAPRpiv fLs 0011 22 s
460. r this case you can set the AL bit before entering Low power mode by executing WFI instruction then the interrupt routine returns directly to Low power mode The run time ISR execution is reduced due to the fact that the register context is saved only on the first interrupt As a consequence all the operations can be executed in ISR in very simple applications In more complex ones an interrupt routine may relaunch the main program by simply resetting the AL bit For example an application may need to be woken up by the auto wakeup unit AWU every 50 ms in order to check the status of some pins sensors push buttons Most of the time as these pins are not active the MCU can return to Low power mode without running the main program If one of these pins is active the ISR decides to launch the main program by resetting the AL bit Concurrent and nested interrupt management STM8B devices feature two interrupt management modes e Concurrent mode e Nested mode Concurrent interrupt management mode In this mode all interrupts are interrupt priority level 3 so that none of them can be interrupted except by a TLI RESET or TRAP The hardware priority is given in the following order from the lowest to the highest priority that is MAIN IT4 IT3 IT2 IT1 ITO TRAP TLI same priority and RESET Figure 15 shows an example of concurrent interrupt management mode Figure 15 Concurrent interrupt management
461. r when transmitting The following software sequence is required to clear the TC bit 1 Read from the SR register 2 Write to the UART DR register Figure 116 TC TXE behavior when transmitting Idle preamble Frame 1 Frame 2 Frame 3 TX line set by hardware set by hardware TXE flag cleared by software cleared by software set by hardware USART_DR TC flag set y hardware software software waits until TXE 1 TC is not set TC is not set TC is set because and writes F2 into DR because TXE 0 because TXE 0 TXE 1 j software waits unt TC 1 ai17121d 1 This example assumes that several other transmissions occur after TE has been set Note The TC bit can also be cleared by writing a 0 to it This clear sequence is recommended d only for multibuffer communication DoclD14587 Rev 12 325 462 Universal asynchronous receiver transmitter UART 0016 Note Note 22 3 3 326 462 Break character Setting the SBK bit transmits a break character The break frame length depends on the M bit see Figure 114 If the SBK bit is set to 1 a break character is sent on the UART line after completing the current character transmission This bit is reset by hardware when the break character is completed during the stop bit of the break character The UART inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame
462. ransfer sequencing EV1 EV3 in the following figure When the acknowledge pulse is received e The bit is set by hardware with an interrupt if the ITEVTEN and the ITBUFEN bits are set If TXE is set and a data was not written in the DR register before the end of the next data transmission the BTF bit is set and the interface waits until BTF is cleared by reading the SR1 register and then writing to the DR register stretching SCL low Figure 102 Transfer sequence diagram for slave transmitter T bit slave transmitter S ddress Data A Data2 A DataN NA EV3 EV3 Eva 7 EV3 2 Ev3 1 10 bit slave transmitter EV1 20 Header Data1 A DataN NA P EV1 EV3 1 EV3 EV3 EV3 2 MS37718V1 2 1 Legend S Start S Repeated Start Stop Acknowledge Non acknowledge EVx Event with interrupt if ITEVTEN 1 EV1 ADDR 1 cleared by reading SR1 register followed by reading SR3 EV3 1 TXE 1 shift register empty data register empty write Data1 in DR EV3 TXE 1 shift register not empty data register empty cleared by writing DR EV3 2 AF 1 AF is cleared by writing 0 in AF bit of SR2 register 2 EV1 and EV3 1 events stretch SCL low until the end of the corresponding software sequence 3 EVS software sequence must be performed before the end of the current byte transfer
463. ransmission corruption when disabling the UART or entering Halt mode 3 324 462 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART Single byte communication Clearing the TXE bit is always performed by a write to the data register The TXE bit is set by hardware and it indicates e The data has been moved from TDR to the shift register and the data transmission has started e The TDR register is empty e next data can be written in the DR register without overwriting the previous data This flag generates an interrupt if the TIEN bit is set When a transmission is taking place a write instruction to the UART DR register stores the data in the TDR register The data is copied in the shift register at the end of the current transmission When no transmission is taking place a write instruction to the DR register places the data directly in the shift register the data transmission starts and the TXE bit is immediately set If a frame transmission is complete after the stop bit and the TXE bit is set the TC bit is set An interrupt is generated if the TCIEN is set in the CR2 register After writing the last data in the UART DR register it is mandatory to wait until TC is set to 1 before entering Halt mode or disabling the UART see Figure 116 TC TXE behavio
464. rd length 8 or 9 bits Configurable stop bits Support for 1 or 2 stop bits LIN Master mode UART1 UART2 UART3 and UART4 LIN break and delimiter generation LIN break and delimiter detection with separate flag and interrupt source for readback checking LIN Slave mode UART2 UART3 and UART4 Autonomous header handling and mute mode to filter responses Identifier parity error checking LIN automatic resynchronization allowing operation with internal RC oscillator HSI clock source Break detection at any time even during a byte reception A Header errors detection Delimiter too short Synch field error Deviation error if automatic resynchronization is enabled Framing error in synch field or identifier field Header timeout Transmitter clock output for synchronous communication UART1 UART2 and UART4 IrDA SIR Encoder Decoder UART1 UART2 and UART4 Support for 3 16 bit duration for normal mode Smartcard Emulation Capability UART1 UART2 and UART4 Smartcard interface supporting the asynchronous protocol for Smartcards as defined in ISO 7816 3 standards 1 5 Stop bits for Smartcard operation Single wire Half Duplex Communication UART1 UART4 Separate enable bits for Transmitter and Receiver Transfer detection flags Receive buffer Transmit buffer empty End of Transmission flags Parity control Transmits parity bit Checks parity of received data byte
465. rd mode is not enabled 3 Bits 7 5 have no effect even if Smartcard mode is enabled d DoclD14587 Rev 12 369 462 Universal asynchronous receiver transmitter UART 0016 22 77 13 UART register and reset values Table 61 UART1 register map Register Address 9 7 6 5 4 3 2 1 0 name UART1_SR TXE TC RXNE IDLE OR NF FE PE Reset Value 1 1 0 0 0 0 0 0 UART1 DR DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO 9x Reset Value x x x x x x X X 0x02 UART1_BRR1 UART_DIV 11 4 Reset Value 00000000 0x03 UART1_BRR2 UART_DIV 15 12 UART_DIV 3 0 x Reset Value 0000 0000 0 04 1 CR1 R8 T8 UARTD M WAKE PCEN PS PIEN Reset Value 0 0 0 0 0 0 0 0 Ge UART1_CR2 TIEN TCIEN RIEN ILIEN TEN REN RWU SBK 0x Reset Value 0 0 0 0 0 0 0 0 UART1 LINEN STOP CKEN CPOL CPHA LBCL Reset Value 0 0 00 0 0 0 0 UART1 CR4 LBDIEN LBDL LBDF ADD 3 0 Reset Value 0 0 0 0 0000 bits UART1 CR5 5 HDSEL IRLP IREN d Reset Value 0 0 0 0 0 0 0 0 ox UART1_GTR GT7 GT6 GT5 GT4 GT3 GT2 GT1 GTO Reset Value 0 0 0 0 0 0 0 0 UART1_PSCR PSC7 PSC6 PSC5 5 4 5 5 2 PSC1 PSCO Reset Value 0 0 0 0 0 0 0 0 Table 62 UART2 register map Register Address 9 7 6 5 4 3 2 1 0 name oso UART2 SR TXE TC RXNE IDLE OR NF FE PE Reset Value 1 1 0 0 0 0 0 0 UART2 D
466. re 2 clear enable Bits 6 4 OC2M 2 0 Output compare 2 mode Bit 3 OC2PE Output compare 2 preload enable Bit 2 OC2FE Output compare 2 fast enable Bits 1 0 CC2S 1 0 Capture compare 2 selection This bitfield defines the direction of the channel input output and the used input 00 CC2 channel is configured as output 01 CC2 channel is configured as input IC2 is mapped on 2 2 10 CC2 channel is configured as input IC2 is mapped on TH FP2 11 Reserved Note 25 bits are writable only when the channel is off CC2E and CC2NE 0 and updated in 1 Channel configured in input IC2F 3 0 IC2PSC 1 0 CC2S 1 0 Bits 7 4 IC2F Input capture 2 filter Bits 3 2 IC2PSC 1 0 Input capture 2 prescaler Bits 1 0 CC2S 1 0 Capture compare 2 selection This bitfield defines the direction of the channel input output and the used input 00 CC2 channel is configured as output 01 CC2 channel is configured as input IC2 is mapped on TI2FP2 10 CC2 channel is configured as input IC2 is mapped on TH FP2 11 CC2 channel is configured as input IC2 is mapped on TRC This mode works only if an internal trigger input is selected through the TS bit 1 SMCR register Note CC2S bits are writable only when the channel is off CC2E and CC2NE 0 and updated in 1 d 200 595 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 17 7 11
467. re 76 shows the behavior of the OC and OCi outputs when a COM event occurs for three different examples of programmed configurations 2 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Figure 76 Six step generation COM example OSSR 1 CCRx 4 counter CNT d OC REF Write COMG to 1 Commutation COM 1 Write to 0 1 0 0 110 PWM1 Y OCiM 100 1 OCN CCiE 1 Write CC NE to 1 CCiE 0 0 1 100 forced inactive 101 EXAMPLE 2 I OCN 1 Write and CxNE to 0 CCiE 1 1 0 110 PWM1 Y 100 EXAMPLE 3 OCN 17 5 8 Using the break function The break function is often used in motor control When using the break function the output enable signals and inactive levels are modified according to additional control bits MOE OSSR and OSSI bits in the TIM1_BKR register When exiting from reset the break circuit is disabled and the MOE bit is low The break function is enabled by setting the BKE bit in the TIM1_BKR register The break input polarity can be selected by configuring the BKP bit in the same register BKE and BKP can be modified at the same time Because MOE falling edge can b
468. re 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Ly Programming 2 24 Stacking OF det osx ac o dca ada oce d a Rol dU a S 25 Memory vue etre ee e T ese URS eR RC e 30 Default stack model 31 Customized stack 32 Flash memory and data EEPROM organization on low density STM8S and STM8AF 38 Flash memory and data EEPROM organization on medium density STM8S and STM8AF39 Flash memory and data EEPROM organization high density STM8S and STM8AF 40 UBC area size definition on low density STM8S 41 UBC area size definition on medium density STM8S and STM8AF with up to 32 Kbytes of Flash program 42 UBC area size definition on high density STM8S and STMB8AF with up to 128 Kbytes of Flash program memory 43
469. re compare 3 generation Refer to CC1G description Bit 2 CC2G Capture compare 2 generation Refer to CC1G description Bit 1 CC1G Capture compare 1 generation This bit is set by software to generate an even It is automatically cleared by hardware 0 No action 1 A capture compare event is generated on channel 1 If the CC1 channel is configured in output mode In this case the CC1IF flag is set and the corresponding interrupt request is sent if enabled If the CC1 channel configured in input mode In this case the current value of the counter is captured in the TIMx CCR 1 register The CC1IF flag is set and the corresponding interrupt request is sent if enabled The CC10OF flag is set if the CC1IF flag is already high Bit UG Update generation 232 595 This bit can be set by software it is automatically cleared by hardware 0 No action 1 Re initializes the counter and generates an update of the registers Note that the prescaler counter is also cleared d DoclD14587 Rev 12 RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 6 8 Capture compare mode register 1 TIMx_CCMR1 The channel can be used in input capture mode or in output compare mode The direction of the channel is defined by configuring the 15 bits All the other bits of this register have a different function in input and in output mode For a given bit describes its function when the channel is configured in outpu
470. re than 6 16 37 596 within one bit The sampling clock is resynchronized at each start bit so that when receiving 10 bits one start bit 1 data byte 1 stop bit the clock deviation should not exceed 3 75 DoclD14587 Rev 12 353 462 Universal asynchronous receiver transmitter UART 0016 354 462 UART clock tolerance when unsynchronized When LIN slaves are unsynchronized meaning no characters have been transmitted for a relatively long time the maximum tolerated deviation of the UART clock is 14 If the deviation is within this range then the LIN Break is detected properly when a new reception occurs This is made possible by the fact that masters send 13 low bits for the LIN Break which can be interpreted as 11 low bits 13 bits 14 11 18 by a fast slave and then considered as a LIN Break According to the LIN specification a LIN Break is valid when its duration is greater than 10 This means that the LIN Break must last at least 11 low bits If the period desynchronization of the slave is 14 slave too slow the character 00h which represents a sequence of 9 low bits must not be interpreted as a break character 9 bits 1496 10 26 Consequently a valid LIN break must last at least 11 low bits Clock deviation causes The causes which contribute to the total deviation are e DTRA Deviation due to transmitter error Note the transmitter can be either a master or a slave in c
471. red by software writing 1 0 No WWDG reset occurred 1 An WWDG reset occurred 8 5 RST register map Refer to the corresponding datasheet for the base address Table 13 RST register map Address Register Name 7 6 5 4 3 2 1 0 offset SR SWIMF ILLOPF IWDGF WWDGF 0x00 Reset value x x x x x x x x 76 462 DoclD14587 Rev 12 Ly RM0016 Clock control CLK 9 d Clock control CLK The clock controller is designed to be powerful very robust and at the same time easy to use Its purpose is to allow you to obtain the best performance in your application while at the same time get the full benefit of all the microcontroller s power saving capabilities You can manage all the different clock sources independently and distribute them to the CPU and to the various peripherals Prescalers are available for the master and CPU clocks A safe and glitch free switch mechanism allows you to switch the master clock on the fly from one clock source to another one EMC hardened clock configuration registers To protect the application against spurious write access or system hang up possibly caused by electromagnetic disturbance the most critical CLK registers are implemented as two bitfields that must contain complementary values Mismatches are automatically detected by the CLK triggering an EMC reset and allowing the application to cleanly recover normal operations See
472. registers are in mask mode 1 Low registers are in identifier list mode FMH1 Filter 1 mode high Mode of the high identifier mask registers of Filter 1 0 High registers are in mask mode 1 High registers are in identifier list mode Filter 1 mode low Mode of the low identifier mask registers of filter 1 0 Low registers are in mask mode 1 Low registers are in identifier list mode FMHO Filter 0 mode high Mode of the high identifier mask registers of filter O 0 High registers are in mask mode 1 High registers are in identifier list mode FMLO Filter 0 mode low Mode of the low identifier mask registers of filter 0 0 Low registers are in mask mode 1 Low registers are in identifier list mode DoclD14587 Rev 12 413 462 Controller area network beCAN RM0016 CAN filter mode register 2 CAN_FMR2 Address offset See Table 71 Reset value 0x00 Reserved FMH5 FML5 FMH4 FML4 r rw rw rw rw Bits 7 4 Bit 3 Bits 2 Bit 1 Bit 0 414 462 Reserved FMH5 Filter 5 mode high Mode of the high identifier mask registers of Filter 5 0 High registers are in mask mode 1 High registers are in identifier list mode FMLS5 Filter 5 mode low Mode of the low identifier mask registers of filter 5 0 Low registers are in mask mode 1 Low registers are in identifier list mode FMH4 Filter 4 mode high Mode of the high identifier mask registers of filter 4 0 High registers are
473. rement reset counter 17 5 4 Output stage 2 The output stage generates an intermediate waveform called OCiREF active high which is then used for reference Break functions and polarity act at the end of the chain Figure 67 Channel output stage block diagram Deadti DTG registers me generation m TIM1 CH1 OCIREF J pre P output control P TIMi CH1N OC1N 0O TIM1 CH2 OC2REF 9 output oa From capture compare gt control p TIM1 CH2N channels OC2N m TIM1 CH3 OC3REF 4 DTG gt output 003 control c TIM1 OC3N OC4REF output M OC4 BI BIN Polarity Selection 27 DoclD14587 Rev 12 169 595 16 bit advanced control timer TIM1 0016 17 5 5 17 5 6 170 595 Figure 68 Detailed output stage of channel with complementary output channel 1 ETR 0 TIM1 CH1 utput 0 Enable x0 A gt 1 Circuit 01 id DT Counter gt CCR1 11 Output Mode OCTREF Deadtime TIM1 CCER1 Counter CCR1 Controller Generator V x OC1N DT 11 0 hs 10 Output TIM
474. res 423 ADG PINS s ui OR ee Geek e ees 426 ADC functional description uu vs vad sewed eu ad Ga 426 245 1 ADC on off control 426 24 5 2 COCK Lives sepa ie added oe Wed PARERE PINE 426 24 5 3 Channel selection 427 24 5 4 Conversion modes 427 24 555 Overrun cocer eben er eA Re ER 428 24 5 6 Analog watchdog 429 24 5 7 Conversion on external 430 24 5 8 Analog Zooming 430 24 59 Timing diagram 244 4004 sete desde ves RE Ever Ribes 430 ADC low power 432 ADC 2s auno hir ia ia tod pex ocn aed du pd 432 Data alignment xa oda REF PX Re ERR 435 Reading the conversion result 435 Schmitt trigger disable registers 436 ADC ISEISIBEIS x ex e RT ues 436 24 11 1 ADC data buffer register x high DBxRH 0 7 or 0 9 436 24 11 2 ADC data buffer register x low ADC_DBxRL x or 0 7 or 0 9 437 24 11 3 control status register 438 24 11 4 ADC configuration register 1 1
475. rescaler restart counting from 0 but the prescaler division factor does not change In addition if the URS bit update request selection in the TIM1 CR1 register is set setting the UG bit generates an UEV without setting the UIF flag Consequently no interrupt request is sent This avoids generating both update and capture interrupts when clearing the counter on the capture event When an update event occurs all the registers are updated and the update flag UIF bit in SR1 register is set depending on the URS bit e The auto reload shadow register is updated with the preload value TIM1 ARR e The buffer of the prescaler is reloaded with the preload value content of the TIM1 PSCR register Figure 35 and Figure 36 show two examples of the counter behavior for different clock frequencies when TIM1 ARR 0x36 In Figure 35 the prescaler divider is set to 2 so the counter clock frequency is at half the frequency of the prescaler clock source PSC The auto reload preload is disabled ARPE 0 Consequently the shadow register is immediately changed and counter overflow occurs when upcounting reaches 0x36 This generates a UEV 2 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Figure 35 Counter update when ARPE 0 ARR not preloaded with prescaler 2 ckesc EN CLOCK
476. resent on SCL input path plus delay due to internal SCL input synchronization with I2C Peripheral clock The maximum time used by the feedback loop is programmed in TRISE bits so that the SCL frequency remains stable whatever the SCL rising time Start condition Setting the START bit causes the interface to generate a Start condition and to switch to Master mode MSL bit set when the BUSY bit is cleared In master mode setting the START bit causes the interface to generate a Re Start condition at the end of the current byte transfer Once the Start condition is sent e SB bit is set by hardware an interrupt is generated if the ITEVTEN bit is set Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address Slave address transmission Then the slave address is sent to the SDA line via the internal shift register e n 10 bit addressing mode sending the header sequence causes the following event ADD10 bit is set by hardware and an interrupt is generated if the ITEVTEN bit is set Then the master waits for a read of the SR1 register followed by a write in the DR register with the second address byte see Figure 104 amp Figure 105 Transfer sequencing EV9 The ADDR bit is set by hardware and an interrupt is generated if the ITEVTEN bit is set Then the master waits for a read of the SR1 register followed by a read in the SR3 DoclD14587 Rev 12 28
477. ressing mode bits 9 8 of address BitO Reserved Ly DoclD14587 Rev 12 303 595 Inter integrated circuit 2 interface 0016 21 7 6 Data register 2 DR Address offset 0x06 Reset value 0x00 DR 7 0 rw Bits 7 0 DR 7 0 Data register 1 2 3 Byte received or to be transmitted to the bus Transmitter mode Byte transmission starts automatically when a byte is written in the DR register A continuous transmit stream can be maintained if the next data to be transmitted is put in DR once the transmission is started TXE 1 Receiver mode Received byte is copied into DR RXNE 1 A continuous transmit stream can be maintained if DR is read before the next data is received RXNE 1 1 In slave mode the address is not copied into DR 2 Write collision is not managed DR can be written if TXE 0 3 If an ARLO event occurs on ACK pulse the received byte is not copied into DR and so cannot be read d 304 595 DoclD14587 Rev 12 0016 Inter integrated circuit interface 21 7 7 Status register 1 2 SR1 Address offset 0x07 Reset value 0x00 7 6 5 4 3 2 1 0 TXE RXNE Reserved STOPF ADD10 BTF ADDR SB r r r r r r r r Bit7 TXE Data register empty transmitters 1 0 Data register not empty 1 Data register empty Set when DR is empty in transmission TXE is not set during address phase Cleared by software writing to the DR regi
478. riority over 8 bit filter For filters of equal scale priority is given to the identifier List mode over the identifier Mask mode For filters of equal scale and mode priority is given by the filter number the lower the number the higher the priority Figure 152 Filter banks configured as in the example in Table 65 Message Received Identifier Ctrl Data Filter bank Num Receive FIFO 0 a Identifier d Identifier Identifier Identifier Identifier Identifier Message Stored Identifier 4 Match gt gt N Identifier List Identifier Mask Identifier Mask 15 FMI Filter number stored Identifier in the Filter Match Mask Index field within the eek eL 17 MFMIR register No Match Found Message Discarded Identifier amp Mask The example above shows the filtering principle of the beCAN On reception of a message the identifier is compared first with the filters configured in identifier list mode If there is a match the message is stored in the FIFO and the index of the matching filter is stored in the Filter Match Index As shown in the example the identifier matches with Identifier 4 thus the message content and FMI 4 is stored in the FIFO If there is no match the incoming identifier is then
479. rogram area write unprotection mechanism 4 8 8 Flash status register FLASH_IAPSR Address offset 0x05 Reset value 0x40 7 6 5 4 3 2 1 0 Reserved HVOFF Reserved DUL EOP PUL WR PG DIS res r r rc wO rc wO d Bit7 Reserved Bit 6 HVOFF End of high voltage flag This bit is set and cleared by hardware 0 HV ON start of actual programming 1 HV OFF end of high voltage Bits 5 4 Reserved forced by hardware to 0 Bit 3 DUL Data EEPROM area unlocked flag This bit is set by hardware and cleared by software by programming it to O 0 Data EEPROM area write protection enabled 1 Data EEPROM area write protection has been disabled by writing the correct MASS keys DoclD14587 Rev 12 55 595 Flash program memory and data EEPROM 0016 Bit 2 EOP End of programming write or erase operation flag This bit is set by hardware It is cleared by software by reading the register or when a new write erase operation starts 0 No EOP event occurred 1 An EOP operation occurred An interrupt is generated if the IE bit is set in the FLASH register Bit 1 PUL Flash Program memory unlocked flag This bit is set by hardware and cleared by software by programming it to O 0 Write protection of main Program area enabled 1 Write protection of main Program area has been disabled by writing the correct MASS keys Bit 0 WR PG DIS Write attempted to protected page flag This bit is set by hard
480. roller area network beCAN 0016 23 3 23 3 1 23 3 2 374 462 beCAN general description In today s CAN applications the number of nodes in a network is increasing and often several networks are linked together via gateways Typically the number of messages in the System and thus to be handled by each node has significantly increased In addition to the application messages Network Management and Diagnostic messages have been introduced e Anenhanced filtering mechanism is required to handle each type of message Furthermore application tasks require more CPU time therefore real time constraints caused by message reception have to be reduced e A receive FIFO scheme allows the CPU to be dedicated to application tasks for a long time period without losing messages The standard HLP Higher Layer Protocol based on standard CAN drivers requires an efficient interface to the CAN controller e All mailboxes and registers are organized in 16 byte pages mapped at the same address and selected via a page select register Figure 140 CAN network topology STM8 MCU Applicati pplication 9 S c 2 Z Z lt lt lt O Controller o Transceiver CAN CAN High Low CAN Bus CAN 2 0B active core The beCAN module handles the transmission and the reception of CAN messages fully autonomously Standard identifiers 11 bit a
481. rols Fast Flash wakeup from Halt mode By default the Flash is in power down state when the microcontroller enters Halt mode The current leakage is negligible resulting in very low consumption in Halt mode However the Flash wakeup time is relatively slow several 15 If you need the application to wakeup quickly from Halt mode set the HALT bit in Section 4 8 1 Flash control register 1 FLASH 1 This ensures that the Flash is in Standby mode when the microcontroller enters in Halt mode Its wakeup time is reduced to a few ns However in this case the consumption is increased up to several pAs Refer to the electrical characteristics section of the datasheet for more details Very low Flash consumption in Active halt mode By default in Active halt mode the Flash remains in operating mode to ensure the fastest wakeup time however in this case the power consumption is not optimized To optimize the power consumption you can set the AHALT bit in Flash control register 1 FLASH CR1 This will switch the Flash to power down state when entering Active halt mode The consumption decreases but the wakeup time increases up to a few us DoclD14587 Rev 12 103 462 General purpose ports GPIO 0016 11 11 2 104 595 General purpose ports GPIO Introduction General purpose input output ports are used for data transfers between the chip and the external world An port can contain up to eight pins
482. ror occurs when the interface detects a non acknowledge bit In this case e AF bit is set and an interrupt is generated if the ITERREN bit is set e Atransmitter which receives NACK must reset the communication If slave Lines are released by hardware f master A stop condition or repeated start must be generated by software Arbitration lost ARLO This error occurs when the I2C interface detects an arbitration lost condition In this case ARLO bit is set by hardware and an interrupt is generated if the ITERREN bit is set e 12 interface goes automatically back to slave mode the MSL bit is cleared e When the 2 loses the arbitration it is not able to acknowledge its slave address in the same transfer but it can acknowledge it after a repeated start from the master e Lines are released by hardware 3 DoclD14587 Rev 12 RM0016 Inter integrated circuit PC interface 21 4 4 d Overrun underrun error OVR An Overrun error can occur in slave mode when clock stretching is disabled and the 2 interface is receiving data The interface has received a byte RXNE 1 and the data in DR has not been read before the next byte is received by the interface In this case e last received byte is lost In case of overrun error software should clear the RXNE bit and the transmitter should re transmit the last received byte Underrun error can occur in slave mode when
483. rovided by ST or write your own by initializing the stack pointer with the correct address The stack pointer is decremented after data has been pushed onto the stack and incremented after data is popped from the stack It is up to the application to ensure that the lower limit is not exceeded A subroutine call occupies two or three locations An interrupt occupies nine locations to store all the internal registers except SP For more details refer to Figure 2 WFI HALT instructions save the context in advance If an interrupt occurs while the CPU is in one of these modes the latency is reduced 2 DoclD14587 Rev 12 RM0016 Central processing unit CPU d Figure 2 Stacking order INTERRUPT GENERATION execute pipeline Complete instruction in execute stage 1 6 cycles latency PUSH PCL PUSH PCH PUSH PCE PUSH Y PUSH X PUSH A PUSH CC 9 CPU CYCLES v JUMP TO INTERRUPT ROUTINE GIVEN BY THE INTERRUPT VECTOR PCL PCH STACK PCE YL PUSH YH XL UNSTACK XH POP A INSTRUCTION 1 LdNdy3LN POP CC POP A POP X POP Y POP PCE POP PCH POP PCL 9 CPU CYCLES JUMP TO THE ADDRESS GIVEN BY PROGRAM COUNTER Reload Pipeline Condition code register CC The condition code register is an 8 bit register which indicates the result of the
484. rupt event fla control from from 9 bit wait Halt CSS event CSSD CSSDIE Yes No Master clock switch event SWIF SWIEN Yes No 2 DoclD14587 Rev 12 RM0016 Clock control CLK 9 9 CLK register description 9 9 1 Internal clock register CLK_ICKR Address offset 0x00 Reset value 0x01 7 5 4 3 2 1 0 Reserved REGAH LSIRDY LSIEN FHW HSIRDY HSIEN r rw r rw rw r rw Bits 7 6 Reserved must be kept cleared Bit 5 Bit 4 Bit 3 d REGAH Regulator power off in Active halt mode This bit is set and cleared by software When it is set the main voltage regulator is powered off as soon as the MCU enters Active halt mode so the wakeup time is longer 0 MVR regulator ON in Active halt mode 1 MVR regulator OFF in Active halt mode LSIRDY Low speed internal oscillator ready This bit is set and cleared by hardware 0 LSI clock not ready 1 LSI clock ready LSIEN Low speed internal RC oscillator enable This bit is set and cleared by software It is set by hardware whenever the LSI oscillator is required for example When switching to the LSI clock see CLK SWR register When LSI is selected as the active source see CLK CCOR register When is enabled BEEPEN bit set in the register When LSI measurement is enabled MSR bit set in the register It cannot be cleared when LSI is selected as master clock source CLK CMSR r
485. ry calibrated by ST However it is not possible to perform further trimming When using the independent watchdog with the LSI as clock source in order to guarantee that the CPU will never run on the same clock in case of corruption the LSI clock cannot be the master clock if LS EN option bit is reset Refer to the option bytes section in the datasheet Master clock switching The clock switching feature provides an easy to use fast and secure way for the application to switch from one master clock source to another System startup For fast system startup after a reset the clock controller configures the master clock source as HSI RC clock output divided by 8 HSI 8 This is to take advantage of the short stabilization time of the HSI oscillator The 8 divider is to ensure safe start up in case of poor Vpp conditions Once the master clock is released the user program can switch the master clock to another clock source Master clock switching procedures To switch clock sources you can proceed in one of two ways e Automatic switching e Manual switching Automatic switching The automatic switching enables the user to launch a clock switch with a minimum number of instructions The software can continue doing other operations without taking care of the switch event exact time To enable automatic switching follow the sequence below refer to the flowchart in Figure 22 1 Enable the switching mechanism by setting the S
486. s Update Counter overflow underflow counter initialization by software or internal external trigger Trigger event counter start stop initialization or count by internal external trigger Input capture Output compare Break input d DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 Figure 31 TIM1 general block diagram MASTER DIV TIM1_ETR TRGO to TIM5 TIM6 or to ADC TRGO from other TIM y ER CLOCK TRIGGER CONTROLLER TRC Clock reset enable TIME BASE UNIT Repetition counter CK CNT CK PSC Prescaler F gt UP DOWN COUNTER 34 Auto reload register v CAPTURE COMPARE ARRAY 1 UEV A TIM1_CH1 TH 1 OCIREF I gt Prescaler 5 Capture Compare 1 Register I Oct OCiN 2 TIM1 CH1N IC2 1 2 5 UE TIM1 CH2 2 OC2REI L t Prescaler p Capture Compare 2 Register L OUTPUT 9 TIM1 CH2 INPUT STAGE OC2N CH2N STAGE Pi TIM1_CH3 F OC3REF 3 Prescaler 638 Capture Compare 3 Register I 985 5 TIM1_CH3 OC3N c i ML CH3N TIM1_CH4 TM Ica caps
487. s it makes it possible to update the duty cycle twice per PWM period When refreshing compare registers only once per PWM period in center aligned mode maximum resolution is 2 X ick psc due to the symmetry of the pattern The repetition down counter is an auto reload type the repetition rate of which is maintained as defined by the register value refer to Figure 42 When the UEV is generated by software by setting the UG bit in the TIM1 EGR register or by hardware through the clock trigger controller it occurs immediately irrespective of the value of the repetition down counter The repetition down counter is reloaded with the content of the TIM1 RCR register 2 DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Figure 42 Update rate examples depending on mode and TIM1 RCR register settings Center aligned mode Edge aligned mode Up counting Down counting Counter LU EE TIML_RCR 0 Ua AAAAAAAARAR AAAAARARAR AAAAABABAA TIM1_RCR 1 AE DADA A A 2 A A A A A A A A A A A A 7772 TIM1_RCR 3 A A A A re synchronization by SW by SW by SW UEV A UEV Preload registers transferred to shadow registers and update interrupt generated UEV if the repetition down counter underflow occurs when the counter is equal
488. s calculated as follows fck fck 2 9C RI2 0D The prescaler value is loaded through a preload register The shadow register which contains the current value to be used is loaded as soon as the LS byte has been written Read operations to the TIMx PSCR registers access the preload registers so no special care needs to be taken to read them DoclD14587 Rev 12 249 595 8 bit basic timer TIM4 TIM6 RM0016 19 6 TIM4 TIM6 registers 19 6 1 Control register 1 TIMx_CR1 Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 ARPE Reserved OPM URS UDIS CEN rw r rw rw rw rw Bit 7 ARPE Auto reload preload enable 0 TIM4_ARR register is not buffered through a preload register It can be written directly 1 TIM4_ARR register is buffered through a preload register Bits 6 4 Reserved must be kept cleared Bit 3 OPM One pulse mode 0 Counter is not stopped at update event 1 Counter stops counting at the next update event clearing the CEN bit Bit 2 URS Update request source 0 When enabled an update interrupt request is sent as soon as registers are updated counter overflow 1 When enabled an update interrupt request is sent only when the counter reaches the overflow underflow Bit 1 UDIS Update disable 0 A UEV is generated as soon as a counter overflow occurs or a software update is generated Buffered registers are then loaded with their preload values 1 A UEV is not generated shad
489. s from preload to shadow registers as well as the update interrupt generation rate if the update interrupt is enabled UIE 1 Each time the REP related down counter reaches zero UEV is generated and it restarts counting from the REP value As REP is reloaded with the REP value only at the repetition update event U RC any write to the RCR register is not taken into account until the next repetition update event In PWM mode REP 1 corresponds to number of PWM periods in edge aligned mode number of half PWM periods in center aligned mode d 208 595 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 7 22 Capture compare register 1 high TIM1_CCR1H Address offset 0x15 Reset value 0x00 CCR1 15 8 Bits 7 0 CCR1 15 8 Capture compare 1 value MSB 17 7 23 register 1 low TIM1 CCR1L Address offset 0x16 If the CC1 channel is configured as output CC1S bits in TIM1 CCMH 1 register The value of CCR1 is loaded permanently into the actual capture compare 1 register if the preload feature is enabled OC1PE bit in CCMR1 Otherwise the preload value is copied in the active capture compare 1 register when a UEV occurs The active capture compare register contains the value which is compared to the counter register TIMx and signalled on the OC1 output If the CC1 channel is conf
490. s mode the DR register consists of a buffer TDR between the internal bus and the transmit shift register see Figure 110 Every character is preceded by a start bit which is a logic level low for one bit period The character is terminated by a configurable number of stop bits The following stop bits are supported by UART The TEN bit should not be reset during transmission of data Resetting the TEN bit during the transmission will corrupt the data on the UAHT pin as the baud rate counters will get frozen The current data being transmitted will be lost An idle frame will be sent after the TEN bit is enabled Configurable stop bits The number of stop bits to be transmitted with every character can be programmed in Control register 3 bits 5 4 1 stop bit This is the default value of number of stop bits e 2 Stop bits This is supported by normal mode UART 1 5 Stop bits used Smartcard mode only An idle frame transmission will include the stop bits A break transmission consists of 10 low bits followed by the configured number of stop bits when m 0 and 11 low bits followed by the configured number of stop bits when m 1 It is not possible to transmit long breaks break of length greater than 10 11 low bits In LIN mode see Section 22 3 8 on page 335 a standard 13 bit break is always generated DoclD14587 Rev 12 323 462 Universal asynchronous receiver transmitter UART
491. s off CC3E and CC3NE 0 and updated in TIM1 CCER2 d DoclD14587 Rev 12 201 595 16 bit advanced control timer TIM1 0016 17 7 12 mode register 4 TIM1 4 Address offset OxB Reset value 0x00 Refer to the CCMR1 register description above Channel configured in output 7 6 5 4 3 2 1 0 OC4CE OC4M 2 0 OC4PE OC4FE CCAS 1 0 rw rw rw rw rw rw rw rw Bit 7 OC4CE Output compare 4 clear enable Bits 6 4 OC4M 2 0 Output compare 4 mode Bit 3 OC4PE Output compare 4 preload enable Bit 2 OC4FE Output compare 4 fast enable Bits 1 0 CCAS 1 0 Capture compare 4 selection This bitfield defines the direction of the channel input output and the used input 00 CC4 channel is configured as output 01 CC4 channel is configured as input IC4 is mapped on TI4FP4 10 CC4 channel is configured as input IC4 is mapped on 4 11 Reserved Note CCAS bits are writable only when the channel is off CC4E and CC4NE 0 and updated in CCER2 Channel configured in input IC4F 3 0 IC4PSC 1 0 CC4S 1 0 Bits 7 4 Input capture 4 filter Bits 3 2 IC4PSC 1 0 Input capture 4 prescaler Bits 1 0 CCAS 1 0 Capture compare 4 selection This bitfield defines the direction of the channel input output and the used input 00 CC4 channel is configured as output 01 CC4 channel is configured as input IC4 is mapped on TI4
492. s selected It is cleared by software 0 No trigger event has occurred 1 Trigger interrupt pending Note In TIMZ TIMG this bit is reserved Reserved must be kept cleared CC3IF Capture compare 3 interrupt flag Refer to CC1IF description CC2IF Capture compare 2 interrupt flag Refer to CC1IF description CC1IF Capture compare 1 interrupt flag If channel CC1 is configured as output This flag is set by hardware when the counter matches the compare value It is cleared by software 0 No match 1 The content of the counter TIMx CNT has matched the content of the TIMx CCR 1 register If channel CC1 is configured as input This bit is set by hardware on a capture It is cleared by software or by reading the TIMx CCR1L register 0 No input capture has occurred 1 The counter value has been captured in CCR1 register an edge has been detected on which matches the selected polarity UIF Update interrupt flag This bit is set by hardware on an update event It is cleared by software 0 No update has occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow if UDIS 0 in the TIMx CR1 register When ONT is re initialized by software using the UG bit in TIMx EGR register if URS 0 and UDIS 0 in the TIMx CR1 register 3 DoclD14587 Rev 12 RM0016 16 bit general purpose timers TIM2 TIM3 TIM5 18 6 6 Status register 2 TIMx SR2 Address o
493. s set and cleared by software The parity will be selected after the current byte 0 Even parity 1 Odd parity PIEN Parity interrupt enable This bit is set and cleared by software 0 Parity interrupt disabled 1 Parity interrupt is generated whenever 1 in the SR register Control register 2 UART CR2 Address offset 0x05 Reset value 0x00 TIEN TCIEN RIEN ILIEN TEN REN RWU SBK rw rw rw rw rw rw rw Bit 7 Bit 6 Bit 5 Bit 4 362 462 TIEN Transmitter interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An UART interrupt is generated whenever TXE 1 in the UART_SR register TCIEN Transmission complete interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An UART interrupt is generated whenever TC 1 in the UART_SR register RIEN Receiver interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An UART interrupt is generated whenever OR 1 or RXNE 1 in the UART_SR register ILIEN IDLE Line interrupt enable This bit is set and cleared by software 0 Interrupt is inhibited 1 An UART interrupt is generated whenever IDLE 1 in the UART_SR register d DoclD14587 Rev 12 RM0016 Universal asynchronous receiver transmitter UART Bit 3 Bit 2 Bit 1 Bit 0 QW c TEN Transmitter enable 1 2 This bit enables the transmitter It is set and cleared by
494. sabled Data EEPROM area DATA R WO Option bytes User boot code area UBC P Readout Main program P protection enabled Data EEPROM area DATA SWIM active Option bytes P Wrop ICP mode User boot code area UBC R E Readout Main program R W EO protection disabled Data EEPROM area DATA R WO Option bytes 50 595 DoclD14587 Rev 12 R W E Read write and execute Read and execute write operation forbidden Read write and execute operations forbidden P The area cannot be accessed read execute and write operations forbidden Protected write forbidden except for ROP option byte The Flash program memory is write protected locked until the correct MASS key is written in the FLASH PUKR It is possible to lock the memory again by resetting the PUL bit in the FLASH IAPSR register If incorrect keys are provided the device must be reset and new keys programmed The data memory is write protected locked until the correct MASS key is written in the FLASH DUKR It is possible to lock the memory again by resetting the DUL bit in the IAPSR register If incorrect keys are provided another key program sequence can be performed without resetting the device To program the UBC area the application must first clear the UBC option byte The option bytes are write protected locked until the correct MASS key is written the FLASH with set to 1 It is possible to lock t
495. served Reserved wO rc wO Bit 7 Reserved must be kept cleared Bit6 TIF Trigger interrupt flag This flag is set by hardware on a trigger event the active edge is detected on the TRGI signal both edges are detected if gated mode is selected It is cleared by software 0 No trigger event has occurred 1 Trigger interrupt pending Note In TIM4 this bit is reserved Bits 5 1 Reserved must be kept cleared Bit Update interrupt flag This bit is set by hardware on an update event It is cleared by software 0 No update has occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow if UDIS 0 in the TIMA CR 1 register When CNT is re initialized by software using the UG bit in the TIM4_EGR register if URS 0 and UDIS 0 in the 4 CR1 register d DoclD14587 Rev 12 253 595 8 bit basic timer TIM4 TIM6 RM0016 19 6 6 Event generation register TIMx_EGR Address offset 0x03 or 0x05 TIM4 0x05 TIM6 for TIM4 address see Section 19 6 10 Reset value 0x00 7 6 5 4 3 2 1 0 UG Reserved Reserved Bit 7 Reserved must be kept cleared Bit6 TG Trigger generation This bit is set by software to generate an event It is automatically cleared by hardware 0 No action 1 The TIF flag is set in 6 SR register An interrupt is generated if enabled by the TIE bit Note In TIM4 this bi
496. sie output enabled with inactive state CCiNP Complementary to OC REF 1 1 1 polarity deadtime not OC REF polarity deadtime 0 0 Output disabled not driven by the timer 0 0 x2 x x 1 Off state output enabled with inactive state 1 Asynchronously OCi and Then if the clock is present OC OIS and OISIN after 1 a deadtime assuming that OIS and 5 do not correspond 1 with OC and in active state 1 Never set CCIE CCNiE 0 when the channel is used When the channel is not used program CCiP CCiNP OISi OISIN 0 otherwise 2 Don tcare Note 2 The state of the external I O pins connected to the channels depends on the channel state and the GPIO registers DoclD14587 Rev 12 205 595 16 bit advanced control timer TIM1 RM0016 17 7 14 enable register 2 TIM1_CCER2 Address offset OxXOD Reset value 0x00 Z 6 5 4 3 2 1 0 Reserved CC4E CC3NP CC3NE rw rw rw rw rw rw Bits 7 6 Reserved Bit5 4 output polarity Refer to CC1P description Bit 4 CC4E Capture compare 4 output enable Refer to CC1E description Bit CC3NP Capture compare complementary output polarity Refer to CC1NP description Bit 2 CC3NE Capture compare 3 complementary output enable Refer to CC1NE
497. sing the CC P bits in the TIM1_CCERi registers It can be programmed as active high or active low The OC output is enabled by a combination of CCE MOE 5 OSSR and OSSI bits TIM1_CCER and TIM1 registers Refer to the TIM1 CCERi register descriptions for more details In PWM mode 1 or 2 TIM1 and TIM1_CCRi are always compared to determine whether TIM1_CCRi lt TIM1_CNT TIM1_CNT lt TIM1 CCRi depending on the direction of the counter The timer is able to generate PWM in edge aligned mode or center aligned mode depending on the CMS bits in the TIM1 CR1 register PWM edge aligned mode Up counting configuration Up counting is active when the DIR bit in the TIM1 1 register is low Example This example uses PWM mode 1 The reference PWM signal OC REF is high as long as TIM1 CNT TIM1 Otherwise it becomes low If the compare value in TIM1 CCRiis greater than the auto reload value in TIM1_ARR then OC REF is held at 1 If the compare value is 0 OCiREF is held at 0 Figure 70 shows some edge aligned PWM waveforms in an example where TIM1 ARR 8 2 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 2 Figure 70 Edge aligned counting mode PWM mode 1 waveforms ARR 8 COUNTER REGISTER Y oY Y 2Y s Y sy ey7zy ey oy3y OCiREF CCRx 4 OCiREF 8 OCiREF 1 CCRx
498. smitted or received e writing the last byte to the Txbuffer set the CRCNext bit in the SPI CR2 register to indicate that after transmission of the last byte the CRC should be transmitted The CRC calculation will be frozen during the CRC transmission e After transmitting the last byte the SPI transmits the CRC CRCNext bit is reset The CRC is also received and compared against the SPI RXCRCR value If the value does not match the CRCERR flag in SPI SR is set and an interrupt can be generated when the ERRIE the SPI ICR register is set Note With high bit rate frequencies the user must take care when transmitting As the 3 number of used CPU cycles has to be as low as possible in the CRC transfer phase the calling of software functions in the CRC transmission sequence is forbidden to avoid errors in the last data and CRC reception DoclD14587 Rev 12 271 595 Serial peripheral interface SPI 0016 20 3 7 Note 20 3 8 272 595 Status flags There are three status flags to allow the application to completely monitor the state of the SPI bus Tx buffer empty flag TXE When set this flag indicates that the Tx buffer is empty and that the next data to be transmitted can be loaded into the buffer The TXE flag is reset when writing the SPI DR register Rx buffer not empty RXNE When set this flag indicates that there is a valid received data in the Rx buffer This flag is reset when SPI DR is
499. software 0 Transmitter is disabled 1 Transmitter is enabled REN Receiver enable This bit enables the receiver It is set and cleared by software 0 Receiver is disabled 1 Receiver is enabled and begins searching for a start bit RWU Receiver wakeup UART mode This bit determines if the UART is in mute mode or not It is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized 9 4 LIN slave mode UART2 UART3 UARTA only if bits LINE LSLV are set While LIN is used in slave mode setting the RWU bit allows the detection of Headers only and prevents the reception of any other characters Refer to Mute mode and errors on page 350 In LIN slave mode when RXNE is set the software can not set or clear the RWU bit 0 Receiver in active mode 1 Receiver in mute mode SBK Send break This bit set is used to send break characters It can be set and cleared by software It should be set by software and will be reset by hardware during the stop bit of break 0 No break character is transmitted 1 Break character will be transmitted During transmission 0 pulse on the TEN bit 0 followed by 1 sends a preamble idle line after the current word When TEN is set there is a 1 bit time delay before the transmission starts Before selecting Mute mode by setting the RWU bit the UART must first receive a data byte otherwise it cannot function in Mute mode with wakeup by ldl
500. ss is received from the SDA line and sent to the shift register Then it is compared with the address of the interface OAR1L and OAR2 if ENDUAL 1 or the General Call address if ENGC 1 In 10 bit addressing mode the comparison includes the header sequence 11110 0 where xx denotes the two most significant bits of the address Header or address not matched the interface ignores it and waits for another Start condition Header matched 10 bit mode only the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8 bit slave address Address matched the interface generates in sequence e Anacknowledge pulse if the ACK bit is set e The ADDR bit is set by hardware and an interrupt is generated if the ITEVTEN bit is set In 10 bit mode after receiving the address sequence the slave is always in Receiver mode It will enter Transmitter mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set 11110xx1 The TRA bit indicates whether the slave is in Receiver or Transmitter mode d DoclD14587 Rev 12 RM0016 Inter integrated circuit PC interface Slave transmitter Following the address reception and after clearing ADDR the slave sends bytes from the DR register to the SDA line via the internal shift register The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent see T
501. ssociated to the communication but is simply derived from the internal peripheral input clock through a 5 bit prescaler The division ratio is configured in the prescaler register UART PSCR frequency can be programmed from fuAsTER 2 to fyuaster 62 where faster is the peripheral input clock IrDA SIR ENDEC block IrDA mode is selected by setting the IREN bit in the UART CR5 register The STOP bits in the CR3 register must be configured to 1 stop bit In IrDA mode the following bits must be kept cleared e LINEN STOP and CKEN bits in the UART_CR3 register e SCEN and HDSEL bits in the UART CR5 register This feature is only available in UART1 UART2 and UAHTA The IrDA SIR physical layer specifies use of a Return to Zero Inverted RZI modulation scheme that represents logic 0 as an infrared light pulse see Figure 128 The SIR Transmit encoder modulates the Non Return to Zero NRZ transmit bit stream output from the UART The output pulse stream is transmitted to an external output driver and infrared LED The UART supports only bit rates up to 115 2 kbps for the SIR ENDEC In normal mode the transmitted pulse width is specified as 3 16 of a bit period DoclD14587 Rev 12 Ly RM0016 Universal asynchronous receiver transmitter UART Note 2 1 SIR receive decoder demodulates the return to zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to UAR
502. ster CFG 28 1 3 4 Global configuration register map and reset values 28 2 Boot gt gt gt rrr 29 3 Memory and register 30 3 1 Memory layout 2 30 3 1 1 ses a cad ean 30 3 1 2 Stack handling 31 3 2 Register description abbreviations 33 4 Flash program memory and data EEPROM 34 4 1 IntroductiOn sda Rh AC OA S 34 4 2 GISSA aio ox ROVER toad ee hielo bad dd 34 4 3 Main Flash memory features 35 4 4 Memory organization 36 4 4 1 STM8S and STM8AF memory organization 36 4 4 2 Memory access wait state configuration 40 4 4 3 User boot area UBC 40 4 4 4 Data EEPROM DATA 43 4 4 5 Main program area 43 4 4 6 Option daos De RR AR ea 43 4 5 Memory protection 44 4 5 1 Readout protection 44 4 5 2 Memory access security system MAS
503. ster SPI_DR Address offset 0x04 Reset value 0x00 DR 7 0 rw Bits 7 0 20 4 6 DR 7 0 Data register Byte received or to be transmitted The data register is split into 2 buffers one for writing Transmit buffer and another one for reading Receive buffer A write to the data register will write into the Tx buffer and a read from the data register will return the value held in the Rx buffer SPI CRC polynomial register SPI CRCPR Address offset 0x05 Reset value 0x07 6 5 4 3 2 1 0 CRCPOLY 7 0 rw Bits 7 0 20 4 7 CRCPOLY 7 0 CRC polynomial register This register contains the polynomial for the CRC calculation The CRC polynomial 0x07 is the reset value of this register You can configure an other polynomial as required for your application SPI Rx CRC register SPI RXCRCR Address offset Ox06Reset value 0x00 RxCRC 7 0 r Bits 7 0 2 RXCRC 7 0 Rx CRC Register When CRC calculation is enabled the RxCRC 7 0 bits contain the computed CRC value of the subsequently received bytes This register is reset when the CRCEN bit in SPI CR2 register is written to 1 The CRC is calculated serially using the polynomial programmed in the SPI CRCPR register Note Aread to this register when the BSY Flag is set could return an incorrect value DoclD14587 Rev 12 281 595 Serial peripheral interface SPI RM0016 20 4 8 SPI Tx CRC regist
504. ster capability and controls all 12 bus specific sequencing protocol arbitration and timing It supports standard and fast speed modes 2 main features e Parallel bus I C protocol converter e Multi master capability the same interface can act as Master or Slave e 12 Master features Clock generation Start and Stop generation e 2 Slave features Programmable 12 Address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 KHz Fast speed up to 400 kHz e Status flags Transmitter receiver mode flag End of byte transmission flag PC busy flag e Error flags Arbitration lost condition for master mode Acknowledgement failure after address data transmission Detection of misplaced start or stop condition J Overrun underrun if clock stretching is disabled e 3 types of interrupts 1 communication interrupt 1 error condition interrupt 1 wakeup from Halt interrupt e Wakeup capability MCU wakes up from Low power mode on address detection in slave mode e Optional clock stretching DoclD14587 Rev 12 283 595 Inter integrated circuit 2 interface 0016 21 3 284 595 2 general description In addition to receiving and transmitting data this interface converts it from serial to parallel format and vice versa The interrupts
505. ster or by hardware after a start or a stop condition or when PE 0 Note TXE cannot be cleared by writing the first data in transmission or by writing a data when the BTF bit is set as in both cases the DR register is still empty Bit6 RXNE Data register not empty receivers 2 9 0 Data register empty 1 Data register not empty Set when data register is not empty in receiver mode RXNE is not set during address phase Cleared by software reading or writing the DR register or by hardware when PE 0 Note RXE cannot be cleared by reading a data when the BTF bit is set as the DR register is still full in this case Bit5 Reserved Bit 4 STOPF Stop detection Slave mode 4 5 0 No Stop condition detected 1 Stop condition detected Set by hardware when a Stop condition is detected on the bus by the slave after an acknowledge if ACK 1 Cleared by software reading the SR1 register followed by a write in the CR2 register or by hardware when PE 0 Bit 3 ADD10 10 bit header sent Master mode 6 d 0 No ADD10 event occurred 1 Master has sent first address byte header Set by hardware when the master has sent the first byte in 10 bit address mode Cleared by software reading the SR1 register followed by a write in the DR register of the second address byte or by hardware when PE 0 DoclD14587 Rev 12 305 595 Inter integrated circuit 2 interface 0016 Bit2 Byte
506. t 0x02 Reset value 0x00 6 5 4 3 2 1 0 UART DIV 11 4 rw rw rw rw rw rw Bits 7 0 UART_DIV 11 4 UART_DIV bits 1 These 8 bits define the 2nd and 3rd nibbles of the 16 bit UART divider UART_DIV 1 00h means UART clock is disabled 360 462 2 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART 22 7 4 Baud rate register 2 UART BRR2 Address offset 0x03 Reset value 0x00 7 6 5 4 3 2 1 0 UART DIV 15 12 UART DIV 3 0 rw rw rw rw rw rw rw rw Bits 7 4 UART_DIV 15 12 MSB of UART_DIV These 4 bits define the MSB of the UART Divider UART_DIV Bits 3 0 UART_DIV 3 0 LSB of UART DIV These 4 bits define the LSB of the UART Divider UART_DIV 22 7 5 Control register 1 UART CR1 Address offset 0x04 Reset value 0x00 7 6 5 4 3 2 1 0 R8 T8 UARTD M WAKE PCEN PS PIEN rw rw rw rw rw rw rw rw Bit 7 R8 Receive Data bit 8 This bit is used to store the 9th bit of the received word when M 1 Bit6 T8 Transmit data bit 8 This bit is used to store the 9th bit of the transmitted word when M 1 Bit 5 UARTD UART Disable for low power consumption When this bit is set the UART prescaler and outputs are stopped at the end of the current byte transfer in order to reduce power consumption This bit is set and cleared by software 0 UART enabled 1 UART prescaler and outputs disabled Bit 4 M word length
507. t rS eati odisea E d ebbe Tas 125 14 81 Keyregister KR 125 14 8 2 Prescaler register IWDG PR 125 14 3 3 Reload register IDG 126 14 8 K8 IWDG register map and reset values 126 15 Window watchdog 127 Jntroductloho 225254 ta RC ed ot eris 127 152 WWDG main features 127 15 3 WWDOG functional description 127 15 4 Howto program the watchdog 129 15 5 WWDG low power modes 130 15 6 Hardware watchdog 131 15 7 Using Halt mode with the WWDG WWDGHALT option 131 15 8 WWDG interrupts 131 15 9 WWODG registers issue RR RR RR RR RE ERG cee 131 15 9 1 Control register WWDG CR 131 15 9 2 Window register WDG WR 132 15 10 Window watchdog register map and reset values 132 16 Timer 4 553 x uod aded md e e Franca ag das EEE G 133 16 1 Timer feature comparison 134 16 2 Glossary of timer signal names
508. t the interrupt is latched and remains pending e External interrupts External interrupts can be used to wake up the MCU from Halt mode The device sensitivity to external interrupts can be selected by software through the External Interrupt Control registers CRx When several input pins connected to the same interrupt line are selected simultaneously they are logically ORed When external level triggered interrupts are latched if the given level is still present at the end of the interrupt routine the interrupt remains activated except if it has been inactivated in the routine e Peripheral interrupts Most peripheral interrupts cause the MCU to wake up from Halt mode See the interrupt vector table in the datasheet A peripheral interrupt occurs when a specific flag is set in the peripheral status register and the corresponding enable bit is set in the peripheral control register The standard sequence for clearing a peripheral interrupt performs an access to the status register followed by a read or write to an associated register The clearing sequence resets the internal latch A pending interrupt that is an interrupt waiting to be serviced is therefore lost when the clear sequence is executed Interrupts and low power modes All interrupts allow the processor to exit from Wait mode Only external and other specific interrupts allow the processor to exit from Halt and Active halt mode see wakeup from halt and
509. t and describes its function when the channel is configured in input Therefore be aware that the same bit can have a different meaning for the input stage and for the output stage Address offset 0x05 or 0x07 TIM2 0x05 TIM3 0x07 TIM5 for TIM2 address see Section Reset value 0x00 Channel configured in output 7 5 2 Reserved 1 2 0 1 Reserved CC1S 1 0 r rw r Bit 7 Reserved Bits 6 4 OC1M 2 0 Output compare 1 mode 3 These bits defines the behavior of the output reference signal OC1REF from which OC1 is derived OC1REF is active high whereas OC1 active level depends on the CC1P bit 000 Frozen The comparison between the output compare register TIMx CCR1 and the counter CNT has no effect on the outputs 001 Set channel 1 to active level on match OC1REF signal is forced high when the counter matches the capture compare register 1 TIMx CCR1 010 Set channel 1 to inactive level on match OC1REF signal is forced low when the counter matches the capture compare register 1 TIMx CCR1 011 Toggle OC1REF toggles when TIMx CCR1 100 Force inactive level OC1REF is forced low 101 Force active level OC1REF is forced high 110 PWM mode 1 In up counting channel 1 is active as long as CNT TIMx CCR1 Otherwise channel 1 is inactive In down counting channel 1
510. t available for UARTS 2 368 462 DoclD14587 Rev 12 0016 Universal asynchronous receiver transmitter UART 22 7 12 Prescaler register UART PSCR Address offset 0 0 UART1 0x0B UART2 and UART4 Reset value 0x00 Note Care must be taken to program this register with correct value when both Smartcard and IrDA interfaces are used in the application PSC 7 0 Bits 7 0 PSC 7 0 Prescaler value In IrDA Low Power mode PSC 7 0 IrDA Low Power Baud Rate 1 Used for programming the prescaler for dividing the system clock to achieve the low power frequency The source clock is divided by the value given in the register 8 significant bits 0000 0000 Reserved do not program this value 0000 0001 divides the source clock by 1 0000 0010 divides the source clock by 2 In Smartcard mode PSC 4 0 Prescaler value 2 9 Used for programming the prescaler for dividing the system clock to provide the smartcard clock The value given in the register 5 significant bits is multiplied by 2 to give the division factor of the source clock frequency 0 0000 Reserved do not program this value 0 0001 divides the source clock by 2 0 0010 divides the source clock by 4 0 0011 divides the source clock by 6 Note These bits are not available for 1 This prescaler setting has no effect if IrDA mode is not enabled 2 This prescaler setting has no effect if Smartca
511. t controller ITC 0016 Note 6 2 2 60 595 1 1 The highest software priority interrupt is serviced 2 If several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first When an interrupt request is not serviced immediately it is latched and then processed when its software priority combined with the hardware priority becomes the highest one The hardware priority is exclusive while the software one is not This allows the previous process to succeed with only one interrupt RESET TLI and TRAP are considered as having the highest software priority in the decision process See Figure 14 for a description of pending interrupt servicing process Figure 14 Priority decision process PENDING INTERRUPTS Different HIGHEST SOFTWARE PRIORITY SERVICED SOFTWARE PRIORITY HIGHEST HARDWARE PRIORITY SERVICED Interrupt sources Two interrupt source types are managed by the STM8 interrupt controller e Non maskable interrupts RESET TLI and TRAP e Maskable interrupts external interrupts or interrupts issued by internal peripherals Non maskable interrupt sources Non maskable interrupt sources are processed regardless of the state of bits 11 and IO of the CCR register see Figure 13 PC X Y A and CCR registers are stacked only when a TRAP d DoclD14587 Rev 12 0016 Interrupt con
512. t interrupt sources can also be generated by software using the corresponding bits in the TIM1 EGR register DoclD14587 Rev 12 185 595 16 bit advanced control timer TIM1 0016 17 7 TIM1 registers 17 7 1 Control register 1 TIM1 CR1 Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 ARPE CMS 1 0 DIR OPM URS UDIS CEN nw rw nw rw nw nw nw nw Bit 7 ARPE Auto reload preload enable 0 TIM1 ARR register is not buffered through a preload register It can be written directly 1 TIM1 ARR register is buffered through a preload register Bits 6 5 CMS 1 0 Center aligned mode selection 00 Edge aligned mode The counter counts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and down alternately Output compare interrupt flags of channels configured in output 5 00 in TIM1 CCMRi registers are set only when the counter is counting down 10 Center aligned mode 2 The counter counts up and down alternately Output compare interrupt flags of channels configured in output 00 in CCMRi registers are set only when the counter is counting up 11 Center aligned mode 3 The counter counts up and down alternately Output compare interrupt flags of channels configured in output CC S 00 in TIM1 CCMRi registers are set both when the counter is counting up and down Note It is not allowed to switch from edge aligned mode to center aligned m
513. t is reserved Bits 5 1 Reserved must be kept cleared Bit UG Update generation This bit can be set by software it is automatically cleared by hardware 0 No action 1 Re initializes the counter and generates an update of the registers Note that the prescaler counter is also cleared 19 6 7 Counter TIMx_CNTR Address offset 0x04 or 0x06 TIM4 0x06 TIM6 for TIM4 address see Section 19 6 10 Reset value 0x00 7 6 5 4 3 2 1 0 CNT 7 0 Bits 7 0 CNT 7 0 Counter value 19 6 8 Prescaler register TIMx PSCR Address offset 0x05 or 0x07 TIM4 0x07 TIM6 for TIM4 address see Section 19 6 10 Reset value 0x00 7 6 5 4 3 2 1 0 PSC 2 0 Reserved rw rw rw Bits 7 3 Reserved must be kept cleared Bits 2 0 PSC 2 0 Prescaler value The prescaler value divides the CK_PSC clock frequency The counter clock frequency fox is equal to 2 PSC 2 0 PSC contains the value which is loaded into the active prescaler register at each UEV including when the counter is cleared through the UG bit of 4 EGR Consequently a UEV must be generated so that a new prescaler value can be taken into account 254 595 DoclD14587 Rev 12 Ly RM0016 8 bit basic timer TIM4 TIM6 19 6 9 Auto reload register TIMx_ARR Address offset 0x06 or 0x08 TIM4 0x08 TIM6 for TIM4 address
514. t trigger enabled 1 Schmitt trigger disabled d DoclD14587 Rev 12 443 462 Analog digital converter ADC RM0016 24 11 11 ADC high threshold register high ADC_HTRH Address offset 0x28 Reset value OxFF 7 6 5 4 3 2 0 HT 9 2 rw rw rw rw rw rw rw Note This register is not available for ADC2 Bits 7 0 HT 9 2 Analog Watchdog High Voltage threshold MSB These bits set and cleared by software They define the MSB of the high threshold for the Analog Watchdog 24 11 12 ADC high threshold register low ADC_HTRL Address offset 0x29 Reset value 0x03 7 6 5 4 3 2 0 Reserved HT 1 0 r rw Note This register is not available for ADC2 Bits 7 2 Reserved must be kept cleared Bits 1 0 HT 1 0 Analog watchdog high voltage threshold LSB These bits are set and cleared by software They define the LSB of the high threshold for the Analog Watchdog 444 462 DoclD14587 Rev 12 Ly 0016 Analog digital converter ADC 24 11 13 ADC low threshold register high ADC LTRH Address offset Ox2A Reset value 0x00 7 6 5 4 3 2 1 0 LT 9 2 rw rw rw rw rw rw rw rw Note This register is not available for ADC2 Bits 7 0 LT 9 2 Analog watchdog low voltage threshold MSB These bits are set and cleared by software They define the MSB of the low Threshold for the Analog Watchdog
515. t up as push pull fast slope for optimal operation 11 8 2 Slope control d The maximum frequency that can be applied to an I O can be controlled by software using the CR2 bit Low frequency operation with improved EMC behavior is selected at reset Higher frequency up to 10 MHz can be selected if needed This feature can be applied in either open drain or push pull output mode on I O ports of output type or O4 Refer to the pin description tables in the datasheets for the specific output type information for each pin DoclD14587 Rev 12 109 595 General purpose ports GPIO 0016 11 9 GPIO registers The bit of each port register drives the corresponding pin of the port 11 9 1 Port x output data register Px ODR Address offset 0x00 Reset value 0x00 7 6 5 4 3 2 1 0 ODR7 ODR6 ODRS5 ODR4 ODR3 ODR2 ODR1 ODRO rw rw rw rw rw rw rw rw Bits 7 0 ODR 7 0 Output data register bits Writing to the ODR register when in output mode applies a digital value to the I O through the latch Reading the ODR returns the previously latched value in the register In Input mode writing in the ODR register latches the value in the register but does not change the pin state The ODR register is always cleared after reset Bit read modify write instructions BSET BRST can be used on the DR register to drive an individual pin without affecting the others 11 9 2 Port x pin in
516. tabilization time in the HSECNT option byte please refer to option bytes section in the datasheet The HSERDY flag in the External clock register indicates if the high speed external oscillator is stable or not At startup the clock is not released until this bit is set by hardware The HSE Crystal can be switched on and off using the HSEEN bit in the External clock register CLK ECKR External source HSE user ext In this mode an external clock source must be provided It can have a frequency of up to 24 MHz You select this mode by programming the EXTCLK option bit Refer to the option bytes section of the datasheet The external clock signal square sinus or triangle with 50 duty cycle has to drive the OSCIN pin while the OSCOUT pin is available as standard see Figure 20 For clock frequencies above 16 MHz Flash data EEPROM access must be configured for 1 wait state This is enabled by the device option byte Refer to the datasheet option byte section HSI The HSI clock signal is generated from an internal 16 MHz RC oscillator together with programmable divider factor 1 to 8 This is programmed in the Clock divider register CLK CKDIVR At startup the master clock source is automatically selected as HSI RC clock output divided by 8 8 The HSI RC oscillator has the advantage of providing a 16 MHz master clock source with 5096 duty cycle at low cost no external components It also
517. te at the end of total address phase It is also cleared by hardware after detection of Stop condition STOPF 1 repeated Start condition loss of bus arbitration ARLO 1 or when PE 0 BUSY Bus busy 0 No communication on the bus 1 Communication ongoing on the bus Set by hardware on detection of SDA or SCL low cleared by hardware on detection of a Stop condition It indicates a communication in progress on the bus This information is still updated when the interface is disabled PE 0 MSL Master Slave 0 Slave mode 1 Master mode Set by hardware as soon as the interface is in Master mode SB 1 Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration ARLO 1 or by hardware when PE 0 Reading 2 SR3 after reading 2 SH1 clears the ADDR flag even if the ADDR flag was set after reading 2 SH1 Consequently 2 SH3 must be read only when ADDR is found set in 2 SH1 or when the STOPF bit is cleared 2 DoclD14587 Rev 12 RM0016 Inter integrated circuit PC interface 21 7 10 Interrupt register I2C ITR Address offset 0 0 Reset value 0x00 6 5 4 3 2 1 0 Reserved ITBUFEN ITEVTEN ITERREN r rw rw rw Bits 7 3 Bit 2 Bit 1 Bit 0 d Reserved ITBUFEN Buffer interrupt enable 0 TXE 1 or RXNE 1 does not generate any interrupt 1 TXE 1 or RXNE 1 generates Event interrupt ITEVTEN
518. tem detection This bit is set by hardware and cleared by software writing 0 0 CSS is off or no HSE crystal clock disturbance detected 1 HSE crystal clock disturbance detected Bit 2 CSSDIE Clock security system detection interrupt enable This bit is set and cleared by software 0 Clock security system interrupt disabled 1 Clock security system interrupt enabled Bit 1 AUX Auxiliary oscillator connected to master clock This bit is set and cleared by hardware 0 Auxiliary oscillator is off 1 Auxiliary oscillator HSI 8 is on and selected as current clock master source Bit CSSEN Clock security system enable This bit can be read many times and be written once only by software 0 Clock security system off 1 Clock security system on 96 462 DoclD14587 Rev 12 Ly 0016 Clock control CLK 9 9 10 Configurable clock output register CCOR Address offset 0x09 Reset value 0x00 7 6 5 4 3 1 0 Reserved CCOBSY CCORDY CCOSEL 3 0 CCOEN r r r rw rw rw rw Bit 7 Reserved must be kept cleared Bit 6 CCOBSY Configurable clock output busy This bit is set and cleared by hardware It indicates that the selected CCO clock source is being switched on and stabilized While CCOBSY is set the CCOSEL bits are write protected CCOBSY remains set until the CCO clock is enabled 0 CCO clock not busy 1 CCO clock busy Bit 5 CCORDY Configurable clock output ready This bit is set and cleared
519. ter is reloaded so that the next period is the expected one the counter is loaded with the new value Below are some examples of the counter behavior for different clock frequencies d DoclD14587 Rev 12 0016 16 bit advanced control timer TIM1 Figure 41 Counter timing diagram fck psc ARR 06h ARPE 1 CK PSC EN TIMER CLOCK CK CONT COUNTER REGISTER 04 3 02 01 0 0102 3 04 05 06 05 04 03 COUNTER UNDERFLOW COUNTER OVERFLOW UPDATE EVENT UEV UPDATE INTERRUPT FLAG UIF AUTO RELOAD PRELOAD REGISTER FD 06 AUTO RELOAD SHADOW REGISTER FD 06 Write a new value in TIMx ARR New value transferred in shadow register on update event Hints on using center aligned mode e When starting in center aligned mode the current up down configuration is used It means that the counter starts counting up or down depending on the value written in the DIR bit in the TIM1 CR1 register Moreover the DIR and CMS bits must not be changed at the same time by the software e Writing to the counter while running in center aligned mode is not recommended as it can lead to unexpected results In particular The direction is not updated if a valu
520. terrupt can be generated if TXIE bit in the SPI ICR register is set Note The software must ensure that TXE flag is set to 1 before attempting to write into the Tx 2 buffer Otherwise it will overwrite the data which was previously written in the Tx buffer The RXNE flag Rx buffer not empty is set on the last sampling clock edge when the data is transferred from the shift register to the Rx buffer It indicates that a data is ready to be read from the SPI DR register An interrupt can be generated if RXIE bit in the SPI ICR register is set Clearing the RXNE bit is performed by reading the SPI DR register In some configurations the BSY flag can be used during the last data transfer to wait until the completion of the transfer Full Duplex Transmit and receive procedure in master or slave mode BDM 0 and RXONLY 0 1 Enable the SPI by setting the SPE bit 2 Write the first data to be transmitted in the SPI DR register this clears the flag 3 Wait until 1 and write the second data to be transmitted Then wait until RXNE 1 and read the SPI DR to get the first received data this clears the RXNE bit Repeat this operation for each data to be transmitted received until the n 1 received data 4 until RXNE 1 and read the last received data 5 Wait until 1 and then wait until BSY 0 before disabling the SPI This procedure can also be implemented using dedicated interrupt subroutines launched at
521. the next byte must be transmitted The same byte will be sent again Write Collision not managed DoclD14587 Rev 12 297 595 Inter integrated circuit 2 interface 0016 21 5 21 6 298 595 2 low power modes Table 48 I C interface behavior in low power modes Mode Wait Description No effect on interface 2 interrupts cause the device to exit from Wait mode Halt In slave mode Communication is reset except for configuration registers Device is in slave mode Wakeup from Halt interrupt is generated if ITEVTEN 1 and address matched including allowed headers The matched address is not acknowledged in Halt mode so the master has to send it again when the CPU is woken up to receive an acknowledge If NOSTRETCH 0 SCLH will be stretched after acknowledge pulse in Halt mode until WUFH is cleared by software None of the flags are set by the address which wakes up the CPU In master mode Communication is frozen until the CPU is woken up Wakeup from Halt flag and interrupt are generated if ITEVTEN 1 and there is HALT instruction going Note It is forbidden to enter Halt mode while a communication is on interrupts Table 49 I C Interrupt requests Enable Exit Exit Event Interrupt event fla control from from g bit Wait Halt Start bit sent Master SB Address sent Master or Address matched ADDR Slave 10 bit header sent
522. the CAN_EIER is enabled Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_EIER register is set This bit is cleared by software writing 1 Bit 1 SLAK Sleep Acknowledge This bit is set by hardware and indicates to the software that the CAN hardware is now in sleep mode This bit acknowledges the sleep mode request from the software set SLEEP bit in CAN_MCR register This bit is cleared by hardware when the CAN hardware has exited Sleep mode Sleep mode is exited when the SLEEP bit in the CAN_MCR register is cleared Please refer to the AWUM bit of the CAN_MCR register description for detailed information for clearing SLEEP bit Bit0 INAK Initialization Acknowledge This bit is set by hardware and indicates to the software that the CAN hardware is now in initialization mode This bit acknowledges the initialization request from the software set INRQ bit in CAN MCR register This bit is cleared by hardware when the CAN hardware has exited initialization mode and is now synchronized on the CAN bus To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal 23 11 3 CAN transmit status register CAN TSR Address offset 0x02 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved TXOK2 TXOK1 TXOKO Reserved RQCP2 RQCP1 RQCPO r r r r r rc w1 rc w1 rc w1 Bit 7 Reserved Bit6 TXOK2 Transmission OK for mailbox 2 This bit is set by hardware when the tra
523. the last byte of the target block is loaded the programming starts automatically It is preceded by an automatic erase operation of the whole block When programming a block in DATA area the application can check the HVOFF bit in the Flash status register FLASH IAPSR As soon the HVOFF flag is reset the actual programming phase starts and the application can return to main program memory The EOP and the WR PG DIS control flags of the FLASH IAPSR together with the Flash interrupt can be used to determine if the operation has been correctly completed Fast block programming Fast block programming allows programming without first erasing the memory contents Fast block programming is therefore twice as fast as standard programming This mode is intended only for programming parts that have already been erased It is very useful for programming blank parts with the complete application code as the time saving is significant Fast block programming is performed by using the same sequence as standard block programming To enable fast block programming mode the FPRG NFPRG bits of the FLASH CR2 and FLASH NCR2 registers must be previously set cleared DoclD14587 Rev 12 Ly RM0016 Flash program memory and data EEPROM Caution 4 6 5 4 7 d The HVOFF flag can also be polled by the application which can execute other instructions RWW during the actual programming phase of the DATA The EOP and WR PG DIS bits of the FLA
524. ther measure fcpy can be reduced by writing to the CPUDIV 2 0 bits in the Clock divider register CLK CKDIVR This reduces the speed of the CPU and consequently the power consumption of the MCU The other peripherals clocked by faster are not affected by this setting To return to full speed at any time in Run mode clear the CPUDIV 2 0 bits Peripheral clock gating For additional power saving you can use peripheral clock gating PCG This can be done at any time by selectively enabling or disabling the clock connection to individual peripherals Refer to the Clock control CLK section These settings are effective in both Run and Wait modes 10 2 Low power modes The main characteristics of the four low power modes are summarized in Table 20 Table 20 Low power mode management Mode consumption Main voltage Oscillators CPU Peripherals Wakeup trigger regulator event level All internal interrupts Wait On On off Ont including AWU or external interrupts reset ai Off 3 Active halt On except LSI or off Only AWU2 AWU or external interrupts reset HSE Active halt with Off 3 Off 2 AWU or external MVR auto power off low power except LSI only Off Only AWU interrupts reset regulator on Off 3 j Halt low power Off Off oft External interrupts reset regulator on 1 If the peripheral clock is not disabled by peripheral clock gating function 2 If activated BEEP or IWDG stay switc
525. tinuous conversion mode the ADC starts another conversion as soon as it finishes one This mode is started by setting the ADON bit in the ADC_CR1 register while the CONT bit is set e f buffering is not enabled DBUF bit 0 in the register the converted data is stored in the DR register the EOC End of Conversion flag is set An interrupt is generated if the EOCIE bit is set Then a new conversion starts automatically e f buffering is enabled DBUF bit 21 the data buffer is filled with the results of 8 or 10 consecutive conversions performed on a single channel When the buffer is full the EOC End of Conversion flag is set and an interrupt is generated if the EOCIE bit is set Then a new set of 8 or 10 conversions starts automatically The OVR flag is set if one of the data buffer registers is overwritten before it has been read see Section 24 5 5 To stop continuous conversion reset the CONT bit to stop conversion or reset the ADON bit to power off the ADC Single scan mode This mode is used to convert a sequence of analog channels from AINO to AINn where n is the channel number defined by the CH 3 0 bits in the ADC_CSR register During the scan conversion sequence the CH 3 0 bits are updated by hardware and contain the channel number currently being converted Single scan mode is started by setting the ADON bit while the SCAN bit is set and the CONT bit is cleared DoclD14587 Rev 12 427 462
526. tion in Table 11 Dedicated interrupt instruction set Removed note 3 in Section 6 2 1 Servicing pending interrupts Removed case of TRAP interruption by in Section 6 2 2 Interrupt sources DoclD14587 Rev 12 Ly RM0016 Revision history Table 79 Document revision history continued Date 31 Jan 2011 Revision Changes Removed Halt mode and HALT instruction from Section 6 4 Activation level low power mode control Section 11 General purpose ports GPIO Added note Figure 24 GPIO block diagram Removed warning note in Section 11 3 Port configuration and usage Updated Table 21 I O port configuration summary Updated Section 11 4 Reset configuration Updated unused I O pin status in Section 11 5 Unused I O pins Added TLI masking in Section 11 7 2 Interrupt capability Updated Section 11 7 3 Analog channels Updated Section 11 8 2 Slope control Changed reset value of Px IDR to OxXX in Section 11 9 2 Port x pin input register Px IDR Specified CR1 reset value in Section 11 9 4 Port x control register 1 Section 12 Auto wakeup Modified Step 5 in Section 12 3 1 AWU operation Section 17 16 bit advanced control timer TIM1 Modified Figure 71 Center aligned PWM waveforms ARR 8 Changed to faster in Figure 31 TIM1 general block diagram
527. to the RDR e An interrupt is generated if the RIEN bit is set e The error flags can be set if a frame error noise or an overrun error has been detected during reception e Clearing the RXNE bit is performed by a software read to the UART DR register The RXNE flag can also be cleared by writing a zero to it The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error The REN bit should not be reset while receiving data If the REN bit is disabled during reception the reception of the current byte will be aborted Break character When a break character is received the UART handles it as a framing error Idle character When an idle frame is detected there is the same procedure as a data received character plus an interrupt if the ILIEN bit is set Overrun error An overrun error occurs when a character is received when RXNE has not been reset Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared When an overrun error occurs e bit is set e The RDR content will not be lost The previous data is available when a read to UART DR is performed e shift register will be overwritten The second data received during overrun is lost e An interrupt is generated if the RIEN bit is set e OR bit is reset by a read to the UART SR register followed by a DR register read operation Noise error
528. transfer finished 7 8 0 Data byte transfer not done 1 Data byte transfer succeeded Set by hardware when NOSTRETCH 0 and In reception when a new byte is received including ACK pulse and DR has not been read yet RXNE 1 In transmission when new byte should be sent and DR has not been written yet TXE 1 Cleared by software reading SR1 followed by either a read or write in the DR register or by hardware after a start or a stop condition in transmission or when 0 Bit 1 ADDR Address sent master mode matched slave mode 99 This bit is cleared by software reading SR1 register followed reading SR3 or by hardware when 0 Address matched Slave 0 Address mismatched or not received 1 Received address matched Set by hardware as soon as the received slave address matched with the OAR registers content or a general call or a SMBus is recognized when enabled depending on configuration Address sent Master 0 No end of address transmission 1 End of address transmission For 10 bit addressing the bit is set after the ACK of the 2nd byte For 7 bit addressing the bit is set after the ACK of the byte Note ADDR is not set after a NACK reception Bit 0 SB Start bit Master mode 8 0 No Start condition 1 Start condition generated Set when a Start condition generated Cleared by software by reading the SR1 register followed by writing the DR register or by hardware whe
529. trigger output MMS 100 in the 2 register 2 Configure the timer A OC1REF waveform TIMx CCMR1 register 3 Configure timer B to get the input trigger from timer A see TS 2 0 bit definitions in TIMx SMCR register 4 Configure timer B in trigger gated mode SMS 101 in TIMx SMCR register 5 Enable timer B by writing 1 in the CEN bit TIMx CR1 register 6 Start timer A by writing 1 in the CEN bit TIMx CR1 register The counter 2 clock is not synchronized with counter 1 This mode only affects the timer B counter enable signal Figure 56 Gating timer B with OC1REF of timer A fMASTER Timer A OC1REF Timer A CNT X rc eo X re X r Kilo X o y Timer B CNT 3045 X 3046 X 307 Y 3048 Timer B TIF S Write TIF 0 In Figure 56 the timer B counter and prescaler are initialized before being started Therefore they start counting from their current value It is possible to start from a given value by resetting both timers before starting timer A In this case any value can be written in the timer counters The timers can easily be reset by software using the UG bit in the TIMx EGR registers 2 DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 2 2 Time
530. troller interrupt occurs The corresponding vector is then loaded in the PC register and bits 11 and 10 of the register are set to disable interrupts level 3 e non maskable software interrupt This software interrupt source is serviced when the TRAP instruction is executed It is serviced as a TLI according to the flowchart shown in Figure 13 A TRAP interrupt does not allow the processor to exit from Halt mode e RESET The RESET interrupt source has the highest STM8 software and hardware priorities This means that all the interrupts are disabled at the beginning of the reset routine They must be re enabled by the RIM instruction see Table 11 Dedicated interrupt instruction set A RESET interrupt allows the processor to exit from Halt mode See RESET chapter for more details on RESET interrupt management e top level hardware interrupt This hardware interrupt occurs when a specific edge is detected on the corresponding TLI input Caution TRAP instruction must not be used in a TLI service routine 3 DoclD14587 Rev 12 61 595 Interrupt controller ITC 0016 6 4 62 595 Maskable interrupt sources Maskable interrupt vector sources are serviced if the corresponding interrupt is enabled and if its own interrupt software priority in SPRx registers is higher than the one currently being serviced I1 and I0 in CCR register If one of these two conditions is not me
531. tware writing to the SWD bit in the Global configuration register CFG In this state the SWIM pin can be used by the application as a standard I O pin In case of a reset the SWIM goes back to OFF mode 3 SWIM This state is entered when a specific sequence is performed on the SWIM pin In this state the SWIM pin is used by the host tool to control the STM8 with commands SRST system reset ROTF read on the fly WOTF write on the fly Refer to the STM8 SWIM communication Protocol and Debug Module User Manual for a description of the SWIM and Debug module DM registers DoclD14587 Rev 12 57 595 Interrupt controller ITC 0016 6 6 1 6 2 58 595 Interrupt controller ITC ITC introduction e Management of hardware interrupts External interrupt capability on most I O pins with dedicated interrupt vector and edge sensitivity setting per port Peripheral interrupt capability e Management of software interrupt TRAP e Nested or concurrent interrupt management with flexible interrupt priority and level management Upto 4 software programmable nesting levels Up to 32 interrupt vectors fixed by hardware 2non maskable events RESET TRAP 1non maskable top level hardware interrupt TLI This interrupt management is based on e Bitl1 and l0 of the CPU Condition Code register CCR e Software priority registers SPRx e Reset vector address 0x00 8000 at the beginni
532. upts 00 Falling edge and low level 01 Rising edge only 10 Falling edge only 11 Rising and falling edge Bits 1 0 PAIS 1 0 Port A external interrupt sensitivity bits These bits can only be written when 11 and 10 in the CCR register are both set to 1 level They define the sensitivity of Port A external interrupts 00 Falling edge and low level 01 Rising edge only 10 Falling edge only 11 Rising and falling edge d DoclD14587 Rev 12 69 595 Interrupt controller ITC 0016 6 9 4 External interrupt control register 1 2 Address offset 0x01 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved TLIS PEIS 1 0 r rw rw Bits 7 3 Reserved Bit 2 TLIS Top level interrupt sensitivity This bit is set and cleared by software This bit can be written only when external interrupt is disabled on the corresponding GPIO port PD7 or PC3 refer to Section 6 6 External interrupts on page 65 0 Falling edge 1 Rising edge Bits 1 0 PEIS 1 0 Port E external interrupt sensitivity bits 70 595 These bits can only be written when 11 and IO in the register are both set to 1 level 3 They define the sensitivity of the Port E external interrupts 00 Falling edge and low level 01 Rising edge only 10 Falling edge only 11 Rising and falling edge DoclD14587 Rev 12 d RM0016 Interrupt controller ITC 6 9 5 ITC and EXTI register map and reset values Table 12
533. upts cause the device to exit from Wait wall mode No effect on I O ports External interrupts cause the device to wakeup from on Halt mode If PA1 PA2 pins are used to connect an external oscillator to ensure a lowest power consumption in Halt mode PA1 and PA2 must be configured as input pull up DoclD14587 Rev 12 107 595 General purpose ports GPIO 0016 11 7 11 7 1 11 7 2 11 7 3 Input mode details Alternate function input Some I Os be used as alternate function input For example as the port may be used as the input capture input to a timer Alternate function inputs are not selected automatically you select them by writing to a control bit in the registers of the corresponding peripheral For Alternate Function input you should select floating or pull up input configuration in the DDR CR1 registers Interrupt capability Each I O can be configured as an input with interrupt capability by setting the CR2x bit while the I O is in input mode In this configuration a signal edge or level input on the I O generates an interrupt request Falling or rising edge sensitivity is programmed independently for each interrupt vector in the CR 2 1 registers External interrupt capability is only available if the port is configured in input mode Interrupt masking Interrupts can be enabled disabled individually by programming the corresponding bit in the configuration
534. ure compare value LSB 210 595 d DoclD14587 Rev 12 RM0016 16 bit advanced control timer TIM1 17 7 26 register high TIM1 CCR3H Address offset 0x19 Reset value 0x00 CCR3 15 8 Bits 7 0 CCR3 15 8 Capture compare value MSB 17 7 27 Capture compare register low TIM1 CCR3L Address offset 0x1A Reset value 0x00 If the CC3 channel is configured as output CC3S bits in TIM1_CCMR3 register The value of CCR3 is loaded permanently into the actual capture compare 3 register if the preload feature is not enabled OC3PE bit in TIM1_CCMR3 Otherwise the preload value is copied in the active capture compare register when a UEV occurs The active capture compare register contains the value which is compared to the counter register TIM1_CNT and signalled on the OC3 output If the CC3 channel is configured as input CC3S bits in TIM1_CCMR3 register The value of CCR3 is the counter value transferred by the last input capture 3 event IC31 7 6 4 3 0 CCR3 7 0 rw rw rw rw rw Bits 7 0 CCR3 7 0 Capture compare value LSB Ly 1014587 Rev 12 211 595 16 bit advanced control timer TIM1 0016 17 7 28 register 4 high TIM1 CCRAH Address offset Ox1B Reset value 0x00 CCR4 15 8 Bits 7 0 CCR4 15 8 Capture
535. veral UARTs connected in a network For example one of the UARTs can be the master its TX output is connected to the RX input of the other UART The others are slaves their respective TX outputs are logically ANDed together and connected to the RX input of the master In multi processor configurations it is often desirable that only the intended message recipient should actively receive the full message contents thus reducing redundant UART service overhead for all non addressed receivers The non addressed devices may be placed in mute mode by means of the muting function In mute mode e None of the reception status bits can be set e receive interrupts are inhibited e The RWU bit in UART CR2 register is set to 1 RWU can be controlled automatically by hardware or written by the software under certain conditions The UART can enter or exit from mute mode using one of two methods depending on the WAKE bit in the UART register e ldle Line detection if the WAKE bit is reset e Address Mark detection if the WAKE bit is set Idle line detection WAKE 0 The UART enters mute mode when the RWU bit is written to 1 It wakes up when an Idle frame is detected Then the RWU bit is cleared by hardware but the IDLE bit is not set in the SR register RWU can also be written to 0 by software An example of mute mode behavior using idle line detection is given in Figure 120 Figure 120 Mute mode using idle l
536. vice datasheet for the definitions of parameters tow lwscLL See device datasheet for the definitions of parameters I2C communication speed 1 thigh tow The real frequency may differ due to the analog noise filter input delay DoclD14587 Rev 12 d RM0016 Inter integrated circuit PC interface 21 7 12 Clock control register high 2 CCRH Address offset OxX0C Reset value 0x00 F S DUTY Reserved CCR 11 8 rw r rw Bit 7 Bit 6 Bits 5 4 Bits 3 0 Note d F S 2 master mode selection 0 Standard mode 2 1 Fast mode 2 DUTY Fast mode duty cycle 0 Fast mode tow thigh 2 1 Fast mode tiow thigh 16 9 see CCR Reserved CCR 11 8 Clock control register in Fast Standard mode Master mode Controls the SCLH clock in master mode Standard mode Period I2C 2 tMASTER thigh CCR CCR tMASTER Fast mode If DUTY 0 Period I2C 23 CCHR MASTER thigh CCR tyAsTER tow 2 CCR tMASTER If DUTY 1 to reach 400 kHz Period I2C 25 CCR tMASTER thigh 9 CCR tuasterR tlow 16 CCR tyAsTER For instance in standard mode to generate a 100 kHz SCL frequency If FREQR 08 125 ns so CCR must be programmed with 0x28 0x28 lt gt 40 x 125 ns 5000 ns Note thigh 1 See device datasheet for the definitions of parameters t
537. vironmental protection In a silicon chip there are two kind of consumption e Static power consumption which is due to analog polarization and leakages This so small it is only significant in Halt and Active halt modes refer to Section 10 2 Low power modes e Dynamic power consumption which comes from running the digital parts of the chip It depends on Vpp clock frequency and load capacitors In a microcontroller device the consumption depends on e supply voltage e Analog performance e MCU size or number of digital gates leakages and load capacitors e Clock frequency e Number of active peripherals e Available low power modes and low power levels Device processing performance is also very important as this allows the application to minimize the time spent in Run mode and maximize the time in low power mode Using the MCU s flexible power management features you can obtain a range of significant power savings while the system is running or able to resume operations quickly 2 DoclD14587 Rev 12 RM0016 Power management 10 1 1 Clock management for low consumption Slowing down the system clock In Run mode choosing the oscillator to be used as the system clock source is very important to ensure the best compromise between performance and consumption The selection is done by programming the clock controller registers Refer to the Clock control CLK section As a fur
538. w r rw d Bit 7 Write option bytes This bit is set and cleared by software 0 Write access to option bytes enabled 1 Write access to option bytes disabled Bit 6 NWPRG Word programming This bit is cleared by software and set by hardware when the operation is completed 0 Word programming enabled 1 Word programming disabled Bit 5 NERASE Block erase This bit is cleared by software and set by hardware when the operation is completed 0 Block erase enabled 1 Block erase disabled Bit 4 NFPRG Fast block programming This bit is cleared by software and set by software reading the register 0 Fast block programming enabled no erase before programming the programmed data values are not guaranteed when the block is not blank fully erased before the operation 1 Fast block programming disabled Bits 3 1 Reserved Bit 0 NPRG Block programming This bit is cleared by software and set by hardware when the operation is completed 0 Block programming enabled 1 Block programming disabled DoclD14587 Rev 12 53 595 Flash program memory and data EEPROM 0016 4 8 4 Flash protection register FLASH FPR Address offset 0x03 Reset value 0x00 7 6 5 4 3 2 1 0 Reserved WPB5 WPB4 WPB3 WPB2 WPB1 WPBO r ro ro ro ro ro ro Bits 7 6 Reserved Bits 5 0 WPB 5 0 User boot code area protection bits These bits show the size of the boot code area They are loaded
539. wakeup from Active halt in the interrupt vector table in the datasheet When several pending interrupts are present while waking up from Halt mode the first interrupt serviced can only be an interrupt with exit from Halt mode capability It is selected through the decision process shown in Figure 14 If the highest priority pending interrupt cannot wake up the device from Halt mode it will be serviced next If any internal or external interrupt from a timer for example occurs while the HALT instruction is executing the HALT instruction is completed but the interrupt invokes the wakeup process immediately after the HALT instruction has finished executing In this case the MCU is actually waking up from Halt mode to Run mode with the corresponding delay of as specified in the datasheet Activation level low power mode control The MCU activation level is configured by programming the AL bit in the CFG register see global configuration register CFG This bit is used to control the low power modes of the MCU In very low power applications the MCU spends most of the time in WFI and is woken up through interrupts at specific DoclD14587 Rev 12 Ly RM0016 Interrupt controller ITC 6 5 6 5 1 d moments in order to execute a specific task Some of these recurring tasks are short enough to be treated directly in an ISR interrupt service routine rather than going back to the main program To cove
540. ware and cleared by software by reading the register 0 No WR PG DIS event occurred 1 A write attempt to a write protected page occurred An interrupt is generated if the IE bit is set in the FLASH CR register 4 8 9 Flash register map and reset values For details on the Flash register boundary addresses refer to the general hardware register map in the datasheets Table 7 Flash register map and reset values Address Register name 7 6 5 4 3 2 1 0 0 00 FLASH CHR1 2 HALT AHALT IE FIX Reset value 0 0 0 0 0 0 0 0 0x01 FLASH_CR2 OPT WPRG ERASE FPRG PRG Reset value 0 0 0 0 0 0 0 0 FLASH NCR2 NWPRG NERASE NFPRG NPRG 0x02 1 Reset value 1 1 1 1 1 0x03 FLASH FPR WPB5 WPB4 WPB3 WPB2 WPB1 WPBO Reset value 0 0 0 0 0 0 0 0 0x04 FLASH NFPR NWPBS NWPB4 NWPB3 NWPB2 NWPB1 NWPBO Reset value 1 1 1 1 1 1 1 1 0x05 FLASH IAPSR _ HVOFF _ DUL EOP PUL WR PG 018 Reset value 0 1 0 0 0 0 0 0 0 06 0 07 Reserved 0x08 FLASH PUKR PUK6 5 PUK4 PUK3 PUK2 PUK1 PUKO Reset value 0 0 0 0 0 0 0 0 0x09 Reserved Ox0A FLASH_DUKR DUNP6 DUK5 DUK4 DUK3 DUK2 DUK1 DUKO Reset value 0 0 0 0 0 0 0 0 56 595 DoclD14587 Rev 12 RM0016 Single wire interface module SWIM and debug module DM 5 5 1 5 2 5 3 Note 2 Single wire interface module SWIM and debug module DM
541. writing e SMS 001 in the SMCR register if the counter is counting on TI2 edges only e SMS 010 if the counter is counting on edges only e SMS 011 if the counter is counting on both TI1 and 2 edges Select the 1 and 2 polarity by programming the CC1P and CC2P bits in the TIM1 CCER1 register When needed the input filter can also be programmed The two inputs and 2 are used to interface an incremental encoder see Table 37 If the counter is enabled when the CEN bit in the TIM1 CR1 register is written to 1 it is clocked by each valid transition on 1 or 2 2 see Figure 64 Input stage of 1 channel 1 The transition sequences of the two inputs and TI2 are evaluated and generate count pulses and a direction signal Depending on the sequence the counter counts up or down and the DIR bit in the TIM1 register is modified accordingly by hardware The DIR bit is calculated at each transition based on inputs from either 1 or T12 without this being dependent on whether the counter is counting pulses on 1 TI2 or both Encoder interface mode acts as an external clock with direction selection The counter counts continuously between 0 and the auto reload value in the TIM1 ARR register 0 to ARR or ARR down to 0 depending on the direction TIM1 ARR must be configured before starting The capture compare prescaler and trigger output features continue to work as normal
542. x bits 0b11 in CAN FCRx register 385 16 bit filter bank configuration FSCx bits 0b10 in CAN FCRx register 385 16 8 bit filter bank configuration FSCx bits 0001 in CAN FCRx register 386 8 bit filter bank configuration FSCx bits 0000 in FCRx register 386 Filter banks configured as in the example in Table 65 388 CAN error state 391 oe Hs E bas eget d bea Rd ti s oes oe RE 392 GAN frames PST E RIPE dE eT ER EROR Reds 393 Event flags and interrupt 1 394 CAN register mapping 419 page mapping 420 ADC1 block 4 424 ADC2 block diagram da a ee De a ck maed ach d 425 Analog watchdog guarded area 1 429 Timing diagram in single mode 0 431 Timing diagram in continuous mode 1 431 Right alignment of data 1 435 Left alignment 1 435 d D
543. x communications The SPI is capable of operating in simplex mode in 2 configurations e 1 clock and 1 bidirectional data wire e 1 and 1 data wire Receive only or Transmit only 1 clock and 1 bidirectional data wire This mode is enabled by setting the bit in the SPI CR2 register In this mode SCK is used for the clock and MOSI in master or MISO in slave mode is used for data communication The transfer direction Input output is selected by the BDOE bit in the SPI CR2 register When this bit is set to 1 the data line is output otherwise it is input 1 clock and 1 unidirectional data wire BDM z 0 In this mode the application can use the SPI either in transmit only mode or in receive only mode e Transmit only mode is similar to full duplex mode 0 RXONLY 0 the data is transmitted to the transmit pin MOSI in master mode or MISO in slave mode and the receive pin MISO in master mode or MOSI in slave mode can be used as general purpose I O In this case the application just needs to ignore the Rx buffer if the data register is read it does not contain the received value e Inreceive only mode the application can disable the SPI output function by setting the RXONLY bit in the CR2 register In this case it frees the transmit I O pin MOSI in master mode or MISO in slave mode so it can be used for other purposes To start the communication in receive only mode configure and enable the
544. y by splitting nominal bit time into three segments as follows Synchronization segment SYNC SEQ a bit change is expected to occur within this time segment It has a fixed length of one time quantum 1 x Bit segment 1 BS1 defines the location of the sample point It includes the PROP SEG and PHASE SEG of the CAN standard Its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network Bit segment 2 BS2 defines the location of the transmit point It represents the PHASE SEG of the CAN standard Its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts The resynchronization Jump Width SJW defines an upper bound to the amount of lengthening or shortening of the bit segments It is programmable between 1 and 4 time quanta To guarantee the correct behavior of the CAN controller SYNC SEG BS1 BS2 must be greater than or equal to 5 time quanta Note For a detailed description of the CAN bit timing and resynchronization mechanism please refer to the ISO 11898 standard As a safeguard against programming errors the configuration of the Bit Timing Registers CAN BTR1 and CAN BTR2 is only possible while the device is in Initialization mode Figure 154 Bit timing
545. y if the word is empty no erase operation is performed and the programming time is shorter see in Table Flash program memory in the datasheet However the programming time can be fixed by setting the FIX bit of the FLASH CR1 register to force the program operation to systematically erase the byte whatever its content see Section 4 8 1 Flash control register 1 FLASH 1 The programming time is consequently fixed and equal to the sum of the erase and write time see in Table Flash program memory in the datasheet To write a byte fast no erase the whole word 4 bytes into which it is written must be erased beforehand Consequently It is not possible to do two fast writes to the same word without an erase before the second write The first write will be fast but the second write to the other byte will require an erase Word programming A word write operation allows an entire 4 byte word to be programmed in one shot thus minimizing the programming time As for byte programming word operation is available both for the main program memory and data EEPROM On some devices the read while write RWW capability is also available when a word programming operation is performed on the data EEPROM Refer to the datasheets for additional information e Inthe main program memory The application stops for the duration of the byte program operation e In DATA area Devices with RWW capability Program execut
546. y the software To fulfil this requirement the beCAN Controller provides 6 configurable and scalable filter banks 5 0 in order to receive only the messages the software needs This hardware filtering saves CPU resources which would be otherwise needed to perform filtering by software Each filter bank x consists of eight 8 bit registers CAN FxR 8 1 DoclD14587 Rev 12 383 462 Controller area network beCAN 0016 384 462 Scalable width To optimize and adapt the filters to the application needs each filter bank can be scaled independently Depending on the filter scale a filter bank provides 32 bit filter for the STDID 10 0 EXID 28 18 IDE EXID 17 0 and bits Two 16 bit filters for the STDID 10 0 EXID 28 18 RTR and IDE bits Four 8 bit filters for the STDID 10 3 EXID 28 21 bits The other bits are considered as don t care One 16 bit filter and two 8 bit filters for filtering the same set of bits as the 16 and 8 bit filters described above Refer to Figure 148 through Figure 151 Furthermore the filters can be configured in mask mode or in identifier list mode Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as must match or as don t care Identifier list mode In identifier list mode the mask registers are used as identifier registers Thus instead of defining an identifier and a m
547. y y y 1 4 ILIEN TEN REN RWU SBK TC RXNE IDLE OR NF FE UART4_SR 4 INTERRUPT CONTROL TRANSMITTER RATE CONTROL NEN Y UARTA4 BRR1 UARTDIV UARTDIV 1 1 4 fMASTER UART4_BRR2 AUTOMATIC RESYNCHRONIZATION y nae UARTDIV 15 12 UARTDIV 3 0 7 43 0 UART4_CR6 RECEIVER RATE LDUM LSLV LASE LHIEN LHDFLSF pey CONTROL DoclD14587 Rev 12 321 462 Universal asynchronous receiver transmitter UART 0016 22 3 1 322 462 UART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the UART CR1 register see Figure 114 The UART pin is in low state during the start bit It is in high state during the stop bit An Idle character is interpreted as an entire frame of 1 s the number of 1 s includes the start bit the number of data bits and the number of stop bits A Break character is interpreted on receiving O s for a frame period At the end of the break frame the transmitter inserts either 1 or 2 stop bits logic 1 bit to acknowledge the start bit Transmission and reception are driven by a common baud rate generator the clock for each is generated when the enable bit is set respectively for the transmitter and receiver The details of each block is given below Figure 114 Word length programming
548. ystem CSS monitors HSE crystal clock source failures When fuAsTER depends on HSE crystal i e when HSE is selected if the HSE clock fails due to a broken or disconnected resonator or any other reason the clock controller activates a stall safe recovery mechanism by automatically switching to the auxiliary clock source HSI 8 Once selected the auxiliary clock source remains enabled until the MCU is reset You enable the clock security system by setting the CSSEN bit in the Clock security system register CLK CSSR For safety reason once CSS is enabled it cannot be disabled until the next reset The following conditions must be met so that the CSS can detect HSE quartz crystal failures e HSE crystal on HSEEN 1 in the External clock register CLK e HSE oscillator in quartz crystal configuration EXTCLK option bit is reset e CSS function enabled CSSEN 1 in the CLK CSSR register If HSE is the current clock master when failure is detected the CSS performs the following actions e The CSSD bit is set in the CLK CSSR register and an interrupt is generated if the CSSIEN bit is set e Clock master status register CMSR Clock master switch register SWR register and the HSIDIV 1 0 bits in the Clock divider register CKDIVR are set to their reset values CKM 7 0 SWI 7 0 E1h HSI 8 becomes the master clock e HSIEN bit in the nternal clock register CLK_ICKR

RM0016 - STMicroelectronics

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