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TM8725 User`s Manual

1. SBCI 0011 0010 DDDD YYYY Ry D B CF CF SBCF RyD 0011 0011 DDDD YYYY AC Ry Ry DB CF CF ADDI 0011 0100 DDDD YYYY Ry D ADDI RyD 0011 0101 DDDD YYYY AC Ry Ry D SUBI 0011 0110 DDDD YYYY Ry 1 SUBF RyD 0011 0111 0000 YYYY AC Ry 2 DB 1 ADNI 0011 1000 DDDD YYYY Ry D ADNI 0011 1001 DDDD AC Ry Ry D ANDI Ry D 0011 1010 DDDD YYYY Ry AND D ANDI RyD 0011 1011 DDDD YYYY AC Ry Ry AND D EORI 0011 1100 DDDD YYYY Ry EOR D EOR 0011 1101 DDDD AC Ry Ry EOR D ORI 0011 1110 DDDD YYYY Ry OR D ORF 0011 1111 DDDD YYYY AC Ry Ry OR D INC Rx 0100 0000 OXXX AC Rx Rx 1 INC HL 0100 0000 1000 0000 AGjRGHL lt R HL 1 lt R HL 1 INC HL 0100 0000 1100 0000 217 2 DEC Rx 0100 0001 OXXX XXXX AC Rx Rx 1 CF DEC HL 0100 0001 1000 0000 AC R HL R HL 1 CF lt R HL 1 DEC HL 0100 0001 1100 0000 ie 201 PA Rx 0100 0010 OXXX lt 1 IPB 0100 0100 OXXX 10 B IPC 0100 0111 AC Rx 10 C PD 0100 1000 OXXX 1O D B3 CF MAF Rx 0100 1010 OXXX lt STS1 ZERO
2. 10 tenx technology inc Rev 1 0 2006 12 13 7 Segment Driver Outp ut Characteristics UM TM8725_E Name Symb Condition For Min Typ Max Unit Static Display Mode UE Voh1d loh 1UA 1 1 0 V n 38 Voh2d loh 1uA 2 2 2 V Voh3d loh 1uA 3 SEG n 3 8 V Output L Volid lol 1uA 1 0 2 V Voltage Vol2d lol 1uA 2 0 2 V Vol3d lol 1uA 3 0 2 V Output H Vohle loh 10uA 1 1 0 V Voltage Voh2e loh 10uA 2 2 2 V Voh3e loh 10uA 3 COM n 3 8 V Output L Volle lol 10uA 1 0 2 V Voltage Vol2e lol 10uA 2 0 2 V Vol3e lol 10uA 3 0 2 V 1 2 Bias Display Mode Output H Voh12f loh 1uA 1 2 2 2 V Voltage Voh3f loh 1uA 3 SEG n 3 8 V Output L Vol12f lol 1uA 71 22 0 2 V Voltage Vol3f lol 1uA 23 0 2 V Output H Voh12g loh 10uA 1 2 COM n 2 2 V Voltage Voh3g loh 10uA 3 3 8 V Output M Vom12g lol h 10uA 1 2 COM n 1 0 1 4 V Voltage Vom3g lol n 10UA 3 1 8 2 2 V 1 3 Bias display Mode Output H Voh12h loh 1uA 1 2 3 4 V Voltage Voh3h loh 1UA 3 5 8 V Output M1 Vomlh lol h 10uA 1 2 1 0 1 4 V Voltage Vom13h lol h 10uA 3 SEG n 1 8 2 2 V Output M2 Vom22h lol h 10uA 1 2 2 2 2 6 V Voltage Vom23h lol h 10uA 3 3 8 4 2 V Output L Vol12h lol 1uA 71 722 0 2 V Voltage Vol3h lol 1u
3. 144 2 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM8725 is an embedded high performance 4 bit microcomputer with LCD driver It contains all the necessary functions such as 4 bit parallel processing ALU ROM RAM I O ports timer clock generator dual clock operation Resistance to Frequency Converter RFC EL panel driver LCD driver look up table watchdog timer and key matrix scanning circuitry in a single chip 1 2 FEATURE 1 Low power dissipation 2 Powerful instruction set 178 instructions e Binary addition subtraction BCD adjusts logical operation in direct and index addressing mode Single bit manipulation set reset decision for branch Various conditional branches 16 working registers and manipulation Table look up LCD driver data transfer 3 Memory capacity e ROM capacity 3072 x 16 bits e capacity 384 4 bits 4 LCD driver output e common outputs and 40 segment outputs up to drive 240 LCD segments 1 2 Duty 1 3 Duty 1 4 Duty 1 5 Duty or 1 6Duty is selected by MASK option 1 2 Bias or 1 3 Bias is selected by MASK option Single instruction to turn off all segments COM5 6 SEG1 40 could be defined as CMOS or P open drain type output by mask option 5b Input output ports e Port IOA 4 pins with internal pull low muxed with SEG24 SEG27 e Port 4 pins with internal pull
4. SCF 1 orpitet SEF4 SCA 10h Ciaterig presei toi miter cPLC To InterruptO Initial reset Interrupt 1 SEF3 ScF3 IEF1 SCF2 SCA 8h SIE 2h Timer1 HRF1 SCF5 Interrupt 1 mal u SHE 2h IEF2 Signal CE m Interrupt 2 changed HRF 2 on IN T pin HEF2 SCF 4 SHE 4h yu Interrupt 3 1 owerflonu SCF SIE 8h e Predivide HRF 3 HEF SHE 8 SIE 10h Interrupt 4 underflow HEF 4 SHE 10h IEF5 SIF 20h Interrupt 5 Key Scanning HRF5 ove flou O SHE 20h SIE 40h Interrupt 6 overflow SHE 40h 2 14 1 STATUS REGISTER 1 STS1 Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the result of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 If the content of the accumulator is not 0 the zero flag is reset to 0 45 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 Bit 0 Carry fl
5. Note The default prevention clock is PH10 This figure shows the organization of chattering prevention circuitry This chattering prevention function works when the signal at the applicable pin ex IOD1 is changed from L level to H level or from H level to L level and the remaining pins ex IOD2 to IOD4 are held at L level When the signal changes at the input pins of IOD port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 and PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF3 At that time the chattering prevention clock will stop due to the delivery of SCF3 The SCFS will be reset to O by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF3 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOD interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOD1 to IOD4 the input data at the port IOD must be read into the RAM immediately after the halt mode is released 81 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 6 EL PANEL DRIVER TM8725 provides an EL panel driver for the backlight of the LCD panel The user can choose different voltage pumping frequencies duty cycle and ON OFF frequency to
6. This figure shows the Pre divider and its Peripherals The PH14 delivers the halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of pre divider is PHO and 4 kinds of frequency of PHO could be selected by mask option MASK OPTION table Mask Option name Selected item PHO lt gt BCLK FOR FAST ONLY 1 PH0 BCLK PHO lt gt BCLK FOR FAST ONLY 2 PHO BCLK 4 PHO lt gt BCLK FOR FAST ONLY 3 PHO BCLK 8 4 PHO lt gt BCLK FOR FAST ONLY PHO BCLK 16 27 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 2 5 System Clock Generator For the system clock the clock switch circuit permits the different clocks input from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator SGC The basic system clock is shown below 28 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 3 PROGRAM COUNTER PC This is a 12 bit counter which addresses the program memory ROM up to 3072 addresses The MSB of program counter PC11 is a page register Only CALL and JMP instructions could address to the w
7. SEG32 IOC1 KI 2 IOC1 SEG33 IOC2 KI2 2 IOC2 SEG34 IOC3 KI3 2 IOC3 SEG35 IOC4 KI4 2 IOC4 After the reset cycle the IOC port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPC instruction Executed OPC instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IPC instructions may store the signals applied to the IOC pins in the specified data memory When the IOC pins are defined as the output executing IPC instruction will save the data stored in the output latches in the specified data memory Before executing SPC instruction to define the IOC pins as output the OPC instruction must be executed to output the data to those output latches This will prevent the chattering signal when the IOC pins change to output mode 76 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E bit bitl bitt Initial clear t SCF SPC 5 1 Data Bus bit2 bit bits bits Note M O is mask option H Control 2 IPC OPC This figure shows the organization of IOC port Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 77 tenx tech
8. No use BO No use B3 SCF3 DPT MSB Rx 0100 1011 AC Rx lt STS2 E s B3 SCF7 PDV Msc Rx 0100 1100 AC Rx lt STS3 x eee BO SCFA INT B3 SCF9 RFC MCX Rx 0100 1101 AC Rx STS3X E BO SCF8 SKI B3 No use B2 RFOVF MSD Rx 0100 1110 OXXX XXXX AC Rx lt STS4 5 SRO 0101 0000 OXXX XXXX i EUM SRI 0101 0001 OXXX XXXX AE 2 EUM SLO 0101 0010 OXXX ACn Rxn lt Rx n 1 139 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Instruction Machine Code Function Flag Remark ACO RxX0 0 SL1 0101 0011 OXXX XXXX 2 0101 0100 0000 0000 BCD AC DAA Rx 0101 0101 OXXX AC Rx BCD AC HL 0101 0101 1000 0000 ACRQGHL BCD AC DAA GHL 0101 0101 1100 0000 2 ED DAS 0101 0110 0000 0000 BCD AC DAS Rx 0101 0111 BCD AC DAS 0101 0111 1000 0000 BCD AC ACRQHL BCD AC DAS HL 0101 0111 1100 0000 e 2 LDS 0101 1000 DXXX LDH Rx HL 0110 0000 XXXX AC Rx HTGHL LDH RxQHL 0110 0001 OXXX XXXX QE LDL Rx HL 0110 0010
9. lt R HL AC B CF lt HL 1 0100 OXXX XXXX AC 137 lt Rx AC tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Instruction Machine Code Function Flag Remark ADD HL 0010 0100 1000 0000 lt R HL AC CF AC lt R HL AC ADD HL 0010 0100 1100 0000 HL QHLH CF ADD Rx 0010 0101 OXXX XXXX lt Rx AC CF ADD HL 0010 0101 1000 0000 AC RQHL lt R HL AC CF AC R HL lt R HL AC ADD HL 0010 0101 1100 0000 HL QHLH CF SUB Rx 0010 0110 OXXX XXXX lt Rx AC B 1 CF SUB HL 0010 0110 1000 0000 JAC lt R HL 1 lt R HL 1 SUB HL 0010 0110 1100 0000 HL lt HL 1 CF SUB Rx 0010 0111 OXXX XXXX AC Rx lt Rx AC B 1 CF SUB HL 0010 0111 1000 0000 AC RQHL j RQHL AC B 1 CF AC R HL lt R HL AC B 1 SUB HL 0010 0111 1100 0000 HL lt HL 1 CF ADN Rx 0010 1000 OXXX lt Rx AC ADN HL 0010 1000 1000 0000 lt R HL AC AC lt R HL AC ADN HL 0010 1000 1100 0000 HL QHLH ADN Rx 0010 1001 OXXX XXXX AC Rx lt Rx AC ADN HL 0010 1001 1000 0000 AC RQHL lt R HL AC AC R HL lt R HL AC ADN HL 0010 1001 1100 0000 HL lt HL 1 AND Rx 0010 1010 OX
10. The following conditions cause the stop mode to be released One ofthe signals on the input mode pin of IOD or IOC port is in H state and holds long enough to cause the CPU to be released from halt mode A signal change in the INT pin The stop release condition specified by the SRE instruction is met When the TM8725 is released from the stop mode the TM8725 enters the halt mode immediately and will process the halt release procedure If the H signal on the IOC IOD port does not hold long enough to set the SCF1 SCF3 once the signal on the IOC port returns to L the TM8725 will enter the stop mode immediately The backup flag BCF will be set to 1 automatically after the program enters the stop mode normal mode The following diagram shows the stop release procedure 56 tenx technology inc STOP HALT MODE STOP Yes released release Rev 1 0 2006 12 13 HALT released decision This Figure shows The stop release state machine UM TM8725_E Before the stop instruction is executed the following operations must be completed e Specify the stop release conditions by the SRE instruction e Specify the halt release conditions corresponding to the stop release conditions if needed e Specify the interrupt conditions corresponding to the stop release conditions if needed When the stop mode is released by an interrupt request the TM8725 will enter the halt mode immediately While the inter
11. P5 P2 P1 PO P10 to PO Low order 11 bits of instruction operand P11 page register When executing the subroutine call instruction or interrupt service routine the contents of the program counter PC are automatically saved to the stack register STACK 29 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 4 PROGRAM TABLE MEMORY The built in mask ROM is organized with 3072 x 16 bits There are 2 pages memory space in this mask ROM Page 0 covered the address range from 000h to 7FFh and page 1 covered 800h to BFFh Page Both instruction ROM PROM and table ROM TROM shares this memory space together The partition formula for PROM and TROM is shown below Instruction ROM memory space 1024 128 N words Table ROM memory space 256 16 N bytes N 0 16 Note The data width of table ROM is 8 bit The partition of memory space is defined by mask option the table is shown below MASK OPTION table Instruction ROM Table ROM Mask Option name Selected item memory space memory space Words Bytes INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM
12. Rx SCF4 SCF5 SCF7 PH15 Description The SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag The content of 15th Start condition flag Start condition flag 7 stage of the 5 4 SCF7 predivider SCF5 SCF4 Halt release Halt release Halt release caused by caused by TM1 caused by INT pin predivider overflow underflow MCX Rx Function AC Rx SCF8 SCF6 SCF9 Description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows 126 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Bit 3 Bit 2 Bit 1 Bit 0 Start condition NA Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 Halt release NA Halt release Halt release caused by caused by TM2 caused by the counter overflow underflow signal change to L applied on KI1 4 in scanning interval MSD Rx Function Rx AC WDF CSF RFOVF Description The watchdog flag system clock status and overflow flag of RFC counter are loaded to data memory specified by Rx and AC The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 of 16 bit counter of enable flag WDF selection flag RFC RFOVF CSF
13. The working registers are part of the data memory RAM and the relationship between them was shown as follows The absolute address of working register Rx Ry 70H Address of working registers Absolute address of data memory specified by Ry Rx Lz represents the address of the latch of LCD PLA PSTB data in cfy file the address range specified by Lz is from to 1FH 5 1 INPUT OUTPUT INSTRUCTIONS LCT Lz Ry Function LCD latch Lz data decoder lt Ry Description The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder Lz 00 1FH Ry 0 FH LCB Lz Ry Function LCD latch Lz data decoder lt Ry Description The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the outputs of the data decoder are all 0 Lz 00 1FH Ry 0 FH LCP Lz Ry Function LCD latch Lz lt Ry AC Description The working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz 101 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Lz 00 1FH Ry 0 FH Table 4 2 The mapping table of LCD latches with the contents of AC and Ry __ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH LCD Lz HL Function Description LCT Lz HL Function Description LCB Lz HL F
14. z o oo Om Ee IN IO INSTRUCTION ROM TABLE ROM INSTRUCTION ROM TABLE ROM ni k INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM INSTRUCTION ROM lt gt TABLE ROM 30 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as the interrupt service routines such as reset address 000 interrupt 0 address 014H interrupt 1 address 018 interrupt 2 address 010H interrupt 3 address 01 interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory When the useful address range of PROM exceeds 2048 addresses 800h the memory space of PROM will be defined as 2 pages automatically Refer to section 2 3 Address 000h 0 a ee O14h High Low Nibble Nibble aspi a X 15 N N 1 gt 15 2 020 2 2 1244028 70 18 16bits Instruction ROM PROM organization Table ROM TROM organization 256 16 N addresses XFFH This figure shows the Organization of ROM 2 4 2 TABLE ROM TROM The table ROM is organized with 256 16 N x 8 bits that shared the memo
15. 0001 active K2 column Xo 1110 active K15 column Xo 1111 active K16 column X X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xo don t care X7X5X4 010 in this setting the key matrix scanning function will be disable Xo don t care X7X5X4 10X in this setting each scanning cycle check 8 specified columns on key matrix The specified column is defined by the setting of X3 X3 0 active K1 K8 columns simultaneously 1 active K9 K16 columns simultaneously X2 Xo don t care X7X5X4 110 in this setting each scanning cycle check four specified columns on key matrix The specified columns are defined by the setting of X3 and Xo X3X2 00 active K1 K4 columns simultaneously X3X2 01 active K5 K8 columns simultaneously X3X2 10 active K9 K12 columns simultaneously X3X2 11 active K13 K16 columns simultaneously X4 Xo don t care X7X5X4 111 in this setting each scanning cycle check two specified columns on key matrix The specified columns are defined by the setting of Xs X2 and X X3X2X1 000 active K1 K2 columns simultaneously X3X2X1 001 active K4 columns simultaneously X3X2X1 110 active K13 K14 columns simultaneously X3X2X1 111 active 15 K16 columns simultaneously Xo don t care 90 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E
16. 100D 0000 0101 Multi Lz lt 7SEG lt R HL 100D 0000 0110 Multi Lz 7SEG R HL Blank Zero 100D 0000 O111 Multi Lz lt R HL amp AC 1010 OXXX XXXX IO A lt Rx 1011 DXXX XXXX IOA1 2 3 4 lt Rx0 Rx1 D Pulse 1100 OXXX XXXX O B lt Rx 1101 OXXX XXXX lt Rx 1110 OXXX XXXX O C lt Rx 1 00DD OXXX XXXX FREQ D 00 D 01 D 10 D 11 lt Rx amp AC 1 4 Duty 1 3 Duty 1 2 Duty 1 1 Duty 1 01 0000 0000 FREQ lt T HL 1 10DD XXXX XXXX 1 1100 OXXX XXXX L lt Rx 1101 OXXX XXXX H 1 1110 OXXX XXXX U x R Rx 0000 OXXX XXXX 0000 1000 0000 ss Rx AC CF R HL AC CF lt lt lt lt 0000 1100 0000 HL R HL lt HL 1 AC CF 0001 OXXX XXXX AC Rx Rx AC CF 0001 1000 0000 AC R HL R HL AC CF 0001 1100 0000 AC R HL HL R HL AC CF lt HL 1 0010 OXXX XXXX AC Rx AC B CF 0010 1000 0000 AC R HL AC B CF 0010 1100 0000 AC HL R HL AC B CF lt HL 1 0011 OXXX XXXX AC Rx Rx AC B CF 0011 1000 0000 AC R HL lt R HL AC B CF 0011 1100 0000 AC R HL HL
17. 5 6 INDEX ADDRESS INSTRUCTIONS MVU Rx Function QU Rx AC Description Loads content of Rx to index address buffer QU U3 Rx 3 U2 Rx 2 U1 Rx 1 U0 Rx 0 MVH Rx Function H lt Rx AC Description Loads content of Rx to index address buffer H H3 Rx 3 H2 Rx 2 H1 Rx 1 H0 Rx 0 MVL Rx Function L lt Rx Description Loads content of Rx to index address buffer L L3 Rx 3 L2 Rx 2 L1 Rx 1 L0 Rx 0 127 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E CPHL X Function If HL X force next instruction as NOP Description Compare the content of index register HL in lower 8 bits H and L with the immediate data X Note In the duration of comparison the index address all the interrupt enable flags IEF has to be cleared to avoid malfunction If the compared result is equal the next executed instruction that behind CPHL instruction will be forced as NOP If the compared result is not equal the next executed instruction that behind CPHL instruction will operate normally The comparison bit pattern is shown below CPHL X7 X6 X5 X4 X3 X2 X1 X0 HL IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO 5 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA Function Description DAA Rx Function Description DAA HL Function Description AC lt BCD AC Converts the content of AC to binary format and then restores to AC When this instructio
18. ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift SRO SR1 SLO SL1 Decision JBO JB1 JB2 JB3 JC JNC JZ and JNZ BCD operation DAA DAS 36 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format is another number format for TM8725 When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 CNN E mmo wn c lt lt 9 lt AC lt 9 0 O 0 no nochange no nochange Example 1 LDS 10h 9 Load immediate data 9 to data memory address 10H LDS 11h 1 Load immediate data 1 to data memory address 11H and AC RF 1h Reset CF to 0 ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to AC amp data memory address 10H R10 AC AH CF 0 DAA 10h Convert the content of A
19. IOA3 D IOA4 lt pulse Description Content of Rx is outputted to IOA port D is outputted to IOA3 pulse is outputted to IOA4 D 0Oor1 IPA Rx Function Rx AC lt I OA Description The data of I OA port is loaded to AC and data memory Rx 103 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E SPB X Function Defines the input output mode of each pin for IOB port and enables disables the pull low device Description Sets the I O mode and turns on off the pull low device The meaning of each bit of X X4 2 X1 is shown below Bit pattern Setting Bit pattern Setting Enable the pull low Disable the pull low X4 1 device on IOB1 IOB4 X4 0 device on IOB1 IOB4 simultaneously simultaneously OPB Rx Function lt Rx Description The contents of Rx are outputted to I OB port IPB Rx Function Rx AC lt I OB Description The data of I OB port is loaded to AC and data memory Rx SPC X Function Defines the input output mode of each pin for IOC port and enables disables the pull low device or low level hold device Description The meaning of each bit of X X4 X3 X2 X1 and X0 is shown below Bit pattern Setting Bit pattern Enables all of the pull low Disables all of the pull low and disables the low level and enables the low level hold devices hold devices X3 1 IOC4asoutputmode 3 0 IOC4asinputmode OPC Rx Fu
20. Set A4 1 Pull Low Set A4 1 I O 1111 0101 101X XXXX 142 Set B4 1 Pull Low tenx technology inc Rev 1 0 2006 12 13 Instruction Machine Code Function Set B4 1 I O UM TM8725 E Flag Remark 1111 0101 110X XXXX Set C4 1 Pull Low Low Level Hold Set C4 1 I O 1111 0101 111X XXXX Set D4 1 Pull Low Set 04 1 I O 1111 0110 XXXX Reload 1 Set WDT Enable HALT after EL EL LIGHT On BCF Set CF Set BCF CF 1111 0111 00 OXXX Reload 1 Reset WDT Reset EL LIGHT Off BCF Reset CF Reset RL1 WDF BCF CF 1111 10XX XXXX XXXX BCLKX PHO BCLK 8 ELP CLK BCLKX ELP DUTY ELC CLK ELC DUTY 1111 110X XXXX XXXX X8 7 6 001 X8 7 6 000 5 0 lt PH15 10 1111 1110 0000 XXXX X3 Enable INT powerful Pull low Close all Segments Dis ENX Set Reload 2 Set INTPL RSOFF DED RL2 1111 1110 1000 XXXX Disable Pull low Release Segments Dis ENX Reset Reload 2 Reset INT powerful INTPL RSOFF DED RL2 1111 1111 0000 0000 Halt Operation 143 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Instruction Machine Code Flag Remark STOP 1111 1000 0000 Stop Operation Po Appendix Symbol Description Content of Register Immediate Data Accumulator Complement of Immediate Data
21. This figure shows the timing of the RFC counter controlled by timer 2 Example In this example use the RT network to generate the clock source SRF 1Ah Build up the RT network and enable the counter controlled by TM2 87 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E SHE 10h enable the halt release caused by TM2 TM2X 20h set the PH9 as the clock source of TM2 and the down count value is 20h HALT PLC 10h Clear the halt release request flag of TM2 MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 8 4 Enable Disable the Counter by CX Signal This is another use for the 16 bit counter In previous modes CX is the clock source of the counter and the program must specify a time period by timer or subroutine to control the counter In this mode however the counter has a different operation method CX pin becomes the controlled signal to enable disable the counter and the clock source of the counter comes from the output of the frequency generator FREQ The counter will start to count the clock FREQ after the first rising edge signal applied on the CX pin when the counter is enabled Once the second rising edge is applied to the CX pin after the counter is enabled the halt release request HRF6 will be delivered and the counter will stop counting In this case if the interrupt enable mode IEF6 is provided the interrupt is accepted and if the halt release enable mode HEF6 is
22. a large current straight through current flows to the input buffer The input level must not be in the floating state After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may output the content of specified data memory to the pins defined as output mode the other pins which are defined as the input will still be input Executed IPB instructions may store the signals applied on the IOB pins into the specified data memory When the IOB pins are defined as the output executing IPB instruction will save the data stored in the output latch into the specified data memory Before executing SPB instruction to define the I O pins as output the OPB instruction must be executed to output the data to the output latches This will prevent the chattering signal on the I O pin when the I O mode changed IOB port had built in pull down resistor The pull low device for each pin is selected by mask option and executing SPB instruction to enable disable this device 75 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Pull low function option Mask Option name Selected item IOB PULL LOW RESISTOR 1 USE IOB PULL LOW RESISTOR 2 NO USE 3 5 3 IOC PORT IOC1 IOC4 pins are MUXed with KI1 SEG32 KI2 SEG33 KI3 SEG34 and KI4 SEG35 pins respectively by mask option MASK OPTION table
23. and the lower frequency may be any all of the combinations from PH10 PH15 2 The frequencies in corresponding to the input clock of the pre divider PHO is 32768Hz 3 The BZ and BZB pins will output DCO after the initial reset Example Buzzer output generates a waveform with 1 KHz carrier and PH15 PH14 envelope LDS 20h ALM 70h Output the waveform In this example the BZ and BZB pins will generate the waveform as shown in the following figure PHSQHZ j euo Lr 1 2 627777777222222222222222222222222022222222222222222222222222223 22 ZZ BB 17222 Un Pis LLL ELL z PLE LPL BZB IL T LI LI LE 71 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 4 2 THE CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver the waveform for the IR remote controller For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example SHE 1 Enable timer 1 halt release enable flag TMSX 3Fh Set value for timer 1 is 3Fh and the clock source is PHY SCC 40h Setthe clock source of the frequency generator as BCLK FRQX 2 3 FREQ BCLK 4 2 se
24. the interrupt enable flags IEF must be set again in the interrupt service routine as required 63 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 2 RESET FUNCTION TM8725 contains four reset sources power on reset RESET pin reset IOC port reset and watchdog timer reset When reset signal is accepted TM8725 will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by mask option the one is PH15 2 and the other is PH12 2 2 uui HL L t Hold 16384 or 2048 clocks for pla Normal operation gt internal reset cycle clock System e Internal reset cycle time is PH15 2 MASK OPTION table RESET TIME 1 PH1572 In this option the reset cycle time will be extended 16384 clocks clock source comes form pre divider long at least Internal reset cycle time is PH12 2 MASK OPTION table RESET TIME 2 12 2 In this option the reset cycle time will be extended 2048 clocks clock source comes form pre divider long at least 3 2 1 POWER ON RESET TM8725 provides a power on reset function If the power VDD is turned on or power supply drops below 0 6V it will generate a power on reset signal Power on reset function can be disabled by mask option MASK OPTION table Mask Option name Selected item POWER ON RESET 1 USE POWER ON RESET
25. will be affected D 0H FH AC Ry Ry Y 1 D represents the immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC The result will not affect the carry flag CF D 0H FH AC Ry lt Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The result will not affect the carry flag CF D 0H FH AC lt Ry amp D D represents the immediate data The contents of Ry and D are binary ANDed the result is loaded to AC D 0H FH AC Ry Ry amp D D represents the immediate data 120 tenx technology inc Rev 1 0 2006 12 13 EORI Ry D Function Description EORI Ry D Function Description ORI Ry D Function Description ORI Ry D Function Description UM TM8725 E The contents of Ry and D are binary ANDed the result is loaded to AC and working register Ry D 0H FH AC lt Ry EOR D D represents the immediate data The contents of Ry and D are exclusive ORed the result is loaded to AC D 0H FH AC Ry lt Ry D D represents the immediate data The contents of Ry and D are exclusive OREd the resu
26. 0 output shift gate open 4 580 1 Shifts bit 1 to bit 0 5 OPAS 1 1 Bit 1 output 6 SRO 1 Shifts bit2 to bit 0 7 OPAS 1 1 Bit 2 output 8 SRO 1 5 5 bit 3 to bit 0 9 OPAS 1 1 Bit 3 output 10 OPAS 1 1 Lastdata 11 OPAS 1 0 Shift gate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 10 11 AC 0 5 AC 2 AC 1 IOA1 for Rx 5 for Rx 5 Bit2 for Rx 5 Bit3 for Rx 5 M 7 IOA2 M M IOA3 M IOA4 M gt lt t BCLK 2 If IOA1 pin is used as the CX pin for RFC function and the other pins IOA2 IOA3 are used for normal IO pins IOA1 pin must always be defined as the output mode to avoid the influence from the CX when the input chattering prevention function is active On the other hand the RFC counter can receive the signal changes on IOA1 when the RFC counter is enabled 3 5 2 IOB PORT IOB1 IOB4 pins are MUXed with ELC SEG28 ELP SEG29 BZB SEG30 and BZ SEG31 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC SEG29 IOB2 ELP SEG30 IOB3 BZB SEG31 IOB4 BZ 74 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following figure shows the organization of IOB port Initial clear SPB 1 Initial clear SPB 2 Initial clear SPB 4 Initial clear SPB 8 option Note If the input level is in the floating state
27. 1 CTL1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC IOD port will deliver the SCF1 SCF3 when SEF4 SEF3 has been set to 1 by executing SCA instruction Once the SCF1 SCF3 is delivered the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag 0 IEFO is set to 1 by executing SIE instruction the interrupt request flag 0 interrupt 0 will be delivered to interrupt the program If the interrupt 0 is accepted by SEF4 SEF3 and IEFO the interrupt 0 request to the next signal change at IOC IOD will be inhibited To release this mode SCA instruction must be executed again Hefer to 2 16 1 1 51 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 15 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 HEF1 2 3 4 5 6 and is set by SHE instruction The bit pattern of the control register CTL2 is shown below Halt release enable flag Enable the halt Enable the halt release caused by RFC counter to be finished HRF6 Enable the halt release caused by Key Scanning HRF5 release caused by TMR2 underflow HRF4 Halt release condition Halt release enable flag Enable the halt Enable the halt Enable the halt release caused by release caused by release caused by pre divider overflow INT pin
28. 111 BCLK8 j For ELC setting X3 X2 X1 X0 Duty cycle o PHB 00 JAHt Aduly 1 3 dut 1 2 duty 1 1 duty The default setting after the initial reset is ELP PHO clock of pre divider and 1 4 duty cycle ELC PH8 clock of pre divider and 1 4 duty cycle The timing of the duty cycle is shown below PH O FPHB 1 4 duty 1 3 duty E 1 1 duty Example ELC 110h ELP outputs BCLK clock with 1 3 duty cycle and ELC outputs PH8 clock with 1 4 duty cycle SF 4h Enables the light control signal LIT and turns on the EL light driver RF 4h Disables the light control signal and turns off the EL light driver 83 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 7 EXTERNAL INT PIN The INT pin can be selected as pull up or pull down or open type by mask option The signal change either rising edge or falling edge by mask option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted MASK OPTION table For internal resistor type Mask Option name Selected item INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Mask Option name Selec
29. 2 NO USE 3 2 2 RESET PIN RESET When H level is applied to the reset pin the reset signal will issue There is a built in pull down resistor on this pin Two types of reset method for RESET pin and the type could be mask option the one is level reset and other is pulse reset It is recommended to connect a capacitor 0 1uf between RESET pin and VDD This connection will prevent the bounce signal on RESET pin 64 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 2 2 1 Level Reset Once a 1 signal applied on the RESET pin TM8725 will not release the reset cycle until the signal on RESET pin returned to 0 After the signal on reset pin is cleared to 0 TM8725 begins the internal reset cycle and then release the reset status automatically e MASK OPTION table Mask Option name Selected item RESET PIN TYPE 1 LEVEL 3 2 2 2 Pulse Reset Once a 1 signal applied on the RESET pin TM8725 will escape from reset state and begin the normal operation after internal reset cycle automatically no matter what the signal on RESET pin returned to 0 or not MASK OPTION table Mask Option name Selected item RESET PIN TYPE 2 PULSE The following table shows the initial condition of TM8725 in reset cycle Program counter PC Address 000H Start condition flags 1 to 7 SCF1 7 0 Stop release enable flags 4577 5 4 57 Os Switch enableflags4 5 4 o Ha
30. AC The contents of HL and AC are binary ANDed the result is loaded to AC OHL indicates an index address of data memory AC lt HL 8 AC HL HL 1 The contents of HL and AC are binary ANDed the result is loaded to AC 116 tenx technology inc Rev 1 0 2006 12 13 AND Rx Function Description AND HL Function Description AND Function Description EOR Rx Function Description EOR HL Function Description EOR HL Function Description EOR Rx Function Description UM TM8725 E The content of index register HL will be increment automatically after executing this instruction OHL indicates an index address of data memory AC Rx lt Rx amp AC The contents of Rx and AC are binary ANDed the result is loaded to AC and data memory Rx AC HL HL amp AC The contents of HL and AC are binary ANDed the result is loaded to AC and data memory QHL OHL indicates an index address of data memory AC HL HL amp AC HL HL 1 The contents of HL and AC are binary ANDed the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC lt Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC AC lt Q HL The contents of HL and AC are excl
31. Frequency for LCD The alternating frequency for LCD is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ Each is MUXed with IOB3 and IOB4 by mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When buzzer output function combined with the clock source comes from the frequency generator this output function may generate melody sound effect or carrier output of remote control MASK OPTION table Mask Option name Selected item SEG30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 95 MU 04 03 2 91 LM X X5 XD This figure shows organization of the buzzer output 70 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 4 1 BASIC BUZZER OUTPUT The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output in any combination of one signal of FREQ PH3 1024Hz PH4 2048 2 PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz 12 8Hz PH13 4Hz PH14 2Hz PH15 1Hz The ALM instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope of the modulation output Notes 1 The high frequency clock source should only be one of PH3 PH4 PH5 or FREQ
32. KEY RESET FOR KEY RESET IOCA KI4 FOR KEY RESET GSM DEAS 227 2292 WD _ 20 32 IOC2KI2 VDD Key Scanning latch circuit loc S keyresa oy ney 1 IOC3KI3 T ame vDD x Key Scanning latch circuit loc4Kl4 2 2 WD Key Scanning latch circuit 66 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 2 4 WATCHDOG RESET The timer is used to detect unexpected execution sequence caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider When the watchdog timer overflows it generates a reset signal to reset TM8725 and most of the functions in TM8725 will be initiated except for the watchdog timer which is still active WDF flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watchdog timer organization 9 bit counter WDF WDRST to reset chip Edge detector SF 10H Reset pin POR RF 10H During initial reset power on reset POR or reset pin the timer is inactive and the watchdog flag WDF is reset Instruction SF 10h will enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the content of the timer will be cleared Once the watchdog timer is enabled the timer will be paused when the program enters the halt
33. OXXX XXXX AC Rx lt L T HL LDL RxQHL 0110 0011 OXXX XXXX 0 MRF1 Rx 0110 0100 lt RFC3 0 MRF2 Rx 0110 0101 OXXX XXXX lt 7 4 MRF3 Rx 0110 0110 OXXX XXXX lt RFC11 8 4 Rx 0110 0111 OXXX XXXX AC Rx lt RFC15 12 STA Rx 0110 1000 Rx STA HL 0110 1000 1000 0000 RGHL AC R HL AC 8 HL 0110 1000 1100 0000 21 0110 1100 IAC 0110 1100 1000 0000 RGHL AC lt RQHL 0110 1100 1100 0000 I iss 0110 1101 ICF Rx3 0110 1110 OXXX XXX AG RGHL AC R HL lt Rx 0110 1110 1 XXXX Sus 2017 0110 1111 RGHL AC Rx lt R HL 0110 1111 DX XXX 2 0111 1YYY lt Ry X 1000 OXXX PC Zx if ACO 1 X 1000 1XXX PC ZX if AC1 1 X TOOL OXXX PC x if AC2 1 X 1001 1XXX PC EX if AC3 1 X 1010 OXXX XXXX PC ZX if AC Z 0 X 1010 1XXX XXX PC EK 0 X O11 PC X if AC 0 X 1011 IXXX ZX 1 140 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Instruction Machine Code Function Flag Remark lt PC 1 X PC gt 000h 7FFh PC gt 800h BFFh X 11
34. Status Register STS3X Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition flag 9 NA flag 6 flag 8 SCF9 SCF6 SCF8 Halt release Halt release Halt release caused by RFC caused by TMR2 caused by SKI counter finish underflow underflow Read only Read only Read only Read only 2 14 5 STATUS REGISTER 4 STS4 Status register 4 STS4 consists of 3 flags 1 po System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generator SCG is used Executing SLOW instruction will change the clock source BCLK of the system clock generator SCG to the slow speed oscillator XT clock and the system clock selection flag CSF is reset to 0 Executing FAST instruction will change the clock source BCLK of the system clock generator SCG to the fast speed oscillator CF clock and the system clock selection flag CSF is set to 1 For the operation of the system clock generator refer to 3 3 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF indicates the operating status of the watchdog timer Overflow flag of 16 bit counter of RFC RFOVF The overflow flag of 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of RFC occurs The flag will reset to 0 when this counter is initiated by executing SRF instruction 48 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The MSD ins
35. When KI1 4 is defined for Key matrix scanning input by mask option it is necessary to execute SPC instruction to set the internal unused IOC port as output mode before the key matrix scanning function is active Fig 2 27 shows the organization of Key matrix scanning input port Each one of SKI1 4 change to High will set HRF5 to 1 If HEF5 had been set to 1 beforehand this will cause SCF7 to be set and release the HALT mode After the key scanning cycle the states of SKI1 4 will be latched and executing IPC instruction could store these states into data RAM Execute PLC 20h instruction to clear HRF5 flag Since the key matrix scanning function shared the timing of LCD waveform so the scanning frequency is corresponding to LCD frame frequency and LCD duty cycle The formula for key matrix scanning frequency is shown below Key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for key matrix is 320Hz 32 x 5 x 2 KH PLC 20h hitial Reset hterrupt 5 request key scanning enable signal 91 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E This figure shows the organization of Key matrix scanning input Example SPC SPKX PLC SHE HALT MCX JB0 ski_release IPC JBO JB1 JB2 JB3 ki1_ release SPKX PLC CALL scan
36. be set to 1 e When HRF4 1 and the TMR2 interrupt enabler IEF4 is set to 1 the interrupt occurred e When HRF4 1 IEF4 0 and the TMR2 halt release enabler HEF4 is set to 1 program will escapes from halt mode if CPU is in halt mode and then HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 STS4 After power on reset the default clock source of TMR2 is PH7 If watchdog reset occurred the clock source of TMR2 will still keep the previous selection The following table shows the definition of each bit in TMR2 instructions OPCODE Selectclock Initiate value of timer TM2Rx 0 AC2 AC1 ACO Rx3 Rx2 Rx1 Rx0 TM2 QHL O bit6 bits bits bit 41 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following table shows the clock source setting for TMR2 x8 X7 X6 clock source 01010 PH pO of 1 PH 201110 X FPH55 01111 FREQ 1 When the TMR2 clock is TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When
37. counter of RFC to AC and data memory specified by Rx Bit 3 RFC 7 Bit 2 RFC 6 Bit 1 RFC 5 Bit 0 RFC 4 Rx AC lt RFC 11 8 Loads the 3 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 11 Bit 2 RFC 10 Bit 1 RFC 9 Bit 0 RFC 8 Rx AC lt RFC 15 12 Loads the highest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 15 Bit 2 RFC 14 Bit 1 RFC 13 Bit 0 RFC 12 123 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 5 5 CPU CONTROL INSTRUCTIONS NOP Function Description HALT Function Description STOP Function Description SCA X Function Description no operation no operation Enters halt mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to port IOC SCF1 IOD SCF3 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When an interrupt is accepted to release the halt mode the halt mode returns by executing the RTS instruction after completion of interrupt service Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signals on the
38. enable the TMR1 SRF 9 build up the RR network and enable the counter HALT SRF 1 stop the counter when TMR1 underflows MRF1 10h read the content of the counter MRF2 11h 86 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E MRF3 12h MRF4 13h MSD 20h JB2 CNT1_OF check the overflow flag of counter JMP DATA_ACCEPT CNT1_OF DEC 2 decrease the TM1 value LDS 20h 0 SBC 1 JZ CHG RANGE change the clock source of TMR1 PLC 1 clear the halt release request flag of TMR1 JMP RE CNT 3 8 3 Enable Disable the Counter by Timer 2 TMR2 will control the operation of the counter in this mode When the counter is controlled by SRF 18 instruction the counter will start to operate until TMR2 is enabled and the first falling edge of the clock source gets into TMR2 When the TMR2 underflow occurs the counter will be disabled and will stop counting the CX clock at the same time This mode can set an accurate time period with which to count the clock numbers on the CX pin For a detailed description of the operation of TMR2 please refer to 2 12 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 18h SRF Ch SRF control Counter active 2 SF h os wh Yo Dh M Content of the counter Koo 2 M1 NH e UU C Halt release request counter starts Counting stops caused to count bythe Timer 2 underflow
39. gt E a 5 25 MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 13 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 1 1 2 1 2 BIAS amp STATIC AT AG BATTERY POWER SUPPLY MASK OPTION table POWER SOURCE 3 1 5V BATTERY BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 1 3 1 3 BIAS AT AG BATTERY POWER SUPPLY 14 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial cle
40. increases by 1 The range of X is from 000H to 7FFH JB1 X Function Program counter jumps to X in current page if AC1 1 Description If bit of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH JB2 X Function Program counter jumps to X in current page if AC2 1 Description If bit2 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH JB3 X Function Program counter jumps to X in current page if AC3 1 Description If bit3 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH JNZ X Function Program counter jumps to X in current page if AC 0 Description If the content of AC is not 0 jump occurs If O the PC increases by 1 The range of X is from 000H to 7FFH JNC X Function Program counter jumps to X in current page if CF 0 Description If the content of CF is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 7FFH 130 tenx technology inc Rev 1 0 2006 12 13 JZ X Function Description JC X Function Description JMP Function Description CALL P X Function Description RTS Function Description UM TM8725 E Program counter jumps to X in current page if AC 0 If the content of AC is 0 jump occurs If 1 the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to X in current page if CF 1 If the
41. index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUSA to DBUSH are all 0 when the input data of the data decoder is 0 7 LCP Lz HL The data of the index RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown below Table 4 3 2 1 The mapping table of LCP and LCD instructions DRUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSH 5 SF2 4h Turns off the LCD display 6 RF2 4h Turns on the LCD display 4 3 3 CONCRETE EXPLANATION Each LCD driver output corresponds to the LCD 1 6 duty panel and has 6 latches refer to The Figure shows Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of the segments in the LCD driver outputs is flexible In other words one of the data decoder outputs DBUSA to DBUSH is applied to the latch input L and one of the PSTBO to PSTB3Fh outputs are applied to clock CLK TM8725 provide a flash type instruction to update the LCD pattern When LCTX D LCBX D LCPX D and LCDX D instruction are executed the pattern of DBUS will be outputted to 16 latches Lz specified by D simultaneously D Specified range of latched 0 Lz 00h 0Fh 1 Lz 10h 1Fh 99 tenx technology inc Rev 1 0 2006 12
42. loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected AC Rx RX AC The contents of Rx and AC are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC HL HL AC The contents of HL and AC are binary added the result is loaded to AC and data memory HL HL indicates an index address of data memory Carry flag CF will be affected AC HL lt HL AC HL HL 1 The contents of HL and AC are binary added the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction OHL indicates an index address of data memory Carry flag CF will be affected AC Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC lt HL 1 The content of AC is binary subtracted from content of HL the result is loaded to AC e HL indicates an index address of data memory Carry flag CF will be affected 114 tenx technology inc Rev 1 0 2006 12 13 SUB HL Function Description SUB Rx Function Description SUB HL Function Description SUB Function Description ADN Rx Function Descript
43. low muxed with SEG28 SEG31 e Port IOC 4 pins with internal pull low low level hold muxed with SEG32 SEG35 IOC port had built in the input signal chattering prevention circuitry e PortIOD 4 pins with internal pull low muxed with SEG36 SEG39 IOD port had built in the input signal chattering prevention circuitry 6 8 level subroutine nesting 7 Interrupt function e External factors 4 INT pin Port IOC IOD amp KI input 3 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E e Internal factors 4 Pre Divider Timer1 Timer2 amp RFC 8 Built in EL light driver ELC ELP with SEG28 SEG29 9 Built in Alarm clock or single tone melody generator e BZB BZ with SEG30 SEG31 10 Built in resistance to frequency converter e RR RT RH Muxed with SEG24 SEG27 11 Built in key matrix scanning function e 1 16 Shared with SEG1 SEG16 12 KI1 Kl4 Muxed with SEG32 SEG35 13 Two 6 bit programmable timer with programmable clock source 14 Watch dog timer 15 Built in Voltage doubler halver tripler charge pump circuit 16 Dual clock operation Slow clock oscillation can be defined as X tal or external RC type oscillator by mask option Fast clock oscillation can be defined as 3 58MHz ceramic resonator internal R or external R type oscillator by mask option 17 HALT function 18 STOP function 1 3 APPLICATION B
44. release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 47 technology inc Rev 1 0 2006 12 13 2 e UM TM8725 E Start condition flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be outputted and the halt release enable flag 4 HEF4 is set beforehand To reset the start condition flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 or the SHE instruction must be used to reset the halt release enable flag 4 HEF4 Start condition flag 9 SCF9 SCF9 is set when a finish signal from mode 3 of RFC function causes the halt release request flag 6 HRF6 to be outputted and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the start condition flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 or the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of
45. setting each scanning cycle check two specified columns on key matrix The specified columns are defined by the setting of X2 and X4 X3X2X1 000 active K1 K2 columns simultaneously X3X2X1 001 active K4 columns simultaneously X3X2X1 110 active K13 K14 columns simultaneously X3X2X1 111 active K15 K16 columns simultaneously Xo don t care SPK Rx Function Sets Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s set the content of AC and Rx to specify the key matrix scanning output state for each SEGn pin in scanning interval The bit setting is the same as SPKX instruction and bit pattern of AC and Rx corresponding to SPKX is shown below Instruction Bit Bits Bit Bits Bit2 Bit Bito SPKRx AC2 AC1 ACO Rx3 Rx2 RxO SPKX X XT X6 X5 X4 X3 X2 X1 X0 SPK HL Function Sets Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s set the content of table ROM HL to specify the key matrix scanning output state for each SEGn pin in scanning interval The bit setting is the same as SPKX instruction and bit pattern of table ROM corresponding to SPKX is shown below Instruction Bit7 Bit Bits Bits Bits Bit2 Bit Bito 106 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E ALM X Function Sets buzzer output frequency Descriptio
46. signal SIE instruction Initial dear 60 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC or IOD ports or Key matrix Scanning 1 External INT pin interrupt request By using mask option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the signal on the INT pin change that matches the mask option will issue the HRF2 interrupt 2 is accepted and the instruction at address10H is executed automatically It is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 port IOC IOD interrupts request An interrupt request signal HRFO is delivered when the input signal changes at I O port IOC IOD specified by the SCA instruction In this case if the interrupt enabled by flag 0 IEFO is set to 1 interrupt 0 is accepted and the instruction at address 14H is executed automatically 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal generated in scanning interval If the interrupt enable flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 3 1 1 2 Internal interrupt fact
47. tenx technology inc Rev 1 0 2006 12 13 AND HL Function Description ADN Rx Function Description ADN HL Function Description ADN Function Description AND Rx Function Description AND HL Function Description AND HL Function Description UM TM8725 E AC lt HL AC HL HL 1 The contents of HL and AC are binary added the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction The result will not affect the carry flag CF OHL indicates an index address of data memory AC Rx lt Rx AC The contents of Rx and AC are binary added the result is loaded to AC and data memory Rx The result will not affect the carry flag CF AC HL HL AC The contents of HL and AC are binary added the result is loaded to AC and data memory HL The result will not affect the carry flag CF OHL indicates an index address of data memory AC HL HL AC HL HL 1 The contents of HL and AC are binary added the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction The result will not affect the carry flag CF OHL indicates an index address of data memory AC lt Rx amp AC The contents of Rx and AC are binary ANDed the result is loaded to AC AC lt HL 8
48. the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPC 1 SPC 2 SPC 4 SPC 8 Interrupt request 1004 10C2 IOCS SCF1 HALT released request chattering PH10 prevention PHS PH6 PLC 1 Interrupt accept scc intruction SCA intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex IOC2 to IOC4 are held at L level 78 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E When the signal changes at the input pins of IOC port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 and PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF1 At that time the chattering prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to 0 by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOC interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOC1 to IOC4 the input
49. the signal changed on INT pin causes the stop mode to be released respectively Example This example illustrates the stop mode released by port IOC 1 4 and INT pin Assume all of the pins in IOD and IOC have been defined as input mode PLC 25h Reset the HRFO HRF2 and HRF5 SHE 24h HEF2 and is set so that the signal change at INT or 1 4 pin causes start condition flag 4 or 8 to be set SCA 10h SEF4 is set so that the signal changes at port IOC cause the start conditions SCF1 to be set SRE ObOh SRF7 5 4 are set so that the signal changes at KI1 4 pins port IOC and INT pin cause the stop mode to be released 53 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E STOP Enter the stop mode JM Dee STOP release MSC 10h Check the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC that causes the stop mode to be released MCX 12h Check the signal change at 1 4 pins that causes the stop mode to be released 2 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM8725 when LCD is operating During the halt mode the program memory ROM is not in operation and only the oscillator circuit pre divider circuit sound circuit I O port chattering prevention circuit and LCD driver output circuit are in operation If the timer has started operating the timer counter stil
50. uu u uu 34 2 7 DATA MEMORY 35 2 8 WORKING REGISTER WR uu uuu u 36 2 9 ACCUMULATOR AC 36 2 10 ALU Arithmetic and Logic 36 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD 37 2 12 MERA TMR Em 38 2 13 TIMER Z TMR 4 cicero oce aya idu a aa 41 2 14 STATUS REGISTER STS u 45 2 15 CONTROL REGISTER 50 2 16 HALT FUNCTION 54 2 17 HEAVY LOAD FUNCTION u u u u u 55 2 18 STOP FUNCTION STOP u 56 2 49 BACK UIP FUNCTION uuu cac ise 57 Chapter 3 Control Function 59 3 1 INTERRUPT FUNCTION uu u uu uuu 59 3 2 RESET FUNCTION soci 64 3 3 CLOCK GENERATOR u u 68 3 4 BUZZER OUTPUT PINS U u u u uuu uu 70 3 5 INPUT OUTPUT PORTS sot tiec u uuu 72 1 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 6 EL PANEL DRIVER uu u uu uuu 82 3 7 EXTERNAL INT 2522 I u u u uu
51. 01 PXXX XXXX XXXX PC gt 000h 7FFh PC gt 800h BFFh AC3 2 11 Ctm FREQ AC3 2 10 Ctm PH15 0000 OXXX 2 01 Ctm PH3 AC3 2 00 Ctm PH9 AC1 0 Rx3 0 Set Timer1 Value TR7 6 11 Ctm FREQ TR7 6 10 Ctm PH15 0001 0000 0000 TR7 6 01 Ctm PH3 TR7 6 00 Ctm PH9 TR5 0 Set Timer1 Value X8 7 6 111 Ctm PH13 X8 7 6 110 Ctm PH11 X8 7 6 101 Ctm PH7 X8 7 6 100 Ctm PH5 001X XXXX XXXX X8 7 6 011 Ctm FREQ X8 7 6 010 Ctm PH15 X8 7 6 001 Ctm PH3 X8 7 6 000 Ctm PH9 X5 0 Set Timer1 Value 0100 OXXX XXXX Timer2 Rx amp AC 0101 0000 0000 Timer2 lt TQHL X8 7 6 111 Ctm PH13 X8 7 6 110 Ctm PH11 X8 7 6 101 Ctm PH7 X8 7 6 100 Ctm 5 011X XXXX X8 7 6 011 Ctm FREQ X8 7 6 010 Ctm PH15 X8 7 6 001 Ctm PH3 X8 7 6 000 Ctm PH9 Set Timer2 Value Enable HEF6 Enable HEF5 Enable HEF4 Enable HEF3 Enable HEF2 Enable HEF 1 Enable IEF6 Enable IEF5 Enable IEF4 1001 OXXX XXXX Enable IEF3 Enable IEF2 Enable IEF 1 Enable IEFO Reset PH15 11 Reset HRF6 0 Enable Cx Control Enable TM2 Control Enable Counter Enable RH Output 141 tenx technology inc Rev 1 0 2006 12 13 1100 PXXX XXXX XXXX 1000 101X OXXX XXXX 1100 00XX XXXX Instruction Machine Code Function En
52. 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle no matter the key is depressed or not and then set SCF7 to 1 X7Xs5X4 000 in this setting each scanning cycle only check one specified column K1 K16 on key matrix The specified column is defined by the setting of Xs Xo Xo 0000 active K1 column X3 Xo 0001 active K2 column Xo 1110 active K15 column Xo 1111 active K16 column X7X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xs Xo don t care 105 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 010 in this setting the key matrix scanning function will be disable X3 Xo don t care X7Xs5X4 10X in this setting each scanning cycle check 8 specified columns on key matrix The specified column is defined by the setting of X3 X3 0 active K1 K8 columns simultaneously 1 active K9 K16 columns simultaneously X2 Xo don t care X7X5X4 110 in this setting each scanning cycle check four specified columns on key matrix The specified columns are defined by the setting of X3 and X X3X2 00 active K1 K4 columns simultaneously X3X2 01 active K5 K8 columns simultaneously XsX 10 active K9 K12 columns simultaneously X3X2 11 active K13 K16 columns simultaneously X4 Xo don t care X7Xs5X4 111 in this
53. 13 UM TM8725_E Refer to Chapter 5 for detail description of these instructions Mask B option 1 Ma sk L Q CLK option 817 Mask option L Q Mask option E PSTBO PSTB3Fh Driver The Figure shows Sample Organization of Segment PLA Option 4 3 4 THE CONFIGURATION FILE FOR MASK OPTION When configuring the mask option of LCD PLA the cfg file provides the necessary format for editing the LCD configuration The syntax in cfg file is as follows SEG PSTB DBUS SEG Specifies the segment pin No 1 40 represents segment pin No C1 C6 represents common pin No When the common pin COM is specified as DC output pin assigned C1 C6 in this column C1 C6 represents COM1 COM6 respectively COM Specifies the corresponding latch in each segment pin Only 0 1 2 3 4 5 6 can be specified in this column 1 6 represents COM1 latch COM6 latch respectively 70 is for CMOS type DC output option and 10 is for P open drain DC output option PSTB Specifies the strobe data for the latch DBUS Specifies the DBUS data for the latch 100 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Chapter5 Detail Explanation of TM8725 Instructions Itis necessary to initialize the content of data memory after initial reset because the initial content of the data memory is unknown
54. 15pf 32168 Crystal 1 Xtal When backup flag BCF is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time but this will increase the power consumption Therefore the backup flag should be reset unless required otherwise The following table shows the power consumption of Crystal oscillator in different condition JAg power option Li power option option BCF 1 Increased Increased Increased BCF 0 Normal Normal Increased Initial reset Increased Increased Increased After reset Normal Normal Increased 2 2 1 2 External RC oscillator MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 2 RC XIN 2 RC 22 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock is a multiple type oscillator mask option which provides a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer I O port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to system clock generator only When the dual clock option is selected by mask option this oscillator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BC
55. 1627 50 1627 50 1627 50 1627 50 1627 50 1627 50 717 50 602 50 487 50 372 50 247 50 122 50 72 50 72 50 72 50 72 50 72 50 72 50 72 50 72 50 72 50 72 50 72 50 72 50 122 50 247 50 372 50 487 50 602 50 717 50 832 50 947 50 1062 50 1177 50 1292 50 1407 50 UM TM8725 E 5 14 14 SEG15 K15 SEG16 K16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 IOA1 CX SEG25 IOA2 RR SEG26 IOA3 RT SEG27 IOA4 RH SEG31 IOB4 BZ SEG32 IOC1 KI1 SEG33 IOC2 KI2 SEG34 IOC3 KI3 SEGS35 IOCA KIA SEG36 IOD1 SEG37 IOD2 SEG38 IOD3 SEG39 IODA SEG40 RESET INT TEST tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 1 7 PIN DESCRIPTION Nam lO Description BAK Positive Back up voltage At Li power mode connect a 0 1u capacitor to GND LCD supply voltage and positive supply voltage VDD1 2 3 In Ag Mode connect positive power to VDD1 In Li or ExtV power mode connect positive power to VDD2 RESET EX for external reset request signal built in internal pull down for external request signal n edge or rising edge triggered is defined by mask option Internal pull down or pull up resistor is defined by mask option TEST Test signal input Switching pins for supply the LCD driving voltage to the VDD1 2 3 pins CUP1 2 Connect the CUP1 and CUP2 pins with non polarized electrolytic capacitors when chip operated in 1 2 or 1 3 bias mode In no BIAS mod
56. A SRE AS 9 3 BR ZX tenx technology inc TM8725 4 Bit Micro Controller with LCD Driver User s Manual tenx technology inc tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E CONTENTS Chapter 1 General Description 3 1 1 GENERAL DESCRIPTION u u uuu uu 3 152 REATUBE 5 E E E EAEE 3 153 Ku cessive ces 4 1 4 BLOCK DIAGRAM u 5 1 5 PAD DIAGRAN 7 5 224 55 24 5 126 PAD COORDINATE his ee 6 1 7 PIN DESCRIPTION u u u uuu u u 7 1 8 CHARACTERISTICS J u u 8 1 9 TYPICAL APPLICATION CIRCUIT u u uuu u 12 Chapter2 TM8725 Internal System Architecture 13 2d POWER SUPPLY ae AS Od Sa ein 13 2 2 SYSTEM CLOCK 21 2 3 PROGRAM COUNTER PC U u u uuu u 29 2 4 PROGRAM TABLE MEMORY uuu uuu 30 2 5 INDEX ADDRESS REGISTER HLL u u uuu 32 2 6 STACK REGISTER STACK u uuu
57. A 3 0 2 V Output H Voh12i loh 10uA 1 2 3 4 V Voltage Voh3i loh 10uA 3 5 8 V Output M1 Vom12i lol h 10uA 1 2 1 0 1 4 V Voltage Vom13i lol h 10uA 3 COM n 1 8 2 2 V Output M2 Vom22i lol h 10uA 1 2 2 2 2 6 V Voltage Vom23i lol h 10uA 3 3 8 4 2 V Output L Vol12i lol 10uA 1 2 0 2 V Voltage Vol3i lol 10UA 3 0 2 V tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 1 9 TYPICAL APPLICATION CIRCUIT This application circuit is simply an example and is not guaranteed to work iF LCD Panel 358MHz m Crystal 1 6 SEG1 40 1 ELFknt External INT I O Port lt 1 16 KIl KM Key Scanning Key Ag power mode 1 3 Bias 1 6 Duty tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Chapter2 TM8725 Internal System Architecture 2 1 POWER SUPPLY TM8725 could operate at Ag Li and EXTV 3 types supply voltage all of these operating types are defined by mask option The power supply circuitry also generates the necessary voltage level to drive the LCD panel with different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias and no bias application 2 1 1 Ag BATTERY POWER SUPPLY Operating voltage range 1 2V 1 8V For different LCD bias application the connection diagrams are shown below 2 1 1 1 NO LCD BIAS NEED AT Ag BATTERY POWER SUPPLY Application on 4 a a
58. AS 1 NO BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased 18 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 1 3 2 1 2 BIAS AT EXT V POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 19 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 1 3 3 1 3 BIAS AT EXT V POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 20 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 2 SYSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below Stop Halt Fast instruction Slowinstructio
59. C to decimal format The result in the data memory address 10H is O and in the CF is 1 This represents the decimal number 10 Instructions DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0s AC 9 6s AC lt F AC A Example 2 LDS 10 1 Load immediate data 1 to the data memory address 10H LDS 11h 2 Load immediate data 2 to the data memory address 11H and AC SF 1h Set CF to 1 which means no borrowing has occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H R10 AC FH CF 0 DAS 10h Convert the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 37 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 12 TIMER 1 TMR1 Re load RL1 S TMS instruction IEF1 D Initial reset TMR1 Interrupt FREQ 6 bit binary down PH3 counter PH5 PH7 PH m SCF5 PH13 Halt release PH15 Operand data x5 x0 TMS instruction Interrupt acc
60. Content of Accumulator bit n Program Counter Complement of content of Accumulator Address of program or control data Watch Dog Timer Enable Flag 7 segment decoder for LCD Address Y of working register System clock for instruction Address of data RAM specified by HL Interrupt Enable Flag Back up Flag HALT Release Flag Generic Index address register HALT Release Enable Flag Content of generic Index address register Address of LCD PLA Latch Content of lowest nibble Index register STOP Release Enable Flag Content of middle nibble Index register Start Condition Flag Content of highest nibble Index register Clock Source of Chattering prevention ckt T HL Address of Table ROM Clock Source of Frequency Generator H T HL High Nibble content of Table ROM Switch Enable Flag L T HL Low Nibble content of Table ROM Frequency Generator setting Value TMR Timer Overflow Release Flag Clock Source Flag Ctm 1 Source of Timer Program Page PDV JPre Divider RFC Overflow Flag STACK Content of stack Resistor to Frequency counter TM1 Timer 1 Bit data of Resistor to Frequency counter TM2 Timer 2 Bit content of Table ROM specified by HL 144 tenx technology inc Rev 1 0 2006 12 13
61. E MASK OPTION table Pull low function option Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE Data Bus a c Mate M is mask option ntra 2 IPD OPD This figure shows the organization of IOD port 80 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 3 5 4 1 Chattering Prevention Function and Halt Release The port IOD is capable of preventing high low chattering of the switch signal applied on IOD1 to IOD4 pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOD port are defined as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPD 1 IEF Interrupt one HRED SPD 4 Edge request SPD 8 dete ct R ODI 4 7 1002 1 4 edge dectect 2 SCF3 HALT released __ S Qm request IOD4 chattering pu prevention Boe orii a accept BCC intruction E SCA intruction
62. Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been defined as input mode PLC 7 Clear all of the flags SCA 10h enable the interrupt request of IOC SIE 7Fh enable all interrupt requests pD PH all interrupts are requested simultaneously Interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 77h Enable the interrupt request except the predivider Interrupt caused by the TM1 underflow occurs and interrupt service is concluded SIE 75h Enable the interrupt request except the predivider and TMR1 Interrupt caused by the TM2 underflow occurs and interrupt service is concluded SIE 65h Enable the interrupt request except the predivider TMR1 and TMR2 Interrupt caused by the RFC counter overflow occurs and interrupt service is concluded SIE 25h Enable the interrupt request except the predivider TMR1 TMR2 and the RFC counter Interrupt caused by the IOC port and interrupt service is concluded SIE 24h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter and IOC port Interrupt caused by the INT pin and interrupt service is concluded SIE 20h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter IOC port and INT Interrupt caused by the Key matrix Scanning and interrupt service is concluded All inter
63. HRF2 TM1 underflow HRF3 p HRF1 Halt release condition When the halt release enable flag 6 HEF6 is set a finish signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF1 to HEF4 are set to 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMR1 the signal change at the INT pin an overflow signal from the pre divider an underflow signal from TMR2 H signal from OR ed output of KI1 4 latch signals When the stop release enable flag 5 SRF5 and the HEF2 are set the signal change at the INT pin can cause the stop mode to be released When the stop release enable flag 7 SRF7 and the HEF5 are set the H signal from OR ed output of K1 4 latch signals can cause the stop mode to be released 2 15 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 7 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset by SIE instruction The bit pattern of control register 3 CTL3 is shown below Interrupt enable flag IEF6 IEF5 IEFA Enable the interrupt Enable the interrupt request caused by request caused by RFC counter to be TMR2 underflow finished HRF6 HRF4 Enable the interrupt Interrupt request flag request caused by Key Scanning HRF5 Interrupt fla Interrupt 6 Interrupt 4 Interrupt 4 g 52 tenx technology inc R
64. LK of the system clock generator will be switched to CF clock and the clock source for other functions will still come from XT clock Halt mode stop mode or SLOW instruction execution will stop this oscillator and the system clock BCLK will be switched to XT clock There are 3 type oscillators can be used in slow clock oscillator selected by mask option 2 2 2 1 External 3 58MHz Ceramic Resonator oscillator MASK OPTION table Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 4 3 58MHz Ceramic Resonator 3 58MHz Ceramic Resonator Note 1 Don t use 3 58MHz Ceramic Resonator as the oscillator when Ag battery option is used Note 2 When the program has to reset the BCF flag to 0 in Li battery power mode don t use 3 58MHz Ceramic Resonator as the oscillator 2 2 2 2 RC oscillator with External Resistor connection diagram is shown below MASK OPTION table Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 3 EXTERNAL RESISTOR R Extemal Resistor 23 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 2 2 3 Internal RC Oscillator MASK OPTION table For 250KHz output frequency Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 1 INTERNAL RESISTOR FOR 250KHz For 250KHz output frequency Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 2 INTERNAL RESISTOR FOR 500KHz CFOUT CFIN N C Intern
65. RF1 18 PLC Y Re load In this example S W enters the halt mode to wait for the underflow of TMR1 LDS 0 0 initiate the underflow counting register PLC 2 SHE 2 enable the HALT release caused by TMR1 TMSX 34h initiate the TMR1 value 52 and clock source is 9 SF 80h enable the re load function RE LOAD HALT INC 0 increase the underflow counter PLC 2 clear HRF 1 JB3 END TM1 if the TMR1 underflow counter is equal to 8 exit subroutine JMP RE LOAD END 1 RF 80h disable the re load function 40 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 13 TIMER 2 TMR2 The following figure shows the TMR2 organization Re load RL2 S Q TM2 instruction IEF Initial reset TM2 6 bit binary down Interrupt counter FREQ 3 5 SCF 499 Ma Halt release 13 15 Operand Data X5 X0 TM2 instruction Operand Data X8 X7 X6 TM2 instruction Interrupt accept signal PLC 10h instruction nitial reset DED QL TENX Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 2 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TM2 or TM2X instruction Once the TMR2 counts down to 3Fh it stops counting then generates an underflow signal and the halt release request flag 4 HRF4 will
66. Timer Calendar Calculator Thermometer 4 tenx technology inc Rev 1 0 2006 12 13 1 4 BLOCK DIAGRAM B1 4 ELC ELP BZB BZ B PORT L DRIVER ALARM Les Lo x PRE 4 6 BITS PRESET DIVIDER TIMER 1 amp 2 OSCILLATOR h d D CUP0 1 XTIN OUT CFIN QUT RESET INT A1 4 cx RR RT RH C 1 4 KI1 4 A PORT C PORT RFC KEY IN Pace amasisa Is Gl 4 BUS 1 5 PAD DIAGRAM L L D D D L D L O L D O L CONTROL CIRCUIT D1 4 lj NEM COM 1 6 UM TM8725 E SEG1 40 VDD1 3 LCD DRIVER SEGMENT PLA j 12 BITS PROGRAM H COUNTER DJ DJ DJ DJ DJ DJ DJ DJ DJ D O L L L L 10 The substrate of chip should be connected to GND OOOOOOOOOOOOOO0000D W FREQUENCY INDEX ROM DATA RAM ALU GENERATOR 256 16 N X 8 BITS 384 X 4 BITS s 8 LEVELS INSTRUCTION STACK DECODER 1 PROGRAM ROM 1024 128 16 5 8725 BLOCK DIAGRAM w 0 gt 16 technology inc Rev 1 0 2006 12 13 1 6 PAD COORDINATE SEG1 K1 SEG2 K 2 SEG3 K3 SEG4 SEG5 SEG6 SEG7 K7 SEG8 K8 SEG9 K9 SEG10 SEG11 SEG12 SEG13 K13 72 50 72 50 72 50 72 50 197 50 322 50 447 50 562 50 677 50 792 50 907 50 1022 50 1137 50 1252 50 1377 50 1502 50 1627 50 1627 50 1627 50 1627 50 1627 50 1627 50
67. XX lt Rx AND AC AND HL 0010 1010 1000 0000 lt R HL AND AC AC lt R HL AND AC AND HL 0010 1010 1100 0000 HL lt HL 1 AND Rx 0010 1011 OXXX lt Rx AND AC HL 0010 1011 1000 0000 JAC R HL lt R HL AND AC AC R HL lt R HL AND AC AND HL 0010 1011 1100 0000 HL lt HL 1 EOR Rx 0010 1100 XXXX JAC lt Rx EOR AC EOR HL 0010 1100 1000 0000 lt R HL EOR AC AC lt R HL EOR AC EORZ 0010 1100 1100 0000 HL lt HL 1 EOR Rx 0010 1101 OXXX XXXX AC Rx lt Rx EOR AC EOR 0010 1101 1000 0000 JAC R HL lt R HL EOR AC AC R HL lt R HL EOR AC EOR HL 0010 1101 1100 0000 HL lt HL 1 OR Rx 0010 1110 OXXX JAC lt Rx OR AC OR HL 0010 1110 1000 0000 lt R HL OR AC AC lt R HL OR AC OR HL 0010 1110 1100 0000 HL lt HL 1 OR Rx 0010 1111 OXXX JAC Rx lt Rx OR AC OR HL 0010 1111 1000 0000 JAC R HL lt R HL OR AC AC RQHL lt R HL OR AC OR HL 0010 1 1100 0000 HL lt HL 1 Ry D 0011 0000 DDDD YYYY JAC lt Ry D CF ADCI IRy D 0011 0001 DDDD AC Ry lt 0 138 tenx technology inc Rev 1 0 2006 12 13 Instruction Machine Code Function UM TM8725_E Flag Remark
68. able RT Output Enable RR Output UM TM8725_E Flag Remark EHM ETP ERR 110 1101 Enable SRF7 Enable SRF5 Enable SRF4 Enable SRF3 SRF7 KEY_S SRF5 INT SRF4 C Port SRF3 D port 110 1110 0000 0000 High Speed Clock 110 1110 1000 0000 Low Speed Clock 110 1111 XXXX XXXX force NOP if X7 0 IDBF7 0 111 0000 OXXX XXXX Rx amp AC 111 0001 0000 0000 lt T HL 1111 0010 XXXX X6 1 X6 0 X7 5 4 000 X7 5 4 001 X7 5 4 010 X7 5 4 10X X7 5 4 110 X7 5 4 111 KEY_S release by scanning cycle KEY S release by normal key scanning Set one of KO1 16 71 by X3 0 Set all 1 Set all Hi z Set eight of KO1 16 1 by X3 X320 gt KO1 8 X321 gt KO9 16 Set four of KO1 16 1 by X3 2 X3 2 00 gt KO1 4 X3 2 01 gt KO5 8 X3 2 10 gt KO9 12 X3 2 11 gt KO13 16 Set two of KO1 16 1 by X3 2 1 X3 1 000 gt KO1 2 X3 1 001 gt KO3 4 X3 1 010 gt KO5 6 X3 1 011 gt KO7 8 X3 1 100 gt KO9 10 X3 1 101 gt KO11 12 X3 1 110 gt KO13 14 X3 1 111 gt KO15 16 1111 0100 0000 0000 PC lt STACK CALL Return 1111 0100 1XOX XXXX X6 1 X6 0 X4 1 X3 1 X2 1 0 001 X2 1 0 010 X2 1 0 100 Cfq BCLK Cfq PHO Set P C Cch Set P D Cch Cch PH10 Cch PH8 Cch PH6 1111 0101 000X X000 Enable SEF4 Enable SEF3 1111 0101 100X XXXX
69. ag AC Zero flag Z Read only Read only Read only 2 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 SCF1 SCF2 and the backup flag The MSB instruction can be used to transfer data of status register 2 STS2 to the accumulator AC and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2 The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition flag 3 flag 2 flag 1 SCF3 SCF2 SCF1 Backup flag BCF Halt release Halt release Halt release caused by the caused by caused by the IOD port SCF4 5 6 7 9 IOC port Read only Read only Read only Read only Start condition flag 3 SCF3 When the SCA instruction specified signal change occurs at port IOD to release the halt mode SCF3 will be set Executing the SCA instruction will cause SCF3 to be reset to O Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 e Start condition flag 2 SCF2 When a factor other than port IOA and IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags in SCF4 5 6 7 9 are set to 1 SCF2 will also be set to 1 simultaneou
70. ag 1 HEF1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the halt release enable flag 3 HEF3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag 3 HRF3 or the SHE instruction must be used to reset the halt release enable flag 3 4 The 15th stage s content of the pre divider The MSC instruction is used to transfer the contents of status register 3 STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3 STS3 Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 7 15th stage ofthe Start condition flag 5 Start condition flag 4 SCF7 pre divider SCF5 SCF4 Halt release caused Halt release caused Halt release caused by TMR1 underflow by INT pin by pre divider overflow Read only Read only Read only Read only 2 14 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags Start condition flag 8 SCF8 SCF8 is set to 1 when any one of KI1 4 1 0 KI1 4 1 in LED mode 1 4 0 in LCD mode causes the halt release request flag 5 HRF5 to be outputted and the halt
71. again IPC JBO wait_scan_again HALT PLC 20h RTS Ofh Disable all the pull down device on internal IOC port Set all of the IOC pins as output mode 10h Generate HALT released request when key depressed Scanning all columns simultaneous in each cycle 20h Clear HRF5 20h Set HEF5 wait for the halt release caused by key matrix 10h Check SCF8 SKI ski_release 10h read KI1 4 input latch state ki1_release ki2_release ki3_ release ki4_release 40h Check key depressed on K1 column 20h Clear HRF5 to avoid the false HALT released wait scan again 10h ki seg1 4fh 20h wait scan again 10h kil seg16 Waiting for the next key matrix scanning cycle The waiting period must longer than key matrix scanning cycle Read KI1 input latch state Only enable SEG 16 scanning output Clear HRF5 to avoid the false HALT released Wait for time over halt LCD clock cycle to sure Read KI1 input latch state 92 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Chapter 4 LCD DRIVER OUTPUT The number of the LCD driver outputs in TM8725 is 40 segment pins with 6 common pins All of these output pins could also be used as DC output ports mask option If more than one of LCD driver output pin was defined as DC output the following mask option must be selected MASK OPTION table When more than one of SEG or COM pins had been used to drive LCD panel 1 LCD When all of SEG an
72. age Input Voltage CFIN at Li Battery or EXT V Mode 0 8xVDD2 VDD2 0 0 2xVDD2 Input Voltage Input L H L H L H L H L H L Voltage RC Mode 0 8xVDDO VDDO lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt 0 2xVDDO Operating Freq Crystal Mode A N RC Mode 1000 A lI N CF Mode 4 INTERNAL RC FREQUENCY RANGE Option Mode 3580 250KHz 500KHz tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 5 ELECTRICAL CHARACTERISTICS at 1 VDD1 1 2V Ag at 2 VDD2 2 4V Li at 3 VDD2 4V Ext V Input Resistance Name Symb Condition RIIh 1 Vi 0 2VDD1 1 L Level Hold Tr IOC RIIh2 Vi 0 2VDD2 2 RIIh3 Vi 0 2VDD2 23 Rmad1 Vi VDD1 1 IOC Pull Down Tr Rmad2 Vi VDD2 2 Rmad3 Vi VDD2 3 Rintu1 Vi VDD1 1 INT Pull up Tr Rintu2 Vi VDD2 2 Rintu3 Vi VDD2 3 Rintd1 Vi GND 1 INT Pull Down Tr Rintd2 Vi GND 2 Rintd3 Vi GND 3 Rres1 Vi GND or VDD1 1 Vi GND or VDD2 2 Vi GND or VDD2 3 RES Pull Down R Rres2 Rres3 6 DC Output Characteristics Name Condition Port iat loh 200uA 1 eke loh 1mA 2 loh 3mA 3 5 6 lol 400uA 1 SEG1 40 lol 2mA 2 lol 6mA 3 Output L Voltage
73. al FREQUENCY RANGE OF INTERNAL RC OSCILLATOR Option Mode 250KHz 1 2V 1 5V 300KHz 350KHz 400KHz 2 4V 5 0V 200KHz 250KHz 300KHz 500KHz 1 2V 1 5V 500 2 600 2 700KHz 2 4V 5 0V 400KHz 500 2 600 2 2 2 3 COMBINATION THE CLOCK SOURCES There are three types of combination of the clock sources that can be selected by mask option 2 2 3 1 Dual Clock MASK OPTION table Mask Option name Selected item CLOCK SOURCE 3 DUAL The operation of the dual clock option is shown in the following figure When this option is selected by mask option the clock source BCLK of system clock generator will switch between XT clock and CF clock according to the user s program When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically The XT clock provides the clock to the pre divider timer I O port chattering prevention and LCD circuitry in this option 24 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Halt Halt Halt mode Slow mode Slow Fast mode XTOSC active XTOSC active XTOSC active CFOSC stop HALT CFOSC stop Fast CFOSC active released Stop pre Stop released release Reset Reset state Reset Stop mode XTOSCiactive q XTOSC stop Bead reset CFOSC stop CFOSC stop eset pin reset Watchdog timer reset Key reset State Diagram of Dual Clock Option was shown on above figure After executing FAST i
74. alue error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 The 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR1 clock is FREQ TMR1 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 39 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 12 2 RE LOAD OPERATION TMR1 provides the re load function which can extend any time interval greater than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load func
75. ar mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 2 11 BATTERY POWER SUPPLY Operating voltage range 2 4V 3 6V For different LCD bias application the connection diagrams are shown below 2 1 2 1 NO BIAS AT LI BATTERY POWER SUPPLY Application 1 p Z e 0 mo 5 e 8 8 5 8 MASK OPTION table Mask Option name Selected item POWER SOURCE 2 BATTERY OR HIGHER BIAS 1 NO BIAS Note The input output ports operate between GND and VDD2 15 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 1 2 2 1 2 BIAS LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin ackup flagBCF MASK OPTION table POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size At the backup flag set mode the operating current is increased T
76. ata on this port will not be affected while the program entered stop mode or LCD turn off mode The Figure shows The Figure shows CMOS Output Type P Open Drain Output Type Only unused COM and SEG pad could be defined as DC output pin The COM pad sequence for LCD driver could not be interrupted when defined the COM pads as the DC output port For example when the LCD lighting system is specified as 1 5 duty the used COM pad for LCD driver must be COM1 COM5 Only COMG pad could be defined as DC output port refer to section 4 3 4 95 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 4 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION Explained below is how the LCD driver section operates when the instructions are executed HL DBUSA DBUS Ista bus decoder Strobe data related robe 101014 a instruction Segment PLA This Figure shows Principal Drawing of LCD Driver Section The LCD driver section consists of the following units Data decoder to decode data supplied from RAM or table ROM e Latch circuit to store LCD lighting information 101014 decoder to decode the Lz specified data in the LCD related instructions which specifies the strobe of the latch circuit Multiplexer to select 1 2duty 1 3duty 1 4duty 1 5duty 1 6duty LCD driver circuitry Segment PLA circuit connected between data decoder LO to L4 decoder and la
77. before turned off These two instructions will not affect the content stored in the latch circuitry When the LCD is turned off by executing RF2 4h instruction the program could still execute LCT LCB LCP and LCD instructions to update the content in the latch circuitry and the new content will be outputted to the LCD while the display is turned on again In stop state all COM and SEG outputs of LCD driver will automatically switch to the GND state to avoid the DC voltage bias on the LCD panel 4 3 2 Relative Instructions 1 LCT Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 2 LCB Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUSA to DBUSH are all 0 when the input data of the data decoder is O 3 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry The data of the RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown below 98 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 5 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 6 LCB Lz HL Decodes the
78. cation When the heavy load function is performed the current dissipation will increase Table 2 17 2 Ag power option initialreset After reset STOP mode SF2 RF2 eer Internal logic Peripheral logic Table 2 17 3 Li power option lnitialreset After reset Stop mode SF2 RF2 ar Gss ril Peripheral logic 55 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Table 2 17 4 EXT V power option Initial reset After reset Stop mode SF2 RF2 L Bor 1 f 01010 Note When the program enters the stop mode the BCF will set to 1 automatically to insure that the low speed oscillator will start up in a proper condition while stop release occurs 2 18 STOP FUNCTION STOP The stop function is another solution to minimize the current dissipation for TM8725 In stop mode all of functions in TM8725 are held including oscillators All of the LCD corresponding signals COM and Segment will output L level In this mode TM8725 does not dissipate any power in the stop mode Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins defined as input mode of IOD and IOC ports must be in the L state and no stop release signal SRFn should be delivered The CPU will then enter the stop mode
79. ce such as Li battery or alkali battery is used During back up mode the 32 768KHz Crystal oscillator will add an extra buffer in parallel and switch the internal power BAK from VDD1 to VDD2 Li power option only In this condition all of the functions in TM8725 will work under VDD voltage range this will cause TM8725 to get better noise immunity For shorten the start up time of 32 768 KHz Crystal oscillator TM8725 will set the BCF to 1 during reset cycle and reset BCF to 0 after reset cycle automatically in Ag and Li power mode option In EXT V power mode option however BCF is set to 1 by default setting and can not be reset to 0 and BCF will be reset to 0 by default setting during normal operation Table 2 17 1 The back up flag status in different conditions Agoption Lioption EXT Voption Remark SF 2 executed BCF 1 BCF 1 BCF 1 RF 2 executed BCF 0 BCF 0 0 For low power consumption application reset BCF to 0 is necessary the 32 768KHz Crystal oscillator operates with a normal buffer only so switch the internal power BAK to VDD1 Li power option only In this condition only peripheral circuitry operates under VDD voltage range the other functions will operate under 1 2 VDD voltage range In Ag and EXT V power options the internal power BAK will not be affected by the setting of BCF With Li power option it is necessary to connect a 0 1uf capacitor from BAK power pin to GND for the backup mode appli
80. content of CF is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to P 800h X Unconditional jump When P 0 page 0 the program jump to address X 000H to 7FFH When P 1 page 1 the program jump to address 800h X 800H to BFFH STACK lt 1 Program counter jumps to P 800h X A subroutine is called When P 0 page 0 the program jump to address X 000H to 7FFH When P 1 page 1 the program jump to address 800h X 800H to BFFH PC lt STACK A return from a subroutine occurs 5 9 MISCELLANEOUS INSTRUCTIONS SCC X Function Description Setting the clock source for IOD and IOC chattering prevention PWM output and frequency generator The following table shows the meaning of each bit for this instruction Bit pattern Clock source setting Bit pattern Clock source setting comes from the system The clock source of frequency generator comes from the PHO Refer to section 3 3 4 for 0 The clock source of frequency generator clock BCLK 131 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Bit pattern Clock source setting Bit pattern Clock source setting X4 X3 01 Chattering prevention X4 X3 10 Chattering prevention clock X2 X1 X0 001 clock of IOD port PHO 2 1 0 001 of IOC port PHO X2 X1 X0 010 clock of IOD port PH8 X2 X1 X0 010 of IOC port PH8 X2 X1 X0 100 cloc
81. ctively and selected by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX SEG25 IOA2 RR SEG26 IOA3 RT SEG27 IOA4 RH 3 8 1 RC Oscillation Network The RFC circuitry may build up 3 RC oscillation networks through RR RT or RH and CX pins with external resistors Only one RC oscillation network may be active at a time When the oscillation network is built up executing SRF 1h SRF 2h SRF 4h instructions to enable RR RT RH networks respectively the clock will be generated by the oscillation network and transferred to the 16 bit counter through the CX pin It will then enable or disable the 16 bit counter in order to count the oscillation clock 85 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Build up the RC oscillation network 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins for RC networks respectively The RR RT RH pins will become of a tri state type when these networks are disabled 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and 16 bit counter The RC oscillation network will not operate if these instructions have not been executed and the RR RT RH pins output 0 state at this time To get a better oscillation clock from the CX pin activate the output pin for each RC n
82. d 5 6 pins had been used for DC output port Mask Option name Selected item LCD ACTIVE TYPE 2 O P During the initial reset cycle all of LCD s lighting system may be lighted or unlighted by mask option All of the LCD output will keep the initial setting until the LCD relative instructions are executed to change the output data MASK OPTION table Mask Option name Selected item LCD DISPLAY IN RESET CYCLE 1 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 LCD LIGHTING SYSTEM IN TM8725 There are several LCD lighting systems could be selected by mask option in TM8725 they are 1 2 bias 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 4 duty 1 2bias 1 5duty 1 2bias 1 6duty 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5duty 1 3 bias 1 6duty 1 3 bias 1 7duty All of these lighting systems are combined with 2 kinds of mask options the one is LCD DUTY CYCLE and the other is BIAS MASK OPTION table LCD duty cycle option LCD DUTY CYCLE 1 O P LCD DUTY CYCLE 2 DUPLEX note 1 2 duty LCD DUTY CYCLE 3 1 3 DUTY LCD DUTY CYCLE 4 1 4 DUTY LCD DUTY CYCLE 1 5 DUTY 1 6 DUTY LCD DUTY CYCLE LCD DUTY CYCLE 1 7 DUTY 1 8 DUTY 5 LCD DUTY CYCLE 6 7 8 93 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E LCD bias option Mask Option name Selected item BIAS 1 NO BIAS 2 1 2 BIAS 3 1 3 BIAS BIAS BIAS The frame frequency for each
83. d CF are binary added the result is loaded to AC and data memory HL Carry flag CF will be affected HL indicates an index address of data memory AC HL HL AC CF HL 1 The contents of HL AC and CF are binary added the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected OHL indicates an index address of data memory AC lt Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC lt HL AC B CF The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC OHL indicates an index address of data memory Carry flag CF will be affected 112 tenx technology inc Rev 1 0 2006 12 13 SBC HL Function Description SBC Rx Function Description SBC HL Function Description SBC Function Description ADD Rx Function Description ADD HL Function Description UM TM8725_E AC lt HL AC B CF HL HL 1 The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be af
84. data at the port IOC must be read into the RAM immediately after the halt mode is released 3 5 4 IOD PORT IOD1 IOD4 pins are MUXed with SEG36 SEG37 SEG38 and SEG39 pins respectively by mask option MASK OPTION table SEG36 IOD1 2 IOD1 2 IOD2 SEG37 IOD2 SEG38 IOD3 2 IOD3 SEG39 IOD4 2 IOD4 After the reset cycle the IOD port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPD instruction Executed OPD instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IPD instructions may store the signals applied to the IOD pins in the specified data memory When the IOD pins are defined as the output executing IPD instruction will save the data stored in the output latches in the specified data memory Before executing SPD instruction to define the IOD pins as output the OPD instruction must be executed to output the data to those output latches This will prevent the chattering signal when the IOD pins change to output mode IOD port had built in pull low device for each pin and that is selected by mask option Enable or disable this device by executing SPD instruction When the IOD pin has been defined as the output mode the pull low device will be disabled 79 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_
85. dress register is a write only register CPHL X instruction could specified an 8 bit immediate data to compare the content of H and L When the result of comparison is equivalent the instruction that behind CPHL X will be skipped NOP if not the instruction behind CPHL X will be executed normally Note In the duration of comparison the index address all the interrupt enable flags IEF has to be cleared to avoid malfunction The comparison bit pattern is shown below CPHL X 32 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Example Mn ES HL 30h CPHL 30h SIE Oh disable IEF JMP able1 this instruction will be force as NOP JMP lable2 this instruction will be executed and than jump to lable2 Wu asss s S D D s S s S s s a Ste Ass Va 33 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stack register are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the fir
86. e application leave these pins opened Time base counter frequency clock specified LCD alternating XIN frequency Alarm signal frequency or system clock oscillation XOUT The usage of 32KHz Crystal oscillator or external RC oscillator is defined by mask option CFIN System clock oscillation for FAST clock only or DUAL clock operation CFOUT The usage of 3 58MHz ceramic resonator oscillator or external R type oscillator is defined by mask option 1 6 28 cowi 6 0 Output pins for driving the common pins of the LCD panel COM5 6 could be defined as COMS or Open Drain type output SEG1 40 Output pins for driving the LCD panel segment UU 1 input pin and 3 output pins for RFC application muxed with 5 24 27 ELC ELP Output port for El panel driver muxed with SEG28 29 BZBBZ 0 Output port for alarm clock single tone melody generator muxed with SEG30 31 K1 16 O Output port for key matrix scanning Shared with SEG1 SEG16 4 Input port for key scanning Muxed with SEG32 SEG35 GND P Negative supply voltage 7 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 1 8 CHARACTERISTICS 1 ABSOLOUTE MAXIMUM RATINGS GND 0V Name Symbol Range Unit VDD1 0 3 to 5 5 V Maximum Supply Voltage VDD2 0 3 to 5 5 V VDD3 0 3 to 8 5 V Maximum Input Voltage Vin 0 3 to VDD1 2 0 3 V Ma
87. e result is loaded to AC HL indicates an index address of data memory AC lt HL AC HL HL 1 The contents of HL and AC are binary ORed the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Rx lt Rx AC The contents of Rx and AC are binary Ored the result is loaded to AC data memory Rx AC HL lt HL AC The contents of HL and AC are binary ORed the result is loaded to AC and data memory HL HL indicates an index address of data memory AC HL lt HL AC HL HL 1 The contents of HL and AC are binary ORed the result is loaded to AC and data memory HL 118 tenx technology inc Rev 1 0 2006 12 13 ADCI Ry D Function Description ADCI Ry D Function Description SBCI Ry D Function Description SBCI Ry D Function Description ADDI Ry D Function Description ADDI D Function Description UM TM8725_E The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC lt Ry D CF D represents the immediate data The contents of Ry D and CF are binary ADDed the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry lt Ry D CF D represents the immediate data The conten
88. enable flag 4 Switch enable flag 3 SEF4 SEF3 Enables the halt release Enables the halt release caused by the signal caused by the signal change on IOC port change on IOD port Write only Write only 50 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following figure shows the organization of control register 1 CTL1 Edge HALT loc Released SEF4 Request SCA 10h Interrupt request Edge IOD detector PLC 1 SEF3 SCF3 SCA 8h Interrupt accept 2 15 1 1 The Setting for Halt Mode If the SEF4 SEF3 is set to 1 the signal changed on IOC IOD port will cause the halt mode to be released and set SCF1 SCF3 to 1 Because the input signal of IOC IOD port were ORed so it is necessary to keep the unchanged input signals at 0 state and only one of the input signal could change state 2 15 1 2 The Setting for Stop Mode If SRF4 SRF3 and SEFA SEF3 are set the stop mode will be released to set the SCF1 SCF3 when a high level signal is applied to one of the input mode pins of IOC IOD port and the other pins stay in O state After the stop mode is released TM8725 enters the halt condition The high level signal must hold for a while to cause the chattering prevention circuitry of IOC IOD port to detect this signal and then set SCF1 SCF3 to release the halt mode or the chip will return to the stop mode again 2 15 1 3 Interrupt for CTL1 The control register
89. ept signal PLC 2 instruction Initial reset Operand data 8 7 6 TMS instruction This figure shows the TMR1 organization 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag 1 HRF1 to 1 and then stop to count down When HRF1 1 and the TMR1 interrupt enable flag IEF1 1 the interrupt is generated When HRF1 1 if the IEF1 0 and the TMR1 halt release enable HEF1 1 program will escapes from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurred the clock source of TMR1 will still keep the previous selection The following table shows the definition of each bit in TMR1 instructions OPCODE Selectclock Initiate value of timer TMS Rx 0 AC3 AC2 AC1 ACO Rx3 R2 Rx0 TMS O bit6 bit5 bit3 bit2 bito 38 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following table shows the clock source setting for TMR1 x8 X7 X6 clock source 01010 PH pO of 1 PH 201110 X FPH55 01111 FREQ 1 When the TMR2 clock is TMR2 set time Set v
90. equency in 1 6 duty type Mask Option name LCD frame frequency Selected item 1 SLOW Remark alternating frequency 21Hz LCD frame frequency 2 TYPICAL 42Hz LCD frame frequency 2 FAST 85Hz LCD frame frequency 2 0Hz LCD not used tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments Maximum Number of FCD Lighting Syst m Driving LCD Segments 1 2bias 1 3duty 123 Connect VDD3 to VDD2 ne s C T 3biasi 3duy 423 J T 3biast Aduy 164 X s T3biasbduy 205 9 3 1 35 81 6 24 When choosing the LCD frame frequency it is recommended to choice the frequency that higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 4 2 DC OUTPUT TM8725 permits LCD driver output pins COM5 COM6 and SEG1 5 40 to be defined as CMOS type DC output or P open drain DC output ports by mask option In this case it is possible to use some LCD driver output pins for DC output and the rest LCD driver output pins for LCD driver Hefer to 4 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output the output d
91. es the 16 bit counter counter X3 must be set to 1 bit counter when this bit is set to 1 X5 1 The 16 bit counter is controlled by X5 0 Disables the CX pin to control the the signal on CX pin X3 must be 16 bit counter set to 1 when this bit is set to 1 Note X4 and X5 can not be set to 1 at the same time 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx Function lt Rx Description The content of Rx is loaded to AC and the working register specified by Ry MRW Rx Function AC R HL lt Rx Description The content of data memory specified by Rx is loaded to AC and data memory specified by HL 108 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E MRW HL Rx Function Description MWR Rx Ry Function Description MWR Rx HL Function Description AC R HL Rx HL HL 1 The content of data memory specified by Rx is loaded to AC and data memory specified by HL The content of index register HL will be increment automatically after executing this instruction AC Rx lt Ry The content of working register specified by Ry is loaded to AC and data memory specified by Rx Rx lt R HL The content of data memory specified by HL is loaded to AC and data memory specified by Rx MWR Rx HL Function Description SRO Rx Function Description SR1 Rx Function Descrip
92. ess Access 70H Working Register 9 mo 80H 2 lt gl 1FFH This figure shows the Data Memory Working Register Organization 35 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory RAM are not only used as general purpose data memory but also as the working register WR The following will introduce the general usage of working registers 1 Be used to perform operations on the contents of the working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ANDI ANDI EORI EORI ORI ORI 2 Be transferred the data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 Decode or directly transfer the contents of the working register and output to the LCD PLA circuit Such as LCT LCB LCP 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory can be performed 2 10 ALU Arithmetic and Logic Unit This is a circuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC
93. etwork before the counter is enabled The RFC function provides 3 modes for the operation of the 16 bit counter Each mode will be described in the following sections 3 8 2 Enable Disable the Counter by Software The clock input of the 16 bit counter comes from the CX pin and is enabled disabled by the S W When SRF 8h instruction is executed the counter will be enabled and will start to count the signals on the CX pin The counter will be disabled when SRF 0 instruction is executed Executing MRF1 4 instructions may load the result of the counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically Example If you intend to count the clock input from the CX pin for a specified time period you can enable the counter by executing SRF 8 instruction and setting timer1 to control the time period Check the overflow flag RFOVF of this counter when the time period elapses If the overflow flag is not set to 1 read the content of the counter if the overflow flag has been set to 1 you must reduce the time period and repeat the previous procedure again In this example use the RR network to generate the clock source Timer 1 is used to enable disable the counter LDS 0 0 Set the TMR1 clock source PH9 LDS 1554 initiate TMR1 setting value to 3F LDS 2 0Fh SHE 2 enable halt release by TMR1 RE CNT LDA 0 OR 1 combine the TMR1 setting value TMS 2
94. ev 1 0 2006 12 13 UM TM8725_E Enable the interrupt Enable the interrupt request caused by request caused by predivider overflow TM1 underflow HRF3 HRF1 Enable the interrupt request caused by INT pin HRF2 Interrupt request flag Interrupt flag Interrupt 3 Interrupt 2 Interrupt 1 Interrupt enable flag IEFO 2011 Enable the interrupt request caused by Interrupt request flag IOC or IOD port signal Interrupt flag InteruptO When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automatically Therefore the desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 2 15 4 CONTROL REGISTER 4 14 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 Stop release SRF4 SRF3 enable flag Enable the stop release Enable the stop release Enable the stop release Stop release request caused by signal request caused by signal request caused by signal request change on 1 4 SKI change on INT pin change on IOC IOD HRF2 When the stop release enable flag 7 SRF7 is set to 1 the input signal change at the KI1 4 pins causes the stop mode to be released In the same manner when SRF4 SRF3 and SRF5 are set to 1 the input signal change at the input mode pins of IOC IOD port and
95. fected Rx lt Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx Carry flag CF will be affected AC HL HL AC B CF The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC and data memory HL HL indicates an index address of data memory Carry flag CF will be affected AC HL HL AC B CF HL HL 1 The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction OHL indicates an index address of data memory Carry flag CF will be affected AC Rx AC The contents of Rx and AC are binary added the result is loaded to AC Carry flag CF will be affected AC lt HL AC The contents of HL and AC are binary added the result is loaded to AC HL indicates an index address of data memory Carry flag CF will be affected 113 tenx technology inc Rev 1 0 2006 12 13 ADD HL Function Description ADD Rx Function Description ADD HL Function Description ADD Function Description SUB Rx Function Description SUB HL Function Description UM TM8725_E AC lt HL AC HL HL 1 The contents of HL and AC are binary added the result is
96. he content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC Rx lt BCD AC Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected HL lt BCD AC Converts the content of AC to binary format and then restores to AC and data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC HL lt BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction When this instruction is executed the AC must be the result of any subtracted instruction 129 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The carry flag CF will be affected AC data before DAS data before DAS AC data after DAS CF data after DAS execution execution execution execution 0 lt lt 9 6 lt lt 5 8 JUMP INSTRUCTIONS JB0 X Function Program counter jumps to X in current page if AC0 1 Description If bitO of AC is 1 jump occurs If 0 the PC
97. herefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD2 at the off state of SW1 is used as an intermediate voltage level for the LCD driver 16 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 1 2 3 1 3 BIAS AT LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin ackup flag BCF MASK OPTION table POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in inverter size At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD at the off state of SW1 is used as an intermediate voltage level for LCD driver 17 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 1 3 EXTV POWER SUPPLY Operating voltage range 3 6V 5 25V For different LCD bias application the connection diagrams are shown below 2 1 3 1 NO BIAS AT EXT V BATTERY POWER SUPPLY MASK OPTION table POWER SOURCE 1 EXT V BI
98. hese pins are muxed with SEG32 SEG35 pins and selected by mask option MASK OPTION table SEG32 IOC1 KI1 SEG33 IOC2 KI2 SEG34 IOC3 KI3 SEG35 IOC4 KI4 The typical application circuit of key matrix scanning is shown below KlE KIS Kid KI2 kB KH K 4 K3 K E ese s b e bal Ese 1 KI 77 7 CS scc dd Te WEMNNEENNESNEN 89 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Executing SPKX X SPK Rx SPK instructions could set the scanning type of key matrix The bit pattern of these 3 instructions is shown below Instruction Bit Bits Bits Bit2 Biti Bito_ SPKX X XT X6 X5 X4 X3 X2 X1 X0 SPK Rx AC3 AC2 AC1 AC0 Rx3 Rx2 Rx1 Rx0 SPK QHL _ T HL7 T HL6 T HL5 T HL4 T HL3 T HL2 T HL1 T HL0 The following description shows the bit definitions in the operand of SPKX instruction 0 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after the key depressed on the key matrix and then set SCF7 to 1 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle no matter the key is depressed or not and then set SCF7 to 1 X7X5X4 000 in this setting each scanning cycle only check one specified column K1 K16 on key matrix The specified column is defined by the setting of X3 Xo Xo 0000 active K1 column X3 Xo
99. hole address range 000h BFFh the rest jump relative instructions could address to either page 0 000h 7ffh or page 1 800h BFFh e The program counter PC is normally increased by one 1 with every instruction execution PC PC 1 When executing JMP instruction subroutine call instruction CALL interrupt service routine or reset occurs the program counter PC loads the specified address corresponding to table 2 3 1 PC specified address shows in table 2 3 1 When executing a jump instruction except JMP and CALL the program counter PC loads the specified address in the operand of instruction All of these jump relative instructions could only address to current page That means when the current page is in page 0 PC1120 only the range 000h 7FFh is reachable when the current page is in page 1 PC11 1 only the range 800h FFFh is reachable PC current page PC11 specified address in operand e Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 Table 2 3 1 PC11 PC10 PC9 PC8 hialest 0 0 0 0 O qm INT pin input port C or D PC PEEN timer 1 interrupt m COMEN pre divider interrupt PU timer 2 interrupt Interrupt 5 Key Scanning interrupt RFC counter interrupt P6 P5 P4 P2 Pt PO Subroutinecall P11 P10 P9 P8 P7 P6
100. ified by HL is loaded to HL indicates an index address of data memory AC lt HL HL 1 The content specified by HL is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory TAB HL high nibble The higher nibble data of look up table specified by HL is loaded to data memory specified by Rx lt TAB HL high nibble HL HL 1 The higher nibble data of look up table specified by HL is loaded to data memory specified by Rx and then is increased in HL Rx TAB HL low nibble The lower nibble data of look up table specified by HL is loaded to the data memory specified by Rx 122 tenx technology inc Rev 1 0 2006 12 13 LDL Rx HL Function Description MRF1 Rx Function Description MRF2 Rx Function Description MRF3 Rx Function Description MRF4 Rx Function Description UM TM8725_E Rx AC TAB HL low nibble HL HL 1 The lower nibble data of look up table specified by HL is loaded to the data memory specified by Rx and then is increased in HL Rx AC RFC 3 0 Loads the lowest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 3 Bit 2 RFC 2 Bit 1 RFC 1 Bit 0 RFC O Rx AC RFC 7 4 Loads the 2 nibble data of 16 bit
101. input mode pin of IOD or IOC port is in H state and holds long enough to cause the CPU to be released from halt mode 2 A signal change in the INT pin 3 The stop release condition specified by the SRE instruction is met The data specified by X causes the halt mode to be released The signal change at port IOC IOD is specified The bit meaning of X XA X3 is shown below Bit pattern 4 1 mode is released when signal applied to IOC X3 1 Halt mode is released when signal applied to IOD X2 0 don t care 124 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E SIE X Function Set Reset interrupt enable flag Description The IEFO is set so that interrupt 0 Signal change at port IOC or IOD specified by 0 1 SCA is accepted X1 1 The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted 2 The IEF2 is set so that interrupt 2 the signal change at the INT pin is accepted 3 The IEF3 is set so that interrupt 3 overflow from the predivider is accepted 4 1 The IEF4 is set so that interrupt 4 underflow from timer 2 is accepted 5 1 The IEF5 is set so that interrupt 5 key scanning is accepted SHE X Function Set Reset halt release enable flag Description X2 1 X5 1 The 5 is set so that the halt mode is released by the signal is L applied on KI1 4 during scanning interval X6 1 The HEF6 is set so that the halt mode is released by RFC counter overflow N
102. ion ADN HL Function Description UM TM8725_E AC lt 1 HL HL 1 The content of AC is binary subtracted from content of HL the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected lt Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC and Rx Carry flag CF will be affected AC HL HL AC B 1 The content of AC is binary subtracted from content of HL the result is loaded to AC and data memory HL HL indicates an index address of data memory Carry flag CF will be affected HL HL AC B 1 HL HL 1 The content of AC is binary subtracted from content of HL the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected Rx AC The contents of Rx and AC binary added the result is loaded to AC The result will not affect the carry flag CF AC lt HL AC The contents of HL and AC are binary added the result is loaded to AC The result will not affect the carry flag CF HL indicates an index address of data memory 115
103. iver output pin is active 1 For X271 when the SF instruction is executed at X3 1 the EL panel driver is active and the halt request signal is outputted then the program enters halt mode similar to HALT instruction X4 1 The watchdog timer is initiated and active and WDF flag is to 1 XT 1 Enables the re load function of timer 1 X6 5 is reserved 135 tenx technology inc Rev 1 0 2006 12 13 RF X Function Description SF2 X Function Description RF2 X Function Description PLC Function Description UM TM8725 E Resets flag Description of each flag 1 The CF flag is reset to 0 X1 1 The chip escaped from backup mode and BCF flag is reset to 0 X2 1 The EL light driver is inactive X4 1 The watchdog timer is disabled and WDF flag is reset to O XT 1 Disables the re load function of timer 1 X6 5 3 is reserved Sets flag Description of each flag X3 1 Enable the strong pull low device on INT pin X2 1 Turn off the LCD display temporarily X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 Resets flag Description of each flag 1 Disable the strong pull low device on INT pin X2 1 Turn on the LCD display X1 1 Resets the DED flag Refer to 2 12 3 for detail 1 Disables the re load function of timer 2 Pulse control The pulse corresponding to the data specified by X i
104. k of IOD port PH6 X2 X1 X0 100 jof IOC port PH6 X5 is reserved FRQ D Rx Function Frequency generator lt D Rx Description Loads the content of AC and data memory specified by Rx and D D1 DO to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting x The bit pattern of preset letterN_ _ Programming divider Bit7 Bit6 Bit5 Bit4 Bit2 Bit Bito Di D J 0 0 0 1 day 1 0 ty FRQ HL Function Frequency generator lt D T HL Description Loads the content of Table ROM specified by HL and D D1 DO to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting x 1 ThebitpatemofpresetletterN Programming divider Bit Bit5 Bit4 Bit2 Bit1 Bito Note TO T7 represents the data of table ROM Preset Letter D Duty Cycle Di D 0 1 4 duty 0 x O 1 ndy 1 0 Al 2duy 1 1 duty 132 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E FRQX D X Function Frequency generator D X Description Loads the data X X7 X0 and D D1 DO to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting Pe The bit pattern of pre
105. l operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters the halt mode The following 3 conditions are available to release the halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When the halt mode is released and an interrupt is accepted the halt release signal is reset automatically The signal change specified by the SCA instruction is applied to port IOC SCF 1 or IOD SCF3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary that the MSB MSC or MCX instruction is executed in order to test the halt release signal and that the PLC instruction is then executed to reset the halt release signal HRF Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 54 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 17 HEAVY LOAD FUNCTION When heavy loading lamp light up motor start etc causes a temporary voltage drop on supply voltage the heavy loading function set BCF 1 prevents TM8725 from malfunctioning especially where a battery with high internal impedan
106. lighting system is shown below these frequencies could be selected by mask option All of the LCD frame frequencies in the following tables based on the clock source frequency of the pre divider PHO is 32768Hz The LCD alternating frequency in duplex 1 2 duty type Mask Option name LCD frame frequency Selected item Remark alternating frequency 16Hz LCD frame frequency 32Hz LCD frame frequency 64Hz LCD frame frequency 0Hz LCD not used The LCD alternating frequency in 1 3 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 21Hz LCD frame frequency 2 TYPICAL 42Hz LCD frame frequency 2 FAST 85Hz LCD frame frequency 2 O P 0Hz LCD not used The LCD alternating frequency in 1 4 duty type Mask Option name LCD frame frequency Selected item 1 SLOW Remark alternating frequency 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz LCD frame frequency The LCD alternating frequency in 1 5 duty 2 0Hz LCD not used type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 25Hz LCD frame frequency 2 TYPICAL 51 2 LCD frame frequency 2 FAST 102Hz LCD frame frequency 2 O P 0Hz LCD not used The LCD alternating fr
107. lt is loaded to AC and working register Ry D 0H FH AC lt Ry D D represents the immediate data The contents of Ry and D are binary OREd the result is loaded to AC D 0H FH AC Ry lt Ry D D represents the immediate data The contents of Ry and D are binary OREd the result is loaded to AC and working register Ry D 0H FH 5 4 LOAD STORE INSTRUCTIONS STA Rx Function Description STA HL Function Description Rx AC The content of AC is loaded to data memory specified by Rx HL AC The content of AC is loaded to data memory specified by HL HL indicates an index address of data memory 121 tenx technology inc Rev 1 0 2006 12 13 STA HL Function Description LDS Rx D Function Description LDA Rx Function Description LDA HL Function Description LDA HL Function Description LDH Rx HL Function Description LDH Rx HL Function Description LDL Rx HL Function Description UM TM8725 E HL AC HL HL 1 The content of AC is loaded to data memory specified by HL The content of index register HL will be increment automatically after executing this instruction OHL indicates an index address of data memory AC Rx lt D Immediate data D is loaded to the AC and data memory specified by Rx D 0H FH AC lt Rx The content of Rx is loaded to AC The content spec
108. lt release request flag 6 10 Halt release enable flags 1 t03 1 6 Os Interrupt enable flags O0to3 IEF06 10 j Input output ports I OA I OB VOC VOD VOB input mode I OC I OD port chattering clock Cch PH10 EL panel driver pumping clock source and duty cycle Celp PHO duty cycle is 1 4 EL panel driver clearing clock source Gala 8 duty cycle is 1 4 and duty cycle Frequency generator clock source and Cf PH0 duty cycle is 1 4 output duty cycle q is inactive Resistor frequency converter RFC Inactive RR RT RH output 0 LCD driver output All lighted mask option Timer 1 2 Watchdog timer WDT Reset mode WDF 0 XT clock slow speed clock in Clock source BCLK dual a Notes PH3 the 3rd output of predivider PH10 the 10th output of predivider Mask option can unlighted all of the LCD output 65 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 2 3 IOC Port Key Matrix RESET Key reset function is selected by mask option When IOC port or key matrix scanning input KI1 4 is in used the O signal applied to all these pins that had be set as input mode in the same time KI1 4 pins need to wait scanning time reset signal is delivered OPTION table IOC or KI pins are used as key reset IOC1 KI1 FOR KEY RESET IOC2 KI2 FOR KEY RESET IOC3 KI3 FOR KEY RESET IOC4 KI4 FOR KEY RESET IOC1 KI1 FOR KEY RESET IOC2 KI2 FOR
109. mode or stop mode When the TM8725 wakes up from the halt or stop mode the timer operates continuously It is recommended to execute SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute SF 10h instruction periodically to prevent the timer overflowed The overflow time interval of watchdog timer is selected by mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER 1 8 x PH10 OVERFLOW TIME INTERVAL 2 64 x PH10 3 512 x PH10 OVERFLOW TIME INTERVAL Note timer overflow time interval is about 16 seconds when PHO 32 768 KHz 67 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 3 CLOCK GENERATOR 3 3 1 FREQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator 8 bit Programmable Duty Cycle Frequency output Divider Generator FREQ BCLK PH0 Clock Option FRQ D Rx SCC 1 FRQ D Rx Rx3 Rx0 SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencie
110. n BCLK 1 T2 T4 Sdk Clock switch System clock generator XT Clock CF Clock Singe dock option Dual dock option Clock switch circuit Predivider The system clock generator provided the necessary clocks for execution of instruction The pre divider generated several clocks with different frequencies for the usage of LCD driver frequency generator etc The following table shows the clock sources of system clock generator and pre divider in different conditions eee i BOLI O Halt mode dual clock option XT clock XT clock Slow mode dual clock option XT clock XT clock Fast mode dual clock option XT clock CF clock 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by mask option or it will be active all the time after the initial reset In stop mode the oscillator will be stopped There are 2 type oscillators can be used in slow clock oscillator selected by mask option 21 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 2 1 1 External 32 768KHz Crystal oscillator MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 1 X tal 15pf
111. n The waveform specified by X X8 X0 is delivered to the BZ and BZB pins The output frequency could be any combination in the following table The bit pattern of X for higher frequency clock source 1 0 0 DC xa O 1 1 PH34KHZ O 0 1 0 fPH KH X 0 1 5 O 0 o o 000 HPV The bit pattern of X for lower frequency clock source Bit clock source lower frequency Notes 1 FREQ is the output of frequency generator 2 When the buzzer output does not need the envelope waveform X5 should be set to 0 3 The frequency inside the bases on the PH0 is 32768Hz ELC X Function The bit control of EL panel driver Description The meaning of each bit specified by X X9 X0 is shown below For ELP pin output clock setting X8 X7 X6 Pumping clock X9 X5 X4 Duty cycle frequency 000 3 4 duty BCLK 2 3 duty BCLK 2 1 2 duty BCLK 4 1 1 duty original BCLK 8 1 3 duty Lo TT 1 4duty 107 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Note X represents don t care For ELC pin output clock setting X3 X2 Discharge pulse X1 X0 Duty cycle frequency 1 1 duty original SRF X Function The operation control for RFC Description The meaning of each control bit X5 X0 is shown below network of RR network of RR network of RT network of RT network of RH network of RH X3 1 lenables the 16 bit counter X3 0 disabl
112. n is executed the AC must be the result of any added instruction The carry flag CF will be affected AC Rx BCD AC Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC HL lt BCD AC Converts the content of AC to binary format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected 128 tenx technology inc Rev 1 0 2006 12 13 DAA HL Function Description UM TM8725 E AC HL lt BCD AC HL 1 Converts the content of AC to binary format and then restores to AC and data memory specified by HL The content of index register HL will be increment automatically after executing this instruction When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt AC lt 9 ASAC lt F AC 6 lt lt 3 6 DAS Function Description DAS Rx Function Description DAS HL Function Description DAS HL Function Description AC lt BCD AC Converts t
113. n this option The backup flag BCF will be set to 1 automatically before the program enters the stop mode Halt Normal mode Halt Halt mode OSC active released OSC active Stop Reset Reset release Stop Release Stop mode OSC stop Reset mode Power on reset OSC active Reset Reset pin reset Watchdog timer reset Key reset This figure shows the State Diagram of Single Clock Option 26 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry PH0 as input When PH0 is changed from H level to L level the content of this counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or at the initial reset mode The pre divider delivers the signal to the halver tripler circuit alternating frequency for LCD display system clock sound generator and halt release request signal I O port chattering prevention clock Frequency Interrupt request Generator SCF7 Initial D PLC 8H Interrupt Halt mode SLOW instruction Clock switch circuit clock generator MSC instruction r Data bus 2 7o Clock switch circuit Single clock epi Dual clock option To timer circuit PLC 100H initial To sound circuit tribler circuit
114. nction lt Rx Description The content of Rx is outputted to I OC port IPC Rx Function Rx AC lt I OC Description The data of I OC port is loaded to AC and data memory Rx SPD X 104 tenx technology inc Rev 1 0 2006 12 13 Function Description UM TM8725_E Defines the input output mode of each pin for IOD port and enables disables the pull low device Sets the I O mode and turns on off the pull low device The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting Enable the pull low device Disable the pull low device IOD1 IOD4 1 1004 simultaneousl simultaneously IOD4 as output mode X3 0 IOD4as input mode IOD3 as output mode IOD3 as input mode IOD2 as output mode IOD2 as input mode IOD1 as output mode IOD1 as input mode OPD Rx Function Description IPD Rx Function Description SPKX X Function Description 1 Rx The content of Rx is outputted to I OD port Rx AC lt I OD The data of I OD port is loaded to AC and data memory Rx Sets Key matrix scanning output state When SEG1 16 is are used for LCD driver pin s set X X7 0 to specify the key matrix scanning output state for each SEGn pin in scanning interval Xs 0 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after the key depressed on the key matrix and then set SCF7 to 1
115. ndex RAM specified by HL are loaded to several LCD latches Lz simultaneously The range of multi Lz is specified by data D Refer to Tabel 4 3 D 0 1 LCBX D Function Mullti LCD latch Lz lt data decoder HL Description The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder The range of multi Lz is specified by data D Refer to Table 4 3 D 0 1 LCPX D Function Mullti LCD latch Lz HL AC Description The contents of index RAM specified by HL and the contents of AC are loaded to several LCD latches Lz simultaneously Refer to Table 4 2 The range of multi Lz is specified by data D Refer to Table 4 3 D 0 1 SPA X Function Defines the input output mode of each pin for IOA port and enables disables the pull low device Description Sets the I O mode and turns on off the pull low device The meaning of each bit of X X4 X3 X2 X1 and X0 is shown below Bit pattern Setting Bit pattern Setting Enable the pull low Disable the pull low X4 1 device on 1 1 4 device on IOA1 1OA4 simultaneously simultaneously X4 0 IOA4 as output mode IOA4 as input mode IOA3 as output mode IOA3 as input mode IOA2 as output mode IOA2 as input mode IOA1 as output mode IOA1 as input mode OPA Rx Function 1 lt Rx Description The content of Rx is outputted to I OA port OPAS Rx D Function IOA1 2 lt Rx
116. nology inc Rev 1 0 2006 12 13 UM TM8725_E IOC port may select the pull low device or low level hold device for each pin by mask option or enable disable this device by program setting When the pull low device and low level hold device are both enabled by mask option the reset will enable the pull low device and disable the low level hold device Executing SPC 10h instruction may also enable the pull low device and disable the low level hold device and executing SPC 0h may disable the pull low device and enable the low level hold device When the IOC pin has been defined as the output mode both the pull low and low level hold devices will be disabled MASK OPTION table Pull low function option IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE The low level hold function will not be available when pull low function is not actived Low level hold function option Mask Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to IOC4 pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOC port are defined as output the signals applied to the output pins will be inhibited for
117. nstruction the system clock generator will hold 12 CF clocks after the CF clock oscillator starts up and then switches CF clock to BCLK This will prevent the incorrect clock from delivering to the system clock in the start up duration of the fast clock oscillator CF clock XT clock FAST so HOLD 12 CF CLOCKS This figure shows the System Clock Switches from Slow to Fast After executing SLOW instruction the system clock generator will hold 2 XT clocks and then switches XT clock to BCLK 25 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E CF Fast clock stops operating clock clock SLOW BCLK This figure shows the System Clock Switches from Fast to Slow 2 2 3 2 Single Clock MASK OPTION table For Fast clock oscillator only Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY For slow clock oscillator only Mask Option name Selected item CLOCK SOURCE 2 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction i
118. o start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 1 TM2 Rx Function Selects timer 2 clock source and preset timer 2 Description The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 TM2 Rx AC1 Rx2 The clock source selection for timer 2 AC3 AC2 134 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E TM2 HL Function Selects timer 2 clock source and preset timer 2 Description The content of Table ROM specified by HL is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 The clock source selection for timer 2 po of _ __ o ouo ee 2 a P 2 TM2X X Function Selects timer 2 clock source and preset timer 2 Description The data specified by X X8 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction The clock source selection for timer 2 PH15 Output of frequency generator FREQ PH5 PH11 EIE SF X Function Sets flag Description Description of each flag 1 The CF flag is set to 1 X1 1 The chip enters backup mode and BCF flag is set to 1 X2 1 The EL panel dr
119. on shown in the following table 1 5V battery mode TM8725 status flag status Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction BCF 0 HALT mode Previous state STOP mode BCF 1 hardware controlled TM8725 status 0 1 32 768KHz Crystal Oscillator Small driver Large driver Voltage on BAK pin VDD1 VDD1 Internal operating voltage VDD1 VDD1 57 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3V battery or higher mode TM8725 status BCF flag status Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode 1 hardware controlled xr Pr o Bosa 32 768KHz Crystal Oscillator Small driver Large driver Voltage on BAK pin VDD1 VDD2 Internal operating voltage VDD1 VDD2 Ext V power mode TM8725 status BCF flag status Initial reset cycle BCF 0 hardware controlled After initial reset cycle BCF 0 hardware controlled Executing SF 2h instruction 1 Executing RF 2h instruction 0 mode Previous state STOP mode 1 hardware controlled Eo BOFO sees 32 768KHz Crystal Oscillator Large d
120. op release flags SKI CSR DSR and HRF2 were specified by the stop release enable flags SRFx and these flags should be clear before the chip enters the stop mode 49 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E All of the pins in IOA and IOC port had to be defined as the input mode and keep in 0 state before the chip enters the STOP mode or the program can not enter the STOP mode Instruction SRE is used to set or reset the stop release enable flags SRF4 5 7 The following table shows the stop release request flags The OR ed The OR ed input The rising or latched signals for mode pins of falling edge on INT 11 4 IOC IOD port pin Stop release request flag CSR DSR HRF2 Stop release enable flag SRF7 SRF4 SRF3 SRF5 2 15 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 CTL1 to control register 4 CTLA 2 15 1 CONTROL REGISTER 1 CTL1 The control register 1 CTL 1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC defined as input mode that causes the halt mode or stop mode to be released 2 Switch enable flag 3 SEF3 Stores the status of the input signal change at pins of IOD defined as input mode that causes the halt mode or stop mode to be released Executed SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 CTL 1 Bit 4 Bit3 Switch
121. operate with few external components This circuitry could generate output voltage up to 150V or above for driving the EL plant the ELC and ELP output is MUXed with IOB1 SEG28 and IOB2 SEG29 and is selected by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC 3 ELC SEG29 IOB2 ELP 3 ELP The ELP pin will output clocks to pump voltage to the EL plant the ELC pin will output the pulse to discharge the EL plant The EL plant driver will not operate until the light control signal LIT is enabled Once the light control signal LIT is enabled the ELC pin will output a pulse to discharge the capacitor before the pumping clocks output to ELP pin This will insure that there is no residual voltage that may cause damage while the first pumping clock is applied When the light control signal LIT is disabled the ELC pin will output a pulse to discharge the EL plant after the last pumping clock EL plant This figure shows the application circuit of EL plant LIT Sat C 0 ELP ELC This figure shows the output waveform of EL plant driver Executing ELC instruction can change ELP ELC pulse frequency and duty cycle When ELC pin outputs the discharge pulse the clock on ELP pin will be inhibited 82 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E For ELP setting Pumping clock X8 X7 X6 X5 X4 Duty cycle PH 00 000 1 3 duty
122. operating timing of TMR 2 in RFC mode Clock source of SANE EB Timer 2 TM2x X Jb ii Content of 3Fh N Y N 2 3Fh Timer 4 TENX S MN TMR2 also provides the re load function when controlled the RFC function The SF2 1h instruction enables the re load function and the DED flag should be set to 1 by SF2 2h instruction Once DED flag had been set to 1 TENX flag will not be cleared to 0 while TMR2 underflows but HRF4 will be set to1 The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HRF4 occurs thus the TENX flag will be reset to 0 when the last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurred disable the re load function by executing RF2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 Set the initiate value of TMR2 to 52 and start counting 2 Enable the TMR2 halt release or interrupt function 3 Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue counting even if TMR2 underflows 4 When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase the counting value to count the underflow times 5 When halt release or interrupt occurs for the 7 time reset the DED flag 6 When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed 43 tenx
123. or The internal interrupt factor involves the use of timer 1 TMR1 timer 2 TMR2 RFC counter and the pre divider 1 Timer1 2 TMR1 2 interrupt request An interrupt request signal HRF1 4 is delivered when timer1 2 TMR1 2 underflows In this case if the interrupt enable flag 1 4 IEF1 4 is set interrupt 1 4 is accepted and the instruction at address 18H 20H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set interrupt 3 is accepted and the instruction at address 1CH is executed automatically 3 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is delivered when the 2 falling edge applied on CX pin and 16 bit counter stops to operate In this case if the interrupt enable flag6 IEF6 is set interrupt 6 is accepted and the instruction at address 28H is executed automatically 61 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the interrupt service routine is initiated all of the interrupt enable flags IEF0 IEF6 are cleared and should be set with the next execution of the SIE instruction
124. ote X0 don t care SRE X Function Set Reset stop release enable flag Description X3 1 The SRF3 is set so that the stop mode is released by the signal changed on IOD port X4 1 The SRF4 is set so that the stop mode is released by the signal changed on IOC port SRF5 is set so that the stop mode is released by the signal changed on INT pin 7 1 The SRF7 is set so that the stop mode is released by the signal is L applied on KI1 4 in scanning interval Note X2 0 don t care FAST Function Switches the system clock to CFOSC clock Description Starts up the CFOSC high speed osc and then switches the system clock to high speed clock 125 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E SLOW Function Switches the system clock to XTOSC clock low speed osc Description Switches the system clock to low speed clock and then stops the CFOSC MSB Rx Function AC Rx SCF3 SCF2 BCF1 BCF Description The SCF1 SCF2 SCF3 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition Backup flag flag 3 flag 2 flag 1 BCF SCF3 SCF2 SCF 1 Halt release Halt release Halt release The backup caused by the caused by caused by the mode status in IOD port SCF4 5 6 7 8 9 IOC port TM8725 MSC Rx Function
125. pping table of LCP and LCD instructions _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH There are 8 data decoder outputs of DBUSA to DBUSH and 32 LO to L4 decoder outputs of PSTB Oh to PSTB 3Fh The input data and clock signal of the latch circuit are DBUSA to DBUSH PSTB Oh to PSTB 1Fh respectively Each segment pin has 8 latches corresponding to COM1 8 The segment PLA performs the function of combining DBUSA to DBUSH inputs to each latch and strobe PSTB Oh to PSTB3Fh is selected freely by mask option Of 512 signals obtainable by combining DBUSA to DBUSH and PSTB Oh to PSTB 3Fh any 320 corresponding to the number of latch circuits incorporated in the hardware signals can be selected by programming and the above mentioned segment PLA Table 4 3 1 2 shows the PSTB Oh to PSTB 3Fh signals concretely 97 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Table 4 3 1 2 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction Strobe in LCT LCB LCP LCD instructions LCD latch The values of Lz in LCT Lz Q Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD outputs could be turned off without changing the segment data Executed SF2 4h instruction could turn off the display simultaneously and executed RF2 4h could turn on the display with the patterns
126. provided the halt release request signal is delivered setting the start condition flag 9 SCF9 in status register 4 STS4 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 28h SRF 0h SRF control Enable counter CX Content of LLTO A UE j Y Y Y Y Y q Counter starts Counter stops to count caused by the 2nd rising edge This figure shows the timing of the counter controlled by the CX pin Example 88 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E SCC 0h Select the base clock of the frequency generator that comes from PH0 XT clock FRQX 1 5 set the frequency generator to FREQ PH0 3 5 the setting value of the frequency generator is 5 and FREQ has 1 3 duty waveform SHE 40h enable the halt release caused by 16 bit counter SRF 28h enable the counter controlled by the CX signal HALT PLC 40h release is caused by the 2 rising edge on CX and then clear the halt release request flag MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 9 KEY MATRIX SCANNING TM8725 shared the timing of LCD waveform to scan the key matrix circuitry and these scanning output pins are SEG1 16 for easy to understand named these pins as K1 K16 The time sharing of LCD waveform will not affect the display of LCD panel The input port of key matrix circuitry is composed by KI1 pins t
127. river Large driver Voltage on BAK pin VDD2 VDD2 Internal operating voltage VDD2 VDD2 Note For power saving reason it is recommended to reset BCF flag to 0 when back up mode is not used 58 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Chapter3 Control Function 3 1 INTERRUPT FUNCTION There are 7 interrupt resources 3 external interrupt factors and 4 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine specified by a fix address in the program memory ROM is called The following table shows the flag and service of each interrupt Table 3 1 1 Interrupt information Interrupt INT pin lOCor TMR1 Pre TMR2 Key source IOD port junderflow divider matrix overflow junderflow Scanning k pou Ed Ed Interrupt 1 enable flag Interrupt priorit 59 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following figure shows the Interrupt Control Circuit Interrupt 0 Specified signal change at Priority IOC or lOD port cortrol circuit Interrupt 1 Timer TM underflow Interrupt Specified signal Interrupt 2 request change amp INT pin signal Interrupt vector address generator redivider overflow TM2 underflow Specified signal enable at Key matrix Scanning RF C counter Interrupt overflow Interrupt accept
128. rupt is accepted the halt mode will be released by the interrupt request The stop mode returns by executing the RTS instruction after completion of interrupt service After the stop release it is necessary that the MSB MSC or MCX instruction be executed to test the halt release signal and that the PLC instruction then be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter the stop mode but the halt mode When the stop mode is released and an interrupt is accepted the halt release signal HRF is reset automatically 2 19 BACK UP FUNCTION TM8725 provide a back up mode to avoid system malfunction when heavy loading occurred such as buzzer is active LED is lighting etc Since the heavy loading will cause a large voltage drop on the supply voltage and the system will be malfunction in this condition Once the program enter back up mode BCF 1 32 768 KHz Crystal oscillator will operate in a large driver condition and internal logic function operates with higher supply voltage TM8725 will get more power supply noise margin while back up mode is active but also increases more power consumption The back up flag BCF indicated the status of back up function BCF flag could be set or reset by executing SF or RF instruction respectively The back up function has different performance corresponding to different power mode opti
129. rupt requests have been processed 62 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service address is executed automatically In this case the CPU performs the following services automatically 1 As for the return address of the interrupt service routine the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and the interrupt enable flags are all reset When the interrupt occurs the TM8725 will follow the procedure below Instruction 1 In this instruction interrupt is accepted NOP TM8725 stores the program counter data into the STACK At this time instruction will be executed as with NOP instruction Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted Instruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are reset to O and the corresponding HRF flag will be cleared
130. ry space with instruction ROM as shown in the figure above This memory space stores the constant data or look up table for the usage of main program All of the table ROM addresses are specified by the index address register HL The data width could be 8 bits 256 16 N x 8 bits or 4 bits 512 16 N x 4 bits which depends on the different usage Refer to the explanation of instruction chapter 31 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and the contents of the register can be modified by executing MVH MVL and MVU instructions Executed MVL instruction will load the content of specified data memory to the lower nibble of the index register L In the same manner executed MVH and MVU instructions may load the content of the data RAM Rx to the higher nibble of the register H U respectively U register H register L register Bit3 Bit2 BitO Bits Bit1 Bit2 Bit1 BitO IDBF11 IDBF10 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF 1 IDBF0 The index address register can specify the full range addresses of the table ROM and data memory index addressing DATA RAM TABLE ROM bit0 addressing This figure shows the diagram of the index address register The index ad
131. s and duty cycles corresponding to the presetting data of FRQ related instructions The FRQ related instructions preset a letter N into the programming divider and letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz X 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of data memory and accumulator AC or the table ROM data or operand data specified in the FRQX instruction The following table shows the bit pattern of the combination The following table shows the bit pattern of the preset letter N ee eee ee The bit pattern of preset letter N Programming divider bit7 Bit6 bit5 bit4 bit3 2 bit1 bito Notes 1 TO T7 represents the data of table ROM 2 XT represents the data specified in operand X The following table shows the bit pattern of the preset letter D Di po o es 0 0 maty oO 1 1 3 duty 1 0 1 2 duty 68 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following diagram shows the output waveform for different duty cycles clock source N 11Hz 1 4 duty carrier aut 1 3 duty carrier aut 1 2 duty carrier aut 1 1 duty carrier aut 3 3 2 Melody Output The frequency generator may generate the frequency for melody usage When the frequency generator is used to generate the melody output the tone table is shown belo
132. s generated 1 Halt release request flag HRFO caused by the signal at I O port C is reset X1 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 X2 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset 1 Halt release request flag HRF3 caused by overflow from the predivider is reset X4 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 X5 1 Halt release request flag HRF5 caused by the signal change to L on KI1 4 in scanning interval is reset X6 1 Halt release request flag HRF6 caused by overflow from the RFC counter is reset X8 1 The last 5 bits of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 simultaneously 136 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Appendix 8725 Instruction Table Instruction Machine Code 0000 0000 0000 No Operation Function Flag Remark 001Z ZZZZ Lz Ry 70H 7FH 010Z ZZZZ YYYY Lz Blank Zero 011Z ZZZZ YYYY Lz 100Z ZZZZ 0000 Lz 100Z ZZZZ 0001 Lz lt R HL 100Z ZZZZ 0010 Lz lt Blank Zero 100Z ZZZZ 0011 Lz R HL amp AC 100D 0000 0100 Multi Lz D 0 D 1 lt R HL Multi Lz 00H OFH 12 10 1
133. s of data memory R HL AC R HL 1 HL HL 1 Substrate 1 from the content of HL the result is loaded to data memory HL and AC The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected OHL indicates an index address of data memory lt RX FAC CF The contents of Rx AC and CF are binary added the result is loaded to AC Carry flag CF will be affected AC lt HL AC CF The contents of HL AC and CF are binary added the result is loaded to AC Carry flag CF will be affected OHL indicates an index address of data memory 111 tenx technology inc Rev 1 0 2006 12 13 ADC HL Function Description ADC Rx Function Description ADC HL Function Description ADC Function Description SBC Rx Function Description SBC HL Function Description UM TM8725 E AC lt HL AC CF HL 1 The contents of HL AC and CF are binary added the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected OHL indicates an index address of data memory AC Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC HL HL AC CF The contents of HL AC an
134. set letter N Programming divider Bite Bit5 Bit4 Bit2 bit1 Note X0 X7 represents the data specified in operand X Preset Letter D Duty Cycle Di D po 0 _ 0 1 dy 1 0 J aduy 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D The content of table ROM specified by HL as preset data N 3 FROX D X The data of operand in the instruction assigned as preset data N TMS Rx Function Select timer 1 clock source and preset timer 1 Description The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Presetting value of timer 1 The clock source selection for timer 1 010 PHO SS PH15 Output of frequency generator FREQ TMS HL Function Select timer 1 clock source and preset timer 1 Description The content of table ROM specified by HI is loaded to timer 1 to start the timer 133 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E The following table shows the bit pattern for this instruction Select clock Presetting value of timer 1 The clock source selection for timer 1 olol 0 XIPMSS 0 1 _ P3 X Function Selects timer 1 clock source and preset timer 1 Description The data specified by X X7 X0 is loaded to timer 1 t
135. sly When all of the flags in SCF4 5 6 7 9 are clear start condition flag 2 SCF2 is reset to 0 Note If start condition flag is set to 1 the program will not be able to enter halt mode e Backup flag This flag could be set reset by executing the SF 2h RF 2h instruction 46 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 14 3 STATUS REGISTER 3 STS3 When the halt mode is released by start condition flag 2 SCF2 status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal change at the INT pin causes the halt release request flag 2 HRF2 to be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC instruction must be used to reset the halt release request flag 2 HRF2 or the SHE instruction must be used to reset the halt release enable flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF1 or the SHE instruction must be used to reset the halt release enable fl
136. st level will be overwritten Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the content of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupt accepted RTS instruction STACK ring with first in last out function 34 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 7 DATA MEMORY RAM The static RAM is organized with 384 addresses x 4 bits and is used to store data The data memory may be accessed using two methods 1 Direct addressing mode The address of the data memory is specified by the instruction and the addressing range is from OOH to 7FH 2 Index addressing mode The index address register HL specifies the address of the data memory and all address space from 00H to 17FH can be accessed The 16 specified addresses 70H to 7FH in the direct addressing memory are also used as 16 working registers The function of working register will be described in detail in section 2 6 OOH DATA RAM Direct Addr
137. tch circuit The data decoder is used for decoding the content of the working register specified in LCD related instructions as 7 segment pattern on LCD panel The decoding table is shown below Content Output of data decoder of data DBUS DBUS DBUS DBUS DBUS DBUS DBUS DBUS memory A B C D E F G H Note The DBUSF of decoded output can be selected as 0 or 1 by mask option The LCD pattern of this option is shown below 96 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E DBUSA DBUSA DBUSF DBUSB DBUSF DBUSB DBUSE DBUSC DBUSE DBUSC ud NL DBUSD DBUSH DBUSD DBUSH DBUSF 0 DBUSF 1 The following table shows the option table for displaying digit 7 pattern MASK OPTION table Mask Option name Selected item F SEGMENT FOR DISPLAY 575 1 ON F SEGMENT FOR DISPLAY 575 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of data memory that specified When the content of data memory that specified by LCB instruction is 0 the decoded output of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on LCD panel The LCP instruction transferred the data of the RAM Rx and accumulator AC directly from DBUSA to DBUSH without passing through the data decoder The LCD instruction transfers the table ROM data T HL directly from DBUSA to DBUSH without passing through the data decoder Table 4 3 1 1 The ma
138. technology inc Rev 1 0 2006 12 13 UM TM8725_E In this example S W enters the halt mode to wait for the underflow of TM2 LDS PLC SHE SRF TM2X SF2 RE LOAD HALT INC PLC LDS SUB JNZ RF2 NOT RESET DED LDA JB3 END TM2 subroutine JMP RE LOAD END TM2 RF2 0 0 10h 10h 19h 34h 3h 0 10h 20h 7 0 initiate the underflow counting register enable the halt release caused by TM2 enable RFC and controlled by TM2 initiate the TM value 52 and clock source is 9 enable the re load function and set DED flag to 1 increase the underflow counter clear HRF4 when halt is released for the 7 time reset DED flag NOT_RESET_DED 2 0 1 reset DED flag store underflow counter to if the TM2 underflow counter is equal to 8 exit this disable the re load function TM2 sia x P count ae count ooa count 08 count count HE count M HRF4 PLC Re load DED _ TENX This figure shows the operating timing of TMR2 re load function for RFC 44 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start condition flags for TM8725 IEF Chaterig PLCO 210
139. ted item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE IEF2 Interrupt request SCF2 Halt release request PLC 4h Initial clear pulse Mask option Interrupt 2 receive signal Open type Note For Ag battery power supply positive power is connected to VDD1 for anything other than Ag battery power supply it is connected to VDD2 This figure shows the INT Pin Configuration 84 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 3 8 RESISTER TO FREQUENCY CONVERTER RFC The resistor to frequency converter RFC can compare two different sensors with the reference resister separately This figure shows the block diagram of RFC SRF Controlled by Timer 2 SRF 18h SRF 200 CX pin signal IEFB interrupt m SRF 2h request 5 HEFG ma SCFa SRF th I ie counter over flaw flag Enable CNT HFF6 SRF 18h CLKIN 16 bit counter SRF 28h E gt ex FREQ output from MF F1 4 frequency gereratar to data memory 400 data b xa SRF 4h E B AN h Y This RFC contains four external pins CX the oscillation Schemmit trigger input RR the reference resister output pin RT the temperature sensor output pin RH the humidity sensor output pin this can also be used as another temperature sensor or can even be left floating These CX RR RT and RH pins are MUXed with 1 SEG37 to IOA4 SEG40 respe
140. the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 The 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 42 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E 2 13 2 RE LOAD OPERATION TMR2 also provides the re load function is the same as TMR1 The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 2 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER RFC TMR2 also controlled the operation of RFC function TMR2 will set TENX flag to 1 to enable the RFC counter once the TMR2 underflows the TENX flag will be reset to 0 automatically In this case Timer 2 could set an accurate time period without setting a value error like the other operations of TMR1 and TMR2 Refer to 2 16 for detailed information on controlling the RFC counter The following figure shows the
141. this instruction are as follows Bit 3 CF Bit 2 Zero AC 0 flag Bit 1 No Use Bit 0 No Use 5 3 OPERATION INSTRUCTIONS INC Rx Function Description INC HL Function Description Rx AC lt Rx 1 Add 1 to the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected HL AC R HL 1 Add 1 to the content of HL the result is loaded to data memory HL and AC Carry flag CF will be affected e HL indicates an index address of data memory 110 tenx technology inc Rev 1 0 2006 12 13 INC HL Function Description DEC Rx Function Description DEC HL Function Description DEC Function Description ADC Rx Function Description ADC HL Function Description UM TM8725_E HL AC R HL 1 HL 1 Add 1 to the content of HL the result is loaded to data memory HL and AC The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected HL indicates an index address of data memory Rx AC Rx 1 Substrate 1 from the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected R HL AC lt R HL 1 Substrate 1 from the content of HL the result is loaded to data memory HL and AC Carry flag CF will be affected OHL indicates an index addres
142. tion SLO Rx Function AC Rx lt R HL HL 1 The content of data memory specified by HL is loaded to AC and data memory specified by Rx The content of index register HL will be increment automatically after executing this instruction Rx n ACn Rx n 1 AC n 1 Rx 3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC Content of Rx Before After Rx n ACn lt Rx n 1 AC n 1 Rx 3 lt 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC Content of Rx Before After Rx n ACn Rx n 1 ACn 1 109 tenx technology inc Rev 1 0 2006 12 13 Description 511 Rx Function Description MRA Rx Function Description MAF Rx Function Description UM TM8725 E Rx 0 ACO 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC Content of Rx Before After Rx n ACn lt Rx n 1 AC n 1 Rx 0 ACO lt 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC Content of Rx Before After CF lt Rx 3 Bit3 of the content of Rx is loaded to carry flag CF lt CF Zero flag The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of
143. tion is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again During this operation the program must use the halt release request flag or interrupt to check the wanted counting value It is necessary to execute the TMS or instruction to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the TMR1 will stop operating immediately after the re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the initiate count down value of TMR1 to 52 and start counting then enable the TMR1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs clear the HRF1 flag by PLC instruction After halt release or interrupt occurs 8 times disable the re load function and the counting is completed a 2 i 2 2 22 7th cou count eod count count Coa count count s 20 TMS H
144. truction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 Bit 3 Bit 2 Bit 1 Bit 0 The overflow flag System clock Reserved of 16 bit counter of s selection RFC 9 CSF 2 14 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF11 will be set to 1 in STOP mode when the following conditions are met e A high level signal comes from the OR ed output of the pins defined as input mode in IOC port which causes the stop release flag of IOC port CSR to output and stop release enable flag 4 SRF4 is set beforehand e A high level signal comes from the OR ed output of the pins defined as input mode in IOD port which causes the stop release flag of IOD port DSR to output and stop release enable flag 3 SRF3 is set beforehand e A high level signal comes from the OR ed output of the signals latch for 11 4 which causes the stop release flag of Key Scanning SKI to output and stop release enable flag 4 SRF7 is set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output and the stop release enable flag 5 SRF5 is set beforehand The following figure shows the organization of start condition flag 11 SCF 11 HRF2 SRF5 SCF11 Stop release request SRF IOC1 IOC2 CSR IOC3 IOC4 SRF4 SRF3 The st
145. ts of Ry D and CF are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH Ry D CF D represents the immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry lt Ry D CF D represents the immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry Ry D D represents the immediate data 119 tenx technology inc Rev 1 0 2006 12 13 SUBI Ry D Function Description SUBI Ry D Function Description ADNI Ry D Function Description ADNI Ry D Function Description ANDI Ry D Function Description ANDI Ry D Function Description UM TM8725 E The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC Ry D 1 D represents the immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC The carry flag CF
146. tting value for the frequency generator is 3 and duty cycle is 1 2 ALM 1COh FREQ signal is outputted This instruction must be executed after the FRQ related instructions HALT for the halt release caused by timer 1 s i EE Halt released ALM 0 Stop the buzzer output 3 5 INPUT OUTPUT PORTS Four I O ports are available in TM8725 IOA IOB IOC and IOD Each I O port is composed of 4 bits and has the same basic function When the I O pins are defined as non IO function by mask option the input output function of the pins will be disabled 3 5 1 IOA PORT 1 IOA4 pins are MUX with CX SEG24 RR SEG25 RT SEG26 and RH SEG27 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX SEG25 IOA2 RR SEG26 IOA3 RT SEG27 IOA4 RH In initial reset cycle the IOA port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined as the input mode will still remain the input mode Executing IPA instructions may store the signals applied to the IO pins into the specified data memory When the IO pins are defined as the output mode executing IPA instruction will store the content that stored in the latch of the output pin into the specified data memory Before exec
147. u 84 3 8 RESISTER TO FREQUENCY CONVERTER RFCO 85 3 9 KEY MATRIX SCANNING c ssssssssssssssssssssssesesesescscscacanaeatacaearataraearaeaeacscssseeees 89 Chapter 4 LCD DRIVER OUTPUT 93 4 1 LCD LIGHTING SYSTEM IN TM8725 J u u uuu 93 4 2 DC OUTPUT cii Tungasukaman N asa 95 4 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY au u 96 Chapter5 Detail Explanation of TM8725 Instructions 101 5 1 INPUT OUTPUT INSTRUCTIONS u u uu 101 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS uuu 108 5 3 OPERATION INSTRUCTIONS u u uu 110 5 4 LOAD STORE INSTRUCTIONS uu uuu u 121 5 5 CPU CONTROL INSTRUCTIONS u uu 124 5 6 INDEX ADDRESS INSTRUCTIONS u u uu 127 5 7 DECIMAL ARITHMETIC INSTRUCTIONS uu 128 5 8 JUMP INSTRUCTIONS I u u uuu 130 5 9 MISCELLANEOUS INSTRUCTIONS u u u uu 131 Appendix 8725 Instruction Table 137 Appendix B Symbol Description
148. unction Description LCP Lz Function Description LCDX D Function Description LCTX D Function LCD latch Lz lt TAB HL HL indicates an index address of table ROM The contents of table ROM specified by HL are loaded to the LCD latch specified by Lz directly Refer to Table 4 2 Lz 00 1FH LCD latch Lz lt data decoder lt HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 4 2 Lz 00 1FH LCD latch Lz lt data decoder lt HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 4 2 If the content of HL is 0 the outputs of the data decoder are all 0 Lz 00 1FH LCD latch Lz HL AC The contents of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz Refer to Table 4 2 Lz 00 1FH Mullti LCD latches Lz s TAB HL HL indicates an index address of table ROM The content of table ROM specified by HL is loaded to several LCD latches 12 simultaneously Refer to Table 4 2 The range of multi Lz is specified by data D D 0 1 Table shows The range of multi Lz latches D 0 Mult Lz 00H 0FH Mullti LCD latch Lz lt data decoder lt HL 102 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Description The contents of i
149. usive Ored the result is loaded to AC OHL indicates an index address of data memory AC lt Q HL AC HL 1 The contents of HL and AC are exclusive ORed the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction OHL indicates an index address of data memory AC Rx lt Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC and data memory Rx 117 tenx technology inc Rev 1 0 2006 12 13 EOR HL Function Description EOR Function Description OR Rx Function Description OR Function Description OR HL Function Description OR Rx Function Description OR HL Function Description OR HL Function Description UM TM8725 E AC HL HL AC The contents of HL and AC are exclusive Ored the result is loaded to AC and data memory QHL OHL indicates an index address of data memory AC HL HL AC HL HL 1 The contents of HL and AC are exclusive ORed the result is loaded to AC and data memory QHL The content of index register HL will be increment automatically after executing this instruction OHL indicates an index address of data memory AC lt Rx AC The contents of Rx and AC are binary Ored the result is loaded to AC AC lt HL AC The contents of HL and AC are binary Ored th
150. uting SPA instruction to define the I O pins as the output mode the OPA instruction 72 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changed IOA port had built in pull down resistor The pull low device for each pin is selected by mask option and executing SPA instruction to enable disable this device Pull low function option Mask Option name Selected item IOA PULL LOW RESISTOR 1 USE IOA PULL LOW RESISTOR 2 NO USE This figure shows the organization of IOA port Initial clear SPA 1 Initial clear SPA 2 Initial clear SPA 4 Initial clear SPAS Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo serial output port by executing OPAS instruction IOA port must be defined as the output mode before executing OPAS instruction 1 BITO and BIT1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS 3 BIT3 of the port delivers pulses 73 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E Shown below is a sample program using the OPAS instruction 1 LDS OAH 0 2 OAH SPA OFH LDS 1 5 3 OPAS 1 1 Bit
151. w 1 The clock source is PH0 i e 32 768 Hz 2 The duty cycle is 1 2 Duty D 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 is the frequency deviation The following table shows the note table for melody application N FREQ Ideal 96 Tone N FREQ Ideal C2 249 65 5360 65 4064 0 19 62 260 063 261 626 0 60 E2 198 82 3317 824069 0 09 E4 49 327 680 329 628 0 59 98 165 495 164 814 041 E5 24 655 360 659255 0 59 69 234 057 233 082 042 5 17 910 222 932 328 2 37 Notes 1 Above variation does not include X tal variation 2 If PHO 65536Hz C3 B5 may have more accurate frequency 69 tenx technology inc Rev 1 0 2006 12 13 UM TM8725_E During the application of melody output sound effect output or carrier output of remote control the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 3 3 3 Halver Doubler Tripler The halver doubler tripler circuits are used to generate the bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 and PH5 When the Li battery application is used the 1 2 VDD voltage generated by the halver operation is supplied to the circuits which are not related to input output operation 3 3 4 Alternating
152. ximum output Voltage Vout1 0 3 to VDD1 2 0 3 V Vout2 0 3 to VDD3 0 3 V Maximum Operating Temperature Topg 40 to 80 C Maximum Storage Temperature Tstg 50 to 125 C 2 POWER CONSUMPTION at Ta 20 C to 70 C GND 0V Sym Condition Only 32 768KHz Crystal oscillator IHALT1 operating without loading Ag mode VDD1 1 5V 0 Only 32 768 KHz Crystal oscillator IHALT2 operating without loading Li mode VDD2 3 0V BCF 0 HALT mode STOP mode ISTOP Note When RC oscillator function is operating the current consumption will depend on the frequency of oscillation 8 tenx technology inc Rev 1 0 2006 12 13 3 ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND OV Name Condition UM TM8725 E Supply Voltage Oscillator Start Up Voltage Crystal Mode Oscillator Sustain Voltage Crystal Mode Supply Voltage Ag Mode 1 8 Supply Voltage EXT V Li Mode 5 25 Input H Voltage Input Voltage Ag Battery Mode VDD1 0 7 0 7 Input Voltage Input Voltage Li Battery Mode VDD2 0 7 0 7 Input Voltage Input Voltage OSCIN at Ag Battery Mode 0 8xVDD1 VDD1 0 0 2xVDD1 Input Voltage Input Voltage OSCIN at Li Battery Mode 0 8xVDD2 VDD2 0 0 2xVDD2 Input Volt

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