Errata Sheet: LPC18S5x/S3x
Contents
1. 17 4 1 Definitions een 17 4 2 Disclaimers 2 b 17 4 3 Trademarks 17 5 Contents nsa RE kde nade 18 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information B V 2015 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 23 October 2015 Document identifier ES LPC18S5X S3X FLASH All rights reserved2. typedef volatile struct volatile uint32 t cap volatile uint32 t curr volatile uint32 t next dTD volatile uint32 t total bytes volatile uint32 t buffer0 volatile uint32 t bufferl volatile uint32 t buffer2 volatile uint32 t buffer3 volatile uint32 t buffer4 volatile uint32 t reserved volatile uint32 t setup 2 volatile uint32 t gap 4 DOH T This is an Interface Event callback routine ErrorCode t USB Interface Event USBD HANDLE T hUsb USB CORE T pCtrl USB CORE T hUsb uintl6 t wIndex pCtrl SetupPacket wIndex W Interface number uintl6 t wValue pCtrl gt SetupPacket wValue W Alternate setting number if wIndex isochronous interface number amp amp wValue 1 ES_LPC18S5X_S3X_FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 12 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices T DOH T 0x40006158 ENDPOINTLISTADDR register int OH idx endpoint address amp 0x0F lt lt 1 1 ep OH QH idx cap packets executed per transaction descriptor lt lt 30 maximum packet size 16 return LPC_OK The value of isochronous_interface_number should correspond to the interface number in the USB descriptor that holds the isochronous endpoint y
3. RX buffer as busy and allow base handler to queue the buffer 9g ep RxBusy 1 break case USB EVT SETUP reset the flag when new setup sequence starts case USB EVT OUT we received the packet so clear the flag g ep RxBusy 0 All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 10 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash ES LPC18S5X S3X FLASH Errata sheet LPC18S5x S3x flash based devices break return g EpOBaseHdlr hUsb data event Install the endpoint 0 patch immediately after USB initialization via the hw Init call ErrorCode t usbd init void USBD_API_INIT_PARAM_T usb_param USB_CORE_DESCS_T desc ErrorCode_t ret LPC_OK USB CORE CTRL T pCtrl USB Initialization ret USBD API hw Init amp g AdcCtrl hUsb amp desc amp usb param if ret LPC OK register EPO patch pCtrl USB CORE T g AdcCtrl hUsb convert the handle to control Structure g Ep BaseHdlr pCtrl ep event hdlr 0 retrieve the default OUT handler pCtrl ep event hdlr 0 EPO patch set our patch routine as EP OUT handler return LPC OR All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 11 of 18 NX
4. 19 Set power state in PMC LPC_PMC gt PDO_SLEEPOQ_MODE DEEP POWER DOWN MODE Set CORE RST in RGU LPC_RGU gt RESET_CTRLO 1 0 2 To initialize the device correctly assert a second external reset signal to the pin after 20 us from the first reset ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 16 of 18 NXP Semiconductors ES LPC18S5x S3x Flash 4 Legal information Errata sheet LPC18S5x S3x flash based devices 4 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 4 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if pro
5. Section 3 1 Section 3 2 Section 3 3 Section 3 4 Section 3 5 Section 3 6 Section 3 7 Section 3 8 Section 3 9 Section 3 10 Section 3 11 Table 3 Errata notes table Errata notes n a Short description n a Revision identifier n a Detailed description n a ES_LPC18S5X_S3X_FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 3 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 Functional problems detail ES_LPC18S5X_S3X_FLASH 3 1 EEPROM 2 Introduction 16 kB EEPROM is available on these parts which operates up to 180 MHz Registers in the EEPROM define the number of wait states that are applied to read and write operations on the device Problem The reset values for the RWSTATE and WSTATE registers in the EEPROM block are different from what is shown in the user manual Table 4 Reset values for RWSTATE and WSTATE Reset value for Rev parts Reset value in the Users Manual RWSTATE 0000 0905 0000 0 07 WSTATE 0002 0602 0004 0802 Work around No workaround needed Program the required values into the registers before using the EEPROM All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 O
6. down unsigned int PD SLEEPO MODE POWER DOWN MODE enter power down xfi ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 7 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash ES LPC18S5X S3X FLASH Errata sheet LPC18S5x S3x flash based devices 3 5 USB 1 Introduction The LPC18S5x parts include two USB 2 0 controllers that can operate in host mode at high speed One of these controllers USBO contains an on chip high speed UTMI compliant transceiver PHY which supports high speed full speed and low speed USB compliant peripherals Problem The USB controller called USBO is unable to communicate with a low speed USB peripheral in host mode when there is a full speed hub directly connected to the USBO port and a low speed peripheral is connected in the tree somewhere below this full speed hub Only USBO has this problem the other USB controller USB1 does not Work around There is no work around for this problem It is suggested that the low speed USB peripheral is either connected directly to USBO or a high speed hub is placed between that peripheral and USBO Does not work Low speed peripheral Full speed HUB Does work 1 Low speed peripheral 2 Low speed peripheral 3 Low speed peripheral Full speed
7. Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities 4 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 17 of 18 NXP Semiconductors ES LPC18S5x S3x Flash 5 Contents Errata sheet LPC18S5x S3x flash based devices 1 Product identification 3 2 Errata overview 3 3 Functional problems detail 4 3 1 2 bL PEDE EG ied 4 3 2 i i ite EPUHP PRI IE EA 5 3 3 plex PEE 6 3 4 SRAMI ves xe ree eU e 7 3 5 USB eee otk erit e fa 8 3 6 USB25 5 2Rilb6RIe4denmieie cbe P nU 9 3 7 1 10 3 8 WSBROM 2 12 3 9 SD MMC T km Ele eee REY 14 3 10 RESET I 2 inue tora 22 ee E deemed 15 3 11 RESET up nS 16 4
8. ES LPC18S5x S3x Flash Errata sheet LPC18S5x LPC18S3x flash based devices Rev 1 1 23 October 2015 Errata sheet Document information Info Content Keywords LPC18S57JET256 LPC18S57JBD208 LPC18S37JBD144 LPC18S37JET100 ARM Cortex M3 flash based devices errata Abstract This errata sheet describes both the known functional problems and any deviations from the electrical specifications known at the release date of this document Each deviation is assigned a number and its history is tracked in a table NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices Revision history Rev Date Description 1 1 20151023 Added RESET 2 1 20150213 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 2 of 18 NXP Semiconductors ES LPC18S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 1 Product identification The LPC18S5x S3x flash based devices hereafter referred to as LPC18S5x typically have the following top side marking LPC18S5xxxxxxx XXXXXXXX xxxY YWWxR x The last second to last letter in the last line field R will identify the devi
9. HUB Fig 1 Suggested USBO to low speed peripheral connections All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 8 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 6 USB 2 Introduction The LPC18S5x flash based devices contain an event handler for USB SOF detection from the host called the USB SOF Event When it is enabled this event fires at the start of each USB frame once per millisecond in full speed mode or once per 125 microseconds in high speed mode and is synchronized to the USB bus Problem The USB SOF Event may fire earlier than expected and or an additional false interrupt may be generated Work around There is no work around The USB SOF Event cannot be used in full speed and high speed device mode in case the system needs an interrupt that is aligned with the incoming SOF tokens ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 9 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash ES LPC18S5X S3X FLASH Errata sheet LPC18S5x S3x flash based devices 3 7 USBROM 1 Introduction The USB ROM drivers include a default endpoint 0 handler which acts on events generated by the USB controller as a result o
10. P Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 8 USBROM 2 Introduction The USB ROM drivers configure and manage data structures used by the USB controller s DMA engine to move data between the controller s internal fifos and system memory The configuration of these data structures are based on many parameters including the type of transfer control bulk interrupt or isochronous that is to be performed These data structures reside in system RAM on a 2 kB boundary and are pointed to by the ENDPOINTLISTADDR register Problem The USB ROM drivers incorrectly configures the Endpoint Capabilities Characteristics field of the device Queue Head dQH structure for isochronous endpoints Specifically the MULT member is set to 0 and the ZLT member is set to 1 Also if the maximum size of isochronous packets are 1024 bytes the Max_packet_length member will be set to 0 For any other packet size this member is set correctly Work around To use isochronous transfers with the USB ROM drivers the Endpoint Capabilities Characteristics field must be correctly configured for that endpoint s device Queue Head structure The USB ROM driver always sets this field incorrectly when the host sends a Set Interface control packet and then it calls the USB_Interface_Event callback routine so the field must be set with the proper value in this callback routine This is the device Queue Head structure
11. ce revision This Errata Sheet covers the following revisions of the LPC18S5x flash based devices Table 1 Device revision table Revision identifier R aN Revision description Initial device revision Field YY states the year the device was manufactured Field WW states the week the device was manufactured during that year 2 Errata overview Table 2 Functional problems table Functional problems EEPROM 2 EMC 1 I2C 1 SRAM 1 USB 1 USB 2 USBROM 1 USBROM 2 SD MMC 1 RESET 1 RESET 2 Short description Reset values for the RWSTATE and WSTATE registers in the EEPROM block are different from what is shown in the user manual Operating frequency of EMC lower than data sheet value In the slave transmitter mode the device set in the monitor mode must write a dummy value of OxFF into the DAT register SRAM in deep sleep and power down modes may lose state USBO unable to communicate with low speed USB peripheral in host mode when using full speed hub The USB_SOF_Event may fire earlier than expected and or a false interrupt may be generated Nested NAK handling of EPO OUT endpoint Isochronous transfers Data CRC error returned on CMD6 command Master Reset MASTER_RST and M3 Reset M3_RST are not functional Loss of device functionality on reset via NRESET in deep sleep and power down mode Revision identifier 7 N TN Detailed description
12. ctober 2015 4 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash ES_LPC18S5X_S3X_FLASH Errata sheet LPC18S5x S3x flash based devices 3 2 EMC 1 Introduction The LPC18Sxx parts contain an External Memory Controller EMC capable of interfacing to external SDRAM SRAM and asynchronous parallel flash memories The EMC can be configured to operate at the processor core frequency BASE M3 CLOCK or the core frequency divided by 2 Problem For SDRAM the electrical characteristic of the LQFP144 and LQFP208 packages limits the operating frequency of the EMC to a certain level which is lower than the specified value in the data sheet Choosing an SDRAM clock of 72MHz as the upper limit provides some safety margin This frequency is either achieved by a core and EMC frequency of 72MHz or by a 144MHz core and a 72MHz EMC frequency However SDRAM performance can vary depending on board design and layout Work around There is no work around The upper limit of the SDRAM clock frequency is highly dependent on the PCB layout and the quality of the power supply and de coupling circuitry All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 5 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash 3 3 Errata sheet LPC18S5x S3x flash based devices 12C 1 Introduction The I2C monitor allows the device to monitor the 12 t
13. etend to shift out OxFF LPC_I2C gt CONCLR 0x08 clear flag SI break ES_LPC18S5X_S3X_FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 6 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 4 SRAM 1 Introduction SRAM state is retained in deep sleep and power down modes Problem Incorrect settings may lead to SRAM state retention loss over time and temperature This can cause erratic behavior due to SRAM data loss after wake up from deep sleep mode or power down mode Work around Reserved register at 0x4004 3008 bits 17 16 should be set to 0x2 before entering deep sleep mode or power down mode define CREGO 008 0x40043008 define PDO_SLEEPO_MODE 0x4004201c define PMC PWR DEEP SLEEP MODE 0x3F00AA define PMC PWR POWER DOWN MODE Ox3FFCBA unsigned int regval EXAMPLE 1 regval unsigned int CREGO 008 regval 1 lt lt 17 regval amp 1 lt lt 16 unsigned int CREGO 008 regval prepare for entering deep sleep unsigned int PD SLEEPO MODE DEEP SLEEP MODE enter deep sleep _wfi EXAMPLE 2 regval unsigned int 008 regval 1 lt lt 17 regval amp 1 lt lt 16 unsigned int CREGO 008 regval prepare for entering power
14. f traffic occurring over the control endpoint The user has the option of overloading this default handler for the purpose of performing user specific processing of control endpoint traffic as required One of the actions the default endpoint 0 handler performs is to prepare the DMA engine for data transfer after the controller has sent out a NAK packet to the host controller This is done in preparation for the arrival of the next OUT request received from the host Problem Due to a race condition there is the chance that a second NAK event will occur before the default endpointO handler has completed its preparation of the DMA engine for the first NAK event This can cause certain fields in the DMA descriptors to be in an invalid state when the USB controller reads them thereby causing a hang Work around Override the default endpoint 0 handler to add checks for and prevents nested event processing activity This is an example of how to do this Endpoint 0 patch that prevents nested NAK event processing static uint32 t g epORxBusy 0 flag indicating whether EPO OUT RX buffer is busy static USB EP HANDLER T g_Ep0BaseHdlr variable to store the pointer to base handler ErrorCode t patch USBD HANDLE T hUsb void data uint32 t event switch event case USB_EVT_OUT_NAK if g epORxBusy we already queued the buffer so ignore this NAK event return LPC OK else Mark
15. ou wish to use The value of maximum_packet_size should correspond to the wMaxPacketSize member of the isochronous endpoint descriptor The value of endpoint_address should correspond to the bEndpointAddress member of the isochronous endpoint descriptor ES_LPC18S5X_S3X_FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 13 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 9 SD MMC 1 Introduction The LPC18Sxx parts have the SD MMC interface After power up the SD memory card is in the default speed mode and by using the Switch Function command CMD6 the Version 1 10 and higher SD memory cards can be placed in High Speed mode In response to the CMD6 command the SD card returns a 512 bit block of data containing the available features and actual settings The SDIO interface is setup for 4 bit data and therefore the 512 bits are returned on the four data lines in 128 clocks followed by 16 clocks of CRC data Problem The CMD6 returned status block always gets a data CRC error although the status data is correct The data CRC error prevents the switching of SD memory card from the default mode to High Speed mode Work around To capture the 512 bits of data and CRC data the DMA buffer length and SD MMC BYTONT are increased to 72 and then the CRC is calculated in
16. raffic on the I2C bus in a non intrusive way Problem In the slave transmitter mode the device set in the monitor mode must write a dummy value of OxFF into the DAT register If this is not done the received data from the slave device will be corrupted To allow the monitor mode to have sufficient time to process the data on the I2C bus the device may need to have the ability to stretch the I2C clock Under this condition the I2C monitor mode is not 100 non intrusive Work around When setting the device in monitor mode enable the SCL bit in the MMCTRL register to allow clock stretching Software code example to enable the ENA SCL bit LPC I2C MMCTRL 1 1 Enable ENA SCL bit In the I2C ISR routine for the status code related to the slave transmitter mode write the value of OxFF into the DAT register to prevent data corruption In order to avoid stretching the SCL clock the data byte can be saved in a buffer and processed in the Main loop This ensures the SI flag is cleared as fast as possible Software code example for the slave transmitter mode case OxA8 Own 51 R has been received returned case OxB0 case 0 8 data byte in DAT transmitted ACK received case 0 0 last data byte transmitted NACK received case 0xC8 last data byte in DAT transmitted ACK received DataByte LPC_I2C gt DATA_BUFFER Save data Data can be process in Main loop LPC_I2C gt DAT OxFF Pr
17. software If the CRC is correct for all four data lines the error is cleared ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 14 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 10 RESET 1 Introduction The LPC18Sxx parts contain a Reset Generation Unit RGU that generates various resets Core Reset CORE_RST Peripheral Reset PERIPH_RST Master Reset MASTER_RST and M3 Reset M3_RST Problem On the LPC18Sxx MASTER_RST and M3_ RST are not functional Work around There is no work around To reset the entire chip use the CORE_RST instead of using MASTER RST or RST ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers NXP B V 2015 All rights reserved Errata sheet Rev 1 1 23 October 2015 15 of 18 NXP Semiconductors ES LPC1 8S5x S3x Flash Errata sheet LPC18S5x S3x flash based devices 3 11 RESET 2 Introduction The LPC18Sxx devices are initialized after a reset If a reset occurs via nRESET pin when the part is in Deep sleep or Power down mode the initialization state of the device may be erroneous and some functionality of the device may be lost Problem When the part is in deep sleep or power down mode and if an external reset occurs via nRESET pin being acti
18. vated as the part comes out of reset the reset state of some functional blocks may be incorrect This may result in loss of functionality of the device The actual functionality lost may vary from part to part depending on the erroneous reset state of the functional blocks The possible affected blocks are Ethernet LCD controller CANO CAN1 USBO USB1 AES SRAM size at 0x2000 0000 may change to 16 kB SRAM size at 0x2000 8000 may change to 0 kB and SRAM size at 0x2000 C000 may change to 0 kB Work around There are two possible work arounds 1 In the application software before initializing peripherals the code should assert a soft reset using the following steps a Read the value in power down modes register PDO_SLEEPO_MODE b If the value in the SLEEPO MODEO register represents deep sleep mode or power down mode the user should check if a reset event occurred on the nRESET pin bit 19 in the Event Status register c If the reset event occurred the software should set the PDO SLEEPO MODE register to deep power down mode and assert a soft reset using the CORE RST bit 0 in the RESET CTRLO register Check if wake up event happens in Deep Sleep or Power Down mode if LPC PMC PD0 SLEEPO MODE PWR DEEP SLEEP MODE LPC PMC PDO0 SLEEPO MODE POWER DOWN MODE Check if the wake up event is due to nRESET pin in Event router if LPC_EVRT gt STATUS amp 1
19. vided by an information Source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or ES LPC18S5X S3X FLASH All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonabl
20. y be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s
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