Uni ted States Department of the Interior Geol ogical Survey AN ON
Contents
1. l OF 2 JO ROGERS U S Gealogices Surveg D E V f Hi Middimftald Rd Mente Park 84425 x 17 The wiring dfagram for the clock interface card cable is given in Appendix 5 3 6 Mass Storage f The contents of the parameter buffer are dumped to the mass storage device every 19 events Efther a low cost cassette tape recorder RAMcassette may be used The RAMcassette is several times more expensive than the cassette but can operate reliably over a larger temperature range and hold more data The RAMcassette consists of an array of 8k byte by 8 bit CMOS RAM chips which all share the same address lines chip select signa determines which RAM from the array is active This signal is produced by CD4516 CMOS 1 of 16 decoder The c rcuit diagram of the 128k byte version 15 shown in Figure 4 The operation of the circuit is fairly straight forward fF ve hexadecimal switches pre load an address into the 17 bit counter chain 127 031 when the reset button 15 pushed This address determines where memory array read write operations will start Bits O through 12 of the counters are used to address each RAM memory location while bits 13 through 16 are input to the decoder The counter is software controlled by the words and CTRL Each execution of this pa r of words advances the address by one count The array s activated by the ENB word which rem2. after the header The header information is also displayed on a terminal if one 1s connected during the event input voltage volts counts 0 019532125 where counts is a hexadecimal number and must be converted to base 10 before multiplication 3 3 Memory Expansion Board 1805 CPU can address up to 64k bytes of memory of which 8k bytes of ROM are on the CPU board along with 4k bytes of RAM Another 2k bytes of ROM and lk byte of RAM are on the Tape 1 0 board This leaves about 50k bytes open for expans on of ELOG specific FORTH words Due to the compactness of FORTH only 4k bytes are needed for the entire ELOG program which is n two 27 16 2k byte by 8 bit CMOS EPROMs 3 4 Tape 1 0 Board The Tape 1 0 board serves the purpose of providing additional memory sockets and interfacing with the cassette tape recorders The memory held on this board is the utility ROM RCA UT62 and the FORTH editor and assembler CPU reset switch 15 also located on this board When switched between reset and ave a Signal 1 generated which causes the CPU to execute the utility program UT62 3 5 Interface Board The Interface Board provides regulated power for the entire system buffers the paralle time input from the clock and conditions the sensory input Figure 3 displays the electronic schematic in two sections for this circuit 3 51 Power Regulation One LM309 3 pin voltage regulator provides 5 volts to power the system elect
3. YINC INCR BY 2 2 NEUF gt IF THEN s YDEC DECR 2 2 YCTR 2 O lt IF 10 NBUF THEN 11 z SVBUF BUF gt RAM 12 CTRL MEMWR ENB SBFPTR 15 24 0 WR 40 BYTES gt RAM 14 E R CTRH CTRL 15 LOOP DIGER QUD 4005 50Ne 39g 0 G N 14 gt 17 18 SCR 14 O ELOG WORDS 1 RDCHAR RAM gt ELOG 2 CTRL MEMRD SELPTR gt CTRL DISB 4 RDREC REC RS2352 24 RDCHAR 48565 LOOP RDRECS N RECS gt RS232 7 DO RDREC LDOP B 2 9 10 11 2 15 14 15 16 17 31 SCRK 1 ELD amp WORDS HEX 1 PRDY 2 4686 C9 WAIT NEW SAMPLE 3 BEGIN DROP 4686 UNTIL SP 4 1 NXT REMOVE MEAN 5 9 YOLD 6 4685 BO YNEM 275 COMPL 7 1 YNEW 2 YCTR 9 BOT 8 YCTR YINCF j 9 3 SAVG 9 ABV STA 9 10 STA RSTA 11 9 N STA RSTA 12 5 13 14 15 16 17 18 SCR 16 ELOG WORDS HEX 1 LAVG YNEW 9 ABV LTA 2 K LTA 5 a K LTA RLTA j 4 KEEP SAVE YCTR LTA STA 5 LTA 9 TLTA STA 9 TSTA 6 9 TYCTR RSTA 9 TRSTA 7 RSTR RESTORE 3 VAR B 9 LTA TSTA STA 9 9 TRSTA 9 RSTA j 10 5 11 12 15 14 15 16 17
4. CK IN 5 SEC 2 NZRO KEEP RESET 0 CTR SPS WIND DO 4 9 9 15T POINT 5 9 2 9 ZND POINT 6 IF SEE IF SIGN CHANGE 7 1 THEN LOOP 9 gt ELOG WORDS 24 4 DOLT WRTM 2 IMAX 4 WRRY o 4856 6 6 0 gt 8 9 2 4556 I FO AND 2 2 2 2 QUTFUT DATA YDEC FRST PCTR WRBY IMOT WRVR WRBY TMXS WRBY WRVR LTA ECTR WRVR NZRO WRVR TPTR 1 4836 OPTR SVRBUF DO 4855 1 OF AND 2k 2 2 LOOF CR 10 PETR IMOT IMAX TMXS NSLT LTA ECT 11 NZRO CR SPACE 12 PCTR 2 SPACES 2 SPACES 15 IMAX SPACES TMXS 2 SPACES 14 SPACE 4 SPACES 15 ECTR SPACE NZRO CR 16 17 18 25 O ELOG WORDS 1 PEVT CHECK FOR TRIG 2 STA LTA 9 5 gt IF RDTM BELL TAIL GET TIME FIRST 4 ECTR 1 COUNT EACH 5 AMPL FREQ SRCH VALID CHECK 6 NSLT 9 lt ENERGY 7 NZRO 9 15 FREQ TEST 8 126 4 lt IMPL TEST 9 AND AND CONDITIONS TRUE 10 IF DOUT THEN STA 9 LTA THEN 11 gt SCR 26 O ELOG WORDS HEX RUN RUN PROG ITAPES INIT ILD CTDS MIE IADR ADPG IADR 1 2 BEGIN 4 S IADR CTEN PRDY NRDY PUTY SAVG CTEN RDY NRDY LAVG amp IADR CTEN RDY NRDY 7 1 L
5. United States Department of the Interior Geological Survey AN ON SITE SEISMIC DATA RECORDING SYSTEM by John Rogers and John Lahr Open File Report 86 251 Menlo Park California 1986 The report 1 preliminary and has not been edited or reviewed for conformity with Geological Survey standards and nomenclature use of trade names and trademarks in this publicat on 1 for descriptive purposes only and does not constitute endorsement by the U S Geological Survey 35 Table of Contents PAGE 1 Introduction ccucnecvvccnnnccnvoccscscrccasvvccasssaceaua 4 2 Program Organization 7 2 1 Data Sampling eee 444 444 8 2 2 Verification of Events 8 4 4 8 2 3 Event Recording 4 9 3 System Hardware 44 4 4444 44 4 12 3 1 CPU Card 12 3 2 A D Converter TX 8 12 3 3 Memory Expansion 14 3 4 1 0 14 3 5 Interface Board 44 peesooseoeseossasconos 14 3 51 Power 14 3 52
6. whole operation is similar to the FORTRAN subroutine Defining new words from already defined words or from assembly language gives FORTH its extensibility FORTH uses two stacks for inter word communication and math The stack orientation of FORTH makes the use of reverse polish operations necessary even though code becomes harder to read All math is done tn fixed point as FORTH does not support floating point Tape 1 0 and the terminal interface is accomplished by calls to a utility ROM UT62 supplied by RCA Thts ROM contains the usual utility routines for writing to tape reading from tape examining memory etc addition one UT62 routine automatically sets the ELOG baud rate to match that of the termina up to 1200 baud 2 1 Data Sampling The sampling routine 1 interrupt driven by a counter internal to the 1805 CPU The counter 15 preset to an initial value by the word ADPG screen 2 which controls the sampling rate Each time the counter goes through zero the CPU is interrupted and the data sampled the case where a higher sampling rate is desired the counter is pre set to a lower value In practice the sampling rate is limited to 100 Hz or less by the CPU processing speed The sampling loop first selects the A D by outputting a code 30H hex which conforms to the RCA two level I O addressing scheme 8 This selection is necessary since there are several I 0 devices connected to the CPU The A D is hard wired to be se
7. 4 9 2 18T POINT BOT 39 2 9 2ND POINT 6 O lt IF SEE IF SIGN CHANGE 7 NZRO 1 THEN 8 LOOP RSTR j 9 10 11 12 13 14 15 16 17 18 SCRS 19 ELOG WORDS HEX 1 DOUT OUTPUT DATA 2 WRTM YDEC FRST PCTR WRBY IMOT WRVR IMAX URBY TMXS WRBY NSLT WRVR LTA 4 WRVR NZRO WRVR 5 4 4656 TPTR 9 482 gt amp IF SAVE BUFFERS 4826 OFTR 7 80 4834 C 4855 C9 1 4835 8 USE 1 THEN 9 60 4B36 OF AND 10 2k 2 2 2 11 4856 I FO AND 2 2 2 2 12 LOOP CR 13 PCTR IMOT IMAX TMXS N3LT LTA 14 NZRO CR SPACE 15 PCTR 2 SPACES IMOT 2 SPACES 16 IMAX 3 SPACES TMXS 2 SPACES 17 NSLT 7 SPACE LTA 4 SPACES 18 ECTR SPACE NZRO CR 3 gt 20 ELOG WORDS HEX 1 YEVT CHECK FOR TRIG 2 STA 9 LTA 9 5 gt IF RDTM BELL TAIL GET TIME FIRST 4 ECTR 1 COUNT EACH 5 AMPL FREQ SRCH VALID CHECK 6 NSLT 2 B4 lt ENERGY 7 NZRO 3 15 gt FREQ TEST B PCTR 9 12C lt IMPL TEST 9 AND AND CONDITIONS TRUE 10 IF DOUT THEN STA LTA THEN 11 gt 12 13 14 15 16 17 42 x P SCR 21 1 5 i ELOS WORDS t RUN RUN PROG gt TAPES INIT ILD CTDS MIE IADR ADPG BEGIN 4 IADR CTEN RDY NRDY SAVG IADR CTEN RDY NRDY NXT PUTY LAVG b IADR CTE
8. 15 01 gt gt 50 gt gt E2 gt gt B gt gt OD gt gt 16 70 gt gt 17 gt 18 20 O ELOG WORDS HEX 1 WRVR ADDR DUF DUF DUF 2 2 DO WR 4 BYTES gt BUFFER 5 I 2 2 2 2 OF AND 4 DPTR OFTR 1 5 I AND 1 7 LOOP WRTM lt 9 5 O DO 11 TIME 1 STATUS BUF 10 2 AND 11 1 12 TPTR 9 2 2 2 2 OF AND 15 9 1 1 14 LOOP 15 gt 16 17 33 SCR 21 ELOG WORDS HEX 1 SRCH 4 FIND LDTHRSH TIME PCTR KEEP INITIALIZE NBUF 4 BOT YNEW SAVG STA 9 LTA 2 LTRG lt STA 9 LTA 9 LTRG k OR IF LEAVE THEN PCTR 1 YDEC LOOF LTA 2 STA RSTA REST STA 10 40 DO LOOK BACK FOR START 11 2 BOT 3 YNEW FAVG 12 STA 2 LTA 3 LTRG gt IF 13 LEAVE THEN 1 PCTR YINC 14 LOOF 3 N D Ul PAH SCRH 22 ELOG WORDS HEX j TAIL t 5SEC FOST EV 2 KEEP l SAVE YCTR STA LTA 5 ADPG CTEN START CTR ENB INTR 4 SPS WIND O DO 5 IADR CTEN RDY ADPG n NXT LOOP 7 AMPL DURATION CHECK 8 KEEP O 9 8 5 WIND DO 10 YINC 11 YCTR 9 9 YNEW SAVG 12 STA 9 LTA 9 2 lt IF 15 NZLT 1 THEN 14 LOOF gt NSLT24VIOLATIONS 15 gt SCR 23 O ELOG WORDS HEX 1 FREQ
9. 1B SCR4 17 O INITIALIZATIONS HEX 1 INIT INITIALIZE VAR 2 97 USE WRITE gt SCR 97 3 8096 4834 BOsUPDATE 62SCRW 4 YNEM YOLD Q YCTR S 1 STA 10 LTA 1 TSTA amp O O PCTR 7 IMAX IMOT O TMXS B 4836 4B36 TPTR 9 4687 IPTR O F NZRO 10 1 TLTA 1 TYCTR 11 ECTR 2 gt 15 14 15 16 17 32 18 ELGG WORDS HEX 1 FRST FIRST 2 1 IMAX 1 IMOT TMXS KEEP 5 PCTR 9 ABS DO YDEC LOOP 4 9 ROT IMOT 9 LTRG 5 BEGIN LOOK FOR MAX amp MIN amp IMOT 9 BOT 9 gt 7 9 9 BOT B WHILE 9 YCTR 9 9 ABS IMAX 9 10 MAX IMAX 11 TMXS 1 YINC 12 REPEAT RSTR 15 gt 14 15 16 17 18 SCR4 19 ELOG WORDS HEX 1 WRBY ADDR 2 1 C9 2 2 Z 2 OF AND OPTR 9 OPTR 1 4 1 OF AND 5 OPTR 9 OFTR 1 3 6 gt gt l BYTE INTR LOADER 7 IPTR 1 3 B ILD INTR 4688 46BE 9 78 gt gt EO gt gt F8 gt gt B2 gt gt AO gt gt 10 gt gt 46 gt gt BO gt gt gt gt 350 gt gt 11 50 gt gt 61 gt gt F8 gt gt QQ gt gt 50 gt 12 66 gt gt FB gt gt OO gt gt 60 gt gt 65 gt gt 15 FB gt gt 09 gt gt AB gt gt 2B gt gt BB gt gt 14 gt gt 9F gt gt 6B gt gt 10 gt gt FB gt gt
10. O ELOG WORDS 1 WRVR ADDR DUP DUP DUF 2 20 DO WR 4 RYTES BUFFER S 2 2 2 Z OF AND 4 509 OPTR OFTR 1 0 6 OFTR OPTR 1 7 LOOP B s WRTM 9 6 O DO 11 TIME 1 STATUS gt RUF 10 9 OF AND 11 SO OPTR DPTR 1 12 JPTR 9 2 2 2 2 OF AND 13 OFTR 2 OPTR 1 TPTR 1 14 LOOP 15 gt 16 17 18 SCR 14 O ELOG WORDS HEX 1r SRCH FIND LOTHKSH TIME 2 PCTR KEEP INITIALIZE 3 NBUF 4 O DO 4 9 9 YNEW SAVG 5 STA LTA 9 LTRG X lt 6 STA 2 LTA 9 OR IF 7 LEAVE THEN B 1 YDEC 9 OOP 10 LTA 9 STA RSTA RESET STA 11 40 O DO LOOK RACK FOR START 12 9 BOT YNEW FAVG 1 STA 9 LTA 3 gt IF 14 LEAVE THEN 1 PCTR YINC 15 LOOP RSTR 2 14 17 18 SCR 17 ELOG WORDS HEX 1 TAIL SSEC POST EV 2 SAVE YCTR STA LTA x ADPG START CTR INTR 4 SPS WIND O DO IADR RDY ADPG 6 NRDY LDOF 7 AMPL DURATION CHECK 8 KEEP NSLT 9 SFS WIND O DO 10 YINC 11 9 9 YNEW SAVG 12 STA 9 LTA 9 2 k lt IF 15 NSLT 1 THEN 14 LOOP RSTR y NSLTZWVIOLATIONS 15 gt 16 17 41 SCRM 18 O ELOG WORDS HEX 1 FREQ CK 0 IN 5 SEC 2 NZRO KEEP RESET 0 CTR 5 SPS WIND DO YINC
11. O INC 13 O LDI O STR 6 OUT O DEC 4 INF Q INC 16 9 SEF END CODE 17 gt 18 SCR 2 CODE DEFINITIONS 19 CODE ADFG PGRM 1805 XID CID STPC 49 101 LDC STM 9 SEP END CODE CODE MIE 4 SET MIE ALLOW INTR RET 9 SEP END CODE CDDE CTEN ENB 1805 CTR INTR CIE 9 SEP END CODE CODE CTDS DISENB 1805 CTR INTR CID 9 SEP END CODE CODE IADR INTR HANDLER ADDR 88 LDI 1 PLO 46 LDI 1 PHI 9 SEP END CODE CODE NRDY i gt DATA NOT RDY 46 LDI PHI 86 LDI O PLO O LDI 9 SEP END CODE 27 5 CODE DEFINITIONS HEX 1 CODE SET CTR F F 2 34 LDI O PLO 48 LDI O PHI 8 LDI 0 STR O SEX 1 OUT O DEC SEL PORT 4 5 LDI O STR 2 OUT O DEC B QUT 98 LDI O STR 6 OUT O DEC F FzQ amp 9 SEF END CODE 7 CODE CTRL CLEAR F F 8 34 LDI O PLO 48 LDI PHI 8 LDI 9 0 STR O SEX 1 QUT O DEC SEL PORT 10 53 LD O STR 2 GUT DEC B 0UT 11 99 LDI O STR 6 QUT O DEC F F 1 12 9 SEP END CODE 15 gt 14 15 16 17 18 SCRH A O CODE DEFINITIONS HEX 1 CODE MEMUR SET R W MEM TO WR 2 34 LDI PLO 48 LDI O PHI B LDI 5 0 STR O SEX 1 OUT O DEC SEL PORT 4 LDI O STR 2 OUT DEC A 0UT 5 SX LDI O STR 2 OUT Q DEC R QUT 16 LDI O STR 6 QUT O DEC MEM RD 7 9 SEP END CODE CODE MEMRD SET R W H READ 9 34 LDI O PLO 48 LDI LDI 10 0 STR 0 SEX 1 OUT O DEC SEL PORT 11 B LDI Q STR 2 OUT DEC A IN 12 53 LDI STR 2 OUT
12. ONSET THRESHOLD 960 CONSTANT NBUF SIZE gt 38 SCR ELCG WORDS HEX 1 FAVG YNEW 9 ABS STA 2 4 MOD 2 STA RSTA 5 RSTA 4 MOD STA RSTA 4 1 STA 8 STA INCR BY 2 amp 2 YCTR 9 NBUF gt IF 7 THEN YDEC DECR YCTR BY 2 9 2 9 O lt IF 10 NBUF YCTR THEN 11 lt gt 12 13 14 15 16 17 18 SCR 10 O ELOG WORDS HEX 1 PRDY 2 4686 WAIT NEW SAMPLE BEGIN DROP 4686 UNTIL SP 4 s NXT REMOVE MEAN S YNEW 9 YOLD amp 4685 BO YNEW 27S COMPL 7 PUTY YNEW 3 3 BOT B YINCF 9 6 8 YNEW STA N id STA RSTA 11 9 N STA RSTA 12 gt 12 14 15 16 17 18 11 4 ELOG WORDS 1 LAVG 3 ABV LTA 2 K LTA 5 9 K LTA RLTA 4 KEEP SAVE YCTR LTA STA LTA 2 STA 9 TSTA RSTA 9 TRSTA 2 7 RESTORE 5 VAR B LTA TSTA STA 9 RSTA 10 gt 11 12 13 14 15 16 17 18 39 12 SCR lt INITIALIZATIONS s INIT INITIALIZE VAR 97 USE WRITE gt SCR 97 BO9S 4834 96 3 YNEW O
13. Signal Conditioning and Amplification TOPPED 14 3 53 Time Buffering 444 4 14 3 6 Mass Storage ecesaassacanseccenveceeves 4 TEUER 17 3 7 Real Time 1 84 4 17 4 Operations seve 20 4 1 Battery Considerations 4 20 4 2 Setting the 1 20 4 3 Sensor Installation ecsoavotus 4 sessansenasosaosne 23 4 4 ELOG Setup a a 23 444 4 44 24 Appendices 1 1 5 4 4 25 2 Interrupt Handler 26 3 ELOG RAM Cassette Software TED 4 44 84 4 27 4 ELOG Cassette Tape 50 36 5 Wiring 2 44 6 Automatic Threshold Adjusting 444 46 Acknowledgements The University of California Berkeley ASP system furnished much of the nitial inspiration for the ELOG development and in particular Ernie Major one of the ASP developers was very helpful in some of the original
14. TRE 4834 APE UPDATE FLA NOT USED ELOG VARIABLES 472E PREDEFINED VARRIBLES A amp RC INTERUPT HANOLER 4687 NOT USED 4666 SEMAPHOR 4685 A D SAMPLE 4998 2088 acp RAM FOR UT62 UT82 MONITOR PROGRRM FIGURE 2 MEMORY ALLOCATION MAP PRE DEFINED SYSTEM FORTH WORDS 87FF X is stored along with the LTA Finally the number of triggers ECTR is stored and if the RAM cassette is used with waveform storage the index to the trigger time YCTR is also stored Each event record written to tape or RAM cassette storage contafns 36 bytes The format used is presented in Table 2 and the ELOG programs for the RAM Cassette and magnetic tape are in Appendices 3 and 4 Note that if the waveform is also stored then an extra 4 bytes of data are needed to Indicate the trigger sample in the buffer relative to the buffer beginning BOT 3 SYSTEM HARDWARE ELOG hardware consists of a card cage for the five printed circuit cards an Omega Radio receiver a clock and either a cassette tape recorder or a RAMcassette Figure 1 shows a block diagram of the system As can be seen the radfo produces synchonizing pulses which keep the clock on time after it has been initially set The parallel clock time is then available through the interface card to the The interface card also has amplifier and power converter sections Program memory is divided between the CPU Tape 1 0 and Memory expansion cards d scussion of
15. YOLD O STA 10 LTA 1 TSTA RSTA PETR O IMAX O IMOT TMXS 4856 4856 TPTR 4487 IPTR F NZRO 10 1 TLTA 1 TYCTR 11 DONDU h 12 gt 13 14 15 16 17 18 SCRN 13 ELOG WORDS HEX 1 FRST FIRST MOTION 2 1 IMAX 1 IMOT 0 TMxS KEEP 3 PCTR 9 ABS DO YDEC LOOF 4 9 BOT IMOT 9 LTRG pa BEGIN LOOK FOR amp MIN amp 9 YCTR 2 O 7 IMOT YCTR 3 BOT 9 OR 2 WHILE 9 YCTR 9 9 ABS IMAX 10 IMAX 11 TMXS 1 12 1 gt 14 15 16 17 18 SCRH 14 O ELOG WORDS 1 WREY ADDR DUP 2 1 2 2 2 2 AND 30 OPTR DPTR it 4 1 OF AND 5 9 I j 6 gt gt BYTE INTR LOADER 7 1 IPTR OC 8 ILD INTR 4698 A46BE 9 78 gt gt EO gt gt FE gt gt B2 gt gt AO gt gt 10 FB gt gt 46 gt gt BO F8 gt gt 30 gt gt 11 50 gt gt 61 gt gt F8 gt gt OO gt gt 50 gt gt 12 66 gt gt FB gt gt gt gt 50 gt gt 65 gt gt 15 gt gt O9 gt gt AB gt gt 2B gt gt BB gt gt 14 gt gt gt gt 6B gt gt 10 gt gt gt gt 15 01 gt gt 50 gt gt E2 gt gt B gt gt OD gt gt 16 70 gt gt 1 17 gt 15
16. a c rcular buffer The STA and LTA are then updated screens 15 16 and compared to see 1f a threshold has been exceeded At this point the sampling loop is e ther executed again with a new sample if the threshold test failed or program execution moves to the verify phase if the threshold was exceeded In the verify phase events are screened to minimize the recording of noise The screening involves running three tests on the data in the buffer to determine which events to save Ampl tude and frequency content must match the type of earthquake being searched for and an emergence test screens out distant events If these three tests are passed then the final recording phase is entered at which time the data is written to a RAM parameter buffer which 1 ultimately written to mass storage The ELOG software is written FORTH a computer language which finds major application dedicated microcomputer based control systems FORTH is a threaded interpretive extensible language 5 6 7 The term threaded has to do with the way FORTH code is compiled In traditional compiled languages source code 15 translated nto machine language as a unit and can only be executed as a unit In FORTH each word is compiled separately and can be executed either by itself or with other FORTH words When FORTH words are executed individually operation 1 similar to other interpretive languages such as BASIC When many words are combined and executed as
17. correctly set this parameter without re visiting the site at least once For example 1f an experiment were of 10 days duration and 2 M byte RAM cassette were used with waveform storage even a liberal threshold would probably not fill the mass storage as an event every 20 minutes or less would be needed before the storage overflowed On the other extreme an experiment of one year would definately need to reject the smallest events or the mass storage would overflow before the year elapsed With a variable ENTH the enerqy threshold used by EVT this parameter can be automatically increased or decreased depending on the rate at which events are recorded Each time the ELOG triggers the time difference between the last time an event was recorded and the time of the present trigger is compared to a desired event recording interval expressed in minutes If this time difference 1s longer than desired then the threshold is increased and visa versa This feedback mechanism tends over the long term to force recording at the desired rate so that the mass storage will fill up but not over fil during the experiment The words used to implement the above scheme are given below It s noted that the two undesireable sftuations which need to be corrected are ENTH is too high allowing an event recording rate higher than desired b ENTH 1 too low rejecting so many events that the recording rate 1s too low In the first case ERATE will decrea
18. entered 2 2 Verification of Events Because memory is a limited resource the verification words attempt to prevent recording events that are not earthquakes Before any tests are made however the word RDTM screen 2 reads the clock and stores the time in memory for later recording if the event is deemed real Then the word TAIL collects another nine seconds of post event data 1n the data buffer TAIL screen 22 uses a similar sampling loop to the one described above with two differences the LTA and STA are not updated and the 1805 counter is re initial zed by AOPG to large value to limit sampling to the 100 Hz rate Now that the above two time critical tasks are done verification starts First the energy of the wave is checked by AMPL AMPL counts the number of times that the STA is Jess than two times the LTA Then FREQ counts the number of zero crossings and SRCH finds the onset time SRCH searches back n time for the point where the STA falls to two or less times the LTA Refer to screen 21 23 Th s point will tend to be early as the STA 1s an average and not immediately follow the data To compensate for this the search is done aga n using a shorter averaging time FAVG and going forward in time to find the start of the event Thus SRCH first looks back in time through the buffer for the approximate onset which tends to be early and then forward in time for the true onset sample This procedure prevents noise spikes
19. on the enable lines high level is produced by the word RDTM which sequentially reads two nibbles of data into the port starting at 1 1005 seconds The sequential reading is implemented by decoding the output bytes produced by ROTM with two 4028 decima decoders The decoders are also used to control the RAMcassette by inputting different control bytes to the decoders 995 A BUSS laa TOCE JE 4T SIGH LAO PUEY MOA FOGE 12042901 PON CORECT Pied TO SY HIGHEST HUHBERS THIS SHEET AAA Il i ALS JE H Ci E4K trf TUE mr Ki sr GLK 4358 hik Ala i ti tk Blo 710 120 16 FIGURE AMPLIFIER oun 4 x ee A u 5 Geo apical Sar g E v M5 Ed Fark UE 24825 wo 506 INTERFACE FRGL SECE 1 RR Et DGHMP 1 OF 2 n NUN 14 21 _ REY 00 5 7 2 1 ST s y EB 5 5 34 HERE B 55 s U YI E Eid 15222 E FERRE zm at paanga pul 25 T X Aa 16 n ELOG INTERFACE DIGETRL SEC CN Y
20. the various components follows 3 1 CPU Card The CPU card uses a CMOS 8 bit CDP1805CE microprocessor running from a 2MHz crystal Instructions need an average of 16 clock cycles for execution resulting in a processing rate of 125 000 instructions per second The card also has serial RS232 port which is used for terminal communication at up to 1200 baud while a paralle programmable port is provided for byte input output The port 15 programmed v a software instructions which determine whether the sect ons are to be used for input output or bi d rectional data flow The ELOG only uses the first two options The card memory section has four 27C16 EPROMs which contain the FORTH compiler and initial dictionary as well as four kilobytes of RAM The external interrupt and polling features are not used wiring diagram of the RS232 cable is given in Appendix 5 3 2 0 Converter The A D converter card converts bipolar analog data to offset binary 8 bit samples The RCA scheme for addressing 1 0 modules necessitates having each module respond to a group select code The code recognized by the 0 during an OUTPUT 1 instruction 15 which 1 put on the bus as data After selection the A D must be programmed for fixed digitizing from channel 0 the input channel This is similar to the group select described above except that 1 used for data and two other output instructions are used for the programming After al these preli
21. 96 RO DIV D RF2QUOT RD REM R1 SGNCTR 2 SEX Q LDI 1 PLO IRX CLR SGNCTR RLXA GHI SHL LD DIV D SGN gt DF 3B C 15 BNF POS ADDR 1 INC GLO FF XRI O PLO GHI FF PHI INC 2 S CML LD SGN GHI 5 POS ADDR SHR SHR SHR SHR PLO O LDI PHI GLO D PLO O GHI 3 D PHI 1 GLO RO REM LD SGN CTR 22 C 29 C B2 END ADDR GLO FF XRI F PLO F GHI FF XRI PHI F INC 2 S COMFL GLO FF XRI D PLO D GHI FF XRI PHI D INC 275 COMPL DEC END ADDR KSXD RSXD 9 SEP END CDDE ON CO RT CODE N DIVIDE BY 16 NIBBLE 2 SEX O LDI 1 PLO IRX Q RLXA O BHI SHL C 59 BNF POS ADDR 1 INC O GLO FF XRI PLO O GHI FF XRI O PHI O INC GHI POS ADDR SHR F PHI Q GLO SHRC PLO GHI SHR PHI GLO SHRC PLO GHI SHR PHI F GLO SHRC PLO GHI SHR F PHI F GLO SHRC F PLO LDI D PHI O GLO F ANI D PLO GLO 32 80 BZ END ADDR F GLO FF XRI F PLO F GHI FF XRI F PHI F INC gt O Tl f T SCRE gt D XRI D PLO D GHI FF 1 D PHI D INC 2 2 DEC END ADDR x D RSXD F RSXD 4 9 SEP END CODE 5 CODE NUM ABSNUM HEX 6 PAGEJUMP 2 SEX IRX RLXA 7 O GHI BO ANI 32 C 12 C 9 GHI FF XRI O PHI 10 O GLO FF PLO 11 0 INC 2 DEC RSXD 12 9 END COUDE 15 CODE 5 NUM PROD POS BYTE 15 2 BEI ORRDCRXSINR SHBERDC STXD 16 END CODE 17 5 18 SCR 10 Q CODE Y
22. EM QUOT HEX PAGEJUMP t DIV STK NUM BY 4096 ROmDIV D RF QUOT RD REM RizSGNCTR 2 SEX O LDI 1 PLO IRX CLR SGNCTR O GHI SHL LD DIV D SGN DF C 15 C BNF POS ADDR 1 INC O GLO FF O PLO O GHI FF XRI O INC Z S8 CML LD SGN O GHI POS ADDR SHR SHR SHR PLO Q LDI FHI GLO D PLO GHI ANI D PHI t GLO ROsREM LD SGN CTR 52 29 t BZ END ADDR GLO FF XRI F PLO F GHI FF XRI PHI F INC 276 COMPL GLO FF XRI D PLO D GHI FF XRI PHI D INC 2 8 COMPL DEC l END ADDR RSXD RSXD 9 SEP END CODE 4 CODE N DIVIDE BY 15 NIBBLE SEX O LDI 1 PLO IRX O RLXA GHI SHL SB C 59 BNF POS ADDR 1 INC O GLO FF XRI Q PLO Q GHI FF XRI PHI O GHI POS ADDR PHI GLO 8 FLO GHI SHR F GLO SHRC PLO GHI SHR F PHI GLO SHRC PLO F GHI SHR F FHI F GLO SHRC F PLO O 1 CJJ OD O T T LDI D PHI Q GLO F ANI D PLO 52 BD C BZ END ADDR GLO FF XRI F PLO F GHI FF F PHI F INC SCR 5 c0 4 QN O jn ON O L K D GLO FF XRI D PLO D GHI FF XRI D PHI D INC 2 DEC END ADDR D RSXD F RSXD 9 SEP END CODE CODE ABV NUM ABSNUM PAGEJUMP 2 SEX IRX O RLXA GHI 80 ANI 52 C 12 C BH1 FF XRI O PHI GLO FF XRI O PLO INC 2 DEC O RSXD 9 SEP END CDDE CODE 3 NU
23. EMOMIC 8 PLO B DEC B GLO BNZ addr 3 INP 0 INC LDI STR 2 SEX CID RET 26 APPENDIX 2 INTERRUPT HANDLER COMMENT T M R2 0 gt operand 82 R 0 0 operand 46 gt R 0 1 operand D M RLO M 4682 30 30 output R 1 24683 sel A D operand D 5M R0 M 4683 0 0 output R 1 468Amfuxed ch operand D M R 0 M 4684 40 0 output R 1 24686 sel ch 0 COMMENT operand 9 5R B 0 8 1 8 R B 0 5D short branch to addr branch back to addr M 4685 A D sample byte R 0 34686 operand D gt M R Q 4686 1 semaphore 2 gt disable counter interrupt return to main program Appendix 3 Cassette Software SCR 0 2 ELOG EARTHQUAKE RECORDER VERSION 2 14 86 VERSION RAMCASSETTE HIGHEST SCR 26 4 EXECUTION ADDR 2 5 6 7 B 9 10 11 12 15 14 15 16 17 18 SCR 1 2000 DF TM BYTES 4856 58 1 CODE RDTM 2 36 LDI O PLO 4R LDI O FHI B LDI STR Q SEX 1 OUT DEC 4 SELECT 1 0 PORT 5 RB LDI Q STR 2 OUT 0 DEC A INP 6 32 LDI O STR 2 OUT O DEC RzOUT 7 9 LDI Q STR 2 DUT DEC 1 LDI O STR 2 OUT DEC 9 READ TIME BYTES 10 5 LDI O STR OUT O DEC 4 INF O INC 11 4 LDI STR 6 OUT DEC 4 INF INC 12 5 LDI STR OUT DEC 4 INP INC 15 2 LDI STR OUT Q DEC 4 INF Q INC 14 1 O STR 6 GUT O DEC 4 INP
24. INCF ADDR FAST INC 1 PAGEJUMP 2 2 SEX IRX LDXA 1 PHI LDX 1 PLO 5 1 SEX LDXA O FHI LDX PLO INC Q INC O GLO 5 40 SDI O GHI 9 SDBI 6 33 C 1B C 7 O LDI STXD STXD 8 30 C iF C 9 0 GLO STXD GHI STXD 10 2 SEX 9 SEP 11 END CODE 12 gt 13 14 15 16 17 18 5 11 VARIABLES CONSTS HEX i VARIABLE RSTA REMAINDER FOR STA 2 VARIABLE RLTA REMAINDER FOR LTA 3 VARIABLE PCTR TRIG ONSET DISP 4 VARIABLE IMAX MAX SAMPLE 15ST VARIABLE IMGT SAMPLE AT ONSET amp VARIABLE TMXS SAMPLES 1ST O 7 VARIABLE OPTR PTR FOR ASCII CHAR 8 VARIABLE TPTR PTR TO HEX TIME 9 VARIABLE IPTR PTR TO INTR HAND 10 VARIABLE YNEW NEW SAMPLE 11 VARIABLE YOLD PREVIOUS SAMPLE 12 VARIABLE YCTR BUFFER INDEX 15 VARIABLE STA SHORT TERM AVG 14 VARIABLE LTA LONG TERM AVG 15 VARIABLE TSTA TMP LOC FOR STA 16 VARIABLE TRSTA TMP LOC FOR RSTA 17 VARIABLE ECTR TRIGS 18 gt 30 SCR 12 VARIABLES VARIABLE NSLT SAMPL lt 3 LTA VARIABLE NZRO O X IN 5 SEC VARIABLE TEMP LOC LTA VARIABLE TYCTR TEMP LOC YCTR 6000 CONSTANT ROT START 64 CONSTANT SPS SAMPLE RATE 9 CONSTANT WIND TEST WINDOW SEC 2 CONSTANT LTRG ONSET THRESHOLD 960 CONSTANT NBUF HEX BUFFER SIZED 10 11 12 15 14 15 16 17 SCR 12 ELOG WORDS HEX FAVG YNEW 2 ABS STA 9 4 MOD STA RSTA RSTA 2 4 MOD STA 1 STA 2 MAX STA
25. M PROD POS BYTE 2 SEX IRX IRX LDX SHL ADC STXD Q LDI O ADCI STXD 9 SEP END CODE gt 37 ADDR FAST INC REMAINDER FOR STA REMAINDER FOR LTA TRIG ONSET DISP MAX SAMPLE iST SAMPLE AT ONSET SAMPLES TO 1ST 0 PTR FOR ASCII CHAR PTR TO HEX TIME PTR TO INTR HAND NEW SAMPLE PREVIOUS SAMPLE BUFFER INDEX STA SHORT TERM AYG LONG TERM AVG TSTA TMP LOC FOR STA CODE YINCF 1 2 2 SEX IRX LDXA 1 PHI LDX 1 PLO 5 1 SEX LDXA PHI LDX PLO INC INC O GLO 50 SDI O GHI 9 SDBI 6 33 1B C 7 OLDI STXD STXD B SO iF C 9 GLO STXD GHI STXD 10 2 SEX 9 SEF 11 END CODE 12 13 14 15 16 17 18 SCR 7 VARIABLES CONSTS 1 VARIABLE RSTA 2 VARIABLE RLTA VARIABLE PCTR 4 VARIABLE 5 VARIABLE IMOT VARIABLE TMXS 7 VARIABLE OPTR B VARIABLE TPTR 9 VARIABLE IPTR 10 VARIABLE YNEW 11 VARIABLE YOLD 12 VARIABLE 13 VARIABLE 14 VARIABLE LTA 15 VARIABLE 14 VARIABLE TRSTA TMP LOC FOR RSTA VARIABLE h SCR 8 a m OUP Ne Oo VARIABLES VARTABLE ECTR TRIGS NSLT SAMPL lt S LTA VARIABLE NZRO 4 IN 5 SEC VARIABLE TLTA TEMP LOC LTR VARIABLE TYCTR TEMP LOC YCTR 6000 CONSTANT BOT BUF START ADDR 64 CONSTANT SPS SAMPLE RATE 9 CONSTANT WIND TEST WINDOW SEC 2 CONSTANT
26. N RDY NRDY gt LTA 9 MAX LTA FEVT UNTIL 3 9 10 11 12 15 14 15 16 17 43 WIRE LIST FOR CLOCK INTERFACE MODIFICATION Component and Pia numbers as marked on back of PCB 0 ao 12 13 14 15 16 17 18 19 21 22 23 24 21 3 1 21 2 6 21 25 21 2 4 21 2 13 21 2 14 21 2 15 21 2 1 21 16 21 1 6 21 144 21 1912 21 14614 21 1018 21 1000 1 510 200 1 510 2 14 510 2011 3 510 2 6 590 1 2 e 510 1 11 510 1 6 Bat 26 OUTPUT CONNECTOR 21 315 27 21 3 14 28 29 30 21 5 13 21 3 4 21 865 31 32 33 55 56 37 38 39 40 41 24 4C1 24 4 13 24 4 14 24 4 4 24 465 24 4 6 24 4C1 21 301 21 5 15 21 5 14 Appendix 5A Wiring List for Parallel Time Cable i 44 Male cennector pins Orient w Batt oennections 45 BLU LLLI AMP 8205 Appendix 5B ELOG RS232 CABLE 46 Appendix 6 Automatic Threshold Adjusting Field experience has shown that the energy threshold ENTH see below is the most critical of the three parameters used to reject uninteresting events Since the optimun setting for this parameter depends on local noise sources the memory size available and the duration of the experiment 1 16 difficult to
27. O DEC i BOUT 1 6 LDI O STR amp OUT 0 DEC MEM RD 14 9 SEP END CODE 15 gt 16 17 18 SCRA 5 CODE DEFINITIDNS 1 CODE ENB ENABLE MEM BANK SEL TOR 2 54 LDI PLO 4B LDI 8 LDI 5 0 STR Q SEX 1 OUT 0 DEC SEL PORT 4 53 LDI O STR 2 OUT DEC BOUT 5 96 LDI STR 6 OUT O DEC ENB DECR amp 9 SEP END CODE 7 CODE DISB DISABLE MEM BANK SEL B 54 LDI O PLO LDI 8 LDI 9 STR O SEX OUT DEC SEL PORT 10 53 LDI O STR 2 OUT O DEC i R QUT 11 97 LDI STR 6 OUT O DEC DECR 12 9 SEP END CODE 13 CODE BBFPTR INIT BUF ADDR PTR 14 34 LDI 1 PLO 48 LDI 1 PHI 15 9 SEP END CODE 16 CODE SELPTR PTR TO MEM BYTE 17 36 LDI 1 PLO 4B LDI 1 PHI 9 SEP 18 END CODE gt 28 29 SCRE 5 O DEFINITIONS HEX 1 CODE E gt R WR FROM ELOG TO RAM 2 34 LDI O PLO AB LDI O PHI 8 LDI 5 STR O SEX 1 OUT DEC SEL PORT 4 AB LDI STR 2 OUT O DEC AsQUT 53 LDI O STR 2 OUT DEC BOUT 6 1 RNX 1 INC LOAD IN RO 7 SEX 4 OUT WRITE BYTE 9 SEP END CODE 9 CODE gt WR FROM TO ELOG 10 11 12 is 14 is 16 17 18 34 LDI O PLO LDI O PHI 8 LDI O STR O SEX 1 OUT O DEC SEL PORT B LDI O STR 2 GUT O DEC A IN 55 LDI STR 2 OUT O DEC 00 1 RNX LD PTR TO RO SEX 4 INP READ BYTE 9 SEP END CODE gt SCR 7 0 x R 5 G CODE NUM REM QUOT HEX PAGEJUMP DIV STK NUM RY 40
28. OT 4 Onset Sample Value The value of the data point at the onset time This also gives the polarity of the first motion 5 2 Maximum Sample The absolute value of the largest amplitude during the first half cycle 6 TMXS 2 Time Until First Zero Crossing The number of samples to the first change of polarity measured from the onset time 7 N3LT 4 Energy Level The number of times during the first nine seconds of the event that the STA drop below twice the LTA This provides information on the energy duration of the event B LTA 2 The LTA value before the event This gives a measure of the background noise y 7 9 ECTR 4 Number of triggers 10 NZRO 4 Number of zero crossing during the first 9 seconds of event The other sections of this report will examine the hardware and software in more detail 11 references to screen numbers refer to the RAM cassette version of the FORTH program Appendix 3 Screen numbers are FORTH s way of dividing up a program into smaller units The other program versions are Cassette Tape Appendix 4 and RAM cassette with waveform storage which is currently under development The basic elements of all three programs are very similar 2 PROGRAM ORGANIZATION The ELOG program is organized into three conceptual parts only one of which will be executing at any given time The central routine is the sampl ng loop screen 25 which digitizes incoming data and places the values in
29. TA 8 LTA EVT UNTIL j SCR 27 Q 35 18 L3 Appendix 4 Cassette Tape Software ELOG EARTHQUAKE RECORDER VERSION DATE 3 14 86 2 VERSION TYPE CASSETTE TAPE 5 HIGHEST SCRW 21 4 EXECUTION ADDR 2886 SCR 1 2000 DP TM BYTES 48565 58 1 CODE RDTM 2 36 LDI O PLO 4B LDI O PHI x B LDI STR O SEX 1 OUT DEC 4 SELECT 1 0 PORT STR 2 OUT O DEC A INP 53 LDI O STR 2 OUT O DEC B DUT 7 9 LDI 0 STR 2 OUT DEC INTBsO 8 1 LDI STR 2 OUT O DEC INTA O 9 READ TIME BYTES 10 5 LDI STR amp QUT O DEC 4 INP INC 11 4 LDI O STR 6 OUT O DEC INP INC 12 X LDI O STR amp QUT O DEC 4 INP O INC 12 2 LDI O STR OUT DEC 4 INP O INC 14 1 LDI 0 STR amp OUT O DEC 4 INP O INC 15 O LDI O STR amp GUT Q DEC 4 INP INC 16 9 SEP END CODE 17 gt 18 SCRH 2 CODE DEFINITIONS HEX 1 CODE ADPG PGRM 1805 CT 2 XID CID STPC 49 101 LDC STM 9 SEP END CODE 4 CODE MIE SET MIE ALLOW INTR RET 9 SEP 6 END CODE 7 CODE ENB 1805 CTR INTR 8 CIE 9 SEP 9 END CODE 10 CODE CTDS DISENB 1805 CTR INTR 11 CID 9 SEP 2 END CODE 13 CODE IADR INTR HANDLER ADDR 14 B8 LDI 1 PLO 46 LDI 1 PHI 9 SEF 15 END CODE 16 CODE DATA 17 46 LDI O PHI 86 LDI O PLO O LDI 18 STR 9 SEP END CODE 2 36 2 OC ig s CODE NUM R
30. This port like the A D must first be selected and programmed for the desired configuration For example when 1 is desired to write a byte to the RAMcassette one port fnternal to the 1851 must be set up as output port These words are located in screens 3 6 For either recording medium the parameters stored are the same First the clock time which fs available fn parallel format is converted to byte seria by the word ROTM Each execution of RDTM initializes the 1851 as half input and half output The output half sends control bytes to the time buffering electronics to contro the order of reading through the input half of the port Then the word WRTM moves the time bytes to the parameter buffer if the screening tests described above are passed compete memory map which shows the location of all ELOG memory areas 1s given Figure 2 The word FRST uses the onset time found by SRCH the verification phase to find the direction of first motion IMOT and the maximum value sample during the first half cycle of the event IMAX SRCH also counts the number of sample points from the trigger time to the nstant when the STA is two times the LTA This value is stored in the variable PCTR PCTR 1 used as an index to the circular buffer for the onset instant and is written to the parameter buffer by the word WRVR WRBY writes the bytes and IMAX to the buffer FRST then counts the number of samples to the first zero crossing from the o
31. cCabe C Forth Fundamentals 1983 Dilithium Press User Manual for the RCA COSMAC Microprocesor Development System RCA Solid State Div Somerville New Jersey 1981 Using the 0 1851 Programmable 1 0 RCA Solid State Div Somerville New Jersey 1982 Omegarec Omegaface Observatiore Cantonal Neuchatel Switzerland Maximum Input mV Current Drain mA Supply Voltage Yolts Operating Temperature Mass Storage Capacity Mass Storage Current Drains Mass Storage Supply Voltage A D Resolution Sampling Rate SPS Size with water tight box Amplifier Ga nt Amplifier Noise at input Dynamic Range Desired LTA Yalue Cost 1984 Appendix 1 Specifications ELOG RAMcassette 7 27 2 GAIN 90 7 5 14 20 C 50 C 128 K bytes prototype lt 1 ma Sv from ELOG 8 bits up to 100 12 x 12 x 22 340 44 000 luY or less 48dB 5 9 counts 2500 1 2M byte RAM cassette has been designed 25 ELOG Cassette Tape 7 27 2 GAIN 120 7 5 14 0 50 80K bytes 30 ma 6 7 5 v ext battery 8 bits up to 100 12 x 9 x 22 340 44 000 or less 484 5 9 counts 2000 Gain 1s set digitally by amplifier switch with lowest value O and highest 7 4698 4698 469 ADDR 4690 469 46A0 46A1 45A2 46A3 46 4 46 5 46A6 46A7 46A8 46A9 46 46 SEX LDI 0 PLO LDI PHI LDI STR 1 OUT LDI STR 6 OUT LDI STR 5 OUT LDI M
32. conceptual izations In addition Chris Stephens was heavily involved in the first array deployment in 1985 I wish also to thank Bob Page for his many important suggestions and insights i a 1 INTRODUCTION Many remote areas of the world are of great interest to 5 5 for example Alaska within the United States The acquisition of seismic data in these areas poses a difficult problem The challenge has been met at least to some extent through the use of low power VHF radios with multiple line of sight links to telemeter seismic data over long distances to the nearest town or communications facility In rugged and remote terrain this has usually meant compromise in choosing sites as well as high cost The Geological Survey embarked in 1984 on a project to develop a low cost smart seismic station which could be used without VHF rad o telemetry The system had to be small rugged low power and be able to record earthquake data on site with accurate internal timing an interval of at least 1 year The system should also permit its data to be relayed via satellite when channels of sufficient baud rate become available The initial primary use for this instrument an earthquake data logger or ELOG is to study special regions out of range of the present VHF links set up in Alaska Extending the current VHF radfo links is not possible due to the high equipment costs tnvolved in the Tinks as well as leasi
33. d and type The ELOG will respond first with an and then after P is typed with the welcome message Then type HEX EXECUTE where 15 hexidecimal address given in Appendix 3 or 4 If cassette tape is being used for storage depress the rewind button on the tape recorder When the tape 15 rewound press any key and push down the orange record button If the RAM cassette 1 being used ignore the rewind commands and depress any key 9 Verify that the gain setting 1 correct by tapping the ground severa times in quick succession to cause an event to be recorded You will also hear the terminal beep This should be done at least twice after remaining still for about 2 minutes If the LTA value sent to the termina js not in the range of 4 8 adjust the gain switch accordingly 10 Note the time on the clock gain setting value and clock status The system is now running 6 2 On gt p 24 REFERENCES Microboard Development Systems RCA Solid State Div Somerville New Jersey 1982 User Manual for the CDP1802 COSMAC Micraprocesor RCA Solid State Div Somerville New Jersey 1976 Microprocessors Memories Peripherials Solid State Div Somerville New Jersey 1982 MB4TH RCA Solid State Div Somerville New Jersey 1983 Brody L Starting Forth 1981 Prentice Hall Loelinger X Threaded Interpretive Languages M
34. dio pulses 15 cancelled by the advance in the clock so that the clock runs within 20msec of rea time If the receiver is unable to decode the incoming code the pulse output s duty cycle is changed thereby informing the clock of a possible timing error In this case the receiver osc llutor then free runs on its own oscillator and the clock status bit 15 set to 1 0 m T T h _ 18 am gt ug gt S ok 43 3 a L 222 5 51 RI os 2 Y x 52 42 E aris 3 Eus oem 534 oes FIGURE 4A RAMCASSETTE CONTROL K ERS POUND IK CIRCUIT U S Geolagical Survey O E V E Cure Cl EACH YCC 1 9 5 TO SV IF IWS 76 14 at SP I THe Sra NOTES 345 Middlefield Ad Perk QuE S HRE 52 sec 2550828 2 85886 4H a P SOR ber sss p a a 19 ELOG 59 FIGURE 49 RIM ARRAY 20 4 0 OPERATIONS Conducting any successful field experiment involves the correct execution of many seemingly trivial tasks Details for an ELOG deployment include selection of batteries and Omega radio receivers the s
35. etting of the clock burying the sensor and starting the ELOG program The information below 1 intended to provide a guide for the deployment of an array of ELOGs A wiring diagram is given Figure 5 and the specifications Appendix 1 4 1 Battery Considerations Although there are many different types of batteries available the 6 volt rechargeable lead acid or the 2 5 volt non rechargeable alkaline gelled electrolyte battery probably are the most cost effective choices for the ELOG power source Lead acid batteries are more suitable for deployments of several weeks while alkaline batteries can run an ELOG for one year but cannot be reused The battery capac ty needed to run an experiment depends on the length of the experiment and the temperature Capacity 1 rated in ampere hours or the number of hours of battery life at one ampere Since the ELOG dr ws less than 0 1 ampere the expected battery life 1 ten times the amp hr rating expressed in hours Of this only 80 percent should be used and this number must be further reduced if operation below freezing 15 needed The manufacturer s data sheet will contain the information needed to make economical choice 4 2 Setting the Clock Accurate and reliable timing depends on a high signal to noise ratio of the Omega Radio signal Thus the nearest Omega transmitter should be selected as the frequency of the Omega radio receiver The antenna needs to be placed horizontally atop a po
36. imum of 512k bytes to M bytes For either recording configuration the ELOG will run for an entire year on four 1000 ampere hr batteries During this time the program monitors incoming data for what might be an event Parameters for events that pass a screening to eliminate low frequency arrivals and no se bursts are Collected in mass storage The heart of the program is a sampling loop which continually updates a long term average LTA and a short term average STA of the data Each time through the loop these averages are compared to see if the STA exceeds the LTA by a factor of three If so the 12 second event buffer starting when the STA is exceeded and lasting 9 seconds 15 tested for frequency content energy and event impulsiveness If the tests are passed the event parameters are written to a temporary buffer which holds 19 events After the 19th event the buffer is written out to mass storage The stored data detailed below with the number of hexidecimal characters in the output in parenthesis 1 Clock Status 1 indicates whether the clock is properly synchronized to Omega 2 Detection T me 11 The instant when the STA reaches or exceeds the LTA by a factor of three expressed n terms of Julian day hour m nute second and hundredth of a second 3 PCTR 2 Onset Time The instant before detection time when the STA reaches or exceeds twice the LTA expressed as the number of samples prior to the detection time 4 IM
37. just prior to the onset from being picked Table 1 gives the parameters used the search process as wel as other ELOG parameters When SRCH finishes executing t produces vartable value which is a measure of the impulsiveness of the event for the final recording phase of the program to be entered the variables values produced by AMPL FREQ and SRCH must be within the bounds given in Table 1 Thus an event must maintain certain energy Jevel have at least a minimum number of zero crossings and not be too emergent Parameters for events that pass these tests are recorded 2 3 Event Recording Each time an event passes the three tests ft 1s recorded in the parameter buffer The parameter buffer holds 19 events which are written to mass storage as a group Mass storage is either low cost cassette tape recorder solid state memory array The cassette tape control software uses features built nto SAVE BUFFERS causes the entire parameter buffer contents to be written to tape The variable USE which contains the number of the next buffer to be used 1 incremented and an update bit in the buffer is set With the RAMcassette a memory location counter jis used to address the memory array and CTRL increment the counter ENB and DISB activate and deactivate the RAMs MEMRD and MEMWR select the read or write mode and E gt R and R E do the reading or writing through the COP1851CE programmable 1 0 port 9
38. le so that a line drawn from the Omega transmitter to the site makes a right angle with the long axis of the antenna A button on the receiver activates the LED so the incoming code pattern can be monitored Irregular fiashing means the antenna is incorrectly oriented When properly oriented the code consists of two pairs of pulses repeated every ten seconds Since the code does not distinguish between ten second intervals the user must provide the minute pulse by releasing the radio reset switch after the new minute Thus a watch having an accuracy of 5 seconds or a WHY radio receiver is needed The reset button 1 released at the end of the first long pause of the receiver LED after the minute The receiver wil then automatically synchronize its output to Omega after this If the button is released more than five seconds after before the start of the long pause the clock will run an integral mult ple of ten seconds from real t me The clock must now be set starting with minutes and working up to the Julian day The receiver automatically takes care of the seconds so no seconds switch is provided The delay mentioned in section 3 7 must also be set This delay is the sum of three components the receiver delay propagation delay and atomic time offset from GMT Table 3 contains pertinent information on the Omega transmitters which can be used to compute the proper settings on the clock For example in Anchorage Alaska the path length fro
39. lected by the 30H code Then two OOH codes are output next to program the single channel mode and data channel zero These two steps configure the 0 to digitize only on channel zero the e ght channe A D Sampling is started as soon as the interrupt handler address 15 loaded IADR and the counter interrupt is enabled CTEN semaphore RDY is used to halt sampling Joop execution until the next sample is ready The interrupt handler cade is presented in Appendix 1 while Screens 2 and 15 contain the above words Once the new sample is stored memory the word NXT converts the 8 bit offset binary code produced by the A D to a 2 s complement 16 bit code and stores the value in the variable YNEW This value 15 placed in the circular buffer by the word PUTY Then the STA and LTA are updated by the words SAVG and LAVG respectively In order to increase processing speed SAVG and LAYG use divisions and absolute value operators written as assembly language FORTH code words Since FORTH does not support floating po nt math the code word divisions also put the remainder on the stack Use of the remainder by SAVG and LAVG gives a more continuous LTA and STA Finally after the LTA and STA have been updated their values are compared the word 7EVT checks each time around the loop to see if the STA is three or more time the LTA If this occurs then the main sampling loop is temporarily exited and the verify section of the program is
40. m the Hawaii transmitter is 4500km Multiplying this number 3 3 x 10 6 yields 15ms propagation delay which 1 added to 4 815 for a total delay of about 4 83ms Note that the leap seconds often added at the end of June or December cause 21 a NOILISNNOIYSINI 9013 S 390913 170139 941904231 gel OU DIGH 5100 03133 NJOJ yid 25259 onaf 0209018 aasia 985 1 1 0 W Da EM UNS JS 1311 976 35 Tw NIM 3238 530 TABLE 3 OMEGA TRANSMITTER DATA Station Norway Liberia Hawa 11 North Dakota La Reunion Argentina Australia Japan 22 Offset Receiver Delay 1 85 2 11 3 51 4 81 5 91 7 31 8 51 9 61 0 81 sec sec sec Sec Sec sec sec Sec 23 GMT to advance with respect to Atomic time by one second per year Consult the manufacturer s operation manual 10 for more detailed information It should also be noted that all Omega transmitters shut down for periodic maintenance The Hawaii transmitter for example is maintained in June The exact dates can be ascertained by calling the Kawaii Omega Transmitter 808 235 498 Once the delay is set via the three BCD switches on the clock front panel the clock will approach real time at the rate of 3msec per minute Thus if the initial setting were off by 3 seconds it
41. minaries the A D is ready to digitize its first sample INPUT 3 instruction initiates the conversion The code in machine language which handles the A D semaphore discussed in Sec 2 1 and 1805 counter interrupt disabling is loaded by the word ILD screen 19 and fs executed once for each sample The A D produces offset binary code which differs from 2 s complement by the most significant bit For 8 bit numbers if 80H 15 subtracted from the offset binary number 2 s complement number results Th s number covers the range of input voltages from 2 5 volts An expression which relates input voltage to counts fs WAVEFORM 1 2 12 13 14 15 18 19 20 21 22 23 26 27 28 29 32 33 36 37 40 41 44 Note NO WAVEFORM 1 2 12 13 14 15 18 19 20 21 22 23 26 27 28 29 32 33 36 13 TABLE 2 ELOG DATA FORMAT DATA DESCRIPTION clock status 0 0 BCD time julian day hr m n sec 1 10 1 100 sec PCTR sample time offset from tr gger to onset IMOT polarity sample value at onset IMAX maximum sample during first half cycle TMXS sample times from onset to first zero crossing N3LT number of t mes STA falls below twice LTA long term average ECTR number of triggers NZRO number of zero crossing during wind ENTH energy threshold index to trigger point in buffer If waveform storage s selected then an additional 1200 bytes of waveform data follows
42. ng the connecting commercial phone circuits A possible secondary use of the ELOG 15 for rapid deployment jn an aftershock investigation Because on site recording capacity is timited entire earthquake events cannot usually be recorded Instead the arrival time and certain key parameters are saved An additional event buffer containing three seconds of pre and nine seconds of post event data can also be saved if the investigation s duration is only several weeks or less Depending on the level of seismicity channel capacity and needed bandwidth for the data the information could also be relayed by satellite The ELOG hardware is based on the commercially available RCA Microboard series of microcomputer products 1 The CPU board handles all digftal signal processing with a memory expansion board holding part of the program Another RCA board handles tape 1 0 and a USGS designed board provides parallel to byte serial time conversion for the 8 bit data bus as well as all analog signal conditioning 8 bit analog to digital A D converter board digit zes the s ngle channel of incoming data Communication with the ELOG is via RS232 port on the CPU board In the field portable terminal is used for ELOG setup The ELOG system block diagram is shown in Figure 1 The RCA microcomputer board is based on the CDPI805CE microprocessor 2 3 which has been set up to run FORTH 4 high level computer lanquage Although similar in some re
43. nset and stores the value in TMXS which 1s also written to the buffer Then the number of times the STA falls below twice the LTA during the event N3LT If this level varies with the rate at which events are recorded an automatic energy threshold adjustment can be achieved This allows a recording rate which wil just fill the available mass storage without having to re visit the site to adjust this parameter The FORTH words that implement this function are given in Appendix 6 TABLE 1 ELOG SETUP PARAMETERS SPS Sampling Rate Samples Per Second Energy Test lt WIND window on event after trigger Zero Crossing Test NZRO gt BOT lowest address of data buffer LTRG onset threshold NBUF buffer length Emergence Test sample times Trigger threshold LTA averaging time LAVG STA averaging time SAVG FAYG fast averaging time 10 100 300 95 45 6000H 2 2400 bytes 100 1 sec 3 4096 16 11 LOW MEMORY HIGH MEMORY FFFF VRVEFORM EXPANSION NOT USED FORTH RSSEMBLER FORTH EDITOR 7FFF 6968 ELOG WAVEFORM SUFFER NOT USED 5808 TERMINAL INPUT BUFFER 4F1F TERMINAL OUTPUT BUFFER 4EBE PARAMETER STACK MESE NOT USED CLOCK TIME 4835 FRATCH 4834 SCRRTCH ti 482 NOT USED TAPE SCREEN NUMBER TRPE UPDATE FLAG USED ___ ___ NOT USED SEMAPHORE SAMPLE ELOG FORTH WORDS 4835
44. oves the inhibit level from the decoder The read or write mode is selected by the words MEMRD and MEMWR 1 these signals first go through flip flops before they are applied to any other circuit Playback of the RAMcassette data is handled by the word RDRECS which takes the number of records desired to be read off the stack The data is outputted through the RS232 port where t can be transferred to floppy disk by a suitable terminal program running on a portable personal computer 3 7 REAL TIME CLOCK Real time is supplied to the ELOG through the interface card by an ek Radio synchronized clock Omega is a world wide low frequency precisely timed radio signal whose six transmitters put out a repetitious code Decoding is done by the Omega Radio receiver which is tuned to the characteristic frequency of the nearest Omega transmitter The code is used to synchonize an oscillator ns de the receiver so that the minute pulse output of the radio 15 always within 20msec of its theoretical value This theoretical value is calculated by adding the offset between Omega which uses Atomic Time the propagat on delay due to path length between the transmitter and receiver and the internal receiver delay The delayed pulse output of the radio receiver is input to a clock whose time runs ahead of the radio pulses the fixed amount calculated above This offset advance is programmed by three BCD switches Once set correctly the delay the ra
45. ronics except for the clock and radio which have their own internal batteries The regulator 1 capable of supplying one ampere of which 500mA is avallable for external use Another voltage converter ICL7660 produces negative 5 volts for use by the signal conditioning section 3 52 Signal Conditioning and Amplification Signal conditioning consists of amplification to match the dynamic range of the A D converter and filtering to prevent signal aliasing The input signa from the 4 vertical geophone is applied to low noise differential amplifier composed of a matched pair of transistors The input impedance produces a critical damping factor of 0 7 with the gain fixed at 21 5 A potentiometer allows zeroing out of any offset In the circuit shown in Figure 3 a cutoff frequency of 30Hz rasults This cutoff s mainly influenced by the filtering action of C8 R10 and C7 R6 Amplifier 021 gives solid state switchable gain control from a minimum of 340 to 44 000 ncrements of 6dB The maximum allowable signal coming out of the amplifier is limited to 2 5 V by the A D 3 53 Time Buffering The internal batteries of the clock are 3 6 volt Lithium so clock logic levels need to be converted to 5 volt CMOS This is accomplished by an array of RCA 40109 CMOS CMOS level converters with three state outputs Each CD40109 converts 4 bits of clock data which is input to the CDP1851CE 1 0 port when the CD40109 output drivers are activated by high
46. se by 1 count In the second case LASTE will fncrease ENTM one count The current value of ENTH will tend to Change the recording rate which is reflected in TOIF the time elasped since the last event recorded Feedback 15 accomplished when TDIF s compared to EITVL the desired recording rate The words used to implement the above scheme are presented below TDIF TDIF LAST EV CVDY DYN CYHR MNN DYN DYO 5 0 HRN HRO 3C MIN MNO UPDAT UPDATE TIME DYN DYO HRN HRO MNN MNO i ERATE EY RATE TDIF EITVL gt if 1 ELSE ENTH 1 THEN ENTH EMIN ENTH 47 EMAX MIN ENTH i UPDAT LASTE CK TIME LAST EV TDIF EITVL IF ENTH 1 THEN ENTH ENTH CYDY 48 36 4837 4837 CYHR 4838 4838 CVMN 4839 4839 EVT STA RDTM ECTR AMPL N3LT NZRO PCTR EMIN ENTH EMAX MIN DY DAY BASE 16 OF AND 64 OF AND A FO AND 10 HR HR gt BASE16 OF AND A FO AND 10 MIN gt 5 16 OF AND A FO AND 10 CHECK FOR TRIG LTA 3 gt IF BELL TAIL GET TIME FIRST 1 COUNT EACH BEEP FREQ SRCH VALID CHECK ENTH lt ENERGY TEST 15 FREQ TEST 32 IMPL TEST OOM gt C3 OOO AND AND 3 CONDITIONS TRUE IF DOUT ERATE ELSE LASTE THEN STA LTA THEN
47. spects to BASIC FORTH 1 faster and more compact than BASIC features that are of prime concern for small systems l ke the ELOG Although assembly language faster than FORTH it 1 not well suited to easy program modification a necessary feature n a dynamic research situation The code 4k bytes is written a combination of FORTH and assembly which can be called from FORTH Timing 1s provided by an Omega Rad o synchronized clock which is accurate to about 20msec Omega is world wide system run by the United States Coast Guard primarily for navigation Its transmiss ons however are very 9 9810 32018 31545 9013 I 340913 NDI 120 19221440 43040934 3113982448 ddl NI KS 31135590 13008 Dus 01QUN ulug HUS 56254 age 5 325 431AL 013 d L BM A 11 TIT M34 xxm STH 11 2 13234 RA d O10UM 67340 Dion YANN LA f precisely timed which allows the synchronization of clock from the radio pulses The parallel time output of the clock is input to the ELOG and read whenever an event is detected The rad o clock combination 1 a commercially available product 10 The data are stored on magnetic tape cassettes or solid state mass storage Without waveform data up to 2000 events can be stored on a single cassette tape or 3200 in a prototype solid state mass storage The later option could be expanded in the printed circuit board version from a min
48. would take about 17 hours for the time to finally be accurate During this period or for any period of poor radio reception the status bit will be 1 For good time the status bit will be Jow logic 0 It can also be seen that the time needed to lock onto real time c n be greatly reduced by having a watch accurate to less than 5 seconds 4 3 SENSOR INSTALLATION The ELOG front end is set up for the Mark Products L4 geophone The sensor should be buried as deeply as practical at least 50 feet from the rest of the site This will help m nimize no se coupling from the site to the geophone level should 4150 be used to achieve an orientation within 5 degrees to the vertical axis to the geophone ax s 4 4 ELOG setup step by step 1 Bury the sensor as described above and connect to GEOPHONE connector input Connect red geophone wire to white wire on geophone cable and black to black 2 Connect the RG 58 coaxial cable from the Omega receiver antenna to input 3 Synchronize the Omega receiver and set the clock as described above 4 Connect the power cable to POWER 5 Connect oscilloscope probe to test points and adjust gain on amplifier until signal 1 200 400 mv peak to peak Remove probe 6 Connect one end of the RS 232 cable to EIA connector on CPU board and the other end to the TRS 80 model 100 computer running the terminal emulation program at 1200 baud 7 Reset CPU switch on Tape I O boar
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