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STK-MBa53 User`s Manual - TQ

1. VCC3V3 VCC3V3 e e Sle Se S Qu Ole ole o N Ole b ym x x DISP1 DATA O 23 DISP1 CLK DISP1 DRDY DE gt DISP1_HSYNC a EDGE HPLG e 1k0 DISP1_VSYNC gt I2C3 SCL e 00 gt BSEL SCL 12C3_SDA lt q e 00 gt DSEL SDA P3 00 e gt ISEL RST Ppa MSEN PO1 1kQ 1kQ Illustration 30 Block diagram DVI digital signals Illustration 31 Position of DVI connector X5 Table 48 DVI connector X5 Manufacturer No Description Package DVI I receptacle a Lellz le ls Js fs gt lb Right angle Molex 74320 1004 1OO matiim cycles a le aag gaa 20 C to 85 C I User s Manual STK MBa53 UM 100 2013 TQ Group Page 36 Table 49 Pin assignment DVI connector X5 Pin Pin name Signal Dir Remark TMDS Data2 TMDS DATA2 TMDS Data2 TMDS_DATA2 TMDS Data2 4 Shield DGND TMDS Data4 DDC Clock 15 k Otto VCC5V additional LCL filter in series DDC Data I O 15 k Of to VCC5V additional LCL filter in series Imax 55 mA 10 uF 1 uFY to DGND additional LCL Filter in series 1 Additional data line filter in series Additional data line filter in series Not used 7 10 11 12 13 14 16 17 18 19 20 21 22 23 24 C1 C2 C3 C4 5V Power VCC5V Additional LCL filter in series Additional data line filter in series Additio
2. 18 Protective creditor VINE VOC ido 19 Position of power supply connectors XB X21 scssssssssssssessssssssccscsssssssscscscsesesessesesessseseseseseaesesesecseseaesessseeseseaeseseeeeseaeaes 21 Block diagram Ethernet rr da 21 Position of Ethernet connector X11 ss ssesseessesseessesssesseessesseesseoseeoseosersseossesseesseoseesseoseeoseossroseessroseesseoseeoseoseroseosersseessessees 22 Block diagram USB 2 0 Hi Speed 1 3 Ethernet 2 ueueesesesssssssssssensnenenenenenenenenenenenenenenenenenennnenennenensnnnsnnnnnnnnenennnenenenen 23 Position of USB RJ45 pin header connectors X9 X10 X19 ssessesssessessessessessessesseeseeseeseeseensensessessesseoseoseeseeseeseeseesee 24 Block diagram USB 2 0 Hi Speed OTG sun 26 Position of USB Micro AB connector iran a AAA AAA 26 block diagram CAN CAN an 27 POSO ads 28 Position Of pin headers X3 X4 sscssesssssssssssssesesescscssssessssssssssssssssssssssssesesesesesesesesesesescasecesecesesesesesesesessesssesesesesssssesssssseseses 29 BIOCK ANLAGE 2 30 Position of D Sub 9 pin connectorX1 een 30 Block diagram RS48B ccesesssssssssssssscssssscsssesescsssssssssssssssssssssssssssssesssesssssessesesescscscseseseseseseseseseseacacacacassesesssssesesessssseseseseseeees 31 Position of pin headers S4 cnc ERE ER ERE ER ER ERE R 32 oido ge laa o ab I E 33 Block diagram DVI analog signals
3. 41 4 2 11 v 42 4 2 12 DE ACER 43 4 2 13 ci n 45 4 3 Diagnostic and user INTEPFACES ccssesesessssssssesesscscscsssssssscscsssssssessesesssssesssscsesssssssscseseseassesscsesessassesssseseseassesssscseseasssseseeseseasassesecseseasassees 49 4 3 1 DANO e EEI ae EN A ENEE 49 4 3 2 SE o Tite p o eG 51 4 3 3 Power On and Reset button uesssssssssssnenenenenenenennnenenenenenenennnnnnnnnnnnnnnnenenenenenenenenenenenenenenenensnenensnsnsnsnsnsnsnsnsnsnsnsnsnsnnsnsnnnsnsnnenenenenenenenenen 51 4 3 4 CANT CANAR AS IA cas 51 4 3 5 Boot Mode CONFIGUIATION ccessssssssssesssecscsesssssesscscssssseseescscsesssessesesesssesessesesessassesseseseseasssucseseseassssussesescaesesscusseseacsesscucseseaeassesseseseaeaseees 52 4 3 6 os 55 User s Manual STK MBa53 UM 100 2013 TQ Group Page ii TABLE OF CONTENTS continued 5 iua Nen uelle vllo MEME 56 5 1 General NOtes s ssessessessesseeseeseessessessessessessesseoseoseoseessesseosessroseoseoseoseoseoseoseoseoseessesseseoseeseoseoseoseoseostostostostestesessteseoseostoseosesseoseostoseoseeseeseesteeeese 56 5 2 DIES O A TM 56 5 3 O Ea a ii ii li a ai i a AE 57 5 4 Ma WM AIT cr N aa A 57 5 5 CNN 57 6 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONG cccssssssssssssssssscscssssseceesescsssssessesesesssusecseseseassesecseseseassescsese
4. User s Manual STK MBa53 UM 100 2013 TQ Group Page 47 Table 67 Pin header X19 Remark 1 Alternative function WEIM bus Pin Signal Interface Dir 2 Routed to DVI transmitter 3 Used for Boot Mode configuration 1 veenv Power 2 VCGV Power AA Power AAA Power 5 ID Power 6 IDN y O Power PARK ISPD RE mnc 0 o 8 DISPIDRDYDE DISI O V2 Jm 0 0 0 9 DISPILHSYC DSPI 0O J2 4 10 DISP DATI J DSPl OO J 23 0 0 M DSPI VSYTNC J DSP 0O R o 12 j DSPLDA3 DSP O 23 0 L0 13 j DSPIDAO DSP O 23 14 jDSPLDAS ISP J 2 m 15 j DISPPLDA2 DISI O V23 Q4 4 J 16 jDISPILDA7 DSPl OO J 1423 9 0 0 0 V DSPIDA4 J DSPl OO J 2 18 DSPLDAP DSP 2 3 19 j DSPIDAG ISPD 0O J2 mJ 20 jDSPIDAT J DSPl OO 23 0 21 jJDISPIDA8 J DSPl 0O J 23 Q3 0 0 0 22 j DIPLIDAT3 DSP o 23 N 0 0 0 23 jDISPILDATO DSPl O J23 4 0 24 DISPI DATIS 7 O J23 4 0 0 0 25 DISP1 DATI BS O 26 DIPL DATI 1 DSPl OO 23 J 0 0 27
5. Common Mode ma mar OS USB H1 DP ma gt USBDPO USBDM2 gt Choke USB_H1_VBUS VBUS_DET MIC2026 1YM PRTCTL2 4 pe ENA OUTA UsB HOST1 VBUS FLGA CAT93C56 PRTCTL3 lt q e gt ENB OUTB USB_HOST2_VBUS DI a EEDO FLGB DO gt EEDI SK 4 EECLK USER a gt b CS EECS Common Mode USB Host 2 T USBDM3 q gt Choke 4 g USBDP4 t gt gt T Common Mode EE USBDM4 a gt Choke MIC2026 1YM PRTCTLA lt q pm ENA OUTA usB HOST3 VBUS FLGA TXP N Ethernet 2 RXP N q Illustration 17 Block diagram USB 2 0 Hi Speed 1 3 Ethernet 2 7 50 ppm incl tolerance at 25 C drift over temperature range of 40 C to 85 C and ageing after 10 years User s Manual STK MBa53 UM 100 2013 TQ Group Page 24 Par apa E LI mur em ell Ei mnn IRE Bane BOE E S508 a 858 E in arse Hr i Illustration 18 Position of USB RJ45 pin header connectors X9 X10 X19 The pin assignment of connectors X9 X10 and X19 is shown in Table 29 Table 30 and Table 31 Table 28 USB RJ45 pin header connectors X9 X10 X19 Connector Manufacturer number Description Dual port USB receptacle type USB A Un 30 Vams AC In 1 A Umax 500 V AC for 1 minute 55 C to 85 C RJ45 receptacle Integrated magnetics 1 5 kVams min LEDs green and yellow 0 C to 70 C 750 mating cycles Pin header 2 54 mm pitch 2 x 30 pins gt 7 Nretention force 40 C to 163 C Yamaichi US
6. 25 Cto 85 C Connectors for TOMa53 module 120 pin Tyco 5177986 5 Plugged height 5 0 mm SMD120 40 C to 125 C 100 mating cycles See 1 TOMa53 User s Manual I AB16 1 2V LVDSO LVDSO CLK N A VDS1 CEK N LVDS1 1 2V A13 V 1 2V LVDSO LVDSO CLK P V User s Manual STK MBa53 UM 100 2013 TQ Group Page 9 Table 7 Pin assignment module connector X1 Ball I O Level Group Signal Pin Signal Group Level I O Ball P ov POWER DGND 1f 2 DGND POWER OV P PO 33V CSIO CSIOHSYNC 3 4 CSIOPIXCIK o CSO o 33V I Por Pia 33V CSO o CSONVSYNC 5 6 DGND POWER ov P P 0V POWER DGND Oo 7 8 CSO DATAEN CSO 33V I POS Rol 33V CSO CSOD amp 9 10 CS0 D5 amp CSO 33V l Ro Ro i 33V CSO CSOD6 1 12 cso D7 CSO 33V l ROB Tor 33V CSO CSODB8 13 14 CSOD9 CSO 33V RM RoS 33V CSO CSODIO 15 16 CSIO D11 2 CSO 33V To T03 33V CSO CSOD 2 17 18 CSIO DI3 CSIO 33V I T06 vor 33V CSO CSODi4 2 19 20 CSIO D15 CSO 33V U0 T04 33V CSO CSODI6 21 22 CSOODI7 CSO 33V T05 U03 33V CSO CSODi8 23 24 CSOODI9 CSO 33V I UO Po5 1 33V CSO CSOPWDN 25 26 CSIOLMCLK o CSO 33V 1 V4 Poe 33V CSIO CSORS 27 28 DGND POWER ov PO P
7. eerte esee esee sete terere teret ntntntnen enin en inen inen spen sw sh sata sata sess saa naa 34 Block diagram DYI digital Signals sureste REK AER KEKEKEKEKE AAA eee SS 35 Position of DVI connector CREE 35 BIOCK A PR a aaa a a aa a aaa anka 37 Position or LVDS connector K Z ad 37 Block diagram AUCIO ccsssssssssssssscscscscscscsesesesescsesssssesssssssssssssssesssssscsssssssesssescsescsesesescseseseseseseaeacaeacaeseassssssessssseseseseseesseeees 39 EO romork AS Ida 40 Block diagram SD as 41 Position of SD card connector X6 eessssssssssssscscsssssssscscsesssssssescscscsssssessesesesesssessescseassesssuesesesssssesseseseaesesesseseseacsesssseseaeass 41 Block el ali m R LE ele mama pl 42 E A 42 Block diagram oo UE en 43 Position OF pin NAAA ccepit tk kh ee nk tkt tta ra ctt 43 Position of pin headers 18 X19 XQO cscccscscseseesescsesesesesesssesesessssssssessseseseseseseseseseseseseseseseseseseaeseseaeseseseseseseseeeeeseeeeeeseseees 45 Position ol LEDS power supply V32 VS UA MMUA GAMME MA UM RARE A 49 Position of LEDs USB Host 1 Host 2 V28 V29 uu esssssssssssessssssssssssssssscscsssssesecscscsssssesescsesssssesscsescassssesecseseacsesesseseseass 50 Position of LEDs USB Host 3 and OTG V30 V31 miinciicicicnicinainicciciacai eese inti 50 Block diagram STIMU DUMONS iS ERR ERERRERRERUxR UOI UU RU UU aaa 51 PON e ee e AY 51 Configuring the boot loader with DIP switches S1 S2 3 uueneseseensnenenennenenene
8. LTC3603 RUN VCC12V max 1 A Illustration 11 Block diagram power supply The STK MBa53 is supplied at X8 or optionally at X21 with 12 V and generates 3 3 V and 5 V internally To supply external components these three internal supply voltages are additionally routed on pin header X20 Power Out At this header all three voltages can each provide a maximum of 1 A To avoid a cross supply and errors in the power up sequence the switching regulator for VCC3V3 should be switched on with VCC 2V775 of the TOMa53 The following implementation is recommended for a customer design VCC5V 4A Switching mak EA lator VIN Protection regu 12V 3 5 A circuitry LTC3605 e RUN VCC3V3 max 2 1 A gt Switching e TOMa53 regulator S LTC3603 a VCC 2V775 h gt RUN VCC12V max 1 A Illustration 12 Block diagram power supply recommended for customer specific carrier board User s Manual STK MBa53 UM 100 2013 TQ Group Page 19 Over a protective circuit the voltage Vin is directly used as a system voltage VCC12V The protective circuit Illustration 13 has the following characteristics e Surge protection by a SMBJ12C diode e Inverse polarity protection by MOSFET e Overcurrent protection by fuse X8 VIN_12V T VCC12V BU2 C 2 2 2 SM401BDY AR n c m BE L34 EE
9. STK MBa53 UM 100 2013 TQ Group Page 44 Table 63 Pin header X7 Manufacturer number Description Header 2 54 mm pitch 2 x 10 pins gt 7 N retention force 40 C to 163 C Fischer Elektronik SL 11 SMD 052 20 G Table 64 Pin assignment JTAG E gt Dir Remark 100 nF4 to DGND use only as reference 100 nF to DGND Imax 10 mA On the TOMa53 10 k01 to VCC2V775 On the TOMa53 10 k01 to VCC2V775 On the TOMa53 10 k01 to VCC2V775 On the TOMa53 10 kOt to DGND Pin name Signal VREF VSUPPLY VCC_2V775 100 Q gt VCC3V3 0 Q gt TRST JTAG TRST N DGND TDI JTAG TDI GND DGND JTAG TMS GND DGND TCK JTAG TCK GND DGND GND DGND 10 kO gt GND DGND TDO JTAG TDO GND DGND SRST RESET_IN GND DGND DBGRQ VCC 2V775 10 kO gt GND DGND DBGACK DGND 10 kO gt GND DGND low active signal t element to VCC5V pull up y element to ground pull down gt element in series U G UN N 6 8 LE Wo la User s Manual STK MBa53 UM 100 2013 TQ Group Page 45 4 2 13 Pin headers To connect extension cards to the STK MBa53 all unused and some other selected signals are routed to pin headers X18 X19 and X20 All pin headers have 60 pins with a 2 54 mm pitch The close placement of the headers makes it easy to plug on self developed boards SS SS 6R0 LIMA A ies d gm m m m m m m m m d Illustration 42 Posit
10. 0V POWER DGND 29 VO VO VO VO UO5 1 33V_ ESPL ESPIMISO 43 VO Vi O 33V ESP ESPLMOSI 45 46 ESPILSSI ECSPM 33V O Vo Yoo O 33V ESP ESPLSS2E 47 48 ESPLSSOR ECSPM 33V O Y03 P ov POWER DGND O 49 50 ESPLSS3 EcSP 33V 0 W03 ABO7 O 33V DISP DISPI_DRDY DE 51 52 DGND Oo POWER ov P AAS O 33V_ DISP DISPLDATI 53 54 ESPLSCLK ECSP 33V 0 U06 Yoo O 33V DISP DISPIDAT3 55 56 DISPI_CLK DISP 33V O AA05 ABOG O 33V DISP DISP1 DAS 57 58 DGND Oo POWER OVE PO AAO7 O 33V DISP DISPI DAT7 59 60 DISPI HSYNC DISP 33V 0 YO YO O 33V DISP DISP1_DAT9 61 62 DISP1_VSYNC DISP 33V O Yo4 ACO3 O 33V DISP DISPIDAMI 63 64 DGND POWER OV PO ABO O 33V DISPI DISPI DATI3 65 66 DISPLDATO DISP 33V O Wo Yoo O 33V DISP DISPIDATIS 67 68 DISPI DA DISP 33V O AA03 O 33V DISP DISP1 DATI7 69 70 DISPI DATA DISP 33V Vo9 Y05 O 33V DISPI DISP1 DATI9 71 72 DISPIDAT6 o DISP 33V O 33V DISP DISPIDATI 73 74 DISPIDAT8 DISP 33V O AC04 V4 O 33V DISPI DISPI DAT23 75 76 DISPI DATIO DISP 33V O P 0V POWER DGND o 77 78 DISPIDATI2 DISPI 33V 0 V07 AA09 O 33V VGA VGAHSYNC 79 80 DISP DATi4 DISP 33V O Yor O 33V VGA VGAVSYNC 81 82 DISPI_DATIG D
11. 29 BT_FREQ 1 ARM frequency 400 MHz diia Pad name i MX53 eFuse Configurations Remark BOOT_CFG1 0 0 MMU Cache is disabled by ROM during the boot vere eee BT_MMU_ENABLE 1 MMU Cache is enabled by ROM during the boot Patauie BOOT_CFG2 4 0 200 MHz AXI 400 MHz DDR gt Em Dal AXI DDR Freq 1 166 MHz AXI 333 MHz DDR poe BOOT_CFG2 3 0 19 2 24 26 27 MHz Auto Detection Zn ee OSC FREQ SEL 1 OSC frequency 24 MHz Default 0 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 53 Table 74 o Configuration Boot Devices for internal Boot Dd eMMC ESDHCV3 3 SD card ESDHCV2 2 SATA ESPI ECSPI 1 eFuse i MX53 Definition Configurations Definition Configurations Definition Configurations Definition Configurations 01 Boot from ESDHC Interface EIM_A22 BOOT CFGI 7 __ 01 Boot from ESDHC Interface Boot Device Selection EIM A21 BOOT CFG1 6 Else not defined Else not defined 0 not defined 0 SD EM A20 BOOT_CFG1 5 SD MMC selection 1 eMMC SD MMC selection 1 MMC 0 Normal Boot 0 Normal Boot EIM_A19 BOOT_CFG1 4 Fast Boot Support 1 Fast Boot Fast Boot Support enorde ei 0 Normal Speed Mode 0 Normal Speed Mode 0 not defined 0 not defined EIM_A18 BOOT CFG1 3 SD MMC Speed Mode 1 High Speed Mode SD MMC Speed Mode 1 High Speed Mode HD Type 1 SATA Serial ROM select 1 SPI EIM_A17 BOOT_CFG1 2 Not defined Not defined a Not defined EU Not de
12. DISP DATI n DSPl O 23 J 0 28 DISPLLDATIO n DSPI O 29 DISPI DATI6 DSPl OO 23 4 J 30 DISPLLDAT20 DSPl OO J 2 4 0 31 jDISPILDATIB DSPI OO Ro 32 DISP1 DAT23 DSPI OO J V2 9 0 0 0 33 DIPIDAD0 DSPl KP 9 34 USBH3WBUS O J 10gFWtoDGND gt gt S 35 DISPPLDAT2 J DIPI O J 0 0 36 USBH3 D VO Commonmodechoksinseries lt 37 DGND J Power 000000 38 USBH3D VO Commonmodechokeinseries 39 R2SC DC2 3 O Additionally used as on board bus 40 DGND S Power MEE AMET 44 SPLMISO A 45 sessi E DE G OS 46 SPLSCK SP BE Oo SOS AT SPLSS2 SP BEE gt DE 0 0 48 ID Pwe 49 CDPOWREN DER O So LCD BITEN LCDCIRL O 51 LCD RESET LCDCRL O 52 LCD CONTRAST COCR O 53 DGND Power Jo 54 DGND q Power AA 56 TOUCHX TR 587 TOUCHY jTouh d 4 000 00 58 TOUH X2 MARA 59 DGND o o j Powe J 60 DGND J d Power j J O low active signa
13. Table 52 Configuration for headphone or line out Signals at X13 R112 R114 R113 R115 R117 R118 Remark nem ona oa nk De Headphone na ma 00 O0 m amp oa Table 53 Electric characteristics of the audio interface gt Parameter in Typ Max Unit Remark At 16 O input impedance mW At 32 O input impedance At 16 Q input impedance with 60 dB input power At 32 Q input impedance with 60 dB input power _ General Vrms 1 25 Z o See 6 data sheet SGTL5000 User s Manual STK MBa53 UM 100 2013 TQ Group Page 40 Illustration 35 Position of jacks X13 X14 X15 Table 54 Jacks X13 X14 X15 Manufacturer number Description e Jack 3 5mm e Right angle e 5 000 mating cycles e Contact resistance 30 MOQ max Yamaichi LJE3530K Table 55 Pin assignment audio connector X13 line out headphone Pin Pin name Signal Dir Remark AGND AUDIO P Optional connection to AGND HP 0 O n a 2A 2B AUDIO OUT L 1 uF gt Optional connection to HP L 0 O n a additional ESD protection 3 AUDIO OUT R 1 uF gt Optional connection to HP R 0 O n a additional ESD protection low active signal t element to VCC5V pull up y element to ground pull down gt element in series Table 56 Pin assignment audio connector X14 line in Pinname Signal Dir Remark 2A 2B AUDIO IN L 1 uF gt Additional ESD protection 3 AUDI
14. uu sesssssssssssssscscssscscscsscscsessscsssssssssssssssssssssssesesesesesesesesesseceesescsescseaees 22 USB RJ45 pin header connectors X9 X10 X19 sccssssssssescscsescscssscsseccscscscsesessssssesescsesesesesssssseseseseseseseseseesescsesesesesesesseseseeees 24 Pin assignment USB host 1 2 connector X9 uusssesesensnsnsnnenenensnsnnnnenenensnsnnsnenenensnsnnrnenenensnsnnsnenenensnsnnsnenensnsnsnnenenensnsnsnnesenensnnnne 25 Pin assignment RJ45 receptacle X10 Ethernet 2 uu eesssesssssssssssscssscscscscscscscscscsesessssssssssssssssssssssssseseseseseseeeeeseceescscseseseaees 25 Pirpassignment USB host gt pin header X Inn 25 USB type Micro AB connector XK 1G ee ee 26 Piriassigbmient USB TG CONNECTION X o 26 Electrical parameter CANT 7 CAND sscisssssssssssasssasasasasasasasnsstassasasasacasasisnsnsnsnsnsnensnsnanasasananaoananasasasasavasasasasasasasnsasnanananshensnsnsnensnonie 27 Settings of DIP switches for CANT CAN2 termination ussessssssessssnsnnnnsnsnnnnenennnnensnnnnensnnnnenensnnensnsnnensnsnnensnsnnensnsnsensnsnnenenne 27 Characteristics of the galvanic separation for CAN1 and CAN2 cccsssesesssscsssssssesscscsssssssececscsssssssesscsesesssesesseseasssseseesees 28 lio A MA ee 29 Pin assignment CANT CAN2 connector X3 X4 ssssscsssssscscessorscssesserscsscosscscessorscssessesacsssosacscessarscssensaracssensacscessanscscensanaceseas 29 Electrical parameters RS232 cceessscsescscssssssssssescscsescscsssssssssscs
15. 2775V bu BOS 68 JTAG TCK o STAG 2775V bo D09 POWER OV P J o 72 SATA RP JSATA I2 Biz 74 SATA RXM o SATA 2 I JAR 76 DGND POWER OV JP 78 FECRSTK FEC o 33V O K0 80 FECRXDO OO FEC 33V I CH 82 FECRXDI FEC 33V ET o 84 FECRXDV FEC 33V DM 86 FECMDO FEC o 33V lOwm D12 88 FECREF CLK FEC 33V JE 90 DGND POWER OV PO 96 SDDAT2 SD 33V VO o 98 SDDAT3 o SD 33V VO E3 100 POWER OV P 1060 DGND POWER OV P 110 BOOT MODEO CONFIG 2775V lo C18 114 sPLss2 SPI 33V O F16 116 SPLSSI SPI 33V O Fiz 118 SPLMOSI SPI 33V O Fi8 120 POWER OV P User s Manual STK MBa53 UM 100 2013 TQ Group Page 11 4 1 2 C address mapping VCC3V3 VCC3V3 Sie Ela Q S yle e E Is 2862450 I2C2_SDA 4 e I2C3_SCL e e I2C3_SDA wed e SDAO SCLO DSEL SDA BSEL SCL SDA1 SCL1 Illustration 3 Block diagram lC buses Both I C buses of the TQMa53 are used on the STK MBa53 I C2 and I C3 Table 9 and Table 10 show the internally used device addresses The PC buses I C2 and I C3 are also routed on the headers X18 and X19 l C3 is level shifted to 5 V and also available at the DVI receptacle X5 see also
16. 3 Registered trademarks TQ Systems GmbH aims to adhere to the copyrights of all the graphics and texts used in all publications and strives to use Original or license free graphics and texts All the brand names and trademarks mentioned in the publication including those protected by a third party unless specified otherwise in writing are subjected to the specifications of the current copyright laws and the proprietary laws of the present registered proprietor without any limitation One should conclude that brand and trademarks are rightly protected by of a third party 1 4 Disclaimer TQ Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality Nor does TQ Systems GmbH assume guarantee for further usage of the information Liability claims against TQ Systems GmbH referring to material or non material related damages caused due to usage or non usage of the information given in the User s Manual or due to usage of erroneous or incomplete information are exempted as long as there is no proven intentional or negligent fault of TQ Systems GmbH TQ Systems GmbH explicitly reserves the rights to change or add to the contents of this User s Manual or parts of it without special notification 1 3 Imprint TQ Systems GmbH Gut Delling M hlstra e 2 82229 Seefeld Tel 49 0 8153 9308 0 Fax 49 0 8153 9308 134 Email info tgs de Web http www tq group com
17. 3 mm diameter see Illustration 54 e Weight Approximately 200 grams Illustration 53 Height of STK MBa53 140702 163 65 142 ii db d d dd la 4 5 TE oss TE dur ir i 8 00 opo 0000 FE 20000 Sa 1700 2 DTT mo 00000000 00000000 L B Jes a gee 000000 TE a os io Ol Q o a de EAS jo o lo ol T 00 2 0095 06 Bet go spp Ba a 0000 sees m fe oft onop Y fl ani H 154 81 119 4 i id i gt ll pipi ima OEE at nrlar 141 4 154 52 163 03 kdd d d db d d d d id Illustration 54 Dimension drawing of STK MBa53 Page 56 I User s Manual STK MBa53 UM 100 2013 TQ Group 5 3 Housing The form factor and the holes of the STK MBa53 are designed to be mounted in the COMSys housing For further information please contact the TO Support 5 4 Thermal management No special precautions have been met concerning the thermal management of the STK MBa53 5 5 Component placement The component placement of the top side is shown in the following illustration No components are assembled on the bottom side Je AS RGR 17 Yi ae 5 V13 ms ewt O 8 iR X12 e e peto e ru e Jv2 n ses BLE o finm S9 euer B bo JE ed x mi i s 85 BEE BORE Hi
18. Hz or pixel rates of up to 165 MHz are supported More details are to be taken from the TFP410 data sheet The VGA signals for RGB are directly routed to the connector The levels of the following signals are separately adapted to the VESA standard e VGA HSYNC and VGA_VSYNC e 2C3 SCLandl12C3 SDA The levels are adapted using the VGA Port Protector MAX4895E This device also provides an ESD protection for the RGB signals Some of the image data signals are used to configure the boot mode and are routed to header X19 too VCC5V g g TQMa53 MAX4895E Je TVDAC_IOR o gt R TVDAC_IOG e gt G TVDAC_IOB o gt B VGA_HSYNC HO H1 VGA VSYNC gt VO V1 I2C3 SCL SCLO SCL1 o I2C3 SDA 4 SDAO SDA1 a o Illustration 29 Block diagram DVI analog signals See 8 data sheet TFP410 la User s Manual STK MBa53 UM 100 2013 TQ Group Page 35 By using a DVI I receptacle which transmits digital and analog image signals the interface is compatible to the VGA standard and to the HDMI standard The difference to the HDMI standard is that with DVI only video and no audio signals are transmitted
19. SDWP 90 Doe 33V SD SD CDH 93 VO E14 O 33V SD SDCIK 97 Oo P 0V POWER DGND 99 P Jov POWER DGND X 105 C16 33V USBOTG USBOTG ID 107 Oo P 2775V POWER VCQV775 TH C7 O 33V SP SPLSSO 113 A20 33V SPI SPLMIO 115 E16 O 33V SPI SPLSCIK 117 P 0V POWER DGND O 119 No of PMIC ball See 3 Serial ATA specification 2 6 gt See 4 USB 2 0 specification I Page 10 Signal Group Level I O Ball 2 vccov POWER 5V p POWER SV P 6 vecsv POWER SV JP J 8 DGND Oo POWER j0OV P 10 DGND POWER OV P 12 DGND POWER OV P 18 DGND POWER OV P 22 RESETOUT PMIC 33V Ooo 24 LCD PWREN LCD o 33V O M4 26 LCD REST LCD o 33V O 1104 28 DGND POWER OV P 30 UARTIRXD UARTI 33V 02 32 UARTI_TXD_ UARTI 33V O J0 34 UARI3 RD UART3 33V I 10 36 UART3_TXD UARI3 33V O 105 POWER OV o P 40 CANLTX CANI 33V O C 42 CANIRX CANI 33V D05 44 DsSCIK DS 33V 0 CO o 46 DS DOUT 1S 33V O B0 o 48 DGND POWER j OV P 50 SPDIF OUT SPDIF 33V O A03 52 SPDIFIN SPDIF 33V I C 54 FIR RXD FIRE 33V I A0 VO 60 DGND POWER OV P 64 RESET_INE CONFIG 33V Ibu 66 JTAGTDI JTAG
20. section 4 2 7 DVI It is also possible to customise A0 to A2 of the lC addresses for the temperature sensor and the I O expander according to own requirements by placement option Table 11 and Table 12 show the possible address configurations Table 9 l C address mapping I C2 bus Device address Device Hex MSB Binary LSB TQMa53 rn 0x08 1 O A0 X MC34708VM Temperature sensor 0x48 1 1 0 A2 O A1 O A0 LM75A STK MBa53 Audio Codec D12 Ox0A 1 1 SGTL5000XNAA3 I O extension 0x20 0 A2 O AD O AO PCA9554 configurable Temperature sensor 0x49 D10 1 1 O A2 O A1 1 AO LM75A configurable EEPROM M24C64 0x50 1 1 0 A2 O A1 O A0 User s Manual STK MBa53 UM 100 2013 TQ Group Page 12 Table 10 l Caddress mapping I C3 bus Device address Device STK MBa53 DVI transmitter TFP410 DVI connector Version DDC2B DVI connector Version DDC Cl DVI connector Version E DDC Table 11 Possible configurations of the C addresses for the I O expander Device address Remark A2 Al Table 12 Possible configurations of the I C addresses for the temperature sensor Device address Remark EE D x gt N gt mi mi gt I Q Co R69 ma na o O ma 00 00 Q 0 There are no pull ups for the C3 bus on the STK MBa53 On a carrier board these
21. service functionality and special characteristics of the used module incl BIOS Specifications of the used components The manufacturer s specifications of the used components for example CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable operation These documents are stored at TO Systems GmbH Chip errata It is the user s responsibility to make sure all errata published by the manufacturer of each component are taken note of The manufacturer s advice should be followed Software behaviour No warranty can be given nor responsibility taken for any unexpected software behaviour due to deficient components General expertise Expertise in electrical engineering computer engineering is required for the installation and the use of the device The following documents are required to fully comprehend the following contents o Circuit diagram MBa53 SP e CPU Manual IMX53RM o User s Manual TOMa53 e Documentation of boot loader U Boot http www denx de wiki U Boot Documentation o Documentation of ELDK http www denx de wiki DULG ELDK la User s Manual STK MBa53 UM 100 2013 TQ Group Page 4 1 11 Acronyms and definitions The following acronyms and abbreviations are used in this document Table 2 Acronyms Acronym Meaning Advanced Host Controller Interface Advanced Microcontroller Bus Architecture Advanced RISC Mach
22. to PMIC register la User s Manual STK MBa53 UM 100 2013 TQ Group Page 17 At overvoltage and undervoltage the switching regulators for VCC3V3 and VCC5V also trigger a system reset over GLBRST The corresponding parameters are listed in Table 18 On self developed carrier boards it is recommended to route the signals RESET_IN and GLBRST to a common button A short keystroke triggers a warm reset of the CPU or a reset of the PMIC Depending on PMIC register GLBRSTTMR 1 0 a long keystroke triggers a complete power down and power up cycle Table 18 Electrical parameters PGOOD signals Parameter in Typ Max Unit Remark PGOOD VCC3V3 HIGH gt LOW Rising voltage 10 12 Overvoltage LOW gt HIGH Falling voltage 10 mE me HIGH LOW Falling voltage 10 13 Undervoltage Rising voltage 10 13 Overvoltage LOW gt HIGH Rising voltage 8 5 Falling voltage 8 5 Table 19 Power and Reset Buttons S8 S9 Manufacturer number Description Push button 3 N 1 N actuating force Knitter Switch TMSE 10 J RA Service life gt 100 000 cycles Right angle 55 C to 125 C Illustration 10 Position of buttons S8 S9 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 18 4 1 7 Power supply VCC5V 4A Switching YA E VIN Protection E ies 12 V 3 5 A circuitr y RUN VCC3V3 max 2 1 A Switching A regulator
23. 0 Diagnostic LEDs Manufacturer number Description SMD LED green Radiation angle 160 Osram LGR971 KN 1 OSM Wavelength 570 nm 30 C to 85 C Optical efficiency 2 5 Im W SMD LED orange Radiation angle 160 Osram LOR971 OSM Wavelength 605 nm 30 C to 85 C Optical efficiency 1 5 Im W V Vis Illustration 43 Position of LEDs power supply V32 V35 User s Manual STK MBa53 UM 100 2013 TQ Group Page 50 Illustration 44 Position of LEDs USB Host 1 Host 2 V28 V29 Illustration 45 Position of LEDs USB Host 3 and OTG V30 V31 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 51 4 3 2 Stimuli buttons As simple input stimulation three push buttons which are read by an I O expander are assembled on the STK MBa53 VCC3V3 VCC3V3 A A sl e e e o o o z push button A S5 I2C2 SCL 7 push button B S6 12C2_SDA e e push button C S7 GPIO5 GPIOO 4 LA Illustration 46 Block diagram stimuli buttons Table 71 Stimuli buttons Manufacturer number Description Push button 1 6 N actuating force Knitter Switch TSS 61N Service life gt 200 000 actuations 4 3 mm high colour brown 40 C to 85 C E MES mT q Illustration 47 Position of S5 S6 S7 4 3 3 Power On and Reset but
24. 1 6 Tips on safety Improper or incorrect handling of the product can substantially reduce its life span I User s Manual STK MBa53 UM 100 2013 TQ Group Page 2 1 7 Symbols and typographic conventions Table 1 Terms and Conventions Meaning This symbol represents the handling of electrostatic sensitive modules and or components These components are often damaged destroyed by the transmission of a voltage higher than about 50 V A human body usually only experiences electrostatic discharges above approximately 3 000 V This symbol indicates the possible use of voltages higher than 24 V Please note the relevant statutory regulations in this regard Non compliance with these regulations can lead to serious damage to your health and also cause damage destruction of the component This symbol indicates a possible source of danger Acting against the procedure described can lead to possible damage to your health and or cause damage destruction of the material used This symbol represents important details or aspects for working with TO products A font with fixed width is used to denote commands file names or menu items 1 8 Handling and ESD tips General handling of your TO products The TO product may only be used and serviced by certified personnel who have taken note of the information the safety regulations in this document and all related rules and regulations A general rule is do not touch the TO produc
25. 156XWO v 1 TQMa53 LVDSO_CLK_ P N LVDSO TXO P N LVDSO TX1 P N LVDSO TX2 P N LVDSO TX3 P N LVDS1 CLK P N LVDS1 TXO P N LVDS4 TX1 P N LVDS1 TX2 P N LVDS1_TX3_ P N Illustration 32 Block diagram LVDS m B8 3825 s BES pHRER aa ii Pin 1 Illustration 33 Position of LVDS connector X17 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 38 Table 50 LVDS connector X17 Manufacturer number Description Board to cable socket connector 30 pin Pitch 1 mm Hirose DF19G 30P 1H Right angle 30 mating cycles 35 C to 85 C Table 51 Pin assignment LVDS header X17 Pin Pin name signal Dir Remark 1 LVDSO TXO N LVDSO TXO P LVDSO TX1 N LVDSO TX1 P LVDSO TX2 N LVDSO TX2 P DGND LVDSO CLK N LVDSO CLK P o 0 EUN o 0 o NEN o MEN 10 LVDSO TX3 N EN o 0 o NE o 0 EN o 0 o 7 11 LVDSO TX3 P 12 LVDS1 TXO N 13 LVDS1 TXO P 14 DGND 15 LVDS1_TX1_N 16 LVDS1_TX1_P 17 DGND 18 LVDS1 TX2 N 19 LVDS1 TX2 P 20 LVDS1_CLK_N 2 8 LVDS 3 3 LVDS NO MA A O Vi 26 VCCSVIVDS P minus the current which is drawn from the headers X19 and Power OUT X20 27 VCCVIVDS P 10 uF 1 uF to DGND additional ferrite filters in series 29 VCGV31VDS P minus the current which is drawn from the h
26. 3 K 3 dd 4 ceo N Lpo ge a gt m M Din 3 5A F 29UH 5A gm desu AS SMBJ12C bs 4TUI25V 4TUI25V HT P468 HTP5 X21 KRM2 DGND DGND DGND DGND DGND 1 2 DGND Illustration 13 Protective circuit for VIN VCC12V Table 20 Electrical parameters of the protective circuit Parameter Overcurrent limitation by fuse Overvoltage limitation by diode SMBJ12C Table 21 shows the electrical parameters of the power supply over Vin The necessary wall plug unit has to be selected accordingly Table 21 Electrical parameters VIN VCC12V Parameter in Max 6 See 5 data sheet Belfuse SSQ 1 5 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 20 4 1 7 1 Electrical parameters switching regulator The parameters shown in Table 22 and Table 23 result from the switching regulators LTC3603 and LTC3605 used on the STK MBa53 Table 22 Electrical parameters VCC5V Parameter Max Unit Remark Output voltage VCC5V 4 795 4 929 Output current VCC5V Ripple MEA NE MEME ama Efficiency a lt 9 5 066 196 feedback resistors gt 21 4 444 lour OA lout 3 9 A lour 4 0 A lour 2 0A lout Load step change lour O A to 3 7 A Temporary drop of VCC5V Control time E Un gt Table 23 Electrical parameter VCC3V3 Parameter Min Typ Unit Remark Output voltage VCC3V3 3 173 3 257 3 344 Output current VCC3V3 Ripple 1 feedback resistors lour 0A lour 1 9A L
27. 3 N LVDS1 1 2V A12 Ov OV POWER DGND N O N O me GND OWER OV User s Manual STK MBa53 UM 100 2013 TQ Group Table 8 Pin assignment module connector X2 Ball I O Level Group Signal P sv POWER VCC5V Pr P sv POWER VCC5V 3 P sv POWER VCCV 5 P 10V POWER DGND 7 P 0V POWER DGND 9 JP OW POWER DGND m P_ J oV POWER DGND 17 Als P 33V PMC LCHL 19 103 O 33V LCD LCDBLTEN 23 B07 O 33V LCD LCD CONTRAST P 10V POWER DGND 27 Jo O 33V UAR2 UARI2TXD 29 Ko 33V UAR UAR2RXD 31 Ko3 33V UAR UART2_RTS 33 Kos O 33V UARI UART2_CTS 35 P 0V POWER DGND 37 E05 O 33V CAN CAN2TX 39 E06 33V CAN CAN2 RX 41 Do6 1 33V US PSDIN__ 8 E07 O 33V S 2S LRCLK 45 P 0V POWER DGND 47 C8 O 33V RS RS MCLK 49 Oo P ov POWER DGND 51 8065 O 33V FRI FRLTXD 53 Op P 0V POWER DGND 59 A07 O 2775V STAG JTAGTDO 63 P 0V POWER DGND 69 A0 O P SATA SATALTIXP 71 B10 O 2 SAA SATATXM 73 P Jov POWER DGND 75 Mos 33V FE X FECINE 77 co O 33V FEC FECTXEN 79 FO O 33V FEC FECTXD 81 D10 O 33V FEC FECTXD 83 E10 O 33V FEC FECMD 85 F12 I 33V FEC FECRXER 87 P J oV POWER DGND 89 CO7 33V SD
28. 33 The characteristics of the galvanic separation are shown in the following table Table 45 Characteristics of the galvanic separation for RS485 Parameter Pin 1 Illustration 28 Position of pin header X2 Table 46 Pin headers connector X2 Manufacturer number Description 4 pin header 160V 8A Pitch 3 5 mm 40 C to 100 C Phoenix Contact MCV 1 5 4 G 3 5 Table 47 Pin assignment RS485 connector X2 Pin Pin name signal Dir RS485_A Non inverted input galvanically separated RS485_Y Non inverted output galvanically separated Inverted output galvanically separated EN 2 RS485B qd Inverted input galvanically separated 0 HOM I User s Manual STK MBa53 UM 100 2013 TQ Group Page 34 4 2 7 DVI An external display can be connected to the single link DVI interface which provides analog and digital image data A DVI receptacle type is used X5 The DVI interface corresponds to the DVI specification 1 0 The Transmitter TFP410 for the digital image signals provides two possibilities to configure the display interface e Byl C bus e By fixed wiring using the config pins On the STK MBa53 the configuration by l C is used by default The display interface can also be configured using configuration resistors as a placement option Detailed information concerning the component placement options is to be taken from the circuit diagram Resolutions of up to 1080p and WUXGA at 60
29. 53 has a different I C address see Table 9 section 4 1 2 C address mapping Table 14 Electric characteristics of the temperature sensor LM75A Parameter Precision Resolution The characteristic curve of the sensor is shown in the following illustration The decimal values are the two s complement of register value Temp More details are to be taken from the data sheet 1100 900 700 500 300 100 100 60 300 Register value decimal 500 Temperature C Illustration 6 Characteristic curve of the temperature sensor The temperature sensor is on the top side of the STK MBa53 directly under the TOMa53 Illustration 7 Position of temperature sensor See 7 data sheet LM75A I User s Manual STK MBa53 UM 100 2013 TQ Group Page 15 4 1 5 RTC backup supply The PMIC used on the TOMa53 provides an RTC For the backup supply of the RTC the PMIC provides a pin LICELL which is routed to the module connector For the RTC to work reliably the voltage at the pin LICELL has to be in the range of 1 8 V to 3 6 V The accompanying quartz is assembled on the TOMa53 A lithium battery with very low self discharge is used to supply the RTC of the TOMa53 The battery only supplies the RTC if VCC5V is not present at the TOMa53 The battery is socketed and can therefore be exchanged easily Table 15 Electrical par
30. 85_Z a S4 2 1200 R11 Illustration 26 Block diagram RS485 UART3 of the i MX53 is routed to the transceiver SP491E which provides the signals as RS485 interface at the D Sub 9 pin connector X2 The RS485 interface is galvanically separated and can operate in Full duplex mode at a maximum of 10 Mbit s Half duplex mode is also possible by placement option Table 42 Configuration of the RS485 modes Mode R10 R11 Remark Full duplex AN Receiver always active default Half duplex Receiver is controlled by DE Signal GPIO1_GPIO3 The RS485 signals can be terminated with 120 O by using DIP switches S4 1 and S4 2 Details can be found in the following section The DC DC converter R1S 0505 provides an isolation voltage of 1 kV It does not provide short circuit protection User s Manual STK MBa53 UM 100 2013 TQ Group Page 32 Table 43 Electrical parameters RS485 Parameter The RS485 signals can be terminated with 120 O using DIP switches S4 1 and S4 2 The possible settings of the DIP switches are shown in the following table Table 44 Settings of DIP switch S4 for RS485 Switch Interface Position On Position Off RS485 Receive path is terminated with 120 O Receive path is not terminated RS485 Transmit path is terminated with 120 O Transmit path is not terminated Illustration 27 Position of pin headers S4 User s Manual STK MBa53 UM 100 2013 TQ Group Page
31. B A 002A Pulse J0011D21BNL Fischer Elektronik SL 22 124 60 G User s Manual STK MBa53 UM 100 2013 TQ Group Page 25 Table 29 Pin assignment USB host 1 2 connector X9 Pin Pin name Signal Dir Remark VBUS USB_HOST1_VBUS EMI filter gt USBH1_D USBH1_D E i U1_1 U1_2 U1 3 U1 4 100 uF to DGND Additional common mode choke in series D Additional common mode choke in series DGND p P Dao VBUS USB HOST2 VBUS EM filter gt P 100 uF to DGND LANE m Ground U2 1 U2 2 U2 3 Additional common mode choke in series o low active signal t element to VCC5V pull up y element to ground pull down gt element in series Additional common mode choke in series Table 30 Pin assignment RJ45 receptacle X10 Ethernet 2 Name Signal Dir Remark ETH2_TXP X X X i ETH2_TXN 9 LED1 Anode 10 LED1 Cathode A2 12 LED2 Anode K2 11 LED2 Cathode ETH2_SPD 270 O gt low active signal t element to VCC5V pull up y element to ground pull down gt element in series Not used N Wi BRL WIN N Link Activity green shines when connection is established blinks during transfer A pe Ss Speed Indicator yellow shines at 100 Mbit s does not shine at 10 Mbit s 2 e Table 31 Pin assignment USB host 3 pin header X19 Pin Signal Dir Remark USBH3_VBUS 100 uF Y to D
32. DIF CSIO WEIM opt l DVI Transmitter BI CAN 120 Reset Power DIP switches On Button o Level shifter RS485 120 Q DIP switches 9 Status LEDs USB 2 0 Hub with integrated 3 Buttons Boot Mode Ethernet navigation DIP switches Controller gt and USBOTG DISP1 Audio Codec omo oz PHY Amplifier USBH1 cS ES VGA 2S UART2 y a A 1202 Ethernet PHY ke SAR j TQMa53 EDS CAN1 LVDS1 M RS232 CAN2 ESDHC2 Transceiver E LICELL SATA RS485 1202 JTAG Transceiver l B mm SET Internal gt I Suppl Transceiver extension de 33V DV CAN Transceiver __ Temperature Power Supply e Sensor galvanically ted separate 12 V LCD CTRL Illustration 1 Block diagram STK MBa53 3 2 Functionality The core of the complete unit is the Freescale i MX53 CPU based processor module TQMa53 of TQ Systems GmbH This module which is plugged onto the STK MBa53 provides the connection to all peripheral components In addition to the standard communication interfaces like USB Ethernet RS232 etc all other available signals of the TQMa53 are routed on headers with a 2 54 mm pitch The STK
33. GND 34 EN 36 USBH3 D Additional common mode choke in series 38 USBH3_D Additional common mode choke in series low active signal t element to VCC5V pull up y element to ground pull down gt element in series 8 See USB Host 1 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 26 4 2 3 USB 2 0 Hi Speed OTG The USB OTG interface of the TOMa53 is provided on the STK MBa53 The OTG compatibility is achieved by a 5 pin Micro AB receptacle The ID signal is directly routed to the CPU USB 2 0 has been implemented which works in the Hi Speed Full Speed or Low Speed mode VCC5V VCC3V3 A A 10 kO USB OTG DN USB OTG DP lt i Common Mode lt lt gt Choke a USB OTG a USB OTG VBUS USB OTG ID Illustration 19 Block diagram USB 2 0 Hi Speed OTG z SEE Mere man yen a y wp wn a EE lol HEHH FE 88 88 EN tss Illustration 20 Position of USB Micro AB connector X16 Table 32 USB type Micro AB connector X16 Manufacturer number Description USB receptacle type Micro AB Right angle 10 000 mating cycles 30 C to 85 C Tyco 1981584 1 Table 33 Pin assignment USB OTG connector X16 Pin Pin name Signal Dir Remark 1 VBUS USB OTG VBUS EMI Filter gt low active signal t element to VCC5V pull up y element
34. ISPI 33V O ACT 84 DISPI DATI8 DISP 33V O Vo6 AB2 86 DISPI_DATZO DISPI 33V O AC21 88 DISPI DAT22 DISP 33V O P 0V POWER DGND 89 90 DGND o POWER OV P ACI O 12V LVDSO CIKP 91 92 LVDSI CLKP LWDS1 12V O Oo LVDSOCIKN 93 94 LVDSICIKN LVDS 12V 0 P 96 DGND o POWER OV P Oo _LvDSO_TXO_P 97 98 LVDS1 TXO P LWDS1 12V O Oo LVDSO_TXON 99 100 LVDS1 TXO N LVDS1 12V 0 P DGND POWER OV P Oo LVDSO XI PO LVDS1_TXI_P_ LVDS 12V O oO LVDSO TXIN LVDS1 TXIN LVDS1 12V 0 P DGND POWER OV P Oo LVDSO_TX2 PO LVDS1_TX2_P_ 1VD 1 12V O oO LVDSO T2 N LVDS1_TX2 N LVDSI 12V O P DGND POWER OV P Oo _LVDSO_TX3_P _LVDS1_TX3_P_ LVDS 12V O oo _LVDSO_TX3_N LVDSI_TS_N LVDS 12V O LETS DEN DGND POWER OV P O Ko 2X PB AFP I xzx XxE X I x UJ cle 2o fe C v Sw En No T4 GND GND OWER OV AA17 LVDSO_TXO_P VDS1 TXO P VDS1 1 2 V B14 Y17 LVDSO TXO N O LVDS1 TXO N LVDS1 1 2V C14 POWER GND 101 102 DGND OWER OV AC17 LVDSO_TX1_P VDS1_TX1_P LVDS1 12V B13 AB17 LVDSO TX1 N 105 106 LVDS1_TX1_N LVDS1 1 2V C13 GND GND OWER OV AA16 LVDSO TX2 P 109 110 LVDS1 TX2 P VDS1 1 2V B12 Y16 LVDSO TX2 N VDS1 TX2 N VDS1 1 2 V C12 GND GND OWER OV AC15 LVDSO_TX3_P 115 116 LVDS1_TX3_P LVDS1 1 2V AB15 LVDSO TX3 N 117 118 LVDS1 TX
35. Illustration 39 Illustration 40 Illustration 41 Illustration 42 Illustration 43 Illustration 44 Illustration 45 Illustration 46 Illustration 47 Illustration 48 Illustration 49 Illustration 50 Illustration 51 Illustration 52 Illustration 53 Illustration 54 Illustration 55 User s Manual STK MBa53 UM 100 2013 TQ Group Page v Block diagram STK MBa53 cccsssssssssssssssssscscscscscscscsescscsesescsssssssesssssssssssssssssesssssssscscsssssssescsesesescscsesesesesesescseacaeacacacacaeacasassenes 6 s fere so rana MOMIA recicla lalalala salda aaa 8 O aa 11 LO AN NN o 13 Block diagram temperature sensor cscscsssssssssssssssssssssssssssssssssssssesssssesssssssesscscscscscsesescseseseseaescacacassssssessseseseesseseseseseeesees 14 Characteristic curve of the temperature sensor ccccesesesesesesesesesssesssessssssssssssssesesesesesesesesesesesesesesesescsesescseacacacseaeeeees 14 Position of temperature Sensor cscsssssssssesesescsescsesesesesesesesssesssssssssssssssssseseseseseseseseseseseseseseseseaescacaeacaeseseseseseseseseseeeeeeeeseees 14 PosiHo ome Da ten nod a 15 Block daragrami Power and ROSEE IM Nooo oe 16 Position of buttons S8 SO sesessssssssssesssscsssssssscscscsesssssesscsescsssescsesescassesesscsesesssesecseseseassesecseseseassesecucseseassesecseseseacsesesseseaeass 17 Block diagram power supply aua RR 18 Block diagram power supply recommended for customer specificcarrierboard
36. MBa53 provides the following interfaces functions and user s interfaces I User s Manual STK MBa53 UM 100 2013 TQ Group Page 7 Table 3 Overview communication and supply interfaces Interface Section Number Type of connector Remark USB 2 0 HS Host USB receptacle type A Dual port receptacle right angle USB 2 0 HS OTG USB receptacle type Micro AB 4 2 1 4 2 2 RJ45 receptacle Receptacle with integrated magnetics CAN Aa Phoenix basic housing Vertical version RS232 MA HEN D Sub 9 pin connector Right angle Debug UART CRM ua Eu DVI receptacle type Right angle VGA and HDMI compatible LVDS 428 1 DF19 receptacle Hirose DF19 Right angle Audio Out 3 5 mm jack 1x Line out stereo 1 x Line in stereo 1 x Microphone mono 14 x GPIO 1 x USB 2 0 HS Host 1 x CSI 1 x UART 1 wire 2 x SPI Pin headers 4 2 13 Pin header 2 54 mm 2x1C SPDIF FIRI 1 x 4 wire touch 1 x parallel display interface LCD backlight control Optional WEIM bus e 33VDC e 5VDC Power OUT Table 68 1 Pin header 2 54 mm e 12VDC e 3x Power On Reset signals Battery holder CR2032 holder Backup battery RTC Table 4 Overview user s interfaces Interface Section Number Remark Diagnostic LEDs 4 x each for power supply Ethernet and USB KE A FonerOn nd esetuman laa u u O O Bootmodeconfowaion s a ET 03 00 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 8 4 ELECTRONICS SPECIFICATION 4 1
37. MM 49 Stimull DUHONS m s 51 Seat cis poe ei lolo ss cac e se te tee A 52 Configuration general i MX53 BoOt ParaMetel cscsssssessssssssssssssesscscsssssesesscscsesssssesescscsssssessesesesssesessesescaesssesseseseaesssessess 52 Configuration Boot Devices for internal BOOT eese essen ee terere ntes tete tt aenea tata tote te senes tates sese sensa ansa 53 E Uraa Me RID 55 Climatic and operational conditions ce eeesesessscssscssescscscscsessssssesesesesesesesesesssssseseseseseseseesesesesesesesesesseseseseseseseseseseseeecaeseeeees 58 Valeo ge 0 2 raz Holaa U1 a alc ql RE A tee enn ia a EAI ER P 60 ILLUSTRATION DIRECTORY Illustration 1 Illustration 2 Illustration 3 Illustration 4 Illustration 5 Illustration 6 Illustration 7 Illustration 8 Illustration 9 Illustration 10 Illustration 11 Illustration 12 Illustration 13 Illustration 14 Illustration 15 Illustration 16 Illustration 17 Illustration 18 Illustration 19 Illustration 20 Illustration 21 Illustration 22 Illustration 23 Illustration 24 Illustration 25 Illustration 26 Illustration 27 Illustration 28 Illustration 29 Illustration 30 Illustration 31 Illustration 32 Illustration 33 Illustration 34 Illustration 35 Illustration 36 Illustration 37 Illustration 38
38. NOAIN Powe o 42 DGND J X Power 43 NEAN ACA o 44 DGND Power o 45 MC Power 46 DGND Power NOAN Powe 48 DGND Power o 8 CCI Power 50 DGND Power SI VCCOV Powe 52 DGND Power MEA Power 4 DGND Power o 55 PWRON Reset 56 Do Power o 57 GBRSF jJRest o 58 DGN J Powe 59 RESETOUT o Ree Oo DGND A I User s Manual STK MBa53 UM 100 2013 TQ Group Page 49 4 3 Diagnostic and user interfaces 4 3 1 Diagnostic LEDs The STK MBa53 provides 12 Diagnostic LEDs to signal some conditions Table 69 Diagnostic LEDs Function Reference Colour Signal 12 V Power LED shines when 12 V supply is active 5 V Power LED shines when 5 V supply is active Power supply 3 3 V Power LED shines when 3 3 V supply is active Global Reset Power Good shines when the TOMa53 is not in reset and if low active signal GLBRST is not active Yellow Speed Indicator Ethernet 2 shines with 100 Mbit s transfer rate Ethernet does not shine with 10 Mbit s transfer rate LEDs in the RJ45 connector Link activity Ethernet 1 shines with valid link blinks with transfer Yellow Speed Indicator Ethernet 1 shines with 100 Mbit s transfer rate does not shine with 10 Mbit s transfer rate Table 7
39. O IN R 1 uF gt Additional ESD protection low active signal t element to VCC5V pull up y element to ground pull down gt element in series Table 57 Pin assignment audio connector X15 microphone Pin Pinname Signal Dir Remark a Goud ANDA UR 2A 2B MIC IN 100 nF gt 2 2 kO MIC BIAS additional ESD protection 3 AGND AUDIO 10 kO gt Not used only mono low active signal t element to VCC5V pull up y element to ground pull down gt element in series I User s Manual STK MBa53 UM 100 2013 TQ Group Page 41 4 2 10 SD card VCC3V3 Lot SD_DATI0 3 t SD_CMD SD_CLK 220 SD CD e SD WP m e Illustration 36 Block diagram SD card The SD card connector is directly routed to the SDHC controller of the TOMa53 All signals are equipped with an additional ESD protection near the card connector It is possible to boot from SD card see section 4 3 5 Boot Mode configuration Illustration 37 Position of SD card connector X6 Table 58 SD card connector X6 Manufacturer number Description SD MMC card connector 10 000 mating cycles Push Push latch 25 Cto 85 C Yamaichi FPS009 2405 0 Table 59 Pin assignment SD card connector X6 Pin Pin name Signal Dir Remark 1 DAT3 CS SDDAI3 NO 10k01 to VCC3V3 n a
40. R FEC INT 4 INT FEC REF CLK lt a e be Illustration 15 Block diagram Ethernet 1 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 22 The operation mode of the LAN8720A is preconfigured with MODE 2 0 111 all capable Other configurations can be set by placement options Table 25 LAN8720A modes MODE 0 2 Function Remark 000 O 10BASET Half duplex autonegotiation off 001 Full duplex autonegotiation off Half duplex autonegotiation off Full duplex autonegotiation off Half duplex start autonegotiation on Repeater Mode Half duplex start autonegotiation on 111 AlLcapable No definitions autonegotiation on preset mode in hardware The RJ45 receptacle X11 provides 2 status LEDs as well as an integrated magnetics Illustration 16 Position of Ethernet connector X11 Table 26 Ethernet connector X11 Manufacturer number Description RJ45 receptacle Integrated magnetics 1 5 kV RMS min LEDs green and yellow 0 C to 70 C 750 mating cycles Pulse J0011D21BNL Table 27 Pin assignment RJ45 receptacle X11 Ethernet 1 Signal Dir Remark ETH1_TXN es ETH1_RXP Se Not used Al 12 LED1 anode VCC3V3A_ETH1 MEN Link Activity green shines with available K1 11 LED1 cathode INTSEL 270 0 gt connection blinks with transfer A2 9 LED2 anode REGOFF NES Speed Indicator yellow shines with K2 10 LED2 cathode DGND 270 Q g
41. STK MBa53 UM 100 28 03 2013 User s Manual STK MBa53 UM 100 2013 TQ Group Page i TABLE OF CONTENTS 1 ABOUT THIS MANUAL sssssssscesssssssscscessscsesssscessssescsesscucscsescsesecscsesesesesucscsssesesesecscscsesesesscscucsesesesecscucscsesesesscucscsesesesecucscsesesesscseseseaseseees 1 1 1 Ei OP TTTTITPITITIRIRIRIEEEEEREEREEEIUE 1 1 2 Copyright and licence expenses cssssscsssssssssssssscsssssssssssssssssssssssssssssssssssssssssssscscsesescscscsescseseseseseacacssacacacacaeaenesesssesssesesesesesesesesesesseseees 1 1 3 Bagistered e e ts 1 1 4 DE TAASI GN 1 1 5 LAA a a aaa aa aka kk Oo II 1 1 6 Lo e o 1 1 7 e amci oral ONA EOS TTT eT tn sete ee Tr 2 1 8 Eta cil ACL ze EZ P S 2 1 9 NENA 3 1 10 Further applicable documents presumed knowledge cssesssssececscscscscscssssscscscsssssssssssssssssessssssseseseseseseseseseseescscsesesescscsescsescacacas 3 1 11 Acronyms and definitions ecesessssssssssssssscscsesesssecscscsessssscscsesssssesscsesescassesseseseseassesscseseseassesscseseseacsesscseseseacsssesseseseacsesesseseseaeassesecseseaeaesees 4 2 BRIEF DES CRIE TIO ie M 6 3 TEEFINIEAL A ai 6 3 1 System architecture and functionality see ssesssesseessesseessesseessesseessesseoseesseoseressesseeoseoseesseoseeoseosseoseossroseesseoseesseoseeoseoseeoseossesseossesseesseo
42. System components 4 1 1 Processor module DDR3 SDRAM eMMC EEPROM CANA DISP1 Temperature WEIM Sensor Illustration 2 Block diagram TQMa53 The main components of the processor module TOMa53 are the i MX53 CPU DDR3 SDRAM and eMMC memory The technical characteristics of the TOMa53 are to be taken from the User s a Manual The available signals are routed over the two 120 pin module connectors X1 and X2 to the STK MBa53 Table 7 and Table 8 show the pins assignment of the connectors as well as signal names and directions seen from the TOMa53 The boot mode configuration of the i MX53 is set via DIP switches See section 4 3 5 Boot Mode configuration The TOMa53 can be plugged put on mating connectors of different stack height on the carrier board In this way different board to board distances can be achieved which are shown in Table 5 Table 5 Possible mating connectors on the carrier board Manufacturer number Contact Plating Board to board distance tyco 5177986 5 0 2 um Gold na Oo 0764mGod mm tyco 6123001 5 Table 6 TOMa53 and module connector Manufacturer number Description Package CPU module with Freescale MX53 2 GiB eMMC flash TQ Systems TQMa53 512 MiB DDR3 SDRAM 800 MHz CPU frequency
43. able 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 User s Manual STK MBa53 UM 100 2013 TQ Group Page iii Terms and CONVENTIONS scssscsssssssssescscscscsessscsssssssssssssssssssssssssssssssssscscscsssesescscscsescseseseseseseseseseseacacacacacacaesesesesesssssesesesesesesesesecesees 2 ATOY eee e eee eee eee eee e eee 4 Overview communication and supply INTEPFACES cesesesscscsssssscesscscsssssssscscssssssssscsescsssssesscscseassesessescsesessseseeseseassesesseseseass 7 Overview user s interfaces csessssssssssssscscssssssccscscsesssessescscsssssessesescassesscsesessassesscseseseassesscseseseassesscseseseassesesscseseacsesecseseseacsesesseseaeass 7 Possible mating connectors on the carrier board eese ettet tn tatnen tatnen tata tata tasa tasa snas tonus 8 1OMaso ana mod lle eco BIB TS Leo PT 8 Pin assignment module connector X1 scsssssssssssssssssssssssssssssssssssssssssssssscscsescsescsescsescsescsescssacscssasasassesssssssssesssesesesesesessseseeeeeeees 9 Pin assignment module connector X2 csssssesssssssssssssssssssssssesssscssssscscsccscscsesesesesesesesesesesessssssssssssesssssseseseseseseeesesseeessseeseseeees 10 IC address DPD NNMERO 11 e dr in my 3 DUS maal laaan
44. additional ESD protection 2 CMD DAAN SDCMD 1O 10KOtto VCC3V3 additional ESD protection E wo PE aD ees sak i oaken 006 VR OND a EE NN S EMEN WP MICA 3 10k01 to VCC3V3 n a additional ESD protection SD DATI 10 kO1 to VCC3V3 n a additional ESD protection DATO DATA OUT SD DATO DAT2 SD DAT2 1 2 3 4 5 7 we co GND COMMON be a O EA Ma A P low active signal t element to VCC5V pull up y element to ground pull down gt element in series I User s Manual STK MBa53 UM 100 2013 TQ Group Page 42 4 2 11 SATA PEE 10 nF SATA TXP Ion SATA_TXM ze ae 10 nF SATA RXP Ion SATA_RXM Illustration 38 Block diagram SATA Interface The SATA interface of the TQMa53 is capacitive coupled 10 nF to a 7 pin SATA connector The SATA device must be supplied separately e g over the Power Out header X20 All four data lines have an ESD protection It is possible to boot from SATA see section 4 3 5 Boot Mode configuration The SATA interface provides the following core functionalities e Compatible with Serial ATA 2 6 AHCI Revision 1 3 and AMBA 2 0 ARM e Datarate of 1 5 Gbit s C g an ann pes s s m pom m m T NS gm SU tE ZEE MERRE j 120 119 Rie 15 el 1 as om Illustration 39 Position of SATA connector X12 Table 60 SATA connector X12 Manufacturer number Description SATA connec
45. al security Due to the occurring voltages lt 30 V DC tests with respect to the operational and personal safety have not been carried out 6 4 Climatic and operational conditions In general reliable operation is given when the following conditions are met Table 76 Climatic and operational conditions Parameter Range Remark Permitted environmental temperature 0 C to 70 C Without Lithium battery CR2032 Permitted storage temperature 10 C to 60 C Permitted environmental temperature 0 C to 60 C With Lithium battery CR2032 Relative air humidity operation storing 10 to 90 6 5 Protection against external effects Protection class IPOO was defined for the STK MBa53 There is no protection against foreign objects touch or humidity 6 6 Reliability and service life No detailed MTBF calculation has been done for the STK MBa53 The STK MBa53 is designed to be insensitive to vibration and impact Middle grade connectors which guarantee at least 100 mating cycles were used for the STK MBa53 The connector for the LVDS interface guarantees 30 mating cycles Information to the mating cycles of the remaining connectors can be looked up in the corresponding paragraphs in section 4 6 7 Environment protection 6 7 1 RoHS compliance The STK MBa53 is manufactured RoHS compliant e All used components and assemblies are ROHS compliant e RoHS compliant soldering processes are used 6 7 2 WEEE regulation The company placi
46. aman bihi idino akl 12 Possible configurations of the I C addresses for the 1 0 xPaNdereicccssscssssssssssesessesssssssssssssssessetessesssssessesessseesssssssesssesses 12 Possible configurations of the I C addresses for the temperature sensor cccesssssssssssssssssssssssssessssesssssssesssessseessesessesses 12 Configurator INTE signal u ii 13 Electric characteristics of the temperature sensor LM75A csssssssssssssssesssesesesesesescsescsesesesesesesesesesessseseeeesesesesesesesesesesesees 14 Electrical parameters of the RTC backup SUPDIY csesesssscsssssssesscscsssssssessescscsssssesescsssssssecsescsssssesessesesesesesecseseassesesseseseass 15 Batory ana Date Noia 15 Resets on the EAA NE EEE AMR 16 Electrical parameters PGOOD SMS III ie 17 Power and Reset Buttons 58 A as 17 Electrical parameters of the protective C rCUit ssessessesseseeseesseesessessesseoseeseesesssesseeseeseeseeseesetetusesstsstoseoseoseseeseeeeseeseeseessess 19 Electrical parameters VIN VCC12V uu sesssssssssssssssssssssssssssssesesesssssssscssscsscscssscsesescsesesesescsssesssssssssssesssesessssssssassesesesssscscseacecscaes 19 Electical parameters AB ol PR E 20 CARNES AA 20 Power supply connectors X8 X21 cscsssssssssssssssssssssssssssssssssssssssssssssccscscscscsescscsesesesesesesesesesssssessssssssseseseseseseseseseeseceeseseseseseaees 21 LADISZ ZORUBOUS AECI o A ME 22 Ethernet connector X1 REN 22 Pin assignment RJ45 receptacle X11 Ethernet 1
47. ameters of the RTC backup supply Parameter Min Typ Max Unit Remark Bridging period 21 42 Years 3 of the batteries energy is available 682 ia css RTE coa Mi E CST ROS C188 R 81 1g V23 Illustration 8 Position of battery holder Table 16 Battery and battery holder Manufacturer number Description e Lithium battery 3 0 V e 20mm diameter e 220mAh e 30 Cto 60 C e CR2032 battery holder MPD BU2032SM JJ GTR 40 C to 280 C Sony CR2032 gt See 1 TQMa53 User s Manual User s Manual STK MBa53 UM 100 2013 TQ Group Page 16 4 1 6 Power and Reset VCC3V3 10 ko 10 ko RESET OUT e RESET RST PWRON RESET_IN Illustration 9 Block diagram Power and Reset There are several different possibilities to trigger a reset on the STK MBa53 which are shown in the following table Table 17 Resets on the TQMa53 Reset Signal Description Trigger RESET_IN Ena ee NDS cru JTAG device at JTAG interface pin header X17 on the TQMa53 Keystroke at S9 PWRON e On switch for PMIC on TOMa53 y e Pull down to GND at pin header X17 see Table 68 is performed GLBRSTTMR 1 0 e Generates complete restart of the PMIC e VCC3V3 and VCC5V switching regulator GLBRSTA on the TOMa53 e g voltage drop at Vin or overload e A Power down and Power up cycle e Long keystroke at S8 according
48. boot from the eMMC assembled on the TOMa53 is highlighted in red in Table 73 and Table 74 This configuration is set in the eFuses on the TQMa53 by default User s Manual STK MBa53 UM 100 2013 TQ Group Page 54 s EEE sep BEEe p TTITEETETTETTEETTITITETEEEETETTEETTTITETEIEEEEEEIET 11 2 HHE 112 T T Em ENE 7 A7 Sr ge 8 epee DV Illustration 49 Position of DIP switch S1 sce En Riga R13 MAR Illustration 50 Position of DIP switches S2 S3 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 55 4 3 6 Buzzer VCC5V Un L e 10 kQ L 12C2_SCL 12C2_SDA Illustration 51 Block diagram buzzer The STK MBa53 provides a buzzer for acoustic signals The buzzer is controlled by P2 of the l C port expander PCA9554 Table 75 Buzzer Manufacturer number Description Buzzer 5 V typ 30 mA max PUI Audio SMI 1324 TW 5V 2 R Resonant frequency 2 400 400 Hz SPL 88 dBA 100 mm min 40 C to 85 C Illustration 52 Position of buzzer 5 2 User s Manual STK MBa53 UM 100 2013 TQ Group MECHANICS SPECIFICATION General notes e The STK MBa53 is assembled on one side with SMD and THD components e High pin count SMD connectors with 0 8 mm pitch Dimensions e Dimensions 170 mm x 170 mm each 0 2 mm see Illustration 54 e Height Minimum 22 4 mm e Mounting holes 6 holes with 4
49. e 74 Boot from eFuses On the TOMa53 active by default 10k01 at BOOT_MODE1 10 kO at BOOT_MODEO Serial Downloader Download program image over USB_OTG or UART2 low active signal t element to VCC5V pull up y element to ground pull down gt element in series Pad name MX53 Configuration Remark 00 Internal Boot 01 Reserved BOOT_MODEO 10 Boot from eFuses 11 Serial Downloader After start up the boot code initializes the hardware and then loads the program image from the selected boot device The STK MBa53 supports the following boot devices e eMMC e SD MMC card e SATAHDD e Serial ROM over ESPI In the boot mode Internal Boot BOOT_MODE 1 0 00 the boot device and its configuration is selected by a combination of eFuses and or GPIO pins The exact behaviour during booting depends on the value of the register BT_FUSE_SEL default 0 e BT_FUSE_SEL 1 All boot options are set exclusively by the values of the eFuses e BI FUSE SEL 0 The values in the eFuses can be overwritten by GPIO pins for different boot options On the TOMa53 the boot mode is set to Boot from Fuses BOOT_MODE 1 0 10 with a resistor combination by default The GPIOs and their function is shown in Table 72 and Table 74 The listed pins are not preconfigured with a defined level on the TOMa53 Table 73 Configuration general i MX53 Boot Parameter DIP switch 1 On 0 Off BOOT_CFG1 1 O ARM frequency 800 MHz
50. e CANH dominant high Output voltage CANL dominant high Output voltage CANH CANL recessive Without load Without load The interfaces CAN1 and CAN2 can be terminated with DIP switches S10 1 S10 2 The configuration of the DIP switches is shown in the following table Table 35 Settings of DIP switches for CAN1 CAN2 termination Switch Interface Position On Position Off S10 1 CAN1 CANI terminated with 120 O CANT not terminated S10 2 CAN2 CAN2 terminated with 120 O CAN2 not terminated I User s Manual STK MBa53 UM 100 2013 TQ Group Page 28 Illustration 22 Position of S10 4 2 4 Galvanic separation The characteristics of the galvanic separation are shown in Table 36 Table 36 Characteristics of the galvanic separation for CAN1 and CAN2 Parameter I User s Manual STK MBa53 UM 100 2013 TQ Group Page 29 4 2 4 2 Connectors and pin assignment Pin X3 1 Pin X4 1 Illustration 23 Position of pin headers X3 X4 Table 37 Pin headers X3 X4 Manufacturer number Description 3 pin header 160V 8A Pitch 3 5 mm 40 C to 100 C Phoenix Contact MCV 1 5 3 G 3 5 Table 38 Pin assignment CAN1 CAN2 connector X3 X4 Pin Pin name signal Dir Remark X3 1 CAN1_H I O CAN High Level I O galvanically separated X2 2 CAN1_L I O CAN Low Level I O galvanically separated I User s Manual STK MBa53 UM 100 2013 TQ Group Pa
51. eaders X19 and Power OUT X20 30 VCC3V3 LVDS P 10 uF 1 uF to DGND additional ferrite filters in series M Z DGN P low active signal t element to VCC5V pull up y element to ground pull down gt element in series la User s Manual STK MBa53 UM 100 2013 TQ Group Page 39 4 2 9 Audio To process audio input and output signals the audio codec SGTL5000 is provided It is connected to the TOMa53 over the interfaces lC and l S The RC bus 2 is used 1 uF 12S_DIN a IPS DOUT LINEIN L ue 125_DOUT gt 125_DIN LINEIN_R lt a 125_LRCLK gt 12S_LRCLK m 2S SCLK gt 125_SCLK LINEOUT_L n LINEOUT_R 00 I2S_MCLK 330 gt SYS MCLK n a HP_L 00 e HP R 00 n a 100 nF I2C2_SCL gt CTRL CLK MIC I2C2_SDA 4 gt CTRL DATA MIC BIAS 4 2 2k0 Illustration 34 Block diagram audio The SGTL5000 provides a stereo line in stereo line out a microphone input as well as an amplified headphone output The headphone output is however not available on the STK MBa53 by default It can be enabled at X13 by placement option The necessary configurations are shown in Table 52 The audio interfaces are provided at three 3 5 mm jacks X13 X15 The basic electric characteristics are shown in Table 53
52. esesesesessssssesesesesesesessesssesesesesesesescsesesesesesesesesesseseseaesesesesesesseseneaeas 30 D Sub 9 pin connector X1 sssesssssssescscscscsessssesesescscsesesesessssesesesesesesesesessesesesesesesesesssseseseseseseseseseesesesesesesesesesceseseaeseseseseseseeseneaeas 31 Pin assignment RS232 connector ge A ee EEUU IIIS 31 Configuration of the R 485 MOdES ssssssssssscscsssssssssscsesssssssssscsssssssssesscscssseseseesesesssssesecsesesssesesscseseseaesesecsesescassesessescaeasseseesees 31 Electhcal parameters ASAS eki S K S SIA RARA AAA 32 Settings of DIP switch S4 for RS485 uu esessssssssssssssscscssssssssescscsssssssesscscsssssesecscsesssssesecsesesesssesecsesescaesesussesescaeseseeseseseasssseseess 32 Characteristics of the galvanic separation for RS485 ou cssssssssssesesecscsssssesscscscsssssssssescsssssssessescscsssesesscsescasssseeseseseasseseesess 33 Pin headers connector QU RR 33 PUTAS os 33 P C O RT 35 Kisi A e DOE een ee ee sak e ak akk sak ee ke sa lk KLM 36 id le ga a A A A KA EN 38 Pin assignment LVDS header X17 scssssssssssssssssssssssssssssssssssssssssscscscscscscscsescsesesesescsesesesssesesssssssssssssssesesesesesesescesececsesesceeseaeaees 38 Configuration for headphone or line out uuu esesesesessssssssssssscscscsesssssecscsessseseseescsesssesescseseseseseseseseassesescseseseaesesesseseseasssseeeees 39 Electric characteristics of the audio interface uu eessssssesessssssssssssesscscssssssssssescscssssscse
53. fined xx0 1 Bit EIM EBO BOOT CFG2 7 l EIM_EB1 BOOT CFG2I6 darn 010 8 Bit Else not defined Bus width ioe DR Bus width MMC BOOT_CFG1 5 1 0 2 bytes 16 Bit EM DAO BOOT CFG2 5 110 8 Bit DDR 000 1 Bit Not defined SPI addressing 1 3 bytes 24 Bit Else not defined 001 4 Bit Else not defined EIM DA3 BOOT CFG2 2 EM DA4 BOOT CFG3I7 Not defined Not defined Not defined Not defined EM DA5 BOOT CFG3 6 5 EIM_DA6 BOOT CFG3IS 10 ESDHCV3 3 01 ESDHCV2 2 Not defined 00 ECSPI 1 EM DA7 BOOT _CFG3 4 Eon Selec Else not defined Pe Else not defined Not defined KO ee Else not definec 0 Boot ROM default S3 7 EM DA8 BOOT CFG3 3 DLL Override 1 Apply value per fuse Not defined 00 SSo field MMC_DLL_DLY 3 0 a 01 SS1 CS select 0 Boot Acknowledge 10 SS2 11 SS3 53 8 EM DA9 BOOT CFG3 2 Boot Acknowledge Disable Not defined Not defined E Not defined DIP switch 1 On 0 Off WN N Ui Boot Device Selection Un N i 0010 Boot from Hard Disk Else not defined 0011 Boot from Serial ROM Else not defined 52 Boot Device Selection Boot Device Selection 52 3 NIN UJ Ww W N 8 1 4 53 WN UJ Ui 0 Boot ROM default DLL Override 1 Apply value per fuse field MMC DLL DLY 3 0 enabled 1 Boot Acknowledge disabled EN EIM_DA10 BOOT_CFG3 1 Not defined The recommended default configuration to
54. ge 30 4 2 5 RS232 VCC3V3 d ER UART2 TXD i gt L RS232 TXD UART2 RXD RS232 RXD UART2_CTS o gt __RS232 RTS UART2_RTS RS232 CTS Illustration 24 Block diagram RS232 UART2 of the i MX53 is routed to the transceiver SP3222E which provides the signals as RS232 interface at a D Sub 9 pin connector according to the EIA TIA 232 F standard The UART2 handshake signals RTS and CTS are also available The UART2 interface is used as debug information output Further information e g default baud rate should be taken from the software specification Table 39 Electrical parameters RS232 Parameter Min Typ Max Unit Remark CT a CREME m melegim a m m OmpuviaeHgh A A Illustration 25 Position of D Sub 9 pin connector X1 User s Manual STK MBa53 UM 100 2013 TQ Group Page 31 Table 40 D Sub 9 pin connector X1 Manufacturer number Description Package D Sub connector 9 pin Right angle 55 C to 105 C Yamaichi DRA 09P11 ZN Table 41 Pin assignment RS232 connector X1 Signal ir Remark Galvanic 1200 separation 84 1 DI A RS485 A gt HCPL 0631 gt e gt DE B RS485_B e HCPL 0601 rad n RO Y a RS485 Y e n a R1S 0505 oa e REH Z a RS4
55. he TOMa53 la User s Manual STK MBa53 UM 100 2013 TQ Group Page 60 8 APPENDIX 8 1 References Table 77 Further applicable documents Date Company TOMa53 User s Manual Rev 0200 03 2013 TQ Systems GmbH i MX53 Multimedia Applications Processor Reference Manual Rev 2 1 06 2012 Serial ATA Specification Rev 1 0a Jan 2003 APT Technologies TQ Systems GmbH M hlstra e 2 Gut Delling 82229 Seefeld info tq group com www tq group com Technology in Quality
56. ine CAN Controller Area Network Card Detect DDR Dale Data Rate e Dale Package SCS ESD IN CA vo o ingress Proteo APD Input with Pull Down resistor IPU Input with Pull Up resistor la User s Manual STK MBa53 UM 100 2013 TQ Group Page 5 Table 2 Acronyms continued Acronym Meaning MMC Multimedia Card MMU Memory Management Unit MOSFET Metal Oxide Semiconductor Field Effect Transistor MSB Most Significant Bit Mean operating Time Between Failures ma Not Assembled Not Connected OOD Output with Open Drain PDO Pull Down resistor PHY Physical layer of the OSI model Pull Up resistor Restriction of the use of certain Hazardous Substances VGA Video Graphics Array 640 x 480 Widescreen Ultra Extended Graphics Array 1920 x 1200 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 6 2 BRIEF DESCRIPTION The STK MBa53 is designed to be used in combination with the TO module TOMa53 which is based on the Freescale ARM CPU MCIMX53 i MX53 Together with the module TOMa53 the STK MBa53 provides all basic functions and interfaces Together with the TOMa53 the STK MBa53 forms a modular system for developments of own products Unless otherwise stated this User s Manual refers to the TOMa53 revision 0200 3 TECHNICAL DATA 3 1 System architecture and functionality 3 11 Block diagram UARTI FIRI GPIOs 1 Wire ESPI SP
57. ion of pin headers 18 X19 X20 Table 65 Pin headers X18 X19 X20 Manufacturer number Description Header 2 54 mm pitch 2 x 30 pins gt 7 N retention force 40 C to 163 C Fischer Elektronik SL 22 124 60 G The following tables show the distribution of the function groups at the three pin headers la User s Manual STK MBa53 UM 100 2013 TQ Group Page 46 Table 66 Pin header X18 Remark 1 Alternative function WEIM bus Signal Interface TQMa53 Dir 2 Routed to DVI transmitter 3 Used for Boot Mode configuration CSIO CSIO CSIO CSIO 7 CSIO 10 CSIO 11 CSIO 12 CSIO 13 CSIO 14 CSIO 15 CSIO 16 CSIO 17 CSIO 18 CSIO 19 CSIO 20 CSIO 21 CSIO 22 CSIO 23 CSIO 24 CSIO 25 CSIO 26 CSIO 27 GPIO 28 CSIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 ESPI 43 DGND 44 ESPI MOSI 45 ESPI_SS1 46 ESPI_SS2 47 ESPI_SSO 48 FIRI_RXD 49 ESPI_SS3 50 FIRI_TXD 51 ESPI_SCLK 52 UART1_RXD 53 OWIRE 54 UART1_TXD 55 I2C3_SCL 56 SPDIF_OUT 57 I2C3_SDA 58 SPDIF_IN 59 DGND DGND I O I O I O I O I O I O I O I O I O I O I O I O I O I O 1 3 1 In addition as an interrupt signal of the I O expander usable Power ESPI ESPI ESPI ESPI FIRI ESPI FIRI ESPI UART1 1 wire UARTI 00 2C3 O Additionally used as on board bus SPDIF o 2C3 Additionally used as on board bus SPDIF LA I
58. l t element to VCC5V pull up y element to ground pull down gt element in series Imax 1 A per voltage minus the current drawn from pin header Power OUT and the LVDS connector N I User s Manual STK MBa53 UM 100 2013 TQ Group Page 48 Table 68 Pin header Power Out X20 Pin Signal Interface Dir Remark o 1 VOB Power 2 DGND Power o 3 VCGVS O Power 2 4 DGN Power o S5 EEV ooo Power 6 IDN IP o 7 NEE o O Power 8 DGN Power O Power 10 DGND Power VOB Powe 12 DGND Power 13 VCGV3 0 Power 4 DGND Power VOB Power 16 DGND y Power 17 e VE Powe 18 DGN Power 19 VCCSV Power 20 DGND Power 2 VCCV Powe 2 DGND Power 3 VCCV Power 24 DGND Power gt VCCV Power 26 BN 1 1 Power A per voltage AA Power minus the current drawn at pin header X19 28 DGND Power ndattheLVDS connector 29 VCCSV Power 30 DGND Power o 3 VCCV Power 32 DGND Power o 3 VCCV Power 34 DGND Power 2 3 VCCV Power 36 DGND Power 2 37 CAN Power 38 DGND o n Power 3 MCV Power 40 DGND J Power 4
59. n SEI ec mz A snis Bl 2 MAD Fa 5 Im ra com o o s etg a np E ee ce ASES i mi uin p mar Riad 0447 li BG C eio m E SEP ET i 2002 Rey EEE ow pasa be 9998 aay St Some BOAR 8 AH 10 EN EN Oggy IA A t Illustration 55 Component placement top Page 57 xs x4 la User s Manual STK MBa53 UM 100 2013 TQ Group Page 58 6 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 6 1 EMC Because the STK MBa53 is a development platform no EMC specific tests have been carried out During the development of the STK MBa53 the following standard was taken into account EMC Interference radiation Measurement of the electrically radiated emission for standard residential commercial and light industrial environments in the range of 30 MHz to 1 GHz according to DIN EN 55022 A1 2007 6 2 ESD Most of the interfaces on the STK MBa53 are protected against electrostatic discharge13 The interfaces which provide an ESD protection is described in the corresponding paragraphs in section 4 Following measures are recommended for a baseboard e Generally applicable Shielding of the inputs shielding connected well to ground housing on both ends e Supply voltages Protection by suppressor diode s e Slow signal lines RC filtering perhaps Zener diode s e Fastsignal lines Integrated protective devices suppressor diode arrays 6 3 Operational safety and person
60. nal data line filter in series LE pull down gt element in series Hot Plug Detect TMDS Data0 5 Shield TMDS Clock Shield C5a b Analog Ground low active signal t element to VCC5V pull up y element to ground n c Y TMDSDats2 E 2 TMDSDataze E 3 TMDS Data2 4 Shield ES mospa ES 8 TMDSDsoer ES 6 DDCClock KA 7 DDCData 0 vo 8 Analogvsync Em 9 TMDSDatsi ER 10 TMDSDatate r1 M TMDS Datat 3 Shield EZ 2 TMDSData3 ES 03 TMDSDatas E M qesvPower 0 LP 15 Ground EN 16 HotPlugDetect E 17 TMDSDatao o 18 TMDSDatsOr E 19 TMDSDatao 5 Shield La 30 TMDSDatas ER X TMDSDatas ES 22 TMDSClockShield _ EN 3 TMDSClock EZ M TMDSClock E Ch AnalogRed LR C AnalogGreen E C AnalogBlue E C4 AmbegHsnc E Cwb AnalogGround E ICM E EA I User s Manual STK MBa53 UM 100 2013 TQ Group Page 37 4 2 8 LVDS Both LVDS interfaces of the TOMa53 one pair of clock signals and four pair of data signals each are routed directly to the 30 pin female connector X17 In addition to the LVDS signals 3 3 V and 5 V are provided at the connector The current drawn from this connector including the current drawn from header X19 and Power out X20 may not exceed 1 A for each voltage The STK MBa53 was qualified with the AUO display G
61. nenennenenenenenennenenenenennnenenenenenennenenenenennnnen 52 Poton O LDIF WI So 54 POOTO DIP ite ges RO 54 BLOCK Ol e ero ir AA o y Sr en 55 Position OF DOZENTEN 55 Height of STK MBa53 A X X XX 56 Dimension drawing Of STK MBa53 cccsssssssssscscsssssssscscscscsssssscsescscsssssessescsesesesessesesesssesesscsesesesesesecseseassesececseseacseseseeseaeass 56 Component pla co Men Oia 57 Vi User s Manual STK MBa53 UM 100 2013 TQ Group Page vi REVISION HISTORY Rev Date Name Pos Modification 28 03 2013 Pez Document created la User s Manual STK MBa53 UM 100 2013 TQ Group Page 1 1 ABOUT THIS MANUAL 1 1 Copyright Copyright protected 2013 by TQ Systems GmbH This User s Manual may not be copied reproduced translated changed or distributed completely or partially in electronic machine readable or in any other form without the written consent of TQ Systems GmbH 1 2 Copyright and licence expenses The drivers and utilities for the used components as well as the BIOS are subject to the copyrights of the respective manufacturers The licence conditions of the respective manufacturer are to be adhered to Bootloader licence expenses are paid by TQ Systems GmbH and are included in the price Licence expenses for the operating system and applications are not taken into consideration and must be separately calculated declared 1
62. ng the product on the market is responsible for the observance of the WEEE regulation To be able to reuse the product it is produced in such a way a modular construction that it can be easily repaired and disassembled They JTAG interface is protected against ESD I User s Manual STK MBa53 UM 100 2013 TQ Group Page 59 6 7 3 Batteries 6 7 3 1 General notes Due to technical reasons a battery is necessary for this product Batteries containing mercury Hg cadmium Cd or lead Pb are not used To allow a separate disposal batteries are generally only mounted in sockets 6 7 3 2 Lithium batteries The requirements concerning special provision 188 of the ADR section 3 3 are complied with for Lithium batteries There is therefore no classification as dangerous goods e Basic lithium content per cell not more than 1 g except for lithium ion and lithium polymer cells for which a lithium content of not more than 1 5 g per cell applies equals 5 Ah e Basic lithium content per battery not more than 2 g except for lithium ion batteries for which a lithium content of not more than 8 g per cell applies equals 26 Ah e Lithium cells and batteries are examined according to UN document ST SG AC 10 1 e During transport a short circuit or discharging of the socketed lithium battery is prevented by extricable insulating foils or by other suitable insulating measures 6 8 Other entries By environmentally friendly p
63. oad step change lout 0 A to 1 9 A Temporary drop of VCC3V3 Control time E EN E ae BES wur E lon 2 1 A er zz MEME 5 eA 0000 User s Manual STK MBa53 UM 100 2013 TQ Group Page 21 4 1 7 2 Connector and pin assignment Illustration 14 Position of power supply connectors X8 X21 Table 24 Power supply connectors X8 X21 Manufacturer number Description DC jack 2 5 mm 5 5 mm Right angle CUI INC PJ 102BH Nominal values 5 A 24 V 5 000 mating cycles 25 C to 85 C Screw terminal 5 mm Nominal values 15 A 240 V AC Max cable cross section 2 5 mm 25 Cto 100 C Lumberg KRM2 4 2 Communication and supply interfaces 4 2 1 Ethernet 1 The following illustration shows the wiring of the Ethernet 1 interface It is designed as a 100Base TX interface and corresponds to the IEEE 802 3 standard The PHY used provides an Auto MDI X detection The maximum cable length at 100 Mbit s is 100 m An oscillator is provided as a clock generator for the LAN8720 CLKIN and the signal FEC_REF_CLK of the TQMa53 VCC3V3 A 9 g g e e e FEC_MDIO a gt gt MDIO FEC MDC MDC a FEC_TXD O 1 gt TXDIO 1 FEC_TX_EN gt TXEN FEC RXDJO 1 a e RXD MODE O 1 FEC RX DV 4 e CRS_DV MODE2 FEC RX ER lt q RXE
64. pull ups have to be provided however gt The pin headers X18 and X19 as well as the DVI receptacle X5 are described in sections 4 2 13 or 4 2 7 la User s Manual STK MBa53 UM 100 2013 TQ Group Page 13 4 1 3 I O extension GPIOs are required for some communication interfaces e g DVI to read status signals or to display control signals A GPIO port expander PCA9554 which is connected to I C bus I C2 is provided on the STK MBa53 for this purpose The IC address can be configured see Table 9 in section 4 1 2 lC address mapping VCC3V3 10 ko m gt na Il2C2 SCL Bo I2C2 SDA gt GPIO5 GPIOO oo Fe Illustration 4 Block diagram I O extension To detect events using an interrupt the INT output of the expander can optionally be used over GPIO5 GPIOO Table 13 shows the placement option Table 13 Configuration INT signal Mode R140 R180 Remark INT available 10 kQ GPIO5 GPIOO is additionally INT not available na Ona available at header X18 User s Manual STK MBa53 UM 100 2013 TQ Group Page 14 4 1 4 Temperature sensor pea sel 2C2_SDA q Illustration 5 Block diagram temperature sensor As with the TQMa53 a temperature sensor is also provided on the STK MBa53 The same sensor as on the TOMa53 is used It is connected to the same l C bus lC2 The sensor on the STK MBa
65. rocesses production equipment and products we contribute to the protection of our environment The energy consumption of this subassembly is minimised by suitable measures Printed pc boards are delivered in reusable packaging Modules and devices are delivered in an outer packaging of paper cardboard or other recyclable material Due to the fact that at the moment there is still no technical equivalent alternative for printed circuit boards with bromine containing flame protection FR4 material such printed circuit boards are still used No use of PCB containing capacitors and transformers polychlorinated biphenyls These points are an essential part of the following laws e The law to encourage the circular flow economy and assurance of the environmentally acceptable removal of waste as at 27 9 94 source of information BGBI 1994 2705 e Regulation with respect to the utilization and proof of removal as at 1 9 96 source of information BGBI 1996 1382 1997 2860 e Regulation with respect to the avoidance and utilization of packaging waste as at 21 8 98 source of information BGBI 1998 2379 e Regulation with respect to the European Waste Directory as at 1 12 01 source of information BGBI 2001 3379 This information is to be seen as notes Tests or certifications were not carried out in this respect 7 SOFTWARE No software is required for the STK MBa53 More information can be found in the Support Wiki for t
66. seasseseesees 58 6 1 es 58 6 2 a 58 6 3 Operational safety and personalseauniy an s u 58 6 4 Climatic and operational CONCITIONS ceeessssecssssescscscsssessssesescsesescsessssssesssssesescsesesesessescseseseseseeseseseaeseseseseseeseseaeseseseseseeeeseseacseseseees 58 6 5 Protection against external effects cecsssssssesesscsssssssssesscsssssssssssescsesssssesescsssssssessesesssssesssesesssesesecseseasassesseseasscaesesseasaeaeseseseeseseaeaesees 58 6 6 Keliability and Service TITG aco cito IHE ERR M AM VRARMERE MAR VEA RRRE MAD a ARMAR ULLA GAB AR AR UA GARA A RA 58 6 7 do mac da PP dada 58 6 7 1 e OU fs B a Pec ee EEE IE 58 6 7 2 WEEE regulation cccscscsssssssssssssssssssssssssssssssssssssesssesesesssscsesescscsescsesesesesesesesescseneacacacassesssssssssesssssssssssssssscsescsessscssscsesescseseseacscaeaeaeacacacaeasasees 58 6 7 3 Sots i LI II eee pr 59 6 7 3 1 General NOtes t M 59 6 7 3 2 Ee SUPA DA USS f PP 59 6 8 OTHER Rid RE EMEK AYYY RE 59 7 SOFTWARE OI PIU 59 8 ARRENDAR 60 8 1 A Ie E E E A 60 TABLE DIRECTORY Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 T
67. sees 6 3 1 1 n Pl PIS 6 3 1 2 PPP OOO OOOO M 6 4 ELECTRONES 2 81 110 cc cscs ccm cmv eae M 8 4 1 O ees 8 4 1 1 PROCESSOR PP A An 8 4 1 2 E o os TE MU mi 11 4 1 3 AS o PA 13 4 1 4 o cana m eT te ee ee ai 14 4 1 5 o PR PA 15 4 1 6 Edel INCL BOSE ERRONEO 16 4 1 7 Power g1 8 o 18 4 1 7 1 Electrical parameters switching rEQUIATON ccsssssssscssssssssssesssssssssssssssesssssssesesscscscscscscscscsescscsescscssasacseasssacaesesesesesesesesesesesesesesesesees 20 4 1 7 2 Connector and Me pre kei e ina AIR A o 21 4 2 Communication and SUPPIY ML A ES ae 21 4 2 1 o EE e e e a ann 21 4 2 2 Ethernet 2 USB 2 0 Hi Speed HOSt ssssssssssssssssssssssssssssssssssssssssssssssesesesssesssssscscscsesescscscscsesesesescasscacasacasasaensaesensseseseseseseseseseeseseesees 23 4 2 3 USB 2 0 Hi Speed OTG ss sssessesssessesssesseessesseesseesseoseesseossesseoseeuseossroseossreseesseoseesstoseeeseesseoseessreseeseossesreosseeseosseeseessroseesseeseesreoseeeseessesseessreseess 26 4 2 4 CNI amp mre 27 4 2 4 1 Galvante separa 28 4 2 4 2 Connectors and Pin ass O as 29 4 2 5 Ue nn 30 4 2 6 RSABS RIEN 31 4 2 7 B 34 4 2 8 APR e o O ccc O CE 37 4 2 9 DU PR 39 4 2 10 A
68. sesssesesscscseseassesecseseacassesecscseassesesecseseass 39 TAS quoq 40 Pin assignment audio connector X13 line out headphone eee eee ee sete esterne terere tt tees neneninins 40 Pin assignment audio connector X14 line in uu eesesesesesesssscsssccscscscscscscscsescsesescsescscsssssssssssssssssssssssesesesssecsessscsesescecscacaees 40 Pin assignment audio connector X15 MICFOPNONA eesssssssssssssssscsccscscscscscscsesssesssssesssssssssssssesesesesesesseeesceceescsceeseseaees 40 PU IS a TOS CO RA EMEN 41 Pin assignmeni SD card EO NES RS anne dl 41 TABLE DIRECTORY continued Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 User s Manual STK MBa53 UM 100 2013 TQ Group Page iv Ohi OO ENN aio db 2 42 FindssianinemtsAJq A CODPnectol geal e AMA PO APO psa uam 42 High and Low level for 2 775V signals of the JTAG interface esee esee ee tette tnte ento tentato tonta toten en estote 43 E e a AAA AAA AAA AE EEEE NEEE 44 FUE VSS PUM G ee o A oy nk 44 AA 45 melanie lake y dl PA 46 A m NEE EEE NEE ERESEREKENESEBESEIEKERETEBESEREIKEEENEERERRR 47 Pin Dealer ONEM Alesana 48 Ono U TED ee ee eee eee 49 DI3Snostc LEDS ode mai m RR md ma E MEE MEME
69. t MEN 100 Mbit s does not shine with 10 Mbit s low active signal t element to VCC5V pull up y element to ground pull down gt element in series I User s Manual STK MBa53 UM 100 2013 TQ Group Page 23 4 2 2 Ethernet 2 USB 2 0 Hi Speed Host A USB hub with integrated Ethernet controller provides three USB 2 0 Hi Speed host interfaces as well as the second Ethernet interface The hub has an upstream USB port four downstream USB ports and an Ethernet interface The wiring is based on the reference schematic of the LAN9514 The 5 V host voltage is activated and the current is monitored in each case with the power distribution switches for the USB 2 0 hosts In case of an overload and or excessive heat they switch off the host voltage The LAN9514 is clocked by an external 25 MHz oscillator USB host 1 and 2 are routed to the dual port USB receptacle X9 USB host 3 is routed on header X19 The RJ45 receptacle X10 provides two status LEDs as well as an integrated magnetics VCC5V VCC3V3 A A a 8 TQMa53 T LAN9514 USB H1 DN gt USBDMO USBDP2
70. t during operation This is especially important when switching on changing jumper settings or connecting other devices without ensuring beforehand that the power supply of the system has been switched off Violation of this guideline may result in damage destruction of the module and be dangerous to your health Improper handling of your TO product would render the guarantee invalid Proper ESD handling The electronic components of your TO product are sensitive to electrostatic discharge ESD Always wear antistatic clothing use ESD safe tools packing materials etc and operate your TO product in an ESD safe environment Especially when you switch modules on change jumper settings or connect other devices la User s Manual STK MBa53 UM 100 2013 TQ Group Page 3 1 9 Naming of signals A hash mark at the end of the signal name indicates a low active signal Example RESET If a signal can switch between two functions and if this is noted in the name of the signal the low active function is marked with a hash mark and shown at the end Example C Ds If a signal has multiple functions the individual functions are separated by slashes when they are important for the wiring The identification of the individual functions follows the above conventions Example WE2 OE 1 10 Further applicable documents presumed knowledge Specifications and manual of the used modules These documents describe the
71. to ground pull down gt element in series M1 6 Em L1 NM la User s Manual STK MBa53 UM 100 2013 TQ Group Page 27 4 2 4 CAN1 CAN2 Galvanic separation Em HCPL 0601 CAN1_TX CAN1 RX CAN2 TX HCPL 0601 CAN2_RX ei HCPL 0601 R2S 0505 Illustration 21 Block diagram CAN1 CAN2 Both CAN interfaces of the STK MBa53 are directly connected to the CAN ports of the TQMa53 They are available at the 3 pin plug connectors X3 and X4 Both interfaces are galvanically separated from the rest of the circuitry The two CAN interfaces are however not galvanically separated from each other The high speed mode is configured at the input Rs of the CAN transceivers MCP2551 by default R24 configures CAN1 and R30 configures CAN2 The two 390 O resistors to ground ensure maximum slew rate The high speed mode supports data rates of up to 1 Mbit s or maximum cable lengths To reduce the slew rate the resistance at Rs can be increased 10 kO to 120 kQ if required The CAN signals can be terminated with 120 O using DIP switches S10 1 and S10 2 More information can be found in the following section Table 34 Electrical parameter CAN1 CAN2 Parameter in Max Unit Remark Transfer rate Line length 10 Mbaud Line length 500 kbaud Output voltag
72. ton The push buttons Power On and Reset are described in section 4 1 6 Power and Reset 4 3 4 CANT CAN2 RS485 termination The termination of the CAN1 CAN2 and RS485 interfaces is described in section 4 2 4 CAN1 CAN2 or section 4 2 6 RS485 I User s Manual STK MBa53 UM 100 2013 TQ Group Page 52 4 3 5 Boot Mode configuration TQMa53 N BOOT_MODE1 DIP switch Boot BOOT MODO jH gt Mode Es 1 NEN DR DISPI CLK DIP switch GPIO2 GPIO27 e T gt General Boot DISP1_DAT8 4 DISP1_DAT7 Ji DISP1_DAT17 ke DISP1_DAT16 Boot DISP1_DAT15 4 gt Devices DISP1 DAT14 lt ____ DISP1 DAT13 4 DIP switch DISP1 DAT11 lt DISP1 DAT10 DISP1 DAT9 e DISP1 DAT3 DISP1 DAT2 e DISP1 DAT1 DISP1 DATO S3 P4 Illustration 48 Configuring the boot loader with DIP switches S1 S2 S3 The i MX53 provides a ROM with integrated boot loader which can be configured with the pins BOOT_MODE 1 0 The supported boot modes which can be configured with DIP switch S1 are shown in the following table Table 72 Configuration Boot Mode DIP switch 1 On 0 Off Internal Boot see Tabl
73. tor 7 pin Vertical version Corresponds to SATA specification 40 C to 85 C 3M 5607 5102 SH Table 61 Pin assignment SATA connector X12 Pin name Signal ir Remark ER ccc B Bao SATA_RX 10 nF gt Additional ESD protection low active signal t element to VCC5V pull up y element to ground pull down gt element in series 1 See 2 i MX53 multimedia Applications Processor Reference Manual 12 No FIS switching la User s Manual STK MBa53 UM 100 2013 TQ Group Page 43 4 2 12 JTAG VCC3V3 Imax 10 mA VCC 2V775 JTAG_VREF JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK JTAG_TRST RESET_IN Illustration 40 Block diagram JTAG The JTAG interface is routed to the 20 pin header X7 The pull up and pull down resistors for the signals TDI TMS TRST and TCK are assembled on the TOMa53 The reference of 2 775 V provided by the TOMa53 is used as I O voltage This causes deviant high and low levels for the corresponding signals see Table 62 Table 62 High and Low level for 2 775V signals of the JTAG interface Parameter Min The reference voltage VCC 2V775 may not be used as a supply voltage VCC3V3 is also routed to the pin header The maximum load is 10 mA The JTAG interface on the STK MBa53 has no ESD protection TTD Pin 1 i ss 2 mia pm E EN J i Illustration 41 Position of pin header X7 User s Manual

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