FMC116/FMC112 User Manual
Contents
1. LAO1_N_CC D9 DCO_N lt 1 gt HAOS_N E7 N C HBOS_N E25 N C LA01_P_CC D8 DCO_P lt 1 gt HAOS_P E6 N C HBOS_P E24 N C LA02_N H8 OUTA_N lt 3 gt HA06_N K11 NC HBO6_N_CC K29 N C LA02_P H7 OUTA_P lt 3 gt HA06_P K10 NC HBO6_P_CC K28 N C LAO3_N G10 OUTB_N lt 3 gt HAO7_N J10 N C HBO7_N J28 N C LAO3_P G9 OUTB_P lt 3 gt HA07_P J9 N C HBO7_P J27 N C LAO4_N H11 OUTA_N lt 2 gt HAO8_N F11 NC HBO8_N F29 N C LAO4_P H10 OUTA_P lt 2 gt HAO P F10 N C HBO8_P F28 N C LAOS_N D12 OUTB_N lt 2 gt HA09_N E10 NC HBO9_N E28 N C LAOS_P D11 OUTB_P lt 2 gt HA09_P EQ N C HBO9_P E27 N C LAO6_N CG FRAME_N lt O gt HA10_N K14 N C HB10_N K32 N C LA06_P C10 FRAME_P lt 0 gt HA10_P K13 NC HB10_P K31 N C LAO7_N H14 OUTA_N lt 1 gt HA11_N J13 N C HB11_N J31 NC LAO7_P H13 OUTA_P lt 1 gt HA11_P Jiz NC HB11_P J30 N C LAO8_N G13 OUTB_N lt 1 gt HA12_N F14 N C HB12_N F32 N C LAO8_P G12 OUTB_P lt 1 gt HA12_P F13 N C HB12_P F31 N C LA09_N D15 OUTA_N lt 0 gt HA13_N E13 N C HB13_N E31 N C LAO9_P D14 OUTA_P lt 0 gt HA13_P E12 N C HB13_P E30 N C LA10_N cis OUTB_N lt 0 gt HA14_N J16 NC HB14_N K35 N C LA10_P C14 OUTB_P lt 0 gt HA14_P sS NC HB14_P K34 N C LA11_N H17 OUTA_N lt 7 gt HA15_N F17 N C HB15_N J34 N C LA11_P H16 OUTA_P lt 7 gt HA15_P F16 N C HB15_P J33 N C LA12_N G16 OUTB_N lt 7 gt HA16_N E16 NC HB16_N F35 NC LA12_P G15 OUTB_P lt 7 gt HA16_P EIS NC HB16_P F34 N C LA13_N D18 OUTA_N lt 6 gt HA2. o YUU UU UU UU UU sc m SDIO Pr Pe Ps Pa Ps P2 P1 Po RAW w1 i wo a12 a11 a10 Ag as a7 a6 a5 as a3 a2 a1 ao D7 pe Ds D4 pa pa D1 Do 8 bit pre selection 16 bit instruction 8 bit register data Figure 17 Read instruction to AD9517 registers A12 A0 Good knowledge of the internal structure and communication protocol of relevant onboard devices is required for controlling the FMC116 FMC112 This document only gives guidelines for programming the devices Please refer to the datasheets mentioned in the Related Documents section of this user manual for detailed information 4DSP may also be contacted for programming support 5 3 Guidelines for controlling the clock tree Apart from enabling the internal reference the whole clock tree is controlled by programming the AD9517 device through a serial communication bus The following guidelines should be taken into account 1 The internal reference is enabled by CLKSRC_SEL1 driven from the CPLD The internal reference should only be enabled if the internal clock is used and no external reference is applied 2 The communication bus should be used in bidirectional mode thus using SDIO as serial data input and output 3 Itis recommended to disable the unused clock outputs 4 It is recommended to disable PLL functions on the AD9517 when an external sampling clock is applied 5 Although the AD9517 provides separate dividers on each cl
3. Bidir CMOS VADJ SPI data in out connected to the CPLD CTRL lt 3 gt CONTROL Output CMOS VADJ Interrupt connected the CPLD reserved for future use CTRL lt 6 4 gt CONTROL Bidir CMOS VADJ Reserved for future use CTRL lt 7 gt CONTROL Input CMOS VADJ Connected to CPLD and external trigger output buffer PG_C2M STATUS Input LVTTL Power good indicator from carrier to module PG_M2C STATUS Output LVTTL Power good indicator from module to carrier IOC SCL IOC Input LVTTL I2C clock line I2C_SDA 12C Bidir LVTTL 12C data line UM012 FMC116 amp FMC112 User Manual Sr e Appendix B CPLD Register map Koy SYNC CLKR LDAC DACR Reserved CLKSRC Table 10 Register CPLD_REGO definition Selection of clock source External clock Internal clock External Reference Reserved do not use Internal clock Internal Reference Asynchronous DAC Clear Normal operation DAC output level can be set trough SPI All DAC output levels set to mid scale This bit is not self clearing Asynchronous DAC Update Normal operation Reserved for future use Clock tree RESET Normal operation Resetting the clock tree is normally not required This bit is not self clearing Clock tree SYNC Normal operation Synchronizing the clock tree is normally not required This bit is not self cleari
4. Whether the loop filter design still works for other configurations should be investigated case by case 4 6 Power supply Power is supplied to the FMC116 FMC112 card through the FMC connector The power provided by the carrier card can be noisy Special care is taken with the power supply generation on the FMC116 card to minimize the effect of power supply noise on clock generation and data conversion The analog and digital 1 8V for the ADC devices are derived directly from the 3 3V plane in a linear way Each analog supply uses its own low noise high PSRR linear regulator to isolate power supply noise between ADCs Analog clock and bipolar 3 3V power is derived from 12V in two steps for maximum efficiency The first step uses switched regulators to generate a 3 8V and 3 8V power rail From this power rail each analog supply is derived with separate low dropout low noise high PSRR and linear regulators The regulators have sufficient copper area and thermal vias to dissipate the heat in combination with proper airflow see section 6 2 Cooling Worst case power consumption 15 4W Typical power consumption 12 0 W UM012 www 4dsp com page 15 of 29 UM012 FMC116 amp FMC112 User Manual JSr Typical Maximum DC High DC Low Power plane Performance Power Maximum VADJ 300mMmA Ivo s 300mA Ivo s 500mA Ivio_B 3P3V 1328mA 1328mA 1436mA 12POV 630mA 289mA 885mA 3P3VAUX Operating 0 1
5. mA 0 1 mA 3mA 3P3VAUX Standby 0 01 pA 0 01 pA 1 uA Table 4 Typical Maximum current drawn from FMC carrier card 5 Controlling the FMC116 FMC112 A small CPLD is implemented on the board to control the FMC116 FMC112 through a minimal amount of connections on the FMC connector This allows for a maximum amount of A D channels mapped to the LPC connections The FMC116 FMC112 maps control signals and 12 A D channels to the LPC connections The remaining four A D channels are mapped to HPC connections If the FMC is used on a LPC carrier 12 of the 16 A D channels will be available FMC112 5 1 Control Architecture The FMC needs to be controlled from the carrier hardware through a single SPI communication bus The SPI communication bus is connected to a CPLD which has the following tasks e Distribute SPI access from the carrier hardware to the local devices 4x LTC2175 A D converters 1x AD9517 Clock Tree 2x LTC2656 D A converters e Select clock source based on a SPI command from the carrier hardware CLKSRC_SEL e Generate SPI reset for AD9517 CLK_N_RESET e Collect local status signals and store them in a register which can be accessed from the carrier hardware e Drive a LED according to the level of the status signals UM012 page 16 of 29 www 4dsp com UM012 FMC116 amp FMC112 User Manual DS Local Side ADCO_N_CS ADC1_N_CS ADC2_N_CS CPLD ADC3_N_CS FMC Side CTRL 0
6. the connector on the FMC116 FMC112 is QSE 020 01 F D A K Figure 5 FMC116 FMC112 dimensions mounting option 2 4 1 2 Front panel One Samtec connector QSE 020 for the 16 analog channels is available from the front panel Note that the cable labels are numbered from 1 to 16 but the captured ADC data is saved from 0 to 15 gna HE D IER ooo HH g bon Er FER T ns JAMP Ei GI o iy coor ka ETH mp HH Be o EI Bo k bo vm HH i anas Wy bo bet Hr rep gM cate bech FER m nm ka fave bro fave ne ampf EI JAMP bei P EI OR bet HCH r aons H E H mp HH sty Ll nn WI SE 5 KOR 2 x 2 S 2 L Side 1 Cable Side 2 Cable Pin Signal Label Pin Signal Label 1 CH 08 CHO9 2 GND 3 GND 4 CH 09 CH10 5 CH 10 CH11 6 GND 7 GND 8 CH 11 CH12 9 CH 04 CHOR 10 GND 11 GND 12 CH 05 CHOD 12 CH 06 CH07 14 GND 15 GND 16 CH 07 CH08 17 CH 00 CHO 18 GND 19 GND 20 CH 01 CH02 21 CH 02 CH03 22 GND 23 GND 24 CH 03 CH04 UM012 www 4dsp com page 9 of 29 UM012 FMC116 amp FMC112 User Manual ef SP 7 25 CH 12 CH13 26 GND 27 GND 28 CH 13 CH14 29 CH 14 CH15 30 GND 31 GND 32 CH 15 CH16 33 GND 34 GND 35 CLOCK IN Cl 36 GND 37 GND 38 TRIGGER IN TI 39 CLOCK OUT CO 40 TRIGGER OUT TO Table 2 Ana
7. 1 oo gt 8 bit pre selection 8 bit instruction 8 bit register data Figure 12 Write instruction to CPLD registers A1 A0 N_CS souk TU UU UU UU UU UU UU U U U U U U UU SDIO 8 bit pre selection 8 bit instruction 8 bit register data Figure 13 Read instruction to CPLD registers A1 A0 N_CS souk TU UU UU UU UU UU UU U U UU U U UU UU L SDIO e a e I e a ae 8 bit pre selection 8 bit instruction 8 bit register data Figure 14 Write instruction to LTC2175 registers A4 A0 N_CS souk TU UU UU UU UU U U UU UU U U U U UU spo P7 Pe Pe Pa Pa pa as as as a ae ac an abba 8 bit pre selection 8 bit instruction 8 bit register data Figure 15 Read instruction to LTC2175 registers A4 A0 N_CS sok TU UU UU UU UU UU UU UU E SDIO r7 Po ps pa Ps P2 P1 Po IRW w1 wo lat2 at1 Ato a9 as a7 a6 as a4 as a2 At AO D7 D6 D5 D4 Ds Ds D1 Do 8 bit pre selection 16 bit instruction 8 bit register data Figure 16 Write instruction to AD9517 registers A12 A0 UM012 www 4dsp com page 18 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 N_CS
8. 17_N_CC K17 N C HB17_N_CC K38 N C LA13_P D17 OUTA_P lt 6 gt HA17_P_CC K16 N C HB17_P_CC K37 N C LA14_N C19 OUTB_N lt 6 gt HA18_N J19 N C HB18_N J37 N C LA14_P C18 OUTB_P lt 6 gt HA18_P J18 NC HB18_P J36 N C LA15_N H20 OUTA_N lt 5 gt HA19_N F20 N C HB19_N E34 N C LA15_P H19 OUTA_P lt 5 gt HA19_P F19 N C HB19_P E33 N C LA16_N G19 OUTB_N lt 5 gt HA20_N E19 N C HB20_N F38 N C LA16_P G18 OUTB_P lt 5 gt HA20_P E18 N C HB20_P F37 N C LA17_N_CC D21 DCO_N lt 2 gt HA21_N K20 N C HB21_N E37 N C LA17_P_CC D20 DCO_P lt 2 gt HA21_P K19 N C HB21_P E36 N C LA18_N_CC C23 FRAME_N lt 1 gt HA22_N IER N C LA18_P_CC C22 FRAME_P lt 1 gt HA22_P IEN N C LA19_N H23 OUTA_N lt 4 gt HA23_N K23 NC LA19_P H22 OUTA_P lt 4 gt HA23_P K22 N C LA20_N G22 OUTB_N lt 4 gt LA20_P G21 OUTB_P lt 4 gt LA21_N H26 OUTA_N lt 11 gt LA21_P H25 OUTA_P lt 11 gt LA22_N G25 OUTB_N lt 11 gt LA22_P G24 OUTB_P lt 11 gt LA23_N D24 OUTA_N lt 10 gt LA23_P D23 OUTA_P lt 10 gt LA24_N H29 OUTB_N lt 10 gt LA24_P H28 OUTB_P lt 10 gt UM012 www 4dsp com page 25 of 29 UM012 FMC116 amp FMC112 User Manual ot SP LA25_N G28 FRAME_N lt 2 gt LA25_P G27 FRAME_P lt 2 gt LA26_N D27 OUTA_N lt 9 gt LA26_P D26 OUTA_P lt 9 gt LA27_N c27 OUTB_N lt 9 gt LA27_P c26 OUTB_P lt 9 gt LA28_N H32 OUTA_N lt 8 gt LA28_P H31 OUTA_P lt 8 gt LA29_N G31 OUTB_N lt 8 gt LA29_P Gan OUTB_P
9. E 11 41 1 Stacked e 11 4a JITA EE 11 4 2 Main characienshGg sse eee eee 11 4 3 Analog input ur 12 4 3 1 1 6 6 s le 21 12 4 3 2 DC offset correction EE 13 4 4 External trigger et eee eee 13 4 4 1 External trigger Input sese eee EE deed ege 12 442 External trigger OUuOUL sss eee eee 12 4 amp 5 Ge 14 K I 191 1 EA 14 4 5 1 External clock input EE 14 4 5 2 External lU getigert Aere Ae dEr Ee 15 453 EN gf B a Ts EE 15 4 6 Power Supp eee ee eee eee eee 15 5 Controlling the FMC116 FMC112 egeeugeeeeeiegge e netic ieee 16 5 1 EECHER ee 16 52 SPIIPrOgrmmnG E 17 5 3 Guidelines for controlling the clock tree AEN 19 5 4 Guidelines for controlling the Ale 19 5 5 Guidelines for ADC Offset control eee eee 19 5 6 Guidelines for controlling onboard MONILOFING esse eee eee eee 20 6 Environment HT 21 61 LEE 21 E e eiel T WE 21 E We een e E 21 6 2 1 Conduction Cooling E 21 UM012 www 4dsp com page 3 of 29 UM012 FMC116 amp FMC112 User Manual ot SP DT Eege 22 gt mL e 22 9 Warianty E 22 Appendix A Pin out FMC116 FMC112 ssssssseeeessssseeree essen eee ennenen eenn 23 Appendix B CPLD Register map cccccsssssseeeeeeeeeeeeseneeeeeeeeeeeeeeeenseeeeeeeeeeseeseeeseneneeeeeses 28 UM012 www 4dsp com page 4 of 29 UM012 FMC116 amp FMC112 User Manual 1 Acronyms and related documents 1 1 Acronyms EPROM FBGA FPGA A JTAG Join Test Action Group Light Emitting Diode LVTT Low Voltage T
10. F34 N C LA13_N D18 OUTA_N lt 6 gt HA17_N_CC K17 N C HB17_N_CC K38 N C LA13_P D17 OUTA_P lt 6 gt HA17_P_CC K16 N C HB17_P_CC K37 N C LA14_N c19 OUTB_N lt 6 gt HA18_N J19 N C HB18_N J37 N C LA14_P C18 OUTB_P lt 6 gt HA18_P J18 N C HB18_P J36 NC LA15_N H20 OUTA_N lt 5 gt HA19_N F20 N C HB19_N E34 N C LA15_P H19 OUTA_P lt 5 gt HA19_P F19 N C HB19_P E33 N C LA16_N G19 OUTB_N lt 5 gt HA20_N E19 N C HB20_N F38 N C LA16_P G18 OUTB_P lt 5 gt HA20_P E18 N C HB20_P F37 N C UM012 www 4dsp com page 23 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 LA17_N_CC D21 DCO_N lt 2 gt HA21_N K20 N C HB21_N E37 N C LA17_P_CC D20 DCO_P lt 2 gt HA21_P K19 N C HB21_P E36 N C LA18_N_CC c23 FRAME_N lt 1 gt HA22_N J22 N C LA18_P_CC c22 FRAME_P lt 1 gt HA22_P J21 N C LA19_N H23 OUTA_N lt 4 gt HA23_N K23 N C LA19_P H22 OUTA_P lt 4 gt HA23_P K22 N C LA20_N G22 OUTB_N lt 4 gt LA20_P G21 OUTB_P lt 4 gt LA21_N H26 OUTA_N lt 11 gt LA21_P H25 OUTA_P lt 11 gt LA22_N G25 OUTB_N lt 11 gt LA22_P G24 OUTB_P lt 11 gt LA23_N D24 OUTA_N lt 10 gt LA23_P D23 OUTA_P lt 10 gt LA24_N H29 OUTB_N lt 10 gt LA24_P H28 OUTB_P lt 10 gt LA25_N G28 FRAME_N lt 2 gt LA25_P G27 FRAME_P lt 2 gt LA26_N D27 OUTA_N lt 9 gt LA26_P D26 OUTA_P lt 9 gt LA27_N C27 OUTB_N lt 9 gt
11. FMC112 is enclosed in will dissipate the heat generated by the onboard components A minimum airflow of 300 LFM is recommended For standalone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC to ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 2 1 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the UM012 www 4dsp com page 21 of 29 UM012 FMC116 amp FMC112 User Manual ot SP junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C The FMC116 FMC112 is designed for maximum heat transfer to conduction cooled ribs A customized cooling frame that connects directly to the surface of the A D devices is allowed This conduction cooling mechanism should be applied in combination with proper chassis cooling Contact 4DSP for detailed mechanical information 7 Safety This module presents no hazard to the user 8 EMC This module is designed to operate within an enclosed host system built to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system T
12. LA27_P c26 OUTB_P lt 9 gt LA28_N H32 OUTA_N lt 8 gt LA28_P H31 OUTA_P lt 8 gt LA29_N G31 OUTB_N lt 8 gt LA29_P G30 OUTB_P lt 8 gt LA30_N H35 CTRL lt 1 gt LA30_P H34 CTRL lt 0 gt LA31_N G34 CTRL lt 3 gt LA31_P G33 CTRL lt 2 gt LA32_N H38 CTRL lt 5 gt PG_C2M D1 PG_C2M LA32_P H37 CTRL lt 4 gt PG_M2C F1 PG_M2C LA33_N G37 CTRL lt 7 gt DC SCH c30 12C_SCL LA33_P G36 CTRL lt 6 gt 12C_SDA c31 VC Spa Table 8 FMC112 pin out AV57 1 LPC Pin FMC112 Signal AV57 1 LPC Pin FMC112 Signal AVS7 1 LPC Pin FMC112 Signal CLKO_M2C_N H5 CLK_TO_FPGA_N HAOO_N_CC F5 N C HBOO_N_CC K26 N C CLKO_M2C_P H4 CLK_TO_FPGA_P HAOO_P_CC F4 N C HBOO_P_CC KMR N C CLK1_M2C_N G3 EXT_TRIGGER_N HAO1_N_CC E3 N C HBO1_N 125 NC CLK1_M2C_P G2 EXT_TRIGGER_P HAO1_P_CC E2 N C HBO1_P J24 NC CLK2_BIDIR_N K5 N C HA02_N K8 N C HBO2_N F23 N C CLK2_BIDIR_P K4 N C HA02_P K7 N C HBO2_P F22 N C CLK3_BIDIR_N J3 N C HAO3_N 17 N C HBO3_N E22 N C CLK3_BIDIR_P J2 N C HA03_P J6 N C HBO3_P E21 N C LAQO_N_CC G7 DCO_N lt 0 gt HAO4_N F8 N C HBO4_N F26 N C LAQO_P_CC G6 DCO_P lt 0 gt HAO4_P F7 N C HBO4_P F25 N C UM012 www 4dsp com page 24 of 29 UM012 FMC116 amp FMC112 User Manual Ft
13. SCLK CTRL 1 CTRL 2 E K spio Shift register RR CLKSRC_SEL 0 1 VY Ctrl CLK_N_RESET CLK_N_SYNC DAC_N_CLR DAC N DAC REFMON a LD a STATUS A B gt AND gt GER VM N INT k a deet 23227 ei CTRL 7 4 Figure 11 CPLD architecture Notes e SDO from the LTC2656 devices are not connected s N PD on the AD9517 is not connected 5 2 SPI Programming The SPI programmable devices on the FMC116 FMC112 can be accessed as described in their datasheet but each SPI communication cycle needs to be preceded with a preselection byte The preselection byte is used by the CPLD to forward the SPI command to the right destination trough CS pins The preselection bytes are defined as follows CPLD LTC2175 LTC2175 LTC2175 LTC2175 AD9517 LTC2656 LTC2656 1 2 3 4 1 2 0x00 0x80 0x81 0x82 0x83 0x84 0x85 0x86 A D channels 00 to 03 A D channels 04 to 07 A D channels 08 to 11 A D channels 12 to 15 KS a YI a The CLPD has three internal registers which are described in Appendix B CPLD Register map The registers of the other devices are transparently mapped UM012 www 4dsp com page 17 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 N CS sek TY UU UU U UU UU UU UU UU UU UU UU UL SDIO P7 P6 P5 P4 P3 P2 P1 PO IRW A6 A5 A41 A91 A2 a ao D7 pe os 04 oa o3 o
14. S_N E7 FRAME_N lt 3 gt HBOS_N E25 N C LA01_P_CC D8 DCO_P lt 1 gt HAOS_P E6 FRAME_P lt 3 gt HB05_P E24 N C LA02_N H8 OUTA_N lt 3 gt HAO6_N K11 OUTA_N lt 13 gt HBO6_N_CC K29 N C LAO2_P H7 OUTA_P lt 3 gt HAO6_P K10 OUTA_P lt 13 gt HBO6_P_CC K28 N C LAO3_N G10 OUTB_N lt 3 gt HAO7_N J10 OUTB_N lt 13 gt HBO7_N J28 N C LAO3_P G9 OUTB_P lt 3 gt HA07_P J9 OUTB_P lt 13 gt HBO7_P J27 N C LAO4_N H11 OUTA_N lt 2 gt HA08_N FIL OUTA_N lt 12 gt HBO8_N F29 N C LAO4_P H10 OUTA_P lt 2 gt HAO P F10 OUTA_P lt 12 gt HBO8_P F28 N C LAOS_N D12 OUTB_N lt 2 gt HAO9_N E10 OUTB_N lt 12 gt HBO9_N E28 N C LAOS_P D11 OUTB_P lt 2 gt HA09_P EQ OUTB_P lt 12 gt HBO9_P E27 N C LAO6_N cil FRAME_N lt O gt HA10_N K14 N C HB10_N K32 NC LAO6_P C10 FRAME_P lt 0 gt HA10_P K13 N C HB10_P K31 N C LAO7_N H14 OUTA_N lt 1 gt HA11_N J13 N C HB11_N J31 N C LA07_P H13 OUTA_P lt 1 gt HA11_P kk NC HB11_P J30 N C LAO8_N G13 OUTB_N lt 1 gt HA12_N F14 N C HB12_N F32 N C LAOS P G12 OUTB_P lt 1 gt HA12_P F13 NC HB12_P IEN NC LA09 N D15 OUTA_N lt 0 gt HA13_N E13 N C HB13_N E31 N C LAO9_P D14 OUTA_P lt 0 gt HA13_P EIS NC HB13_P E30 N C LA10_N cis OUTB_N lt 0 gt HA14_N J16 NC HB14_N K35 N C LA10_P C14 OUTB_P lt 0 gt HA14_P KE NC HB14_P K34 N C LA11_N H17 OUTA_N lt 7 gt HA15_N F17 N C HB15_N J34 N C LA11_P H16 OUTA_P lt 7 gt HA15_P F16 NC HB15_P J33 N C LA12_N G16 OUTB_N lt 7 gt HA16_N E16 N C HB16_N F35 NC LA12_P G15 OUTB_P lt 7 gt HA16_P EIS NC HB16_P
15. UM012 FMC116 amp FMC112 User Manual ot SP FMC116 FMC112 User Manual o ENN fue 4DSP LLC USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied or communicated to a third party without the written permission of 4DSP LLC 4DSP LLC 2015 UM012 FMC116 amp FMC112 User Manual oe SP 7 Revision History 2012 08 31 Mentioned that the analog inputs are inverted by 1 1 the input circuit 2013 03 01 VADJ range revised 2013 06 03 Added a cable label in 4 1 2 2014 03 06 Changed external clock and reference input 1 4 power level 2014 04 11 Revised some descriptions and fixed typos 2014 12 03 Clarified the op amp used in the front end circuit 2015 02 25 Revised some descriptions and fixed typos UM012 www 4dsp com page 2 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 Table of Contents 1 Acronyms and related documents ssssssseeeeessssssseeeeeesssssseereeee essere esen 5 Een T ne ee ere eee eee eee eee ee eee eee ene 5 1 2 Related A lf Lu 5 2 General GOSH UO senses cick cases cs sees ca eects Seen c inndcncc deste bentaxna dadean anian ARa EEEN iaaii 6 3 Installati n E 7 3 1 Requirements and handling metruchons sees eee 7 Ms s TT A n A A A a E 7 41 Physical Speer nre een EAE EEEE Ea gege 7 4 1 1 Board DIMENSIONS E 7 412 POU ve BEE 9 4 1 1 Clock Trigger connector opt sss 10 4 1 2 LVDS 010 ener ere eee eee eee ee er eee een 10 cN D EEPROM
16. ampling frequency through a serial communication bus SPI The card is also equipped with power supply and temperature monitoring and offers several power down modes to switch off unused functions or protect the card from overheating Clock Ref IN Clock Status amp Control f Clock Ref OUT Clock Tree d Trigger OUT Trigger IN LVDS Clock 4x LVDS Data 32x LVDS Frame 4x JOJO9UUOD jeued 100 SONDAMI pue SOA suid 00p JUNOD u q YBIH OWS Figure 1 FMC116 block diagram UM012 www 4dsp com page 6 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 3 3 1 4 4 1 Clock Ref IN Clock gt Clock Tree Status amp Control 8 a S E lt 5 e Trigger OUT D si oS Trager LL e H gt gt S LL ag ADC 00 Eo D LVDS Clock 3x SS S LVDS Data 24x OG LVDS Frame 3x AP D Wa Figure 2 FMC112 block diagram Installation Requirements and handling instructions The FMC116 FMC112 daughter card must be installed on a carrier card compliant to the FMC standard The FMC carrier card must either offer an LPC or HPC FMC site Note that a LPC FMC site offers limited functionality 12 out of 16 channels The carrier card can support VADJ VIO_B voltage range of 1 65V to 3 3V for the FMC116 but typically VADJ will be 1 8V or 2 5V for LVDS operation Prevent electrostatic discharges by observin
17. ence clock input if the internal clock with external reference is desired An RF switch UM012 www 4dsp com page 14 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 ADG918 connects the external clock input to either the reference input REFIN or the clock input CLK of the AD9517 Note When the internal clock is enabled and there is no need for an external reference it is highly recommended to leave the clock input unconnected to prevent interference with the internal clock 4 5 2 External clock output The external clock output is connected through a RF transformer TC2 1T Setting up the AD9517 for LVDS outputs is recommended The RF transformer is used for differential to single ended conversion and impedance matching A 500 load on the clock output is expected 4 5 3 PLL design The PLL functionality of the AD9517 3 is used to operate from an internal sampling clock To enable flexibility in frequency selection while maintaining high performance the internal VCO is used The default loop filter is designed for a phase detector frequency of 10MHz loop bandwidth of 10 kHz phase margin of 45 degrees and a charge pump of 4 8mA o o Be R1 R2 C3 T 39nF 82R 180R T 18nF V C2 yz T 680nF WY Figure 10 VCO loop filter design Lower phase detector frequencies might be required to achieve the required output clock frequency phase detector frequency equals the VCO tuning step size
18. g ESD precautions when handling the card Design Physical specifications 4 1 1 Board Dimensions The FMC116 FMC112 card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O The front area holds an edge mounted Samtec connector QSE 020 01 F D EM2 that might conflict with a front rib on a carrier card There are different mounting options for different cable ends UM012 www 4dsp com page 7 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 1 For this option an adapter PCB is mounted on the FMC This enables the cable to be mated while the FMC is installed on a carrier All signals including clock and trigger signal are mapped on a single connector This is the default factory configuration E TP T E 5 IG JG Figure 3 FMC116 FMC112 dimensions mounting option 1 A SMA breakout solution is available for the FMC116 FMC112 It gives access to the signals on female SMA connectors The breakout option can be specified in the order number Figure 4 SMA breakout cable UM012 www 4dsp com page 8 of 29 UM012 FMC116 amp FMC112 User Manual Ft 2 The second mounting option is a cable is directly mounted on the FMC The cable needs to be mounted prior installing the FMC on the carrier The part number of
19. ges on the board as well as temperature The devices can be programmed and read out through the 12C interface 1 The measured value on 3 3V and rails must be multiplied by two to get the actual level 2 The negative supply 3 3V Analog is connected with a resistive divider to Vdd Therefore the formula from the Table 6 should be used 3 Continuously operating the 12C bus might interfere with the conversion process and result in signal distortion It is recommended to program the minimum and maximum limits in the monitoring devices and only read from the device when the interrupt line is asserted UM012 www 4dsp com page 20 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 Parameter Device 1 Formula address 1001 000 On chip temperature On chip AINO Vpp 3 3V VDD External AIN1 1 8V 2 AIN1 External AIN2 1 8V 3 AIN2 External AIN3 1 8V Digital AIN3 External AIN4 3 3V Analog 5 7 AIN4 4 7 VDD External AIN5 1 8V 1 AIN5 External AIN6 1 8V 0 AIN6 External AIN7 3 3V Clock AIN7 2 External AIN8 3 3V Analog AIN8 2 Table 6 Temperature and voltage parameters 6 Environment 6 1 Temperature Operating temperature e 40 C to 85 C Industrial Storage temperature e 40 C to 120 C 6 2 Cooling Two different types of cooling will be available for the FMC116 FMC112 6 2 1 Convection cooling The air flow provided by the chassis fans the FMC116
20. his module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 9 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included Extended Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional UM012 www 4dsp com page 22 of 29 UM012 FMC116 amp FMC112 User Manual Appendix A Pin out FMC116 FMC112 Table 7 FMC116 pin out JSr AVS7 1 HPC Pin FMC116 Signal AVS7 1 HPC Pin FMC116 Signal AVS7 1 HPC Pin FMC116 Signal CLKO_M2C_N HS CLK TO FPGA N HAOO_N_CC FS DCO_N lt 3 gt HBOO_N_CC K26 N C CLKO_M2C_P H4 CLK_TO_FPGA_P HA00_P_CC F4 DCO_P lt 3 gt HBOO_P_CC K25 N C CLK1_M2C_N G3 EXT_TRIGGER_N HAO1_N_CC E OUTA_N lt 15 gt HBO1_N J25 N C CLK1_M2C_P G2 EXT_TRIGGER_P HA01_P_CC E2 OUTA_P lt 15 gt HBO1_P J24 N C CLK2_BIDIR_N K5 N C HA02_N K8 OUTB_N lt 15 gt HBO2_N F23 N C CLK2_BIDIR_P K4 N C HA02_P K7 OUTB_P lt 15 gt HBO2_P F22 N C CLK3_BIDIR_N J3 N C HA03_N J7 OUTA_N lt 14 gt HB03_N E22 N C CLK3_BIDIR_P J2 N C HA03_P J6 OUTA_P lt 14 gt HBO3_P E21 N C LAOO_N_CC G7 DCO_N lt 0 gt HAO4_N F8 OUTB_N lt 14 gt HB04_N F26 N C LAOO_P_CC G6 DCO_P lt 0 gt HADA p F7 OUTB_P lt 14 gt HBO4_P F25 N C LA01_N_CC D9 DCO_N lt 1 gt HAO
21. log input connector pin out Channels 12 to 15 are not available on LPC carrier cards 4 1 1 Clock Trigger connector option Optionally four dedicated SSMC connectors can be placed for the following signals CLOCK IN CLOCK OUT TRIGGER IN TRIGGER OUT Whether those signals are connected to the SSMC or the QSE 020 connector is determined by a OR build option The SSMC connectors are not placed by default and all signals connect to the QSE 020 connector Please contact the factory for other options Note that the SSMC connectors will be placed on the opposite side of the QSE 020 connector The customer should verify whether this is acceptable in their environment since it breaches the mechanical constraints of the FMC standard Figure 6 SSMC connector option 4 1 2 LVDS mode All data and clock signals to the carrier are LVDS pairs The VADJ voltage supplied to the FMC116 can range between 1 65V and 3 3V but typically VADJ will be 1 8V or 2 5V for LVDS operation VIO_B is connected to VADJ The A D converters operate in LVDS mode supplying an LVDS clock and DDR LVDS data frame signals All other status and control signals like serial communication busses operate at LVCMOS level Von VADy UM012 www 4dsp com page 10 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 4 1 1 EEPROM The FMC116 FMC112 card carries a small serial EEPROM which is accessible from the carrier card through the ISC bus The EEPROM is po
22. lt 8 gt LA30_N H35 CTRL lt 1 gt LA30_P H34 CTRL lt 0 gt LA31_N G34 CTRL lt 3 gt LA31_P G33 CTRL lt 2 gt LA32_N H38 CTRL lt 5 gt PG_C2M D1 PG_C2M LA32_P H37 CTRL lt 4 gt PG_M2C F1 PG_M2C LA33_N G37 CTRL lt 7 gt DC SCH c30 12C_SCL LA33_P G36 CTRL lt 6 gt 12C_SDA c31 VC Spa UM012 www 4dsp com page 26 of 29 UM012 FMC116 amp FMC112 User Manual ADS ns Table 9 Signal description FMC116 FMC112 Signal Group Direction UO Standard Description DCO_N lt 3 0 gt A D Output LVDS Digital clock output from the LTC2175 One DCO_P lt 3 0 gt pair per device OUTA_N lt 15 0 gt A D Output LVDS Output port A from the LTC2175 Four pairs OUTA_P lt 15 0 gt per device OUTB_N lt 15 0 gt A D Output LVDS Output port B from the LTC2175 Four pairs OUTB_P lt 15 0 gt per device FRAME_N lt 3 0 gt A D Output LVDS Frame output from the LTC2175 One pair per FRAME_P lt 3 0 gt device CLK_TO_FPGA_N CLOCK Output LVDS Spare clock output from the AD9517 May be CLK_TO_FPGA_P used for debugging monitoring purposes EXT_TRIGGER_N TRIGGER Output LVDS Representation of the signal connected to the EXT_TRIGGER_P external trigger input CTRL lt 0 gt CONTROL Input CMOS VADJ SPI clock connected to the CPLD CTRL lt 1 gt CONTROL Input CMOS VADJ SPI chip select connected to the CPLD CTRL lt 2 gt CONTROL
23. mpling clock The AD9517 3 PLL and clock distribution device is the base of the clock tree The external clock input is routed to a RF switch connecting either to the reference input on the AD9517 3 REFIN or to the clock input on the AD9517 3 CLK The clock input can be connected directly to the distribution section of the AD951 7 3 The internal VCO of the AD9717 3 is used A reference clock on REFIN is required to tune the VCO to a certain frequency An onboard oscillator can be enabled if no external reference is connected The onboard oscillator is connected in parallel with the clock input behind the RF transformer To avoid interference there should be no signal applied to clock input when internal reference is used selected by CLKSRC_SEL1 Loop Filter CLKSRC_SEL1 RF CLKSRC_SELO i AND MONITOR SWITCHOVER L To FMC SERIAL CONTROL PORT lt _ AND DIGITAL LOGIC C S Figure 9 Clock tree architecture The AD9517 3 has four LVPECL outputs OUTO to OUT3 which are used for clocking the ADC devices The other four clock outputs can be either programmed as LVDS or LVCMOS33 These outputs have the ability to enable a programmable delay one is connected to the FMC connector for test and monitoring purposes while the other connects to the clock output on the front panel 4 5 1 External clock input There is one clock input on the front panel that can serve as a sampling clock input or as refer
24. ng Table 11 Register CPLD_REGO description Reserved IRQ VM STATUS LD REFMON Table 12 Register CPLD_REG2 definition read UM012 FMC116 amp FMC112 User Manual oe SP Reflect the status of the REFMON output of the AD9517 Reflect the status of the LD output of the AD9517 Reflect the status of the STATUS output of the AD9517 Reflect the status of the INT output of the ADT7411 inverted INT is not asserted INT is asserted access to the ADT7411 trough the 1 C bus is required to determine the source of the interrupt Logic function NOT REFMON AND LD AND STATUS AND INT All status signals indicate OK One or more status signals indicate ERROR Table 13 Register CPLD_REG2 description read Reserved LED_SEL Table 14 Register CPLD_REG2 definition write Writing to this register determines which status signal is reflected on the LED REFMON LD STATUS VM IRQ Table 15 Register CPLD_REG2 description write XXXX1 XXX10 XX100 X1000 10000 UM012 www 4dsp com page 29 of 29
25. ock output it is not recommended to use different divider settings 6 Lower phase detector frequencies may be used to increase flexibility on the output frequency The stability of the PLL is not guaranteed in all cases 7 If multiple cards are cascaded by means of connecting the clock output to the clock input of the next card the programmable delay on the clock output may be used to compensate for the propagation delay between cards 5 4 Guidelines for controlling the ADCs Controlling the ADCs enables advanced control of the digitizing process The ADC devices allows for serial and parallel programming On the FMC116 FMC112 the PAR SER pins of the ADC are tied together and driven low by the CPLD forcing the devices in serial programming mode 5 5 Guidelines for ADC offset control Offset control is available per individual ADC channel The following table shows the ADC channel controlled by each DAC output UM012 www 4dsp com page 19 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 LTC2656 Channel LTC2656 Device 1 LTC2656 Device 2 VOUT_A A D 08 A D 00 VOUT_B A D 09 A D 01 VOUT_C A D 10 A D 02 VOUT_D A D 11 A D 03 VOUT_E A D 04 A D 12 VOUT_F A D 05 A D 13 VOUT_G A D 06 A D 14 VOUT_H A D 07 A D 15 Table 5 Offset control 5 6 Guidelines for controlling onboard monitoring The FMC116 FMC112 has one ADT7411 device for monitoring several power supply volta
26. per channel Output data width Frequency 3 5 times the sample frequency Data Format Offset binary or 2 s complement Sampling Frequency Range 5 MHz to 125 MHz FMC connector type HPC ASP 134488 01 Internal sampling clock Frequency Range up to 125MHz Software programmable Table 3 FMC116 FMC112 daughter card main characteristics 4 3 Analog input channels The analog input signals are connected to the FMC116 FMC112 via the Samtec connector on the front panel The Samtec connector alternates channels and ground pins to minimize crosstalk between channels 4 3 1 ADC driver The input circuit is DC coupled using Analog Devices ADA4938 ADC driver The gain G is set to one giving maximum input bandwidth BW As a build option larger gain can be realized but the bandwidth will be reduced accordingly consult factory for more details Note that that a polarity twist between the op amp and the ADC results in an inverted input signal UM012 www 4dsp com page 12 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 DC Offset Correction Figure 7 ADC input circuit 4 3 2 DC offset correction DC offset correction is enabled through a small 16 bit DAC device An op amp is used as a buffer and to make a bi polar output on the DAC The DAC uses an external reference voltage Vref The DAC output swings from OV to 2 Vref A resistor divider is used for a reduced swing of OV to Vref The output of the op amp has a swing f
27. ransistor Logic level Least Significant Bit s LVDS Se PLL PMC PSSR SDRAM M TL MC DC DSP FMC LED L LSB MGT MSB PCB PCI SRA Synchronous Random Access memory Transistor Logic level PCle Mezzanine card Table 1 Glossary T X 1 2 Related Documents e FPGA Mezzanine Card FMC standard ANSI VITA 57 1 2010 e Datasheet AD9517 Rev A Analog Devices e Datasheet LTC2175 14 Linear Technology e Datasheet ADT7411 Rev B Analog Devices UM012 www 4dsp com page 5 of 29 DS UM012 FMC116 amp FMC112 User Manual oe SP 7 2 General description The FMC116 is a 16 channel ADC FMC daughter card The card provides sixteen 14 bit 125MSPS ADC channels which can be clocked by an internal clock source optionally locked to an external reference or an externally supplied sample clock There is a trigger input and a trigger output for customized sampling control A low pin count variant is available offering 12 channels FMC112 The FMC116 FMC112 daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The FMC116 FMC112 has a high pin count connector front panel I O and can be used in conduction cooled environments The design is based on Linear Technology s quad channel 14 bit 125MSPS ADC with high speed serial DDR LVDS outputs 2 lanes per channel The analog signal input is DC coupled connecting to a Samtec connector on the front panel The FMC116 FMC112 allows flexible control on s
28. rom Vref to Vref The granularity of the DC offset correction depends on the DAC resolution and the voltage reference For a 16 bit DAC device with 1 25V reference each step corresponds to approximately 40uV The circuit depicted in Figure 8 is implemented for each channel using two octal DAC devices LTC2656 eight dual op amps ADA4932 2 and one voltage reference LTC6655 1 25 LTC6655 1 25V L DAC 1o SS LTC2656 SPI from FMC Figure 8 DC offset correction circuit 4 4 External trigger signals 4 4 1 External trigger input The input is single ended and DC coupled with an input impedance of approximately 2 5kQ The input threshold is approximately 1 25V An LVTTL signal is recommended 4 4 2 External trigger output The signal CTRL lt 7 gt from the FMC connector is routed to the external trigger output through a SN74LVC1G126 buffer The buffer is always enabled and powered by 3 3V The trigger output is LVTTL level NOTE The external trigger output can only work with a VADJ level of 2 5V CTRL7 requires Vih min 2V UM012 www 4dsp com page 13 of 29 UM012 FMC116 amp FMC112 User Manual oe SP 7 4 5 Clock tree 4 5 1 Architecture The FMC116 FMC112 card offers a clock architecture that combines flexibility and high performance Components have been chosen to minimize jitter and phase noise and to improve the data conversion performance The user may choose to use an external or an internal sa
29. wered by 3P3VAUX The standby current is only 0 01 UA when SCL and SDA are kept at 3P3VAUX level These signals may also be left floating since pull up resistors are present on the FMC116 FMC1 12 The EEPROM is factory programmed with information recommended in the FMC standard The EEPROM is therefore available as read only memory on the FMC116 FMC112 write protected 4 1 1 Stacked FMC The FMC connector as defined in ANSI VITA 57 1 is referred as the top FMC connector The FMC116 FMC112 can be used in a stacked environment when the bottom FMC connector is mounted The following connections are available between the top and bottom FMC connector e All gigabit data signals DP 0 9 M2C_P N DP 0 9 _C2M_P N e All gigabit reference clocks GBTCLK 0 1 _M2C_P N e RESO e 3P3VAUX 3P3V 12POV VADJ The bottom FMC connector is not mounted on factory default boards 4 1 2 JTAG The FMC116 FMC112 has a CPLD device in the JTAG chain 4 2 Main characteristics Analog inputs Numb fch l 16 on FMC116 umber of channels EE ee Input voltage range 2Vp p 10 dBm inverted Input impedance Analog input bandwidth DC to 62 5MHz External sampling clock input Input Level 10dBm to 7dBm UM012 www 4dsp com page 11 of 29 UM012 FMC116 amp FMC112 User Manual ft Sr 7 Logic 0 input low gt max 1 25V Threshold c a Logic 1 input high gt min 1 25V Frequency range Up to 125 MHz ADC Output 2 pair DDR LVDS
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