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1. Sheffield Hallam University Project Report TITLE THE DESIGN AND REALISATION OF AN FPGA BASED AUDIO PROCESSOR STUDENT MIKE HUDSON 18022224 PROJECT DR JOHN HOLDING a COURSE BENG HON ELECTRICAL AND MM 0 a8022224 shu ac uk 9 05 2012 Mike Hudson Preface This report describes project work carried out within the Engineering Programme at Sheffield Hallam University from October 2011 to April 2012 The submission of the report 1s in accordance with the requirements for the award of the degree of Bachelor of Electrical and Electronic Engineering with Honours under the auspices of the University II Mike Hudson Acknowledgements I would like to thank my supervisor Dr John Holding for his advice and guidance throughout the duration of this project I would also like to thank every one who has helped me over at the Altera Internet forums IH Mike Hudson Abstract This project report documents the use of a field programmable gate array FPGA for real time processing of audio The traditional software approach to digital signal processing often introduces an unacceptable delay between the audio input and the audio output referred to as the total system latency This can be problematic for applications that require real time operation such as live processing of musical instruments An FPGA design allows the same software routines to be implemented as hardware therefore eliminating high system latenc
2. 8 2 Choice of RAM device The DE2 has an 8MB SDRAM chip and a 512Kb SRAM chip Both devices were considered suitable for this project The general advantages of the SRAM chip 1s that it would usually be a lot easier to implement and also would inherently be faster than the SDRAM However since the RAM was to be written to and read from through the Avalon interface the advantages were considered negligible 8 3 SDRAM controller Core The SDRAM Controller core provides a byte addressable interface to the external SDRAM chip on the DE2 board and handles all protocol requirements The control core is instantiated from within SOPC builder and is connected into the Avalon bus as a memory mapped slave device Figure 8 1 illustrates how the RAM controller core effectively sits between the Avalon memory mapped slave port and the RAM chip 29 Mike Hudson Altera FPGA Clock PLL SDRAM Clock Source Phase Shift Controller Clock SDRAM Controller Core SDRAM Chip PC100 clock Avalcn MM slave address interface data control to on chip logic waitrequest Avalon MM Slave Port Interface to SDRAM pins readdatavalid Figure 8 1 SDRAM Controller with Avalon interface block diagram Altera Embedded Peripherals IP User Guide Figure 8 1 also shows two separate PLL generated clocks to drive the SDRAM chip and the controller core Due to the physical characteristics and PCB layout of the DE2 board the SDRAM chip requires a phase shift of
3. e Four serial interface modes e 16 20 24 and 32 bit word lengths Master or slave clocking modes The codec will easily provide adequate functionality for this project in terms of audio quality sample rate and bit depth and also interfacing requirements The codec uses an IC bus for configuration which is a standard protocol for communication between digital devices which reside on the same circuit board The Altera DE2 user manual provides full schematic diagrams of all its peripherals connected to the FPGA Figure 6 1 shows how the WM8781 chip is physically connected to the FPGA and a description of the signals are given in Table 6 1 16 Mike Hudson Standard 3 5mm audio Jack sockets x C control from FPGA N VCC33VCC33 Y i 1 RI R2 l l I AGND AGND li2c_SDAT I2C SCLK E A A 330 I 2 y 7 s c3 gt 1U OF J Uc R8 680 c4 R9 Y AGND I 1000P2 47K l l I l 1 l 1 AGND AGNO 1 Y Y A VCC33 inc i AGN AGN Codec signals to from GNO AGND FPGA Figure 6 1 Audio codec schematic Altera DE2 User manual This allowed for a better understanding of how the codec device is interfaced to the FPGA and which signals are available in the FPGA For example the lineout signals from the codec have been omitted in the design of the DE2 and it can be seen from Figure 6 1 that the headphone output is used instead The figure also confirms
4. 3ns with reference to the system clock to compensate for the clock lag The 3ns applies to the DE2 board only and would probably need to be altered for other boards or devices 8 4 Reading writing to and from the SDRAM In order to access the Avalon memory mapped slave port provided by the SDRAM controller core a memory mapped master component was created in SOPC builder The component wizard was used to create a custom TCL component for use in SOPC builder An Avalon memory mapped interface was added to the component along with a clock and reset All necessary signals were added to the component to create the interface to the RAM controller These signals are given on the top level of the generated SOPC system and will be used in a VHDL state machine to access the RAM See Figure 8 2 30 Mike Hudson 14 Component Editor sdrambuffer_hw tcl RO File Templates Introduction HDL Files Signals Interfaces HDL Parameters Library Info gt About Signals Name Interface Signal Type Width Direction clk clock_reset clk 1 input reset clock_reset_reset reset_n 1 input address avalon_master address 32 output read avalon master read 1 output readdata avalon master readdata 32 input waitrequest avalon master waitrequest 1 input write avalon master write 1 output writedata avalon master writedata 32 output Figure 8 2 SOPC Builder custom component signals The newly created component named sdrambuffer 0 was
5. 8 5 RAM state machine A state machine Figure 8 6 was implemented in VHDL to write read to and from the Avalon memory mapped master component The component editor gives an example of the read and write waveforms Figure 8 5 For example to write to the SDRAM the write signal is asserted and proceed with write when the waitrequest signal is zero Write Waveform address po fa fi fe writedata 0 for fa write waitrequest 7 XV X address uo AN CE readdata po for X jo j Figure 8 5 Read and write waveforms for Avalon memory mapped master inc write pointer read state idle state r write state Figure 8 6 State Machine for a RAM Buffer 32 Mike Hudson Source State Destination State rising edge of sample clk waitrequest 0 waitrequest 0 Table 8 1 RAM state machine conditions The left and right audio channels were combined into one 32 bit word defined as a logic vector in VHDL The read and writes to the RAM were done 32 bits at a time which requires the write pointer to increment by 4 on every sample since every address location the RAM contains a byte This was initially tested with the read pointer lagging one sample behind the write pointer This is shown in the VHDL Code extract 8 1 if inc_write_pntr 1 then write pntr lt write pntr 4 end if if inc read pntr 1 then read pntr lt read pntr 4 end if Code extract 8 1 Em Ao CO ND
6. Higher system level integration e Ability to emulate an embedded microprocessor for maximum flexibility 2 2 Digital audio theory Generally the first stage of Digitally processing audio 1s to convert the analogue audio signal to a digital representation using an analogue to digital converter ADC The digital signal processing 1s then carried out before being fed into a digital to analogue converter DAC to create an analogue signal from the digital one The ADC and DAC are most commonly offered as one IC package referred to in this report and the majority Mike Hudson of literature as an audio Codec The ADC samples the amplitude of the analogue signal at even points in time at a rate that obeys Nyguist s sampling theorem referred to as the sample rate or fs The value of the amplitude is represented with a binary value PCM typically for audio anywhere from 16 to 24 bits in length In general the higher the bit depth the more precision and lower guantisation error and noise a signal will have Figure 2 1 shows how precision can be lost with a smaller bit length avn JB TEC HN Minitizad E Ninitizad PCM cian Analog signa Digitized PCM signa Ulgitized FEM Signal using a b c ewer bils ol precision Figure 2 1 a An analogue signal b Digitised PCM signal c Digitised PCM signal with fewer bits of precision Katz D amp Gentile R 2009 The most basic of effects a volume control can be realised by
7. 1f these effects can be successfully implemented then almost any audio effect can be created The proposed digital audio effects e Echo requires a relatively large buffer size at least one second e Flanger requires the ability to modulate a delay value in real time e Filter requires only very small fixed sample delays e Reverb requires multiple buffer instances and read pointers The effects should be selectable and parameters of each audio effect should be controllable via user input 1 1 Previous works and current products Recent years has seen an increase in the use of FPGAs being used for high audio equipment that require truly parallel operations on multiple channels whilst maintaining ultra low latency An example of this is Euphonix choice to use the Altera Cyclone FPGAS in their high end audio mixing consoles There have been a number previous projects regarding audio processing on an FPGA Khan et al 2010 demonstrated their FPGA based design of an IZC controller for fetching sound from the audio codec on board the Altera DE2 development board This alone can be quite a time consuming task and requires a more in depth knowledge of IC and simulation options without the use of any existing IP proving how valuable IP blocks are to the designer to realise trivial functions Mike Hudson T Kaczmarczyk et al 2010 explores further the possibilities of creating a well finished and useable project with their
8. 6 4 For example bit six enables master mode as described towards the end of section 6 2 configuration 6 3 Serial parallel conversion The ADC ADC DAT data comes into the FPGA as a channel multiplexed serial stream which needs to be de serialised into N bit sized words for the left and right channel A SIPO Serial In Parallel Out and PISO parallel In Serial Out entity was created in VHDL and simulated using Altera Qsim to prove their functionality Figure 6 7 and Figure 6 8 show the simulation waveforms of the parallel serial converters 21 Mike Hudson Another symbol block was created Figure 6 5 from the serial and parallel converter entities to create one simple parallel out in interface channel1_in 15 0 serial_out i channel2_in 15 0 count_out 4 0 channel1_out 15 0 channel2_out 15 0 channel clk serial in Figure 6 5 Digital audio stream into the FPGA Figure 6 6 shows the actual clock waveforms of the configured Codec using the SignalTap logic analyser in Altera Ouartus To check the correct configuration of the codec the actual freguencies of the sample clock and bit clock were measured by dividing 50MHZ system clock by the amount of system cycles for one period For example 50E6 1024 48 83kHz for actual sampling frequency and 50E6 16 3 125MHz for the bit clock This is as expected however the sampling frequency is slightly more than 48kHz because the Codec
9. Figure 12 7 One all pass filter 20ms delay time and 0 7 gain sssssese 50 Figure 12 8 Three series all pass filters on the DE2 setting one 50 Figure 12 9 Three series all pass filters on the DE2 setting two occcccccccnoncnnnnnn 51 Fieure 12 10 Avero Teever in Logia Proa 52 Ei ure 12 Te vero SC LUI OTIO eaaa N UG Ci Oa GG UR 53 Figure 12 12 A Verb Sete TWO Y ada 53 Piau Scenes eleet ena Masin ou asas S6 Figure sl 3 2 Latency test SOUP ti 56 Figure 13 3 DE2 total system latency at 48kHZ occcccccccnnnnnonoooonaannnnnccnnccnonnnnnnnnnnnnnos 57 Figure 13 4 Logic Pro total system latency at 48kbZ 0ooooooooconcccccconoonanononaoooononnononononnnnos 57 Figure 14 1 Quadrature encoder outputs eere entere aea danni OT 60 Figure 14 2 Quadrature encoder connections to the DE2 GPIO header 60 Figure 14 3 Simulation of quadrature encoder VHDL code 61 Figure 14 4 Construction of the rotary control box c oooococcocccooooooooononnnnnononononononononnnnononnos 61 Figure 14 5 Eight rotary controls and 10 LEDS oooooccccccccooooononnnononnnnnnnononononnonnononnononnnnos 61 Figure 14 6 All eight encoder connected on the top level in Quartus 62 Figure 14 7 LCD when no effect has been selected ssssssesssesssssss 63 Mike Hudson F
10. Mapped Master clk in primary E sdrambuffer 5 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 6 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 7 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 8 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 9 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary Figure 8 10 Multiple SDRAM buffer components in SOPC Builder As established in section 1 2 the length of the buffer needed to be a minimum of one second The buffer delay was to be controlled by a seven bit value whose maximum value is 127 The resolution of the delay value was initially 10ms to obtain a maximum buffer size of 1 27 seconds This requires a buffer size of 245760 bytes 128 1920 The VHDL code in Code extract 8 4 shows how the first buffer base address and size 1s declared The second buffer starts at one address location after the end of the previous buffer signal base addr integer 0 base address of sdram signal buff size integer 245760 base _ addr size of circular buffer Code extract 8 4 3 9 Summary Using the Avalon interface for multiple read and write to memory makes design a lot more straightforward 37 Mike Hudson e This may not be the best method of creat
11. Mm KR tb The code was synthesised and tested on the DE2 board with an audio source connected to the input whilst the output was monitored through speakers Results were successful and audio could be heard on the line out This test confirmed that the audio samples were successfully writing to the SDRAM then being read out and sent through the codec and to the line out port of the DE2 Figure 8 7 shows the RAM state machine as a block symbol connected to the SOPC system Now all that was required was to modify the state machine to implement the function of a circular buffer 33 Mike Hudson a DIE AR ERAN sdrambuffer_v1 EP Ue RE D IRE LedramOaddress 31 0 A E address 31 0 aa 11 ledrm rset 1 oh ok read a A SdraroOreaddata 31 0 write SdramOwrtedata 31 D Thiramowaitrequest readdata 51 0 writedata 51 0 JP PE TERES S waitrenuest ch1 out tap1 15 0 cb E vira 292 a ial AN ch out tapi 15 0 ea A E DYCH a eee A Ig yno NF RR RES Figure 8 7 SDRAM state machine connected to SOPC System 3 6 Implementation of a circular buffer With the basic read and write functionality to the RAM working the state machine was modified to implement a circular buffer Another if statement was added to the original code to check on every increment if the pointer had reached the size of the buffer and if so then reset the pointer back to the beginning defined as the base address Code ext
12. VHDL SignalTap pdf Altera 2012 Introduction to SOPC Builder Available ftp ftp altera com up pub Altera Material 11 0 Tutorials VHDL Introduction to the A Itera SOPC Builder pdf David Katz amp Rick Gentile A Source of Information In Clive Maxfield 2009 FPGAs World Class Designs Oxford Elsevier Ch 8 67 Mike Hudson R C Cofer amp Ben Harding A Source of Information In Clive Maxfield 2009 FPGAs World Class Designs Oxford Elsevier Ch 7 Tomasz Kaczmarczyk Tomasz Henisz Dominik Stozek 2010 DGN 1 Digital Guitar Effects Processor Available http dgn teamovercrest org Last accessed January 2012 Udo Zolzer Ed 2002 DAFX Chichester John Wiley amp Sons Volnei A Pedroni 2010 Circuit Design and Simulation with VHDL Cambridge Massachusetts MIT Press 68 Mike Hudson 17 Appendices 17 1 Quartus II screenshots SOPC system LL rr 9RR GR EINEM Interface controls gt Audio effects 69 Mike Hudson 17 2 Project photographs Figure 17 1 Control box T v Hi a TE e YAA EL dor 23 TUA WN MANAW AWS E mNOMEMNM m mm mmm PAIN rE d gen E intl Bute DE IATA PERCERCRE ETRE RCE itr HHHHETHEEDGUDETTTI TA t 4x w L LP IPIITr pem i J l Ps so BE Bi J Figure 17 2 Control input via GPIO on DE2 board 70 Mike Hudson y qn 1 Figure 17 3 T
13. VHDL architecture for the multiply function begin product lt a in reg 0 amp g val amp 11111111 y out lt product 31 amp product 29 downto 15 sync a_ in with system clock before multiplication process clk reset begin 1 2 3 4 5 6 7 8 9 if reset 0 then a in reg lt others gt 0 elsifrising edge clk then a in reg lt a in end if end process end architecture beh Code extract 7 1 72 Sum The samples were converted to fractional form using the fixed package library see line 1 amp 2 of VHDL Code extract 7 2 This allowed for straightforward addition of two sample values represented as logic vectors library IEEE PROPOSED use IEEE PROPOSED FIXED PKG ALL begin convert to fractional form bits negative indexes 25 Mike Hudson a lt to sfixed a in 0 15 b lt to sfixed b in 0 15 y lt atb y out lt to slv y 0 downto 15 convert back to logic vector end architecture Code extract 7 2 73 Mixer A mixer was implemented in from the previously designed multiply and sum blocks in order to control the ratio of the original signal to the affected signal Figure 7 1 Figure 7 2 shows the implemented mixer design as a reusable Quartus block symbol dry signal multiply multiply wet signal Mixed sienal gt Amount ratio Figure 7 1 Dry wet ratio control of affected and original signal
14. of them The introduction of Steinberg s Virtual Studio Technology VST in 1996 played a key role in allowing this to happen This significant development has paved way for completely new instruments and made musicians and technicians look at making music 1n a different way spawning hundreds of new music genres The last decade of music provides a good audible example of how the development of technology directly influences music The underlying concepts and theory of DSP may not have changed much but the technology on which they are implemented continues to develop at a phenomenal rate The change in embedded multimedia processing technology has demonstrated especially in the last decade how fast the technology is moving However as the need for higher speed lower cost and smaller size increases demanding digital processing applications are beginning to see the limitations of traditional sequential instruction DSP processors Mike Hudson Although not new technology FPGAs are starting to be used more and more to overcome the limitations of general purpose DSPs in applications where low latency is critical 1 2 Project aims and objectives The aim of this project 1s to create a real time digital audio processor using an FPGA to overcome the problems with latency experienced with traditional computer software Along the way comparisons will be made discussing advantages and disadvantages of related technology and developmen
15. then connected to the SDRAM controller named sdram 0 See Figure 8 3 E audio and video config 0 Audio and Video Config clock reset 3 avalon av config slave Avalon Memory Mapped Slave clk in primary 0x00101000 Ox0010100 E sdram_0 SDRAM Controller cik s1 Avalon Memory Mapped Slave clk_in_primary Ox00000000 oxon7 f altpll_0 Avalon ALTPLL clk_in_primary 0x00101010 Ox0010101 E sdrambuffer 0 sdrambuffer clock reset Figure 8 3 Component connection to the SDRAM Controller in SOPC Builder The SOPC system was generated as VHDL code and connected up in the top level of Quartus The top right of Figure 8 4 shows the signal connections to the external SDRAM chip and the bottom left and right show the signals that will be connected to a RAM state machine zs addr from the sdram O0 11 0 zs ba from the sdram O 1 0 zs cas n from the sdram 0 zs cke from the sdram 0 zs cs n from the sdram 0 zs dq to and from the sdram O 15 0 zs dgqm from the sdram O 1 0 zs ras n from the sdram 0 ill a ee MT TW AA NU e c O ERAS address_from_the_sdrambuffer_0 31 0 readdata_to_the_sdrambuffer_0 31 0 wr o 0 es read from the sdrambuffer 0 reset to the sdrambuffer 0 ee n a rs al eu UM write from the sdrambuffer 0 waitrequest to the sdrambuffer 0 r a es wW ritedata_from_th e_sdrambu ffer_0 31 0 s os 9 a we RU m 9 V N vw Ter Figure 8 4 System top level connections in Quartus 3l Mike Hudson
16. was created in VHDL DAC DAT ADC DAT An audio source was connected to the line in which gave acceptable results when monitored on the audio line out To confirm the audio data stream was coming into the FPGA and not just looping back in the ADC one channel was disconnected in the top level Quartus block schematic file Figure 6 5 This was re compiled and loaded onto the FPGA Only the connected channel was audible on the line output confirming the digital data is being routed into the FPGA 6 2 Summary At this point the system can be illustrated by the block diagram in Figure 6 9 Once this configuration was established and working correctly the next stage was to implement the digital effects to go in the audio effects block In terms of design this 1s the first major step completed EC Configuration serial to parallel audio WM8781 effects ADC DAC here parallel to serial Cyclone II FPGA 24 Mike Hudson 7 Building a project library of Quartus block symbols A project library of reusable blocks was built up throughout the length of this project starting with the basic building blocks as discussed 1n section 8 2 7 1 Multiply A general purpose multiply function was implemented in VHDL and 1ts symbol added to the library The multiplier was tested on an audio VU meter to ensure a maximum gain of unity when the 7 bit gain control was at its full value of 127 Code extract 7 1 shows the
17. 26 Mike Hudson reset mix 6 O a_in 15 0 b in 15 0 Figure 7 2 Wet dry ratio block symbol in Ouartus 7 4 Small delay line in hardware For processing that just requires a sample delay of a few samples 1t was considered a waste of resources to use a dedicated buffer Instead a hardware delay line was created in VHDL which consists of a series of registers clocked by the sample freguency The simulation in Figure 7 3 shows the delayed outputs from the first four registers Code extract 7 3 shows how an array of clock registers were be created in VHDL using a for loop type buffer array is array 0 to 128 of std logic vector 15 downto 0 signal tap buffer array begin process ch clk is begin if rising edge ch clk then tap 0 lt chl in for i in 1 to 126 loop tap i lt tap i 1 end loop OO Y WA NM Aa GU hh end if end process chl out lt tap 0 chl out delayl lt tap 1 chl out delay2 lt tap 2 chl out delay3 lt tap 3 chl out delay4 lt tap 4 Code extract 7 3 21 Mike Hudson V9VVUdadyYds o ps 20 0 ns 40 0 ns 60 0 ns 80 0 ns 100 0 ns 120 0 ns 140 0 ns 160 0 ns Name Ops ck Sn E iun e oad cosacos E D a dtou doya K oo faut n 3 cnt_out delay f wnn nnt n 4 chi ut delaya K see famu Figure 7 3 Delay line simulation in Ouartus simulator 7 5 Summary Building up a custom library of components and instantiating them multiple times in a hierarchi
18. 6 0 A WN mm We GPIO_0 7 rotary_seven 6 0 i hohes as MAE e gt cr GPIO_0 8 rotary_eight 6 0 cu gt GPIO_0 9 A TO PO HE GPIO_0 10 D R ee mr GPIO_0 11 O al GPIO_0 12 Ae gt GPIO_0 13 ien els MEME Co e GPIO_0 14 GPIO 0 12j OSO GPIO_0 15 Figure 14 6 All eight encoder connected on the top level in Quartus 14 4 Visual feedback The two immediate methods of display on the DE2 board were considered e The VGA display output e The on board 16x2 LCD display 62 Mike Hudson Both display methods were not perfectly suitable the LCD was too small and a VGA monitor would probably be too big However the chosen method of display was the on board LCD display since a VGA monitor was not always available In order to easily write to the LCD a NIOS II processor was included in the system This allows the use of the familiar printf function to be used in the C language The final work provides the user with visual feedback using the LCD to display the selected effect and how its parameters are mapped to the controller Values can be represented in a bar format or binary format using the 10 LEDs on the control box The LEDs display whichever value was altered last dynamically displaying values For example to view the value of a parameter a slight nudge of the encoder will display its associated value The eight switches on the DE2 board used to select an audio effect are fe
19. CW T T s o o La o Yr e 0 1 edge Figure 14 1 Quadrature encoder outputs The encoders were interfaced using the DE2 boards general purpose GPIO ports each consisting of 32 available bidirectional pins Figure 14 2 Quadrature encoder O A34 vcc33 OM I A O A30 135 O ASZ O A34 Figure 14 2 Ouadrature encoder connections to the DE2 GPIO header The code to read each encoder was written in a VHDL process The pseudo code for one state of the encoder is shown in Code extract 14 1 60 Mike Hudson if A is rising then if B 0 and count 127 then increase value count lt count l elsif B 1 and count 0 then decrease value count lt count I end if end if Code extract 14 1 This VHDL code was repeated for the other three conditions B rising A falling B falling Figure 14 3 shows the functional Quartus simulation for a clockwise motion of the encoder Encoder in forward direction gt CLK BO ma Bo ree Ls gt B BO EP gt vaueout ALO tm 10 A B X mj a EY ET O Y YD Increase 1n value Figure 14 3 Simulation of quadrature encoder VHDL code A box containing 8 rotary encoders was constructed Figure 14 4 and connected to the general purpose inputs on the DE2 via a 40pin ribbon cable Figure 14 5 shows the completed control box 6 8 O 2d o e e e CGU E REP RR REA DADA Figure 14 4 Constr
20. II software package an Altera device was preferred The choice of development board was narrowed down to two similar boards from Altera the DE1 and the DE2 both based around a Cyclone II FPGA Essentially the DEI appears to be a slightly downgraded version of the DE2 in terms of on board peripherals The Altera DE2 development board was chosen due to 1t meeting all reguirements and being readily available However 1f this was not the case the DE1 board may have been a more cost effective option at less than half the price of the DE2 11 Mike Hudson 4 The Altera DE2 development board 4 1 Features The DE2 development board is intended to target the educational market and offers a wide range of features suitable for many different kinds of projects Features that are of interest to this project include e Altera Cyclone II 2C35 FPGA device with 33000 logic elements 512 Kbyte SRAM e 8 Mbyte SDRAM e 4 pushbutton switches e 18 toggle switches e 18red user LEDs e 9 green user LEDs e 50 MHz oscillator and 27 MHz oscillator for clock sources e 24 bit CD quality audio CODEC with line in line out and microphone in jacks Two 40 pin Expansion Headers with diode protection Figure 4 1 gives an overview of the readily available peripherals on the DE2 board 50 Mhz 27 Mhz Extin Cyclone Il FPGA 2035 EPCS16 Config as Device Blaster Figure 4 1 The Altera DE2 inputs and outputs Altera DE2 manu
21. Large reverb tails can be created with the Averb e The sound of the Averb is far superior to the DE2 reverb in terms of simulating a real acoustic space e The DE2 reverb has no pre delay 12 5 Summary It 1s difficult to make a good comparison between the Averb and the all pass reverb implemented on the DE2 because the Averb 1s parameterised Also the performance of the reverb cannot be evaluated from plots and data alone 1t needs to be listened to This creates the need for a lot of experimentation and time to obtain the desired affect It is also worth noting that on the spectrogram plots of the Averb there appears to be a large pre delay Whilst some of this delay may be due to the nature of the reverb a small amount is probably due to latency which was not taken into account at the time of testing Due to time constraints on this project the work on the reverb effect was cut a little short and the three all pass structure shown in Figure 12 5 was used for the reverb in this project It was the intention that various different reverb structures be 1mplemented tested and compared and the best one chosen for this project Possible improvements to the reverb may include e Using nested all pass filters e Simulating pre delay e Parallel comb filters to create early reflections 54 Mike Hudson e Using a low pass filter to create frequency damping effects e Ensuring all delay values are mutually co prime e Proper
22. S processor 65 Mike Hudson e To further demonstrate the major advantage of hardware true parallel processing e More elaborate and demanding audio effects e High quality audio For example 24 bit at 96kHz 66 Mike Hudson 16 References A R M Khan A P Thakare S M Gulhane 2010 FPGA Based Design of Controller for Sound Fetching Codec Using Altera DE2 Board International Journal of Scientific 7 Engineering Research Altera Euphonix chooses Altera Cyclone FPGAs Available http www prnewswire com news releases euphonix chooses alteras cyclone fpgas and nios ii processor for audio mixing console product line 74981927 html Last accessed January 2012 Altera 2006 DE2 User Manual Available ftp ftp altera com up pub Webdocs DE2 UserManual pdf Last accessed January 2012 Altera 2011 Audio Video Configuration Core Available ftp ftp altera com up pub Altera Material 11 0 University Program IP Cores Audio _ Video Audio and Video Config pdf Altera 2011 Clock Signals for Altera DE Series Boards Available ftp ftp altera com up pub Altera Material 11 0 University Program IP Cores Altera _ UP Clocks pdf Altera 2011 Introduction to the Altera Nios II Soft Processor Available ftp ftp altera com up pub Altera Material 11 0 Tutorials Nios2 introduction pdf Altera 2011 SignalTap II with VHDL Designs Available ftp ftp altera com up pub Altera Material 11 0 Tutorials
23. SSDISANDCOBIOLGP OLG out did 29 8 4 Reading writing to and from the SDRAM sese 30 5c RAM Stale THO C DITIO AAA YN HF Y so tubos ei tradi FRY FHEWR T HHE WA 32 5 0 implementa onor a Circular DUE naaa Ed EM IND MEM do aa 34 Ser JVbultiplesead Pontes 36 o Multiple DUTICE IMS AN COS sedis euo o an dod ns ga uem mises Od DR dyd beue RES ERU P uS Usa SU US DOOR dU 36 BuU SS DI coo steer nL O Nu RC re 37 A E a 39 A lc a A E EE A E EN AOT E T eas 39 I AES into TO 41 LOL State variable tl ls 41 10 27 DISO Oera a anillas 43 BE Flansereifecn ae A TT 44 12 Reverb ration Cire Cl isecaseccscecssccacecensceccccccatewnsensceeecesccessaadnasnsstesscassaveseceseanesssdinasansaeedcctscsasaee 46 ISL ADA Old 46 12 2 Thea Das TU A AAA 46 T2231 Multiple all pass ers a met ec ete UMP M MM 48 12 3 pulse fOspolise CS A tete sce eeu EE See NR P MD M SNC DU IIS 48 12 4 Comparison with a commercial software reverb oooocccnnncnnnnnonoonnncnnonnnnnnnnnonanonoconannnnns 51 NES HDMI ER UT Uer ERN 54 VI Mike Hudson 153 WACO CY test a AN o AS EAN cis 56 13 1 Comparison with computer SO LWAEG isis S6 E doo o mo RR Y NY AN HN Y NI N Y YR RYN FF 57 14 User Interia Onei E NC AG 59 IN Considera ons enen E 59 AZ Ouadrature rotary cnCoder ae a Pu Pa A ee ee aa 60 da MA Sennen A EE AGNE 62 Ma Visual tec dae E Ee ee 62 145 Discussion and SUMMA Ni 64 I5 YC OP CIISIOD Sana adan ias 65 SL EUA e d RE TT Ri 65 TO a a
24. a DE2 manual 12 Figure 6 1 Audio codec schematic Altera DE2 User manual 17 Figure 6 2 left justified format WM8781 datasheet ooooooococcconooooooononooonn nono nnnononononnnnos 19 Figure 6 3 Master mode WM8731 datasheet 20 Figure 6 4 WM8731 register map WM8731 datasheet ooooooonnnnncccccccnnnnnnnnnnnnnnss 21 Figure 6 5 Digital audio stream into the FPGA esee 22 Figure 020 Codec waveform g iS 23 ia RC Y I Y CF Y EF HY 23 Figure 6 9 Parallel To senial ueu di o YO O 23 Figure 6 9 Digital audio interfaced to the FPGA cooccccccccccocooonoooon nono nonononnnnnnnnnnnonnonononnos 24 Figure 7 1 Dry wet ratio control of affected and original signal 26 Figure 7 2 Wet dry ratio block symbol in Quartus ooooooconcnonooononoonn ono nononnononononononononnnnos 27 Figure 7 3 Delay line simulation in Quartus simulator ccsesseessssessssssseesseeeseseens 28 Figure 8 1 SDRAM Controller with Avalon interface block diagram Altera Embedded P ripherals IP User Guide a du ts ad 30 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 0 Figure 8 7 Figure 8 8 Figure 8 9 SOPC Builder custom component signals ooooooonnnnnnnccccnnnnnnnnnnnnnnnnnononannnnos 31 Component connection to the SDRAM Controller in SOPC Builder 31 System top level connections in Quart
25. al 12 Mike Hudson The DE2 board features a Wolfson WM8781 24 bit sigma delta audio ADC DAC designed for consumer audio applications Throughout this report the term audio codec will be used in reference to the Wolfson WM8781 a single device that has an ADC and DAC running off the same clock These features appear to satisfy the reguirements of the project established in section 25 13 Mike Hudson 5__ Altera Ouartus II 5 1 Introduction Altera Quartus II 1s the software used to create projects for analysis and synthesis of HDL designs It includes several tools and features to help with HDL design including e VHDL and Verilog HDL input e Block schematic entry e Pin assignment editor e Programmer tool e Megafunctions IP design blocks e SOPC Builder Projects can consist of a mixture of Verilog and VHDL hardware description language For this project VHDL will be used for all HDL input due to familiarity with this language However some pre made design blocks such as the Audio and Video Core used to configure the audio ADC will generate Verilog code Altera Quartus II comes with a range of building blocks of pre made HDL design blocks referred to as IP core It 1s proposed that IP core be used in this project for realising trivial tasks and functions such as configuration of peripherals which could be very time consuming to design and test 1n HDL from scratch The free web edition version of the Qu
26. artus II v11 0 software is used throughout this project 5 2 SOPC Builder The SOPC System On Programmable Chip builder is a development tool that comes packaged with the Altera Quartus II software SOPC builder has a library of common components and intellectual property including memory controllers interfaces and peripherals Components are to be chosen from the library and are automatically connected through the Avalon bus interconnect fabric Custom components can be 14 Mike Hudson made and saved to the library to be instantiated anywhere in the project A SOPC builder component is described by a tcl file which describes its properties and interface behaviours as well as associated HDL and available signals on the Avalon bus The VHDL 1s generated from the SOPC builder and integrated into the project by connecting it on the top level either in HDL or using a schematic file 15 Mike Hudson 6 Interfacing Audio to the audio to the FPGA 6 1 The Wolfson WM8781 audio ADC This section introduces the on board audio codec and gives an overview of 1ts configuration and 1ts various modes of operation The default mode of the codec 1s an internal signal loop back which connects the audio input signal to the audio output The codec features stereo line in and out as well as mono microphone level audio input Its features include e Standard sampling frequencies of 8 32 44 1 48 88 2 and 96kHz e C serial control interface
27. aving multiple read pointers whose locations can be specified by the designer usually with reference to the write pointer This concept can be visualised in Figure 2 3 where the read pointer is lagging the write pointer read pointer write pointer m d circular buffer Figure 2 3 Circular buffer concept Mike Hudson The multiplier and accumulator are relatively straightforward to implement However the choice of floating point or fixed point arithmetic needs to be established from the start 2 4 Digital filter example A common operation in digital processing 1s the digital filter Figure 2 4 demonstrates how an FIR filter could be represented in hardware at register level Each sample word 1s clocked through the registers Each sample from x to x n x being the input sample and x n being a previous input sample are multiplied by a coefficient and accumulated at the summing point multiply accumulate or MAC The coefficients define the specification of the filter whilst the amount of coefficient multipliers aka taps directly determines the filter order For an IIR filter the diagram could be modified to include delayed versions of the output are also added at the summing point Data Out Figure 2 4 Parallel FPGA FIR filter structure Maxfield C 2006 2 5 Conclusion Mike Hudson The nature of an FPGA allows for straightforward implementation of many digital processing structures that reguire on
28. cal structure is a valuable aspect of system design Instantiating custom library components in a hierarchical structure is very useful The use of the fixed package for the sum block may have not been the best option since it cannot be readily synthesised for simulation and is not a standard IEEE library The standard logic signed package may have been a better option For the multiplication of a sample with an arbitrary value the sample needs to be synchronised to the system clock edge This is not necessary when multiplying with a fixed constant The FPGA logic elements get used up guickly when large hardware delay lines are created For delays of more than 100 or so samples the dedicated RAM will be used Mike Hudson 8 Implementing a buffer in RAM 8 1 Requirements The requirements for the buffer are as follows e Must be able to seamlessly wrap around to implement a circular buffer e At least one second in length e Must be able to have multiple read pointers e The ability to modulate read pointer values in real time e The ability to run multiple independent circular buffers simultaneously The buffer length only needs to be one or two seconds at the most A reverb effect typically requires less than 80ms delay whilst an echo would be anything between 80ms up to a few seconds A buffer of one second in length at a sampling rate of 48kHz at 16 bit for both left and right channels would require 192000 bytes 48000 32 8
29. ck of various parameters e Simultaneously vary different parameters e Aid in testing e Make the project useable Three methods of user input were considered e Switches on the DE2 board e Keys on the DE2 board e Quadrature rotary encoders The DE2 board has 17 switches which could be used to represent binary values for the various effect parameters This was not considered a very user friendly method of input Rotary encoders were used because of their versatility and intuitive nature turn clockwise to increase value Quadrature encoders also have many other advantages such as e Resolution can be altered e Ease of control over minimum and maximum values Do not have absolute values as opposed to resistive potentiometers therefore allowing one encoder to alter multiple values e One encoder only uses 2 digital inputs on the FPGA e Velocity can be detected to alter the value rate of change 59 Mike Hudson 14 2 Ouadrature rotary encoder A guadrature rotary encoder outputs two pulses when turned 90 degrees out of phase with each other The direction of the decoder can be determined by testing 1f one of the channels 1s high or low at the falling or rising transition of the other channel Four possible states are available in one channel cycle and the associated variable is incremented or decremented by one Figure 14 1 shows how the outputs of the encoder are used to determine direction o eo C o E
30. d into the SOPC system on the top level to enable their values to be available on the Avalon bus and read in a NIOS II program The NIOS program gives a different display depending on the status of the switches The display shows what parameters are currently mapped to which rotary encoder whose values are dynamically mapped depending on which effect 1s selected See Figure 14 7 and Figure 14 8 Figure 14 7 LCD when no effect has been selected 63 Mike Hudson a TDi ne FBG FEF ART E 3 Figure 14 8 Reverb effect selected placement of text corresponds to a rotary encoder 14 5 Discussion and summary The performance of the rotary encoders is still not entirely satisfactory since they have no de bounce mechanism in place An improvement would be to use some de bounce circuitry possibly in the form of a capacitor filter circuit in the rotary control box Nios II was not entirely necessary for project work up to this point since it was only used to provide ease of writing to the LCD The intention is that a more elaborate user interface will be implemented in the future which will be driven by the NIOS processor 64 Mike Hudson 15 Conclusion The completed project has fulfilled all of the initial aims and objectives Effective time management along with the excellent teaching resources from Altera have played a large part in making the project a success A library of basic building blocks was established and u
31. e added to the state machine for every read pointer tap inc write pointer read state read2 state idle state r write state Figure 8 9 Multiple read pointers in the RAM state machine 8 8 Multiple buffer instances Some audio effects a reverb effect for example may require multiple independent buffers and each with multiple taps Using the Avalon bus for read and write operations to and from the SDRAM makes it very easy to perform multiple simultaneous read and writes to the SDRAM The custom Avalon memory mapped component sdrambuffer previously created can be instantiated multiple times and all can be connected up to the same SDRAM controller in SOPC Builder Figure 8 4 Each instance of the 36 Mike Hudson sdrambuffer component has its own state machine writing and reading to its own allocated section of memory using a different range of addresses E sdram_0 SDRAM Controller clk 81 Avalon Memory Mapped Slave clk in primary E sdrambuffer 0 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 1 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 2 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 3 sdrambuffer clock reset avalon master Avalon Memory Mapped Master clk in primary E sdrambuffer 4 sdrambuffer clock reset avalon master Avalon Memory
32. e PUR 67 17 IXDDOHUICOS iii deta 69 LA Quartus IbsSereensBols ue A Fi 69 AA os Re end O AY N AN HWFA HER Hn 70 VII Mike Hudson Nomenclature and abbreviations ADC AIFF CODEC DAC DE2 DSP FIR FPGA HDL FC IC IDE IEEE IP LSB MAC MSB PISO PLL SIPO SOPC VHDL Analogue to Digital Converter Audio Interchange File Format Refers to audio ADC DAC device Digital to Analogue Converter Refers to the Altera Development and Education board Digital Signal Processor Finite Impulse Response Field Programmable Gate Array Hardware Description Language Inter Integrated Circuit Serial Protocol Integrated Circuit Integrated development Environment Institute of Electrical and Electronics Engineers Intellectual property Least Significant Bit Multiply Accumulate Most Significant Bit Parallel In Serial Out Phase Locked Loop serial In Parallel Out System On Programmable Chip VHSIC Hardware Description Language VIII Mike Hudson Table of Figures Figure 2 1 a An analogue signal b Digitised PCM signal c Digitised PCM signal with fewer bits of precision Katz D amp Gentile R 2009 ooooocononnnccococococonononnnnnnns 6 Figure 2 2 Digital audio processor example volume Udo Zolzer 6 Figure 2 3 Circular bur eriGon DL ee elio Deae Puoi a T Figure 2 4 Parallel FPGA FIR filter structure Maxfield C 2006 8 Figure 4 1 The Altera DE2 inputs and outputs Alter
33. ency response with the delay at an instantaneous value of 10 samples As the delay 1s increased more notches get introduced and they shift along the spectrum 44 Mike Hudson Notches shift along the Freguency response Figure 11 3 Original signal mixed with a ten sample delayed version This effect is used as the basis of many other audio effects such as the chorusing effect and other extensions of phasing type effects 45 Mike Hudson 12 Reverberation effect 12 1 A basic reverb The basic idea of a reverb was first created using a variable delay with its signal fed back to create a series of delays that fade out over time feedback gain must be less than one Equation 17 1 shows how the gain parameter 1s calculated to control the amount of feedback and to determine the amount of reverb reflections Figure 12 1 shows this structure comb filter delay ru w gain Figure 12 1 Comb filter g 0 001 RVI 17 1 Where 1 is the delay time in ms and RVT is the total reverb time of the comb filter Reverb time is defined as the time it takes for the output to fall to zero 60dB when an impulse is applied This form of reverb was implemented on the DE2 board but did not give very satisfactory results The sounds seemed to resonate at the high frequencies and could completely alter the tone depending on the delay Further techniques were explored 12 2 The all pass filter The all pass filter is effect
34. ependently controlled feedback delays The first one is as Figure 9 2 describes and the second has an adjustable filter in the feedback path which gives an interesting variation on the standard echo effect 40 Mike Hudson 10 Audio filter Initially the filter design and analysis tool fdatool in Matlab was experimented with The fdatool provides a graphical interface for the design and analysis of digital filters by setting desired specifications and then generating the HDL to use in the Ouartus project A low pass FIR filter was first generated and loaded to the DE2 board which proved successful This would be appropriate for fixed freguency filters but the aim was to have a filter whose cut off freguency could be varied in real time Other filtering techniques were investigated 10 1 State variable filter The state variable filter s suitability has been proven in many audio applications digital and analogue and was found to be the best solution for the following reasons e Low pass high pass band pass and band reject signals are all available simultaneously e Its tuning coefficients frequency cut off and damping factor are independent of one another allowing both values to be easily varied independently e Straight forward to implement highpass Bandpass Lowpass From Audio Device Delay4 Delay2 Delay3 Figure 10 1 State variable filter 41 Mike Hudson The outputs of the state variable filte
35. erb plugins that come packaged with Logic and all are different in terms of their sound parameters and versatility Impulse responses were obtained for three different settings on the Averb reverb See Table 12 1 for the different settings 51 Mike Hudson XC reverb impulse test o View Show Channel Strip Show insert v Bypass Compare lt default Figure 12 10 Averb reverb in Logic Pro Setting one Setting two Pre delay 20ms Table 12 1 Three different settings in Logic s Averb reverb plugin Figure 12 11 and Figure 12 12 show the response from the Averb reverb with setting one and two respectively 32 Mike Hudson x10 Averb setting one time domain impulse 8 6 9 a 4 E 2 Time Seconds Averb setting one spectrogram 140 120 100 8 60 40 20 px on n h co Frequency z 10 Hz ro e Figure 12 11 Averb setting one x10 Averb setting two time domain impulse Amplitude Time Seconds verb setting two spectrogram Lo Gas onds 4 3 2 1 Frequency x10 Hz 0 Figure 12 12 Averb setting two 53 Mike Hudson Key differences of the DE2 all pass reverb and Logic s Averb reverb e The DE2 reverb reflections appear to be very periodic compared to the Averb e The DE2 reverb has a more uniform frequency response e The response of the Averb appears to be a lot more dense at low frequencies
36. es of the codec can be utilised through its IC interface such as volume control and different filtering options These extra options will be left at their default values as g1ven from the audio and video IP core since all that 1s needed 1s the digitised audio and 20 Mike Hudson any further processing would be done on the FPGA itself Table 6 2 shows the actual values used to configure the codec RO 00h LRINBOTH LINMUTE LINVOL 4 0 O0 1001 0111 Left Line In R1 01h RLINBOTH RINMUTE RINVOL 4 0 O0 1001 0111 Right Line In LRHPBOTH LZCEN LHPVOL 6 0 O0 0111 1001 Headphone Out R1 01h RLHPBOTH RZCEN RHPVOL 6 0 O0 0111 1001 Right Headphone Out R4 04h SIDEATT 1 0 SIDETONE DACSEL BYPASS INSEL MUTEMIC MICBOOST 0 0000 1010 Analogue Audio Path Control R5 05h HPOR DACMU DEEMPH 1 0 ADCHPD 0 0000 1000 Digital Audio Path Control R6 06h POWEROFF CLKOUTPD OSCPD OUTPD DACPD ADCPD MICPD LINEINPD 0 1001 1111 Power Down Control R7 07h BCLKINV MS LRSWAP LRP IWL 1 0 FORMAT 1 0 0 1001 1111 Digital Audio Interface Format R8 08h CLKODIV2 CLKIDIV2 SR 3 0 BOSR USB O0 0000 0000 NORMAL R9 09h Active O0 0000 0000 Active Control R15 0Fh RESET 8 0 not reset Reset Figure 6 4 WM8731 register map WM8731 datasheet R7 7h07 digital audio interface format 0100 0001 9 h041 Table 6 2 WM8781 modified register values Table 6 2 shows the modified bits in register seven the highlighted row in Figure
37. esting the audio effects Audio Input Built in Input Audio Output Soundflower 2ch Sample Rate Hz 96000 Waveform Energy Crop Fade 40 60 20 80 100 Monitor Monitor Channel 1 2 Sal Monitor Level 4 120 d8 Monitor Mute Sweep Generator Sweep Channel 1 Soundflower Test Tone 1 kHz ed on Sweep Level 12 0 dB Sweep Length 10 s mw mw Reverb Time 20s gt C Preroll Sweep T r Position Mic Position Input S R Level Process jo sa a al Deconvolve Audition IR Create Space Designer Setting AAA reverb testing 3 i o o Um i ES a ES a Inspector Preferences Settings Auto Zoom Automation Flex SetLocators Repeat Section Crop gt MIDI Thru t d sf H EtEdit v Track v Region y MIDI v b reverb impulse test Global Tracks Xx amp reverb impulse test o View v Show Channel Strip Show Insert v Setting Setting SS Bypass Compare 4 gt Wdefault EQ Inserts Inserts Predelay Reflectivity AVerb Sends 1 0 Input 1 Stereo Out m s O Bnce Mixer Sample Editor Piano Roll Score Hyper E 01 00 00 00 00 1 1 120 0000 1 3 1 1 130 Figure 17 4 Apple s impulse response utility and the Logic Pro computer software 71
38. igure 14 8 Reverb effect selected placement of text corresponds to a rotary encoder 64 Figure 7 I Control box uu Y I Y RF Y O GY A 70 Figure 17 2 Control input via GPIO on DE2 board ooococcccccoconononononnnnnnnnnnnnnnnnonononononononos 70 Figure 17 3 Testine the audio clear 71 Figure 17 4 Apple s impulse response utility and the Logic Pro computer software 7 1 XI Mike Hudson 1 Introduction 1 1 Digital audio processing Digital audio processing offers a huge amount of flexibility and an almost infinite amount of possibility to manipulate and process audio in a way that would not be possible using analogue techniques In the last two decades or so the music studio has evolved drastically from consisting of predominantly analogue equipment to nearly all digital equipment based around a computer or digital audio workstation A traditional recording studio would have several rooms full of analogue hardware mixers effects units and huge multi track recorders using magnetic tape An enthusiastic technician may spend days going through their huge repository of equipment to find the perfect reverb effect for a recording With the development of digital signal processing DSP and computer processing power increasing at an exponential rate 1t has become possible to have all those analogue reverb units and amplifiers emulated in software on even the most modest of personal computers using the click of a computer mouse to audition each
39. ing a variable delay There is a noticeable zipping sound when the read pointer 1s varied by a considerable amount A better solution may be to interpolate between samples to create smoother transition e Using IP for example the SDRAM controller core greatly speeds up the design process 38 Mike Hudson 9 Echo effect 9 1 Implementation A delay effect was first realised using a buffer instance with a read pointer whose distance from the read pointer determines the delay The delayed signal was then mixed with the original non delayed version See Figure 9 1 To Audio Device From Audio Device Variable Delay Figure 9 1 Variable delay To create the echo effect the delay was added into a feedback path and scaled by a multiply block to create a decaying series of the delay Figure 9 2 From Audio Device Devicel multiply ben elay Figure 9 2 Variable delay feedback 39 Mike Hudson io eh CEPIT sys_cik ch1_out 15 0 TERRY ch_cik ch2_out 15 0 AU NN reset sdram0address 31 0 M oT ae ch1_in 15 0 sdramOread sdffm reset ch2_in 15 0 sdramOw rite sdr mOreaddata 31 0 sdramOreset sdramOw ritedata 31 0 sdf amp PhOvaitreguest sdramOreaddata 31 0 sdramOw aitreguest delay 1 6 0 fb1_gain 6 0 delay 2 6 0 fb2 gain 6 0 fb2 freg 6 0 fb2 q 6 0 Figure 9 3 Delay effect symbol on top level in Quartus The final delay effect gives two ind
40. ing manufacture data sheets of selected tools e Reinforcing my understanding trying out theory in Matlab Simulink Once the FPGA development board was chosen the key aspect of making the project a success was to get to develop a good working knowledge of the associated tools and software 3 2 Selection of Tools and Software The choice of tools and software was carefully considered The main requirements for the FPGA development board 10 Mike Hudson e JO expansion e On board audio ADC DAC e LCD Display e User input switches e On board RAM e Well documented The choice of the FPGA device was between the two main manufactures of FGPAs Xilinx and Altera Rather than considering the specification of individual FPGA devices for the suitability of this project the features and specification of FPGA development boards as a whole were reviewed It was assumed that a relatively recent FPGA would easily have enough logic elements to fulfil the aims of this project It was decided that good documentation and tutorial material and support from the manufacturer would be vital to the success of this project Both Xilinx and Altera provide free design software and comprehensive guides and reference designs to get started The Altys Spartan 6 Xilinx FPGA and the Altera DE2 development board both met the requirements for this project offering all relevant peripherals and features However due to familiarity with the Altera Quartus
41. ively the same as the comb filter but with a feed forward path in addition to the feedback path Figure 12 2 The all pass filter has a flat frequency response unlike the comb filter and allows for a frequency independent delay Figure 12 3 shows how the all pass filter was realised in practice 1n Quartus as a block 46 Mike Hudson diagram A new Ouartus symbol containing the all pass structure was created Figure 12 4 gain Figure 12 2 All pass filter The reverb eguation 17 1 also applies to the all pass filter negative m ch1_out 15 0 ch2_out 15 0 sdram6address 31 0 sdram6read sdram6write sdram6writedata 31 0 ch2 in 15 0 sdram reset sdrambreaddata 31 0 sdram6waitreguest Figure 12 4 All pass filter in Ouartus II 47 Mike Hudson The single all pass filter was programmed to the DE2 to prove 1t was working correctly and to hear its effect on audio This did not sound like a reverb sound but more like a flutter echo where individual delays could be heard See Figure 12 7 for the impulse response and spectrogram plot of the single all pass filter measured with the effect mix at 5090 12 2 1 Multiple all pass filters Three series all pass filters were implemented in an attempt to create a denser sounding reverb APl AP2 AP3 Figure 12 5 Multiple series all pass reverb Adding these extra all pass filters made a significant difference to the reverb effect to the point where
42. kers in Figure 13 3 and Figure 13 4 is 10ms 0 00 09 570 a l Figure 13 3 DE2 total system latency at 48kHz 0 00 Pw 0 00 dos gt 10ms Figure 13 4 Logic Pro total system latency at 48khz 13 2 Summary This test demonstrates the potential advantages of an FPGA for a low latency solution to digital audio signal processing due to the parallel nature of its operation The following observations were made 57 Mike Hudson e A considerable amount of latency is introduced for every effect added to the chain on the computer software e The audio latency on the computer software would most likely be unsuitable for real time processing Especially for instruments and vocals where latency would be most noticeable e Audio latency on the DE2 is negligible and would be unnoticed e Total latency for the DE2 board will always be less than the time of one audio sample even when more effects are added It was noted that this was a rather crude method for testing latency Possible improvements to this test would be e Use a signal generator impulse for a consistent audio source e Use a dual channel storage oscilloscope with configured axis for more accurate readings e Could test both systems first with no effects then with effects to make a comparison and to determine the minimum system delay 58 Mike Hudson 14 User Interface 14 1 Considerations The aim of the user interface was to e Provide visual feedba
43. length independent and therefore easily allowing the word length to be changed at a later point if required Figure 6 2 shows how the channel clock is used to frame the left and right words on the serial bit stream with each bit being clocked on the falling edge of the bit clock When the channel clock goes high the serial data contains the left channel data with the MSB aligned to the left LEFT CHANNEL RIGHT CHANNEL DACLRC ADCLRC BCLK DACDAT ADCDAT Figure 6 2 left justified format WM8781 datasheet The WMS8731 provides two independent channel clocks for DAC and the ADC which allows both to operate with different sampling frequencies However sampling frequencies will be the same for the line in and line out for this project Therefore the same channel clock can be used for both the DAC and ADC The channel clock operates at sampling frequency fs The bit clock is derived from the sampling frequency and the word length For example a sampling frequency of 48kHz and a word length of 16 bits requires a minimum bit clock value of 2x16x48000 1 536MHz Timing for the bit clock and channel clock can either be obtained from the codec 1tself master mode or provided externally slave mode Master mode was chosen to configure the serial interface clocks as inputs to the FPGA as shown in Figure 6 3 These clocks are used to convert the serial stream to left and right channel parallel words for processi
44. ly relatively small signal delay such as the one illustrated in Figure 2 4 For larger delay values a dedicated RAM device will be required The use of FPGA design allows the user to review the design at multiple levels of abstraction for maximum learning potential and possibly a more intuitive design process The personal computer has always been the dominant platform for running audio processing software on mainly because of the standardised and well established hardware and operating systems However as embedded technology matures audio processing may be able to move away from the potentially unreliable standard computer and move towards a form of dedicated reconfigurable platform that can do or be anything you want 1t to Mike Hudson 3 Approach 3 1 General The general approach to the project consisted of the following phases Literature review Choosing the tools and software Learning how to use the tools and software Review of related data sheets and manufacturer documentation Creation of a basic audio in out system Creation of the basic building blocks of digital processing Reviewing the theory of desired audio effects Implementation of effects pec xe ce xo S46 eee A em Testing results and conclusions The research stage of the project consisted of Review of previous work and current products e Evaluation of available tools and software e Reading theory of signal processing e Reading review
45. master clock was provided with 12 5MHz rather than 12 288 MHz since this was the closest divisible value from the PLL using a SOMHz input 22 Mike Hudson Jordy 00070 TrTOOY Or T00 Foro 0T00 11000 0F000 F0000 00007 Y TITO OFTTO Y TOFTO OO TO TTOLO ororo Fooro odoro T1100 OTT OG 0700 OO O0 11000 f 07000 T00000T0000T000T OOT OT OOLOT OT OT OT 1 1 I 1 I sn Q er sn 8 TT sn g9 TT snzs TT sn 9 TT sn TT Sn eO TT sn 88 0T sn c 0T sn 95 0T sn e or snpc or sn 80 0T sn c6 6 sn 9 6 T0000 0000000000000000 HEHHEE a M SIMINHHHIN 01 1 1 3 a FOTTTTTTTTTTTTTT i 0000000000000000 0T00000000000000 I 1 1 1 I I 1 I I 1 I 1 I snz 6r snz6 T snp9 9gp SNES sngovr sn gt SnZS TET Snpc Or sn 96 8 sn 89 sni 9 snzr s Sn p8 sn 95 Z i i ZHAS8 SY I sn p 0c our o dureg SC I 09 AP iq a 19 yasal al sdo gt anl aueN l m y wosrva anv e xxawv m i xa av anv EJ UUW 1198 any a 0821 cSt 4 968 89 079 cbs rot 95 acl 0 Bzh 9Sc anjeA Pc0l gt 9150 G 0 3LUEN sei adA E 0 PLESEL SL LO ZLOZ 60 A Parallel to Figure 6 8 Serial to Figure 6 7 parallel Codec Figure 6 6 serial waveforms 23 Mike Hudson 6 1 Digital serial data stream To test the correct configuration of the audio Codec a simple audio in out loopback
46. multiplying each digital sample value by a value less than one Since most digital audio sample data 1s represented as fractional twos complement format the values range from 1 to 1 multiplying by any number less than unity will remain in range 1 to 1 The result from Figure 2 2 would be an output signal half the amplitude of the input yn x t N A Figure 2 2 Digital audio processor example volume Udo Zolzer Mike Hudson 2 3 The building blocks of basic audio effects Digital signal processing routines consist of repetitive multiplication and summation referred to as multiply accumulate or MAC of multiple samples delayed at different points in time which is usually given in terms of the sample rate In order to realise some common digital audio effects these three main components need to be established e Variable delay line e Multiplier e Accumulator These fundamental operations are arranged 1n various structures to obtain the desired effect on the output The variable delay line would typically be some form of RAM buffer that stores a fixed amount of previous sampled values The RAM will need to be implemented as a circular buffer when the write pointer reaches the end of the specified buffer length 1t goes back to the beginning and overwrites the oldest sample Many DSP routines require multiple samples of a signal simultaneously but all at different delayed points in time This is effectively realised by h
47. nd from the filter produced satisfying results 43 Mike Hudson 11 Flanger effect The flanger is a phasing effect and creates a whooshing sound by mixing the original signal with a delayed version of itself The whooshing sound results from the variable delay length being modulated usually by a low freguency sine wave As the delay value 1s varied certain frequencies will become 180 degrees out of phase causing cancellation hence the reason why this effect is most prominent when both the delayed and original signal are mixed at a 5090 Variation of zero to about 30 sample delays in increments one seems to be sufficient for this effect The sample delay was provided by a hardware delay line written in VHDL code as discussed in section 7 4 Figure 11 1 shows the schematic drawn in Simulink From Audio Device SP sine Wawe Delay DC offset Figure 11 1 Flanger diagram in Matlab Simulink Figure 11 2 shows the actual spectrogram plot frequency against time of the recorded flanger effect from the DE2 The frequency notches are a bit uneven because the variable delay was modified manually rather than automatically with a sine wave since some difficulty was had with creating a variable low frequency sine wave in VHDL One advantage of manually controlling the delay was that the notching effect could be observed at each delay increment to get a better understanding of how the effect works Figure 11 3 shows the frequ
48. ng and then back to serial for the DAC 19 Mike Hudson Direction of clock signals in master mode BCLK ADCLRC DSP WM8731 5 DACLRC ENCODER CODEC DECODER ADCDAT DACDAT Note ADC and DAC can run at different rates Figure 6 3 Master mode WM8731 datasheet 6 2 1 Sampling frequency The desired sampling frequency was chosen by providing the appropriate master clock MCLK frequency to the codec This provides a reference clock to which all audio data processing 1s synchronised The source of the master clock can either be from the provided crystal oscillator or from an external clock the FPGA This master clock provides a reference to which all audio data processing 1s synchronised To be able to control the sample rate by selecting the master clock frequency the codec must be in normal mode as opposed to USB mode which can only use a 12MHz clock From the WM 731 datasheet a master clock frequency of 12 288MHz is needed to obtain a sampling frequency of 48kHz for the DAC and ADC This was provided from the FPGA by utilising the PLL mega function in Altera Quartus and the DE2 50MHz crystal as the reference 6 2 2 Register map Figure 6 4 shows the complete register map for WM 731 audio Codec as given in the datasheet There are eleven registers 1n total each having nine bits per register note there is a misprint in the datasheet where R3 is labelled as R 1 Several different featur
49. nter 1s made by the state machine the code will test 1f the read pointer 1s more than the write pointer If true this means the write pointer has reset wrapped back round and so instead of obtaining the read pointer value from the usual subtraction it 1s increased by 4 until 1t reaches the end of the buffer where 1ts value will then be calculated as normal again The other modification to the initial code was to wait until the write pointer was ahead of the read pointer by the delay amount This allowed the read pointer delay value to be modulated by external means which 1s necessary to implement various audio effects such as phasing and chorus type effects The extra 1f statements 1n the code below eliminated these problems if inc read pntr 1 then write pntr has reset if read pntr gt write pntr then read pntr lt read pntr 4 if read pntr gt buff size then wrap round 35 Mike Hudson read pntr lt conv std logic vector base addr 32 end if elsif write pntr gt base addr sample delay then read pntr lt write pntr 4 sample delay else read pntr lt write pntr end if Code extract 8 3 8 7 Multiple read pointers Figure 8 9 illustrates how additional read pointers may be easily be added to the state machine code The location of the taps relative to the write pointer can be changed independently Values of the taps are read out sequentially since a new state has to b
50. orks and current products iii ans YUA ee PE o Y ctp es 3 2 j Backeround and hc Music lid 5 2 Back O A GN A A I A A EU 5 22 Bei aud io heo pn Y Y Y Y ast e de Lo eons 5 2 3 The building blocks of basic audio effects ooooonnccnnnnnnnnnononononncnnnnnnonononanononoconnnnnnnnnnnos 7 DA Metal TAGE examples 8 2 COn OM seein TU mee 8 3 FAP ROACH aida 10 zi A NR NR e eet 10 2 2 lc Ion LOOIS and SO Vat oia 10 4 The Altera DE2 development board coccooccccnnnocccnonoccccnnnncccononcocccnonoccccnconocccnonccccnonenaccos 12 Z3 NMEMEB Uu e re rm 12 5 JXltera Ouarfus IIa sies ovii ascii 14 Sal ANTOdUCIOR UU mm 14 352 ORG BUKE i A I eect UA LA ees 14 6 Interfacing Audio to the audio to the FPGA ooomnccccccnononoccccnnnnonoccccnnnonincccccnnononoccccnnononoos 16 Oil The Wolfson WNIS 78 L audio ADC Co aU D voL dae Y O ote eT UU OIM 16 02 COM a FR NN ANN NR aspen I RF UNI NF FR RE FN NEF FFR 18 62 41 Samplino requerida ia 20 022 IRCCISLER MA A Y 20 Mike Hudson 6 penal parallel COBVEESTOTo 2 a 21 DL Dietalscral dataset o 24 Diz o DEC DE 1 821 dt dc 24 7 Building a project library of Quartus block symbols cccccsssssccccssssccccsssscccsessscees 25 A ET 25 A SUN erase tea Seat E E 25 Te NHAD A OR O OO UU GR O A i OR 26 74 pmalldelav line mhardWarc an 27 To OUMA AFF FN FFF m 28 5 implementing a bulHer in RAM a e 29 Sl IS urn dia 29 8 2 Choice ot RAN dy TG O a A Gol 29 So
51. parameterisation with relation to a physical space 55 Mike Hudson 13 Latency test 13 1 Comparison with computer software A simple test was carried out to determine the latency of a series effect chain on the DE2 board The same test was then carried out on a computer running Apples OS X operating system with an equivalent series effect chain Figure 13 1 within Logic Pro 9 a commercially available digital audio workstation The standard built in CoreAudio driver and built in soundcard were used which is supposedly prepared to run low latencies Figure 13 1 shows the series effect chain and Figure 13 2 1llustrates how the equipment was setup to measure the system latency The delayed signal goes into chl and ch is the direct signal The system latency is the difference between the two Audio EI out Figure 13 1 Series effect chain chl AW ife oscilliscope ch2 Figure 13 2 Latency test setup Due to lack of 1mmediately available resources and time the oscilloscope was replaced with a computer running audio recording software setup to record a stereo input for 56 Mike Hudson channels one and two A microphone was used for the audio source and was tapped to create a transient This meant the test was not of good enough quality to determine the exact latency value since the waveform editor scale was not small enough but it 1s acceptable for a rough visual comparison The distance between the two mar
52. r 20ms time domain impulse DO orn Amplitude no Time Seconds One all pass filter 20ms spectrogram m i s m onds mo co Frequency x10 Hz o Figure 12 7 One all pass filter 20ms delay time and 0 7 gain x 10 Three series all pass filters on DE2 setting one time domain impulse Amplitude Time Seconds E Three series all pass filters on DE2 setting one spectrogram 140 120 100 8 60 40 20 p Se on m _ eee a ro Figure 12 8 Three series all pass filters on the DE2 setting one 50 Mike Hudson x 10 Three series all pass filters on DE2 setting two time domain impulse Am plitude Time Seconds 0 Three series all pass filters on DE2 setting two spectrogram 140 120 100 8 60 40 20 m i coa HF AM o Figure 12 9 Three series all pass filters on the DE2 setting two 12 4 Comparison with a commercial software reverb As a matter of interest the impulse response test was also done on a commercially available software reverb A comparison was made with results from the reverb effect implemented on the DE2 and key differences were noted The Averb reverb Figure 12 10 was chosen due to its intuitive and straightforward interface and parameters This is one of the standard effects that comes packaged with the Apple Logic Pro software and 1s quite highly regarded as far as digital software effects are concerned There are six different rev
53. r are described by eguation 16 1 ym n f YN yp n 1 ypp n f Ynp N Yop n 1 ypp n X N Ynp n 1 Q yy n 1 16 1 Where the fc coefficient determines the filter cut off frequency and O is the damping factor filter resonance f 2sin E 16 2 To prove equation 16 2 describes the relationship between the f coefficient and the filter cut off frequency a value of 500Hz was used equation 16 3 f 2sin x an 48000 16 3 Which gave a value of 0 0654 for the f coefficient A frequency response measurement was taken to prove the working of the filter with the calculated frequency coefficient and the Q coefficient of 1 4 Figure 10 2 shows the frequency response of the low pass filter when subject to white noise at the input and the gain raised to Odb for easy interpretation of the plot The spectrum plot also proves this is a two pole 12dB decade filter 42 Mike Hudson Fc 500Hz Figure 10 2 Low pass filter on the DE2 fc 500hz 10 2 Discussion The coefficients have to be carefully limited since it can easily become unstable as it approaches high frequencies with a low damping factor One other disadvantage to this filter topology is that its stability limit is 1 6 of the sample frequency when the tuning coefficient f 1 A limit of 8kHz in this case with a sampling frequency of 48kHz Despite these minor drawbacks and potential room for improvement the overall sou
54. ract 8 2 shows the modified VHDL that implements this functionality increase write pointer index if inc write pntr 1 then if write pntr buff size then wrap round write pntr lt base address else write pntr lt write pntr 4 increase as normal end if end if l 2 3 4 5 6 7 9 Code extract 8 2 This basic method of increasing the read and write pointers presented a few problems e White noise when resetting or powering up the DE2 e Periodic white noise when the read pointer lags by more than several samples e Moving the sample delay whilst it is running gives pops and crackles 34 Mike Hudson Every time the write pointer resets back to the base address the read pointer cannot be properly calculated cannot be a minus number from the write pointer and this continues for the length of the specified lag time of the read pointer This resulted in white noise for the length of the samples between the write and read pointer at every new cycle of the buffer Figure 8 8 attempts to demonstrate this The shaded area illustrates the dead zone This continues until the read pointer s value 1s positive Base re ad addr pointer write pointer sample delay Figure 8 8 Problem with circular buffer The problem was rectified by implementing some further logic in the form of 1f statements on every increase of the read pointer only When a request to increase the read poi
55. t tools The initial requirements and proposed outcomes were established e A minimum of 44 1kHz with minimum 16 bit sample depth Real time line in and out audio e A platform which can be used to further develop and implement audio processing effects e A selection of digital audio effects User controllable parameters via a software interface preferably in real time Re routable effects User feedback of parameters and selections The project will be targeted at CD guality audio two channel stereo with a sample rate of 44 1kHz and bit depth of 16 bits The quality should also be acceptable for the processing of an electric guitar audio signal For audio processing of instruments and voice a real time response of the audio processor is desired in order to minimise and potentially completely eradicate perceivable delay between the input and the output signals A typical delay value also referred to as system latency on a computer software implementation of an audio processor may be in the region of around 10ms Therefore an acceptable result would be a latency of less than 10ms of latency on an Mike Hudson FPGA A short list of effects was created Each of these effects require a different functionality in a digital processing system and would also demonstrate a degree of flexibility in terms of what can be created In other words the choices of effects were carefully chosen in order to prove a concept The idea being that
56. that the line in and line out are stereo two channels whilst the mic in is mono one channel The former will be used for this project Table 6 1 shows the description of the signals in Figure 6 1 17 Mike Hudson Audio CODEC Bit stream Clock Table 6 1 WM8781 pins sourced from the DE2 manual 6 2 Configuration The codec is configured via a serial IC controller which is automatically generated when instantiating the Audio and Video Config IP core in the SOPC Builder A number of different modes and options are available and are selected by writing to the appropriate register on the codec and will be discussed in this section The digital audio data 1s interfaced to the FPGA through the digital serial audio mterface Audio left and right data channels are multiplexed to form the serial stream of data with reference to the bit clock and the channel clock see Figure 6 2 The audio interface mode describes how the serial audio data stream 1s framed relative to the bit clock named BCLK and the DAC ADC channel clock named DACLRCK and ADCLRCK respectively The three available standards are Left justified e Right justified e 2S Inter IC Sound Bus For the scope of this project the choice of interface mode is not too critical since there are no compatibility requirements for example interfacing with other devices or 18 Mike Hudson software However left justified mode was chosen due to it being word
57. the individual reflections were dense enough to not be individually recognised by ear This resulted in a smoother reverb sound as can be seen in the spectrogram plots in section 12 3 12 3 Impulse response test A test was devised in order to determine both the frequency and time characteristics of the reverb effect An impulse response was obtained using Apple s impulse response utility to apply a sweeping sine wave to the input and record 24b1t 96kHz the response at the output The output was then de convolved to get a time domain impulse response which was exported as an audio AIFF file A short time Fourier transform STFT was performed in Matlab on the audio AIFF file and plotted in order to view both time and frequency information on one graph The Matlab code below was used to plot the spectrogram of the impulses 48 Mike Hudson ir fs aiffread impulse aiff figure specgram ir 512 fs colorbar title Spectrogram xlabel Time Seconds ylabel Freguency x10 4 Hz Code extract 12 1 Figure 12 6 shows the applied sine wave sweep generated from Apple s impulse response utility Sine wave sweep time domain Time Seconds Sine wave sweep spectrogram 150 100 50 50 ms me on a o Dunne Hz o Figure 12 6 Sine wave logarithmic sweep test signal 49 Mike Hudson Figure 12 7 shows the effect of one all pass filter when subject to an impulse x10 One all pass filte
58. tilised to implement all four of the proposed audio effects echo flanger filtering and reverberation The total latency of the FPGA was under Ims where as an equivalent setup on a personal computer running audio processing software had a typical latency of 10ms Comparisons showed that the latency of the FPGA audio processor remains relatively constant when more audio effects are added whereas the computer software adds a considerable amount of delay for every audio effect in the chain This demonstrates the benefits of using an FPGA for a low latency solution to audio processing The design of the project demonstrates how a library of VHDL entities can be built up to form the basic building blocks of digital processing Instantiating these blocks in Quartus schematic editor proved to be a very intuitive method of designing such systems allowing for multiple levels of abstraction The SOPC Builder also proved to be a valuable tool for the system design and allowed ease of interconnection between components and intellectual property 15 1 Further work A considerable amount of time was spent creating the basic audio in out system Therefore this work could be valuable to any other work concerned with utilisation of the audio codec on the Altera DE2 board There are many possibilities to extend the work carried out for this project such as e Improvements of the user interface and parameterisation of audio effects possibly using a NIO
59. uction of the rotary Figure 14 5 Eight rotary controls and control box 10 LEDS 61 Mike Hudson The problem with the functional simulation of the VHDL code for the rotary encoder is that 1t does not account for any switch bounce The VHDL process was clocked at 50MHz and when it came to physically testing the encoder its behaviour was very erratic indicating the need to implement some form of de bounce mechanism within the code After some experimentation the problem was resolved by clocking the VHDL process with a slower clock frequency of 48kHz 14 3 Interfacing the controls The controlbox VHDL entity Figure 14 6 provides the eight seven bit values from the encoders These values were initially connected directly to the parameters to control However with four effects eight controls were not enough and so an effect selection feature was devised The switches on the DE2 board were used to select which effect the control values were connected to o Interface to 8 rotary snceders conenected to the GPIO 0 S9 111717171717171 the last value to change is represented on a row of 10 LEDS AA CLOCK LEDG 6 0 GOLN o HE a i gt GPIO O 0 GPIO_0 16 25 i UE MAN o GPIO_0 1 rotary_one 6 0 babes aco DR Lo GPIO_0 2 rotary_two 6 0 A GPIO_0 3 rotary_three 6 0 SEIOS ooo __ E T GPIO_0 4 rotary_four 6 0 SOL Nen 3i GPIO_0 5 rotary_five 6 0 GO IR oo Co GPIO_0 6 rotary_six
60. us oooooooooooocccccncccnnonnnnnnnnnnnnnnnnnnnnnnnos 31 Read and write waveforms for Avalon memory mapped master 32 state Machine for a RAM Bulletin RAN RWAN NW MARN NAG 32 SDRAM state machine connected to SOPC SystemM oocccccccccnncnnnnnonononnnoss 34 Problem with circular buffer seen 35 Multiple read pointers in the RAM state machine eeesssssss 36 Figure 8 10 Multiple SDRAM buffer components in SOPC Builder 37 IX Mike Hudson Pieurc A AM NFYFC FN NY citur 39 Figure 9 2 Variable delay feedback sii 39 Figure 9 3 Delay effect symbol on top level in QuartUS oooooononnncnonononononononnnnnnnnnonononnnos 40 Froure IU 1 State Variable HIR ii 41 Figure 10 2 Low pass filter on the DE2 fc S00hz essen 43 Figure 11 1 Flanger diagram in Matlab Simulink eeeeeeeesseeeeeeessssse 44 Pigurc 11225 Flanger erect on hc DE se etie id O OO Gi 45 Figure 11 3 Original signal mixed with a ten sample delayed version 45 Figure 12 1 Comb TIET iu cis 46 Pig tbe 1222 AUEDaSS MIr sand 47 Figure 12 3 An all pass filter in Simulink essen 47 Figure 124 ATPpass HHeran Quartas a 47 Figure 12 5 Multiple series all pass TeVetb id esa etta FY 48 Figure 12 6 Sine wave logarithmic sweep test signal ooooooooooooonccccccnccnnnnnnnnnnnnnnnos 49
61. winning design for the Swedish Embedded Award for 2010 and proves 1t 1s possible to realise a complete guitar multi effect chain on a single FPGA chip a project they claim could potentially disrupt the market Results are impressive with overall system latency kept under one sample at 48kHz A NIOS soft core processor has been utilised to provide a rich graphical animated VGA interface comparable to current products on the market such as Native Instruments Guitarrig Mike Hudson 2 Background and Theory 2 1 Background The need to create faster and smaller devices whilst also maintaining a low cost continues The most common solution for increasing performance in a DSP would be to run at a higher clock speed However even with high clock rates two MAC units and modified bus architecture there is a maximum level of performance that can be achieved Maxfield C 2006 Audio applications reguire absolute minimum system latency especially for eguipment used in a live environment or recording studio 1t needs to be as close to real time as possible Cascaded digital audio effect chains can introduce unacceptable delays which can be very disruptive any delay over 10 milliseconds would be deemed unacceptable to the recording artist or technician An FPGA DSP implementation offers may advantages over the traditional software approach e True hardware e Highly flexible True parallel processing of DSP operations e Reliable
62. y and potential unreliability Ouartus II v11 0 and SOPC Builder have been used to design and create the VHDL code to be synthesised The implementation of the VHDL design uses the DE2 development board from Altera which is based around a Cyclone EP2C35 FPGA device having 35000 logic elements Four audio effects were explored and implemented echo flanger filter and reverb External control to the FPGA was implemented using rotary encoders to change various effect parameters and visual feedback been given through an LCD The final design utilises a Nois II soft core processor to form part of the user interface The results show that the total system latency of the FPGA audio processor was considerably less than a computer software application less than 1ms compared to 10ms The initial concept has been proven using a total of 11702 logic elements There 1s much scope for development of the final project Future work could focus of a more user friendly system in terms of the user interface and also the creation of more advanced audio effects IV Mike Hudson Table of contents aU nn FO IDEM I A FR Y Y Y Y RY HR II VICKHOWIPdO E HIE ESL aie cec nn oe Ded eM Erde III ny o M I E RF HN RS NU FYN IV Tableof CONTA TT T V Nomenclature and abbreyIatlOHs s eiieset e eren stra e ai DE OO Ud VIII TODO Of IL RS IX EM ici erc RD Y 1 LM SDT etal audio DEOCGSSIDE dada 1 1 2 Project ams ando DUE ei ida 2 1 1 Previous w

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