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User`s Manual - MSC Technologies

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1. 12 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 7 System Memory The MSC CXB 6S CPU module provides two sockets only one socket on CXB 6S 010 for memory modules which have to meet the following demands e 204pin unbuffered non ECC DDR3 SO DIMM Raw Card A B C and F e 1 5V Supply Voltage e DDR3 1066 PC3 8500 DDR3 1333 PC3 10600 e DDR3 1600 PC3 12800 with Core i7 2715QE and Core i3 5 7 3 e Maximum module height 30mm e SPD Serial Presence Detect EEPROM 2 8 Mechanical Dimensions 2 8 1 Compact module 95 00 91 00 e E 91 00 i i i eh D1 18 00 6 00 e 4 00 RES i e 0 00 38 a Npn Al 3 SS owt wo o N Se co NN There are two height options defined in the COM Express specification 5mm and 8mm The height option is defined by the connectors on the baseboard 13 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Heatspreader jf Module PCB Fie KH i 1 5 00 2 00 i HA Em N N Carrier Board PCB 2 9 Thermal specifications The cooling solution of a COM Express module is based on a heat spreader concept A heat spreader is a metal plate typically aluminium mounted on the top of the module The connection between this plate and the module components is typically done by thermal interface ma
2. eDP Port D LFP Driven by Int DisplayPort encoder from Port D through PCH Onboard EDID EEPRIM Enabled Enable or disable the onboard EDID EEPROM Disabled 6 1 11 3 DMI Configuration ome omm EC DMI Vc1 Control Enabled Enable or disable DMI Vc1 Disabled DMI Vcp Control Enabled Enable or disable DMI Vcp Disabled DMI Vcm Control Enabled Enable or disable DMI Vcp Disabled DMI Link ASPM Control Disabled LOs DMI Gen 2 L1 LOsL1 Auto Enabled Disabled Enable or disable the control of Active State Power Management on SA side of the DMI Link Note For optimal performance let this option disabled DMI Extended Synch Co Enabled Enable or disable the control of Active State Power Disabled Management on SA side of the DMI Link Enable or disable the control of Active State Power Management on SA side of the DMI Link 68 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 11 4 NB PCle Configuration rmm mm o omm PEGO Gen X Auto Gent Configure PEGO B0 D1 f0 Gen1 Gen2 Gen3 Gen2 Gen3 PEG ASPM Disabled Auto Control ASPM support for the PEG Device This ASPM LOs has no effect if PEG is not the currently active ASPM L1 device ASPM LOsL1 ASPM LOs Root Port Only Enable PCle ASPM LOs Endpoint Port Only Both Root and Endpoint Ports Disabled Enable PEG Disabled To enable or disable PEG Enabled Auto Detect Non Compliance Enabled Detect Non Compliance PCI Express D
3. PCI IRQ A PCI IRQ B PCI IRQ C REQO if used PCI REQ 0 PCI REQ 1 PCI REQ 2 PCI REQ 3 Z REQ1 if used PCI REQ 1 PCI REQ 2 E PCI REQ 3 PCI REQ 0 REQ2 if used PCI_REQ 2 4 PCI_REQ 3 4 PCI REQ O PCI REQ 1 REQ3 if used PCI_REQ 3 PCI REQ O0 PCI REQ 1 PCI REQ 2 GNTO if used PCI GNT 0 PCI GNT 1 PCI GNT 2 PCI GNT 3 GNT1 if used PCI GNT 1 PCI GNT 2 PCI GNT 3 PCI GNT 0 GNT2 if used PCI GNT 2 PCI GNT 3 E PCI GNT O PCI GNT 1 GNT3 if used PCI GNT 3 e PCI GNT 0 PCI GNT 1 PCI GNT 2 The signals PCI IRQx PCI REQx or PCI GNTx are are routed exclusively to the COM Express connector They are not shared on the CPU board 5 4 SMB Address Map Device Address HW Monitor ADT7490 CMOS Backup EEPROM SO DIMM 0 SPD EEPROM AOh 50h SO DIMM 1 SPD EEPROM A4h 52h 8 bit address with R W 7 bit address without R W 5C 27h A8h 54h AAh 55h 39 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 BIOS 6 1 1 Introduction This guide describes the AMI Aptio Setup Startup screen and contains information on how to access Aptio setup to modify the settings which control AMI pre OS operating system functions 6 1 2 Startup Screen Overview The AMI Aptio Startup screen is a graphical user interface GUI that is included in AMI Aptio products The default bios behavior is to show an informational text screen during bios POST phas
4. MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 7 Tech Notes 1 Intel amp Rapid Storage Technology With Intel Rapid Storage Technology you can take use of the advantages of AHCI and RAID Through AHCI storage performance is improved with Native Command Queuing NCQ AHCI also delivers longer battery life with Link Power Management LPM which can reduce the power consumption of the chipset and Serial ATA SATA hard drive By enabling Raid you have the possibilities of using Raid 0 Raid 1 Raid 5 and Raid 10 RAID 0 uses the read write capabilities of two or more hard drives working together to maximize storage performance The hard drives in a RAID 0 volume are combined to form one volume which appears as a single virtual drive to the operating system For example four 120GB hard drives in a RAID 0 array will appear as a single 480GB hard drive to the operating system ARAID 1 array contains two hard drives where the data between the two is mirrored in real time Because all of the data is duplicated the operating system treats the usable space of a RAID 1 array as the maximum size of one hard drive in the array For example two 120GB hard drives in a RAID 1 array will appear as a single 120GB hard drive to the operating system ARAID 5 array is three or more hard drives with data divided into manageable blocks called strips The main benefits of RAID 5 are storage capacity and data protection ARAID 10 array uses four ha
5. USB COM Express PCI Express PCI LPC SPI Graphics Controller Video Memory LVDS Digital Display Ports multiplexed with PEG PEG CRT Interface Ethernet Sound Interface Watchdog Timer TPM option Fan Supply Real Time Clock Intel Core i7 3615QE Intel Core i7 3612QE Intel Core i7 3555LE Intel Core i7 3517UE Intel Core i5 3610ME Intel Core 3 3120ME Intel Core 3 3217UE Intel Core i7 2715QE Intel Core 7 2655LE Intel Core 7 2610UE Intel Core 5 2515E Intel Core 3 2310E Quad Core 2 3GHz 6MB SV 45W Quad Core 2 1GHz 6MB SV 35W Dual Core 2 5GHz 4MB LV 25W Dual Core 2 1GHz 4MB ULV 17W Dual Core 2 7GHz 3MB SV 35W Dual Core 2 4GHz 3MB SV 35W Dual Core 1 6GHz 3MB ULV 17W Quad Core 2 1GHz 6MB SV 45W Dual Core 2 1GHz 4MB LV 25W Dual Core 1 5GHz 3MB ULV 17W Dual Core 2 1GHz SV 35W Dual Core 2 1GHz SV 35W Let Vu Vm est ume Leet SN a m s Zeien e rer eeh pins Lee Intel Celeron B810E Dual Core 1 6GHz SV 35W Intel Celeron 847E Dual Core 1 1GHz 2MB ULV 17W Intel Celeron 827E Single Core 1 4GHz 1 5MB ULV 17W Intel Celeron 807UE Single Core 1 0GHz 1MB ULV 10W Intel 82QM77 with Intel Core 5 3 and Intel Core i7 3 processor SKUs Intel 82QM76 with Intel Core i3 3 processor SKUs Intel 82QM67 with Intel Core i5 2 and Intel Co
6. 1 8 User Manual 2 3 COM Express implementation COM Express required and optional features of pin out type 2 are summarized in the following table The features identified as Minimum Min shall be implemented by all modules Features identified up to Maximum Max may be additionally implemented by a module The column MSC CXB 6S shows the implemented features of the MSC module LT Twe2 msc CXB 65 SR Min ax Sien O Jooo PCI Express Lanes 16 31 E same as PEG pins 0 16 1 x16 off module x16 PCI Express Graphics VGAPot 0 IW y Ou NA 0 jJetevilbe id 4x 300MB s ports O 3 SATA Ports 1x SSD optional 1 x Solid State Disk port 4 HDA Digital Interface 0 1 BEEN 3 USB 2 0 Ports 48 8 USB Client Gbit LAN Intel 82597LM GbE PHY Texas Instruments PCle to PCI Bridge SPI E System managemen General Purpose Inputs 4 4 a Oooo General Purpose Ouiputs 4 4 ups AR A PoC Vd WaichDogTimer on SSCS Speaker Out on o OOS External BIOS ROM support 0 2 2 SSCS Reset Functions ARE 4 SSCS Pd SS Power Management PA Thema Protection onm PO BateylowAam on SSCS Sara LE We 2 EH PowerButonSupot 3 1 PA PowrGod A 4 1 CO E sch IM Al af a lala 9 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 4 Functional units CPUs FCBGA 1023 Chipset Memory SATA EIDE
7. 2 PCI Local Bus Specification Rev 2 1 PCl21 PDF Last update June 1 1995 http www pcisig com 3 ATA ATAPI 6 Specification d1410r3b pdf http www t13 org 4 Serial ATA Specification Serial ATA 1 0 gold paf Last update August 29 2002 Rev 1 0 http www sata io org 5 IEEE Std 802 3 2002 802 3 2002 pdf http www ieee org 6 Universal Bus Specification usb 20 pdf Last update April 27 2000 http www usb org 7 2 Generation Intel Core Processor Family Mobile and Intel Celeron Processor Family Mobile Datasheet Volume 1 2nd gen core family mobile vol 1 datasheet pdf Last update September 2011 http www intel com content www us en processors core CoreTechnicalResources html 8 2 Generation Intel Core Processor Family Mobile and Intel Celeron Processor Family Mobile Datasheet Volume 2 2nd gen core family mobile vol 2 datasheet pdf Last update June 2011 http www intel com content www us en processors core CoreTechnicalResources html 9 Mobile 3rd Generation Intel Core Processor Family Datasheet Volume 1 of 2 3rd gen core family mobile vol 1 datasheet pdf Last update September 2012 http www intel com content www us en processors core CoreTechnicalResources html 10 Mobile 3rd Generation Intel Core Processor Family Datasheet Volume 2 of 2 3rd gen core family mobile vol 2 datasheet pdf Last update June 2012 http www intel com content www us en processors core Co
8. AC HDA SDINT C29 PCI_AD10 D29 PCI AD13 A30 AC HDA_RST B30 AC HDA_SDINO C30 PCI_AD12 D30 PCI_AD15 A31 GND FIXED B31 GND FIXED C31 GND FIXED D31 GND FIXED A32 AC HDA BITCLK B32 SPKR C32 PCL AD14 D32 PCL PAR A33 AC HDA SDOUT B33 I2C CK c33 Pci c BEt amp D33 PCI_SERRK A35 THRMTRIP B35 THRM C35 PCI LOCK D35 PCI TRDY A49 EXCDO CPPE amp B49 SYS RESET amp C49 PCLIRQA D49 PCI M66EN A50 LPC_SERIRQ B50 CB RESET C50 PCIIROB D50 PCI CLK PCI AD27 PCI IRQC C42 C43_ C44 PCI A45 USBO B45 USB C45 PCLAD25 D45 PCI AD30 C46 PCI C47 C48 C42 C43 C44 C45 C46 C47 C48 C49 C50 31 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual EAN O AA A STER GND FIXED GND FIXED GND FIXED D60 GND FIXED PEG_RX3 PEG_RX3 RSVD RSVD PEG_RX4 PEG RX4 D66 PEG TX4 RSVD PEG_RX5 PEG RX5 D69 PEG TX5 GND FIXED GND FIXED A83 LVDS l2C CK B83 BKLT A84 LVDS l2C DAT B84 VCC 5V SBY C84 GND D84 GND AB5 Iert B85 VCC 5V SBY C85 JPEG bn D85 PEG TX10 GND FIXED D90 GND FIXED eno Ds Jono O PEG RXi4 D99 PEG TXi4 C110 __ not supported on standard MSC CXB 6S modules 32 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 12DDI Port Pin Assignment The pin assignment of the PEG port can be switched from PEG signals to Dig
9. DIMM Disabled EXTTS pin on the PCH Virtual Temperature Enabled Enable or disable Virtual Temperature Sensor Sensor VTS Disabled VTS 6 1 11 7 GT Power Management rmm mm rem RC6 Render Standby Enabled Check to enable render standby support Disabled RC6 Deep RC6 Enabled Check to enable Deep RC6 support Disabled 6 1 12 Boot me m Se Setup Prompt Timeout 1 65535sec Number of seconds to wait for setup activation key 65535 0xFFFF means indefinite waiting Bootup NumLock State On Off Select the keyboard NumLock state Quiet Boot Enabled Enables Disables Quiet Boot option Disabled Fast Boot Enabled Enables Disables boot with initialization of a minimal Disabled set of devices required to launch active boot option Has no effect for BBS boot options For more information see also technotes in chapter 6 7 Option ROM Messages Force Bios Set display mode for option ROM Keep current 71 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee omm en GateA20 Active Upon Request UPON Request GA20 can be disabled using BIOS Always services Always do not allow disabling GA20 this option is useful when any RT code is executed above 1MB Interrupt 19 Response Immediate Bios reaction on INT19 trapping by Option Rom Postponed Immediate execute the trap right now Postponed execute the trap during legacy boot Launch CSM Enable Disable This option controls if CSM
10. Disabled of Post before OS is booted 57 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 8 10 6 1 8 10 1 Watchdog Timeout Watchdog Delay 0 4s 1s 5 s 10s 30s 1min 5min 10min Select the maximum watchdog trigger period If the watchdog will not be triggered during selected period system reset will be generated 1s 5 s 10s 30s 1min 5min 10min 30min After the watchdog is activated it waits the selected delay time before starting to decrement the timeout period Serial Port Console Redirection mee Lal eme Com 0 Console Redirection Console Redirection settings Com 0 Com1 Console Redirection Console Redirection Settings Com1 Serial Port for Out of Band Management Windows Emergency Management Service EMS Console Redirection Console Redirection Settings Enabled Console Redirection Enable or Disable Disabled Submenu The settings specify how the host computer and the remote computer which the user is using will exchange data Both computers should have the same or compatible settings Enabled Console Redirection Enable or Disable Disabled Submenu The settings specify how the host computer and the remote computer which the user is using will exchange data Both computers should have the same or compatible settings Enabled Console Redirection Enable or Disable Disabled Submenu The settings specify how the host computer and the remote computer which t
11. 3V Port B DisplayPort Hot Plug Detect Multiplexed with PEG_RX3 DPB HPD EA d 4 en Port C DisplayPort Lane 0 3 differential pairs DPC LANE 0 3 on module Multiplexed with PEG TX 4 7 and PEG TX 4 7 A A DPC_AUX on module Multiplexed with PEG_RX6 and PEG_RX6 ere Multiplexed with PEG_RX7 ENN e DPD LANE 0 3 on module Multiplexed with PEG_TX 8 11 and PEG TX 8 11 egal mmodo Mutpoxes am Pee AXIOr and PEG xro DPD AUX on module Multiplexed with PEG RX10 and PEG RX10 TTT TI T Loo MiieedwnPER Re 000000000 ooo Multiplexed with PEG RX11 Note PEG ENABLEZ D97 from the carrier board must be high to select DisplayPort instead of PEG 24 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 14 Miscellaneous Pin Signal Power Remark PU PD SR Description Source Target Pew Hpe tewl rat foance DC CK CMOS EN ePU 2 2 KQ General purpose I2C port clock output OD 3 3V GPIO47 Sus IOC DAT O CMOS 3 3V 3 3V ePU 2 2 KO General purpose 12C port data I O line PCH OD 3 3V GPIO56 Sus SPKR IO CMOS 33V Outputfor audio enunciator the speaker in PC AT systems BIOS DIS 1 0 CMOS 33V ePU 5KQ Module BIOS disable inputs 1 0 WT Jo CMOS 33V ePD 10KQ Active high output indicating that a watchdog time out has occurred PIC12F509 poe ee tee ee Input to module from optional external keyboard controller that can force a reset Pulled high
12. CK HDMI Port C Clock Differential DPC_LANE3 DisplayPort G Lane3 PEG TXT D75 TMDSC CK Pair DPC LANE3 differential Pair PEG_TX8 D78 DSL PEG TX8 D79 PEG TX9 D81 PEG TX9 D82 PEG TX10 D85 PEG TX10 D86 PEG_TX11 D88 PEG_TX11 D89 1 CTRLDATA pins do have strap functionality and are sampled during power up A high level on these pins enables the appropriate DDI 34 81 port B C or D inside the PCH MSC CXB 6S CXB 6SI Rev 1 8 User Manual 3 Jumpers and Connectors 3 1 Jumpers There are four jumpers available on the module RTC Reset By shorting the pins of this jumper the RTC Clock is reset and the values of the CMOS NV RAM are cleared SHRTC Reset By shorting the pins of this jumper the manageability register bits in the CMOS NV RAM are reset Clear Backup EEPROM By shorting the pins of this jumper during boot the values of the Backup EEPROM and the values of the NV ROM are invalidated thus forcing the board to start up with default values BIOS Recovery By shorting the pins of this jumper during boot the system is forced into crisis recovery mode See chapter 6 5 for how to use the Bios Recovery These jumpers are located at the top side of the board at the border TAMA TET 0 030D60B16 udi src DILE ZEE Reset BB gie E E Ge W ER Go 35 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 3 2 Fan Connector The connector of the fan is located at
13. Multiplexed with PEG_TX 1 and PEG_TX 1 Er SE SDVOB BLU on module Multiplexed with PEG_TX 2 and PEG TX 2 oves e ups ee e Serial Digital Video B clock output differential pair SDVOB CK on module Multiplexed with PEG TX 3 and PEG TX 3 PCH PCH PCH PCH PCH PCH pene Je ae Serial Digital Video B TVOUT Synchronization Clock input mu SDVO TVCLKIN off module differential pair Multiplexed with PEG_RX 0 and PEG RX 0 SDVO_INT GE EAE E Serial Digital Video Interrupt input differential pair fe SDVO_INT off module Multiplexed with PEG_RX 1 and PEG RX 1 Ei EE eech Serial Digital Video Field Stall input differential pair EHE SDVO FLDSTALL off module Multiplexed with PEG RX 2 and PEG RX 2 SDVO CTRLDATA l O CMOS 3 3V 3 3V PD 20KQ SDVO Control Data Shared with port B HDMI DVI strap option Port PCH Ap II P BestectiPD cisabledafr PE a SDVO CTRLCLK O CMOS 3 23 V 33V SDVO Control Clock Shared with port B HDMI DVI Note PEG ENABLE D97 from the carrier board must be high to select SDVO 22 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 13 2 DVI HDMI Type Level Ra Tolerance Target mem ek Ee teeta ae Gaara TMDSB_D 0 3 on module Multiplexed with PEG_TX 0 3 and PEG_TX 0 3 imd d ERR RUNE E SDVO CTRLCLK TMDSB_CTRLDATA IO CMOS 3 3V iPD 20 KO Port B HDMI DVI Control Data Shared with port B SDVO_CTRLDATA strap option Port B detect iPD is disabled after PL
14. RTS CTS overflow When sending data if the receiving buffers Software are full a stop signal can be sent to stop the data Xon Xoff flow Once the buffers are empty a start signal can be sent to re start the flow Hardware flow control uses two wires to send start stop signals 6 1 8 11 Intel ICC mee mm en Use Watchdog Timer for Disabled Enable Watchdog Timer operation for ICC If Enabled enabled Watchdog Timer will be started after ICC related changes This timer detects platform instability caused by wrong clock settings Turn off unused PCI P Disabled Disabled all clocks turned on Enabled clocks for Enabled empty PCI PCle slots will be turned off to save power Platform must be powered off for changes to take effect Lock ICC registers Static only All All registers all ICC registers will be locked Static Registers only only static ICC registers will be locked DIV 1S Informative GFX DIV 2S Submenu Control Spread Spectrum BCLK DMI PEG PCle SATA USB DIV3 Informative not used DIV4 Informative GFX Bending DIV 1NS Informative GFX DIV 2NS Informative BCLK DMI PEG PCle SATA USB 60 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 8 12 DIV 2S Submenu me me NI New SSC Mode Down up Requested SSC mode Changes will not be applied center unless Accept changes is pressed New Spread percentage 0 50 Requesed SSC in percent in 0 01 increments Chang
15. Slot Number IDSEL or Onboard Device or Oc Talasnians 2 mjor gt DEV Fune OSOE UR OE Or OE PRIOR 5 Ez el e E e EE e e o oslosljlosjia lt sjaosja lt s lo lo Intel Integrated Graphic 2 0 0 x Device SA Thermal Device 4 0 0 x SATA 0 SATA 1 SATA 1F 2 0 x RAID Controller Onboard PATA Controller 0 0 dyn A JMICRON SMBus Controller 1F 3 0 D Thermal Controller 1F 6 0 x EHCI 0 1D 0 0 x EHCI 1 1A 0 0 x HD Audio 1B 0 0 x GbE Controller 19 0 0 x Management Engine 16 0 3 0 B C D A devices PCIE Slot 1 Lane 0 1C 0 dyn A B C D PCIE Slot 42 Lane 1 10 1 dyn D A B C PCIE Slot 3 Lane 2 1C 2 dun C D A B PCIE Slot 4 Lane 3 1C 3 dyn B C D A PCIE Slot 5 Lane 4 1C 4 dyn A B C D PCI Slot 1 4 AD 20 dyn D A B C PCI Slot 2 5 ADH21 dun C D A B PCI Slot 3 6 AD 22 dyn B C D A PCI Slot 4 7 AD 23 dyn A B C D P E G Port Slot x16 if 1 0 dun A B C D used P E G Port Slot x8 if used 1 0 dyn D A B C P E G Port Slot x4 if used 1 0 dun C D B Note x means that this Interrupt is used by an internal chipset device e g the Intel Graphics Device is connected to PIRQO and uses Interrupt A Chipset internal devices are connected to PIRQO PIRQ2 JMicron and PIRQ4 7 PIRQ1 and PIRQ3 are not shared with chipset devices Note The assignment of the PCI Express slots to the ComExpress connector is 1 1 Chipset PCle lane 0 is connected to ComEx
16. Source Target Type Level Rail Tolerance AA gt iPD 32 KO IDE_CBLID CMOS 3 3V 3 3 ePD 100 Input from off module hardware indicating the type of IDE cable JMB368 KO being used High indicates a 40 pin cable used for legacy IDE modes Low indicates that an 80 pin cable with interleaved grounds is used Such a cable is required for Ultra DMA 66 100 and 133 modes Note The IDE interface is realized by a JMicron JMB368 PCle to IDE controller located on PCle lane 6 2 10 4 Serial ATA Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance SATAO_TX SATA 3 3V AC coupled Serial ATA Channel 0 transmit differential pair P SATAO TX on module SATAO RX SATA 3 3V AC coupled Serial ATA Channel 0 receive differential pair P SATAO RX on module SATA1_TX P SATA1_TX SATA1_RX P SATA1 RX P P P P on module on module SATA2 RX SATA3_TX SATA3_RX SATA3_RX ATA_ACTH SATA 3 3V AC coupled Serial ATA Channel 2 receive differential pair on module Serial ATA Channel 3 transmit differential pair Serial ATA Channel 3 receive differential pair PE SATA activity indicator active low on module SATA 3 3V AC coupled on module CMOS 5V 20 mA CH CH CH CH CH CH CH CH CH SATA2_TX SATA 3 3V AC coupled Serial ATA Channel 2 transmit differential pair SATA2_TX on module OD Le i 17 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 5 PCI Expres
17. Type Level Rail Tolerance GPI 0 3 CMOS 3 3V 3 3V ePU 10 KQ General purpose output pins PCH Upon a hardware reset these outputs are low GPIO 38 39 48 49 GPO 0 3 CMOS 3 3V General purpose input pins PCH Pulled high internally on the module GPIO 24 35 70 71 27 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 17 SPI Interface Signal Pin Signal Power Rem PU PD SR Description Source Type Level Rail Tol Target SPI CS O CMOS 3 3V Sus ePU 10 KO Chip select for Carrier Board SPI may be sourced from chipset SPIO or SPI1 PCH SPI_MISO CMOS 3 3V Sus 3 3V J eSR 470 Data in to Module from Carrier SPI PCH SPI MOSI O CMOS 3 3V Sus eSR 470 Data out from Module to Carrier SPI PCH SPI CLK O CMOS 3 3V Sus eSR 47 0 Clock from Module to Carrier SPI PCH SPI_POWER O Power 3 3V Sus Power supply for Carrier Board SPI sourced from Module nominally 3 3V The PCH Module shall provide a minimum of 100mA on SPI POWER Carriers shall use less than 100mA of SPI POWER SPI POWER shall only be used to power SPI devices on the Carrier BIOS DIS CMOS 3 3V Sus 3 3V ePU 10 KO Selection straps to determine the BIOS boot device PCH 1 0 4 BIOS_DIS 1 0 4 SPI CS14 SPI CSO Carrier SPI BIOS Destination Destination SPI CS Descriptor Entry 1 1 Module Module HIGH Module SPIO SPI1 1 0 Module Module HIGH Module Carrier FWH 0 1 Module Carrier SPIO Carrier SPIO SPI1 0 0
18. for the Security Device EE take ownership Note Your computer will reboot during clear restart in order to change State of Security Device Pending Operation 48 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 7 4 CPU Configuration Note Dependent on used CPU available setup options may vary me om Js Hyper Threading Enabled Disabled Enabled for Windows XP and Linux OS optimized for Hyper Threading Technology and Disabled for other OS OS not optimized for Hyper Threading Technology Active Processor Core All 1 2 n Number of cores to enable in each processor package All All logical processors will be enabled n max cores 1 Limit CPUID Maximum Enabled Disabled Disabled for Windows XP Execute Disable Bit Enabled Disabled XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS Intel Virtualization Enabled Disabled When enabled a VMM can utilize the Technology additional hardware capabilities provided by Vanderpool Technology For more information see also technotes in chapter 6 7 Hardware Prefetcher Enabled Disabled To turn on off the Mid Level Cache L2 streamer prefetcher Adjacent Cache Line Enabled Disabled To turn on off prefetching of adjacent Prefetch cache lines TCC Activation offset Offset from the TCC activation temperature 49 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 7 5 CPU Power Manag
19. is 32 PCI bus clocks Enabled Disabled Set this value to change the PCI VGA Pal AAF AERE SNOR bus clocks Default is 32 PCI Bus clocks PERR Generation Enabled Disabled Enables or disables PCI Device to generate PERR SERR Generation Enabled Disabled Enables or disables PCI Device to generate SERR PCI Express Settings Configure PCI Express 6 1 7 1 1 PCI Express Settings Feature Options Description Relaxed Ordering Enabled Disabled Enables or disables PCI Express Device Relaxed Ordering Extended Tag Enabled Disabled If enabled allows device to use 8 bit Tag field as a requester No Snoop Enabled Disabled Enables or disables PCI Express Device No Snoop option Maximum Payload Auto 128 256 512 1024 Set maximum payload of PCI Express 2048 4096 Bytes Device or allow system Bios to select the value Maximum Read Request Auto 128 256 512 1024 Set read request size of PCI Express 2048 4096 Bytes Device or allow system Bios to select the value ASPM Support Disabled Auto Force LOs Set the ASPM level Force LOs State Auto Bios configures ASPM Force LOs LOs will be forced Disabled No ASPM will be used Extended Synchronization Enabled Disabled Enabled allows generation of extended synchronization patterns 46 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual ome om cm Link Training Retry Disabled 2 3 5 Defines number of retry Attempt software will take to retrain the link if previou
20. on the module This is a legacy artifact of the PC AT KBD A20GATE CMOS 3 3V 3 3V ePU 10 KQ Input to module from optional external keyboard controller that can PCH be used to control the CPU A20 gate line The A20GATE restricts the memory access to the bottom megabyte and is a legacy artifact of the PC AT Pulled high on the module Note COM Express Specification R2 1 redefines the 12C bus to be in the suspend plane 3 3V SUS rather than in the 3 3V plane To avoid leakage current into carrier boards that were designed upon earlier COM Express specifications the MSC CXB 6S modules hold these pins in the 3 3V plane Alternatively the 12C bus can be switched to the 3 3V SUS plane as an assembly option Please contact your MSC representative if you will need this option The 12C pins are implemented by bit banging at GPIOs As a result the maximal I2C bus speed depends on CPU performance 25 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 15 Power and System Management Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance CMOS 3 3V Sus 3 3V ePU 10 KQ_ Power button to bring system out of or into Suspend states active iPU 20 KO on falling edge after 16 ms debounce Ii CM CM PWRBTN SYS_RESET ePU 10KO Reset button input When the SYS_RESET pin is detected as active after the 16 ms debounce logic the ICH attempts to perform a graceful reset by waiting u
21. supply must be able to deliver this additional amount of power 2 The Intel Turbo Boost Technology 2 0 feature is not available on 2 Generation Intel Core i3 and Intel Celeron processors 2 6 2 Power Dissipation Standby Modes 1 System is shut down into Soft Off 85 or Suspend to Disk 84 by Windows 7 Professional 64 bit SP1 2 System is shut down into Soft Off 85 or Suspend to Disk 84 by Windows 7 Professional 64 bit SP1 with Wake On LAN enabled 3 System is shut down into Suspend to RAM S3 by Windows 7 Professional 64 bit SP1 4 System is shut down into Suspend to RAM S3 by Windows 7 Professional 64 bit SP1 with Wake On LAN enabled S3 4 S5 Module CPU p no WOL no WOL WOL enabled WOL enabled MSC CXB 6S 009 Intel Celeron 827E 17W MSC CXB 6S 004 Intel Core 3 2310E 35W MSC CXB 6S 001 Intel Celeron B810E 35W MSC CXB 6S 010 Intel Celeron 807UE 10W MSC CXB 6S 008 Intel Core i7 2715QE 45W MSC CXB 6S 006 12V 5V_SBY Intel Core i7 2610UE 17W MSC CXB 6S 005 Intel Core 5 2515E 35W MSC CXB 6S 002 Intel Celeron 847E 17W 12V only MSC CXB 6S 007 Intel Core i7 2655LE 25W 12V 5V_SBY 12V only MSC CXB 6SI 011 Intel Core i7 3612QE 35W 42v 5vV sBv MSC CXB 6SI 008 i Intel Core i7 3615QE 45W MSC CXB 6SI 005 Intel Core i5 3610ME 35W 12V only
22. the data determines the extent of the summary of the software This allows a third party to verify that the software has not been changed e Binding encrypts data using the TPM endorsement key a unique RSA key burned into the chip during its production or another trusted key descended from it e Sealing encrypts data in similar manner to binding but in addition specifies a state in which the TPM must be in order for the data to be decrypted unsealed Software can use a Trusted Platform Module to authenticate hardware devices Since each TPM chip has a unique and secret RSA key burned in as it is produced it is capable of performing platform authentication For example it can be used to verify that a system seeking access is the expected system 79 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 11 List of references 4 Turbo Boost http en wikipedia org wiki Intel Turbo Boost 5 ASPM http en wikipedia org wiki Active State Power Management 8 Intel Vt and VT d http ark intel com VTList aspx http www intel com technology it 2006 v1 0i3 2 io 7 conclusion htm 10 TPM http en wikipedia org wiki Trusted Platform Module 7 EAPI The Embedded Application Programming Interface EAPI used by this module provides a standardized interface for customer applications This interface allows a user mode application access to hardware specific information as well as hardware resources Following features are supporte
23. type Auto enumerates devices according to their media format Optical drives are emulated as CDROM drives with no media will be emulated according to a drive Note This option is appears only if a USB storage device is connected 6 1 8 6 Smart Settings CSC Smart Self Test Enabled Disabled Run Smart Self Test on all HDDs during Post 55 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 8 7 WB627 SIO Configuration rmm mm rem COM A Enabled Enable or disable COM A on Winbond SIO Disabled COM A Setting Auto Resource setting for COM A on Winbond SIO UO 3F8h IRQ 4 UO 3F8h IRQ 3 4 5 6 7 10 11 12 UO 2F8h IRQ 3 4 5 6 7 10 11 12 I O 3E8h IRQ 3 4 5 6 7 10 11 12 I O 2E8h IRQ 3 4 5 6 7 10 11 12 COM B Enabled Resource setting for COM A on Winbond SIO Disabled COM B Setting Auto Resource setting for COM A on Winbond SIO I O 2F8h IRQ 3 I O 3F8h IRQ 3 4 5 6 7 10 11 12 I O 2F8h IRQ 3 4 5 6 7 8 10 11 12 I O 3E8h IRQ 3 4 5 6 7 10 11 12 I O 2E8h IRQ 3 4 5 6 7 10 11 12 COM B Mode Normal IrDA1 2 Mode Setting for COM B on Winbond SIO ASK IR 1 4 LPT Disabled Enable or disable LPT on Winbond SIO Enabled LPT Setting Auto Resource setting for LPT A on Winbond SIO 1 0 378h IRQ 5 7 1 O 278 IRQ 5 7 56 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee mm eme LPT Mode SPP EPP 1 9 Mode setting
24. 3 3V Sus ePU 1 KO 48kHz fixed rate sample synchronization signal to the CODEC s PD 20 KO functional strap option sampled with rising edge of RSMRST eSR 33 O iPD is disabled after RSMRST de assertion HDA_BITCLK IO CMOS 33VSus eSR 330 24 00 MHz serial data clock generated by the PCH HDA SDOUT CMOS 3 3V Sus iPD 20KO Serial TDM data output to the CODEC functional strap option PD is PCH eSR 330 disabled after PLTRST de assertion Do not pull high externally HDA SDIN 0 2 E CMOS 3 3V Sus iPD 20 KQ Serial TDM data inputs from up to 3 CODECs eSR 330 15 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 2 Ethernet Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance GBEO_MDI 0 3 VO Analog 3 3V Sus 3 3V Gigabit Ethernet Controller 0 Media Dependent Interface Differential 82579LMi GBEO MDI 0 3 Pairs 0 1 2 3 The MDI can operate in 1000 100 and 10 Mbit sec modes MDI O B1_DA MDI 1 B1_DB MDI 2 B1_DC MDI S B1_DD GBEO_ACT OD CMOS 3 3V Sus 5V 20mA Gigabit Ethernet Controller 0 activity indicator active low 82579LM GBEO_LINK OD CMOS 3 3V Sus 5V 20mA Gigabit Ethernet Controller 0 link indicator active low 82579LM GBEO_LINK100 OD CMOS 3 3VSus 5V 20mA Gigabit Ethernet Controller 0 100 Mbit sec link indicator active low 82579LM GBEO_LINK1000 adi CMOS 3 3V Sus 5V 20 mA p Gig
25. Carrier Module SPI1 Module SPIO SPI1 28 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 18 Module Type Definition E Signal Power Remark PU PD SR Description Source Target A ae Level Rail Tolerance TYPE 0 2 On Type 2 The TYPE pins indicate to the Carrier Board the Pin out Type that is Carrier board logic module all implemented on the module The pins are tied on the module to Type Detect either ground GND or are no connects NC For Pin out Type 1 pins are n c these pins are dont care X TYPE2 TYPE1 TYPEO X X X Pin out Type 1 NC NC NC Pin out Type 2 NC NC GND Pin out Type 3 no IDE NC GND NC Pin out Type 4 no PCI NC GND GND Pin out Type 5 no IDE no PCI GND NC NC Pin out Type 6 no IDE no PCI The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off e g deactivates the ATX ON signal for an ATX power supply if an incompatible module pin out type is detected The Carrier Board logic may also implement a fault indicator such as a LED TYPE10 On COMX Rev 2 1 Type 2 modules this pin is n c Dual use pin Carrier board logic Indicates to the Carrier Board that a Type 10 Module is installed Indicates to the Carrier that a Rev 1 0 2 0 Module is installed TYPE10 NC Pin out R2 0 PD Pin out Type 10 pull down to ground with 4 7K resistor 12V Pin out R1 0 This pin is reclaimed from the VCC_12V pool In R1 0 Mod
26. GTT Size the GTT Size Aperture Size 128MB 256MB Select the coli P Size 512MB DVMT Pre Allocated 32 512MB in Select DVMT 5 0 Pre Allocated Fixed Graphics 32MB steps Memory size used by the SC Graphics Device 1024MB DVMT Total Gfx Mem 128M 256M Select DVMT5 0 Total Graphic Memory size used by MAX the Internal Graphics Device Gfx Low Power Mode Enabled This option is applicable for SFF only Disabled Graphics Performance Enabled Enable or disable Intel Graphics Performance Analyzer Disabled Analyzer Counters LCD Control LCD Control 6 1 11 2 LCD Control Submenu me est Se Primary IGFX Boot VBIOS Default Select the Video Device which will be activated Display CRT EFP LFP during POST EFP 3 EFP 2 LFP This has no effect if external graphics present Secondary boat display selection will appear based on your selection VGA modes will be supported only on primary display 66 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee mm rn LCD Panel Type Select LCD panel used by Internal Graphics Device 640x480 by selecting the appropriate setup item 800x600 Note resolutions in bold are 2PPC all other 1PPC timings 1024 768 1280x1024 1400x1050 RB 1400x1050 1600x1200 1366x768 1680x1050 1920x1200 1440x900 1600x900 1024x768 INV 1280x800 1920x1080 Panel Color Depth 18bit 24bit Select the LFP Panel Color Depth SDVO LFP Panel Type VBIOS Default Select SDVO panel u
27. Intel High Definition Audio Interface Support for up to three external Codecs Integrated DisplayPort HDMI Audio support PIC12C509A creates system reset programmable timeout 1s Optional TPM module TPM 1 2 SLB9635 4 pin header for support of a 12V PWM fan RTC integrated in PCH 255h 10 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual CMOS Battery External System Monitoring Voltages temperatures fan Core voltage 3 3V onboard voltage 12V input voltage 5V SBY input voltage CPU temperature 0 C 100 C System memory temperature Board temperature Fan speed and automatic fan speed control 2 5 Power Supply 412V primary power supply input 45V standby Option is not required for module operation If not present customer has to make sure that the supply voltages which are generated on the carrier board are switched off during suspend states so that no current from the carrier board s signal lines can flow to the CPU board 3 3V RTC power supply Option is not required for module operation BIOS SETUP data is stored in a non volatile backup memory device therefore configuration data will not get lost during power off except for time and date information Voltage Input range Power Consumption rey ta TeV 5V Standby ALT BY 5 25 V Refer to chapter 2 6 3V RTC power supply 2 0V 3 3V Typ 1 8 yA 2 6 Power Dissipation 2 6 1 Running Mode All measurements were mad
28. MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 8 Thermal Configuration m LI zm NI SMBusBuffer Lenth 1 2 5 9 10 14 20 SMBus Block Read message lenght Thermal Reporting Packet Enabled Disabled Enable Packet Error Checking PEC Error for SMBus Block Read DIMM1 TS Read Enabled Disabled DIMM1 Thermal Sensor Read DIMM2 TS Read Enabled Disabled DIMM2 Thermal Sensor Read PCH Thermal Device Enable or disable PCH Thermal Device D31 F6 6 1 8 1 Intel amp Rapid Start Technology Feature Options Description Intel Rapid Start Enabled Disabled Enable or disable Intel amp Rapid Start technology For more information see also technotes in chapter 6 7 6 1 8 2 Intel Trusted Execution Technology O e f rem Secure Mode Extensions Enabled Intel CPU SMX Support Enabled Disabled Intel TXT LT Support Enables or Disables Intel R TXT LT support For more information see also technotes in chapter 6 7 52 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 8 3 PCH FW Configuration m IL e Le MDES Bios Status Code Enabled Disabled Enable or disable MDES Bios Status Code Firmware Update Submenu Configure Management Engine Configuration Technology parameters 6 1 8 3 1 Firmware Update Configuration Submenu O ee oe f e Me FW Image Re Flash Enabled Disabled Enable Disable ME FW Image Re Flash function Note Enable this option if Bios update requires an update of the Intel Management Eng
29. SA Configuration 41 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual The Menu Bar The Menu Bar at the top of the window lists these selections EE MM I Use this menu for basic system information Advanced Use this menu to set the Advanced Features available on your system s chipset Chipset Use this menu to set Chipset Features Security Use this menu to set User and Supervisor Passwords and the Backup and Virus Check reminders Boot Use this menu to set the boot order in which the BIOS attempts to boot to OS Save amp Exit Saves and Exits the Aptio setup utility Use the left and right arrow keys on your keyboard to make a menu selection The Legend Bar Use the keys listed in the legend bar on the right side of the screen to make your selections or to exit the current menu The following table describes the legend keys and their alternates Esc Exit submenu Exit Setup utility without saving Left and right arrow keys Select Screen Up and down arrow keys Select Item Select an item To select an item use the arrow keys to move the cursor to the field you want Then use the plus and minus value keys to select a value for that field Alternatively the Enter key can be used to select a value from a Pop Up menu The Save Values commands in the Exit Menu save the values currently displayed in all the menus 42 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Display a submenu To display a submenu
30. T Vt d SMX and TPM must be enabled IAMT Intel Active Management Technology Intel Active Management Technology AMT is a technology for remotely managing and securing PCs out of band With AMT it is possible to remotely power up power down power cycle and reset the client computer Complete Systeminformation Hardware Software System Log is remotely available for the Administrator It is also possible to remote boot the PC and redirect to a CD ROM DVD or other boot device that is connected on the host pc This is usefull if the PC has a corrupted or missing OS Also it is possible to remotely redirect to the systems bios via console redirection through serial over LAN SOL This feature supports remote repair remote troubleshooting remote repair software upgrades and so on Intel VT and VT d Increasing manageability security and flexibility in IT environments virtualization technologies like hardware assisted Intel Virtualization Technology Intel VT combined with software based virtualization solutions provide maximum system utilization by consolidating multiple environments into a single server or PC By abstracting the software away from the underlying hardware a world of new usage models opens up that reduce costs increase management efficiency strengthen security while making your computing infrastructure more resilient in the event of a disaster For more information about the technology please visit http
31. TRLDATA strap option Port C detect CPU PD is disabled after PLTRST de assertion PEG RX8 IO CMOS 3 3V 3 PD 20KQ DDPD CTRLDATA strap option Port D detect CPU PD is disabled after PLTRST de assertion mu 3 3V 3V PEG LANE RV CMOS 3 3V 3V ePU 5 7 KQ PCI Express Graphics lane reversal input strap CPU Pull low on the carrier board to reverse lane order Be aware that the digital display interface that share this interface do not support reverse order functionality if this strap is low i li 3V PEG ENABLE CMOS 3 3V ePU 10 KQ PCI Express x16 external Graphics Enable Signal PCH MUX Pull low to enable the x16 interface PEG or PCle Pull high or leave as no connect to switch the PCHs digital display interface port B port C and port D to the COM Express connector Note Module input signal PEG ENABLE D97 must be low to select PEG PCle functionality 18 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 7 Express Card Support Pin Signal Power Remark PU PD Description Source Target Type Level Rail Tolerance EXCD 0 CPPE E CMOS 33V 3323V ePU 10KO ExpressCardcardrequest acivelov PCH_ EXCD t CPPE amp CMOS 3 3V 33V ePU 10 KO ExpressCardcardrequest activelow JPCH EXCD O RST O CMOS 3 33V 33V X ePU 82KO ExpressCard reset activelow__________________ PCH O EXCD t RST O CMOS 33V 33V X ePU 8 2K0 ExpressCard reset acti
32. TRST de assertion Multiplexed with PEG_RX3 mem ele Vil Merc NN CR TMDSC _ DIO 5 on module Multiplexed with PEG_TX 4 7 and PEG TX 4 SE ke EL Bee pr Multiplexed with PEG_RX5 TMDSC_CTRLDATA I O CMOS 3 3V iPD 20 KQ Port C HDMI DVI Control Data Multiplexed with PEG_RX5 strap option Port C detect iPD is disabled after PLTRST de assertion TMDSD DIO aL S module Multiplexed with PEG eg D and PEG TX 8 11 Multiplexed with PEG_RX8 TMDSD_CTRLDATA I O CMOS 3 3V LM A 20 KO Port D HDMI DVI Control Data Multiplexed with PEG RX8 strap option Port D detect PD is disabled after PLTRST de assertion Multiplexed with PEG RX11 Notes PEG ENABLE D97 from the carrier board must be high to select HDMI or DVI instead of PEG Additional level shifters are required on the carrier board or ADD 2 card in GE to translate TMDS data outputs into DVI HDMI signal format Video BIOS supports only SDVO on digital display port B Please ask your MSC representative if other options are required on port B 23 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 13 3 DisplayPort EE Type Level Rail Tolerance DPE ANEO o DPB_LANE 0 3 DPB_AUX 1 0 Soa Jl Port B DisplayPort Lane 0 3 differential pairs PCH Multiplexed with PEG_TX 0 3 and PEG TX 0 3 AC coupled Port B DisplayPort Aux control channel differential pair on module Multiplexed with PEG RX4 and PEG RX4 AC coupled on module CMOS 3 3V 3
33. User can Enable Disable PET Events progress to receive PET events or not Watchdog Enabled Disabled Enable or disable Watchdog timer 6 1 8 5 USB Configuration C ee ce Legacy USB Support Auto Enabled Disabled Enables Legacy USB support AUTO option disables legacy support if no USB devices are connected DISABLE option will keep USB devices available only for EFI applications EHCI Hand off Enabled Disabled This is a workaround for OSes without EHCI hand off support The EHCI ownership change should be claimed by EHCI driver 54 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual me omm om Port 60 64 Emulation Enabled Disabled Enables UO port 60h 64h emulation support This should be enabled for the complete USB keyboard legacy support for non USB aware OSes USB transfer time out 1 5 10 20 sec The time out value for Control Bulk and Interrupt transfers Device reset time out 10 20 30 40 sec USB mass storage device Start Unit command time out Device power up delay Auto Manual Maximum time the device will take before it properly reports itself to the Host Controller Auto uses default value for a Root port it is 100 ms for a Hub port the delay is taken from Hub descriptor Device power up delay Value 1 40 Delay range is 1 40 seconds in one second increments USB Mass Storage Auto Floppy Forced FDD Select Mass storage device emulation Device e g USB Stick Hard Disk CD ROM
34. Vu Intelligent Solutions Engineering Leadership User Manual COM Express Basic Module MSC CXB 6S CXB 6SI Type 2 Pin out 2 4 3 Generation Intel Core Processor Family Intel 6 7 Series Chipset Rev 1 8 2015 04 15 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Preface Copyright Notice Copyright O 2014 MSC Technologies GmbH All rights reserved Copying of this document and giving it to others and the use or communication of the contents thereof is forbidden without express authority Offenders are liable to the payment of damages All rights are reserved in the event of the grant of a patent or the registration of a utility model or design Important Information This documentation is intended for qualified audience only The product described herein is not an end user product It was developed and manufactured for further processing by trained personnel Disclaimer Although this document has been generated with the utmost care no warranty or liability for correctness or suitability for any particular purpose is implied The information in this document is provided as is and is subject to change without notice EMC Rules This unit has to be installed in a shielded housing If not installed in a properly shielded enclosure and used in accordance with the instruction manual this product may cause radio interference in which case the user may be required to take adequate measures at his or her owns expen
35. abit Ethernet Controller O 1000 Mbit sec link indicator active 82579LM low pc ee y o GBEO CTREF REF N A Center tab voltage not needed by 82759LM 2 10 3 IDE Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance IDE_D 0 6 8 15 CMOS eSR 330 Bidirectional data to from IDE device JMB368 IDE_D7 CMOS eSR 330 Bidirectional data to from IDE device JMB368 IPD 32kQ IDE A 0 2 O CMOS eSR 330 __ Address lines to IDE device JMB368 IDE_lOW O CMOS eSR 220 I O write line to IDE device Data latched on trailing rising edge JMB368 IDE IOR O CMOS eSR 220 I O read line to IDE device JMB368 IDE REQ CMOS 3 3V 3 3V ePD 5 6 KO IDE device DMA Request Asserted by IDE device to request a data JMB368 eSR 82 0 transfer PD 32 KO IDE_ACK IO CMOS eSR 220 IDE Device DMA Acknowledge JMB368 IDE_CS1 O CMOS eSR 33 0 IDE Device Chip Select for 1FOh to 1FFh range JMB368 IDE_CS3 O CMOS eSR 330 IDE Device Chip Select for 3FOh to 3FFh range JMB368 IDE IORDY CMOS 3 3V 3 3V ePU 4 7 KO IDE device I O ready input Pulled low by the IDE device to extend JMB368 eSR 820 the cycle PU 47 KO IDE RESET O CMOS eSR 330 Reset output to IDE device active low JMB368 IDE IRQ CMOS ePD 10 KQ Interrupt request from IDE device JMB368 16 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Pin Signal Power Remark PU PD SR Description
36. ath to future CPU technologies Utilizing different sizes COM Express can be used for highly embedded solutions up to high performance platforms The design of the MSC CXB 6S module supports the 2 Generation Intel Core Processor Family enabling you to boost your embedded application to highest performance levels For evaluation and design in of the COM Express modules we offer evaluation baseboards and develop motherboards providing the interface infrastructure for the COM Express module using PC type connectors for external access Currently three module sizes are defined in the COM Express Specification 2 0 the Compact Module Basic Module and the Extended Module The primary difference between them is the over all physical size and the performance envelope supported by each The Extended Module is the largest and can support larger processor and memory solutions The Basic Module is the most common supporting typical processor platforms in the embedded world The Compact Module is the smallest one and is intended to be used when designing with processors and chipsets in small form factor footprints SFF All module sizes use the same connectors and pin outs and utilize several common mounting hole positions This level of compatibility allows that a carrier board designed to accommodate an Extended Module can also support a Basic or Compact Module Up to 440 pins of connectivity are available between COM Express modules and the Ca
37. ct your sales representative 14 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 Signal description Pins are marked in the following tables with the power rail associated with the pin and for input and I O pins with the input voltage tolerance The pin power rail and the pin input voltage tolerance may be different For example the PCI group is defined as having a 3 3V power rail meaning that the output signals will only be driven to 3 3V but the pins are tolerant of 5V signals An additional label Sus indicates that the pin is active during suspend states S3 S4 S5 If suspend modes are used then care must be taken to avoid loading signals that are active during suspend to avoid excessive suspend mode current draw Input O Output OD Open Drain output 1 OD Bi directional Input Open Drain Output Pin I O Bi directional Input Output ePU external pull up resistor on COM Express module ePD external pull down resistor on COM Express module eSR external series resistor on COM Express module iPU integrated pull up resistor inside PCH or other IC real value may vary from nominal one iPD integrated pull down resistor inside PCH or other IC real value may vary from nominal one 2 10 1 High Definition Audio Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance HDA_RST lO CMOS 333VSus eSR 330Q ___ Reset output to CODEC active low HDA SYNC CMOS
38. d view board information access to NVRAM access to l2C control GPIO s control backlight Set watchdog timer View sensor values of hardware monitor MSC provides a software package which is downloadable here after registration www msc technologies eu support boards 80 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 8 Troubleshooting Problem 1 USB stick recognized as floppy Some USB sticks are recognized as floppies show up as A drive under DOS If this is not wanted there is way to handle such a USB stick as a fixed disk int13h device 8xh Solution For USB you can check in BIOS setup program under Advanced gt USB Configuration and at the bottom it should have a list of USB mass storage devices Here you can choose between Floppy Forced Floppy Hard Disk or CD ROM behavior of your USB stick Problem 2 ADD2 card not recognized In some cases the Digital Display Port B will not be enabled when used as SDVO port The SDVO_CTRLDATA pin is defined in the 3 3V plane of the PCH Originally SDVO control signals were defined as 2 5V level signals The SDVO CTRLDATA pin has a 20k pull down inside the PCH which is active during power up The minimum high level of the PCH to recognize an enabled SDVO port is 0 7 x 3 3V The internal pull down may cause that this level is not achieved Solution The pull up resistor at the SDVO CTRLDATA pin on the ADD2 card must be set to an appropriate value For additi
39. e but the graphical boot screen can be enabled in the bios setup The standard boot screen is a black screen without any logo 6 1 3 Activity Detection Background While the startup screen is displayed press the Setup Entry key ESC or DEL The system acknowledges the input and at the end of POST the screen clears and setup launches 6 1 4 Aptio Setup Utility With the AMI Aptio Setup program you can modify Aptio settings and control the special features of your computer The setup program uses a number of menus for making changes and turning the special features on or off This chapter provides an overview of the setup utility and describes at a high level how to use it 6 1 5 Configuring the System BIOS To start the AMI Aptio Setup utility press ESC or DEL to launch Setup The setup main menu appears 40 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual The BIOS Menu Structure The BIOS Menu is structured in the following way MSC Board Info Hardware Monitoring Measurement PCI Subsystem Settings ACPI Settings Trusted Computing CPU Configuration SATA Configuration Thermal Configuration Intel amp Rapid Start Technology Intel TXT LT Configuration AMT Configuration USB Configuration Smart Settings WB627 SIO Configuration HWM ADT7490 Configuration PIC Watchdog Configuration Serial Port Console Redirection Intel ICC PCH IO Configuration System Agent
40. e by plugging the module onto a MSC CX EVA2 evaluation board The module was equipped with two 4GByte memory modules NANYA NT4GC64B8HBONS CG 1112 CN 4GB 2Rx8 PC3 10600S 9 10 F2 1333 The table below shows typical values which refer to consumption of the module itself without consumption of the base board and CPU fan The following applications have been tested at room temperature 1 DOS prompt 2 Windows desktop idle under Microsoft Windows 7 Professional 64 bit SP1 3 Running Intel Thermal Analysis Tool TAT Ver 4 3 to achieve 70 CPU workload on each processor core thread and 10096 Graphics workload as recommended by Intel under Microsoft Windows 7 Professional 64 bit SP1 i Module CPU Win 7 Idle E long term max MSC CXB 6S 010 5 Intel Celeron 807UE 10W MSC CXB 65 009 2 Intel Celeron 827E 17W f Ee 5QE 45W E RA Ee OUE 17W Were qu NNNM 11 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual MSC CXB 65 004 2 Intel Core 3 2310E 35W i MSC CXB 65 002 2 Intel Celeron 847E 17W MSC CXB 65 001 2 Intel Celeron B810E 35W MSC CXB 6SI 011 MSC CXB 6SI 008 Intel Core i7 3615QE 45W Tero Intel Core 5 3610ME 35W 1 Due to the Intel Turbo Boost Technology 2 0 feature on 2 Generation Intel Core i5 and 2 Generation Intel Core i7 processors the maximum power consumption for short durations may be higher than the long term power consumption The power
41. e le TE EE 8 2 8 COM Express Implementaton nennen nennen nnn nnns nhinnnen nsns 9 2 4 Functional units eese nennen eee nisi d nnn aaa s sisi nnn rnnt nr nsn sented 10 2 5 PowerSupply iu dde BRE HE HH id a dd 11 2 6 Power EE 11 2 6 1 lie ln Ree EE 11 2 6 2 Power Dissipation Standby Modes nennen nnn 12 2 7 System Memonm AN 13 2 8 Mechanical Dimensions A 13 2 8 1 Gompactmoduls s tetti tni 13 2 9 Neu EI ee E 14 2 10 Signal description 15 2 10 Eligh Definitioni AUGIO TTT 15 2 10 27 tu 16 PO S 16 le E EIERE 17 LODO PGl Express Lares eee eee e 18 2 10 6 PCI Express x16Graphic Lanes sse enne nennen nnn nnn 18 2 10275 Express Gard SUppolt sni err rea ten tutu ens tun pe e RR 19 2 10 8 POL BUS t He HE Ha i n e e o a er Fe n Fn Fed ee b d 19 AS RM 20 2 10510 e EEEEEEEEEEE 21 21011 LVDS Flat VER 21 2 10 12 Analog VG int t tet t t te e ate ete e t ia ete ob rte Ea tet te Leber adu 21 2 10 13 Digital Display Interfaces eee eee ted eee bide 22 2 10 14 Miscellaneous oooocccccnnnononccnnnncnnnnnnnnnncnnnn nro naar nn nr cnn nn eee nr nn nn r enana nr rn nr ran nr ran nnnn nn rnrannrnennnnes 25 2 10 15 Power and System Management 26 2 10 16 General Purpose lO cocoa em eem en emn t ee 27 2 10 Ke Wien ET 28 2 10 18 Module Type Definition enne n nenne nnns neni nnn 29 2310519 Power and GND eode o 30 2 11 Pin List for MSC CXB 6S module Type 2 31 2 12 DDI Port Pi
42. ement ome om Rm Enabled Disabled Turbo Mode CPU C3 Report Enabled Disabled CPU C6 Report Enabled Disabled CPU C7 Report Enabled Disabled Configurable TDP TDP Nominal TDP Down TDP Up Disabled Enabled Disabled Config TDP LOCK Long duration power limit Short duration power limit 0 x 50 81 Enabled Disabled 0 x Enable or disable Intel Speedstep For more information see also technotes in chapter 6 7 Enable or disable Turbo Mode For more information see also technotes in chapter 6 7 Enable or disable CPU C3 ACPI C2 report to OS Enable or disable CPU C6 ACPI C3 report to OS Enable or disable CPU C7 ACPI C3 report to OS Allow reconfiguration of TDP levels base on current power and thermal delivery capabilities of the system Note This setting appears only on specific Celeron CPU s Example for Celeron 3217UE TDP Nominal TDP is in short duration 4W above normal TDP After this time TDP is normal until system load ends and starts again TDP Down TDP is in short duration 4W above normal TDP After this time TDP is 4W under normal TDP until system load ends and starts again TDP up and disabled is same as nominal for this CPU Lock the Config TDP control register Long duration power limit in Watts O means use factory defaults Min and max value depends on type of CPU Time window in seconds which the short duration power is maintained Short duration power
43. es will not be applied unless Accept changes is pressed Changes will be applied permanently starting after the next reboot Use it to provide changes that are verified and safe Apply settings permanently after reboot Apply settings Changes will be applied immediately but forgotten immediately after reboot This mode of making changes is more likely to cause platform instability and spontaneous restart 6 1 9 Chipset anwe E PCH IO Configuration PCH parameters System Agent SA Submenu System Agent SA parameters Configuration 6 1 10 PCH IO Configuration PCI Express Submenu PCI Express Configuration settings Configuration USB Configuration USB Configuration settings PCH Azalia Submenu PCH Azalia Configuration settings Configuration Bios Security Submenu Bios Security Configuration settings Configuration PCH LAN Controller Enabled Enable or disable onboard NIC Disabled 61 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual rmm me rem Wake on LAN Enabled Enable or disable integrated LAN to wake the Disabled System Board Capability SUS PWR DN Board Capability SUS PWR DN ACK gt Send _ACK DeepSx Disabled to PCH DeepSx gt Show DeepSx Policies Display Logic Enabled Enable or disable the PCH Display logic Disabled CLKRUN Logic Enabled Enable the CLKRUNZ logic to stop the PCI clocks Disabled SB CRID Enabled Enable or disable the PCH Display logic Disabled High Preci
44. evice in PEG Device Disabled De emphasis Control 6 dB 3 5dB Both Root and Endpoint Ports PEG Sampler Calibrate Auto Enabled Enable or disable PEG Sampler Calibrate Auto Disabled means disabled for SNB MB DT ENbaled for IVB AO BO Swing Control Full Half Perform PEG Swing Control on IVB CO and later Reduced Fast PEG Init endis Enable or disable Fast PEG Init Some optimization if no PEG devices present in cold boot Enabled RxCEM Loop back Disabled Enable or disable RxCEM Loop back RxCEM Loop back lane Fines Selection RxCEM Loop Back lane 6 1 11 5 Memory Configuration ome f mee o om o Memory Information Displays Information about installed Memory DIMM profile Default DIMM Select DIMM timing profile that should be used profile Custom Profile XMPprofile1 XMP profile 2 69 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee mm eme Memory Frequency Auto 1067 Maximum Memory Frequency selections in MHz 1333 1600 1867 1867 2133 2400 2667 ECC Support Enabled Enable or disable DDR Ecc Support Disabled Max TOLUD Dynamic 1GB Maximum Value of TOLUD Dynamic assignment to 3 25 GB in would adjust TOLUD automatically based on largest 0 25GB steps MMIO length of installed graphic controller NMode Support Auto 1N Mode NMode Support Option 2N Mode Memory Scrambler Enabled Enable or disable Memory Scrambler support Disabled MRC Fast Boot Enabled Enable or disable MRC fast b
45. faults Boot Override It will display all the available boot options from the Boot Option List The user can select any of the options to select to the particular device and boot directly from it Launch EFI Shell from filesystem device Attempts to Launch EFI Shell application Shellx64 efi from one of the available filesystem devices 6 2 BIOS and Firmware Update If a System BIOS update is required please follow these instructions Bios Update from DOS Create a bootable DOS disk USB Stick or hard disk and unpack the update tool AFUDOS exe from AFUx64 301 msi Copy the files afudos exe uefi rom and update bat to this device Boot the system from this device Type update to update the System Bios When the Bios update has finished reboot the system Bios Update under Windows Copy the afuwingui exe amifldrv32 sys and the bios image uefi rom to a storage media e g USB stick Boot Windows XP or Windows 7 Copy the 3 files from your storage media to your Harddisk Run afuwingui exe Make sure that no other application is running to avoid crashes during the update procedure Select Open and choose the bios image file uefi rom After it has opened a new Tab Window will be displayed where you can choose what block options should be updated To make sure all relevant updates will be updated select Program all Blocks All Blocks should be marked now Click the Button Flash and Bios update w
46. for D Disabled Azalia 6 1 10 4 Security Information mee mm eme SMI Lock Enabled Enable or disable SMI lockdown Disabled BIOS Lock Enabled Enable or disable BIOS lock enable BLE bit Disabled GPIO Lock Enabled Enable or disable GPIO lockdown Disabled BIOS Interface Lock Enabled Enable or disable BIOS Interface lockdown Disabled RTC RAM Lock Enabled Enable or disable bytes 38h 3Fh in the upper and Disabled lower 128 byte bank of RTC RAM lockdown 6 1 11 System Agent SA Configuration Feature Options Description Enabled Disabled Check to enable VT d function on MCH CHAP Device B0 D7 FO SC Enable or disable SA CHAP Device Thermal Device Sei Enable or disable SA Thermal Device BO D4 FO Enable NB CRID E Enable or disable NB CRID Workaround Disabled f BDAT ACPI Table Enabled Enables support for the BDAT ACPI table Support Disabled Memory Thermal Submenu Memory Thermal Configuration settings Configuration 65 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Description GT Power Management GT Power Management Control settings Control 6 1 11 1 Graphics Configuration rmm mm rem Graphics Turbo IMON C SE turbo IMON current values supported 14 Primary Display Auto Select which of IGFX PEG PCI Graphics device IGFX PEG PCI should be Primary Display Internal Graphics Auto Disabled Keep IGD enabled based on the setup options Enabled GTT Size 1MB 2MB Selectthe
47. for LPT on Winbond SIO ECP ECP EPP 1 9 Printer Mode EPP 1 7 ECP EPP 1 7 6 1 8 8 HWM ADT7490 Configuration mee mm en E Fan 1 Control Temperature Define how the fan should be controlled manually based Manual set to a fixed duty cycle or temperature based auto control Temperature Source CPU Board Fan is controlled by either CPU or board temperature Minimum Fan Speed 25 50 100 Set the fan duty cycle for manual fan control Note Only possible if Fan 1 Control is set to manual CPU Low Temperature 30 C 40 C Temperature in degrees Celsius when exceeded 50 C 60 C controls fan to minimum speed CPU High Temperature 70 C 80 C Temperature in degrees Celsius when exceeded controls fan to maximum speed CPU Temperature The value in degree Celsius that the temperature Hysteresis has to fall below a certain threshold before minum fan speed will be enabled Board Low Temperature 30 C 40 C Temperature in degrees Celsius when exceeded 50 C 60 C controls fan to minimum speed Board High 70 C 80 C Temperature in degrees Celsius when exceeded Temperature controls fan to maximum speed Board Temperature The value in degree Celsius that the temperature Hysteresis has to fall below a certain threshold before minum fan speed will be enabled 6 1 8 9 PIC Watchdog Configuration me Lei e Watchdog Start on Boot Enabled Select if the watchdog should be started at the end
48. he user is using will exchange data Both computers should have the same or compatible settings Console Redirection Settings COMO Submenu me em Jn Terminal Type Emulation ANSI Extended ASCII char set VT100 ASCII char set VT100 Extends VT100 to support color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes ANSI VT100 VT100 VT UTF8 58 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee omm rn Bits per second 9600 19200 Selects serial port transmission speed The speed 38400 57600 must be matched on the other side Long or noisy 115200 lines may require lower speeds Data Bits Data Bits None Even A parity bit can be sent with the data bits to detect Odd Mark some transmission errors Even parity bit is O if the Space num of 1 s in the data bits is even Odd parity bit is O if num of 1 s in the data bits is odd Mark parity bit is always 1 Space Parity bit is always 0 Mark and Space Parity do not allow for error detection They can be used as an additional data bit Stop bits indicate the end of a serial data packet A start bit indicates the beginning The standard setting is 1 stop bit Communication with slow devices may require more than 1 stop bit Flow Control None Hardware Flow control can prevent data loss from buffer RTS CTS overflow When sending data if the receiving buffers are full a stop signal can be sent t
49. ill start After update is finished all blocks are green restart your system Note The Amiflash tool for windows can be downloaded from www ami com 74 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Bios Update from EFI Shell Create a FAT32 formatted removable device and unpack the update tool AfuEfix64 efi from AFUx64 301 msi e Copy an EFI Shell shellx64 efi into the root directory of the device e Copy the files Afuefix64 efi uefi rom update nsh to this device e Enter System setup and under the menu bar Save and Exit choose Launch EFI Shell from filesystem device e After Shell is loaded type fsO update nsh e When the Bios update has finished reboot the system Note If an EFI Shell is needed for Bios updates please contact MSC Technical support Note After the system has been updated the setup settings will be changed to defaults and therefore it may be necessary to enter Setup to reconfigure the system settings 6 3 Blind Restoration of Bios default settings no display available Power up the System Repeatedly press DEL for several seconds Press F3 for default settings or F2 for previous values Press Enter Press F4 Press Enter System will restart 6 4 Restore Bios settings from file It is possible to save configured Bios settings and copy these settings to other boards which have the same Bios version Configure the setup as required Load DOS or EFI Shel
50. imum speed Turbo Boost Technology won t be available 771 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 4 Turbo Boost Technology 2 0 Intel Turbo Boost is a technology that enables the processor to run above its base operating frequency via dynamic control of the CPU s clock rate It is activated when the operating system requests the highest performance state of the processor The increased clock rate is limited by the processor s power current and thermal limits as well as the number of cores currently in use and the maximum frequency of the active cores For more information about Intele Turbo Boost 2 Technology visit the Intelewebsite Note Turbo Boost will only work if EIST is enabled ASPM Active State Power Management Active State Power Management or ASPM is a power management protocol used to manage PCI Express based serial link devices as links become less active over time As serial based PCle bus devices such as IEEE1394 FireWire become less active it is possible for the computer s power management system to take the opportunity to reduce overall power consumption by placing the link PHY into a low power mode and instructing other devices on the link to follow suit TXT Trusted Execution Technology Due to the complexity of this feature please visit http www intel com content dam www public us en documents white papers trusted execution technology security paper pdf Note To use this feature V
51. ine ME See the Readme txt which comes with the actual Bios file 6 1 8 4 AMT Configuration C ee oe NEN NN Intel AMT Enabled Disabled Enable Disable Intel R Active Management Technology BIOS Extension Note iAMT H W is always enabled This option just controls the BIOS extension execution If enabled this requires additional firmware in the SPI device Note To configure AMT settings press CTRL P after System powered on For more information see also technotes in chapter 6 7 BIOS Hotkey Pressed Enabled Disabled OEMFLag Bit 1 Enable Disable BIOS hotkey press 53 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual O ee oe f e MEBx Selection Screen Enabled Disabled OEMFLag Bit 2 Enable Disable MEBx selection screen Hide Un Configure ME Enabled Disabled OEMFlag Bit 6 Hide Un Configure ME without password Confirmation Prompt MEBx Debug Message Enabled Disabled OEMFlag Bit 14 Output Enable MEBx debug message output Un Configure ME Enabled Disabled OEMFlag Bit 15 Un Configure ME without password Amt Wait Timer Value Set timer in seconds to wait before sending ASF_GET_BOOT_OPTIONS Disable ME Enabled Disabled Set ME to Soft temporary disabled AS Enabled Disabled Enable Disable Alert Specification Format Activate Remote Enabled Disabled Trigger CIRA boot Assistence USB Configure Enabled Disabled Enable Disable USB Configure function PET Progress Enabled Disabled
52. ital Display Interface signals Refer to chapter 2 10 13 COM Express Connector COM Express pin D97 PEG_ENABLE 1 Name Pin PEG RXO0 C52 SDVO TVCLKIN SDVO TVOU PEG RXO C53 SDVO TVCLKIN Synchronization Clock PEG RX1 C55 SDVOB_INT SDVO Port B Interrupt PEG RX1 C56 SDVOB INT Input Differential Pair PEG RX2 C58 SDVOB_FLDSTALL SDVO Field Stall Input PEG RX2 C59 SDVOB FLDSTALL Differential Pair PEG RX3 C61 TMDSB HPD HDMI Port B Hot Plug Detect DPB HPD DisplayPort B Hot Plug Detect PEG RX4 C65 DPB_AUX DisplayPort B Auxiliary PEG_RX4 C66 DPB AUX Differential Pair PEG_RX5 C68 TMDSC CTRLCLK HDMI Port C Control Clock IC PEG RXS C69 TMDSC CTRLDATA HDMI Port C Control Data C DPC_ CTRLDATA Refer to Note 1 PEG RX6 C71 DPC_AUX DisplayPort C Lane3 PEG RXe6 C72 DPC AUX differential Pair SDVO CTRLDATA C73 SDVO CTRLDATA SDVO Control Data IC TMDSB CTRLDATA HDMI Port B Control Data C DPB CTRLEDATA Refer to Note 1 PEG RX7 C74 TMDSC HPD HDMI Port C Hot Plug Detect DPC HPD DisplayPort C Hot Plug Detect PEG RX8 C78 PEG RX8 C79 DPD CTRLDATA Refer to Note 1 PEG RX10 C85 DPD_AUX DisplayPort D Auxiliary PEG_RX10 C86 DPD AUX Differential Pair PEG RX11 C88 DPD HPD DisplayPort D Hot Plug Detect PEG RX11 C89 PEG_TX0 D52 SDVOB_RED SDVO Port B Red TMDSB_DATA2 HDMI Port B Data 2 DifferentialDPB LANEO DisplayPor
53. l with afudos exe for DOS or afuefix64 efi for EFI Shell Run afudos exe afuefix64 efi with following switch to save current Bios Afudos exe filename o Afuefix64 efi filename o To copy these Bios settings onto another module run afudos exe or afuefix64 efi with following switch Afudos exe filename n R Afuefix64 efi filename n R Only the Bios settings will be updated without flashing the complete Bios 75 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual If complete Bios update is also needed additional switches are needed Afudos exe filename p b n x Afuefix64 efi filename p b n x 6 5 Bios Recovery If an Bios update will be interrupted e g due to power loss and the update has not been finished it can be that the system will not boot In this case it is possible to restore the Bios with the following method 1 Copy the bios file uefi rom in the root folder of an USB stick 2 Connect the USB stick with the system which was not correctly updated 3 Short the recovery jumpers as seen in chapter 3 1 and turn on system Wait until you see the bios setup screen with the recovery options then disconnect shorted jumpers 4 Check that Reset NVRAM and Main Block Update is enabled Select Proceed with flash update 6 Bios will be restored m 6 6 Post Codes For Post Code information please contact MSC Technical Support Email support msc technologies eu Phone 49 8165 906 200 76 81
54. le PCI Express Unsupported Disabled Request Reporting FER Enabled Enable or disable PCI Express Device Fatal Error Disabled Reporting NFER Enabled Enable or disable PCI Express Device Non Fatal Disabled Error Reporting CER Enabled Enable or disable PCI Express Device Correctable Disabled Error Reporting CTO Enabled Enable or disable PCI Express Completion Timer Disabled TO SEFE Enabled Enable or disable Root PCI Express System Error Disabled on Fatal Error Enabled Enable or disable Root PCI Express System Error Disabled on Non Fatal Error SECE Enabled Enable or disable Root PCI Express System Error Disabled on Correctable Error PME SCI Enabled Enable or disable PCI Express PME SCI Disabled Hot Plug Enabled Enable or disable PCI Express Hot Plug Disabled PCle Speed Geni Gen2 Select PCI Express port Speed Extra Bus Reserved 0 Extra Bus Reserved 0 7 for bridges behind this Root Bridge Reserved Memory 1 20MB Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Reserved I O Value Reserved I O 4K 8K 12K 16K 20K Range for this Root Bridge 63 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 10 2 USB Configuration Submenu rmm o me rem XHCI Pre Boot Driver Enabled Enable or disable XHCI Pre Boot Driver support Disabled XHCI Mode Smart Auto Mode of operation of xHCI controller Auto Enabled Disabled HS Port 1 4 Enabled Allows for HS port switching bet
55. limit in Watts O means use factory defaults Min and max value depends on type of CPU MSC CXB 6S CXB 6SI Rev 1 8 User Manual O ee e o e ACPI T State Enabled Disabled Enable or disable ACPI T state support 6 1 7 6 SATA Configuration m o JL rem SATA Controller s Enabled Disabled Enable or disable SATA DEVICE SATA Mode Selection AHCI IDE RAID Software Feature Mask Configuration For more information see also technotes in chapter 6 7 SATA Test Mode Enabled Disabled Enable or disable Test Mode Note If you have problems with your Sata Device try to enable Test Mode Aggressive LPM Support Enabled Disabled Enable PCH to aggressively enter link power state SATA Controller Speed Gent Gene ade Indicates the maximum speed the SATA controller can support Note For GENG it is highly recommended to use SATAS cables Pox Potoa x Por Potx Potoa 4 Enabled Disabled Disabled Enable or disable SATA Port Enable or disable SATA Port disable SATA Port Hot Plug Port 0 4 Enabled Disabled CT this port as HOT pluggable External SATA Port 0 4 Enabled Disabled External SATA Support SATA Device Type Port Hard Disk Driver Solid State Identify the SATA port is connected to 0 1 Driver Solid State Drive or Hard Disk Drive Spin Up Device Port 0 4 Enabled Disabled On an edge detect from 0 to 1 the PCH starts a COMRESET initialization sequence to the device 51 81
56. m Assignment ini hn ro n E ee E rrt pitt 33 1 CTRLDATA pins do have strap functionality and are sampled during power up A high level on these pins enables the appropriate DDI port B C or D inside the PCH c 00occonnccccccccoccncnnncconanananoncnnnncnnnnnnnn anos 34 3 Jumpers and Corinectors i e HE P P EP PP Pa PEE Po EP i Eee bea 35 SANTER 35 3 2 Retro 36 A Watchdog EE 36 SENE EELER a EE 37 bs SPGEIBOIBOUlIB ar eos ee A et Met OLI EUER 37 5 21 IBGbinespnAPIG MOGe oorr eer ed 38 5 3 Carrier Board PCI Resource Allocation 39 5 4 SMB Address Map 39 0 BIOS o m oh ce m e EE 40 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 156 The Main Menus nee tt E a E Ha E P EE Pr a Pe P n Pe P a be aedes 43 ox 7 ThesAdvanced Menus rere re terere drei n DATES 45 ENEE ue AAA AAA AAA 61 A ee e 71 lee EES 72 6 1 14 The Save amp Exit Mem 73 6 2 BIOS and Firmware Update eene nnne nenne nennen nner isses nnn nnns 74 6 5 Bos R Gewe iaa e ERE E FERE RE ERE ONERE E ER iti eee 76 6 7 Tech NOTES tienta ooo ee ee en ee 77 T SBAP sheet ei ENESA EAE EA ol het A EEEE thea vhve wayyy huh then vaya 80 8 Troubleshooting iie bett EP E ERE PE EE ERR EE eb ea iet 81 4 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 1 General Information 1 1 Revision History Description Rev Date 1 2 Reference Documents 1 COM Express Module Base Specification COM Express Revision 2 0 Last update August 8 2010
57. o stop the data flow Once the buffers are empty a start signal can be sent to re start the flow Hardware flow control uses two wires to send start stop signals VTUF8 Combo Key Enabled Enable VT UF8 Combination Key Support for Support Disabled ANSI VT100 terminals Recorder Mode Disabled With this mode enabled only text will be sent This is Enabled to capture Terminal data Resolution 100x31 Disabled Enables or disables extended terminal resolution Enabled Legacy OS Redirection 80x24 80x25 On Legacy OS the number of rows and Columns supported redirection Putty KeyPad VT100 Linux Select FunctionKey and KeyPad on Putty XTERMRE SCO ESCN VT400 6 1 8 10 2 Console Redirection EMS e Lei ee Out of Band Mgmt Port COMO COM1 Microsoft Windows Emergency Management Services EMS allows for remote management of a Windows Server OS through a serial port 59 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee mm en Terminal Type ANSI VT100 Emulation ANSI Extended ASCII char set VT100 VT100 VT ASCII char set VT100 Extends VT100 to support UTF8 color function keys etc VT UTF8 Uses UTF8 encoding to map Unicode chars onto 1 or more bytes Bits per second 9600 19200 Selects serial port transmission speed The speed 57600 115200 must be matched on the other side Long or noisy lines may require lower speeds Flow Control None Hardware Flow control can prevent data loss from buffer
58. odule An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board 20 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 10 LPC Bus Poel ur uuum umm em ee Type Level Rail Tolerance LPC_FRAME O CMOS 33V LPC frame indicates the start of an LPCcycle LPC_DRQ o 1 CMOS 3 3V 3 3V iPU 20KQ j LPCserialDMArequst 1 LPC CLIK o CMOS 33V JesR 220 _ LPC clock output 33MHz nomina Cd 2 10 11 LVDS Flat Panel Pow tme tew Rat Tone E Type Level Rail Tolerance e TUTE LVDS A 0 3 pur m 1 Jum 1 LVDS A CK EET NN GEN I RII dna AN LVDS B 0 3 LVDS B CK LVDS LVDS Channel B differential clock LVDS B CK LVDS VDD EN O CMOS 33V ePD 100KQ LVDS panel power enable LVDS BKLT EN Jo CMOS 33V ePD 100KQ LVDS panel backlight enable LVDS BKLT_CTRL O CMOS 33V LVDS panel backlight brightness control LVDS I2C CK O CMOS 33V ePU 22KQ I2C clock output for LVDS display use LVDS I2C DAT l OD CMOS 3 3V 3 3V ePU 2 2 KO I2C data line for LVDS display use PCH iPD220KO LVDS detect PD is disabled after PLTRST de assertion 2 10 12 Analog VGA Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance VGA_RED Analog ePD 150 Q Red for monitor Analog DAC output designed to drive a 37 5 Ohm PCH equi
59. on Pulled to GND by Carrier Board device or by Slot Card if the devices are NOT capable of 66 MHz operation Note The PCI bus is realized by a Texas Instruments XIO2001 PCle to PCI bridge located on PCle lane 5 Therefore PCIe lane 5 isn t available for external use by default 2 10 9 USB Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance Ic NAR 7 E EST 3 bil Sus 3 E BEEN differential pairs channels O through 7 Ic NAR 7 USB 0 1_OCH Mal 3 e Sus 3 EC ePU 82 ME USB channels 0 and 1 over current sense A pull up for this line is present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board USB 2 3 OC CMOS 3 3V Sus 3 3V ePU 8 2 KO USB channels 2 and 3 over current sense A pull up for this line is present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board USB 4 5 OCH CMOS 3 3V Sus 3 3V ePU 8 2 KO USB channels 4 and 5 over current sense A pull up for this line is present on the module An open drain driver from a USB current monitor on the Carrier Board may drive this line low Do not pull this line high on the Carrier Board USB 6 7 OCH CMOS 3 3V Sus 3 3V ePU 8 2 KO USB channels 6 and 7 over current sense A pull up for this line is present on the m
60. onal help contact MSC Technical Support Phone 49 8165 906 200 Fax 49 8165 906 201 Email support msc technologies eu 81 81
61. oot Disabled Force Cold Reset Enabled Force cold reset or choose MRC cold reset mode Disabled when cold boot is required during MRC execution Note If ME 5 0MB is present Force cold reset is required DIMM Exit Mode Auto Slow Exit DIMM Exit Mode Control Fast Exit Power Down Mode No Power Down Power Down Mode Control Scrambler Seed Enabled Control Memory Scrambler Seed Generation Generation Off Disabled Enable do not generation scrambler seed Disable Generation scrambler seed always Memory Remap Enabled Enable or disable memory remap above 4G Disabled Memory Alias Check Enabled Enable or disable Memory Alias Check Disabled Channel A DIMM Enable Both Enable or disable DIMMs on channel A Control DIMMS Disable DIMMO Disable DIMM1 Disable both DIMM Channel B DIMM Enable Both Enable or disable DIMMs on channel B Control DIMMS Disable DIMMO Disable DIMM1 Disable both DIMM 70 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 11 6 Memory Thermal Configuration omm zeg Memory Thermal Enabled Enable or disable Memory Thermal Management Management Disabled PECI Injected Enabled Enable or disable memory temperatures to be Temperature Disabled injected to the processor via PECI EXTTS via TS on Enabled Enable or disable routing TS on Board s ALERT Board Disabled and THERM to EXTTS pins on the PCH EXTTS via TS on Enabled Enable or disable routing TS on DIMM s ALERT to
62. p to 25 ms for the SMBus to go idle If the SMBus is idle when the pin is detected active the reset occurs immediately otherwise the counter starts If at any point during the count the SMBus goes idle the reset occurs If however the counter expires and the SMBus is still active a reset is forced upon the system even though activity is still occurring Once the reset is asserted it remains asserted for 5 to 6 ms regardless of whether the SYS_RESET input remains asserted or not It cannot occur again until SYS_RESET has been detected inactive after the debounce logic and the system is back to a full SO state This behavior is a result of Intel ICH internal chipset logic which is different to the COM Express Module Base Specification stating that the system shall remain in reset as long as SYS_RESET input is low oO oO p TL DT quet toon pce teyboar or mouse aeiy L CB_RESET OS 3 3V eSR 22 0 Reset output from module to Carrier Board Active low Issued by module chipset and may result from a low SYS_RESET input a low PWR OK input a VCC 12V power input that falls below the minimum specification a watchdog timeout or may be initiated by the module software SUS STAT SUS_S3 SUS_S4 SUS_S5 WAKEO WAKE1 CMOS 3 3V Sus 3 3V ePU 220 KO Power OK from main power supply A high value indicates that the Power Good power is good logic CMOS 3 3V Sus 3 3V Indicates imminent suspend operation used
63. press connector lane 0 Chipset PCle lane 1 is connected to ComExpress lane 1 and so on Note PCle Lane 5 is used for PCIe2PCI Bridge PCle Lane 6 is used for onboard PATA Controller JMICRON and PCle lane 7 is used for internal Lan device 37 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 5 2 IRQ Lines in APIC Mode IRQ Available Typical Interrupt Source Connected to Pin 0 No Counter 0 1 No Keyboard 2 No Cascade Interrupt from Slave PIC 3 Yes 4 Yes 5 Yes 6 Yes 7 Yes 8 No RTC 9 Yes shared SCI 10 Yes 11 Yes 12 Yes 13 No Math processor 14 Yes 15 Yes 16 Yes INTA 17 Yes INT B 18 Yes INTC 19 Yes INTD 20 Yes INTE 21 Yes INT F 22 Yes INTG 23 Yes INT H 38 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 5 3 Carrier Board PCI Resource Allocation The external PCI resource allocation on the carrier board should be as follows Slot Device Slot Device 0 Slot Device 1 Slot Device 2 Slot Device 3 Signal IDSEL PCI AD 20 PCI AD 21 PCI AD 22 PCI AD 23 PCI Clock PCI CLK replica PCI CLK replica PCI CLK replica PCI CLK replica INTA PCI IRQ A PCI IRQ B PCI IRQ C PCI IRQ D INTB if used PCI IRQ B PCI IRQ C PCI IRQ D PCI IRQ A INTC if used PCI IRQ C amp PCI IRQ D PCI IRQ A Z PCI IRQ B Z INTD if used PCI IRQ D
64. rd drives to create a combination of RAID levels O and 1 by forming a RAID 0 array from two RAID 1 arrays To select the Raid mode desired enter setup and enable Raid in the Sata Submenu under Advanced Exit the setup with F4 System will restart and you will be prompt to enter CTRL I to open Raid GUI Here you can configure your connected Raid disks and select the raid mode On Windows systems it is recommended to install the Intel Rapid Storage Device drivers Note Using AHCI or Raid needs to install AHCI Raid drivers during setup of Windows XP by pressing F6when setup starts The drivers must be available on an USB FD Drive 2 Intel Rapid Start Using this technology wakes your system from a S4 sleep state nearly as fast as from S3 If your system is in SO and you enter S3 the system will wake up from S3 and saves all the memory to a special partition on a SSD and then the system will enter S4 After resuming from S4 all saved memory content will be written back from SSD to Ram The advantage with this simulated S3 is power saving 3 EIST Enhanced Intel Speed Step This allows the processor to meet the instantaneous performance needs of the operation being performed while minimizing power draw and heat dissipation Processor clock will be at it s minimum possible frequency when in IDLE When performing CPU loads it will change its frequency up to its maximum frequency Note If EIST is disabled in setup the CPU will run at its max
65. re System Temperature Informative Shows System Temperature Also supported in EAPI 44181 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 7 The Advanced Menu rmm omm EI Trusted Computing Trusted Computing TPM settings SATA Configuration AHCI SATA Configuration settings Thermal Configuration Thermal Configuration parameters Intel amp Rapid Start Submenu Intel amp Rapid Start Technology Technology Intel TXT LT Submenu Intel Trusted Ececution Technology Configuration PCH FW Configuration Submenu Configure Management Engine Technology parameters AMT Configuration Submenu Configure Active Management Technology parameters USB Configuration USB configuration parameters SMART Settings Sumeru ener setings WB627 SIO Configuration Submenu Submenu for Super IO Winbond W82627 HWM ADT7490 Submenu Configuration of the ADT7490 Configuration Hardware Monitor PIC Watchdog Configuration of the PIC Watchdog Serial Port Console Submenu Serial Port Console Redirection Redirection settings Intel ICC Integrated clock control options 45 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 7 1 PCI Subsystem Settings Submenu CCRN P Enables or disables 64bit capable 4G D Enabl D O ee devices to be decoded in above 4G address space only if system supports 64bit PCI decoding PCI Latency Timer 32 64 96 128 160 192 224 Set this value to change the PCI 248 PCI bus clocks bus clocks Default
66. re i7 2 processor SKUs Intel 82HM65 with Intel Core i3 2 and Intel Celeron processor SKUs Two 204 pin DDR3 SO DIMM sockets for up to 16GB 4GB with Intel Celeron 807UE non ECC unbuffered DDR3 One socket for up to 4GB on COM Express modules with Intel Celeron 807UE Max height 1250mil 31 75mm PC3 8500 10600 DDR3 SDRAM DDR3 1066 1333 PC3 12800 DDR3 SDRAM DDR3 1600 with Core i7 2715QE and Core i3 5 7 3 4 SATA channels up to 300MB s each 1 Enhanced IDE port ATA UDMA100 8 x USB 2 0 Type 2 interface fully compliant to COM Express Base Specification R2 0 Five channels PCle x1 32 Bit standard interface Low Pin Count Bus for heritage interfaces Serial Peripheral Interface for up to two SPI flash devices Intel HD Graphics 2000 3000 4000 depending on processor SKU Intel Dynamic Video Memory Technology Intel DVMT 5 0 Dual channel 24 bit LVDS 1 600 x 1 200 60 Hz DDPort B configurable as HDMI DVI 1920 x 1200 60 Hz DP 2560 x 1600 60 Hz and SDVO 200 MP s DDPort C configurable as HDMI DVI 1920 x 1200 60 Hz and DP 2560 x 1600 60 Hz DDPort D configurable as HDMI DVI 1920 x 1200 60 Hz DP 2560 x 1600 60 Hz and eDP PCle x16 graphics port PEG supports external graphics cards not available on Intel Celeron amp 807UE processor 340 4 MHz RAMDAC 2 048 x 1 536 75 Hz 10 100 1000Base TX Intel amp 82579LM Device ID 0x1502 with WOL support S3 S4 S5
67. reTechnicalResources html 5 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 11 Intel amp 6 Series Chipset and Intel C200 series Chipset Datasheet 6 chipset c200 chipset datasheet pdf Last update May 2011 http www intel com products notebook chipsets 6series technicaldocuments htm 12 Intel 6 Series Chipset and Intel C200 series Chipset Specification Update 6 and c200 chipset specification update pdf Last update August 2011 http www intel com products notebook chipsets 6series technicaldocuments htm 13 Intel 7Series C216 Chipset Family Platform Controller Hub PCH Datasheet 7 series chipset pch datasheet pdf Last update June 2012 http www intel com content www us en chipsets 7 series chipset pch datasheet html wapkw intel 7 series chipsets 14 Intel O 7Series C216 Chipset Family Platform Controller Hub PCH Family Specification Update 7 series chipset pch spec update pdf Last update August 2012 Revision 010 http www intel com content www us en chipsets 7 series chipset pch spec update htm l wapkwsintel 7 series chipsets 1 3 Introduction COM Express an open specification of the PICMG PCI Industrial Computer Manufacturer Group is a module concept to bring PCI Express and other latest technologies like SATA USB 2 0 and LVDS ona COM Computer On Module A COM Express module is plugged onto an application specific base board similar to the ETX concept but offers more options and a growth p
68. rrier Board Legacy buses such as PCI parallel ATA LPC HDA are supported as well as new high speed serial interconnects such as PCI Express Serial ATA and Gigabit Ethernet To enhance interoperability between COM Express modules and Carrier Boards seven common signaling configurations Pin out Types have been defined to ease system integration 6 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 Technical Description 2 1 Key features The MSC CXB 6S COM Express module is designed as a type 2 module according to COM Express Module Base Specification Revision 2 0 and is also drop in compatible with carrier boards designed according to COM Express Base Specification R1 0 Key features include Module size 125 mm x 95 mm Various 2 and 3 Generation Intel Core Processors Dual 220 pin connector 440 pins 2x DDR3 SO DIMM module up to 8 GB each one Eight USB 2 0 ports 4 shared over current lines Four Serial ATA ports with data rates up to 3 0Gb s 300MB s Optional SATA NAND Flash Silicon Disk 4 GB to 32 GB Five PCI Express x1 lanes Support pins for two ExpressCards Dual 24 bit LVDS channel Analog VGA High definition digital audio interface external CODEC Single Gbit Ethernet interface Intel 82579LM Device ID 0x1502 with Wake On Lan support S3 S4 S5 LPC interface Support for following Super IO Winbond 83627 Four GPI pins Four GPO pins 12V primary power suppl
69. s Lanes Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance PCIE TX 0 44 PCle 3 3V AC coupled PCI Express Differential Transmit Pairs O through 4 PCIE TX 0 4 on module PCH PCIE RX 0 4 PCle 3 3V AC coupled PCI Express Differential Receive Pairs 0 through 4 PCH PCIE RX 0 4 off module PCIE CLK REF PCle 3 3V Differential Reference Clock output for all PCI Express and PCI PCH PCIE CLK REF CLK Express Graphics lanes Note PCle lanes 5 is used on the CXB 6S module and therefore not available for externally by default 2 10 6 PCI Express x16Graphic Lanes Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance PEG TX 0 15 PEG TX 0 15 them are multiplexed with the digital display interface of the PCH SDVO DVI HDMI or DisplayPort AC coupled PCI Express Graphics receive differential pairs off module These signals can also be used as standard PCI Express receive lanes as PCIE RX 16 31 on type 5 and type 5 modules Some of these signals are multiplexed with the digital display interface of the PCH SDVO DVI HDMI or DisplayPort PCle 3 3V AC coupled PCI Express Graphics transmit differential pairs on module These signals can also be used as standard PCI Express transmit 8 lanes as PCIE TX 16 31 on type 4 and type 5 modules Some of PEG_RX 0 15 PCle PEG RX 0 15 CPU i PEG RX5 CMOS 3 3V 3 iPD 20 KQ DDPC C
70. s training attempt was unsuccessful Link Training Timeout 10us to 10000us Defines number of microseconds software will wait before polling Link Training bit in link status register Value range from 10 to 1000us Unpopulated Links Kepp Link ON Disable Link In order to save power software will disable unpopulated PCI Express links if this option set to disabled 47 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 7 2 ACPI Settings Enable Hib ti Enabled Disabled Enables or disables system ability to NOAA len anon Hibernate OS S4 Sleep State This option may not effective with some OS ACPI Sleep State Suspend Disabled S1 only Select the highest ACPI Sleep state CPU Stop Clock the system will enter when the S3 only Suspend to RAM Suspend button is pressed Both S1 and S3 available to choose from OS Lock Legacy Resources Enabled Disabled Enables or disables lock of Legacy parameters S3 Video Repost SE Disabled Enable or disable S3 Video Repost 6 1 7 3 Trusted Computing Feature Options Description Enabled Disabled TPM Support Enables or disables TPM support OS will not show TPM Note Reset of platform is required to see more TPM options For more information see also technotes in chapter 6 7 Enabled Disabled TPM state Turn TPM Enable Disable NOTE Your Computer will reboot during restart in order to change State of TPM None Enable take ownership Schedule an operation
71. se Trademarks All used product names logos or trademarks are property of their respective owners Certification MSC Technologies GmbH is certified according to DIN EN ISO 9001 2000 standards Life Cycle Management MSC products are developed and manufactured according to high quality standards Our life cycle management assures long term availability through permanent product maintenance Technically necessary changes and improvements are introduced if applicable A product change notification and end of life management process assures early information of our customers Product Support MSC engineers and technicians are committed to provide support to our customers whenever needed Before contacting Technical Support of MSC Technologies GmbH please consult the respective pages on our web site at www msc technologies eu for the latest documentation drivers and software downloads If the information provided there does not solve your problem please contact our Technical Support Email support msc technologies eu Phone 49 8165 906 200 2 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Content 1 General Information ssssssssssssssssssssseeeee eene nnn n anna r ran r ran rne rre nnne nnns 5 UE REVISION Klee 5 Zo Reference DOCUM EMSA ee EE 5 RS Ware ee TOT Scooters nem eme LA LE LM IM M Iu T LA NE E 6 2 SPechmicaliDesen puoi es tem eme acum c LUN UN m DU UNTEN mU 7 ANE A EE EE EE EE EE EE EE H EE Eeg
72. sed by Internal Graphics 1024 768 Device by selecting the appropriate setup item 1280x1024 1400x1050 1600x1200 Panel Scaling Auto Force Select the LCD panel scaling option used by the Scalling Off Internal Graphics Device Backlight Control PWM Inverted Backlight Control setting PWM Normal GMBus Inverted GMBus Normal LFP Backlight 0 100 Backlight Brightness setting Brightness Auto Disabled gt gt Auto GMCH Use VBT Default gt gt Level n Level 1 5 Enabled with Selected Aggressiveness Level Spread Spectrum clock Off Hardware gt gt Hardware Spread is controlled by chip Software gt gt Software Spread is controlled by BIOS TV1 Standard VBIOS default Select the ability to configure a TV Format NTSC x PAL x Secam x HDTV x TV2 Standard VBIOS default Select the ability to configure a TV Format NTSC x PAL x Secam x HDTV x 67 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee mm eme ALS Support Enabled Active LFP Disabled No LVDS Int LVDS SDVO LVDS eDP Port A eDP Port D Valid only for ACPI Legacy ALS Support through the IGD INT10 function ACPI ALS support through an ACPI ALS driver Select the Active LFP Configuration No LVDS VBIOS does not enable LVDS Int LVDS VBIOS enables LVDS driver by Integrated encoder SDVO LVDS VBIOS enables LVDS driver by SDVO encoder eDP Port A LFP Driven by Int DisplayPort encoder from Port A
73. sion Timer Enabled Enable or disable the High Precision Event Timer Disabled Restore AC Power Loss Power Off Select AC power state when power is re applied Power On Last after a power failure State Note This setting will only work if RTC battery is used Otherwise system will always power on after power failure 6 1 10 1 PCI Express Configuration Feature Options Description PCI Express Clock Gate Enabled Enable or disable PCI Express Clock Gating for Disabled each root port DMI Link ASPM Control Disabled Lo The control of Active State Power Management on LOsL1 both NB side and SB side of the DMI Link DMI Link Extended Syn Enabled The control of Extended Synch on SB side of the Disabled DMI Link Subtractive Decode Disabled Enable or disable PCI Express Subtractive Decode Enabled PCle USB Glitch W A Enabled PCle USB Glitch W A for bad USB devices Disabled connected behind PCle PEG Port PCI Express Root Port x Submenu Control the PCI Express Root Port 0 7 62 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 10 1 1 PCI Express Root Port x 0 7 Submenu rs Le lem PCI Express Root Port Enabled Control the PCI Express Root Port Disabled ASPM Support Disabled LOs Set the ASPM Level Force LO Force all links to LO L1 LOsL1 Auto State AUTO BIOS auto configure DISABLE Disables ASPM For more information see also technotes in chapter 6 7 URR Enabled Enable or disab
74. splayed in the menus in a flash The next time you boot your computer the BIOS configures your system according to the setup selections stored in flash If you attempt to exit without saving the program asks if you want to save before exiting During boot up the Aptio BIOS attempts to load the values saved in flash If those values cause the system boot to fail reboot and press lt ESC or DEL gt to enter Setup In Setup you can get the Default Values as described below or try to change the selections that caused the boot to fail Discard Changes and Exit Exit system setup without saving any changes Save Changes and Reset When you have completed the system configuration changes select this option to save the changes and reboot the system so the new system configuration parameters can take effect Discard Changes and Reset Select this option to quit Aptio TSE without making any modifications to the system configuration Save Changes Selecting Save Options saves all the selections without exiting Setup You can return to the other menus if you want to review and change your selections Discard Changes Discard changes done so far to any of the setup options Restore Defaults Restore load default values for all the setup options Restore User Defaults 73 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Restore the User defaults to all the setup options Save as User Defaults Save changes done so far as User de
75. t B Lane PEG TXO D53 SDVOB RED Differential Pair TMDSB DATA2 Pair DPB LANEO differential Pair SDVO CTRLCK D73 SDVO CTRLCLK SDVO Control Clock FC TMDSB CTRLCLK HDMI Port B Control Clock IC PEG TX1 D55 SDVOB_GRN SDVO Port B Green TMDSB DATA1 HDMI Port B Data 1 DifferentialDPB_LANE1 DisplayPort B Lane PEG TX1 D56 SDVOB GRN Differential Pair TMDSB DATA1 Pair DPB LANE1 differential Pair PEG_TX2 D58 SDVOB_BLU SDVO Pot B Blue TMDSB DATAO HDMI Port B Data 0 Differential DPB_LANE2 DisplayPort B Lane2 PEG TX2 D59 SDVOB BLU Differential Pair TMDSB DATAO Pair DPB LANE2 differential Pair 33 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual COM Express Connector COM Express pin D97 PEG_ENABLE 1 Name Pin PEG_TX3 D61 SDVOB_CK SDVO Port B Clock TMDSB_CK HDMI Port B Clock DifferentialDPB_LANE3 DisplayPort B Lane3 PEG TX3 D62 SDVOB CK Differential Pair TMDSB CK Pair DPB LANE3 differential Pair PEG TX4 D65 TMDSC_DATA2 HDMI Port C Data 2 Differential DPC_LANE0 DisplayPort C Lane PEG TX4 D66 TMDSC DATA2 Pair DPC LANEO differential Pair PEG TX5 D68 TMDSC_DATA1 HDMI Port C Data 1 DifferentialDPC_LANE1 DisplayPort C Lane PEG TX5 D69 TMDSC DATA1 Pair DPC LANE1 differential Pair PEG TX6 D71 TMDSC_DATA0 HDMI Port C Data 0 Differential DPC_LANE2 DisplayPort C Lane2 PEG TX6 D72 TMDSC DATAO Pair DPC LANE2 differential Pair PEG TX7 D74 TMDSC
76. terials like phase change foils gap pads and copper or aluminium blocks A very good thermal conductivity is required in order to conduct the heat from the CPU and the chipset to the heat spreader plate The heat spreader of the MSC module is thermally attached using phase change materials and small aluminium blocks filling the gap between cpu and chipset dies and the heat spreader plate The heat spreader is not a heat sink It is a defined thermal interface for the system designer with fixed mechanical dimensions so it should be possible to change different module types without problems There must be a cooling solution for the system The surface temperature of the heat spreader should not exceed 80 C Main issue for the thermal functionality of a system is that each device of the module is operated within its specified thermal values The max value for the CPU is 100 C and 108 C for the chipset So there may be system implementations where the heat spreader temperature could be higher Anyway in this case it has to be validated that there are no thermal specification violations of any assembled part or integrated circuit over the system temperature range even at worst case conditions Additionally MSC offers adequate heat sink solutions for the different CXB 6S modules depending on the power dissipation of the implemented CPU For more information please refer to support 2msc technologies eu or conta
77. to notify LPC devices CMOS 3 3V Sus 3 3V Indicates system is in Suspend to RAM state Active low output CMOS 3 3V Sus 3 3V Indicates system is in Suspend to Disk state Active low output CMOS 3 3V Sus 3 3V Indicates system is in Soft Off state Also known as PS ON and can be used to control an ATX power supply CMOS 3 3V Sus ePU 1 2 KO PCI Express wake up signal CMOS 3 3V Sus 3 3v ePU 10KOQ General purpose wake up signal May be used to implement wake PCH up on PS2 keyboard or mouse activity GPIO13 26 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail Tolerance BATLOW CMOS 3 3V Sus ePU 8 2 KQ Indicates that external battery is low CMOS 3 3V 3 3V ePU 10 KQ_ Input from off module temperature sensor indicating an over temp PCH situation GPIOO THERMTRIP CMOS 3 3V 3 3V ePU 3300 Active low output indicating that the CPU has entered thermal CPU shutdown PCH OD through 5V standby rail and main power rails OD through 5V standby rail and main power rails SMB_ALERT CMOS 3 3V Sus 3 3V ePU 10KQ_ System Management Bus Alert active low input can be used to PCH generate an SMI System Management Interrupt or to wake the system Power sourced through 5V standby rail and main power rails 2 10 16 General Purpose UO Pin Signal Power Remark PU PD SR Description Source Target
78. top side of the CPU module directly beneath the CPU The following connector type is used e JST SAB PH SM4 TB The fan itself should be equipped with a JST PHR 4 connector and one of the following contact types e SPH 002T P0 5S AWG 30 24 SPH 002T P0 5L AWG 28 24 or SPH 004T P0 5S AWG 32 28 The pinning is as following Pin Signal Description 1 GND GND 2 V12FAN 12V fan supply voltage 3 TACHO Input for the tacho signal of the fan O C 4 PWM Output of the PWM Signal for fan speed control The fan control circuit was designed and tested with 9PH0812P7S06 12V 0 26A The use of a 6 Watt fan is allowed 4 Watchdog The CXB 6S board has a watchdog function implemented in a PIC Microcontroller The watchdog can be enabled and configured in the BIOS Setup If the watchdog is enabled a counter is started which generates a reset if it is not retriggered within a programmable time window Possible watchdog delays 1s 5s 10s 30s 1min 5min 10min 30min Possible watchdog timeout 0 4s 1s 5s 10s 30s 1min 5min 10min The time delay starts as soon as it is enabled in the BIOS MSC provides a software API which gives the application software access to the Watchdog functionality if needed 36 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 5 System resources 5 1 PCI IRQ Routing Interrupts of Controller PCH
79. ules this pin will connect to other VCC_12V pins In R2 0 this pin is defined as a no connect for types 1 6 A Carrier can detect a R1 0 Module by the presence of 12V on this pin R2 0 Module types 1 6 will no connect this pin Type 10 Modules shall pull this pin to ground through a 4 7K resistor 29 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 10 19 Power and GND Pin Signal Power Remark PU PD SR Description Source Target Type Level Rail 13 peces 12V BM Ee 15 Primary power input 12V 15 Voltage Regulators ord DV SBY a Se 5 Standby power input 5 0V 5 VCC3 3V SUS If VCC5_SBY is used all available VCC_5V_SBY pins on the regulator connector s shall be used Only used for standby and suspend functions May be left unconnected if these functions are not used in the system design VCC_RTC IPowr 1 Real time clock circuit power input 3 0V 2 0V to 3 3V GND Power Ground DC power and signal and AC signal return path All available GND connector pins shall be used and tied to Carrier Board GND plane 30 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 11 Pin List for MSC CXB 6S module Type 2 RowwA RowwB o JRowC Row A GBEO MD2 Be X LPC AD2 Tee IDE D8 DG IDE D4 A8 GBEO LINK B8__ LPC DRQOf C8 IDE D2 D8 IDE REQ A9 GBEO MD B9 X LPC ppo cg JIDE D13 D9 IDE ONS A29 AC HDA SYNC B29
80. use the arrow keys to move the cursor to the sub menu you want Then press Enter A pointer marks all submenus 6 1 6 The Main Menu You can make the following selections on the Main Menu itself Use the sub menus for other selections O ee e o e Access Level Informative This feature shows what kind of user has entered the Aptio setup It depends on the Security Tab if a Administrator and or User password is set System Language English Select the system default language System Date Enter Date MM DD YYYY Set the system date on the real time clock System Time Enter Time HH MM SS Set the system time on the real time clock MSC Board Info Shows board specific information PCH Information Informative Shows information of the Platform Controller Hub ME FW Version Shows the ME firmware version ME Firmware SKU Shows the ME firmware SKU SPI Clock Frequency Shows the SPI clock frequencies Processor Information Informative Shows several information of the processor the VBIOS and Memory 43 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 6 1 6 1 MSC Board Info O ee oe f e E Serial Number Shows the boards serial number Boot Counter Shows the amount of boots Onboard Lan MAC Informative Shows the onboard Lan MAC adresse adresse 6 1 6 2 Hardware Monitoring Measurement O ee e o e CPU Temperature Informative Shows CPU Temperature Also supported in EAPI Memory Temperature Shows Memory Temperatu
81. valent load PCH pe Pp DL o p renee A Ohm equivalent load wee gewesen pec UTE equivalent load 21 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual A eur uuu umm em LL Type Level Rail Tolerance VGA HSYNC fo CMOS 33V Horizontal sync output to VGAmonitor JPCH vea VSYNC O CMOS 33V Vertical sync output to VGA monitor POH VGA I2C CK ER CMOS RENE ePU 2 2 KO DDC clock line IC port dedicated to identify VGA monitor capabilities VGA DC DAT l OD CMOS ePU 2 2 KQ DDC data line I C port dedicated to identify VGA monitor capabilities 2 10 13 Digital Display Interfaces The Intel Platform Controller Hub PCH provides three Digital Display Ports B C and D that may be configured for SDVO HDMI DVI or DisplayPort functionality These ports may be switched to the COM Express Connector C D by a HIGH level on input signal PEG_ENABLE D97 instead of the CPUs PCI Express Graphic lanes The pin out is chosen in a way that the digital display ports are accessible through special ADD2 Cards that can be plugged into the PEG slot on existing COM Express type 2 carrier boards Be aware that the digital display interface does not support reverse order functionality if PEG LANE RVZ strap is low 2 10 13 1 SVDO Digital Display Port B only Pepe tel Rab Tolerance en et Type Level Rail Tolerance SDVOB_RED on module Multiplexed with PEG_TX 0 and PEG_TX 0 SDVOB_GRN on module
82. velow__________________ PCH 2 10 8 PCI Bus A oS osa e Type Level Rail Tolerance PCI_AD O 31 Do CMOS 33V 5v_ PCI bus multiplexed address and datalines XIO2001 PCI_C BE O 3 Io CMOS 3 3v__ 5v_ PCI bus byte enable lines activelow XIO2001 PCI PAR O CMOS 33V 5V PCibusparity XIO200 O data that has a parity error PCI_REQ 0 3 CMOS 3 3V_ 5V___ ePU 8 2 KQ PCI bus master request input lines activelow XIO2001 PCI_GNT 0 3 O CMOS 33V PC bus master grant output lines active low n XIO2001 PCI RESET O CMOS 33V POI Reset output activelow_______________________ XIO20014 OD detects a system error condition PCI PME Z CMOS 3 3V Sus 5V ePU 8 2 KO PCI Power Management Event PCI peripherals drive PME to wake XIO2001 POSE IT ITT TTT lom poner states S18 o ore MER To wake AORO systems PCI_IRQ A D CMOS ePU 8 2 KO PCI interrupt request lines XIO2001 PCI CLK CMOS 3 3V eSR 820 PCI clock output XIO2001 33 MHz if PCI Me6EN low 66 MHz if PCI M66EN high or open 19 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual ESA e Signal Power Remark PU PD SR Description Source Target A ae Level Rail Tolerance PCI M66EN CMOS 3 3V 5V ePU 10 KO Module input signal indicates whether an off module PCI device is XIO2001 capable of 66MHz operati
83. ween XHCI and Switchable Disabled EHCI If disabled port is routed to EHCI If HS port is routed to xHCI the corresponding SS port is enabled XHCI Streams Enabled Enable or disable x HC Maximum Primary Stream Disabled Array EHCI 1 Ports 0 5 Enabled Control the USB EHCI USB 2 0 functions SES One EHCI controller must always be enabled EHCI 2 Ports 6 7 Enabled Control the USB EHCI USB 2 0 functions EES One EHCI controller must always be enabled USB Port x Disable Enabled Disable USB port Disabled 6 1 10 3 PCH Azalia Configuration HD Audio me Lei e Azalia Auto Enabled Control Detection of the Azalia device SSES Disabled Azalia will be unconditionally disabled Enabled Azalia will be unconditionally Enabled Auto Azalia will be enabled if present disabled otherwise Azalia Docking Supp Enabled Enable or disable Azalia Docking Support of Audio Disabled Controller Azalia PME Enabled Enable or disable Power Management capability of Disabled Audio Controller Azalia Internal HDMI Enabled Enable or disable internal HDMI codec for Azalia Disabled Azalia HDMI codec Port Enabled Enable or disable internal HDMI codec Port for B Disabled Azalia Azalia HDMI codec Port Enabled Enable or disable internal HDMI codec Port for C Disabled Azalia 64 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual mee mm en Azalia HDMI codec Port Enabled Enable or disable internal HDMI codec Port
84. will be launched Boot option filter UEFI and This option controls what devices system can boot Legacy Legacy to only UEFI only Launch PXE OPROM Do not launch Controls the execution of UEFI and Legacy PXE policies UEFI only OPROM Legacy only Launch Storage Do not launch Controls the execution of UEFI and Legacy Storage OPROM UEFI only OPROM Legacy only Onboard PATA Disabled Enable or disable boot option for onboard PATA Controller OPROM Enabled controller Note This option is only available on CXB 6S Launch Video OPROM Do not launch Controls the execution of UEFI and Legacy Video UEFI only OPROM Legacy only Legacy first UEFI first Other PCI device ROM UEFI Oprom For PCI devices other than Network Mass storage Legacy Oprom or Video defines which Oprom to launch Boot Option 1 Device x Set the system boot order Note The number of available Boot options is dependent on the devices which are connected 6 1 13 Security e f me OO e Administrator Password Set Password Set Setup Administrator Password Set Password Set User Password 72 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual HDDSecurity Set Password Set HDD Password Configuration 6 1 14 The Save amp Exit Menu The following sections describe each of the options on this menu Save Changes and Exit After making your selections in the setup menus always select Exit Saving Changes This procedures stores the selections di
85. www intel com technology virtualization 78 81 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 10 VT d supports the remapping of I O DMA transfers and device generated interrupts The architecture of VT d provides the flexibility to support multiple usage models that may run un modified special purpose or virtualization aware guest OSs The VT d hardware capabilities for I O virtualization complement the existing Intel VT capability to virtualize processor and memory resources Together this roadmap of VT technologies offers a complete solution to provide full hardware support for the virtualization of Intel platforms Fast Boot Fast Boot supported by Aptio provides faster boot time by learning the system configuration on the first boot On the Next boot system boots faster because the bios will only use the best boot path from the first OS boot It configures only devices needed for the OS to boot It adapts when system changes Trusted Platform Module TPM A TPM is a cryptoprocessor that can store cryptographic keys that protect information The Trusted Platform Module offers facilities for the secure generation of cryptographic keys and limitation of their use in addition to a hardware pseudo random number generator It also includes capabilities such as remote attestation and sealed storage e Remote attestation creates a nearly unforgeable hash key summary of the hardware and software configuration The program encrypting
86. y input 45V standby optional and 3 3V RTC power supply inputs 32 bit PCI interface IDE port to support legacy ATA devices such as CD ROM drives and Compact Flash storage cards 21 PCI Express lanes 5 on A B and 16 on C D 16 of 21 PCI Express lanes used for PCI Express Graphics Up to three digital display interfaces configurable as SDVO HDMI DVI or DisplayPort pins shared with PCI Express Graphics TPM module option TPM 1 2 SLB9635 Automatic fan control Watchdog timer Embedded Application Programming Interface EAPI 7181 MSC CXB 6S CXB 6SI Rev 1 8 User Manual 2 2 Block diagram VCCRTC bit 1600MT s 64bit 1600MT s 5VSBY A 12V ny i y CPU Debug poo PCH Debug TYPE 2 0 12V HW Monitor PCle x16 PCle MUX GBEO MDI 82579 PCle x1 SDVO HDMI DVI DP SEL ASB GbE PCle 7 DDP_B PHY HDMI DVI DP PEG_ENABLE A PWR Ctrl SLP States Thermals Misc DDP_C 1 HDMI DVI DP eDP A 8x USB 2 0 DDP_D USB 0 5 7 9 l 2Ch 24Bit LVDS LVDS_A B PCH Debu 1 des 7 gt HD Audio HDA 4x GPI 4x GPO RS 2x SATA 6G JMB368 SATA 0 1 PCle 6 PCIe2PATA 1 2x SATA 3G Master Slave SATA 2 3 D GPIOs TI X102001 SATA 4 PCle2PCI PCH em PCle 0 4 32 bit PCI Bus Si 1x SATA 3G gt optionally GPIOs Type2 COM Express R2 0 Module MSC CXB 6S 6SI Rev 09 8 81 MSC CXB 6S CXB 6SI Rev

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