CoreLV™ User`s Manual - prpl Foundation wiki
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1. TRSTN EJTRSTN MIPS 3 EJTDI TDI E TDO JTGCPU EJTDO S CTDO GTTDO 2 1Mux GT TDI 4 64120 TDO TCK inhibit JTGCPU Figure 4 JTAG Connectivity in Revision 09 and Earlier TRSTN EJTRSTN MIPS 3 EJTDI TDI EY TDO EJTDO Figure 5 JTAG Connectivity in Revision 10 and Later 3 7 Revision Register The CoreLV card has a hard wired board and revision code which can be read from the REVISION register on the motherboard The CORID field 6 bits is always 0x01 for CoreLV boards The CORRV field 2 bits is given in the following table Table 4 CORRV Revision Field CoreLV revision CORRY 2 bits 02 09 020 CoreLV User s Manual Revision 02 08 10 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 3 Description Table 4 CORRV Revision Field CoreLV revision CORRY 2 bits 10 Ox1 CoreL V User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 11 4 Testpoints 4 Testpoints The following testpoints are fitted Table 5 Testpoints Reference Silk screen Function TP1 8 D3V3 3 3V TP2 D5V 5 TP3 4 5 GND GND CLK In revision 09 and earlier The board main clock to all devices CPU TP6 GT64120 SDRAM EPLD etc SYSC In revision 10 and later As above except2. AD 31 0 ALE CSN 3 0 BootCS CSTiming RDWRN READYN DevRWN DADR 2 0 AD 31 0 ALE CSN 3 0 BootCS CSTiming RDWRN READYN DevRWN 3 5 Interrupts AD 4 2 gt BUFFER pe CD 31 0 gt lt AD 25 5 LATCH ml lt EPLD e CWRN CRDN CCSN Figure 2 Revision 09 and Earlier Device Bus to CBUS Conversion BUFFER TRANSCEIVER AD 4 2 CD 31 0 LATCH AD 25 5 Y vvvv v Y EPLD CWRN CR ces Figure 3 Revision 10 and Later Device Bus to CBUS Conversion The InterruptN signal from GT64120 is connected to the global motherboard interrupt controller through CINTHIN on the J3 connector The PCI interrupt from GT64120 PCI_INTN is not used CINTLON is driven inactive From the motherboard the 6 interrupt signals IINTN 5 0 and the NMI signal INMIN are taken directly to the LV CPU 3 6 JTAG Chain A JTAG chain is implemented on the Core card In revision 09 and earlier the chain can be configured to contain the CPU only or the CPU and the GT64120 This is illustrated in the figure below CoreLV User s Manual Revision 02 08 Copyright O 1999 2001 MIPS Technologies Inc All rights reserved 3 Description Note that in revision 10 and later the JTAG chain contains the CPU only
3. In revision 10 and later R175 1 In revision 09 and earlier IO 3 3V IO JP4 1 2 amp 3 4 3V3 amp IO In revision 10 and later R176 1 To measure the current to the LV s Core amp IO supplies in revision 09 and earlier of the MIPS CoreLV card remove the Current Jumpers and connect an ammeter between the two Current Measurement Testpoints all as specified in Table 1 Do not power the board up without the ammeter in circuit In revision 10 and later the two currents are determined by measuring the voltage across the two 0 1 Ohm resistors R175 and R176 as shown in the table above use the testpoints in the table A direct current measurement as described for revision 09 and earlier is also possible if the two resistors are removed Do not power the board up without the ammeter or the two resistors in circuit 3 2 System Controller GT64120 The system controller is a Galileo GT64120 In revision 09 and earlier of the MIPS CoreLV card it is a GT64120 that is used see Ref 2 and in revision 10 and later it is a GT64120A see Ref 3 This system controller is designed to interface R4000 R5000 and R7000 MIPS CPUs The main functions in this device include Host to PCI bridge functionality SDRAM controller and Host to SDRAM interface Device bus interface The device bus from the GT64120 is modified in the EPLD on the Core card to provide the CBUS which is used for access to Boot Flash
4. signals Bypass PLL Enabled Controlled by pulldown only in revision 10 and later 3 2 1 Programming Notes The GT64120 initially powers in a SYSAD bus mode where it cannot accept so called DDD back to back transfers As the LV will start using these types of transfer as soon as it starts to run cached it is essential that the 64120 be configured to accept these as soon as possible during the initialisation process before the caches are enabled This is done by setting bit 16 CPU WriteRate in register 0x000 CPU Interface Configuration to 1 The GT64120 also should be set to use the BOOTCSN chip select for its entire device bus region This is done by the following sequence Write 0x0000 0000 to register Ox43c CS 3 High Decode Address Write 0x0000 00f0 to register 0x440 BootCS Low Decode Address Write 0x0000 00ff to register 0x444 BootCS High Decode Address The addresses for the above register writes are OXBBEO 0000 register number gt CoreL V User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 3 Description Note also that due to a bug in the GT64120 in big endian mode all register contents are effectively byte swapped which should be taken into account in performing the above setups 3 3 SDRAM The SDRAM controller can be configured so that PC100 SDRAM DIMM up to 8 maximum 01 256 Mbyte will function Note versions of YAMON ea
5. COREO 10 TOP VIEW U6 J10 Keys LO co 5 U7 U5 7064 GT64120 El r co O J4 O J3 J4 Samtec MOLC 150 31 x Q 200 pin 50 x 4 1 27mm pitch connectors on underside Figure 6 CoreLV Revision 09 and Earlier Layout CoreLV Users Manual Revision 02 08 23 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 10 PCB Layout Offset from the other O Q three holes JP3 i 12V PC100 DIMM A J7 debug P dl eal UU Ke Y DXV 3V3 O O GND ew OND CORE 0 O 6 S 9 gt 5 5 MIPS LV 5 DO D12 TOP VIEW SYSC CPUC GCLKB O 0 he GND at lt 5 GT64120 U7 s 7064 E 2V5 3V3 5V O E O J4 e O J3 J4 Samtec MOLC 150 31 x Q 200 pin 50 x 4 1 27mm pitch connectors on underside Figure 7 CoreLV Revision 10 and Later Layout CoreLV User s Manual Revision 02 08 Copyright O 1999 2001 MIPS Technologies Inc All rights reserved Keys 24 10 PCB Layout Appendices CoreLV Users Manual Revision 02 08 25 Copyright 1999 2001 MIPS Technologies Inc All rights reserved A References A References 1 MIPS 4K 5KTM Lead Vehicle datasheet MD00001 Galileo GT64120 datasheet Version 1 4 Sept 14 1999 3 Galileo GT6412
6. the CPU TP7 D12V 12V TP9 CORE M ne E Ee SE with TP11 for current measurement see Section TP10 IO LV IO voltage use together with TP8 for current measurement see Section 3 1 1 CPU Power Supply TP11 DXV LV core power supply voltage use together with TP9 for current measurement see Section 3 1 1 CPU Power Supply TP12 CPUC The CPU clock only in revision 10 and later TP13 GCLKB GCLKB output from MIPS LV only in revision 10 and later TP14 D2V5 Core supply to Galileo GT64120A only in revision 10 and later CoreLV User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 12 5 Connectors 5 Connectors The following connectors are present on the board Table 6 Connectors Label Type Function J1 SMA External clock source 50 ohm terminated The functionality of this is not defined at the time of writing See the pin documentation for ERES 11 0 in the Lead Vehicle specification see Ref 1 p 0 1 In revision 09 and earlier it is a 16 pin header with ERES 11 0 header PM DTLBMISS ERESP 12 PM DTLBHIT ERESP 13 and EJ DEBUGM ERESP 14 In revision 10 and later it is a 12 pin header with ERES 11 0 J3 200 way Motherboard connector J3 as defined in Ref 4 J4 200 way Motherboard connector J4 as defined in Ref 4 Connector for standard 12V PC fan 5 e In revision 09 and earlier the pinout is Pin 1 12V pin 2 NC pin
7. the CPU clock run at least 1 MHz faster than the PCI clock This limits the lowest frequency useable to 34 MHz unless it is possible to slow the PCI clock This can be done on some MIPS motherboards Note that both 14 pin and 8 pin oscillator modules can be fitted on the card in place of U6 A dashed line shows the positioning of the 8 pin module 9 1 CPU Clocking The input clock for the CPU GCLKP is derived either from the onboard oscillator or from an external source connected to the SMA connector J1 This clock directly gives the SYSAD bus frequency For MIPS64 5K CPUs and later versions of MIPS32 4K CPUs the internal core clock frequency is controlled by the LV s GMULTP 1 0 signals which are set by a board default and the two links 1 2 3 4 on JP7 For MIPS32 4K CPUs of RTL version 3 2 and earlier the multiplication factor is fixed at 2 As this is a complex system depending on precisely which CPU is fitted please refer to the appropriate documentation if altering any of these link settings Specific Core card configurations are provided in Table 12 These cards are or will soon be available from MIPS Technologies or an authorized manufacturer Table 12 Clock Frequencies Crystal Clock Core clock PCB frequency multiplier frequency CPU Rev Manufacturer code MHz factor MHz MIPS32 4K 01 04 4Kc TI F731940 40 2 fixed value 80 CoreLV Users Manual Revision 02 08 21 Copy
8. 09 and earlier there is a 4 way pianokey DIP switch S1 on the board This is for MIPS internal use only and if fitted should have all switches on the OFF position In revision 10 and later there is no switch on the board CoreLV User s Manual Revision 02 08 20 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 9 Clock Circuitry 9 Clock Circuitry Clocking of both MIPS LV and GT64120 is controlled from a single source In revision 09 and earlier this source may be up to 5OMHz the limitation being in the card s layout rather than in any particular device In revision 10 and later the clock may be up to 100MHz In revision 09 and earlier jumper J1 selects between an external clock source attached to connector J8 which is an SMA connector terminated with 50 ohms and the on board clock oscillator U6 In revision 10 and later the jumper enables the external frequency generator and the on board oscillator has to be removed from the socket U6 if the jumper is fitted The selected source drives via a buffer circuit the following MIPS LV CPU System controller SDRAM DIMM EPLD Debug connectors 16 J7 18 and JO Note that 19 18 not implemented in revision 10 and later Note that the PCI clock 18 totally independent of this system It is sourced from the 14 connector and only connected to the PCI clock input on GT64120 However note that the Galileo system controller has a timing requirement that
9. 0A datasheet Version 1 0 Feb 29 2000 4 Malta User s Manual MD00048 2 wo CoreLV Users Manual Revision 02 08 26 Copyright 1999 2001 MIPS Technologies Inc All rights reserved B Revision History B Revision History Revision Date Description 01 00 99 12 15 Initial release Added details of CAWBLK jumper 01 01 2000 01 13 Added specification of SDRAM CAS latency and burst length Added details of TI 4Kc LV 02 00 2000 02 07 PCB Rev 04 details added 02 01 2000 03 10 Added REVISION register field info Minor trademark cleanup 02 02 2000 03 24 Clocking table updated Copyright updated Removed CSM J25C1 from document 02 03 2000 05 30 Updated copyright notice PCB rev 04 changed to revision 10 02 04 2000 07 07 General cleanup with regard to revision 10 functionality Added details of 5Kc LSS version 02 05 2000 11 17 Added notice about compatible PCI Clock frequencies 02 06 2001 01 23 Document Lauout updated Added information on TI 5Kc and TSMC 4Kc to clocking table 02 07 2001 08 03 Added references to Malta removed references to Atlas and Harp 02 08 2002 07 18 Added 256 Mbyte DIMM information CoreLV Users Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 27
10. 18 SYSADIO 20 SYSADO 22 SYSAD8 24 SYSAD7 26 SYSAD6 28 SYSAD5 30 SYSAD4 32 SYSAD3 34 SYSAD2 36 SYSAD1 38 SYSADO CoreLV User s Manual Revision 02 08 14 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 5 Connectors 5 1 3 J8 ODD label BUS CTRL1 Pin Signal Pin Signal Pin Signal Pin Signal 1 NC 3 GND 5 SYSCLK T SYSCMD8 9 SYSCMD7 11 SYSCMD6 13 SYSCMD5 15 SYSCMD4 17 SYSCMD3 19 SYSCMD2 21 SYSCMDI 23 SYSCMDO 25 RELEASEN 27 RDRDYN 29 WRRDYN 31 VALIDINN 33 VALIDOUTN 35 EXTRQSTN 37 SYSCMDP J8 EVEN label BUS CTRL2 Pin Signal Pin Signal Pin Signal Pin Signal 2 NC 4 NC 6 SYSCLK 8 SYSADC7 10 SYSADC6 12 SYSADCS 14 SYSADC4 16 SYSADC3 18 SYSADC2 20 SYSADCI 22 SYSADCO 24 RSTN 26 DEBUG6 28 DEBUGS 30 DEBUG4 32 DEBUG3 34 DEBUG2 36 DEBUGI 38 DEBUGO Note 1 indicates that in revision 10 and later this signal is No connect and in revision 09 and earlier it is as stated 5 1 4 J9 ODD label CPU1 Pin Signal Pin Signal Pin Signal Pin Signal 1 NC 3 GND 5 SYSCLK 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 J9 EVEN label CPU2 Pin Signal Pin Signal Pin Signal Pin Signal 2 NC 4 NC 6 SYSCLK 8 10 12 Reserved 14 dtlb_miss 16 dtlb_hit 18 instncomplete 20 wtbnomerge 22 wtbmerge 24 jtlb_miss 26 jtlb_hit 28 itlb_miss 30 itlb_hit 32 icache_miss 34 icache_hit 36 dcache miss 38 dc
11. 3 GND In revision 10 and later it is a header with lock pin 1 GND pin 2 12V pin 3 NC J6 8 HP LA SYSAD debug connectors See below for signal allocation Debug connector for CPU performance meassurement signals J9 HP LA This connector is not implemented in revision 10 and later J10 JTAG programming connector for EPLD 5 1 Logic Analyzer Connectors The card contains 3 HP Logic Analyzer connectors for debugging of the SysAD bus In revision 09 and earlier there is however an extra HP Logic Analyzer connector for monitoring of the PM signals Table 7 Debug Connectors Signal Function TCLK SysAD bus Clock Up to 50 MHz in revision 09 and earlier and 100MHz in revision 10 and later SYSADI 63 0 System Address Data bus SYSCMD 8 0 System command Data identifier bus SYSCMDP System command Data identifier bus parity SYSADC 7 0 System Address Data parity check RELEASEN Signals that the CPU is releasing the system interface to slave state RDRDYN External agent can accept a processor read WRRDYN External agent can accept a processor write VALIDINN External agent drives valid address or data on SysAD and SysCmd busses CoreLV User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 13 5 Connectors Table 7 Debug Connectors Signal Function VALIDOUTN The CPU is driving vali
12. BUS also used on the motherboard enabling the design to run at 100MHZ The JTAG chain contains the CPU only CoreLV Users Manual Revision 02 08 4 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 2 Installation 2 Installation Before use the supplied or other suitable SDRAM DIMM should be mounted in the socket provided The keying slots should be aligned as shown in Figure 6 and Figure 7 Since the modules must be capable of 2 cycle CAS latency and a burst length of 8 at 100MHz PC100 2 2 2 modules must be used The CoreLV card is placed on the motherboard and an asymmetrically placed mounting pillar on the motherboard prevents reverse insertion CoreLV User s Manual Revision 02 08 5 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 3 Description 3 Description The following features are present on the MIPS CoreLVTM card 3 1 CPU The CPU is a MIPS core Lead Vehicle according to Ref 1 It interfaces to the System controller via its 64 bit SYSAD bus 3 1 1 CPU Power Supply The CPU power supply is split between the core and the IO sections of the LV chip There is also a separately decoupled supply for the internal PLL Table 1 Power Supplies Voltage Current measurement Supply Voltage test point Current jumper resistors testpoints In revision 09 and earlier 1 25 to 2 5V set by Core R134 amp R135 CORE JP4 7 8 amp 9 10 DXV amp CORE
13. Flash memory and peripheral devices as DUART LED s switches etc placed on the motherboard The reset configuration for the GT64120 is sampled on a number of shared pins while reset is asserted The EPLD U7 drives some of these values others are controlled by pullup down resistors CoreLV User s Manual Revision 02 08 6 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 3 Description Table 2 GT64120 Boot Time Configuration Parameter Value Function PCI bus config Only PCI 0 enabled 32 bit PCI enabled Endianness Automatic Controlled by endian signal from the motherboard GT address ID 2 bll Default for boot device Controlled by pullup PCI code class select 1 host bridge Controlled by pullup Multiple GT64120 No Controlled by pulldown support 66 MHz PCI Disabled Controlled by pulldown DO support Disabled Controlled by pullup UMA support Disabled Controlled by pullup retry Disabled This is controlled from the EPLD Expansion ROM enable Disabled This is controlled from the EPLD Device Boot bus width 32 bit This is controlled from the EPLD Autoload Disabled This is controlled from the EPLD ee Disabled Controlled by pulldown only in revision 10 and later Disabled Controlled by pulldown only in revision 10 and later Duplicate ALE Disabled This is controlled from the EPLD Dapur DE Disabled This is controlled from the EPLD
14. MISS TECHNOLOGIES CoreLV User s Manual Document Number MD00007 Revision 02 08 July 18 2002 MIPS Technologies Inc 955 East Arques Avenue Sunnyvale CA 94085 4521 Copyright 1999 2001 MIPS Technologies Inc All rights reserved Copyright 1999 2001 MIPS Technologies Inc All rights reserved Unpublished rights if any reserved under the copyright laws of the United States of America and other countries This document contains information that is proprietary to MIPS Technologies Inc MIPS Technologies Any copying reproducing modifying or use of this information in whole or in part that is not expressly permitted in writing by MIPS Technologies or an authorized third party is strictly prohibited At a minimum this information is protected under unfair competition and copyright laws Violations thereof may result in criminal penalties and fines Any document provided in source format i e in a modifiable form such as in FrameMaker or Microsoft Word format is subject to use and distribution restrictions that are independent of and supplemental to any and all confidentiality restrictions UNDER NO CIRCUMSTANCES MAY A DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF MIPS TECHNOLOGIES INC MIPS Technologies reserves the right to change the information contained in this document to improve function design or otherwise MIPS Technologies does
15. ache hit J9 is only present in Revision 09 and earlier For debugging of the signals to the SDRAM module it is recommended to use a purpose build logic analyzer adapter card for example the Future Plus FS2320 168 pin SDRAM DIMM Analysis Probe and Extender Card CoreLV User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 15 6 LEDs 6 LEDs The following LEDs are fitted to the board Table 8 LEDs in Revision 09 and Earlier LED Color subLED Function Marking 8 LEDs connected to PM signals 0 left PM_DCacheHit DH 1 PM_DCacheMiss DM 2 PM_ICacheHit IH D2 Red 3 PM_ICacheMiss IM 4 PM_ITLBHit TH 5 PM_ITLBMiss TM 6 PM_JTLBHit JH 7 PM_JTLBMiss JM 4 LEDs 3 connected to PM signals 0 left PM_WTBMerge WM DI Red 1 PM_WTBNoMerge WN 2 PM InstnComplete IC 3 Reserved XX D13 Green ON when Core card ready to come out of reset OK Table 9 LEDs in Revision 10 and Later LED Color Position Function Marking DO Red 0 left PM_DCacheHit DH DI Red 1 PM DCacheMiss DM D2 Red 2 PM ICacheHit IH D3 Red 3 PM ICacheMiss IM D4 Red 4 PM ITLBHit TH D5 Red 5 PM ITLBMiss TM D6 Red 6 PM JTLBHit JH D7 Red 7 PM JTLBMiss JM D8 Red 8 PM WTBMerge WM D9 Red 9 PM_WTBNoMerge WN D10 Red 10 PM_InstnComplete IC D11 Red 11 PM_DTLBHit UH D12 R
16. cation reproduction release modification disclosure or transfer of this information or any related documentation of any kind is restricted in accordance with Federal Acquisition Regulation 12 212 for civilian agencies and Defense Federal Acquisition Regulation Supplement 227 7202 for military agencies The use of this information by the Government is further restricted in accordance with the terms of the license agreement s and or applicable contract terms and conditions covering this information from MIPS Technologies or an authorized third party MIPS MIPS I MIPS II MIPS III MIPS IV MIPS V MIPS 3D MIPS16 MIPS 16e MIPS32 MIPS64 MIPS Based MIPSsim MIPSpro MIPS Technologies logo MIPS VERIFIED MIPS VERIFIED logo 4K 4Kc 4Km 4Kp 4KE 4KEc 4KEm 4KEp 4KS 4KSc 4KSd M4K 5K 5Kc 5Kf 24K 24Kc 24Kf 24KE 24KEc 24KEf 34K 34Kc 34Kf 74K 74Kf 74Kc 1004K 1004Kc 1004Kf R3000 R4000 R5000 ASMACRO Atlas At the core of the user experience BusBridge Bus Navigator CLAM CorExtend CoreFPGA CoreLV EC FPGA View FS2 FS2 FIRST SILICON SOLUTIONS logo FS2 NAVIGATOR HyperDebug HyperJTAG JALGO Logic Navigator Malta MDMX MED MGB OCI PDtrace the Pipeline Pro Series SEAD SEAD 2 SmartMIPS SOC it System Navigator and YAMON are trademarks or registered trademarks of MIPS Technologies Inc in the United States and other countries All other trademarks referred to herein are the property of their respective owne
17. d address or data on SysAD and SysCmd busses EXTRQSTN The system interface is submitting an external request RSTN System reset DEBUG 6 0 Various signals from the 7064 EPLD U7 For debugging Each of the HP Logic Analyzer connectors contains a EVEN part and a ODD part which are labelled individually Below is the pin layout for each connector 5 1 1 J6 ODD label JD3 Pin Signal Pin Signal Pin Signal Pin Signal 1 NC 3 GND 5 SYSCLK 7 SYSAD63 9 SYSAD62 11 SYSAD61 13 SYSAD60 15 SYSAD59 17 SYSAD58 19 SYSAD57 21 SYSAD56 23 SYSAD55 25 SYSAD54 27 SYSAD53 29 SYSAD52 31 SYSAD51 33 SYSAD50 35 SYSAD49 37 SYSAD48 J6 EVEN label JD2 Pin Signal Pin Signal Pin Signal Pin Signal 2 NC 4 NC 6 SYSCLK 8 SYSAD47 10 SYSAD46 12 SYSAD45 14 SYSAD44 16 SYSAD43 18 SYSAD42 20 SYSAD41 22 SYSAD40 24 SYSAD39 26 SYSAD38 28 SYSAD37 30 SYSAD36 32 SYSAD35 34 SYSAD34 36 SYSAD33 38 SYSAD32 5 1 2 J7 ODD label JD1 Pin Signal Pin Signal Pin Signal Pin Signal 1 NC 3 GND 5 SYSCLK 7 SYSAD31 9 SYSAD30 11 SYSAD29 13 SYSAD28 15 SYSAD27 17 SYSAD26 19 SYSAD25 21 SYSAD24 23 SYSAD23 25 SYSAD22 27 SYSAD21 29 SYSAD20 31 SYSAD19 33 SYSAD18 35 SYSAD17 37 SYSAD16 J7 EVEN label JDO Pin Signal Pin Signal Pin Signal Pin Signal 2 NC 4 NC 6 SYSCLK 8 SYSADIS 10 SYSADIA 12 SYSAD13 14 SYSAD12 16 SYSADII
18. ed 12 right PM_DTLBMiss UM CoreLV Users Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 16 6 LEDs Table 9 LEDs in Revision 10 and Later LED Color Position Function Marking D13 Green ON when Core card ready to come out of reset OK Note These functions are only applicable on some MIPS32 4K LVs They are applicable on all MIPS64 5K LVs CoreLV Users Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 17 7 Jumpers 7 Jumpers The following jumper headers can be fitted to the board Those specified for MIPS internal use are not fitted to all production boards Table 10 Board Configuration Jumpers Jumper Type options default Function D onb In revision 09 and earlier Switches between external y clock SMA connector J1 amp on board clock sources JPI In revision 10 and later Enables external clock SMA 2 way ext notfit connector J1 If fitted the on board clock oscillator in socket U6 must be removed JP2 3 way norm pll norm For MIPS internal use only JP3 2 way fit notfit notfit For MIPS internal use only Fit In revision 09 and earlier These jumpers can be removed in order to measure current to the LV as follows 122 1 2 amp 3 4 IO current JP4 10pin n a 3 4 7 8 amp 9 10 Core current 7 8 In Rev 04 the
19. not assume any liability arising out of the application or use of this information or of any error or omission in such information Any warranties whether express statutory implied or otherwise including but not limited to the implied warranties of merchantability or fitness for a particular purpose are excluded Except as expressly provided in any written license agreement from MIPS Technologies or an authorized third party the furnishing of this document does not give recipient any license to any intellectual property rights including any patent rights that cover the information in this document The information contained in this document shall not be exported reexported transferred or released directly or indirectly in violation of the law of any country or international law regulation treaty Executive Order statute amendments or supplements thereto Should a conflict arise regarding the export reexport transfer or release of the information contained in this document the laws of the United States of America shall be the governing law The information contained in this document constitutes one or more of the following commercial computer software commercial computer software documentation or other commercial items If the user of this information or any related documentation of any kind including related technical data or manuals is an agency department or other entity of the United States government Government the use dupli
20. right 1999 2001 MIPS Technologies Inc All rights reserved 9 Clock Circuitry Table 12 Clock Frequencies Crystal Clock Core clock PCB frequency multiplier frequency CPU Rev Manufacturer code MHz factor MHz MIPS32 4K 10 467 TSMC 4KcH01X01 150 2 150 MIPS64 5K 10 5Kc LSS LJA0004 20 2 fixed value 40 MIPS64 5KTM 10 5Kc TI F741763 80 2 160 Note 1 This board runs in PLL bypass mode so the core clock is the same as the crystal frequency The SYSAD bus frequency is half this number 1 6 75 MHz Some variants of this board have been originally built with 125MHZ crystal but can be upgraded to 150MHz Note 2 These board variants require a slower PCI clock from the motherboard See the appropriate motherboard documentation for how to set this CoreL V User s Manual Revision 02 08 22 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 10 PCB Layout 10 PCB Layout This card complies to the standard size as described in Ref 4 The placement of the major components is illustrated in the figures below Offset from e the other gt 6 J3 o three holes 5 PC100 J6 debug J8 debug J7 debug DIMM J9 debug D2 J2 33 Do MIPS LV JP4 O
21. rlier than 2 03 only allocate 128 Mbytes even if the mdule is bigger than this Modules must be capable of 2 cycle CAS latency and a burst length of 8 at 100MHz Parity signals are connected and can be used if desired The CPU can access the DIMM s serial PROM through the I2C bus on the motherboard in order to identify the module characteristics The programmable address for the I2C device is selected to 3 b000 Connections between the GT64120 SDRAM controller and the SDRAM socket are as follows Table 3 GT64120 SDRAM Connectivity GT64120 SDRAM DIMM DAdr 10 0 A 10 0 DMAReq2N DAdr 11 A 11 BAO BAO DMAReqIN BAI BAI AD 63 0 D 63 0 SRASN RAS SCASN CAS DWIN WE SCSN 2 CS 3 2 SCSN 0 CS 1 0 SDQMI7 0 DQM 7 0 ADP 7 0 CB 7 0 3 4 CBUS The CBUS is the motherboards simple bus interface for access to the boot PROM and other devices where a more direct access than that available through the PCI bus is required The CBUS is connected via connector J3 In order to provide the CBUS protocol the GT64120 device bus signals are decoded by the EPLD U7 as shown in Figure 2 Note that in order to isolate the CD signals on the CPU Card from the CBUS data signals on the motherboard a transceiver has been introduced on the CPU Card see figures below CoreLV User s Manual Revision 02 08 Copyright O 1999 2001 MIPS Technologies Inc All rights reserved 3 Description DADAR 2 0
22. rs Template 1 07 Build with Conditional Tags 2B CoreLV User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved Table of Contents Bt Oe Dee 2 Ee EE 3 D SCHPHON dete tet e 2 ns ES AE a O E E E A E E E E 3 11 CPU Power Supply oett tg m a ee E ee 3 2 System Controller GT64120 i a EU 3 2 T Programming Notes i eet etm d diem testi ien ee Mes nent eb 3 3 SDRAM erte di eec A bob m dd tete A 34 CB S citada t e eer P Co eater rte ed dte pite en ee tend det ees 3 5 Een le 3 6 STA ET NEE 37 REVISION Register nt ete eee dee EE Ee P ue in tnt SE er A RE Se nn me en RE ee Te es 9 ConnectOrs o eub A EO e e i eto E 1 Logic Analyzer Connectors ii A e I e ete ope Ep due SL L J6 ODD label LE E EE 3 12 37 ODD label CIDT uie e tr ee teer ette deside t eoe de 5 1 3 J8 ODD label BUS GERT tte tee et Ee RUDI SERE ENTRE EE 3 1 4 J9 ODD label CPU eee et P te e d eee A ee ee e Let its 0 M LE ee LEE 0106 6161 EE 9 CPU Clockmg 3 ee BIO aed e Ne ei ee 10 BEB ayo secs C N Tues M ten 5 0S A References aee A A EA ESE OE OEE ROE A N E E E EA AE AESA B R vision EE re EE CoreLV User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 1 Introduction 1 Introduction This doc
23. se jumper are not implemented see Section 3 1 1 CPU Power Supply for LV current measurement 9 10 Not implemented in revision 10 and later a none JPS 16pin n a fitted For MIPS internal use only JP6 16pin n a fitted For MIPS internal use only The table below shows the jumpers used for internal configuration of the MIPS LV All are not fitted by default CoreL V User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 18 7 Jumpers Table 11 CPU Configuration Jumpers Jumper sub default Function 1 2 z Sets clock multiplier factor 3 4 GMULTP 1 0 3 4 1 2 5 6 notfit Fit to set CTIMERSP 0 disables internal timer 7 8 notfit dus set CPIPEWRP 0 disables pipelined writes over SYSAD In revision 09 and earlier Fit to set CAWBLKP 0 disables 4 word i e 2 doubleword bursts over SYSAD bus JP7 This jumper MUST be fitted as the GT64120 does not support 2 doubleword bursts 9 10 In revision 10 and later This jumper functionality is inverted Default is therefore that the jumper MUST not be fitted as the GT64120 does not support 2 doubleword bursts 11 12 notfit For MIPS internal use only 13 14 15 16 notfit Reserved JP8 all notfit For MIPS internal use only Core V User s Manual Revision 02 08 Copyright 1999 2001 MIPS Technologies Inc All rights reserved 19 8 Switches 8 Switches In revision
24. ument is the User s Manual for the MIPS CoreLV card which is a Core Card designed for use with the MIPS Atlas and other compatible MIPS motherboards There may be small variations between types dependent on the CPU fitted if so they will be documented in this Manual The MIPS CoreLVTM card provides A North Bridge chip with PCI interface SDRAM controller in North Bridge Debug connectors to system busses Clock source for the CPU Interface to MIPS motherboard The MIPS CoreLV card carries one of the standard LV Lead Vehicle implementations of MIPS32 4KTM or MIPS64 SK processor cores see Ref 1 It provides a standard platform for these cores via its interface to a MIPS motherboard q Motherboard Motherboard connectors J3 J4 168 pin SDRAM socket PCI EPLD 7064 GT64120 Core Lead Vehicle Conf jumpers HP LA debug Clock generation Figure 1 Overview The manual is valid for all revisions of the MIPS CoreLVTM card Revision specific issues are treated in the relevant paragraphs The main difference between revision 09 and earlier and revision 10 and later is that revision 10 and later is based on a new PCB design This new PCB design has the following features that differ from the previos one e The board has support for the Galileo GT64120A 100MHz system controller e A transciever isolates the SDRAM data bus from the C
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