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phyCORE-MPC5200B-I/O (HW), Englisch

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1. RN7 RN8 cosa 1 11111111111111111111111111111111 m 10 Ec R98 Cr ae TF EN NEN 104 8105 4 C7 cese 1 il x Figure 23 5200 Component Placement Top View PHYTEC Messtechnik GmbH 2008 L 694e 1 Component Placement Diagram 5 8582 88 sa BEN g 089 _ 2 5 g INH SINH io 2 13 C54 ELLE oa RN6 8 s s S am m Bi Fus itu m Em RT Li IDE 3 ri 8 g 11811918 1 5 6 m s 12 x 38 R107 77 694 _1 Figure 24 phyCORE MPC5200B I O Component Placement Bottom View L PHYTEC Messtechnik GmbH 2008 phyCORE MPC5200B 1 O Index ESO ONE 27 28 TGS E RERUM 30 PEIN S b 59 59 PorResetl 25 ell Tm 28 1 0 2 u etos 31 I 31 PNO A saa 25 B Ac 25 205500 E 25 3
2. 59 14 3 7 Ethernet Interface 1 59 14 3 8 USB Host Interface 60 14 3 9 Audio Interface 60 14 3 10 Compact Flash Card Socket X10 61 14 3 11 IDE Interface 61 14 3 12 PCI Card Slot Ades iui eie bit te coop eiie 61 14 3 13 Misc Configuration Jumpers on the Carrier Board 62 14 3 14 FPGA JTAG Connector 8 62 14 3 15 Pin Assignment Summary of the phyCORE the Expansion Bus and the Patch Field 63 14316 Gold CAP Connector 119 74 15 Revision History 75 16 Component Placement Diagram 76 nere E RE 78 Appendix 81 A 1 Release 5 81 Messtechnik GmbH 2008 1 694 1 Contents Index of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Block Diagram phyCORE MPC5200B V O
3. 23 veter cS 32 ur ite Emu 59 ENK BED 59 LocalPlus Bus 34 32 MAC Address 32 6364 24 59 mu 60 Patch Field 63 PCI Card Slot 61 PCI Interrupt 61 PY ME T 31 PHY Adress 31 phyCORE connector 9 Physical Layer Transceiver 31 Pin Assignment 63 Pin Description 8 18 PHYTEC Messtechnik GmbH 2008 94 1 PIUG dots ote ner idees 57 Pl g P2 58 Power Requirements 24 Power Supply 7 54 Real Time Clock 46 qui 25 Reset Button 51 HS 232 TTL 5 5 22 232 Interface 31 23 24 29 46 RTC Interrupt 46 RTC_CLKOUT 46 SDRAM 28 Bus 28 28 SDRAM 28 Second CAN Interface 58 Second Serial Interface
4. 4 Top View of the phyCORE MPC5200B 1 O PCB Rev 1250 1 5 Bottom View of the phyCORE MPC5200B I O PCB Rev 1250 1 6 Pinout of the phyCORE MPC5200B I O Bottom 9 Numbering of the Jumper 19 Location of the Jumpers phyCORE MPC5200B I O Standard VOTSIOI Du 21 Power Supply DIagrarmi 24 Serial Memory Slave Address 29 U Boot Memory ord eu pent en euet 39 Physical Dimensions Top View 42 Modular Development and Expansion Board Concept with the 00 01 0 52008 0 48 Location of Connectors the phyCORE MPC 5200B I O Carrier 50 Numbering of Jumper Pads 51 Location of the Jumpers View of the Component Side 52 Default Jumper Settings of the phyCORE Development Board MPC5200B I O with phyCORE MPC5200B I O 53 Connecting the Supply Voltage at 6 54 Pin Assignment of the DB 9 Socket P3A as RS 232 PSC3 55 Pin Assignment of the DB 9 Socket P3B as S
5. 30 SRAM Device Options for U11 30 Signal Definition PHY Ethernet Port 02 32 Signal Connection between MPC5200B and FPGA Pins 34 JTAG Interface qs 41 Thee hini al oo EU UD Lc 43 Jumper Configuration for the First RS 232 Interface 55 Jumper Configuration of the DB 9 Socket P3B PSC6 56 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Carrier Board 57 Improper Jumper Settings for the CAN Plug P2A CAN Transceiver on the 57 Jumper Configuration for CAN Plug P2B using the Transceiver on the Carrier Board 0200 58 Improper Jumper Settings for the CAN Plug P2B CAN Transceiver on the Carrier 58 JP17 Configuration of the Programmable LED D3 59 JP8 JP9 Ethernet Interface Configuration 59 JP2 USB Host Interface Configuration 60 JP14 JP15 AC97 Audio Interface Configuration 60 PHYTEC Messtechnik GmbH 2008 1 694 1 Table 24 25 26 Table 27 Table 28 Table 29 30 Table 31 Table 32 33 Table 34 35
6. 56 Serial 5 31 Serial 27 29 SMT 9 Socket First RS 232 55 Socket Second RS 232 56 Solder 5 19 SPEED 59 SPIO Sl 59 SRAM uS GU ARS CET 27 SRAM Options 30 SRAM battery backed 27 30 Start up Configuration 26 Supply Voltage 24 System 27 System Start Up Configuration 26 Technical Specifications 42 E re 25 30 LEO sonos 24 29 Bcc 31 23 uama 23 24 29 46 79 phyCORE MPC5200B 1 O 31 U Bootl 36 USB Full Speed 32 e eaid 32 60 USB HOSE 32 USB Host Interface 60 USB1 1 Interface 32 24 80 Voltage Supervision Voltage Supervisor 9712 Messtechnik GmbH 2008 1 694 1 1 Release Notes The following section contains information about dev
7. Table 14 Jumper Configuration for the First RS 232 Interface 1 E 2 7 Pin 2 TxD3 232 3 Pin 7 CTS3 232 8 Pin 3 RxD3 232 4 Pin 8 CTS3 232 9 5 Pin 5 GND Figure 17 Pin Assignment of the DB 9 Socket P3A as RS 232 PSC3 Front View PHYTEC Messtechnik GmbH 2008 L 694e_1 55 phyCORE MPC5200B 1 O 14 3 3 Second Serial Interface at Socket P3B Socket P3B is the upper socket of the double DB 9 connector at P3 P3B is connected directly to the serial interface PSC6 of the phyCORE MPC5200B I O The only signal configurable with Jumper JP18 is UART6_CTS_TTL coming from PSC6 on the MPC5200B Jumper Setting Description JP18 1 2 Signal UART6 CTS is connected to the RS 232 022 on the 5200 Carrier Board interface signals with RS 232 level are available at connector P3B JP18 open UART6_CTS_TTL signal is freely available Table 15 Jumper Configuration of the DB 9 Socket P3B PSC6 E 2 Pin 2 TxD6 RS232 7 Pin 7 CTS6 RS232 3 8 3 RxD6_RS232 4 Pin 8 RTS6_RS232 9 5 Pin 5 GND Figure 18 Pin Assignment of the DB 9 Socket P3B as Second RS 232 Front View 56 PHYTEC Messtechnik GmbH 2008 1 694 1 5200 on the Carrier Board 14 3 4 First CAN Interface at Plug P2A Plug P2A is the lower plug of the double DB 9 connector at P2 P2A is connected to the first CAN interface of the
8. 6225 10 z 694 1 L PHYTEC Messtechnik GmbH 2008 20 Jumpers RN6 1 m TP1 TP8 AI RN18 RN15 RN14 aa Bite Bite ia Figure 6 Location of the umpers phyCORE MPC5200B O Standard Version PHYTEC Messtechnik GmbH 2008 1 694 1 21 phyCORE MPC5200B 1 O The jumpers J solder jumper have the following functions Jumper Default Comment J1 42 92 disconnect the receive lines UART3_RXD_TTL and UART6 RXD TTL of the MPC5200B PSC3 and PSC6 from the RS 232 transceiver at U3 This makes the controller s TTL signals available at pins X1D16 UART3_RXD_TTL and X1C19 UART6 RXD This is useful for instance for optical isolation of the RS 232 interface The UART receive signals UART3_RXD_TTL and UART6 RXD TTL are disconnected from the RS 232 transceiver The UART receive signals TTL and UART6 RXD TTL are connected to the on board RS 232 transceiver J4 connects pin 7 of the serial memory at U25 to GND On many memory devices pin 7 enables the activation of a write protect function It is not guaranteed that the standard serial memory populating the phyCORE MPC5200B I O will have this write protection function Please refer to the corresponding memory data sheet for more detailed information Packag
9. 38 9 3 Modifying the U Boot 40 10 JTAG Ihtertaca 41 11 Technical Specifications U 42 12 Hints for Handling the Module 45 13 Real Time Clock RTC 8564 U5 46 14 phyCORE MPC5200B I O on the Carrier Board 47 14 1 Concept of the Carrier Board phyCORE MPC5200B l O 47 14 2 Carrier Board phyCORE MPC5200B I O Connectors and i Mec CP 49 14 24 uuu u cis tone recap cont Sosa S haste 49 PHYTEC Messtechnik GmbH 2008 1 694 1 phyCORE MPC5200B 1 O 14 2 2 Jumpers on the Carrier Board phyCORE MPC5200B I O 51 14 3 Functional Components on the phyCORE MPC5200B I O Carrier P M 54 14 3 1 Power Supply at gt 6 54 14 3 2 First Serial Interface at Socket 55 14 3 3 Second Serial Interface at Socket 56 14 3 4 First CAN Interface at Plug 57 14 3 5 Second CAN Interface at Plug 2 58 14 3 6 Programmable LED 016
10. Comments 6 232 PA TxD output on the RS 232 transceiver for the MPC UART PSC6 UART6_RTS_TTL 5 6 request to send signal UART6_CTS TTL O 56 clear to send signal Second Interface 26C 1202 Clock SCL 28C 1222 10 Data SDA Clock for first 2 SCL ETH_DUPLEX ETH_NWAYEN ETH_LINK ETH_SPEED ETH_RX ETH PD COP TRST CK STOP CPU TRST 10 100MBit TP Ethernet Interface if on board PHY is not populated pins are NC Duplex LED Hzhalf duplex L full duplex Collision LED H no collision L collision detected Link Activity LED L link toggle act Speed LED H 10 Mbit s L 100 Mbit s Differential receive input Differential transmit output Power down JTAG Interface JTAG reset input Via logic OR connected to PORRESET resulting in TRST signal Scan enable clock stop JTAG reset in output 44C Timer5 Timer 5 signal of the MPC5200B USB1 Host 45C USB1_OVRCRNT 1 46 USB1_SUSPEND Suspend 48C USB1_RXN Receive negative 49C USB1_TXN Transmit negative 50C USB1_OE O Output enable active high Signal Interface 51C ETH Receive Data Input 53C ETH RXD1 Receive Data Input 1 54C ETH RXDO Receive Data Input 0 55C ETH_COL Collision Detect Input 56C ETH_RXDV Receive Data Valid 58C ETH TXERR Transmit Error Output 59C ETH_TXD2
11. Pin EG phyCORE MPC5200B O Hardware Manual Edition April 2008 product of Technology Holding company phyCORE MPC5200B 1 O In this manual are descriptions for copyrighted products that are not explicitly indicated as such The absence of the trademark and copyright symbols does not imply that a product is not protected Additionally registered patents and trademarks are similarly not expressly indicated in this manual The information in this document has been carefully checked and is believed to be entirely reliable However PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result Additionally PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves the right to alter the layout and or design of the hardware without prior notification and accepts no liability for doing so Copyright 2007 PHYTEC Messtechnik GmbH D 55129 Mainz Rights including those of translation reprint
12. The default PHY address configured with the boot strapping option is 0x1 Table 10 shows the interface signals for the Ethernet channel PHYTEC Messtechnik GmbH 2008 L 694e 1 31 phyCORE MPC5200B 1 O FEC Channel Pin Function Location at phyCORE PHY U2 Connector ETH_RX Differential positive receive input signal X1D35 ETH Differential negative receive input signal X1C35 ETH _ Differential positive transmit output signal X1D36 ETH TX Differential negative transmit output signal X1C36 ETH LINK Link activity LED output X1C33 H LED off no link L LED on link toggle LED toggle activity ETH SPEED Speed LED output X1C34 H LED off 10BT L LED on 100BT ETH DUPLEX Duplex LED output 1 29 Half Duplex L VLED on Full Duplex ETH NWAYEN _ Collision LED output X1C30 H LED off no collision L LED on collisions Table 10 Signal Definition PHY Ethernet Port U2 7 2 2 MAC Address In a computer network such as a local area network LAN the MAC Media Access Control address is a unique computer hardware number For a connection to the Internet a table is used to convert the assigned IP number to the hardware s MAC address In order to guarantee that the MAC address is unique all addresses are managed in a central location PHYTEC has acquired a pool of MAC addresses The MAC address of the phyCORE MPC5200B is located on the bar code sticker attached to
13. 015 730 13 750 16 760 14 770 15 780 12 800 FPGA B3 G16 810 12 820 830 411 850 916 860 15 870 16 y o 88D FPGA B3 L14 900 12 910 15 920 16 93 15 950 15 960 4 970 7 98D FPGA B4 7 1000 connected Table 2 Pinout of the phyCORE Connector X1 18 PHYTEC Messtechnik GmbH 2008 L 694e_1 Jumpers 3 J umpers For configuration purposes the phyCORE MPC5200B I O has 12 solder jumpers some of which have been installed prior to delivery Figure 5 illustrates the numbering of the jumper pads while Figure 6 and indicates the location of the jumpers on the board open closed Les 1 2 1 1 2 41000 6 2 2 3 5 6 Dur 7 8 9 Figure 5 Numbering of the J umper Pads PHYTEC Messtechnik GmbH 2008 94 1 19 phyCORE MPC5200B 1 O 024 Ji5 mg TP18 comP m m E TP17 m 0 06 imm 431111112 08 U7 gt Tr m XT1 0 RN2 LS JE U5
14. I L D m L mee s x IN 82 A 1 mm mm a BREE m 2 J5 B e 1 a 12 LE am j m 5 1 1 1 JP9 1 __ JL EE PIB op m panat npa m SS Tope ee rl m JP3 0000 0000 2 00 mE gPI7 JPI6 Eo mp gue T El n Figure 15 Default Settings of the phyCORE Development Board 5200 1 with phyCORE MPC5200B 1 O PHYTEC Messtechnik GmbH 2008 1 694 1 53 phyCORE MPC5200B 1 O 14 3 Functional Components on the phyCORE 5200 Carrier Board This section describes the functional components of the phyCORE Carrier Board HD200 supported by the phyCORE MPC5200B I O and appropriate jumper settings to activate these components Depending on the specific configuration of the phyCORE MPC5200B I O module alternative jumper settings can be used These jumper settings are different from the factory default settings as shown in Figure 15 and enable alternative or additional functions on the phyCORE MPC5200B l O Carrier Board depending on user needs 14 3
15. 36 Messtechnik GmbH 2008 Contents JP11 CF Card Interface Configuration 61 Misc Configuration Jumpers JP10 12 62 FPGA JTAG Connector X8 Pin 62 Pin Assignment Data Address Bus for the phyCORE MPC5200B Carrier Board Expansion 65 Pin Assignment Dedicated LocalPlus Control Signals phyCORE MPC5200B I O Carrier Board Expansion Board 66 Pin Assignment PCI dedicated signals phy CORE MPC5200B I O Carrier Board Expansion 66 Pin Assignment Dedicated ATA IDE Interface Signals phyCORE MPC5200B I O Carrier Board Expansion Board 66 Pin Assignment Interfaces for the phyCORE MPC5200B 1 O Carrier Board Expansion 67 Pin Assignment COP Interface Signals for the phyCORE MPC5200B I O Carrier Board Expansion Board 68 Pin Assignment Misc Control Signals for the phyCORE MPC5200B I O Carrier Board Expansion Board 69 Pin Assignment FPGA Signals for the phyCORE MPC5200B l O Carrier Board Expansion 72 Pin Assignment Power Supply for the phyCORE MPC5200B 1 O
16. 40D X2 12 X5 12 X7 41D 42D 43D 45D 12 X8 12 X3 10 46D 47D 48D X4 10 X6 10 X9 100D 10 11 X4 11 6 11 9 11 12 4 12 6 12 9 25 Table 36 Unused Pins on the phyCORE MPC5200B O Carrier Board Expansion Board 14 3 16 Gold CAP Connector C119 The mounting space C119 see PCB stencil is provided for connection of a gold cap that buffers the RTC and the SRAM on the phyCORE MPC5200B 1 O In the event of VCC operating voltage failure the RTC and SRAM is automatically supplied with power from the connected gold cap The optional gold cap required for the RTC and SRAM buffering is available through PHYTEC order code CG 002 74 PHYTEC Messtechnik GmbH 2008 L 694e 1 Ethernet Port 15 Revision History Version Changes in this manual numbers 7 Mar 2007 Manual 1694 0 First draft Preliminary documentation PCM 032 phyCORE MPC5200B 1 O in Prototype state PCB 1250 1 PCM 973 PCB 1260 0 PHYTEC Messtechnik GmbH 2008 94 1 75 phyCORE MPC5200B 1 O 16 Component Placement Diagram 76 a 024 1111 00000000 don find s R47 R48 R50 00000000 76 65 mm HJG m ELE E
17. CPU TRST 41C C l Table 32 Pin Assignment COP Interface Signals for the phyCORE MPC5200B I O Carrier Board Expansion Board 68 PHYTEC Messtechnik GmbH 2008 L 694e 1 5200 on the Carrier Board Signal phyCORE Module Expansion Bus Patch Field IRQ 0 4A 4A X15 1 IRQ 1 2B 2B X12 1 IRQ 2 3B 3B X13 1 IRQ 3 3A 3A X14 1 Timer2 12D 12D X4 4 Timer3 13D 13D 6 4 4 61 61 2 16 5 44C 44C X7 11 Timer6 60C 60C 8 15 36 17 9 100 100 2 4 HReset 11C 11C 9 2 SReset 10C 10C 9 1 PWR_GOOD 7D 7D X7 1 FL_WP 9C 9C X8 2 GPIO7 11D 11D X3 4 RTC CLKOUT 1B 1B X11 1 IRQRTC 33D 33D X6 9 PSC2 4 43C 43C X5 11 ETH 58D 58D X6 15 ETH TXD2 59C 59C X7 15 ETH TXD1 60D 600 X9 15 ETH TXDO 61D 61D X3 16 ETH RXD3 51C 51C X2 14 ETH RXD2 52D 52D X4 14 ETH RXD1 53C 53C X5 14 ETH RXDO 54 54 7 14 ETH 5 500 500 9 12 51 51 X3 14 ETH TXCLK 530 530 6 14 ETH RXCLK 55D 55D X9 14 ETH 56D 56D X3 15 ETH MDC 57D 57D X4 15 ETH TXEN 62D 62D X4 16 ETH TXERR 58C 58C X5 15 ETH RXDV 56C 56C X2 15 ETH COL 55C 55C X8 14 Test Sel 1 35A 35A X16 9 ETH NWAYEN 30C 30C X8 7 ETH DUPLEX 29C 29C 7 7 WDI 8D 80 9 7 2 WDO 8C 8C X8 1
18. Carrier Board Expansion 79 Unused Pins on the phyCORE MPC5200B 1 O Carrier Board Expansion Board Suet et ass itia tuse 74 L 694e 1 Preface Preface This phyCORE MPC5200B 1I O Hardware Manual describes the board s design and functions Precise specifications for the Freescale MPC5200B microcontroller series can be found in the enclosed MPC5200B microcontroller Data Sheet User s Manual If software is included please also refer to additional documentation for this software In this hardware manual and in the attached schematics low active signals are denoted by a in front of the signal name i e RD 0 indicates logic zero or low level signal while 1 represents a logic one or high level signal Declaration regarding Electro Magnetic Conformity of the PHYTEC phyCORE MPC5200B I O C PHYTEC Single Board Computers henceforth products are designed for installation in electrical appliances or as dedicated Evaluation Boards i e for use as a test and prototype platform for hardware software development in laboratory environments Note PHYTEC products lacking protective enclosures are subject to damage by ESD and hence may only be unpacked handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers It is also necessary th
19. Figure 13 Numbering of J umper Pads 0 Messtechnik GmbH 2008 1 694 1 51 phyCORE MPC5200B 1 O sm uU 1 mu sn 1 D 3 Was mmm mum m mam m m 1 2 1 1 un si 1 Wa t n au 18 X JPI7 6 lal 255 SPIO LE J Qo Figure 14 Location of the J umpers View of the Component Side 52 PHYTEC Messtechnik GmbH 2008 1 694 1 5200 on the Carrier Board Figure 15 shows the factory default jumper settings for operation of the phyCORE MPC5200B I O Carrier Board with the standard phyCORE MPC5200B 1 O standard MPC5200B controller use of first and second RS 232 both CAN interfaces and LED D3 on the Carrier Board Jumper settings for other functional configurations of the phyCORE MPC5200B l O module mounted on the Carrier Board are described in section 14 3 B 1 1 UU
20. SPI Bus UARTO RXD6 TXD6 UART6 TTL Timer Outputs PWM CS Signals for ATA Interface COP JTAG Debug Test Port VBat 3V for RTC and SRAM Power 3V3 1 2A L 694e_1 1 2 View of the phyCORE MPC5200B I O ma 1111 um tome Ue immu 111111114 8 R63 R61 H maka THU PUTIH E ELI C7 R66 Be SEJE SEM ne LIB AND 2225 m NIE fitting Figure 2 Top View of the phyCORE MPC5200B I O Rev 1250 1 Or PHYTEC Messtechnik GmbH 2008 1 694 1 5 phyCORE MPC5200B 1 O ma CP 1107 css ay Jmm uw 29 x 82 RN18 Rite 103 Figure 3 Bottom View of the phyCORE MPC5200B I O Rev 1250 1 6 PHYTEC Messtechnik GmbH 2008 L 694e 1 Introduction 1 3 Minimum Requirements to Operate the phyCORE MPC5200B 1 O Basic operation of the phyCORE MPC5200B 1 O only requires supply of a 3V3 input voltage and the corresponding GND connection These supply pins are located at the phyCORE connector X1 3 3 x1 1C 2C 4C 5C 1D 2D GND x1 3C 3D 7C 9D 12C 14D Caution We recommend connect
21. 1 Power Supply at X6 Caution Only use the included power adapter to supply power to the Carrier Board Do not change modules or jumper settings while the Carrier Board is supplied with power Permissible input voltage 9 14 V DC unregulated The required current load capacity of the power supply depends on the specific configuration of the phyCORE MPC5200B I O mounted on the Carrier Board as well as whether an optional expansion board is connected to the Carrier Board An adapter with a minimum supply of 1 2 A is recommended Polarity C HO 49 14 VDC enter Hole 2 1200 mA emm 5 0 mm 2 GND Figure 16 Connecting the Supply Voltage at X6 No jumper configuration is required in order to supply power to the phyCORE MPC5200B I O module 54 PHYTEC Messtechnik GmbH 2008 L 694e_1 5200 on the Carrier Board 14 3 2 First Serial Interface at Socket Socket P3A is the lower socket of the double DB 9 connector at P3 P3A is directly connected to the serial interface PSC3 of the phyCORE MPC5200B I O The only signal configurable with Jumper JP18 is UART3_CTS_TTL coming from PSC3 on the MPC5200B Jumper Setting Description JP18 3 4 Signal UART3 CTS TTL is connected to the RS 232 022 on the phyCORE MPC5200B 1 O Carrier Board interface signals with RS 232 level are available at connector JP18 open UART3_CTS_TTL signal is freely available
22. 2 3 2 3 OxA8 1 2 1 2 OXAD 243 1 2 Table 8 Serial Memory 2 Address Examples Address lines 1 and 2 not always made available with certain serial memory types This should be noted when configuring the bus slave address 6 4 Optional Battery Backed SRAM The phyCORE MPC5200B I O can be populated with an optional battery backed SRAM supporting non volatile data storage The use of the backup battery is optional However when used without the battery as a backup supply during power down of the phyCORE MPC5200 B I O module all data stored in this SRAM device will be lost The optional SRAM features either 1 MByte or 2 MByte of storage capacity and has a 16 bit data bus connection to the processor Note With a typical SRAM standby current draw of 5 pA at 3 V and when using 3V 190mAh Lithium battery the longest possible backup period would be up to 4 years Replacement of the backup battery is required at this time Access to the battery backed SRAM is controlled by the processor s Chip Select signal CS2 However the Byte Select lines are generated by the GAL ATF16LV8C based on the TSIZ signals from the processor Table 9 gives an overview of available SRAM types for use at 011 on the phyCORE MPC5200B I O at the time this manual was created PHYTEC reserves the right to use alternative SRAM types should they become available in the future Type Capacity Access
23. 90C X8 22 FPGA M12 9D 900 X9 22 FPGA B3 M14 91C 91C X2 24 FPGA M15 91D 91D X3 24 FPGA B3 M16 92D 92D X4 24 FPGA B3 N12 93C 93C X5 24 FPGA B3 N15 93D 93D X6 24 FPGA B3 N16 94C 94C 7 24 14 95 95 8 24 _ _ 15 950 950 9 24 16 96 96 2 25 FPGA B4 960 96D X3 25 FPGA B4 K7 97D 97D X4 25 FPGA B4 N6 98C 98C 5 25 7 98D 98D X6 25 99 99 7 25 FPGA B4 R6 100C 100C X8 25 Table 34 Pin Assignment FPGA Signals for the 72 phyCORE MPC5200B 1 O Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2008 L 694e 1 5200 the Carrier Board Signal phyCORE Module Expansion Bus Patch Field 1C 2 1D 2D X2 1 X2 2 1 X3 2 3V3 1C 2C 4C 5C 4 4 1 4 2 10 20 FGPA_VCCIO 4D 5D 40 5D ber Jumper X5 1 X5 2 VCC_SRAM 6D 6D 6 2 6 6 6 1 GND 2A 12A 17 2A 12A 17 X2 3 X2 8 X2 13 22 27 32A 22 27 32A 2 18 2 23 3 37A 42A 47 52 37A 42A 47A 52 3 8 3 13 X3 18 57 62 67A 72 57 62 67 728 3 23 X4 3 4 8 82 87 92 77 82 87 92 4 13 4 18 4 23 97 97 5 3 5 8 5 13 4 9 14 19 4 9 14 198 5 18 5 23 6 3 248 29 3
24. Backup U Boot In the event the original U Boot at address OxFFFO 0000 becomes corrupted e g by overwriting the loader with a wrong version a second U Boot loader at address 0000 is available as an emergency backup version providing the same functionality as the original copy This backup U Boot can be started by connecting a 4 7kOhm pull down resistor at pin X1 C8 during a hardware reset cycle Note When using the phyCORE MPC5200B I O in conjunction with the applicable Carrier Board part number PCM 973 the Backup U Boot loader can be started by closing Jumper JP3 at position 1 2 38 PHYTEC Messtechnik GmbH 2008 L 694e 1 Flash 32MByte OxFFFF FFFF OxFFF4 0000 U Boot highSector 124 OxFFFO 0000 OxFE040000 U Boot low Sector 0 OxFEO0 0000 EEPROM 4kByte OxOFFF environment Figure 9 U Boot Memory PHYTEC Messtechnik GmbH 2008 L 694e 1 U Boot Boot Loader RAM 64MByte 0x0400 0000 U Boot is working from here OxOSFB 0000 STACK counting down 0 0000 0000 Trap table 0x0000 0100 39 phyCORE MPC5200B 1 O 9 3 Modifying the U Boot Loader Changing the U Boot should always be compared to recompiling the program code and updating the Flash contents A detailed description of each individual step would by far exceed the scope of this Hardware Manual Please refer to the Application Note Configuring and Updating the Boot Loader document number LA
25. FPGA B1 58B 33C 5 9 FPGA B1 4 59A 59A X15 15 FPGA B1 P1 60A 60A X16 15 FPGA B1 P2 60B 34C 7 9 1 618 350 9 9 2 11 88 88 13 2 2 08 15 2 2 11 10 10 16 2 FPGA_B2_F10 10B 10B X10 4 FPGA_B2_G10 11A 11A X17 2 FPGA_B2_F9 11B 11B X11 4 70 PHYTEC Messtechnik GmbH 2008 L 694e_1 5200 on the Carrier Board Signal phyCORE Module Expansion Bus Patch Field FPGA B2 D11 12B 12B X12 4 FPGA B2 B11 13A 13A X14 4 FPGA B2 D10 13B 13B X13 4 FPGA B2 A11 14A 14A X15 4 FPGA B2 B9 15A 15A X16 4 FPGA B2 B10 15B 15B X10 5 FPGA B2 A9 16A 16A X17 4 FPGA B2 A10 16B 16B X11 5 FPGA B2 B8 17B 17B X12 5 FPGA B2 F8 18A 18A X14 5 FPGA B2 A8 18B 18B X13 5 FPGA B2 F7 19A 19A X15 5 FPGA B2 A7 20A 20A X16 5 FPGA B2 G7 20B 20B X10 6 FPGA B2 B7 21A 21A X17 5 FPGA B2 G6 21B 21B X11 6 FPGA B2 F6 22B 22B X12 6 FPGA B2 D6 23A 23A X14 6 FPGA B2 E6 23B 23B X13 6 FPGA B2 C6 24A 24A X15 6 FPGA B2 A6 25A 25A X16 6 FPGA B2 C5 25B 25B X10 7 FPGA B2 B6 26A 26A X17 6 FPGA B2 C4 26B 26B X11 7 FPGA B2 A5 27B 27B X12 7 FPGA B2 A4 28A 28A X14 7 FPGA B2 B5 28B 28B X13 7 FPGA B2 B4 29A 29A X15 7 FPGA B2 A3 30A 30A X16 7 FPGA B2 D9 30B 30B X10 9 FPGA B2 B3 31A 31A X17 7 FPGA B2 A1
26. FPGA B1 L1 FPGA B1 L3 FPGA B1 M2 FPGA B1 M4 FPGA B1 1 FPGA B1 FPGA B1 P2 FPGA FPGA JTAG Singals 62B FPGA_TMS Test Mode Select 63B FPGA_TCK Test Clock LocalPlus Address Data Signals EXT_AD30 EXT_AD27 EXT_AD25 EXT_AD24 EXT_AD21 EXT_AD19 EXT_AD18 EXT_AD16 EXT_AD15 EXT_AD13 EXT_AD12 EXT_AD10 EXT_AD6 EXT AD5 EXT ADS EXT ADO ATA Interface Signals ATA DMA request ATA write ATA write enable for PCI bus sharing ATA DMA acknowledge Dedicated PCI Signals PCI and external peripheral clock PCI bus request Initial device select Frame start Target ready Transition stop Bus parity Command byte enable 0 ATA DRQ ATA_IOW ATA Isolation ATA DACK PCI CLOCK PCI REQ PCI IDSEL PCI FRAME PCI TRDY PCI STOP PCI PAR PCI CBE 0 000 PHYTEC Messtechnik GmbH 2008 L 694e 1 13 phyCORE MPC5200B 1 O Comments Pin Row X1C 1C 2C 4 3 3 Supply voltage 3 3 VDC 5C 7C 12C GND Ground 0 V 17C 22C 27C 32C 37 42C 47C 52C 57C 62C 67C 72C 77C 82C 87C 92C 97C 6C VBAT Connection for external battery 2 4 3 3 V to supply backup the RTC U5 External Watchdog output FL_WP Flash Write Protection only with P33 Flash populated 1 10C SRESET External SRESET is an open drain signal which is connected to a 10 kOhm pull up resistor on the module Assertion of SRESET causes assertion of the internal soft reset Internal soft res
27. PCBs when the module is mounted on the corresponding carrier board In order to get the exact spacing the maximum component height 3 0 mm on the underside of the phyCORE must be subtracted Component height 6 mm Manufacturer Molex Number of pins per contact row 200 2 rows of 100 pins each Molex part number lead free 53467 1009 header Component height 10 mm Manufacturer Molex Number of pins per contact row 200 2 rows of 100 pins each Molex part number lead free 53553 1009 header Please refer to the corresponding data sheets and mechanical specifications provided by Molex www molex com 44 Messtechnik GmbH 2008 L 694e_1 Real Time Clock RTC 8564 U5 12 Hints for Handling the Module e Modifications on the phyCORE Module Removal of various components such as the microcontroller and the standard quartz is not advisable given the compact nature of the module Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to loosen rendering the module inoperable Carefully heat neighboring connections in pairs After a few alternations components can be removed with the solder iron tip Alternatively a hot air gun can be used to heat and loosen the bonds Caution If any modifications to the module are performed regardless of their nature the manufacturer guarant
28. SRAM 05 U11 Figure 7 Power Supply Diagram 24 PHYTEC Messtechnik GmbH 2008 L 694e_1 Power Requirements Internally generated voltages 1V2 1V5 2V5 e 3V3 PowerPC FPGA I O Flash memory 2 5 DDR SDRAM and Ethernet PHY 1 5 PowerPC Core e 1V2 FPGA Core and FPGA PLL 4 1 Voltage Supervision and Reset The input voltage 3V3 as well as the on board generated operation voltages 2V5 and 1V5 are monitored by a voltage supervisor device at U22 This circuitry is responsible for generation of the system reset signal PorReset The voltage supervisor IC initiates a reset cycle if any operating voltage drops below its minimum threshold value After all voltages reach their required value the supervisor chip adds an additional 200 ms delay until the PorReset line will be inactive high PorReset connects to the processor reset input PorReset is combined the diodes D7 and with TRST to a logic OR with CPU JTAG controller reset as output This logic connection is used to ensure a proper reset of the CPU internal debug interface by PorReset or by the COP signal COP The PorReset signal can be used in order to force a reset of the phyCORE MPC5200B I O module by an external source The PorReset signal can be considered as both an input and an output In order to release a proper reset the PorReset signal should be pulled to GND for the duration of the reset via an open coll
29. Table 1 can only be used if a special module configuration was purchased e g SBC version without on board RS 232 transceivers Please contact PHYTEC for more details Note The following sections of this manual assume use of the port pins according to configuration listed in Table 1 CPU Port Function Port_conf Used on Register Bits phyCORE SBC PSC1 97 1 01x 29 31 PSC2 CAN 1 2 001 25 27 No PSC3 UARTS SPI 1100 20 23 Yes USB USB 01 18 19 No Ethernet Ethernet w MD 0101 12 15 Yes Timer ATA CS 00 11 2 3 6 7 No 2 1261 2 2 default Yes 12 1 available PSC6 UART6 101 9 11 Yes Table 1 Default Port Configuration 8 PHYTEC Messtechnik GmbH 2008 L 694e 1 Pin Description As Figure 4 indicates all controller signals extend to surface mount technology SMT connectors 0 635 mm lining two sides of the module referred to as phyCORE connector refer to section 2 This allows the phyCORE MPC5200B I O to be plugged into any target application like a big chip DC A 100 100 100 100 x1 X1 Figure 4 Pinout of the phyCORE MPC5200B I O Bottom View Table 2 provides an overview of the pinout of the phyCORE connector Please refer to the Freescale MPC5200B User Manual Data Sheet for details on the functions and features of controller signals and port pins PHYTEC Messtechnik GmbH 2008 1 694
30. The available capacity is 4 kByte Note The first 2 kilobytes section of the EEPROM is already used for storing the boot manager U Boot environment variables This portion must not be used by user data The MPC5200B processor provides two on chip interfaces The memory device is connected to interface 2 Table 7 gives an overview of the possible devices for use at U25 as of the printing of this manual Type M Address Write Life d Frequenc Pins Cycles Data y EEPRO 4 400 kHz 2 A1 1 000 100 CAT24WC32 CATALYST M kBytes 000 5 Table 7 Serial Memory Options for 025 It is important to note that the RTC U5 is also connected to the 2 bus The RTC can operate with a bus frequency up to 400 kHz Therefore the use of high bus frequencies for accessing the serial memory is not recommended The RTC has the bus slave address 2 The slave address of the serial memory must be selected accordingly using solder jumpers J5 A1 and J6 A2 to avoid bus collision The address input AO is hard wired to GND Serial Memory Address OxA 14 GND Figure 8 Serial Memory I C Slave Address PHYTEC Messtechnik GmbH 2008 1 694 1 29 phyCORE MPC5200B 1 O Possible configuration options are shown below Address J13 J14 1 2 OxA1 1 2 2 3 4
31. Time Device Manufacturer 1 55ns 70ns K6F8016U6M Samsung SRAM 2 MByte 55ns 70ns K6F1616U6C Samsung SRAM 2 MByte 45ns CY62167DV30 Cypress SRAM 2 MByte 45ns 55ns HM62V16100 Renesas Table 9 SRAM Device Options for U11 30 PHYTEC Messtechnik GmbH 2008 L 694e_1 Serial Interfaces 7 Serial Interfaces 7 1 RS 232 Interface A dual channel RS 232 transceiver is located on the phyCORE MPC5200B I O at This device adjusts the signal levels of the UART3_RXD TXD_TTL and UART6_RXD TXD_TTL lines MPC5200B PSC3 PSC6 The RS 232 interface enables connection of the module to a COM port on a host PC or other peripheral devices In this instance the RXD3 232 or RXD6 232 line X1D22 X1C21 of the transceiver is connected to the corresponding TXD line of the COM port while the TXD3 232 or TXD6 232 line X1D23 X1C23 is connected to the RXD line of the COM port The Ground circuitry of the phyCORE MPC5200B 1I O must also be connected to the applicable Ground pin on the COM port The processor s on chip UART supports handshake signal communication Use of an RS 232 signal level in support of handshake communication requires use of an external RS 232 transceiver not located on the module Furthermore it is possible to use the TTL signals of both of the UART channels externally These signals are available at X1D16 X1D17 UART3_RXD_TTL UART3_TXD_TTL and X1C19 1 20 UART6_RXD_TTL UART6_TXD_TTL on the phyCORE connect
32. U12 in order to ensure proper functioning of the phyCORE module The GAL will generate the Flash CS signal based on its input signals closed X If 415 is populated then the Flash CS signal is directly connected to the controller s CSO signal The user has to ensure that only one of these options is used Having both J15 and U12 installed at the same time is not allowed Package Type SMD 0402 Table 3 PHYTEC Messtechnik GmbH 2008 J umper Settings L 694e 1 23 phyCORE MPC5200B 1 O 4 Power Requirements The phyCORE MPC5200B 1 O only requires one main supply voltage Supply voltage 3 3 V 10 96 with 1 5 A load Caution Connect all 3V3 input pins to your power supply and at least the matching number of GND pins neighboring the 3V3 pins As a general design rule we recommend connecting all GND pins neighboring signals which are being used in the application circuitry Optional Supply Input VBAT VBAT is the input pin that supplies the Real Time Clock U5 The MAX6364 battery supervisor IC U12 senses the 3 3 V main supply and VBAT and switches to the voltage with the higher level VBAT should be supplied from a 3 V source i e lithium battery 3V3 Power 2V5 i pe Converter Power Voltage PorReset Eo 1 1V5 Supervisor Converter PWR_Good Power DC DC 1V2 Converter Power VCC SRAM DC DC Converter Real Time Optional Clock
33. at 400 MHz 40 to 85 32 k instruction cache 32 k data cache Double precision FPU Instruction and data MMU e SDRAM DDR SDRAM memory Interface up to 132 MHz operation SDRAM and DDR SDRAM support 256 MByte addressing range per CS two CS available e Flexible multi function external bus interface Peripheral component interconnect controller controller BestComm DMA subsystem 6programmable serial controllers PSC configurable for the following functions e Fast Ethernet controller FEC Supports 100Mbps IEEE 802 3 10 Mbps IEEE 802 3 e Universal serial bus controller USB USB revision 1 1 host e Two inter integrated circuit interfaces 12 e Serial peripheral interface SPI e Dual CAN 2 0 controller MSCAN e 31850 byte data link controller BDLC e Test debug features e JTAG IEEE 1149 1 test access port Common on chip processor COP debug port Memory Configuration DDR SDRAM 64 MByte to 128 MByte e Flash up to 64 MByte Intel Strata Flash memory 32 bit memory width only asynchronous J3 P33 devices are supported memory 4 kByte EEPROM Other Board Level Features Two UART ports RS 232 interfaces RxD TxD One 10 100 Mbit s Ethernet port via optional Micrel PHY Real Time Clock with calendar and alarm function FPGA with ca 8000 logic cells configurable through controller interface or active serial configuration device Up to 2 MByte batter
34. be made available by adding the corresponding resistor on the Carrier Board Note The current draw of the PCI application in combination with the power consumption of all other circuitry used at the same time must not exceed the allowed maximum current draw for the phyCORE MPC5200B I O and Carrier Board hardware combination PHYTEC Messtechnik GmbH 2008 L 694e 1 61 phyCORE MPC5200B 1 O 14 3 13 Misc Configuration umpers on the Carrier Board The following table describes additional jumpers provided for configuration of the Carrier Board or the phyCORE MPC5200B I O operated on it Jumper Setting Description JP3 open Default Boot configuration of the connected phyCORE MPC5200B I O will be used 1 2 Boot configuration of the inserted 5200 will be overwritten by a LOW level 2 3 Boot configuration of the inserted 5200 will be overwritten by a HIGH level JP10 open Default Flash Bank Select configuration of the connected phyCORE 5200 will be used 1 2 Flash Bank Select configuration of the inserted phyCORE MPC5200B will be overwritten by a LOW level 2 3 Flash Bank Select configuration of the inserted phyCORE MPC5200B will be overwritten by a HIGH level JP12 open Independent JTAG clocks for FPGA JTAG interface Controller JTAG interface JTAG clock for controller FPAG connected only applicable conjuncti
35. configuration of the analog multiplexer U17 If the flexible configuration option is selected the processor s GPIO6 signal is used to configure the analog multiplexer from user software This allows the user to switch between using the corresponding GPIO signals for either programming the FPGA at runtime or to use the signals with the alternative function depending on the application requirements 8 2 2 Configuration via Serial Configuration Device As an alternative to configuring the FPGA via the processor s GPIOs it is also possible to configure the FPGA using a serial configuration device from ALTERA e g EPCS4 The difference to the variant described in section 8 2 1 is that the contents of the FPGA can only be changed over the JTAG interface of the FPGA or by exchanging the contents of the serial configuration device A corresponding initialization of the FPGA is started following power up of the phyCORE MPC5200B Subsequent reconfiguration via software is no longer possible The FPGA s contents are retained until the next power down 8 3 TAG Interface The FPGA provides a JTAG interface for convenient programming and testing during the development stage of the corresponding FPGA firmware The JTAG programming method is always prioritized over all other means of loading code to the device This means that firmware previously loaded in the FPGA will be overwritten by a JTAG programming cycle When using ALTERA s proprieta
36. in customer designed applications 14 1Concept of the Carrier Board phyCORE MPC5200B The Carrier Board phyCORE MPC5200B 1 O provides a flexible development platform enabling quick and easy start up and subsequent programming of the phyCORE MPC5200B I O Single Board Computer module The Carrier Board design allows easy connection of additional expansion boards featuring various functions that support fast and convenient prototyping and software evaluation This modular development platform concept is depicted in Figure 11 and includes the following components e actual Carrier Board 1 which offers all essential components and connectors for start up including a power socket enabling connection to an external power adapter 2 and serial interfaces 3 of the SBC module at DB 9 connectors depending on the module up to two RS 232 interfaces and up to two RS 485 or CAN interfaces e All of the signals from the SBC module mounted on the Carrier Board extend to two mating receptacle connectors A strict 1 1 signal assignment is consequently maintained from the phyCORE connectors on the module to these expansion connectors Accordingly the pin assignment of the expansion bus 4 depends entirely on the pinout of the SBC module mounted on the Carrier Board e the physical layout of the expansion bus is standardized across all applicable PHYTEC Carrier Boards we are able to offer various expansion boards 5 that attach to
37. occur to a specific time or date 10 100MBit TP Ethernet Interface if on board PHY is not populated pins are NC Differential receive input 35D ETH_RX Differential transmit output 36D ETH O MII interface interrupt 37D ETH INT 5200 JTAG interface 38D CPU_TCK H Clock 40D CPU TDI Datain 410 CPU Data out 42D CPU_TMS Mode select 0581 Host 43D USB1_PORTPWR Enable disable port power 45D USB1_SPEED Speed select 46D USB1_RXD Receive data 47D USB1_RXP Receive positive 48D USB1_TXP Transmit positive PHYTEC Messtechnik GmbH 2008 1 694 1 17 phyCORE MPC5200B 1 O Signal Comments Interface Signals 50D ETH_CRS 510 _ Receive Error Input 52D ETH RXD2 Receive Data Input 2 53D ETH_TXCLK Transmit Clock 55D ETH RXCLK 560 ETH Management Data 570 _ Management Data Clock 58D ETH Transmit Data Output 60D ETH_TXD1 Transmit Data Output 1 61D ETH TXDO Transmit Data Output 0 62D ETH_TXEN Transmit Enable Flash Bank Selection 63D FL_Bank_Sel Selection Flash Bank if P33 Flash is populated 65D 2 12 FPGA Signals 660 2 13 670 2 13 680 2 13 700 16 710 014 720
38. on the boards providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design The phyCORE MPC5200B I O is a subminiature 53 x 57 mm insert ready Single Board Computer populated with Freescale s PowerPC MPC5200B microcontroller Its universal design enables its insertion in a wide range of embedded applications All controller signals and ports extend from the controller to high density 0 635 mm Molex pin header connectors aligning two sides of the board allowing it to be plugged like a big chip into a target application Precise specifications for the controller populating the board can be found in the applicable controller User s Manual or Data Sheet The descriptions in this manual are based on the MPC5200B controller No description of compatible microcontroller derivative functions is included as such functions are not relevant for the basic functioning of the phyCORE MPC5200B 1 O The 5200 offers the following features e Single Board Computer in subminiature form factor 84 x 57 according to phyCORE specifications applicable controller and other logic signals extend to two high density 200 pin Molex connectors processor Freescale embedded PowerPC 5200 e single max 1 2 A supply voltage 2 PHYTEC Messtechnik GmbH 2008 1 694 1 Introduction Internal Features of the MPC5200B e300 core 760 MIPS
39. phyCORE MPC5200B I O via jumpers There are no CAN transceivers available on the phyCORE MPC5200B I O therefore the transceivers on the Carrier Board must be used Depending on the configuration of the CAN transceivers and their power supply the following configuration is possible 1 CAN signals generated by the Carrier Board CAN transceiver U9 extend to connector P2A with galvanic separation Jumper Setting Description closed Input at opto coupler U3 on the Carrier Board connected to CAN1_TX signal from the phyCORE MPC5200B I O JP5 closed Output at opto coupler U4 on the Carrier Board connected to CAN1_RX signal of the phyCORE MPC5200B 1 O Table 16 Jumper Configuration for CAN Plug P2A using the CAN Transceiver on the Carrier Board 5 t 8 3 3 GND Carrier Board Ground 7 Pin 7 CAN with galvanic separation 2 Pin 2 CAN_L1 with galvanic separation 6 Pin 6 GND Carrier Board Ground Figure 19 Pin Assignment of the DB 9 Plug P2A CAN Transceiver on Carrier Caution Board When using the DB 9 connector P2A as CAN interface and the CAN transceiver on the Carrier Board the following jumper settings are not functional and could damage the module Jumper Setting Description JP4 open CAN1 signal not connected to transceiver CAN communication possible JP5 open CAN1_RX signal not connected to transceiver no CAN communication possible Table 1
40. the Carrier Board at the expansion bus connectors These modular expansion boards offer supplemental functions 6 as well as peripheral support devices for specific functions offered by the controller populating the SBC module 9 mounted on the Carrier Board e All controller and on board signals provided by the SBC module mounted on the Carrier Board are broken out 1 1 to the expansion board by means of its patch field 7 The required connections between SBC module Carrier Board and the expansion board are made using patch cables 8 included with the expansion board Figure 11 illustrates the modular development platform concept PHYTEC Messtechnik GmbH 2008 L 694e 1 47 phyCORE MPC5200B 1 O Figure 11 Modular Development and Expansion Board Concept with the phyCORE MPC5200B I O The following sections contain specific information relevant to the operation of the phyCORE 5200 mounted the phyCORE Development MPC5200B 1 O 48 PHYTEC Messtechnik GmbH 2008 L 694e 1 5200 on the Carrier Board 14 2 Carrier Board phyCORE MPC5200B 1 O Connectors and J umpers 14 2 1 Connectors As shown in Figure 12 the following connectors are available on the phyCORE Development PCM 973 1 phyCORE connector for phyCORE module with 400 pins e g phyCORE MPC5200B 2 phyCORE connector for phyCORE module with 200 pins e g phyCORE MPC5200B tiny X3 400 pin matin
41. the pin layout of the phyCORE connector is provided to identify signals on the Expansion Bus connector X3 on the Carrier Board as well as the patch field However the numbering scheme for Expansion Bus connector and patch field matrices differs from that of the phyCORE connector as shown in the following two figures Figure 21 Pin Assignment Scheme of the Expansion Bus PHYTEC Messtechnik GmbH 2008 1 694 1 63 phyCORE MPC5200B 1 O ABCDEF Figure 22 64 Pin Assignment Scheme of the Patch Field PHYTEC Messtechnik GmbH 2008 L 694e_1 5200 on the Carrier Board assignment on the 5200 conjunction with the Expansion Bus on the Carrier Board and the patch field on an expansion board is as follows Signal phyCORE Module Expansion Bus Patch Field Ext_ADO 100B 99A X15 25 Ext_AD1 100A 98B X13 25 Ext_AD2 99A 98A X14 25 Ext_AD3 98B 97B X12 25 Ext_AD4 98A 96A X17 24 Ext_AD5 97B 96B X11 25 Ext_AD6 96B 95 16 24 Ext_AD7 96A 95B X10 25 Ext_AD8 95 93 13 24 Ext_AD9 94A 93A X14 24 Ext_AD10 93B 91B X11 24 Ext_AD11 93A 91 17 22 Ext_AD12 92B 90B X10 24 Ext_AD13 91B 90A X16 22 Ext_AD14 91 88 13 22 Ext_AD15 90B 89A X15 22 Ext_AD16 83B 83A X14 21 Ext_AD17 83A 78B X1
42. 1 9 phyCORE MPC5200B 1 O Comments sa pi Ground 0 V 17 22 27 2 37A 42 47 52 57 62A 67A 72 77A 82 87 3 LocalPlus Bus control signals CS1 Chip Select 1 LP ALE Address Latch Enable OE Output enable LP LP Bus Acknowledge Misc Signals Test Sel 1 Test Sel 1 signal of the MPC5200B Input in CPU production test Can be configured as LocalPlus Bus TSIZ bit Refer to section 7 3 2 1 1 in the MPC5200 controller User s Manual Timer 7 Signal of MPC5200B Timer7 FPGA IO Signals FPGA B2 D8 FPGA B2 A7 FPGA B2 B7 FPGA B2 D6 FPGA B2 C6 FPGA B2 A6 FPGA B2 B6 FPGA B2 A4 FPGA B2 B4 FPGA B2 A3 FPGA B2 B3 FPGA B2 D1 FPGA B1 D3 FPGA B1 D5 FPGA B1 E1 FPGA B1 FPGA B1 F3 FPGA B1 G4 FPGA B1 H1 10 PHYTEC Messtechnik GmbH 2008 L 694e 1 Pin Description Comments FPGA IO Signals FPGA JTAG Interface FPGA_TDO n Test Data out Test Data LocalPlus Address Data Signals FPGA_TDI EXT_AD31 EXT_AD29 EXT_AD28 EXT_AD26 EXT_AD23 EXT_AD22 EXT_AD20 EXT_AD17 EXT_AD14 EXT_AD11 EXT_AD9 EXT_AD8 EXT_AD7 EXT_AD4 EXT_AD2 EXT_AD1 ATA Interface Signals Timer Port configured as ATA CS Timer Port configured ATA_CS ATA negated to extend transfer ATA read ATA interrupt request Dedicated PCI Signals Reset output open drain Bus grant Command byte enable 3 Command byte enable 2 Initiator HOST
43. 10 LP_CS4 B4 T11 LP_ALE 4 11 OE 4 19 LP_RD WR 110 LP_ACK B4 R10 LP_TS 10 EXT B4 K11 _ 1 4 10 EXT 4 12 EXT AD3 B4 P13 EXT AD4 B4 T12 EXT AD5 B4 R12 EXT AD6 B4 T13 EXT 07 B4 R13 EXT AD8 T14 EXT B4 R14 EXT AD10 B4 M11 EXT AD11 L11 EXT AD12 B4 N11 EXT AD13 P11 EXT 014 B4 T3 EXT AD15 B4 R3 EXT AD16 B4 P5 EXT 017 B4 P4 EXT AD18 T4 EXT AD19 B4 R4 EXT AD20 B4 T5 EXT AD21 B4 R5 EXT AD22 B4 7 EXT 023 B4 R7 EXT AD24 B4 L7 EXT AD25 B4 L8 EXT AD26 B4 T8 EXT AD27 B4 R8 EXT AD28 B4 T9 EXT AD29 B4 R9 EXT AD30 B4 N8 EXT AD31 B4 T6 Table 11 Signal Connection between MPC5200B and FPGA Pins 34 PHYTEC Messtechnik GmbH 2008 L 694e 1 On board FPGA 8 2 FPGA Configuration Interface The phyCORE MPC5200B I O provides two options for configuring the FPGA Jumper 48 which is used to configure the FPGA s serial programming interface is used to select the different options refer to section 3 for more details 8 2 1 Configuration via Processor GPIO Interface The phyCORE MPC5200B I O offers the capability of configuring the FPGA over the processor s GPIO signals In order to use this method the FPGAs configuration interface must be connected with the applicable GPIO signals on the processor The analog multiplexer IC at U17 is provided to accomplish this task In addition Jumper J11 on the module allows fixed or flexible
44. 2 63 63C X5 16 _ 2_ 12 64 64 7 16 2 14 65 65 8 16 _ 2_ 12 650 650 9 16 _ 2_ 14 66 66 2 17 FPGA_B2_C13 600 660 X3 17 FPGA_B2_A13 67D 67D X4 17 2 680 680 6 17 FPGA B2 D7 68C 68 5 17 FPGA_B3_C14 69C 69C X7 17 15 70 70 8 17 FPGA B3 C16 70D 70D X9 17 FPGA B3 D13 71C 71C X2 19 FPGA B3 D14 71D 71D X3 19 FPGA B3 D15 72D 72D X4 19 FPGA B3 D16 73C 73C X5 19 FPGA B3 E13 73D 73D X6 19 FPGA B3 E14 74C 74C X7 19 FPGA B3 E15 75C 75C X8 19 PHYTEC Messtechnik GmbH 2008 94 1 71 phyCORE MPC5200B 1 O Signal phyCORE Module Expansion Bus Patch Field FPGA_B3_E16 75D 75D X9 19 FPGA_B3_F13 76C 76C X2 20 FPGA_B3_F14 76D 76D X3 20 FPGA B3 F15 77D 77D X4 20 FPGA F16 78C 78C X5 20 FPGA 12 780 780 6 20 FPGA 13 79 79 7 20 FPGA 15 80 80 X8 20 FPGA_B3_G16 80D 80D X9 20 FPGA_B3_H11 81C 81C X2 21 FPGA_B3_H12 81D 81D X3 21 FPGA_B3_H13 82D 82D X4 21 FPGA_B3_H15 83C 83C X5 21 FPGA_B3_J11 83D 83D X6 21 FPGA_B3_J12 84C 84C X7 21 FPGA_B3_J15 85C 85C X8 21 FPGA_B3_J16 85D 85D X9 21 FPGA_B3_K13 86C 86C X2 22 FPGA_B3_K15 86D 86D X3 22 FPGA B3 K16 87D 87D X4 22 FPGA B3 L12 88C 88C 5 22 FPGA B3 114 88D 88D X6 22 FPGA B3 L15 89C 89C 7 22 116 90
45. 21 Pci Trdy 86B 85A X16 21 Pci Stop 87B 86A X17 21 Pci Perr 88A 85B X10 22 Pci Par 88B 88A X14 22 Pci_Serr 89A 86B X11 22 Pci_Cbe_1 90A 87B X12 22 0 95 94 15 24 Table 29 Pin Assignment PCI dedicated signals phyCORE MPC5200B 1 O Carrier Board Expansion Board Signal phyCORE Module Expansion Bus Patch Field ATA Isolation 67B 61B X11 16 ATA lor 68A 65A X16 16 ATA Dack 68B 62B X12 16 ATA intrq 69A 66A X17 16 51 65 14 16 658 588 13 15 50 4 61 17 15 lochrdy 66 64 15 16 ATA_low 66B 60B X10 16 Table 30 Pin Assignment Dedicated Interface Signals phyCORE MPC5200B 1 O Carrier Board Expansion Board 66 PHYTEC Messtechnik GmbH 2008 L 694e 1 5200 on the Carrier Board Signal phyCORE Module Expansion Bus Patch Field AC97 1 In 16 1 0 AC97_1_Sdata_O 15D __ 97 1 Res 13C li o ___ 97 1 14 ____ ____ 97 1 15 __ ____ TXD6 232 23C 23C X5 6 RXD6 232 21C 21C X2 6 UART6_TXD_TTL 20C 20C X8 5 UART6_RXD_TTL 19C 19C X7 5 UART6_RTS_TTL 24C 24C X7 6 UART6_CTS_TTL 25C 25C X8 6 RXD3 2
46. 3 20 Ext_AD18 82B 81A X17 20 Ext_AD19 81B 77B X12 20 Ext_AD20 81A 80A X16 20 Ext_AD21 80B 76B X11 20 Ext_AD22 80A 79 15 20 Ext_AD23 79 75 10 20 Ext_AD24 77B 78A X14 20 Ext_AD25 76B 72B X12 19 Ext_AD26 76A 75A X16 19 Ext_AD27 75B 71B X11 19 Ext_AD28 75A 74 15 19 Ext_AD29 74A 70B X10 19 Ext_AD30 73B 73A X14 19 Ext_AD31 73A 68B X13 17 Table 27 Pin Assignment Data Address Bus for the phyCORE MPC5200B 1I O Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2008 1 694 1 65 phyCORE MPC5200B 1 O Signal phyCORE Module Expansion Bus Patch Field CS1 5A 5A X16 1 CS2 35B 35B X10 10 5B 5B X10 2 Cs4 6 X11 2 Cs5 36B 36B X11 10 Cs6 47B 47B X12 12 Cs7 48B 48B X13 12 Ts 33B 33B X13 9 LP Ack 34A 34A X15 9 Ale 6A 6A X17 1 Oe 8A 8A X14 2 LP RD WR 7B 7B X12 2 Table 28 Pin Assignment Dedicated LocalPlus Control Signals phyCORE MPC5200B 1 O Carrier Board Expansion Board Signal phyCORE Module Expansion Bus Patch Field Pci Reset 70A 70A X16 17 Pci Clock 70B 66B X11 17 Pci Gnt 71A 71A X17 17 Pci Req 72B 67B X12 17 Cbe 3 78A 738 13 19 Pci 788 76 17 19 2 84 80 10 21 85 81 11 21 Pci Frame 85B 84A X15 21 Pci Devsel 86A 82B X12
47. 32 22D 22D X4 6 TXD3 232 23D 23D X6 6 UART3_TXD_TTL 17D 17D X4 5 UART3_RXD_TTL 16D 16D X3 5 UART3_RTS_TTL 25D 25D X9 6 UART3_CTS_TTL 26D 26D X3 7 CAN1_TX 21D 21D X3 6 CAN1_RX 20D 20D X9 5 2 18 18 5 5 180 180 X6 5 12 1_ 31C 31C X2 9 1261 lo 320 320 4 9 2 2 26 26 2 7 2 2 lo 28 28 5 7 SPI Mosi 27D 27D X4 7 SPI Miso 28D 28D X6 7 SPI 30D 30D X9 7 SPI Ss 31D 31D X3 9 ETH_RX 35C a ____ ____ ____ _ 35D E 36 __ ____ 360 __ ____ ____ E 37 li x h cEC Ij ETH LINK 33C __ ETH SPEED 34C 7 db X 1 ETH PD 38C __ ____ USB1 Oe 50C USB1 TXP 48D __ _ ud USB1 TXN 49C u USB1 RXD 46D USB1 RXP 47D 5550 _ USB1_RXN 48C __ ____ USB1 Suspend 46C __ USB1 PortPwr 43D 8 S USB1_Overcnt 45C 4 20 OOo ee USB1_Speed 45D x ee Table 31 Pin Assignment Interfaces for the phyCORE MPC5200B O Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2008 L 694e 1 67 phyCORE MPC5200B 1 O phyCORE Module Expansion Bus Patch Field CPU_TCK 38D gt COP_TRST 39C ___ 400 ___ 410 __ 5 42 3 E cm CK STOP 40C C _____
48. 3V3 using a battery backup circuit MAX6364 serves as supply voltage for the Real Time Clock and for the SRAM circuit 16 PHYTEC Messtechnik GmbH 2008 L 694e_1 Pin Description Comments 100 PorReset Reset input signal of the MPC5200B I O It could be 8 1 asserted via connection to a reset push button Signal connected to 3V3 10 kOhm pull up resistor D 00 GPIO WKUP 7 Dedicated GPIO with wakeup capability 5D D 12D Timer2 Timer 2 signal of the MPC5200 13D Timer3 Timer signal of the MPC5200 97 codec signal PSC1 1 AC97 1 SDATA O E AC97 serial data output UT 16D UARTS RXD TTL PSC3 receive data signal 17D UART3 TXD TTL PSC3 transmit data signal CAN2_RX receive of the second CAN interface PSC2 CAN1_RX receive of the first CAN interface PSC2 O CAN interface PSC2 AN1 TX AN transmit of the first CAN interface PSC2 22D RXD3 232 RxD input on the RS 232 transceiver for UART3 2503 TXD3 232 TxD output on the RS 232 transceiver for UART3 2503 250 UART3 RTS TTL 5 request to send signal 26D UART3 CTS TTL PCS3 clear to send signal SPI Interface PSC3 SPI MOSI SPI master out slave in SPI MISO SPI master in slave out SPI CLK SPI clock 3 SPI SS SPI slave select 32D 33D IRQ Interrupt from the on board RTC 05 Interrupt be programmed to
49. 48 398 248 29 348 398 6 8 6 13 6 18 44 498 548 598 448 498 548 598 6 23 7 3 7 8 64 69 718 748 64 69 74 79 7 13 7 18 7 23 79 84 89 94 848 89 94 99 8 3 8 8 8 13 99 8 18 8 23 9 3 7 12 17 7 12 17 9 8 9 13 9 18 22C 27C 32C 37 22C 27C 32C 37C 9 23 10 3 X10 42C 47C 52C 57 42C 47C 52C 57C 8 X10 13 X10 18 62C 67C 72C 77C 62C 67C 72C 77C X10 23 X11 3 X11 82C 87C 92C 97C 82C 87C 92C 97C 8 X11 13 X11 18 3D 9D 14D 19D 3D 9D 14D 19D X11 23 X12 3 X12 24D 29D 34D 39D 240 29D 34D 39D 8 X12 13 X12 18 44D 49D 54D 59D 44D 49D 54D X12 23 X13 3 X13 64D 69D 74D 79D 590 64D 69D 740 8 X13 13 X13 18 84D 89D 94D 99D 790 84D 89D 94D X13 23 X14 3 X14 99D 8 X14 13 X14 18 X14 23 X15 3 X15 8 X15 13 X15 18 X15 23 X16 3 X16 8 X16 13 X16 18 X16 23 X17 3 X17 8 X17 13 X17 18 X17 23 Table 35 Pin Assignment Power Supply for the phyCORE MPC5200B I O Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2008 1 694 1 73 phyCORE MPC5200B 1 O Signal Module Expansion Bus Patch Field N C 1A 100D 15 16 35C 36C X8 4 X2 5 X8 9 38 39C 40C 45C X2 10 X5 10 X7 46C 48C 49C 50C 10 X8 10 X8 11 36D 37D 38D
50. 7 Improper Jumper Settings for the CAN Plug CAN Transceiver on PHYTEC Messtechnik GmbH 2008 the Carrier Board L 694e_1 57 phyCORE MPC5200B 1 O 14 35 Second CAN Interface at Plug P2B Plug P2B is the upper plug of the double DB 9 connector at P2 P2B is connected to the second CAN interface CAN2 of the phyCORE MPC5200B I O via jumpers There are no CAN transceivers available the phyCORE MPC5200B I O therefore the transceivers on the Carrier Board must be used Depending on the configuration of the CAN transceivers and their power supply the following configuration is possible 1 CAN signals generated by the Carrier Board CAN transceiver 010 extend to connector P2B with galvanic separation Jumper Setting Description JP6 closed Input at opto coupler U5 on the Carrier Board connected to CAN2_TX signal from the phyCORE MPC5200B 1 O JP7 closed Output at opto coupler 06 on the Carrier Board connected to 2 RX signal of the phyCORE MPC5200B l O Table 18 Jumper Configuration for CAN Plug P2B using the CAN Transceiver on the Carrier Board HD200 Pin 3 GND Carrier Board Ground Pin 7 CAN 2 no galvanic separation Pin 2 CAN L2 no galvanic separation Pin 6 GND Carrier Board Ground ON co o 5 4 3 2 1 Figure 20 Pin Assignment of the DB 9 Plug P2B CAN Transceiver Carrier Board Caution When using the DB 9 connector P2B as second CAN interface and
51. HYTEC Messtechnik GmbH 2008 L 694e 1 Technical Specification The height of all components on the top side of the PCB is ca 2 5mm The PCB itself is approximately 1 6 mm thick The Molex connector pins are located on the underside of the PCB oriented parallel to its two long sides The maximum height of components on the underside of the PCB is 3 0 mm Additional Technical Data Parameter Condition Characteristics Dimensions 84 mm x 53 mm Weight approximately 30g with all optional components mounted on the circuit board Storage Temp Range 40 C to 90 Operating Temp Range Extended 25 C to 85 C Humidity max 95 RH not condensed Operating voltages 3 3V supply voltage 3 3 V 45 Operating Power Consumption depending on load 3 3V supply voltage Max 3 3 watts Table 13 Technical Data These specifications describe the standard configuration of the phyCORE MPC5200B I O as of the printing of this manual PHYTEC Messtechnik GmbH 2008 94 1 43 phyCORE MPC5200B I O Connectors on the phyCORE MPC5200B 1 O Manufacturer Molex Number of pins per contact rows 200 2 rows of 100 pins each Molex part number lead free 52760 1009 receptacle Two different heights are offered for the receptacle sockets that correspond to the connectors populating the underside of the phyCORE MPC5200B I O The given connector height indicates the distance between the two connected
52. N 044 for more details 40 PHYTEC Messtechnik GmbH 2008 1 694 1 JTAG Interface 10 J TAG Interface The MPC5200B CPU provides a JTAG interface for connecting to debuggers emulators and boundary scan The JTAG interface signals extend to the module s phyCORE connector Furthermore there is an on board JTAG connector X1 located at the edge of the module which has the standard COP Interface pinout but uses a 2 0 mm pin pitch instead of 2 54 mm The connector is not populated on the standard version of the phyCORE MPC5200B I O You can order a specific debug version of the module denoted by the part number extension or populate 2 8 pin header connector at space X1 The numbering scheme is depicted on the phyCORE MPC5200B I O The pinout of the JTAG interface at X1 is described in the following table Signal PinRow Signal Bottom Top TDO 1 2 NC quack TDI 3 4 TRST NC halted 5 6 3 3 TCK 7 8 TMS 9 10 SReset 11 12 GND HReset 13 14 NC key CK_Stop 15 16 GND Table 12 TAG Interface X1 PHYTEC Messtechnik GmbH 2008 L 694e 1 41 phyCORE MPC5200B 1 O 11 Technical Specifications The physical dimensions of the phyCORE MPC5200B I O are represented in Figure 10 HE wi 3 6nm 81 0 0 635nm 4 751 11 2 T 3 25 21 69nm 14 21 31nm Figure 10 Physical Dimensions Top View 42 P
53. PEED indication are integrated in the connector Two additional LEDs at D19 and D20 are provided to allow display of other Ethernet transmission states These LEDs can be used to indicate transmission type and possible collisions that may occur on the Ethernet network Jumpers JP8 and JP9 allow configuration of additional Ethernet PHY interface signals The following configuration options are possible Jumper Setting Description JP8 open ETH INT from PHY on the phyCORE MPC5200B 1 O not connected closed ETH INT from PHY on the phyCORE MPC5200B I O connected to IRQ1 on the phyCORE module JP9 open PHY transceiver ETH PD input on the phyCORE MPC5200B I O not connected 1 2 PHY transceiver ETH PD input the phyCORE MPC5200B I O connected to SPI MISO signal on the phyCORE module 2 3 PHY transceiver ETH PD input the 5200 connected to GPIO7 signal on the phyCORE module Table 21 JP8 J P9 Ethernet Interface Configuration PHYTEC Messtechnik GmbH 2008 1 694 1 59 phyCORE MPC5200B 1 O 14 3 8 USB Host Interface P1B The USB Host interface of the phyCORE MPC5200B I O is accessible at connector on Carrier Board This interface is compliant with USB version 1 1 and its mode can be configured with the help of Jumper JP2 The following configuration options are possible Jumper Setting Description JP2 open VMO mode selected closed FSEO mode select
54. Table 33 Pin Assignment Misc Control Signals for the phyCORE MPC5200B 1 O Carrier Board Expansion Board PHYTEC Messtechnik GmbH 2008 1 694 1 69 phyCORE MPC5200B 1 O phyCORE Module Expansion Bus Patch Field FPGA TDO 61A Ro c el FPGA TMS 62B cou FPGA TDI 63A ___ ____ _ 638 ____ FPGA B1 C1 31B 31B X11 9 FPGA B1 C2 32B 32B X12 9 FPGA 1 33A 33A X14 9 FPGA B1 D2 37B 37B X12 10 FPGA B1 03 38A 38A X14 10 FPGA B1 D4 38B 38B X13 10 FPGA B1 D5 39A 39A X15 10 FPGA B1 E1 40A 40A X16 10 FPGA B1 E2 40B 40B X10 11 FPGA B1 41A 41A X17 10 FPGA B1 E4 41B 41B X11 11 FPGA B1 E5 42B 42B X12 11 FPGA 43A 43A X14 11 FPGA B1 F5 43B 43B X13 11 FPGA B1 G4 44A 44A X15 11 FPGA 45A 45A X16 11 FPGA B1 H6 45B 45B X10 12 FPGA B1 J1 46A 46A X17 11 FPGA B1 J2 46B 46B X11 12 FPGA B1 J4 48A 48A X14 12 FPGA B1 J6 49A 49A X15 12 FPGA B1 K1 50A 50A X16 12 FPGA B1 K2 50B 50B X10 14 FPGA B1 K4 51A 51A X17 12 FPGA B1 K5 51B 51B X11 14 FPGA B1 L1 52B 52B X12 14 FPGA B1 L2 53A 53A X14 14 FPGA B1 L3 53B 53 13 14 14 54 54 15 14 FPGA B1 1 55A 55A X16 14 FPGA B1 M2 55B 55B X10 15 FPGA 56A 56A X17 14 FPGA B1 M4 56B 56B X11 15 FPGA B1 1 57B 57B X12 15 FPGA B1 N2 58A 58A X14 15
55. Transmit Data Output 2 Misc Signals 60C Timer 6 Signal MPC5200B 61C Timer4 Timer 4 Signal of MPC5200B PHYTEC Messtechnik GmbH 2008 L 694e_1 15 phyCORE MPC5200B 1 O Pin Number Number Signal Comments FPGA IO Signals 63C FPGA_B2_A12 64 _ 2_ 12 65 _ 2_ 14 66 2 14 68 FPGA_B2_D7 69 14 70 15 71 FPGA D13 73 016 74C FPGA E14 75 15 76 13 78 16 79 FPGA G13 80C FPGA_B3_G15 81 _ _ 11 83 15 84 FPGA 412 85 FPGA 415 86 88 112 89 115 90C FPGA_B3_L16 91 14 93C FPGA_B3_N12 94 16 95 14 96 16 98 FPGA 6 99 100 FPGA B4 R6 Pin Row X1D 1D 2D _ Supply voltage 3 3 VDC 3D 9D 14D GND Ground 0 V 19D 24D 29D 34D 39D 44D 49D 54D 59D 64D 69D 74D 79D 84D 89D 94D 99D 4D 5D FPGA_VCCIO Optional IO Voltage for FPGA Banks 1 2 and B VCC_SRAM supply voltage is generated by VBAT or
56. V3 25 ALTERA EP2C8 FPQA 33 Audio 60 Audio Interface 60 74 Battery Connector 74 Boot 36 Carrier Board Connectors 49 CF Socket 61 GE payakuna 61 CF Write 61 Concept of the Carrier Board 47 s 61 RETE 61 ona sona 59 DY OASE a tere O 59 DDR SDRAM 3 27 28 DIP Switch S3 62 EEPROM 27 EEPROM serial 29 EMG u m yaaa 1 1 Ethernet Interface 31 59 Ethernet PHY 59 Expansion Bus 63 78 Fast Ethernet Controller 31 2 FREG 31 First CAN Interface 57 First Serial Interface 55 cat eens 3 27 Start Address 28 Flash Access Time 28 Flash Memory 27 33 FPGA Configuration 35 FPGA JTAG Con
57. YY YYYYYY Y Tal B Cio 2 a 3 Figure 12 Location of Connectors on the phyCORE MPC 5200B I O Carrier 50 Board PHYTEC Messtechnik GmbH 2008 L 694e 1 5200 on the Carrier Board Please note that all module connections not to exceed their expressed maximum voltage current Maximum signal input values are indicated in the corresponding controller User s Manual Data Sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals 14 2 2 Jumpers on the Carrier Board phyCORE 5200 1 Peripheral components of the phyCORE MPC5200B I O Carrier Board can be connected to signals of the phyCORE MPC5200B 1 O by setting the applicable jumpers The Carrier Board s peripheral components are configured for use with the phyCORE MPC5200B I O by means of removable jumpers If no jumpers are set no signals connect to the DB 9 connectors the control and display units and the CAN transceivers The Reset input on the phyCORE 5200 directly connects to the Reset button S1 Figure 13 illustrates the numbering of the jumper pads while Figure 14 indicates the location of additional jumpers on the Carrier Board z B JP28 z B JP23 2 24
58. at only appropriately trained personnel such as electricians technicians and engineers handle and or operate these products Moreover PHYTEC products should not be operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Conformity only in accordance to the descriptions and rules of usage indicated in this hardware manual particularly in respect to the pin header rows or connectors power connector and serial interface to a host PC Implementation of PHYTEC products into target devices as well as user modifications and extensions of PHYTEC products is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives Users should ensure conformance following any modifications to the products as well as implementation of the products into target systems phyCORE MPC5200B I O is one of a series of PHYTEC Single Board Computers that can be populated with different controllers and hence offers various functions and configurations PHYTEC supports common 8 16 and numerous 32 bit controllers on two types of Single Boards Computers 1 the basis for Rapid Development Kits which serve as a reference and evaluation platform 2 gt insert ready fully functional phyCORE OEM modules which can be embedded directly into the user s target design PHYTEC
59. broadcast photomechanical or similar reproduction and storage or processing in computer systems in whole or in part are reserved No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH EUROPE NORTH AMERICA Address PHYTEC Technologie Holding AG PHYTEC America LLC Robert Koch Str 39 203 Parfitt Way SW Suite D 55129 Mainz G100 GERMANY Bainbridge Island WA 98110 USA Ordering 49 800 0749832 1 800 278 9913 Information order phytec de sales phytec com Technical 49 6131 9221 31 1 800 278 9913 Support support phytec de support phytec com Fax 49 6131 9221 33 1 206 780 9135 Web Site http www phytec de http www phytec com Edition April 2008 PHYTEC Messtechnik GmbH 2008 1 694 1 Contents fe 1 DEED MP 2 1 1 ee SBI Pt 4 1 2 View of the phyCORE MPC5200B l O 5 1 8 Minimum Requirements to Operate the phyCORE MPC5200B I O 7 2 ees 8 lol EC 19 4 PowerHedgulrements u 24 4 1 Voltage Supervision and 25 5 System Start Up Configuration 26 6 System Memory
60. bus clocks of wait state 1 48 PCI bus clocks of wait state ETH boot rom swap E Bit 0 no byte lane swap same endian ROM image Bit 1 byte lane swap different endian ROM image ETH_TXERR boot_rom_size 1 Boot ROM address is max 25 significant bits during address tenure Bit 0 16 bit ROM data bus Bit 1 32 bit ROM data bus ETH MDC boot rom type 1 0 non muxed boot ROM bus single tenure transfer 1 muxed boot ROM bus with address and data tenures ALE and TS active ETH TXDO large flash sel p Bit 0 boot in large Flash mode 1 Bit 1 Boot in large Flash mode 1 3 4 Table 4 System Start Up Configuration Note Since most of these signal lines are routed to the phyCORE connector care must be taken not to overwrite the startup configuration accidentally when connecting these signals to external devices 26 PHYTEC Messtechnik GmbH 2008 L 694e 1 System Memory 6 System Memory The standard system memory consist of Flash memory DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory and a small non volatile memory device In addition to the standard memory configuration it is possible to populate a battery backed SRAM with 16 bit data bus width 32 MByte Intel Strata Flash memory 2x 16 bit multiplexed mode 64 MByte DDR SDRAM 2x 16 bit 4 kByte serial memory EEPROM optionales bis zu 2MByte 16 bittiges batteriepufferbares RAM The Flash memory is connected to th
61. dress 0x51 PHYTEC Messtechnik GmbH 2008 1 694 1 37 phyCORE MPC5200B 1 O 9 2 System Resources Required by U Boot U Boot is located at address OxFFFO 0000 in the module s Flash and occupies two sectors 2x 128kByte The boot loader itself makes sure that these sectors are protected using the Flash s locked sector mechanism This makes accidental erasure of U Boot almost impossible Following a system start at address OxFFFO 0100 high boot U Boot first initializes the DDR RAM interface then copies itself to the upper end of the RAM memory space and transfers program execution to this address As a result U Boot now runs out of RAM which allows for reprogramming itself in Flash firmware update So called environment variables are used to configure U Boot Such variables define the IP number as well as the MAC address using Ethernet configuration as example The variables are saved in the module s EEPROM 04 and occupy the first 2 kByte When using the RAM memory care should be taken to not overwrite the U Boot code as well as the trap table which is located in the lower portion of the RAM Among other factors the size of the U Boot stack determines how much memory at the upper end of the RAM memory range is occupied by U Boot As U Boot is used the stack size is growing and more memory space is required It is recommended to reserve a sufficient RAM portion to be used for the stack beginning at the stack start address 9 2 1 The
62. e SMD 0805 J8 configures the FPGA configuration mode Please refer to the corresponding FPGA Data Sheet for more detailed information The FPGA configuration mode is set to Passive Serial Mode PS Mode This allows loading the FPGA firmware through a controller interface In this configuration external FPGA configuration EEPROM is not required The FPGA configuration mode is set to Active Serial Mode AS mode In order to use this configuration an external FPGA configuration EEPROM is required at U18 from which the functional implementation can be loaded into the FPGA _____ 47 49 10 Each of these jumpers configures the voltage of the corresponding freely available FPGA I O banks Please refer to the corresponding FPGA Data Sheet for more detailed information about the I O bank voltages 1 2 X voltage of the corresponding FPGA bank set 3V3 supply voltage 243 voltage of the corresponding FPGA bank supplied by an external source through the FPGA VCCIO input Package Type OR in SMD 0805 22 PHYTEC Messtechnik GmbH 2008 L 694e 1 Jumpers Jumper Default Comment J11 J11 configures the use of the PSC6 signals from the MPC5200B Please refer to the corresponding controller Data Sheet for more detailed information 1 2 X The GPIO6 signal is connected to the select input of the multiplexer IC at U17 This allows configuration of the PSC6 signals
63. e PowerPC LocalPlus bus and is controlled by CSO This Chip Select signal is used for boot operation The DDR SDRAM is connected to the special SDRAM interface of the MPC5200B processor and operates at the maximum frequency 132 MHz Communication to the small non volatile memory device is established over the processor s C bus This memory device holds the boot loader U Boot environment variables in its first two kilobytes and can be used for parameter storage The size of the optional battery backed SRAM can be up to 2 MByte This SRAM device at U11 is connected to the MPC5200B LocalPlus bus using 16 bit data bus with access controlled by the CS2 signal 6 1 Flash Memory Use of Flash as non volatile memory on phyCORE MPC5200B l O provides an easily reprogrammable means of code storage e 32 MByte Intel Strata Flash memory 32 bit bus width Only asynchronous operation is possible The Flash memory bank at U9 and U10 supports the following Intel memory devices Type Size Manufacturer Device Code Manufacturer Code Asynchronous Devices 2 28F128J 2 16 MByte Intel 0x0018 0x0089 3 2 28F256P 2 32MByte Intel 33 Table 5 Choice of Flash Memory Devices and Manufacturers 1 Flash types in the shaded lines are the preferred parts for the phyCORE MPC5200B 1 O PHYTEC Messtechnik GmbH 2008 1 694 1 27 phyCORE MPC5200B 1 O The organization of the Flas
64. econd RS 232 Front VIeW W 56 Pin Assignment of the DB 9 Plug 2 CAN Transceiver Carrier seio T 57 Pin Assignment of the DB 9 Plug P2B CAN Transceiver on Garer B atd 58 Pin Assignment Scheme of the Expansion Bus 63 Pin Assignment Scheme of the Patch Field 64 PHYTEC Messtechnik GmbH 2008 1 694 1 phyCORE MPC5200B 1 O Figure 23 phyCORE MPC5200B l O Component Placement Top View 76 Figure 24 phyCORE MPC5200B l O Component Placement Bottom View 77 Index of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Default Port Configuration is 8 Pinout of the phyCORE Conne ctor X1 18 J mper Settings u ua pc ae a 23 System Start Up Configuration 26 Choice of Flash Memory Devices and Manufacturers 27 DDR SDRAM Device Selection 28 Serial Memory Options for 025 29 Serial Memory Address Examples
65. ection 0 The Real Time Clock also provides an interrupt output that extends to the IRQRTC signal X1D33 An interrupt occurs in the event of a clock alarm timer alarm timer overflow and event counter alarm It has to be cleared by software With the interrupt function the Real Time Clock can be utilized in va rious applications If the RTC interrupt is to be used as a software interrupt via a corresponding interrupt input of the processor the signal IRQRTC must be connected externally with a processor interrupt input The RTC_CLKOUT signal can be programmed to various frequencies e g 1Hz The RTC_CLKOUT output must be enabled via solder jumper J12 For more information on the features of the RTC 8564 refer to the corresponding Data Sheet Note After connection of the supply voltage the Real Time Clock generates no interrupt The RTC must first be initialized see RTC Data Sheet for more information 46 PHYTEC Messtechnik GmbH 2008 L 694e_1 5200 on the Carrier Board 14 The phyCORE MPC5200B 1I O on the Carrier Board PHYTEC Carrier Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start up and subsequent communication to and programming of applicable PHYTEC Single Board Computer SBC modules Carrier Boards are designed for evaluation testing and prototyping of PHYTEC Single Board Computers in laboratory environments prior to their use
66. ector circuit PHYTEC Messtechnik GmbH 2008 L 694e 1 25 phyCORE MPC5200B 1 O 5 System Start Up Configuration During the reset cycle the MPC5200B processor reads the state of selected controller signals to determine the basic system configuration The configuration circuitry pull up or pull down resistors is located on the phyCORE module The system start up configuration includes e Clock configuration e Basic LocalPlus characteristic for boot memory configuration The following default configuration is read by the processor with the rising edge of the reset line PorReset The logic level of the signals written in italic style could be configured via solder jumpers on board refer to section 3 Signal Name Register Bit Logic Description Level LP_Ale 0 Bus clock ratio XLB core clock 1 3 LP_RD WR 0 4 1 132 MHz 3 396 MHz ATA_low 0 ATA_lor 0 ATA_Dack 0 LP_Ts xlb clk sel Bit 0 XLB_CLK fsystem 4 Bit 1 XLB_CLK fsystem 8 USB1_TXN Sys 0 E Bit 20 fsystem 16x SYS XTAL IN 1 fsystem 12x SYS XTAL IN USB1 TXP Sys cfg1 Bit 0 fvcosys fsystem Bit 1 fvcosys 2 x fsystem ETH_TXEN boot_rom_mg Bit 0 boot in most graphics mode 1 Bit 1 Boot in most graphics mode ETH_TXD1 ppc_msrip 1 Bit 0 0000_0100 hex boot address Bit 1 FFFO_0100 hex boot address ETH TXD2 boot rom wait 1 0 4 PCI
67. ed Table22 JP2 USB Host Interface Configuration A second USB connector is porvided at P1C However this connector does not carry any USB communication signals Connector P1C can only be used to access the USB supply voltage 14 3 9 Audio Interface The AC97 interface on the phyCORE MPC5200B lI O connects to a Wolfson WM9712 audio codec controller on the Carrier Board A variety of signals gerenated by the WM9712 IC are available at the following connectors Header X15 Base Speaker Header X18 SPDIF OUT Header X19 Differential Output Header X20 Auxiliary Output Socket P4 MIC1 MIC2 Socket P5 LINE IN R L Socket P6 LINE OUT R L Jumpers JP14 and JP15 are available for configuration of interrupt signals generated by the WM9712 device The following configuration options are possible Jumper Setting Description JP14 open INT signal on WM9712 not used closed INT signal connected to IRQ 2 on the phyCORE MPC5200B l O JP15 open PEN INT signal from WM9712 not used closed PEN INT signal connected to IRQ 3 on the phyCORE MPC5200B l O Table 23 JP14 JP15 97 Audio Interface Configuration 60 PHYTEC Messtechnik GmbH 2008 L 694e 1 5200 on the Carrier Board 14 3 10 Compact Flash Card Socket X10 The phyCORE MPC5200B I O Carrier Board provides a Compact Flash CF card socket at X10 cards used in this socket can only be op
68. ee is voided Integrating the phyCORE MPC5200B I O into a Target Application Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module For best results we recommend using a carrier board design with a full GND layer It is important to make sure that the GND pins that have neighboring signals which are used in the application circuitry are connected Just for the power supply of the module at least 6 GND pins that are located right next to the VCC pins must be connected PHYTEC Messtechnik GmbH 2008 94 1 45 phyCORE MPC5200B 1 O 13 Real Time Clock RTC 8564 U5 For real time or time driven applications the phyCORE MPC5200B I O is equipped with a RTC 8564 Real Time Clock at U24 This RTC device provides the following features e Serial input output bus address 2 e Power consumption Bus active 400 kHz lt 1mA Bus inactive CLKOUT inactive lt 1 Clock function with four year calendar Century bit for year 2000 compliance Universal timer with alarm and overflow indication 24 hour format Automatic word address incrementing Programmable alarm timer and interrupt functions The Real Time Clock is programmed via the bus address 0 2 0xA3 Since the MPC5200B is equipped with an internal controller the protocol is processed very effective without extensive processor action refer also to s
69. erated in IDE mode Activity on the CF card socket is indicated by LED D14 Jumpers J3 and JP11 are available for configuration of the Compact Flash card interface The following configuration options are possible Jumper Setting Description J3 open Not recommended 1 2 Compact Flash write protection active 2 3 Compact Flash card write protection active JP11 open Compact Flash slave mode selected closed Compact Flash master mode selected Table 24 J 3 J P11 CF Card Interface Configuration 14 3 11 IDE Interface 11 The phyCORE MPC5200B I O Carrier Board provides an IDE interface header at X11 for connection to external 2 5 hard disks The 44 pin header connector in 2 0 mm pin spacing allows easy and convenient connection to peripheral devices using a ribbon cable Activity on the IDE socket is indicated by LED D15 14 3 12 PCI Card Slot X4 The phyCORE MPC5200B l O Carrier Board provides 3 3V PCI interface connector at All common 3 3 PCI insert cards can be used in this slot allowing the user to add additional interface features to this hardware platform Configuration of the PCI interface via jumpers is not necessary Only the required interrupt sources can be configured via SMD resistors Resistors R95 R98 on the Carrier Board connect the available interrupts Only R95 is placed as the default configuration connecting INTA with _0 Additional interrupt sources can
70. et is actually an interrupt that takes the same exception vector as HRESET In particular this means that SRESET cannot abort a hung XLB operation and no device should use SRESET in a way that interferes with any bus operation in progress SRESET can also be asserted by internal sources When is asserted internally external SRESET is also asserted 1 HRESET HRESET is a bi directional signal with a Schmitt trigger input and an open drain output The HRESET signal is connected a 10 kOhm pull up resistor on the module Assertion of external HRESET causes external HRESET and SRESET as well as internal hard and Soft resets to be asserted for at least 4096 reference clock cycles During PORRESET or HRESET the reset configuration word is sampled to establish the initial state of various vital internal MPC5200B functions The reset configuration word is latched internally when PORRESET or HRESET is released 97 Codec Signals 5 1 AC97 1 RES Reset signal to the external AC97 device AC97 1 SYNC Frame sync or start of frame SOF AC97 1 BITCLK Driven by the external serial bit clock AC97 1 SDATA IN AC97 serial data input 18C TX CAN transmit output of the second CAN interface PSC2 UART6 TTL PSC6 receive data signal UART6 TXD TTL PSC6 transmit data signal 21C RXD6 232 RxD input on the RS 232 transceiver for the MPC UART PSC6 14 PHYTEC Messtechnik GmbH 2008 L 694e 1 Pin Description Signal
71. g receptacle for GPIO expansion board connectivity X4 PCI connector for compatible 3 3V PCI insert cards X5 JTAQ pin header for PCI insert card connector X4 X6 Connector for supply voltage 9 14V X7 PE connection X8 JTAG pin header for FPGA 9 JTAG pin header for MPC5200B controller X10 Compact Flash card socket X11 IDE Interface connector X12 FPGA configuration interface X15 Base Speaker Interface of the WM9712 U20 X16 Mono out from WM9712 X17 Beeper out from WM9712 X18 SPDIF out from WM9712 X19 Differential output from WM9712 X20 Auxiliary output from WM9712 P1 RJ45 Interface for Ethernet connection 10 100MBit P2 dual DB 9 plugs for CAN interface connectivity P3 dual DB 9 sockets for serial RS232 interface connectivity 4 input 5 Line in left right P6 Line out left right GND1 GND connector for measurement purposes PHYTEC Messtechnik GmbH 2008 L 694e 1 49 phyCORE MPC5200B 1 O UPI op sell ssescoriesss NN x10 Ser 9INH SINH __ _ ______ ______ e Ls 013 af Dee ge el x c a __ Lease YY
72. h memory bank is 32 bit The Flash memory bank is controlled by the processor Chip Select signal CSO This Chip Select signal is the dedicated control signal for boot purposes The MPC5200B s LocalPlus bus can be configured for many different bus modes For CSO the 25 bit address 32 bit data multiplexed mode was chosen because it offers the largest address space without interfering the ATA or PCI bus With 25 address lines a total of 32 MByte of data code can be addressed It is possible to use different bus modes on other available Chip Select signals The Flash memory bank 0 starts at address 0 0000_0100 or OxFFFF 0100 depending on the startup configuration and relative to the base address of the processor s Chip Select signal CSO The access speed depends on the equipped memory device The LocalPlus Bus clock cycle is determined by the PCI clock which is configured by the PCI clock divider A typical configuration selects 66 MHz The resulting basic cycle time is 15 15 ns The MPC5200B processor multiplexed read or write is divided into a address tenure and a data tenure Because the Chip Select signal is generated with the start of the data tenure only this period is of interest for access time calculation The equation for access time calculation is 2 WS tecick 8 5 ns To support all memory speed grades up to 75 ns at least 4 wait states must be added for 50 4 wait states for CSO supports 66 MHz PCI clock No additional v
73. iations to the description in this manual Revisions to previous manuals are also listed PHYTEC Messtechnik GmbH 2008 94 1 81 phyCORE MPC5200B 1 O Document phyCORE MPC5200B l O Document number L 694e 1 Edition April 2008 How would you improve this manual Did you find any mistakes in this manual Submitted by Customer number Name Company Address Return to PHYTEC Technologie Holding AG Robert Koch Str 39 D 55129 Mainz Germany Fax 449 6131 9221 26 82 PHYTEC Messtechnik GmbH 2008 page L 694e 1 Published by Eo Messtechnik GmbH 2008 Ordering L 694e_1 Printed in Germany
74. immediate startup The U Boot software project is subject to continuous maintenance and improvements Firmware updates will occur without special notification Should you require a specific version of U Boot pre installed at time of delivery please contact sales department If U Boot is used as boot loader firmware and basic component of the system software the user should be familiar with the following topics in order to ensure proper function U Boot default system configuration e system resources required by U Boot e modifying the U Boot loader 36 PHYTEC Messtechnik GmbH 2008 1 694 1 U Boot Boot Loader 9 1 U Boot Default System Configuration The U Boot boot loader changes the following default settings to different than the reset values of the processor on the phyCORE MPC5200B 1 O Clock Core 396 MHz IPB 132 MHz PCI 33 MHz Memory Base Address Register MBAR OxF0000000 DDR RAM Automatic storage size detection start address 0 0 Flash Chip Select CSBoot 32 bit data bus width 25 address lines multiplexed mode 4 wait states 32 MByte starting at address OxFE000000 FPGA Chip Select 3 and CS4 32 bit data bus width 25 address lines multiplexed mode 32MByte Address space per CS signal at address OxE2000000 CS3 and 0xE4000000 CS4 PSC2 CAN1 amp 2 PSC3 UART 115200 baud 8 N 1 SPI PCI enabled Ethernet 100 Mbit s with MD 2 EEPROM at address 0x52 RTC at ad
75. in two different configurations 1 GPIO6 goes low This multiplexer configuration allows use of the PSC6 signals as UART interface The multiplexer at 017 will route the PSC6 signals to the RS 232 transceiver 2 GPIO6 goes high In this multiplexer configuration the FPGA contents can be configured using the PSC6 signals 2 3 PSC6 signals are directly connected to the FPGA configuration interface through the multiplexer at U17 Package Type OR in SMD 0805 913 414 J5 and J6 define the slave addresses A1 and A2 of the serial memory UA on bus In the high nibble of the address memory devices have the slave ID OxA low nibble consists of A2 A1 AO and the R W bit AO is tied to GND It must be noted that the RTC at U5 is also connected to the bus The has the address OxA2 0xA3 which cannot be changed 1 2 2 3 X 2 0 1 0 0 0 OxA1 slave address 0xA0 for write operations and OxA1 for read access 1 2 1 2 2 1 1 0 0 0 OxA9 2 3 2 3 2 0 1 1 0 0 4 5 2 3 1 2 2 1 1 1 0 0 OxAD 412 Enables or disables the clock output the 05 RTC clockout is connected to X1B1 1 2 X RTC clockout disabled 243 clockout enabled Package Type OR in SMD 0805 J15 J15 configures the CS signal used for accessing the Flash open If J15 is not populated then a programmed GAL ATF16LV8C must populate
76. ing all available 3V3 input pins to the power supply system a custom carrier board housing the phyCORE MPC5200B I O and at least the matching number of GND pins neighboring the 3V3 pins In addition proper implementation of the phyCORE module into a target application also requires connecting all GND pins neighboring signals that are being used in the application circuitry Please refer to section 4 for more information PHYTEC Messtechnik GmbH 2008 1 694 1 7 phyCORE MPC5200B 1 O 2 Pin Description Please note that all module connections are not to exceed their expressed maximum voltage or current Maximum signal input values are indicated in the corresponding controller manuals data sheets As damage from improper connections varies according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals Many of the phyCORE MPC5200B l O pins offer alternative functions These alternative functions must be activated by configuring the applicable controller registers prior to their use Certain controller functions are pre configured based on the module s design and are shown in Table 1 Signals that are routed directly from the CPU to the Molex connectors can configured to any available alternative function desired by the user In contrast signals that are used on the phyCORE MPC5200 tiny as listed in
77. nector 62 FPGA JTAG Interface 35 PRAM 27 FSEO Mode 60 Functional Components on the phyCORE Carrier Board 54 GAL ATF16LV8C 30 GND Connection 45 Gpio_Wkup _7 59 Hints for Handling the Module 45 BUS edo 23 29 1 29 Memory 2 23 IDE 61 Intel Strata Flash 27 Introduction 2 22 METRE 22 THREE 23 Nuper 23 23 30 eee 23 30 23 22 DES 61 Messtechnik GmbH 2008 1 694 1 22 jJ n 29 29 dr 22 22 1 22 Som 62 EEE EE 61 RUBIA ADU 62 u 59 Sur c 60 S dede aa st asi 60 EET 60 Sae 62 59 59 JACI e 41 JTAG COCK 62 JTAG Interface 41 Jumper Configuration 51 Jumper Location 19 Jumper Settings
78. oltages are needed for in system programming As of the printing of this manual Flash devices generally guarantee at least 100 000 erase programming cycles Refer to the applicable INTEL data sheet for detailed description of the erasing and programming procedure 6 2 DDR SDRAM phyCORE MPC5200B l O is equipped with fast Double Data Rate Synchronous Dynamic Random Access Memory DDR SDRAM devices This memory is connected to a dedicated SDRAM interface provided by the MPC5200B processor The DDR SDRAM memory bank at U13 and U14 consists of two 16 bit data port devices connected in parallel to support the 32 bit bus width of the processor The memory bank is controlled by Chip Select signal SD_CS0 of the processor s DDR SDRAM controller Table 6 shows all possible memory configurations Available Capacity Device Organization Devices two 32 MByte 128 MBit MT46V8M16 2 MBit x 16 x 4 banks TSOP66 packaging 64 MByte 256 MBit MT46V16M16 4 MBit x 16 x 4 banks TSOP66 packaging 128 MByte 512 MBit MT46V32M16 8 MBit x 16 x 4 banks TSOP66 packaging Table 6 DDR SDRAM Device Selection 28 PHYTEC Messtechnik GmbH 2008 1 694 1 System Memory 6 3 Serial Memory The phyCORE MPC5200B l O features a non volatile memory device EEPROM with a serial interface This memory be used for storage of configuration data or operating parameters that must be maintained in the event of a power interruption
79. on with corresponding settings at DIP switch S3 generating a Boundary Scan chain Table 25 Misc Configuration J umpers J P10 J P12 14 3 14 FPGAJ TAG Connector X8 Connector X8 provide access to the JTAG signals for the FPGA on the phyCORE MPC5200B I O module Signal j Pin Pinf Signl FPGA TCK 1 2 GND FPGA TDO 3 4 3 3 5 5 default J1 connects 3 3V 7 8 9 10 GND Table 26 FPGAJ TAG Connector X8 Pin Assignment 62 PHYTEC Messtechnik GmbH 2008 L 694e_1 5200 on the Carrier Board 14 3 15 Pin Assignment Summary of the phyCORE the Expansion Bus and the Patch Field As described in section 14 1 all signals from the phyCORE MPC5200B I O extend in a strict 1 1 assignment to the Expansion Bus connector X3 on the Carrier Board These signals in turn are routed in a similar manner to the patch field on an optional expansion board that mounts to the Carrier Board at X3 Please note that depending on the design and size of the expansion board only a portion of the entire patch field is utilized under certain circumstances When this is the case certain signals described in the following section will not be available on the expansion board However the pin assignment scheme remains consistent A two dimensional numbering matrix similar to the one used for
80. or External connection of TTL signals is required for galvanic separation of the interface signals Using solder jumpers J1 and J2 the TTL transceiver outputs of the on board RS 232 transceiver devices can be disconnected from the receive lines UART3_RXD_TTL and UART6_RXD_TTL This is required so that the external transceiver does not drive signals against the on board transceiver The transmit lines UART3_TXD_TTL UART6_TXD_TTL can be connected parallel to the transceiver input without causing any signal conflicts 7 2 Ethernet Interface Connection of the phyCORE MPC5200B I O to the world wide web or a local network LAN is possible over the integrated FEC Fast Ethernet Controller of the Freescale processor The FEC operates with a data transmission speed of 10 or 100 Mbit s 7 2 1 PHY Physical Layer Transceiver The phyCORE MPC5200B I O has been designed for use in 10Base T and 100Base T networks The 10 100Base T interface with its LED monitoring signals extends to phyCORE connector X2 In order to connect the module to an existing 10 100Base T network some external circuitry is required The required 49 9 Ohm 1 termination resistors the analog signals ETH _ are already populated on the module If you are using the applicable phy CORE MPC5200B I O Carrier Board for the phyCORE MPC5200B part number PCM 973 the external circuitry mentioned above is already integrated on the board refer to section 14 3 7
81. ready Device select Parity error System Error open drain Command byte enable 1 ATA_CS_0 ATA_CS_1 ATA_IOCHRDY ATA_IOR ATA_INTRQ 3 2 PCI IRDY PCI DEVSEL PCI PERR PCI SERR CBE 1 PHYTEC Messtechnik GmbH 2008 L 694e 1 11 phyCORE MPC5200B 1 O Comments w RTC_CLKOUT O Clock output of the RTC U5 Interrupt input 1 of the processor IRQ2 Interrupt input 2 of the processor 4B 9B 148 GND Ground 0 V 19B 24B 29B 34B 39B 41B 44B 49B 54B 59B 64B 69B 71B 74B 79B 84B LocalPlus Bus Signals LP_CS3 Chip Select 3 LP_CS4 Chip Select 4 LP_RD WR Read not Write Signal write signal active low LP_Ts Transfer Start Signal LP_CS2 Chip Select 2 LP_CS5 Chip Select 5 LP_CS6 Chip Select 6 LP_CS7 Chip Select 7 PSC3 is UART3 FPGA IO Signals Pin Row XIB o 0 0 0 0 0 0 0 FPGA_B2_C11 FPGA_B2_F10 FPGA_B2_F9 FPGA_B2_D11 FPGA_B2_D10 FPGA_B2_B10 FPGA_B2_A10 FPGA_B2_B8 FPGA_B2_A8 FPGA B2 G7 FPGA B2 G6 FPGA B2 F6 FPGA B2 E6 FPGA B2 C5 FPGA B2 C4 FPGA B2 A5 FPGA B2 B5 FPGA B2 D9 FPGA B1 C1 FPGA B1 C2 FPGA B1 D2 FPGA B1 D4 FPGA B1 E2 FPGA B1 E4 FPGA B1 E5 12 PHYTEC Messtechnik GmbH 2008 L 694e 1 Pin Description Signal Comments FPGA Signals FPGA_B1_F5 FPGA_B1_H6 FPGA_B1_J2 1 2 1 5
82. ry serial configuration devices in order to program the FPGA it is possible to download firmware to this configuration device over the JTAG interface of the FPGA The JTAG interface signals of the FPGA are routed to the Molex connectors of the phyCORE MPC5200B refer to section 2 When used in combination with the phyCORE MPC5200B I O Carrier Board access to the JTAG port is available at a 10 pin header connector X8 refer to section 14 3 14 for details PHYTEC Messtechnik GmbH 2008 L 694e 1 35 phyCORE MPC5200B 1 O 9 The U Boot Boot Loader U Boot is a universal boot loader firmware based on GPL Gnu Public License Its main function is initializing the system hardware following a reset followed by starting application software such as an operating system Furthermore U Boot provides various functions to query system information and to change the start up behavior of the target system For example U Boot allows to choose from different boot sources such as Ethernet etc It also provides functions to download application code into Flash The serial interface is used to communicate with U Boot on the target system The U Boot for phyCORE MPC5200B tiny uses PSC3 with 115 200 Baud 8 1 The U Boot boot messages can be viewed within a terminal program running on a host PC using the above mentioned communication settings Note PHYTEC delivers all phyCORE MPC5200B IO modules with a pre installed U Boot allowing the user
83. s microcontroller modules allow engineers to shorten development horizons reduce design costs and speed project concepts from design to market PHYTEC Messtechnik GmbH 2008 1 694 1 1 phyCORE MPC5200B 1 O 1 Introduction The phyCORE MPC5200B I O belongs to PHYTEC s phyCORE Single Board Computer module family The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology Like its mini micro and nanoMODUL predecessors the phyCORE boards integrate all core elements of a microcontroller system on a sub miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments As independent research indicates that approximately 70 of all EMI Electro Magnetic Interference problems stem from insufficient supply voltage grounding of electronic components in high frequency environments the phyCORE board design features an increased pin package The increased pin package allows dedication of approximately 20 all pin header connectors on the phyCORE boards to Ground This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the complexity of the module 0402 packaged SMD and laser drilled Microvias components are used
84. sii iie eire Bee 27 6 1 Flash Memory a 27 6 2 BDR SDRAM z S 28 6 3 Serial Memory 29 6 4 Optional Battery Backed 30 7 Seriallnterfaces cates u 31 7 1 RS 232 Interface 31 7 2 Ethernet Interface D 31 7 2 1 PHY Physical Layer Transceiver 31 1 9727 MAG ACCESS u 32 7 3 USB 1 1 Host Interface T 32 8 The On Board 33 8 1 FPGA BUS Connection 34 8 2 FPGA Configuration Interface 35 8 2 1 Configuration via Processor GPIO Interface 35 8 2 2 Configuration via Serial Configuration Device 35 8 3 FPGA JTAG Interface 35 9 The U Boot Boot Loader 36 9 1 U Boot Default System 97 9 2 System Resources Required by 38 921 The Backup
85. the CAN transceiver on the Carrier Board the following jumper settings are not functional and could damage the module Jumper Setting Description JP6 open 2_ signal not connected to transceiver no CAN communication possible JP7 open signal not connected to transceiver no CAN communication possible Table 19 Improper J umper Settings for the CAN Plug P2B CAN Transceiver the Carrier Board 58 PHYTEC Messtechnik GmbH 2008 1 694 1 The 5200 on the Carrier Board 14 3 6 Programmable LED D16 The phyCORE Carrier Board MPC5200B offers a programmable LED at 016 for user implementations This LED can be connected to port pin Gpio Wkup 7 ball C12 or to the SPI MOSI signal ball B5 of the MPC5200B CPU A low level at applicable port pin causes the LED to illuminate LED D16 remains off when writing a high level Jumper Setting Description JP13 1 2 Port pin MOSI of the MPC5200B controls LED 016 on the Carrier Board JP13 2 3 Port pin Wkup 7 the MPC5200B controls LED D16 on the Carrier Board Table 20 17 Configuration of the Programmable LED D3 14 3 7 Ethernet Interface P1A The Ethernet interface of the phyCORE MPC5200B 1 O is accessible at an RJ45 connector the Carrier Board Due to its characteristics this interface is hard wired and can not be configured via jumpers The LEDs for LINK and S
86. the module This number is a 12 position HEX value 7 3 USB 1 1 Host Interface The MPC5200B integrates a USB 1 1 compliant host interface with two ports This interface supports full speed 12 Mbit s transmission rates The USB 1 1 controller is integrated in the MPC5200B processor The physical layer transceiver unit must be connected externally it is not populated on the phyCORE module For additional information of the USB 1 1 controller refer to the MPC5200B Reference Manual as well as the USB 1 1 bus specification provided by www usb org 32 PHYTEC Messtechnik GmbH 2008 L 694e 1 On board FPGA 8 The On Board FPGA The phyCORE MPC5200B I O SBC module design includes an ALTERA EP2C8 FPGA which be used in a variety of applications Data exchange between the FPGA and the MPC5200B processor occurs over the multiplexed LocalPlus Bus PHYTEC Messtechnik GmbH 2008 94 1 33 phyCORE MPC5200B 1 O 8 1 FPGA Bus Connection As previously mentioned the FPGA is connected to the processor via the multiplexed LocalPlus Bus of the MPC5200B This connection is used for data transfer between the two components and allows a data exchange of up to 44 Mbyte s depending on the bus frequency used The following LocalPlus Bus signals are routed to the FPGA Processor Signal FPGA Pin HRESET 9 LP_CS3 B4 N
87. y buffered SRAM e Optional industrial temperature range 40 85 1 Please contact PHYTEC for more information about additional module configurations PHYTEC Messtechnik GmbH 2008 L 694e 1 3 phyCORE MPC5200B 1 O 1 1 Block Diagram MPC5200B MPC603e series e300 core 16k D cache DDR SDRAM Bus 64 to 128MB DDR SDRAM 133MHz 32 bit LocalPlus Bus 396 MHz core Clock FLASH Altera FPGA EEPROM EP2C8F256 32 bit 32 bit 33 MHz Quarz 16k 4 Alarm FPU pioating Point I2C 1 4 5 MMU 1290 FEC FastEthernet Lm PHY USB Host PSC1 97 PSC2 CAN1 2 PS3 UART SPI NM Transceiver PSC 6 UART eee 1 _ _ COP JTAG Figure 1 Block Diagram phyCORE MPC5200B I O PHYTEC Messtechnik GmbH 2008 LoCalPlus Bus External Bus Interface PCI Bus V2 2 33 66MHz ATA Interface JTAG port for re programming 1 0 10 100 Mbit Ethernet USB 1 1 Host Interface PSC1 could be used as AC97 codec CANO TTL CAN1 TTL RXD3 TXD3 TTL

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