Home

User Manual - ALICE TPC Front End Electronics

1. Software Trigger Instruction Code 0x5306 Access Type Command Description This command will issue sequence of L1a and L2a to front end cards The latency between L1 and L2 is programmable through the Altro interface configuration register ALTROIF Timing Parameters Latency between L1 and L2 is programmable with Altro interface register Total of 13 bits can be assigned to set this latency L1 is synchronized with respect to sampling clock asserted for two clock cycle Similar way L2 to FEC is synchronized with read out clock as shown in figure 1 4 con_fec samp_clk f I1 altro tdo_clk Es Pa Sd GOGL GOGL L 2 altro H L1 to L2 programmable un Figure 1 5 software trigger chronogram 46 CLRERSTREG Clear Error and Status Registers Instruction Code 0x5307 Access Type Command Description This command clears all the error status registers The coding of this command from DDL is different DDL send command function is used to issue this command and value passed to the function must be 0x10000 47 CLRCNT Clear Error and Status Registers Instruction Code 0x5309 Access Type Command Description This command clears all the counters in the RCU 48 ARM SYNCH Arm Synchronization of Sampling Clock Instruction Code 0x530A Access Type Command Description This command will set the RCU for Synchronization with LO of SOD
2. table 1 7 Name Address Size Access Description Instruction Memory Ox 0000 Ox OFFF SPM W R Contains instructions to be 22x4K executed by IS Read out List Ox 1000 Ox 17FF SPM W R Configured with the channel Memory Branch A 12x2K addresses for event readout Read out List Ox 1800 Ox 1FFF SPM W R Memory Branch B 12x2K Result Memory Ox 2000 0x 37FF SPM W R It contains result of each 25x 6K transaction by IS TTCRx Register set 0x 4000 0x 4FFF Register W R These registers are used in s of TTCRx module various sizes Hit List Memory Ox 5000 Ox 503F DPM Configured by Board Branch A 32x64 Controllers with list of active channels for all FECs in Branch A Hit List Memory Ox 5040 Ox 507F DPM W R Configured by Board Branch B 32x64 Controllers with list of active channels for all FECs in Branch B Data Memories Ox 5800 Ox 5FFF DPM W R Contains the event data from 8 20x2 FECs 56 Table 1 7 Addressable Memories of RCU 26 1 5 Instruction Sequencer Commands There are four internal instructions for the Instruction Sequencer IS which controls the execution of instructions from instruction memory Result of these internal commands is loaded in the result memory as well In this section detail structure of these commands in the instruction memory and the respective result in the result memory is described 27 Instruction Sequencer Loop Instruction Coding in Instruction Memory
3. 100nsec 10 divide by 8 Period of sampling clock 200nsec 11 divide by 16 Period of sampling clock 400nsec Nr Samples channel 9 0 11 TRGCONF Trigger Configuration Register 16 0 Address 0x5102 Access Type RW Bit Width 17 Description Trigger Source 16 14 i 100 CTP Triger Enabled ii 110 L1 pulse is used as Trigger input Serial B input is ignored iii 001 Software Trigger Enable 0x5306 iv 010 Auxiliary Trigger Enable This trigger pulse is directly injected to RCU Trigger Mode 13 0 Trigger mode is TPC L1 from CTP is mapped to L1 to FEC 1 Trigger mode is PHOS LO from CTP is delivered as L1 to FEC L1 L2 Latency 12 0 12 RDOMOD Readout Mode Configuration Register 3 0 Address 0x5103 Access Type RW Bit Width 5 2 Debug mode Description Skip Empty Channel 6 6 1 RCU will skip the empty channel while performing Full Readout 5 0 RCU will not skip the empty channel while performing Full Readout Mask Check of Channel Address Block Length Mismatch 5 4 5 1 check of Channel address mismatch will be masked not checked 5 0 check of Channel address mismatch will not be masked checked 4 1 check of Block Length mismatch will be masked not checked 4 0 check of Block Length mis
4. 21 20 19 16 15 12 11 i 1 1 0001 ee of Loop Return Address Table 1 8 Structure of LOOP instructions Description This command is used as internal instruction of the sequencer to repeat a set of instructions for specific number of times The iteration is made for the specific number of times till the loop return address Parametric structure for loop command is shown in table 1 8 Result of LOOP in the Result Memory Result of this instruction is loaded in the result memory Status bit 20 shows the success or failure of the execution 0 success 1 failure Table 1 9 and 1 10 shows the result of execution for successful or failed execution respectively 24 21 20 19 16 15 12 11 0 0100 0 Zeros Number of Loop Return Address Loops Table 1 9 Content of result memory for successful execution of loop 24 21 20 19 14 13 10 9 0 0100 1 Zeros Error Loop Number of Errors Number Table 1 10 Content of result memory for failed execution of loop 28 AIT Instruction Sequencer Wait Instruction Coding in Instruction Memory 21 20 19 16 15 0 1 1 0010 Number of wait cycles 40MZ CLK Table 1 11 Structure of WAIT instruction Description This command is used as internal instruction of the sequencer to wait for specified number of clock cycles Parametric structure for WAIT command is shown in table 1 11 Result of WAIT in the Result Memory Result of this instruction is loaded in the result memory Table
5. Address space allocated to the ROLM A is 0x1800 Ox1FFF 2 Hit List Memory HLM Hit list memory is split into two separate memories one is specified for each branch A and B Size of each memory is 32 64 four consecutive locations specified for each FEC Address space allocated to the HLM A is Ox 5000 0x 503F Address space allocated to the HLM B is 0x 5040 0x 507F 3 SCEVL Delay Time to perform the scan event length command is configurable This is the time taken by the board controller to read the content of ADEVL register from ALTROs This register is set to a default value of 90 usec OxE10 for TPC Address of this register is 0x510A and its 13 bit wide 4 Configurable Frequency of Slow Control Clock Slow control clock is provided from RCU to the FECs the frequency of this clock is configurable Address of this register is Ox800C and its 2 bit wide Top Level Unit 1 1 functionality The data configuration transfer between the RCU and front end cards is performed with the ALTRO protocol as described in the ALTRO Chip User s Manual From the User s point of view the ALTROs are not directly accessible from the RCU The link is made through a Licontrollerlike procedure that will execute sequentially a set of pre loaded instructions In this way the user can send large portions of front end configuration in an instruction memory in the RCU and execute the sequence with a single command These seq
6. Error Register from Branch A and Branch B Word ID Parameter Code Value 10 0001 Error Registers for Branch A and B Description This trailer words contains information about errors occurred during normal read write command operation on FEC for branch A and branch B Mapping of these bit with respect to branches is described below Error Register1 25 13 FECERRA 19 7 Error Register1 12 0 FECERRB 19 7 FECERRA and FECERRB are two status registers copy of these registers are mapped in this trailer word List of the errors in FEC ERRA and FEC ERRB and respective bits are given as under FECERR 18 ALTRO error signal asserted while data being transferred FECERR 17 transfer not asserted FECERR 16 ALTRO error asserted before transfer FECERR 15 Write FSM error when started by RDO FSM FECERR 14 ackn not released by ALTRO FECERR 13 ALTRO error asserted while waiting for ackn to be released FECERR 12 ALTRO does not assert ackn FECERR 11 ALTRO error asserted while waiting for ackn FECERR 10 ALTRO asserts ackn before assertion of cstb FECERR 09 ALTRO error asserted while waiting for ackn in state chkack FECERR 08 ALTRO error asserted in state assertbus FECERR 07 ALTRO error asserted in the execution of a broadcast command 57 Error Register 2 Readout Errors Word ID Parameter Code Value 10 0010 Read out Error Register Descr
7. 0 Rol enabled 1 Region of Interest announced ESR 2 Rol received 3 Within region of interest 4 7 Calibration SW trigger type RoC 8 Software trigger event 9 Calibration trigger event 10 Event has L2 Reject trigger 11 Event has L2 Accept trigger 12 Include payload 17 13 SCLK phase when LO L1 trigger arrives 0 Serial B Stop Bit Error 1 Single Bit Hamming Error Individually Addr 2 Double Bit Hamming Error Individually Addr 3 Single Bit Hamming Error Broadcast 4 Double Bit Hamming Error Broadcast 5 Unknown Message Address Received 6 Incomplete L1 Message 7 Incomplete L2a Message 8 Incomplete Rol Message 9 TTCrx Address Error not X 0003 10 Spurious LO 11 Missing LO 12 Spurious L1 13 Boundary L1 14 Missing L1 15 L1 message arrives outside legal timeslot 16 L1 message missing timeout 17 L2 message arrives outside legal timeslot 18 L2 message missing timeout 19 Rol message arrives outside legal timeslot 20 Rol message missing timeout 21 Pre pulse error 0 possible future use 22 L1 message content error 23 L2 message content error 24 Rol message content error Table 1 6 Trigger interface module register set 25 1 4 RCU Memories and Address space RCU contains a number of memories to execute the block transactions and to perform the event readout These memories and their description are given in
8. 1 12 shows the result of execution 24 21 20 19 16 15 0 0101 0 Zeros Number of wait cycles 40MZ CLK Table 1 12 Content of result memory for the execution of Wait 29 ENDSEQ End OF Sequence Instruction Coding in Instruction Memory 21 20 19 16 15 0 1 1 1000 X Table 1 13 Structure of ENDSEQ instruction Description This command is used as internal instruction of the sequencer to end a set of instructions Parametric structure for ENDSEQ command is shown in table 1 13 Result of ENDSEQ in the Result Memory Result of this instruction is loaded in the result memory along with the address of last instruction executed Table 1 14 shows the result of execution for ENDSEQ 24 21 20 19 12 11 0 0111 0 Zeros Address of last executed instruction Table 1 14 Content of result memory for ENDSEQ 30 ENDMEM Instruction Sequencer End of memory Instruction Coding in Instruction Memory 21 20 19 16 15 0 1 1 1111 X Table 1 15 Structure of ENDMEM instruction Description This command is used to declare that end of memory has reached Parametric structure for ENDMEM command is shown in table 1 15 Result of ENDMEM in the Result Memory Result of this instruction is loaded in the result memory along with the address of last instruction executed Table 1 16 shows the result of execution for ENDMEM 24 21 20 19 12 11 0 0111 0 Zeros Address of last executed instruction Table 1
9. 16 Content of result memory for ENDSEQ 31 1 6 Front End Card Instructions There are three instructions which can be executed through the instruction sequencer These instructions are to perform three different functions in FECs read write or command Results of these instructions are loaded in the result memory regardless of successful or failed execution In this section detail structure of these instructions for the instruction memory and the respective result in the result memory is described 32 Front End Card Read Instruction Instruction Coding in Instruction Memory 0 0 Altro Instruction Format Table 1 17 Structure of FEC_RD instruction Description This instruction is used to perform the read operation on FEC Any addressable location of ALTRO or Board controller can be read using this instruction through instruction sequencer Parametric structure for FEC_RD instruction is shown in table 1 17 Timing Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 Clock P pgdly st cstb f r Hi Tout_ad 2 Ack N f aroso A I aono Figure1 2 FEC read chronogram Pgdly The command strobe is asserted after this programmable delay with respect to the ALTRO bus Tout_ack1 This is the maximum time for which acknowledge from FEC is awaited to get asserted 40 readout clock cycles Tout_ack2 This is the maximum time for which acknowledge from FEC is awaited to get released 40 readout
10. 5110 20 R Description Error code transactions on branch A 0 Altro Error is asserted FSM_WR 1 Altro assert error before cstb assert 2 ack assert before cstb 3 Altro assert error during waitack 4 ack not asserted amp time out 5 Altro error asserted during waitdone 6 ack not released by Altro 7 Altro Assert the error while waiting for broad cast command FSM_RD 8 Altro error is asserted during assertbus 9 Altro error is asserted while waiting for ack chlack 10 Altro assert ack before cstb assert 11 Altro error is asserted while waiting for ack 12 Altro does not assert ack 13 Altro error is asserted while waiting for release of ack 14 ack never released by Altro FSM_RDO 15 Fsm wr error when started by FSM RDO 16 Altro error asserted before transfer asserted 17 Transfer not asserted 18 Altro error asserted while data being transferred 19 Transfer not released FECERRB Ox 5111 20 Error code transactions on branch A 0 Altro Error is asserted FSM_WR 1 Altro assert error before cstb assert 2 ack assert before cstb 3 Altro assert error during waitack 4 ack not asserted amp time out 5 Altro error asserted during waitdone 6 ack not released by Altro 7 Altro Assert the error while waiting for b
11. BP_VERSION 0x5107 1 W R Mapping of ACTFECLIST to cardswitch lines 0 for TPC and FMD 1 for PHOS RCUID 0x5108 9 W R RCU ID Register SCEVL_DLY 0x510A 13 W R Time to perform SCEVL command SCLK_FREQ 0x800C 2 W R Frequency of the slow control clock is configured in this register Table 1 4 Configuration Registers of RCU ACTFECLIST Active Front End Card List 31 0 Address 0x5100 Access Type RAV Bit Width 31 Description Front end cards are set turned on and off by configuring this register FEC Branch A 15 0 FEC Branch B 31 16 10 ALTROIF ALTRO Interface Register 17 0 Address 0x5101 Access Type R W Bit Width 18 Description Instruction error check selection 17 16 00 Contents of Instruction memory are not Checked 01 Contents of Instruction memory will be checked against TPC instruction set 10 Contents of Instruction Memory will be checked against PHOS instruction set 11 Contents of Instruction Memory will be checked against FMD instruction set CSTB programmable delay 15 14 This is the delay between the assertion of cstb and altro bus to avoid any possibility of glitch on hand shake signals due to 40 bit ALTRO bus driving Sampling Clock Dividing Ratio T sampling Tanc 13 10 00 divide by 2 Period of sampling clock 50nsec 01 divide by 4 Period of sampling clock
12. CSTB branch B 4 ACK branch B 5 TRSF branch B 6 L1 of ALTRO 7 L2 of ALTRO RCU bus is busy running instruction sequencer PuSSSY xole 2 0 instruction sequencer busy 1 Last instruction sequence completed with errors MEBST 0x511B 4 3 0 MEB status counter CNT Debug 7 4 DATA_READY 9 8 DM_SEL it shows which of memory block out of AO A1 B0 B1 is being read by the data assembler SWTTRGC 0x511C 20 Software Trigger counter NT AUXTRGC 0x511D 20 Auxiliary Trigger counter NT TTCL2_AC 0x511E 20 TTC L2 Accept Counter NT TTCL2_RC 0x511F 20 TTC L2 Reject Counter NT DSTB_A 0x5120 20 Branch A DSTB Assert Counter CNT DSTB_B 0x5121 20 Branch B DSTB Assert Counter CNT 22 TRSFA CNT 0x5122 12 Branch A TRSF Assert Counter TRSFB CNT 0x5123 12 Branch B TRSF Assert Counter ACKA CNT 0x5124 12 Branch A ACK Assert Counter ACKB CNT 0x5125 12 Branch B ACK Assert Counter CSTBA CNT 0x5126 12 Branch A CSTB Assert Counter CSTBB CNT 0x5127 12 Branch B CSTB Assert Counter DSTB_NUM A 0x5128 DID WD D D D D Block length of last data written from Branch A DSTB_NUM B 0x5129 Block length of last data written from Branch B ADD_MM_C NT BLTH_MM_ CNT 0x512A 0x512B 12 12 Number of address mismatches between ALTRO trailer and addressed channel from ROLM Number of block length mismatches between ALTRO traile
13. Content of Result Memory for Successful FEC_RD Execution Content of Result Memory for Failed FEC_RD Execution Execution Description of AIM error code in result memory for FEC RD Description of Inst Analyzer error code in result memory FEC_RD Structure of FEC_WR Instruction Content of Result Memory for Successful FEC_WR Execution Content of Result Memory for Failed FEC_WR Execution Execution Description of AIM error code in result memory for FEC_WR Description of Inst Analyzer error code in result memory FEC_WR Structure of FEC_CMD Instruction Content of Result Memory for Successful FEC_CMD Execution Content of Result Memory for Failed FEC_CMD Execution Execution RCU Commands Structure of Event data block Common Data Header CDH Error amp Status Bit in CDH 4 27 12 Order of 10 bit words in 32 bit data packet RCU Trailer 7 7 7 8 20 22 23 25 25 25 26 26 27 27 28 28 28 31 31 31 31 32 33 33 33 33 34 35 35 36 46 47 49 50 51 List of Figures 1 1 1 2 1 3 1 4 1 5 Block Diagram of Top Level Module of the RCU Firmware FEC Read Chronogram FEC Write Chronogram CONFGFEC Chronogram Software Triger Chronogram 30 32 40 43 Updates w r t Version 2 0 1 Readout List Memory ROLM Read out list memory is split into two separate memories one is specified for each branch A and B Size of each memory is 12 2048 Address space allocated to the ROLM A is 0x1000 0x17FF
14. Instruction memory is used to perform read write command transaction to ALTRO or board controller Configuration of ALTROs is performed by execution of the sequence written in the instruction memory ADDRESS CONTENT COMMENT WRITE ALTRO REGISTER A BRANCH A FEC 0 0x000 0x20000A CHANNEL 0 0x001 Ox000ABC DATA TO WRITE ABC ADDRESS TO 0X002 0x00000A READ END OF 0x003 0X380000 SEQUENCE Readout List Memory ROLM Readout list memory is configured with channel addresses for event readout 66 67
15. clock cycles 33 Result of FEC_RD in the Result Memory Result of this instruction is loaded in the result memory Result of each read instruction comprises of two locations of the result memory Status bit 20 shows the success or failure of the execution 0 success 1 failure Table 1 18 ad 1 19 shows the result of execution for successful or failed execution respectively FEC Address from instruction memory for current instruction Data Read from FEC Table 1 18 Content of result memory for successful execution of FEC_RD FEC Address from instruction memory for current instruction 0000000 AIM Error Code 10 6 Instr error code 5 0 Table 1 19 Content of result memory for failed execution of FEC_RD AIM Error Description Code 10 6 01010 Altro Error line is asserted before the ack from FEC 01100 Altro asserts error while RCU wait for ack 01101 Altro does not assert ack time out 1 occurs Altro error is asserted while waiting the release of ack 01111 ALTRO doesn t release the ack time out 2 occurs Table 1 20 Description f the AIM error code in the result memory for read transaction Bit Number Instr error code 5 0 Description This bit is set if there has been an error in loop instruction This error bit is set if the format of instruction sequencer command is not correct 4 2 This bit is set if the format of instruction to boar
16. header are either loaded using the data transmitted by the ALICE Trigger system or created locally by the RCU when running without the ALICE Trigger system e g for standalone tests The parameters which are set at the RCU level are described here 31 24 16 8 0 0 Block length 0 31 i Format version MBZ L1 trigger MBZ Event ID 1 24 31 22 23 message 14 21 12 13 bunch crossing 0 11 gt MBZ Event ID 2 orbit number 24 31 0 23 Participating sub detectors 3 RCU VERSION 0x2 0 23 4 MBZ Status amp error bits Mini event ID 28 31 12 27 bunch crossing 0 11 5 Trigger classes low 0 31 ROI low Trigger classes high 6 28 31 18 27 0 17 y ROI high 0 31 Table 2 1 Common Data Header Block Length parameter in CDH 0 is set to FFFFFFFF RCU Version is set in CDH3 31 24 set to OX2 In CHD4 status amp Error bits are set by RCU RCU receives total of 25 bits of errors from trigger receiver module and code them into these 15 bits These errors are described in table 2 2 51 Error Bit Name Explanation No MESA Spurious LO High if a LO trigger comes outside of the legal time window for a LO Missing LO High if the LO trigger is missing O2 a 0 O Data parity error Not handled in RCU set to 0 3 0 Control parity error Not handled in RCU set to 0 eee eee ee Message e
17. 1 ESR_L2a ee eee High if a combination of the following occur content error BCID_Rol gt 3563 a j oo rravent baer eror Not Handed n ROU so T 145 oo 0o O Reserved Not used 0 Table 2 2 Error amp Status Bit in CDH 4 27 12 53 2 2 Pay Loac ALTRO data is s words The data is sent i Order of 10 bit words in 3 31 3029 20 19 10 9 0 Altro channel header 1 DW8 DW7 ows owa DW2 DW 1 0 Altro channel header 2 4 ows Altro channel header 3 Table 2 3 Order of 10 bit words in 32 bit data packet Altro channel header 11 0 Channel Address from Altro Altro channel header 25 16 Block Length Number of 10 bit words from Altro Altro channel header 29 E Channel Error Bit it is set to 1 if there has been a mismatch for channel address or block length received from ALTRO trailer RCU will add a corrected Altro channel header followed by the data received from corresponding channel Altro channel header 31 30 Word ID 01 to mark ALTRAO Header 00 for payload Altro channel header 15 12 28 26 Reserved 0000 DW 10 bit data word 0x00 Padding 54 2 3 RCU Trailer Event data is followed by RCU trailer This trailer comprises of 9 words of 32 bits Start and end of RCU trailer is marked by two most significant bits Each trailer word consists of parameter code and its value RCU trailer format is shown in table 2 4 detail of each parameter is described
18. 7 Enable second baseline correction RDO_CFG1 11 Glitch filter configuration for zero suppression RDO_CFG 1 13 12 Nr Of post samples excluded from suppression RDO_CFG1 16 14 Nr Of pre samples excluded from suppression RDO_CFG1 18 17 Enable Zero Suppression RDOCFG1 19 14 ALTROCFG2 Altro Configuration Register 2 24 0 Address 0x5105 Access Type R W Bit Width 25 Description Nr of ALTRO Buffers copy of RCU register ALTROCFG2 4 RDO_CFG2 24 Nr of pre trigger samples copy of RCU register ALTROCFG2 3 0 RDO_CFG2 23 20 Nr Samples channel copy of RCU register ALTROIF 9 0 RDO_CFG2 19 10 Sparse Readout RDO_CFG2 9 Tsampling TLHC RDO_CFG2 8 5 Phase of L1 trigger w r t LHC bunch crossing RDO_CFG2 4 0 The phase is calculated in terms of bunch crossing cycles for example if the T sampling TLHC is equal 01 10MHz sampling rate only the two least significant bits are meaningful and the phase can take values 0 1 2 3 15 RCU_VERSION RCU Version Register 23 0 Address 0x5106 Access Type R Bit Width 24 Description This register describes the RCU version along with the revision format is MM YY AE VERSION read as X 07 08 AE 20 Month Year 0708 Version 2 0 Identification AE 16 BP_VERSION Back Plane Version Register 0 Address 0x5107 Access Type R Bit Width 1 Description This re
19. Sampling Clock is reset upon receiving the first LO after this command has been received 49 RCU Data Format In the RCU the 40 bit wide ALTRO data packets are formatted into 32 bit wide packet Structure of event data is described in table 1 26 The 32 bit data packet is completed by a trailer table 1 1 to form the RCU data block The trailer consists of 2 fixed words the first and the last one in the trailer and N optional words that carry information on the settings and status of the FECs and RCU The two fixed trailer words define respectively 1 the Payload Length which specifies the number of 40 bit data words 2 the RCU Address and the Trailer Length in 32 bit words The optional words that compose the trailer consist of a parameter code the 6 MSB and the parameter itself that consists of 26 bits The parameters to be appended to the Event Trailer will be stored in a dedicated RCU memory Trailer Memory that contains a maximum of 64 words The actual number of parameter that will be included in the Trailer is variable and is defined by the first word in the Trailer Memory Hereunder detail of each parameter is described in table 1 32 that will be included in the RCU Firmware V2 0 Common Data Header 8 words Payload Variable nr of words minimum 0 RCU Trailer 9 words Table 1 31 Structure of the Event data block 50 2 1 Common Data Header CDH The various fields of the common data format
20. W EXESEQ W 0x 5304 Start Execution of Instruction Sequencer ABRTSEQ W 0x 5305 Abort the Execution cycle of Instruction Sequencer SWTTRG Ox 5306 Issue Software Trigger Clear Error amp Status Registers CLERRSTREG Ww Ox 5307 j 0x10000 Value for DDL send command CLEARRDRXREG za Ox 5308 Clear RD_RX error register CLRCNT ae ee Ox 5309 Clear Counters ARBITERIRQ 0x 5310 DCS BUS INTERRUPT REQUEST Note In DCS interface ARMSYNCH w ox530a AmSynchronization with Lo ofSOD Table 1 30 RCU Commands 39 GRESET Global Reset Instruction Code 0x5300 Access Type Command Description This command will reset the full RCU including configuration registers error and status registers and front end cards The code 0x5300 is specific to be used from DCS only The coding of this command from DDL is different DDL send command function is used to issue this command and value passed to the function must be 0x2 40 FECRST FEC Reset Instruction Code 0x5301 Access Type Command Description This command is used to send a reset pulse to Front end cards The coding of this command from DDL is different DDL send command function is used to issue this command and value passed to the function must be 0x8 41 RCURST RCU Reset Instruction Code 0x5302 Access Type Command Description This command will reset the RCU for state machines Configuration registers error and stat
21. as followed 31 30 29 26 25 0 Word ID Parameter Value 10 Pay Load Length 0000 Number of 32 bit words 10 Error Register 1 0001 Error Registers for Branch A and B 10 Error Register 2 0010 Read out Errors 10 Error Register 3 0011 Number of Altro Trailer Errors 10 Act FECA 0100 Active Front End Cards for Branch A 10 Act FEC B 0101 Active Front End Cards for Branch B 10 RDO CONFIG 1 0110 Readout configuration Register1 of Altro 10 RDO CONFIG 2 0111 Readout configuration Register2 of Altro RCU 11 RCU ID 1000 FW RCU address version Table 2 4 RCU Trailer 31 30 Word ID two most significant bits are used to identify the start and end of RCU trailer Word ID 10 shows that the word belong to RCU Trailer where as 11 shows that this is the last word of the RCU trailer 29 26 Parameter four bits field is used to mark different words in the RCU trailer 25 0 Value These 26 bits are used to record the status of the parameters listed in the table for the event 55 Pay Load length Number of 32 bit words transmitted from RCU Word ID Parameter Code Value 10 0000 Number of 32 bit words Description This trailer words contains the number of data words sent from RCU to SIU It s the first word in trailer and the parameter code is 0x0 The Word ID is two most significant bits set to 10 showing that the word is part of RCU trailer 56 Error Register 1
22. d controller is not correct This bit is set if the board controller at Off FEC is addressed checked w r t FEC ACTIVE LIST Sa This bit is set if the format of instruction to ALTRO is not correct This bit is set if ALTRO at Off FEC is addressed checked w r t FEC_ACTIVE LIST Table 1 21 Description of the instruction Analyzer error code in the result memory for read transaction 1 3 5 34 FEC WR Front End Card Write Instruction Instruction Coding in Instruction Memory 21 20 19 0 Altro Instruction Format Data to be written to FEC Table 1 22 Structure of FEC_WR instruction Description This instruction is used to perform the write operation on FEC Any write able location of ALTRO or Board controller can be written using this instruction through instruction sequencer Each write instruction consists of two locations first one contains the instruction parameters same as ALTRO next subsequent location contains the data for the write transaction Parametric structure for FEC_WR instruction is shown in table 1 22 Timing Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 Clock pgdl sdy y cstb f i Tout_ackt Tout_ad2 i Arria te Ack Y y Write Y l 7 AltroBDI9 0 Figure 1 3 FEC write Chronogram Pgdly The command strobe is asserted after this programmable delay with respect to the ALTRO bus Tout_ack1 this is the maximum time for which ac
23. e ell ee eae Message Be erent eg Message a ee High if the L1 message does not start to arrive within the legal missing timeout time window for a L1 message a L2 message High if all or part of the L2a L2r message arrives outside of the arrives outside legal time window for a L2a L2r message legal timeslot Pe oe High if the Rol message does not start to arrive within the legal missing timeout time window for a Rol message 5 0 Frontend electronics error Not Handled in RCU set to 0 0 HLT decision flag Not Handled in RCU set to 0 O7 ila 0 OEO HLT payload flag Not Handled in RCU set to 0 0 TTCrx Address Error 8 DDG payload flag Not Handled in RCU set to 0 High if the TTCrx address is unequal to 0x8001 The message will not be decoded if this is this case and the message decoder will return to idle 10 L2 message High if all or part of the L2a L2r message arrives outside of the arrives outside legal time window for a L2a L2r message legal timeslot Beas High if the L2a L2r message does not start to arrive within the missing timeout legal time window for a L2a L2r message Serial B Stop Bit Serial B stop bit is 0 when it is expected to be 1 Error SingleBit Hamming Single bit hamming error found and corrected in individually Error Individually addressed message Addr Double Bit Double bit hamming error found in individually addressed Hamming Error message not possible to correct Most likely a lo
24. e mask 1 10 L2 Timeout FIFO storage mask 1 11 L1a message mask 1 12 Trigger Input Mask Enable 0 13 15 Not Used 16 Bunch_counter overflow 17 Run Active 18 Busy receiving sequence 19 Not Used 23 20 CDH version 0x2 31 24 Trigger Receiver Version 0x13 Module Reset 0x4001 Reset Module Rol_Config1 17 0 0x4002 RW Definition of what region of interest the RCU is a part of depends on the sector Bit 17 0 Rol_Config2 17 0 0x4003 RW Definition of what region of interest the RCU is a part of depends on the sector Bit 35 18 Reset Counters 0x4004 Write to this registers will reset the counters in the module Issue Testmode 0x4005 Debug Issues testmode sequence Note that serialB channel input MUST be disabled when using this feature L1_Latency 15 0 0x4006 RW 15 12 Uncertainty region N default value 0x2 50 ns 11 0 Latency from LO to L1 default value 0x0D4 5 3 us L2_Latency 31 0 0x4007 RW 15 0 Max Latency from BCO to L2 default value 0x4E20 500 us 31 16 Min Latency from BCO to L2 default value 0x0C80 80 us Rol_Latency 31 0 0x4009 RW 15 0 Max Latency from BCO to Rol msg 31 16 Min Latency from BCO to Rol msg L1_msg_latency 31 0 0x400A RW 15 0 Max Latency from BCO to L1 msg default value 0x0028 1 us 31 16 Min Latency from BCO to L1 msg default value Ox0F8 6 2 us Pr
25. e_pulse_counter 15 0 0x400B R Number of decoded pre pulses BCID_Localf11 0 0x400C R Number of bunchcrossings at arrival of L1 trigger LO_counter 15 0 0x400D R Number of LO triggers L1_counter 15 0 0x400E R Number of L1 triggers L1_msg_counter 15 0 0x400F R Number of successfully decoded L1 messages L2a_counter 15 0 0x4010 R Number of successfully decoded L2a messages L2r_counter 15 0 0x4011 R Number of successfully decoded L2r messages Rol_counter 15 0 0x4012 R Number of successfully decoded Rol messages Bunchcounter 1 1 0 0x4013 R Debug Number of bunchcrossings 24 Address Access Description Event_error 24 0 0x4029 R hammingErrorCnt 31 0 0x4016 R 15 0 Number of single bit hamming errors 31 16 Number of double bit hamming errors ErrorCnt 31 0 0x4017 R 15 0 Number of message decoding errors 31 16 Number of errors related to sequence and timeouts Buffered_events 4 0 0x4020 R Number of events stored in the FIFO DAQ_Header01 31 0 0x4021 R Latest received DAQ Header 1 DAQ_Header02 31 0 0x4022 R Latest received DAQ Header 2 DAQ_Header03 31 0 0x4023 R Latest received DAQ Header 3 DAQ_Header04 31 0 0x4024 R Latest received DAQ Header 4 DAQ_Header05 31 0 0x4025 R Latest received DAQ Header 5 DAQ_Header06 31 0 0x4026 R Latest received DAQ Header 6 DAQ_Header07 31 0 0x4027 R Latest received DAQ Header 7 Event_info 17 0 0x4028 R Latest Received Event information
26. ee RCU Firmware V2 1 User Manual Started 15 April 2010 Last Update 13 August 2010 DRAFT 0 1 Index of Contents RCU Firmware V2 1 User Manual 0 1 Index of Contents 0 2 List of Tables 0 3 List of Figures 0 4 Updates w r t RCU_FW v2 0 Chapter 1 1 1 Functionality 1 2 RCU FEC Instruction Format 1 3 Register Table 1 4 RCU Memories and Address space 1 5 Instruction Sequencer Commands 1 6 front End Card Instructions 1 7 RCU Commands Chapter 2 2 1 Common Data Header CDH 2 2 Pay Load ALTRO Read out Data 2 3 RCU Trailer Appendix a fF OO N a o o DD 26 27 32 39 50 51 54 55 66 List of Tables 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 1 19 1 20 1 21 1 22 1 23 1 24 1 25 1 26 1 27 1 28 1 29 1 30 1 31 2 1 2 2 2 3 2 4 IS Instruction Format IS Internal Instruction Codes IS Internal Instruction format Configuration Registers of RCU Status amp Error Registers of RCU Trigger Interface module Register set Addressable Memories of RCU Structure of LOOP Instruction Content of Result Memory for Successful Loop Execution Content of Result Memory for Failed Loop Execution Structure of WAIT Instruction Content of Result Memory for WAIT Execution Structure of ENDSEQ Instruction Content of Result Memory for ENDSEQ Execution Structure of ENDMEM Instruction Content of Result Memory for ENDMEM Execution Structure of FEC_RD Instruction
27. gister set the mapping structure of ACTFECLIST to card switch lines 0 TPC and FMD PHOS 17 RCUID RCU Identification Register 8 0 Address 0x5108 Access Type RW Bit Width 9 Description This register identifies the physical location of RCU RCUID 8 0 for A side 1 for C side RCUID 7 3 sector number 0 17 RCUID 2 0 readout partition number 0 5 18 SCEVL DELAY Scan Event Length Command Delay 8 0 Address 0x510A Access Type R W Bit Width 13 Description SCEVL command is given in broadcast mode to all FECs while performing the sparse readout This register is used to configure the delay for scan event length command to the board controller This time is taken by the every board controller to transfer the contents of the event length register from ALTRO and build the event length register in board controller for 128 channels Default value of this register is set to 0xE10 3600 25nsec 90usec for TPC 19 SCLK FREQ Frequency of the Slow control clock 1 0 Address 0x800C Access Type RAV Bit Width 2 Description Slow control clock is provided to board controller to perform the readout of monitoring parameters The frequency of this clock is configurable as described below Value Frequency MHz 0x0 5 0 0x1 2 5 0x2 1 25 0x3 0 625 20 Name FECERRA Address Width Access 0x
28. iption This trailer words contains the errors occurred during readout process Bit number 7 and 8 shows that there has been at least one channel address or block length mismatch in the event data SCANEVENLEN error and EVLENRDO errors are related to the errors occurred during sparse readout ERR_REG2 8 ERR_REG2 7 ERR_REG2 6 ERR_REG2 5 ERR_REG2 4 0 Block Length mismatch Channel Address mismatch RDYRX error SCANEVLEN error EVLENRDO error 58 Error Register 3 Number of Altro Trailers Errors Word ID Parameter Code Value 10 0011 Count address amp block length mismatch Description This trailer words contains the number of channel address and block length mismatches found in the trailers sent from Altro Channel address mismatch is incremented when the last channel addressed is different than the channel address in Altro trailer block length mismatch is marked by comparing the number of data strobes and number of 10 bit words in the Altro trailer ERR_REG3 11 0 Number of mismatches in the channels address detected by the data assembler during the readout ERR_REG3 24 12 Number of mismatches in the channel data block length detected by the data assembler during the readout 59 Act FEC A Active Front End Card List for Branch A Word ID Parameter Code Value 10 0100 Active Front End Cards on Branch A Description This trailer words contains the of Acti
29. knowledge from FEC is awaited to get asserted 40 readout clock cycles Tout_ack2 This is the maximum time for which acknowledge from FEC is awaited to get released 40 readout clock cycles 35 Result of FEC_WR in the Result Memory Result of this instruction is loaded in the result memory Result of each write instruction comprises of two locations of the result memory Status bit 20 shows the success or failure of the execution 0 success 1 failure Table 1 23 ad 1 24 shows the result of execution for successful or failed execution respectively 24 21 20 19 0 FEC Address from instruction memory for current instruction 0010 0 Data written to FEC from Instruction memory Table 1 23 Content of result memory for successful execution of FEC_WR 24 21 20 19 0 FEC Address from instruction memory for current instruction 0010 1 0000000 AIM Error Code 10 6 Instr Aniz Code 5 0 Table 1 24 Content of result memory for failed execution of FEC_WR AIM Error Description Code 10 6 Altro Error line is asserted before cstb is asserted from RCU Altro ack is asserted before the cstb from RCU Altro asserts error while RCU wait for ack Altro does not assert ack time out 1 occurs Altro error is asserted while waiting the release of ack Table 1 25 Description of the error code in the result memory for write transaction Bit Number I
30. match will not be masked checked Mask Read to Receive RDYEX 3 1 Ready to receive command is masked means even if the ready to receive command is not given from DDL still data will be delivered from RCU to SIU Used for debugging purposes 0 Ready to receive command open link must be given before data is to be received Sparse Readout Mode 2 0 Read out mode is full readout according to readout list memory 1 Read out mode is sparse readout according to readout list memory SOE EOE Instruction Memory Execution 1 0 Sequence in the instruction memory will not be executed on SOE EOE T Sequence in the instruction memory will be executed on SOE EOE and result from result memory will be sent as payload MEB multi event buffer Mode 0 0 Multi event buffer mode is set to 4 1 Multi event buffer mode is set to 8 13 ALTROCFG1 ALTRO Configuration Register 1 19 0 Address 0x5104 Access Type RW Bit Width 20 Description This register is copy of ALTRO configuration register Parameters in this register are used to record in the RCU trailer word Refer to ALTRO manual pages 36 37 First Baseline Correction Mode RDOCFG1 3 0 Polarity When set the ADC data is inverted 1 s C 4 Nr Of pre samples excluded from 2 baseline corr RDO_CFG1 6 5 Nr Of post samples excluded from 2 baseline corr RDO_CFG41 10
31. nstr error code 5 0 Description This bit is set if there has been an error in loop instruction This error bit is set if the format of instruction sequencer command is not correct This bit is set if the format of instruction to board controller is not correct w r t FEC_ACTIVE LIST This bit is set if the format of instruction to ALTRO is not correct This bit is set if ALTRO at Off FEC is addressed checked w r t FEC_ACTIVE LIST This bit is set if the board controller at Off FEC is addressed checked Table 1 26 Description of error codes in the result memory for write transaction 36 FEC CMD Front End Card Command Instruction Instruction Coding in Instruction Memory 21 20 19 0 0 1 Altro Instruction Format Table 1 27 Structure of FEC_CMD instruction Description This instruction is used to execute FEC command operation Parametric structure for FEC_CMD instruction is shown in table 1 27 Timing Parameters The timing behaviour for this instruction is same as the FEC write instruction There is one exception for the EVLRDO command which is issued while making the sparse readout The exception is related to acknowledge signal ACK from FEC For this command ACK is not checked for its assertion 37 Result of FEC_CMD in the Result Memory Result of this instruction is loaded in the result memory Result of each command instruction comprises of two locations of the re
32. nstructions codes IS FEC IS CMD CMD PARAMETER 11 Wait Number of wait cycles 11 Loop No ONDOpS Loop return address 1 1 0 15 12 11 ENDSEQ xX 11 ENDMEM xX Table 1 3 IS internal instruction format 1 3 Configuration Registers The register Table 1 4 incorporates various registers that are used for configuration of the RCU Table 1 5 and table 1 6 describes the status and error register which can be read externally for RCU and trigger module respectively Addres Width Access Description S ACTFECLIST 0x5100 32 W R Active FEC List ALTROIF 0x5101 18 W R Nr Samples channel 9 0 T sampling Thue 1 3 10 CSTB programmable delay 15 14 Instruction error check selection 17 16 TRGCONF 0x5102 17 W R Trigger Source 16 14 Trigger Mode 13 L2 latency wrt L1 12 0 RDOMOD Ox 5103 4 W R 3 Mask RDYRX Sparse readout enable 2 execute sequencer on SOE EOE 1 MEB mode 0 ALTROCFG1 0x5104 20 W R Copy of the ALTROCFG 1 register of the ALTRO chip see ALTRO manual pags 36 37 The content of this register will be copied in one of the words of the event data block trailer ALTROCFG2 0x5105 25 W R Copy of the ALTROCFG2 register of the ALTRO chip see ALTRO manual pags 36 37 The content of this register will be copied in one of the words of the event data block trailer RCU_VERSION 0x5106 24 R RCU version ASCII coding of version number
33. on for details please see ALTRO manual page 36 37 This register can be written as ALTROCFG2 at 0x5105 This register can be configured for any detector related information please consult page 14 of this manual 4 0 Phase of sampling clock with respect to Arrival of the trigger 63 RCU Identification Register Word ID Parameter Code Value 11 1000 RCU Identification Description This trailer words contains the parameters related to the RCU in terms of its location This parameter contains the firmware version as well Details of the this parameter is given as under 25 16 0x2 RCU Firmware Version 15 7 RCU Address RCU Address 8 0 for A side 1 for C side RCU Address 7 3 sector number 0 17 RCU Address 2 0 readout partition number 0 5 6 0 Trailer length no of 32 bit words related to trailer words 64 Monitoring Unit SLOW Control Monitoring unit can read all of the status registers available in board controller Read process is done in three steps i Write address in the SC Address Register 0x8005 ii Give Execute Command 0x8010 iii Read the result Register 0x8002 RD TX from MSM to Baord Controller 7 5 usec for one complete Transaction Cursor 61 806 ne 53 888168866us e A ina i inj SP Page TimeA 61 806632686 6lus Figure 3 1 Read Transaction from MSM to Board Controller 65 Appendix Instruction Memory IM
34. r word and the data strobe counter 1 ABDFSMPR _ST RDOFSMPR _ST 0x512C 0x512D 22 15 ABD state machines status 21 19 FSM_RDO status of branch B 18 15 FSM_RD status of branch B 14 11 FSM_WR status of branch B 10 8 FSM_RDO status of branch A 7 4 FSM_RD status of branch A 3 0 FSM_WAR status of branch A Readout state machines status 14 12 SCEVLEN_FSM status 11 8 _EVLEN_FSM status 7 4 FSM_EVRDO_CTRL status 3 2 FSM_SEL_BR status of branch B 1 0 FSM_SEL_BR status of branch A INSSEQ PR_ST 0x512E 15 Execute instruction sequencer state machines status 14 10 FSM_INSTSEQ status 9 5 FSM_INSTLOOP status 4 0 FSM_RU status EVMNGPR_ ST 0x512F 12 Event manager state machines status 11 10 FSM_TST_TRG status 9 6 FSM_TTC_TRG status 5 3 FSM_EV status 2 0 FSM_INSSEQ status DA_FSM 0x5130 29 25 fsmrdrm_st 24 20 fsmrdpar_st 19 15 fsmrddm_st 14 10 fsmrdcdhsoft_st 9 5 fsmrdcdh_st 0 4 fsmdamain_st RDO_TIME 0x5132 32 R Time taken by last event readout L2 EOEV RDO_TIME 25 TIME IN nsec Table 1 5 Status amp Error Registers of RCU 23 Name Control 23 0 Address Ox 4000 Access RW Description 0 Serial B channel on off Default 1 1 Disable_error_masking 0 2 Enable Rol decoding 0 3 LO support 1 4 7 Not Used 8 L2a FIFO storage mask 1 9 L2r FIFO storag
35. road cast command FSM_RD 8 Altro error is asserted during assertbus 9 Altro error is asserted while waiting for ack chlack 10 Altro assert ack before cstb assert 11 Altro error is asserted while waiting for ack 12 Altro does not assert ack 13 Altro error is asserted while waiting for release of ack 14 ack never released by Altro FSM_RDO 15 Fsm wr error when started by FSM RDO 16 Altro error asserted before transfer asserted 17 Transfer not asserted 18 Altro error asserted while data being transferred 21 19 Transfer not released Errors related to Event Read out ROOERE pxodta 3 0 Error occur during send command 1 Atiro error when wait trsf assert 2 Trsf not assert 3 Altro not give four dstb data 4 Trsf not release 5 Error occur during send scan event length command 6 RD_RX not asserted or de asserted during event readout 7 Channel Address mismatch 8 Data Block Length mismatch Debug 31 28 FSMWR_ST_B 27 24 FSMWR_ST_A 23 20 FSMEVLEN_ST ALTRO bus status refreshed every clock cycle E Pori 3 0 CSTB branch A 1 ACK branch A 2 TRSF branch A 3 CSTB branch B 4 ACK branch B 5 TRSF branch B 6 L1 of ALTRO 7 L2 of ALTRO ALTBSST 0x5115 8 ALTRO bus status when TRSF_A or TRSF_B is TRSF asserted 0 CSTB branch A 1 ACK branch A 2 TRSF branch A 3
36. sult memory Status bit 20 shows the success or failure of the execution 0 success 1 failure Table 1 28 and 1 29 shows the result of execution for successful or failed execution respectively 24 21 20 19 0 FEC Address from instruction memory for current instruction 0001 0 XXXXXX Table 1 28 Content of result memory for successful execution of FEC_CMD 24 21 20 19 0 FEC Address from instruction memory for current instruction 0001 1 0000000 AIM Error Code 10 6 Instr Aniz Code 5 0 Table 1 29 Content of result memory for failed execution of FEC_CMD Explanation of the error codes is same as the FEC write transaction please refer to table 1 25 and table 1 26 38 1 7 RCU Commands There are eleven commands which can be executed directly on RCU means that its not loaded in the instruction sequencer These commands are to initialize different functions in RCU Results of these instructions are not available in the result memory In this section detail structure of these commands is described Please not that the instruction for the resets is different for DDL and DCS side Name Access a Code Description Global reset Resets RCU and FECs GRESET 0x 5300 0x2 Value for DDL send command Front end card reset FECRST w Ox 920 0x8 Value for DDL send command RCU Reset RCURST w Ox 5302 0x4 Value for DDL send command CONFGFEC Ox 5303 Re configures the BC of the FEC
37. t of other errors Individually Addr will come as a result of this Double Bit Double bit hamming error found in broadcast message not Hamming Error possible to correct Most likely a lot of other errors will come as Broadcast a result of this Unknown Message If an individually addressed message has arrived with a not Address Received known address Known addresses are given in Table 5 7 TTCrx Address High if the TTCrx address is unequal to 0x8001 The message Error will not be decoded if this is this case and the message decoder will return to idle L1 message High if all or part of the L1 message arrives outside of the legal arrives outside time window for a L1 message legal timeslot L2 message High if all or part of the L2a L2r message arrives outside of the arrives outside legal time window for a L2a L2r message legal timeslot High if all or part of the Rol message arrives outside of the legal 52 a legal timeslot MEN High if the Rol message does not start to arrive within the legal missing timeout time window for a Rol message L1 message High if a combination of the following occur content error CIT_L1 0 after arrival of pre pulse L1_SwC 0 when CIT_L1 1 L1_SwC L2_SwC CIT_L1 CIT_L2a ESR_L1 ESR_L2a L2 message High if a combination of the following occur content error BCID_L2a L2r gt 3563 CIT_L2 0 after arrival of pre pulse L2_SwC 0 when CIT_L2 1 L1_SwC L2_SwC CIT_L1 CIT_L2a ESR_L
38. uences can be composed with ALTRO instructions and RCU specific instructions This manual contains full information on all accessible memories and registers along with the executable commands CSWB 13 0 ly JILL fo elisiT Ho Lov CSWA 13 0 Figure 1 1 Block Diagram of TOP Module of the RCU Firmware 2 1 1 2 RCU FEC Instruction Format An important difference between v1 and v2 of the RCU firmware regards the Instruction Sequencer IS In the new version the IS can execute ALTRO Instructions but not RCU Instructions In addition the IS recognizes a set of 4 internal instructions that can be used to condition the execution of the ALTRO instructions The Instruction Memory IM of the IS has in RCU v2 a depth of 4096 x 22 bit wide words The format of the Instructions for the IS is illustrated in tables 1 1 1 2 and 1 3 21 IS FEC 20 19 INSTRUCTION PARAMETERS 0 00 FEC_RD ALTRO Instruction 01 FEC_CMD ALTRO Instruction ALTRO Instruction Address 10 FEC_WR ALTRO Instruction Data 11 1S_CMD IS Internal Code 4 bits A oon Code parameter 16 Its Table 1 1 IS Instruction Format Name Access Inst Code Description LOOP W 0x1 Execute the instructions in loop for defined number of times WAIT W 0x2 Wait for defined number of clock cycles ENDSEQ End of specific sequence set of instructions ENDMEM End of Instruction Memory Table 1 2 IS internal i
39. us registers will not have any effect from this command The code 0x5302 is specific to be used from DCS only The coding of this command from DDL is different DDL send command function is used to issue this command and value passed to the function must be 0x4 42 CONFGFEC Configuration of Front End Card Board Controller Instruction Code 0x5303 Access Type Command Description This command will turn off the front end cards for 4 0uSec After the 4 0uSec the front end cards will be turned on same as the original configuration of active front end card list as shown in the figure Timing Parameters Clock PLE LE LE LE LALA LAL LEE LEE con_fec y Co ae oD Gate ee ee eee eee Cees eee Ee Settings 4 ALL FRONT END CARDS ARE KEPT OFF FOR THIS PERIOD Settings A Figure 1 4 CONFGFEC Chronogram 43 EXESEQ Execute Sequence Start Sequencer Instruction Code 0x5304 Access Type Command Description This command will start the execution of Instruction sequencer Instruction sequencer will execute the sequence loaded in the instruction memory 44 ABRTSEQ Abort Sequence Stop Sequencer Instruction Code 0x5305 Access Type Command Description This command will abort the execution of current sequence which is being executed by the sequencer Instruction sequencer will exit from the sequence loaded in the instruction memory to idle state 45 SWTTRG
40. ve Front End Cards FECs in branch A This information is copied same as configured during RCU configuration for readout The Word ID is two most significant bits set to 10 showing that the word is part of RCU trailer 60 Act FEC B Active Front End Card List for Branch B Word ID Parameter Code Value 10 0101 Active Front End Cards on Branch B Description This trailer words contains the list of Active Front End Cards FECs in branch B This information is copied same as configured during RCU configuration for readout The Word ID is two most significant bits set to 10 showing that the word is part of RCU trailer where as the parameter code is 0101 61 RDO CONFIG 1 Read out Configuration 1 Copy of ALTRO Register DPCFG 1 Word ID Parameter Code Value Copy of ALTRO Register 1 11 ae Data Path Configuration 1 Description This trailer words is copy of Altro Register DPCFG 1 for TPC application for details please see ALTRO manual page 36 37 This register can be written as ALTROCFG1 at 0x5104 This register can be configured for any detector related information please consult page 13 of this manual 62 RDO CONFIG 2 Read out Configuration 2 Copy of ALTRO Register DPCFG 2 Word ID Parameter Code Value 10 0111 Copy of ALTRO Register Data Path Configuration 2 Description This trailer words is copy of Altro Register DPCFG 2 for TPC applicati

User Manual - ALICE TPC Front End Electronics

Contents

Download Pdf Manuals

Related Search

Related Contents