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uPD75P3018A DS - Renesas Electronics

1. 14 5 DIFFERENCES BETWEEN uPD75P3018A AND 4PD753012A 753016A AND 7530174 15 6 MEMORY CONFIGURATION eranc cc ere sro creen po Cr nage encarar ee pc 16 6 1 Program Co nter 16 6 2 Program Memory inerenti seats petu ra cents tabe ka nce nr 16 6 3 Data Memory 19 INSTRUCTION SET E 20 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY 30 8 1 Operation Modes for Program Memory Write Verify 30 8 2 Program Memory Write Procedure 31 8 3 Program Memory Read Procedure 32 8 4 One time PROM geee 33 9 ELECTRICAL SPECIFICATIONS 34 10 PACKAGE DRAWINGS 48 11 RECOMMENDED SOLDERING CONDITIONS 52 APPENDIX A uPD75316B 753017A AND 75P3018A FUNCTION LIST 55 APPENDIX B DEVELOPMENT TOOLS
2. 57 APPENDIX C RELATED DOCUMENTS 4 61 Data Sheet U11917EJ2V1DS 3 NEC uPD75P3018A 1 PIN CONFIGURATION Top View 80 pin plastic QFP 14 x 14 mm UPD75P3018AGC 3B9 75P3018AGC 3B9 A 75P3018AGC 8BT 75P3018AGC 8BT A 80 pin plastic TQFP fine pitch 12 12 mm uPD75P3018AGK BE9 75P3018AGK 9EU 75P3018AGK 9EU A sb CO QN CO 10 t CO QN 0000000000 00 D 080090 o E S120 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 o P60 KRO S130 20 59 X2 5140 3 58 o X1 5150 4 57 VppNote 5160 5 56 o XT2 S xm s5 o XT1 S180 7 54 Vpp S190 8 53 o P33 MD3 S20 o 52 o P32 MD2 210 51 o P31 SYNC MD1 22 0 50 o P30 LCDCL MDO 23 49 P23 BUZ 524 P22 PCL PTO2 S25 BP1 P21 PTO1 526 2 P20 PTOO 527 o P13 TIO 528 4 o P12 INT2 TI1 T12 29 5 o P11 INT1 530 o P10 INTO S31 BP7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 o POS SI SB1 O O gt 2 eran S58OrAMHYTNORYIXO 38 3 555008 95 289 SsaszpO 00900 82208550 9 Note Connect the Vp directly to Voo during normal operation PIN IDENTIFICATIONS BIAS LCD Power Supply Bias Control
3. rS detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0 10 mm of A 14 00 0 20 its true position T P at maximum material condition 12 00 0 20 12 00 0 20 14 00 0 20 1 25 1 25 I 0 05 0 221004 0 10 0 50 T P 1 00 0 20 0 50 0 20 0 055 0 1457 025 0 10 1 05 0 07 0 10 0 05 5 5 0 2 2 0 02 50 Data Sheet U11917EJ2V1DS 1 27 MAX P80GK 50 BE9 6 NEC uPD75P3018A 80 PIN PLASTIC TQFP FINE PITCH 12x12 detail of lead end Y 1 ITEM MILLIMETERS Each lead centerline is located within 0 08 mm of A 14 0 0 2 its true position T P at maximum material condition 12 0 0 2 12 0 0 2 14 0 0 2 1 25 1 25 0 22 0 05 0 08 0 5 1 0 0 2 0 5 0 145 0 05 0 08 1 0 0 1 0 05 ot 4 39736 1 1 0 1 0 25 0 6 0 15 P80GK 50 9EU 1 Zio u ZEI zx c I Irio Data Sheet U11917EJ2V1DS 51 NEC uPD75P3018A 11 RECOMMENDED SOLDERING CONDITIONS The uPD75P30184A should be soldered and mounted under the following recommended conditions F
4. 1 8 to 5 5 V Parameter Conditions LCD drive voltage 0 40 to 85 C Ta 10 to 85 C VACO 1 VAC 1 VACO 1 2 0 V 10 LCD output voltage lo 1 0 uA Vicpo Vico deviation Vicbi x 2 3 common Vicp2 Vicp x 1 3 LCD output voltage lo 20 5 uA 1 8 V Vico lt deviationNete 2 segment Supply current ee 3 6 0 MHzNe e4 Voo 5 0 V 10 Notes crystal 3 0 10 Note 6 oscillation HALT 5 0 V 10 C1 2 22 mode Von 3 0 V 10 4 19 216 4 Voo 5 0 41096 5 crystal 3 0 10 te6 oscillation HALT 5 0 V 10 C1 2 22 mode Von 3 0 V 10 32 768 Low 3 0 10 kl dzNete voltage 2 0 V 10 crystal mode 3 0 V Ta 25 C oscillation Low current consump tion modeNete 9 HALT Low 3 0 10 3 0 V 10 Voo 3 0 V Ta 25 C mode voltage Voo 2 0 V 10 mode 3 3 0 V Ta 25 C Low current consump Voo 3 0 V 410 tion 3 0 V Ta 25 C modeNetes 0 Vete Voo 5 0 V 10 STOP mode Voo 3 0 V 10 Notes 1 Clear VACO to 0 in the low current consumption mode and STOP mode When VACO is set to 1 the current increases by about 1 uA
5. Note For 2 fx during 6 0 MHz operation is 21 8 ms and during 4 19 MHz operation is 31 3 ms For 2 fx during 6 0 MHz operation is 5 46 ms and during 4 19 MHz operation is 7 81 ms Caution Noise resistance and noise radiation are different in PROM and mask ROMs In transferring to mask ROM version from the PROM version in a process between prototype development and full production be sure to fully evaluate the mask ROM version s CS not ES Data Sheet U11917EJ2V1DS 15 NEC uPD75P3018A 6 MEMORY CONFIGURATION 6 1 Program Counter PC 15 bits This is a 15 bit binary counter that stores program memory address data Bit 15 is valid during Mk mode But PC14 is fixed at zero during Mk mode and the lower 14 bits are all valid Figure 6 1 Configuration of Program Counter Fixed at zero during Mk mode PC 6 2 Program Memory PROM 32768 x 8 bits The program memory consists of 32768 x 8 bit one time PROM The program memory address can be selected as shown below by setting the stack bank selection SBS register i ode NK I Mode Usable address 0000H to 3FFFH 0000H to 7FFFH Figures 6 2 and 6 3 show the addressing ranges for the program memory and branch instruction and the subroutine call instruction during Mk and Mk II modes 16 Data Sheet U11917EJ2V1DS Figure 6 2 Program Memory Map Mk mode 5 0
6. lt 2 Notes 1 Shaded areas indicate support for Mk mode only Other areas indicate support for Mk mode only 2 Only the low order 3 bits in the B register are valid 24 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Instruction Group Bit transfer Mnemonic Operand CY fmem bit Machine Cycle Operation CY lt fmem bit Addressing Area Skip Condition CY pmem L CY lt pmem7 2 L3 2 bit L1 0 CY H mem bit lt H mems3 0 bit fmem bit CY fmem bit lt CY pmem L pmem7 2 L3 2 bit L1 0 lt CY H mem bit CY H mems3 0 bit lt CY Arithmetic A n4 lt 4 8 lt 8 A HL A lt A HL XA rp XA lt XA lt 1 A HL A CY A HL CY XA rp CY lt XA rp CY XA 1 CY lt 1 A HL lt A HL borrow XA rp XA lt XA rp borrow XA 1 lt rp1 XA borrow A HL A CY A HL CY XA rp CY lt XA rp 1 CY lt rp1 XA CY A n4 lt 4 A HL A A HL XA rp lt rp rp 1 lt rp1AXA A c Avn4 A HL A A v HL XA rp
7. IBM PC AT Refer to OS for 3 5 2HD LS7B13PG1500 or compatible IBM PCs Note Ver 5 00 or later includes a task swapping function but this software is not able to use that function Remark Operation of the PG 1500 controller is guaranteed only when using the host machine and OS described above 58 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Debugging Tools In circuit emulators IE 75000 R and 75001 are provided as program debugging tools for the uPD75P3018A Various system configurations using these in circuit emulators are listed below Hardware IE 75000 RNete 1 The IE 75000 R is an in circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products For development of the uPD75P3018A the IE 75000 R is used with optional emulation board IE 75300 R EM and emulation probe EP 753018GC R or EP 753018GK R Highly efficient debugging can be performed when connected to host machine and PROM programmer The IE 75000 R includes a connected emulation board IE 75000 R EM IE 75001 R The 75001 is an in circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products The IE 75001 R is used with optional emulation board IE 75300 R EM and emulation probe EP 753018GC R or EP 753018GK R Highly efficient debugging can be perform
8. No of stack bytes 2 bytes 3 bytes BRA addr1 instruction CALLA addr1 instruction Instruction Not available Available Instruction CALL addr instruction 3 machine cycles 4 machine cycles execution time instruction 2 machine cycles 3 machine cycles Supported mask ROMs When set to Mk mode LP D753012A 753016A and 753017 When set to Mk mode 753012 753016A and 753017A Caution The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series Therefore this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes With regard to the number of stack bytes during execution of subroutine call instructions the usable area increases by 1 byte per stack compared to the Mk mode when the Mk mode is selected However when the CALL addr and CALLF instructions are used the machine cycle becomes longer by 1 machine cycle Therefore if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility the Mk mode should be used Data Sheet U11917EJ2V1DS 13 NEC uPD75P3018A 4 2 Setting of Stack Bank Selection Register SBS Use the stack bank selection register to switch between mode and Mk mode Figure 4 1 shows the format for doing this The stack bank selection register is set using
9. tkso1 2 1 Data Sheet U11917EJ2V1DS 43 NEC uPD75P3018A Serial Transfer Timing Bus Release Signal Transfer 4 gt SCK tsiks 4 SBO 1 tksos 4 Command Signal Transfer SCK SBO 1 tksos 4 Interrupt Input Timing INTO 1 2 4 KRO 7 RESET Input Timing RESET 44 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Data retention characteristics of data memory in STOP mode and at low supply voltage Ta 40 to 85 C Parameter Data retention power supply voltage Conditions Release signal setup time isREL Oscillation stabilization wait timeNete 1 Released by RESET Released by interrupt request Notes 1 The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started 2 Set by the basic interval timer mode register BTM Refer to the table below Wait Time fx 4 19 MHz 220 fx approx 250 ms fx 6 0 MHz 22 approx 175 ms 217 fx approx 31 3 ms 2 7 fx approx 21 8 ms 2 5 fx approx 7 81 ms 2 3 fx approx 1 95 ms Data Retention Timing when STOP mode released by RESET 2 5 fx approx 5 46 ms 213 approx 1 37 ms Internal reset operation HALT mode Operation mode STOP mode
10. MD3 P33 32 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 8 4 One time PROM Screening Due to its structure the one time PROM cannot be fully tested before shipment by NEC Electronics Therefore NEC Electronics recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below the PROM should be verified via a screening Storage Temperature Storage Time Data Sheet U11917EJ2V1DS 33 NEC uPD75P3018A 9 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta 25 C Parameter Supply voltage Conditions Ratings 0 3 to 7 0 PROM supply voltage 0 3 to 413 5 Input voltage Other than ports 4 and 5 0 3 to 0 3 Ports 4 and 5 During N ch open drain 0 3 to 14 Output voltage 0 3 to 0 3 High level output current Per pin 10 Total of all pins 30 Low level output current Per pin 30 Total of all pins 220 Operating ambient temperature 40 to 4 85Nete Storage temperature Note To drive LCD in normal mode Ta 10 to 85 C 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter Thatis the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under condit
11. Data retention mode 7 STOP instruction execution RESET N Data Retention Timing standby release signal when STOP mode released by interrupt signal STOP instruction execution STOP mode HALT mode gt Operation mode Data retention mode Standby release signal interrupt request Data Sheet U11917EJ2V1DS 45 NEC uPD75P3018A DC Programming Characteristics TA 25 5 C 6 0 0 25 V 12 5 0 3 V Vss 0 V Parameter High level input voltage Conditions Pins other than X1 X2 X1 X2 Low level input voltage Pins other than X1 X2 X1 X2 Input leakage current Vin Vit or High level output voltage 1 mA Low level output voltage lo 1 6 mA Voo supply current supply current Cautions 1 Ensure that Ver does not exceed 13 5 V including overshoot MD1 2 must be applied before Vpr and cut after Vpr AC Programming Characteristics TA 25 5 C 6 0 0 25 V 12 5 10 3 V Vss 0 Parameter Address setup to MDOL Conditions setup time to MDOJ Data setup time to 00 Address hold from MDOT Data hold time from MDOT MDOT Data output float delay time Vr setup time to Voo s
12. Voltage deviation is the difference between the ideal values VLCDn n 0 1 2 of the segment and common outputs and the output voltage The current flowing through the internal pull up resistor is not included Including the case when the subsystem clock oscillates When the device operates in high speed mode with the processor clock control register PCC set to 0011 When the device operates in low speed mode with PCC set to 0000 When the device operates on the subsystem clock with the system clock control register SCC set to 1001 and oscillation of the main system clock stopped When the sub oscillation circuit control register SOS is set to 0000 When the SOS is set to 0010 When the SOS is set to 00 1 and the feedback resistor of the sub oscillator is cut x don t care poo 38 Data Sheet U11917EJ2V1DS NEC uPD75P3018A AC Characteristics Ta 40 to 85 C 1 8 to 5 5 V Parameter Conditions CPU clock cycle time Nete 1 Operation with 2 7 t0 5 5 V minimum instruction execution main system clock time 1 machine cycle Operation with subsystem clock TIO TI1 TI2 input frequency 2 7 to 5 5 V TIO TI2 input high tru tnu Voo 2 7 to 5 5 V low level width Interrupt input high low level tint width INT1 2 4 KRO 7 RESET low level width Notes 1 Thecycle time minim
13. 1 1 0000H Internal reset start address high order 6 bits Internal reset start address low order 8 bits 0002H 4 start address high order 6 bits 4 start address low order 8 bits CALLF instruction 0004H INTO start address high order 6 bits entry address INTO start address low order 8 bits 0006H INT1 start address high order 6 bits INT1 start address low order 8 bits BRCB 0008H INTCSI start address high order 6 bits oe INTCSI start address low order 8 bits 000AH INTTO start address high order 6 bits B h f INTTO start address low order 8 bits BR BCDE INTT1 INTT2 high 000CH start address high order 6 bits BCXA 2 start address low order 8 bits BR addr CALL addr Branch call address 0020H by GETI Reference table for GETI instruction ncc c 007FH BR addr instruction 0080H relative branch address 715 to 1 RENE 2 to 16 0800H OFFFH 1000H BRCB Icaddr instruction branch address RED Y 2000H BRCB Icaddr instruction branch address LRN RC Y 3000H BHCB Icaddr instruction branch address 3FFFH Y Y Remark Forinstructions other than those noted above the BR PCDE and BR instructions can be used to branch to addresses with changes in the PC s low order 8 bits only Data Sheet U11917EJ2V1DS 17 uPD75P3018A 0000H Internal reset start address hi
14. MD2 P32 t tussr MD3 P33 Data Sheet U11917EJ2V1DS 47 NEC uPD75P3018A 10 PACKAGE DRAWINGS 80 PIN PLASTIC QFP 14x14 48 NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition Data Sheet U11917EJ2V1DS detail of lead end rS ITEM MILLIMETERS A 17 2 0 4 14 0 0 2 14 0 0 2 17 2 0 4 0 825 0 825 0 30 0 10 0 13 0 65 T P 1 620 2 0 80 2 0 10 0 1579 05 0 10 2 7 0 1 0 10 1 57 59 0120 0 12 m e Ir O mn olol w 3 0 MAX S80GC 65 3B9 6 NEC uPD75P3018A 80 PIN PLASTIC QFP 14x14 detail of lead end rS NOTE ITEM MILLIMETERS Each lead centerline is located within 0 13 mm of 17 20 0 20 its true position T P at maximum material condition 14 00 0 20 14 00 0 20 17 20 0 20 0 825 0 825 0 32 0 06 0 13 0 65 1 60 0 20 0 80 0 20 1798 gt 0 10 1 40 0 10 0 125 0 075 ot7 3 4 1 70 MAX P80GC 65 8BT 1 D OD z T O mno ojo Data Sheet U11917EJ2V1DS 49 NEC uPD75P3018A 80 PIN PLASTIC TQFP FINE PITCH 12x12
15. PORT2 These are 4 bit pins for which an internal pull up resistor connection can be specified by software 1 2 LCDCL MDO SYNC MD1 MD2 This is a programmable 4 bit I O port PORT3 Input and output in single bit units can be specified When set for 4 bit units an internal pull up resistor connection can be specified by software P4 QNete 2 1 Note 2 P42Note 2 p4 Note 2 DO D1 D2 D3 This is an N ch open drain 4 bit I O port PORTA When set to open drain voltage is 13 V Also functions as data pin low order 4 bits for program memory PROM write verify p50Nete 2 P51 Note 2 2 2 2 4 5 D6 D7 This is an N ch open drain 4 bit port PORT5 When set to open drain voltage is 13 V Also functions as data pin high order 4 bits for program memory PROM write verify Notes 1 Circuit types enclosed in brackets indicate Schmitt trigger input 2 Low levelinputleakage current increases when input instructions or bit manipulation instructions are executed Data Sheet U11917EJ2V1DS High impedance High impedance NEC uPD75P3018A 3 1 Port Pins 2 2 Pin Name Alternate Function Function After Reset Circuit TypeNete 1 This is a programmable 4 bit I O port PORT6 Input and output in single bit units can be specified
16. Refer to OS for IBM PCs 3 5 2HC uS7B13DF753017 Note Ver 5 00 or later includes a task swapping function but this software is not able to use that function Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described above Data Sheet U11917EJ2V1DS 57 NEC uPD75P3018A PROM Write Tools Hardware PG 1500 This is a PROM programmer that can program single chip microcontroller with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter It can also program typical PROMs in capacities ranging from 256 K to 4 M bits PA 75P316BGC This is a PROM programmer adapter for the uPD75P3018AGC 3B9 It can be used when connected to a PG 1500 PA 75P316BGK This is a PROM programmer adapter for the uPD75P3018AGK BE9 It can be used when connected to a PG 1500 PA 75P3018AGC 8BT This is a PROM programmer adapter for the u PD75P3018AGC 8BT It can be used when connected to a PG 1500 PA 75P3018AGK 9EU This is a PROM programmer adapter for the u PD75P3018AGK 9EU It can be used when connected to a PG 1500 Software PG 1500 controller Connects PG 1500 to host machine with serial and parallel interface and controls PG 1500 on host machine Host machine Part No name OS Supply medium PC 9800 Series MS DOS 3 5 2HD uS5A13PG1500 Ver 3 30 to Ver 6 2Note
17. SP 3 SP 4 lt PC11 0 5 2 X X RBE PC14 0 13 0 lt taddr 5 0 taddr 1 When using instruction other than TBR or TCALL Execute taddr taddr 1 instructions Notes 1 Before executing the IN or OUT instruction set MBE to 0 or 1 and set MBS to 15 2 TBR and TCALL instructions are assembler pseudo instructions for the GETI instruction s table definitions 3 Shaded areas indicate support for Mk mode only Other areas indicate support for Mk mode only Data Sheet U11917EJ2V1DS Determined by referenced instruction 29 NEC uPD75P3018A 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY The program memory contained the uPD75P30184 is a 32768 x 8 bit one time PROM that can be electrically written one time only The pins listed in the table below are used for this one time PROM s write verify operations Clock input from the X1 pin is used instead of address input as a method for updating addresses Function Pin where program voltage is applied during program memory write verify usually potential Clock input pins for address updating during program memory write verify Input the X1 pin s inverted signal to the X2 pin MDO MD3 Operation mode selection pin for program memory write verify DO P40 to D3 P43 8 bit data pins for program memory write verify low order 4 bits D4 P50 to D7 P53 high order 4 bits Pin where power supply vol
18. When set for 4 bit units an internal pull up resistor connection can be specified by software This is a 4 bit I O port PORT7 When set for 4 bit units an internal pull up resistor connection can be specified by software 1 bit output port BIT PORT These pins are also used as segment output pin Notes 1 Circuit types enclosed in brackets indicate Schmitt trigger input 2 Vici is selected as the input source for BPO to BP7 The output level varies depending on the external circuit for BPO to BP7 and Vict Example As shown below BPO to are mutually connected via the uPD75P3018A so the output levels of BPO to BP7 are determined by the sizes of R Re and Ra R2 VLC1 R3 LA PD75P3018A Data Sheet U11917EJ2V1DS 7 NEC uPD75P3018A 3 2 Non port Pins 1 2 Pin Name Alternate Function Function After Reset Circuit TypeNete 1 Input P13 External event pulse input to timer event counter TI1 TI2 P12 INT2 PTOO Output P20 Timer event counter output P21 P22 P22 Clock output P23 Optional frequency output for buzzer or system clock trimming P01 Serial clock I O SO SBO P02 Serial data output Serial data bus SI SB1 Serial data input Serial data bus INT4 Edge detection vectored interrupt input both rising and falling edges detection INTO P1
19. XA lt v rp rp 1 lt 1 v XA A 4 A HL A v HL XA rp lt v rp rp lt 1 Accumulator manipulation A CY lt Ao lt CY 1 lt An A Increment decrement reg lt 1 lt 1 1 HL lt HL 1 mem lt mem 1 reg lt reg 1 lt 1 Data Sheet U11917EJ2V1DS 25 NEC uPD75P3018A Instruction Group Comparison Mnemonic Operand Machine Cycle Operation Skip if reg n4 Addressing Area Skip Condition reg n4 Skip if HL n4 HL n4 Skip if A HL A HL Skip if XA HL XA HL Skip if A reg A reg Skip if XA rp XA rp Carry flag manipulation CY 1 CY 0 Skip if CY 1 CY Memory bit manipulation 26 mem bit mem bit lt 1 fmem bit fmem bit lt 1 pmem L pmem7 2 L3 2 bit L1 0 lt 1 H mem bit H mems 0 bit lt 1 mem bit mem bit lt 0 fmem bit fmem bit lt 0 pmem L pmem7 2 L3 2 bit L1 0 lt 0 H mem bit H mems 0 bit lt 0 Skip if mem bit 1 mem bit 1 fme
20. minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressl
21. 0000H 3FFFH addr addr1 Current PC 15 to Current PC 1 Current PC 2 to Current PC 16 caddr 0000H 0FFFH PCt14 13 12 0008 or 1000H 1FFFH PC14 13 12 001B 2000H 2FFFH 14 13 12 010B 3000H 3FFFH PC14 13 12 011 or P 4000 4 PC14 13 12 1008 Mk II mode only deine 5000H 5FFFH 14 13 12 101B Mk mode only or 6000H 6FFFH 14 13 12 1108 Mk mode only or 7000H 7F7FH PC14 13 12 111B Mk Il mode only faddr 0000H 07FFH taddr 0020H 007FH 0000H 7FFFH mode only Remarks 1 MB indicates access enabled memory banks 2 In area 2 MB 0 for both MBE and MBS 3 In areas 4 and 5 MB 15 for both MBE and MBS 4 Areas 6 to 11 indicate corresponding address enabled areas 22 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 4 Description of machine cycles S indicates the number of machine cycles required for skipping of skip specified instructions The value of S varies as shown below Note 3 instructions BR addr BRA addr1 CALL CALLA laddr1 Caution The GETI instruction is skipped for one machine cycle One machine cycle equals one cycle tcv of the CPU clock Use the PCC setting to select among four cycle times Data Sheet U11917EJ2V1DS 23 NEC uPD75P3018A Instruction Group Mnemonic Operand A n4 Machine Cycle Oper
22. Ltd Madrid Spain Seoul Branch Tel 091 504 27 87 Seoul Korea Tel 02 558 3737 Succursale Francaise V lizy Villacoublay France NEC Electronics Shanghai Ltd Tel 01 30 67 58 00 Shanghai P R China a Tel 021 5888 5400 Filiale Italiana Milano Italy NEC Electronics Taiwan Ltd Tel 02 66 75 41 Taipei Taiwan Branch The Netherlands Te 0272719 2317 Eindhoven The Netherlands Tel 040 265 40 10 NEC Electronics Singapore Pte Ltd Novena Square Singapore e Tyskland Filial Tel 6253 8311 Taeby Sweden Tel 08 63 87 200 United Kingdom Branch Milton Keynes UK Tel 01908 691 133 405 6 Data Sheet U11917EJ2V1DS 63 NEC uPD75P3018A MS DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of International Business Machines Corporation These commodities technology or software must be exported in accordance with the export administration regulations of the exporting country Diversion contrary to the law of that country is prohibited The information in this document is current as of August 2005 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please che
23. Output Alternate Function Function Segment signal output After Reset Circuit Type 524 531 Output BPO BP7 Segment signal output 0 3 Output Common signal output VLCO VLC2 Power source for LCD driver BIAS Output Output for external split resistor cut High impedance LCDCLNete 2 P30 MDO Clock output for driving external expansion driver Input SYNCNete 2 P31 MD1 Clock output for synchronization of external expansion driver Input Notes 1 The Vicx X 0 1 2 shown below are selected as the input source for the display outputs 50 531 0 2 Vice Vico 2 These pins are provided for future system expansion Currently only P30 and P31 are used Data Sheet U11917EJ2V1DS NEC uPD75P3018A 3 3 Pin Input Output Circuits The input output circuits for the L PD75P30184A s pins are shown in abbreviated form below 1 2 O e 77 CMOS standard input buffer Output disable 777 Push pull output that can be set to high impedance output with both P ch and N ch OFF Data Output disable Schmitt trigger input with hysteresis characteristics P U R q P U R enable P U R Pull Up Resistor 10 Data Output disable Data Sheet U11917EJ2V1DS sexos IN OUT P U R Pull
24. P70 P73 Port7 7 Bit Port 0 7 PCL Programmable Clock BUZ Buzzer Clock PTOO PTO2 Programmable Timer Output 0 2 COMO COM3 Common Output 0 3 RESET Reset 00 07 Data Bus 0 7 S0 S31 Segment Output 0 31 INTO 1 4 External Vectored Interrupt 0 1 4 SBO SB1 Serial Bus 0 1 INT2 External Test Input 2 SCK Serial Clock KRO KR7 Key Return 0 7 SI Serial Input LCDCL LCD Clock SO Serial Output MDO MD3 Mode Selection 0 3 SYNC LCD Synchronization Porto TIO TI2 Timer Input 0 2 P10 P13 Port Positive Power Supply P20 P23 Port2 2 LCD Power Supply 0 2 P30 P33 Port3 VPP Programming Power Supply P40 P43 Port4 Vss Ground P50 P53 Port5 X1 X2 Main System Clock Oscillation 1 2 P60 P63 PortG XT1 XT2 Subsystem Clock Oscillation 1 2 4 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 2 BLOCK DIAGRAM 1 21 TIMERIEVENT COUNTER 1 1 2 P12 INT2 TIMER EVENT COUNTER 2 22 2 INTT24TOUTO BASIC INTERVAL TIMER WATCHDOG TIMER TIO P13 O 7 TIMER EVENT PTOO P200 COUNTER 0 INTWy SI SB1 P03 0 CLOCKED SO SBO P020 SCK P01 INTERFACE INTCSI TOUTO INTO P100 110 2 12 1 120 44 INTERRUPT INT4 P00 O CONTROL to KR7 P73 BIT SEQ BUFFER 16 GENERAL DECODE AND 32768 x
25. User s Manual EEU 967 EEU 1495 PG 1500 User s Manual U11940E U11940E Software RA75X Assembler Package Operation U12622J U12622E User s Manual Language U12385J U12385E PG 1500 Controller User s Manual PC 9800 Series EEU 704 EEU 1291 MS DOS base IBM PC Series EEU 5008 U10540E PC DOS base Other Related Documents Document No Document Name Japanese English SEMICONDUCTOR SELECTION GUIDE Products amp Package CD ROM Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices Electrostatic C11892J C11892bE Discharge ESD Guide to Microcontroller Related Products by Third Parties U11416J Caution The above related documents are subject to change without notice For design purpose etc be sure to use the latest documents Data Sheet U11917EJ2V1DS 61 NEC 62 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between MAX and MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the inpu
26. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offi
27. 0 Edge detection vectored interrupt input Noise elimination circuit detected edge is selectable asynchronous is selectable P11 INTO P10 can select noise elimination circuit Asynchronous INT2 P12 TH TI2 Rising edge detection testable input Asynchronous KRO KR3 P60 P63 Falling edge detection testable input KR4 KR7 P70 P73 Falling edge detection testable input X1 Ceramic crystal oscillation circuit connection for main system clock If using an external clock input to X1 and input X2 inverted phase to X2 Crystal oscillation circuit connection for subsystem clock If using an external clock input to XT1 and input inverted phase to XT2 XT1 can be used as a 1 bit test input System reset input low level active P30 LCDCL Mode selection for program memory PROM write verify P31 SYNC P32 P33 P40 P43 Data bus for program memory PROM write verify D4 D7 P50 P53 VppNote 2 Program power supply voltage for program memory write verify For normal operation connect directly to Apply 12 5 V for PROM write verify Positive power supply Ground Notes 1 Circuit types enclosed in brackets indicate Schmitt trigger input 2 The Vr pin does not operate correctly during normal operation unless connected to the pin 8 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 3 2 Non port Pins 2 2 Pin Name S0 S23
28. 1 lists differences among the u PD75P3018A and the uPD7530124A 753016A and 753017A Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or later when using them with a mask ROM for full scale production For the CPU functions and internal hardwares refer to 753017 User s Manual U11282E Table 5 1 Differences between uPD75P3018A and 753012 753016A and 753017A Item 753012 753016 uPD753017A uPD75P3018A Program counter 14 bits 15 bits Program memory bytes Mask ROM One time PROM During 12288 16384 Mk mode During 12288 32768 Mk II mode Data memory x 4 bits 1024 Mask options Pull up resistor for Yes Can be specified whether to incorporate or not No Cannot incorporate PORT4 and PORT5 LCD split resistor Feedback resistor Yes Can be specified whether to use or not No used for subsystem clock Wait time Yes Can be specified either 2 7 fx or 215 fx Nete No Fixed at 215 fx Nete during RESET Pin configuration Pin Nos 29 to 32 P40 to P43 40 00 to P43 D3 Pin Nos 34 to 37 P50 to P53 P50 D4 to P53 D7 Pin No 50 P30 LCDCL P30 LCDCL MDO Pin No 51 P31 SYNC P31 SYNC MD1 Pin Nos 52 and 53 P32 P33 P32 MD2 P33 MD3 Pin No 57 IC VPP Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts
29. 2768 x 8 bits RAM 1024 x 4 bits General purpose register 4 bit operation 8 x 4 banks 8 bit operation 4 x 4 banks Input output port CMOS input 8 On chip pull up resistor connection can be specified by using software 23 CMOS input output 16 CMOS output 8 Also used for segment pins N ch open drain input output 8 13 V breakdown voltage Total 40 LCD controller driver Segment number selection 24 28 32 segments can be changed to CMOS output port in unit of 4 max 8 Static 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias Display mode selection 5 channels 8 bit timer event counter 3 channels can be used for 16 bit timer event counter carrier generator timer with gate Basic interval timer watchdog timer 1 channel Watch timer 1 channel Serial interface 3 wire serial I O mode MSB or LSB be selected for transferring first bit 2 wire serial I O mode SBI mode Bit sequential buffer BSB 16 bits Clock output PCL 524 262 65 5 kHz main system clock at 4 19 MHz operation 750 375 93 8 kHz main system clock at 6 0 MHz operation Buzzer output BUZ 2 4 32 kHz main system clock at 4 19 MHz operation or subsystem clock at 32 768 kHz operation 2 93 5 86 46 9 kHz main system clock at 6 0 MHz operation Vectored interrupt Exte
30. 8 BITS CONTROL DATA MEMORY 1024 x 4 BITS PORTO 4 POO to PORT1 4 P10 to P13 PORT2 4 P20 to P23 P30 MDO to PORTS 4 p33 MD3 P40 DO to 4 P43 D3 P50 D4 to PORTS 4 P53 D7 PORT6 4 P60 to P63 PORT7 4 P70 to P73 S0 to S23 S24 BPO to S31 BP7 COMO to COMS3 fx 2N CPU CLOCK SYSTEM CLOCK CLOCK GENERATOR DIVIDER 1 PCL PTO2 P22 XT1XT2 X1 X2 Data Sheet U11917EJ2V1DS CONTROLLER DRIVER Vico to Vic2 BIAS LCDCL P30 MDO SYNC P31 MD1 4 4 Vss RESET VPP NEC uPD75P3018A 3 PIN FUNCTIONS 3 1 Port Pins 1 2 Pin Name POO P02 Alternate Function INT4 SCK SO SBO SI SB1 Function This is a 4 bit input port PORTO P01 to are 3 bit pins for which an internal pull up resistor connection can be specified by software After Reset Input Circuit TypeNete lt B gt lt F gt A lt F gt B lt gt 10 11 12 P13 INTO TH TI2 INT2 TIO This is a 4 bit input port PORT1 These are 4 bit pins for which an internal pull up resistor connection can be specified by software P10 INTO can select noise elimination circuit lt B gt C P20 P21 P22 P23 PTOO PTO1 PCL PTO2 BUZ This is a 4 bit I O port
31. 8 V 2 7 V Ports 0 1 6 7 RESET 27 lt lt 5 5 1 8 V lt Voo lt 2 7 V Ports 4 5 2 7 V lt Voo lt 5 5 V N ch open drain 1 8 V lt Voo lt 2 7 V X1 XT1 Low level input Ports 2 to 5 2 7 V lt Voo lt 5 5 V voltage 1 8 V lt Voo lt 2 7 V Ports 0 1 6 7 RESET 2 7 V lt 5 5 V 1 8 V lt 2 7 V X1 XT1 High level output SCK SO Ports 2 3 6 7 BPO to BP7 xxx voltage lou 2 1 0 mA Low level output SCK SO Ports 2 to 7 lo 2 15 mA voltage BPO to BP7 4 5 to 5 5 V lo 1 6 mA 5 0 SB1 N ch open drain Pull up resistor gt 1 High level input ViN Pins other than X1 XT1 leakage current X1 XT1 Ports 4 5 N ch open drain Low level input Pins other than X1 XT1 Ports 4 5 leakage current X1 XT1 Ports 4 5 N ch open drain When input instruction is not executed Ports 4 5 N ch open drain When input Vop 2 5 0V instruction is executed Voo 3 0 V High level output Vout SO SBO 5 1 Ports 2 3 6 7 leakage current Vout 13 V Ports 4 5 N ch open drain Low level output Vout 0 V leakage current Internal pull up Ports 0 to 3 6 7 except pin resistor Data Sheet U11917EJ2V1DS 37 NEC uPD75P3018A DC Characteristics TA 40 to 85 C
32. IET2 IEO IE2 4 IEW RBO RB3 MBO MB3 MB15 Note When processing 8 bit data only even numbered addresses can be specified 20 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 2 Operation legend A A register 4 bit accumulator B B register C C register D D register E E register H H register L L register X X register XA Register pair XA 8 bit accumulator BC Register pair BC DE Register pair DE HL Register pair HL XA Expansion register pair BC Expansion register pair BC DE Expansion register pair DE HL Expansion register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn 0107 Interrupt master enable flag IPS Interrupt priority selection register IEXXX Interrupt enable flag RBS Register bank selection register MBS Memory bank selection register PCC Processor clock control register Delimiter for address and bit XX Addressed data XXH Hexadecimal data Data Sheet U11917EJ2V1DS 21 NEC uPD75P3018A 3 Description of symbols used in addressing area MB MBE MBS MBS 0 3 15 MB 0 000H 07FH Data memory MB 15 F80H FFFH addressing MBS MBS 0 3 15 MB 15 fmem FBOH FBFH FFOH FFFH MB 15 pmem FCOH FFFH a addr
33. PD75P3018AGC 3B9 A 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm LuPD75P3018AGC 8BT 80 pin plastic QFP 14 x 14 mm resin thickness 1 4 mm UPD75P3018AGC 8BT A 80 pin plastic QFP 14 x 14 mm resin thickness 1 4 mm LPD75P3018AGK BE9 80 pin plastic TQFP fine pitch 12 x 12 mm resin thickness 1 05 mm uPD75P3018AGK 9EU 80 pin plastic TQFP fine pitch 12 x 12 mm resin thickness 1 00 mm uPD75P3018AGK 9EU A 80 pin plastic TQFP fine pitch 12 x 12 mm resin thickness 1 00 mm Caution Mask option pull up resistors are not provided in this device Remark Products with A at the end of the part number are lead free products The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information Document U11917EJ2V1DS00 2nd edition The mark shows major revised points Date Published August 2005 N CP K Printed in Japan NEC Electronics Corporation 1997 2000 NEC uPD75P3018A FUNCTION OUTLINE Item Function Instruction execution time 0 95 1 91 3 81 15 3 main system clock at 4 19 MHz operation 0 67 1 33 2 67 10 7 us main system clock at 6 0 MHz operation 122 us subsystem clock at 32 768 kHz operation Internal memory PROM 3
34. To our customers Old Company Name in Catalogs and Other Documents On April 15 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 15 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 5 5 10 11 12 Notice information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is
35. Up Resistor P U R enable IN OUT O lt Type P U R Pull Up Resistor NEC uPD75P3018A 2 2 P U R enable Output VDD disable D FOE Pon IN OUT Data Output disable gt Bit Port Output data disable Output N disable P U R Pull Up Resistor P U R P U R enable P ch IN OUT o Daia J Output disable 77 lt P U R Pull Up Resistor E 1 9IN OUT Voltage controller 413 V withstand voltage Note Pull up resistor operated only when executing input instructions when pins are low level current flows from to pins Data Sheet U11917EJ2V1DS 11 NEC uPD75P3018A 3 4 Recommended Connection for Unused Pins 12 POO INT4 Recommended Connection Connect to Vss or 1 5 P02 SO SBO Connect to Vss via resistor individually POS SI SB1 Connect to Vss P10 INTO P11 INT1 P12 TH TIZ INT2 P13 TIO Connect to Vss or P20 PTOO P21 PTO1 P22 PTO2 PCL P23 BUZ P30 LCDCL MDO P31 SYNC MD1 P32 MD2 P33 MD3 Input Connectto Vssor resistor individually Output Leave open P40 DO P43 D3 P50 D4 P53 D7 Connect to Vss P60 KRO P63 KR3 P70 KR4 P73 KR7 Input Connect
36. a 4 bit memory manipulation instruction When using the Mk mode be sure to initialize the stack bank selection register to 10 at the beginning of the program When using the Mk II mode be sure to initialize it to OOXXBN Note Set the desired value for XX Figure 4 1 Format of Stack Bank Selection Register Address 1 0 Symbol 5851 5850 585 Stack area specification 3 2 F84H Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 0 Be sure to set bit 2 00 Mode selection specification Mk mode Mk mode Cautions 1 SBS3is to 1 after RESET input and consequently the CPU operates mode When using instructions for Mk Il mode set SBS3 to 0 and set Mk Il mode before using the instructions 2 When using Mk mode execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register 14 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 5 DIFFERENCES BETWEEN 4PD75P3018A AND 4PD7530124A 753016A AND 753017A The uPD75P3018A replaces the internal mask ROM in the 753012 7530164 and 75301 7A with a one time PROM and features expanded ROM capacity The uPD75P3018A s mode supports the Mk mode in the 753012 753016A and 753017A and the uPD75P3018A s Mk Il mode supports the Mk mode in the uPD753012A 7530164 and 753017 Table 5
37. artment TEL 81 3 3820 7112 Osaka Electronics 2nd Department TEL 81 6 6244 6672 Ver 5 00 or later includes a task swapping function but this software is not able to use that function Operation of the IE control program is guaranteed only when using the host machine and OS described above Data Sheet U11917EJ2V1DS 59 NEC uPD75P3018A OS for IBM PCs The following operating systems for the IBM PC are supported Version PC DOS Ver 5 02 to Ver 6 3 J6 1 V to J6 3 V MS DOS Ver 5 0 to Ver 6 22 5 0 V to 6 2 V DOS J5 02 V Caution Ver 5 0 or later includes a task swapping function but this software is not able to use that function 60 Data Sheet U11917EJ2V1DS NEC uPD75P3018A APPENDIX C RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Device Related Documents Document No Document Name Japanese English 753012 753016 753017A Data Sheet U11662J U11662E uPD75P3018A Data Sheet U11917J U11917E This document 753017 User s Manual U11282J U11282E 753017 Instruction Table IEM 5598 75XL Series Selection Guide U10453J U10453E Development Tool Related Documents Document No Document Name Japanese English Hardware IE 75000 R IE 75001 R User s Manual EEU 846 EEU 1416 IE 75300 R EM User s Manual U11354J U11354E EP 753017GC GK R
38. at 200 C or higher Count Twice or less VP15 00 2 Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once Preheating temperature 120 C max package surface temperature WS60 00 1 Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating Remark For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 52 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Table 11 1 Surface Mounting Type Soldering Conditions 2 3 3 uPD75P3018AGK BE9 80 pin plastic TQFP fine pitch 12 x 12 mm resin thickness 1 05 mm Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max IR35 107 3 at 210 C or higher Count Three times or less Exposure limit 7 days ete after that prebake at 125 C for 10 to 72 hours Package peak temperature 215 C Time 40 seconds max VP15 107 3 at 200 C or higher Count Three times or less Exposure limit 7 days after that prebake at 125 C for 10 to 72 hours Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use differen
39. ation 2 byte stack Mk mode 2 byte stack Mk mode 3 byte stack Instruction BRA CALLA addr1 MOVT XA BCDE MOVT XA BCXA BR BCDE BR BCXA Unavailable mode unavailable Mk mode available Available CALL addr 3 machine cycles Mk mode 3 machine cycles Mk Il mode 4 machine cycles CALLF faddr 2 machine cycles Mk mode 2 machine cycles Mk Il mode 3 machine cycles Mask option Yes None Timer 3 channels Basic interval timer 1 channel 8 bit timer event counter 1 channel Watch timer 1 channel Data Sheet U11917EJ2V1DS 5 channels Basic interval timer watchdog timer 1 channel 8 bit timer event counter 3 channels can be used as 16 bit timer event counter carrier generator timer with gate Watch timer 1 channel 55 NEC uPD75P3018A uPD75316B 753017 75 3018 Clock output PCL 524 262 65 5 kHz 524 262 65 5 kHz Main system clock Main system clock at 4 19 MHz operation at 4 19 MHz operation 750 375 93 8 kHz Main system clock at 6 0 MHz operation BUZ output BUZ 2 kHz 2 4 32 kHz Main system clock Main system clock at 4 19 MHz operation or at 4 19 MHz operation subsystem clock at 32 768 kHz operation 2 93 5 86 46 9 kHz Main system clock at 6 0 MHz operation Serial interface 3 modes are available 3 wire seria
40. ation Ac n4 Addressing Area Skip Condition String effect A reg n4 regie n4 XA n8 lt n8 String effect A HL 8 HL n8 String effect B rp2 8 rp2 n8 A HL A HL HL then L lt L 1 A HL then L L 1 A 1 XA lt HL A HL A HL XA A mem lt mem lt lt A lt XA lt rp reg1 regi A NIN lt XA A HL HL A HL then L lt 1 1 A A 1 A c lt gt lt gt HL then L lt 1 1 lt gt 1 XA XA e HL A mem A mem XA mem lt gt mem A reg1 A lt gt regt XA rp XA rp Table reference M OV TNote 1 XA PCDE XA lt PC13 8 DE Rom XA PCXA lt PC14 84 DE ROM lt PC13 8 XA ROM lt PC14 8 XA ROM BCDE lt BCDE RoM ete 2 lt 2 lt
41. ce equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
42. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electr
43. ck with an NEC Electronics sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To
44. dering methods together except for partial heating Remarks 1 Products with at the end of the part number are lead free products 2 For soldering methods and conditions other than those recommended above contact NEC Electronics sales representative 54 Data Sheet U11917EJ2V1DS NEC uPD75P3018A APPENDIX A 75316 753017A AND 75P3018A FUNCTION LIST 75316 753017 5 018 Program memory Mask ROM 0000H 3F7FH 16256 x 8 bits Mask ROM 0000H 5FFFH 24576 x 8 bits One time PROM 0000H 7FFFH 32768 x 8 bits Data memory 000H 3FFH 1024 x 4 bits CPU 75X Standard 75XL CPU Instruction execution time When main system clock is selected 0 95 1 91 or 15 3 us at 4 19 MHz operation 0 95 1 91 3 81 or 15 3 us at 4 19 MHz operation 0 67 1 33 2 67 or 10 7 us at 6 0 MHz operation When subsystem clock is selected 122 us at 32 768 kHz operation Pin connection 29 to 32 P40 to P43 40 00 to P43 D3 34 to 37 P50 to P53 P50 D4 to P53 D7 44 P12 INT2 P12 INT2 TH TI2 47 21 P21 PTO1 48 P22 PCL P22 PCL PTO2 50 to 53 P30 to P33 P30 MDO to P33 MD3 57 IC SBS register None SBS 3 1 Mk mode selection SBS 3 0 Mk II mode selection Stack area 000H 0FFH nOOH nFFH n 0 3 Subroutine call instruction Stack oper
45. e SBI mode SCK external clock input slave TA 40 to 85 1 8 to 5 5 V Parameter Conditions SCK cycle time Von 2 7 to 5 5 V 800 3200 SCK high low level width 2 7 to 5 5 V 400 1600 SBO 1 setup time 2 7 10 5 5 V 100 to SCK 1 150 SBO 1 hold time from SCK 1 2 SCK gt SBO 1 output 4 1 Note 2 7 to 5 5 V 0 delay time C 100 pF 0 SCK gt 880 1 SBo 1 1 gt SCK SBO 1 low level width SBO 1 high level width Note Ri and respectively indicate the load resistance and load capacitance of the SBO 1 output line Data Sheet U11917EJ2V1DS 41 NEC uPD75P3018A AC Timing Test Points except X1 and XT1 inputs MIN MIN Vit MAX MAX MIN MIN Vor Vor MAX Clock Timing 1 fx txt lt 0 1 V X1 input 0 1V 1 fxr 0 1 V XT1 input 0 1V TIO TH TI2 Timing 1 fn tri 1 TIO TH 112 42 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Serial Transfer Timing 3 wire Serial I O Mode tkcy1 2 TKL1 2 2 SCK tksi1 2 tsik1 2 tkso1 2 2 wire Serial I O Mode tkcy1 2 2 SCK SBO 1
46. ed when connected to host machine and PROM programmer IE 75300 R EM This is an emulation board for evaluating application systems using the 75 018 It is used in combination with the IE 75000 R or IE 75001 R EP 753018GC R EV 9200GC 80 This is an emulation probe for the uPD75P3018AGC When being used it is connected with the IE 75000 R or IE 75001 R and the IE 75300 R EM It includes a 80 pin conversion socket EV 9200GC 80 to facilitate connections with target system 753018GK R TGK 080SDW ere This is an emulation probe for the uPD75P3018AGK When being used it is connected with the IE 75000 R or IE 75001 R and the IE 75300 R EM It includes a 80 pin conversion adapter TGK 080SDW to facilitate connections with target system Software Notes 1 2 Remark IE control program This program can control the IE 75000 R or IE 75001 R on a host machine when connected to the IE 75000 R or IE 75001 R via an RS 232 C or Centronics interface Host machine Part No name OS Supply medium PC 9800 Series MS DOS 3 5 2HD 55 131 75 5 2HD uS5A10IE75X Ver 3 30 to Ver 6 2Note 3 IBM PC AT Refer to OS for 3 5 2HC 7 1 75 or compatible IBM PCs 5 2HC 57 101 75 This is a maintenance product This is a product of TOKYO ELETECH CORPORATION For further information contact Daimaru Kogyo Ltd Tokyo Electronics Dep
47. emory address by one Repeat steps 6 to 9 until the end address is reached Select the zero clear program memory address mode Return the Voo and Vr pins back to 5 V Turn off the power The following figure shows steps 2 to 9 00 40 to D3 P43 x D4 P50 to D7 P53 Data input output ata input X repetitions P Address Additional increment Write Verify write MDO P30 7 MD1 P31 N MD2 P32 MD3 P33 Data Sheet U11917EJ2V1DS 31 NEC uPD75P3018A 8 3 Program Memory Read Procedure The uPD75P3018A can read program memory contents using the following procedure 1 Pull unused pins to Vss through resistors Set the X1 pin low 2 Supply 5 V to the and Vr pins Wait 10 us 4 Select the zero clear program memory address mode 5 Supply 6 V to the and 12 5 to the pins Select the verify mode Apply four pulses to the X1 pin Every four clock pulses will output the data stored in one address 3 Select the zero clear program memory address mode 5 Return the Voo and Vr pins back to 5 V Turn off the power The following figure shows steps 2 to 7 VPP VPP VDD VDD 1 487 i VDD 0450 to 07153 Data output D4 P50 to D7 P53 Data output Data output MDO P30 x S MD1 P31 E M Moz Ps2
48. etup time to MD3T Initial program pulse width Additional program pulse width MDO setup time to MD17 MDO Data output delay time MD1 Vi hold time from MDOT gt 50 us recovery time from Program counter reset time X1 input high low level widths tx X1 input frequency Initial mode setting time setup time to MD17 hold time from MD1J setup time to MDOJ Program memory read Data output delay time from address ete Program memory read Data output hold time from address ete Program memory read hold time from MDOT Program memory read Data output float delay time Program memory read Notes 1 Symbol of corresponding uPD27C256A 2 The internal address signal is incremented by 1 on the 4th rise of the X1 input and is not connected to a pin 46 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Program Memory Write Timing m lvPs Voo m tvps 1 x1 00 40 03 43 04 50 07 53 ti MD1 P31 MD2 P32 MD3 P33 Program Memory Read Timing D0 P40 D3 P43 D4 P50 D7 P53 MD1 P31 2
49. gh order 6 bits Internal reset start address low order 8 bits 0002H INTBT INT4 start address high order 6 bits INTBT INT4 start address low order 8 bits 0004H INTO start address high order 6 bits INTO start address low order 8 bits 0006H INT1 start address high order 6 bits INT1 start address low order 8 bits 0008H INTCSI start address high order 6 bits INTCSI start address low order 8 bits 000AH INTTO start address high order 6 bits INTTO start address low order 8 bits 000CH INTT1 INTT2 start address high order 6 bits INTT2 start address low order 8 bits Figure 6 3 Program Memory Map Mk II mode 0 CALLF instruction entry address BRCB instruction branch address BR Branch addresses for the following instructions BR BCDE BR BCXA addr1 CALLA addr1 BR addr1 instruction relative branch address 715 to 1 2 to 16 Reference table for GETI instruction laddr instruction branch address CALL laddr instruction branch address 07FFH 0800H 0020H 007FH 0080H OFFFH 1000H 1FFFH 2FFFH 3000H 3FFFH 400H 4FFFH 5000H 5FFFH 6FFFH Y 1 instruction branch address 1 BRCB instruction branch addres
50. granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
51. hod Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max 60 207 3 at 220 C or higher Count Three times or less Exposure limit 7 days ete after that prebake at 125 C for 20 to 72 hours Wave soldering For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating Remarks 1 Products with at the end of the part number are lead free products 2 Forsoldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 6 uPD75P3018AGK 9EU A 80 pin plastic TQFP fine pitch 12 x 12 mm resin thickness 1 00 mm Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max IR60 207 3 at 220 C or higher Count Three times or less Exposure limit 7 days after that prebake at 125 C for 20 to 72 hours Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 or less and 65 RH or less for the allowable storage period Caution Do not use different sol
52. ion and coding formats for operands In the instruction s operand area use the following coding format to describe operands corresponding to the instruction s operand representations for further description see the RA75X Assembler Package User s Manual Language U12385E When there are several codes select and use just one Codes that consist of uppercase letters and or symbols are key words that should be entered as they are For immediate data enter an appropriate numerical value or label Enter register flag symbols as label descriptors instead of mem fmem pmem bit etc For details refer to the uPD753017 User s Manual U11282E The number of labels that can be entered for fmem and pmem are restricted Representation Coding Format A L D L BC DE HL BC DE HL BC DE XA BC DE HL BC DE HL BC DE HL XA BC DE HL HL HL HL DE DL DE DL 4 bit immediate data or label 8 bit immediate data or label 8 bit immediate data or labelNete 2 bit immediate data or label FBOH FBFH FFOH FFFH immediate data or label FCOH FFFH immediate data or label 0000 3 immediate data or label 0000H 7FFFH immediate data or label Mk mode only 12 bit immediate data or label 11 bit immediate data or label 20H 7FH immediate data however bitO 0 or label PORTO PORT7 IEBT IECSI IETO IET1
53. ions that ensure that the absolute maxim Capacitance Ta 25 0 V Parameter Input capacitance Output capacitance 1 capacitance 34 um ratings are not exceeded Conditions f21MHz Unmeasured pins returned to 0 V Data Sheet U11917EJ2V1DS NEC uPD75P3018A Main System Clock Oscillator Characteristics Ta 40 to 85 C 1 8 to 5 5 V Resonator Recommended Circuit Parameter Conditions Ceramic resonator Oscillation frequency 6 0Note 2 fx Nete 1 Oscillation After has stabilization timeNe e3 reached MIN value of oscillation voltage range Crystal resonator Oscillation frequency 6 0 1 Oscillation Voo 4 5 to 5 5 V 10 stabilization timeNete3 30 External clock Notes 1 Caution Remark X1 input frequency 6 0792 fx Nete X1 input high low level width txt The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only For the instruction execution time refer to AC Characteristics If the oscillation frequency is 4 19 MHz fx lt 6 0 MHz at 1 8 V lt 2 7 V do not select processor clock control register PCC 0011 If PCC 0011 one machine cycle is less than 0 95 falling short of the rated value of 0 95 us The oscillation stabilization time is the time required for oscilla
54. ire serial 1 modes SCK external clock input TA 40 to 85 C 1 8 to 5 5 V Parameter Conditions SCK cycle time 2 7 to 5 5 V SCK high low level width Voo 2 7 to 5 5 V SlNetet setup time to SCK T tse 2 7 to 5 5 V hold time from 7 tksiz 2 7 to 5 5 V J gt 5 output 1 Nete2 2 7 to 5 5 V delay time 100 pF Notes 1 2 wire serial 1 mode read SBO or SB1 instead 2 C respectively indicate the load resistance and load capacitance of the SO output line 40 Data Sheet U11917EJ2V1DS NEC uPD75P3018A SBI mode SCK internal clock output master TA 40 to 85 C 1 8 to 5 5 V Parameter Conditions SCK cycle time 2 7 to 5 5 V 1300 3800 SCK high low level width 2 7 to 5 5 V 2 50 2 150 1 setup time 2 7 10 5 5 V 150 to SCK 500 380 1 hold time from SCK 1 2 SCK 4 gt SBO 1 output Ri 1 Note 2 7 to 5 5 V 0 delay time 100 pF 0 SCK gt SBO 11 SBO 1 gt SCK1 SBO 1 low level width SBO 1 high level width Note and respectively indicate the load resistance and load capacitance of the SBO 1 output lin
55. l I O mode MSB LSB can be selected for transfer first bit 2 wire serial mode SBI mode SOS register Feedback resistor cut flag None Provided SOS 0 Sub oscillator current None Provided cut flag SOS 1 Register bank selection register RBS None Yes Standby release by INTO Unavailable Available Interrupt priority selection register IPS None Yes Vectored interrupt External 3 Internal 3 External 3 Internal 5 Supply voltage Voo 2 0 to 6 0 V 1 8 10 5 5 V Operating ambient temperature Ta 40 to 85 C Package 80 pin plastic TQFP fine pitch 12 x 12 mm 80 pin plastic QFP 14 x 14 mm 56 Data Sheet U11917EJ2V1DS NEC uPD75P3018A APPENDIX B DEVELOPMENT TOOLS The following development tools have been provided for system development using the uPD75P3018A In the 75XL Series the relocatable assembler common to series is used in combination with the device file of each type RA75X relocatable assembler Device file Host machine OS Supply medium Part No name PC 9800 Series MS DOS Ver 3 30 to Ver 6 2Note 3 5 2HD LS5A13RA75X PC AT or compatible Host machine Refer to OS for IBM PCs 3 5 2HC OS Supply medium LS7B13RA75X Part No name PC 9800 Series MS DOS Ver 3 30 to Ver 6 2Note 3 5 2HD uS5A13DF753017 IBM PC AT or compatible
56. lt SP 6 CALL Note SP 4 SP 1 SP 2 lt PC11 0 3 MBE PC13 12 14 lt 0 PC13 0 lt SP lt SP 4 5 5 lt 0 14 12 SP 6 SP 3 SP 4 lt PC11 0 SP 2 X X MBE PC14 lt 0 PC13 0 lt addr SP lt 5 6 Ifaddr SP 4 SP 1 SP 2 lt PC11 o SP 3 lt MBE 13 12 14 lt 0 PC13 0 lt 000 faddr SP lt SP 4 5 5 lt 0 PC14 12 SP 6 SP 3 SP 4 PC11 0 2 X X MBE 14 0 lt 0000 faddr SP lt 6 MBE PC13 12 lt SP 1 PC11 0 lt SP SP 3 SP 2 PC14 lt 0 SP lt SP 4 X X MBE lt SP 4 0 PC14 12 lt 1 PC11 0 lt SP SP 3 SP 2 SP lt 5 6 RETSNete MBE PCt13 12 lt SP 1 Unconditional PC11 0 lt SP SP 3 SP 2 14 lt 0 SP lt SP 4 then skip unconditionally X X MBE RBE lt SP 4 0 PC14 12 SP 1 PC11 0 lt SP SP 3 SP 2 SP SP 6 then skip unconditionally RETINote MBE RBE PC13 12 lt SP 1 14 0 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 0 PC14 12 SP 1 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP 5 6 Note Shaded areas indicate support for Mk mode only Other areas indicate support for Mk mode only 28 Data Sheet U11917EJ2V1DS NEC uPD75P3018A Instruction Group Subr
57. m bit Skip if fmem bit 1 fmem bit 1 pmem L Skip if pmem7 2 L3 2 bit L1 0 1 H mem bit Skip if H mems o bit 1 pmem L 1 H mem bit 1 mem bit mem bit 0 fmem bit Skip if fmem bit 0 fmem bit 0 pmem L Skip if omem7 2 L3 2 bit L1 0 0 pmem L 0 H mem bit Skip if H mems o bit 0 H mem bit 0 SKTCLR fmem bit Skip if mem bit 0 Skip if fmem bit 1 and clear fmem bit 1 pmem L Skip if pmem7 2 L3 2 bit L1 0 1 and clear pmem L 1 H mem bit Skip if H mems o bit 1 and clear H mem bit 1 CY fmem bit CY lt CY fmem bit CY pmem L CY lt CY pmem7 2 L3 2 bit L1 0 CY H mem bit CY lt C H memz3 o bit CY fmem bit CY CY v fmem bit CY pmem L CY lt v pmemr 2 L3 2 bit L1 o CY H mem bit CY fmem bit CY lt fmem bit CY pmem L CY lt CY v CY v pmem7 2 L3 2 bit L1 0 CY H mem bit PY lt C v H mems3 0 bit Data Sheet U11917EJ2V1DS NEC uPD75P3018A Instruction Mnemonic Group BRNete 1 Operand Machine Cycle Operation 14 lt 0 PC13 0 lt addr Use the assembler to select the most appropriate instruction among the follo
58. onics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 8 0 DATASHEET RENESAS MOS INTEGRATED CIRCUIT uPD75P3018A 4 BIT SINGLE CHIP MICROCONTROLLER DESCRIPTION The uPD75P3018A replaces the uPD753017A s internal mask ROM with a one time PROM and features expanded ROM capacity The uPD75P3018A inherits the function of the 75 3018 and enables high speed operation at a low supply voltage of 1 8 V Because the wPD75P3018A supports programming by users it is suitable for use in evaluation of systems in development stages using the 753012 7530164 or 7530174 and for use small scale production The following document describes further details of the functions Please make sure to read this document before starting design 753017 User s Manual 011282 FEATURES Compatible with 753017 Memory capacity PROM 32768 x 8 bits RAM 1024 x 4 bits Can operate in the same power supply voltage as the mask version 753017 1 8 to 5 5 V LCD controller driver ORDERING INFORMATION Part Number Package LuPD75P3018AGC 3B9 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm u
59. or technical information see the following website Semiconductor Device Mount Manual http www necel com pkg en mount index html 1 uPD75P3018AGC 3B9 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm Soldering Method Infrared reflow Table 11 1 Surface Mounting Type Soldering Conditions 1 3 Soldering Conditions Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Three times or less Recommended Condition Symbol IR35 00 3 VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher Count Three times or less VP15 00 3 Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once Preheating temperature 120 C max package surface temperature WS60 00 1 Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating Remark For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 2 uPD75P3018AGC 8BT 80 pin plastic QFP 14 14 mm resin thickness 1 4 Soldering Method Infrared reflow Soldering Conditions Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count Twice or less Recommended Condition Symbol IR35 00 2 VPS Package peak temperature 215 C Time 40 seconds max
60. outine stack control Mnemonic Operand Machine Cycle Operation SP 1 SP 2 lt rp SP lt SP 2 Addressing Area Skip Condition SP 1 MBS 5 2 lt RBS SP lt 5 2 rp lt SP 1 SP SP lt SP 2 MBS lt SP 1 RBS lt SP SP lt SP 2 Interrupt control IME IPS 3 1 IEXXX 1 IME IPS 3 0 IEXXX IEXXX 0 1 A PORTn lt 0 7 lt PORTn 1 1 4 6 UTNete 1 PORTn A PORTn A 2 7 PORTn 1 PORTn lt 4 6 CPU control Set HALT Mode PCC 2 lt 1 Set STOP Mode PCC 3 lt 1 No Operation RBS n n 0 3 mnm MBS lt n n 0 3 15 GET Nete 2 3 Co When using instruction PC13 0 lt taddr 5 0 taddr 1 PC14 lt 0 When using TCALL instruction SP 4 SP 1 SP 2 lt PC11 0 SP 3 lt MBE PC 3 12 lt 0 PC13 0 lt taddr 5 0 taddr 1 When using instruction other than TBR or TCALL Execute taddr taddr 1 instructions Determined by referenced instruction When using TBR instruction PC13 0 lt taddr 5 0 taddr 1 PC14 lt 0 When using TCALL instruction 5 lt 0 PC14 12 SP 6
61. rnal Internal 3 5 Test input External 1 Internal 1 System clock oscillator Ceramic or crystal oscillator for main system clock oscillation Crystal oscillator for subsystem clock oscillation Standby function STOP HALT mode Power supply voltage 1 8 to 5 5 V Package 80 pin plastic QFP 14 x 14 mm 80 pin plastic TQFP fine pitch 12 x 12 mm Data Sheet U11917EJ2V1DS NEC uPD75P3018A CONTENTS 1 PIN CONFIGURATION Top View ccccsssscceessssceceesnsecceeeseeseeeeensnsneeeeensnseeeeensenseesseesnsneeseoes 4 2 2 A 5 3 PIN FUNCTIONS 6 34 PINS E H I 6 3 2 Pins orn rd rar osa tea ria a ko agna dpa akin ER Ra 8 3 3 Pin InpUt OUtPUt Circuits eicere 10 3 4 Recommended Connection for Unused Pins eese nennen nennen nnne nennt 12 4 SWITCHING FUNCTION BETWEEN Mk MODE AND 13 4 1 Difference between Mk Mode and Mk Mode 13 4 2 Setting of Stack Bank Selection Register SBS
62. s 1 instruction branch goes Branch call address by GETI 1 instruction branch 1 BRCB instruction branch address 1 BRCB instruction branch address 1 BRCB instruction 7FFFH branch address Caution 0000H to 3FFFH Remark to addresses with changes in the PC s low order 8 bits only 18 Data Sheet U11917EJ2V1DS To allow the vectored interrupt s 14 bit start address noted above set the address within a 16K area For instructions other than those noted above the BR PCDE and BR PCXA instructions can be used to branch NEC uPD75P3018A 6 3 Data Memory RAM 1024 x 4 bits Figure 6 4 shows the data memory configuration Data memory consists of a data area and a peripheral hardware area The data area consists of 1024 x 4 bit static RAM Figure 6 4 Data Memory Map Data memory Memory bank 4 i 000H General purpose register area 01FH 020H 100H 1DFH 1 Display data memory 1FFH 200H Data area static RAM 1024 x 4 Stack area Note 2FFH 300H Not incorporated i F80H Peripheral hardware area 128 x 4 15 FFFH Y Note Memory bank 1 2 or 3 can be selected as the stack area Data Sheet U11917EJ2V1DS 19 NEC uPD75P3018A 7 INSTRUCTION SET 1 Representat
63. signal or 1 pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Data Sheet U11917EJ2V1DS uPD75P3018A NEC uPD75P3018A Regional Information Some information contained in this document may vary from country to country Before using any NEC Electronics product in your application please contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors They will verify Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country GLOBAL SUPPORT http www necel com en support support html NEC Electronics America Inc U S NEC Electronics Europe GmbH NEC Electronics Hong Kong Ltd Santa Clara California Duesseldorf Germany Hong Kong Tel 408 588 6000 Tel 0211 65030 Tel 2886 9318 800 366 9782 Sucursal en Espa a NEC Electronics Hong Kong
64. t level passes through the area between MAX and MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be to
65. t soldering methods together except for partial heating Remark For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 4 uPD75P3018AGK 9EU 80 pin plastic TQFP fine pitch 12 x 12 mm resin thickness 1 00 mm Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max IR35 107 2 at 210 C or higher Count Twice or less Exposure limit 7 days e e after that prebake at 125 C for 10 to 72 hours Package peak temperature 215 C Time 40 seconds max VP15 107 2 at 200 C or higher Count Twice or less Exposure limit 7 days e e after that prebake at 125 C for 10 to 72 hours Partial heating Pin temperature 350 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating Remark For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative Data Sheet U11917EJ2V1DS 53 NEC uPD75P3018A Table 11 1 Surface Mounting Type Soldering Conditions 3 3 5 uPD75P3018AGC 3B9 A 80 pin plastic QFP 14 x 14 mm resin thickness 2 7 mm UPD75P3018AGC 8BT A 80 pin plastic QFP 14 x 14 mm resin thickness 1 4 mm Soldering Met
66. tage is applied Applies Voo 1 8 to 5 5 V in normal operation mode 6 V for program memory write verify Caution Pins not used for program memory write verify should be connected to Vss via a resistor individually 8 1 Operation Modes for Program Memory Write Verify When 6 is applied to the pin and 12 5 V to the VPP pin the wPD75P3018A enters the program memory write verify mode The following operation modes can be specified by setting pins MDO to MD3 as shown below Operation Mode Specification Operation Mode MD1 Zero clear program memory address Write mode Verify mode Program inhibit mode X L or H 30 Data Sheet U11917EJ2V1DS NEC uPD75P3018A 8 2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure 1 2 2 3 4 5 6 7 8 9 Se YS 0 1 2 3 Pull unused pins to Vss through resistors Set the X1 pin low Supply 5 V to the and Vr pins Wait 10 us Select the zero clear program memory address mode Supply 6 V to the and 12 5 V to the Ver pins Write data in the 1 ms write mode Select the verify mode If the data is correct go to step 8 and if not repeat steps 6 and 7 X number of write operations from steps 6 and 7 x 1 ms additional write Apply four pulses to the X1 pin to increment the program m
67. tion to be stabilized after Voo has been applied or STOP mode has been released When using the main system clock oscillator wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with other signal lines Do not route the wiring in the vicinity of a line through which a high alternating current flows Always keep the ground point of the capacitor of the oscillator at the same potential as Do not ground to a power supply pattern through which a high current flows Do not extract signals from the oscillator For the resonator selection and oscillator constant customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation Data Sheet U11917EJ2V1DS 35 NEC Subsystem Clock Oscillator Characteristics TA 40 to 85 C 1 8 to 5 5 Resonator Recommended Circuit Parameter Conditions Crystal resonator Oscillation frequency fxr Nete 1 Oscillation Vop 4 5 to 5 5 V stabilization timeNete External clock Notes 1 Caution Remark 36 XT1 input frequency fxr Nete 1 XT1 input high low level width xr The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillator only For the ins
68. to Vss or via a resistor individually Output Leave open 50 523 524 531 7 COM0 COM3 Leave open VLCO VLC2 Connect to Vss BIAS Connectto Vss only when to 2 are all not used In other cases leave open XT1 Note Connect to Vss XT2 Note Leave open Note When subsystem clock is not used specify 505 0 1 indicates that internal feedback resistor is disconnected Data Sheet U11917EJ2V1DS NEC uPD75P3018A 4 SWITCHING FUNCTION BETWEEN Mk MODE AND MODE Setting a stack bank selection SBS register for the uPD75P3018A enables the program memory to be switched between mode and II mode This function is applicable when using the uPD75P3018A to evaluate the 753012 7530164 or 7530174 When the SBS bit is set to 1 sets Mk mode supports Mk mode for 753012 7530164 and 7530174 When the SBS bit is set to 0 sets Mk mode supports Mk Il mode for 753012 753016A and 7530174 4 1 Difference between Mk Mode and Mk Il Mode Table 4 1 lists points of difference between the Mk mode and the Mk II mode for the wPD75P3018A Table 4 1 Difference between Mk I Mode and Mk Il Mode Program counter Mk Mode PC13 0 14 is fixed at 0 Mk Mode Program memory bytes 16384 Data memory bits 1024 4 Stack Stack bank Selectable via memory banks 0 to 3
69. truction execution time refer to AC Characteristics The oscillation stabilization time is the time required for oscillation to be stabilized after has been applied When using the subsystem clock oscillator wire the portion enclosed in the broken line in the above figure as follows to prevent adverse influence due to wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with other signal lines Do not route the wiring in the vicinity of a line through which a high alternating current flows Always keep the ground point of the capacitor of the oscillator at the same potential as Do not ground to a power supply pattern through which a high current flows Do not extract signals from the oscillator The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator Therefore exercise utmost care in wiring the subsystem clock oscillator For the resonator selection and oscillator constant customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation Data Sheet U11917EJ2V1DS uPD75P3018A NEC uPD75P3018A DC Characteristics TA 40 to 85 1 8 to 5 5 V Parameter Conditions Low level output Per pin current Total of all pins High level input Ports 2 3 2 7 V lt 5 5 voltage 1
70. uched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels 1 settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an pull up power supply while the device is not powered The current injection that results from input of such a
71. um instruc tion execution time of the CPU tcv vs clock is determined by the with main system clock oscillation frequency of the connected resonator and external clock the system clock control register SCC and processor clock control register Operation PCC guaranteed range The figure on the right shows the supply voltage vs cycle time tcy characteristics when the device operates with the main system clock Cycle time tcy us 2 2tcy or 128 fx depending on the setting of the interrupt mode register IMO Supply voltage Vpp V Data Sheet U11917EJ2V1DS 39 NEC uPD75P3018A Serial transfer operation 2 wire and 3 wire serial 1 modes SCK internal clock output TA 40 to 85 C Voo 1 8 to 5 5 V Parameter Conditions SCK cycle time 2 7 to 5 5 V 1300 3800 SCK high low level width tk tkH1 2 7 to 5 5 V 2 50 1 2 150 1 1 setup time to SCK 7 tsi 2 7 to 5 5 V 150 500 51 1 hold time from 2 7 10 5 5 V 400 J gt SOete output 1 Nete2 2 7 to 5 5 V delay time 100 pF Notes 1 In 2 wire serial I O mode read SBO or SB1 instead 2 and respectively indicate the load resistance and load capacitance of the SO output line 2 wire and 3 w
72. wing BR laddr BRCB caddr BR addr Addressing Area Skip Condition PC14 0 lt addr1 Use the assembler to select the most appropriate instruction among the following BRA addr1 BR laddr BRCB caddr laddr 14 lt 0 PC13 0 lt addr addr PC14 lt 0 PC13 0 lt addr addr1 14 0 lt 14 lt 0 PC13 0 lt PC13 8 DE 14 0 lt PCi4 8 DE 14 lt 0 PC13 0 lt PC13 8 XA 14 0 lt 14 8 14 lt 0 PC13 0 lt BCDENete 2 PC14 0 lt BCDENte PC14 0 PC13 0 lt BCXANete2 PC14 0 lt BCXANete2 BR ANote 1 14 lt 0 PC13 0 lt addr 14 0 lt BRCBNete 1 Icaddr 14 lt 0 PC13 0 lt PC13 12 caddr11 0 14 0 lt PC14 13 12 caddr11 0 Notes 1 Shaded areas indicate support for Mk mode only Other areas indicate support for Mk mode only 2 The only following bits are valid in the B register For Mk mode Low order 2 bits For Mk mode Low order bits Data Sheet U11917EJ2V1DS 27 NEC uPD75P3018A Instruction Mnemonic Operand Machine Operation Addressing Skip Group Cycle Area Condition Subroutine CALLA te laddr1 5 lt 0 14 12 stack control SP 6 SP 3 SP 4 lt PC11 0 2 X X MBE 14 0 lt addr1 SP
73. y specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1

uPD75P3018A DS - Renesas Electronics

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