SMT317 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. 1 is a header located to the left of the JTAG pins JMP2 is a header to the right closer to the TIM connector The Jumpers JPx are numbered from the left to the right JP1 JP2 JP3 for each connector JMPx JP1 JP2 refer to the following link positions on JMPx JP1 JP2 JP3 Figure 6 JUMPER JMPx 16 1 JMP1 Control Comm port Select Em pe pe een ror NA Table 2 Comm port selection Version 6 1 20 24 SMT317 User Manual 16 2 JMP2 SDB Clock speed select and external trigger e SDB Clock speed select N A N A Table 3 Clock speed selection e External trigger JP2 is used to apply the external trigger signal The trigger signal is different depending of the mode selected e n burst mode the trigger is an edge e n continuous mode the trigger is a level The user has to make sure he inputs the right external trigger signal according to the mode selected Version 6 1 Page 21 of 24 SMT317 User Manual 17 Input Circuitry The jumper located near the channel input connector is used to select the input mode If the jumper is installed it selects single ended input C11 C10 100nF 1uF REF1 ADC R11 R1 R4 510K Ji R2 510K Ri 276 VIN ADC 2 ru 4 HJ 5 LO VIN ADC C7 220pF R6 510K R5 276 J2 1 sat OPA2350 JMP2 R7 10K Figure 7 ADC Input circuitry Version 6 1 22 24 SMT317 User Manual2. 13 1 Programmable Clock Divider A 4 bit divider is provided which allows generating up to 16 different clock frequencies for the ADC clock from the on board reference clock ADC Clock Frequency 18 8 Divider Value 1 MHz Sampling frequency ADC Clock 16 The programmable divider on default setting is to divide by 16 The programmable divider has no effect on an external clock 13 2 LED 1 The LED 1 is lit when the 511x16 bit FIFO is full In order to clear the overrun the user has to clear the SDB receiver s FIFO and send a new control word to the SMT317 13 3 Synchronization signal It s a pulse active high If the internal synchronization signal is selected bit23 1 as soon as a control word is received a pulse is generated internally to synchronize all the ADCs If the external synchronization signal is selected bit23 0 the user has to send a pulse active high to the SMT317 via the SYNC connector to make sure all the ADCs are synchronized together 13 4 Trigger In Continuous mode The trigger is a level As long as the trigger is active the data are sent to the DSP board via the SDB The active level is selectable The trigger can be active high bit26 1 or active low bit26 0 In Burst mode The trigger is an edge In the case of an internal trigger every time a new control word is sent with burst mode selected and internal trigger selected then a new burst mode occurs In the case of an external trigg
3. 17 1 SDB Pinout Function Function aw s s ara fe joue e n Jmm Go v NW _ bw m ww _ Gp zs zs DATA em 2 m qwe DATA13 eno sr Gp ss _ REQ 38 37 WEN Table 4 SDB Pinout Version 6 1 23 24 18 Example Code Code to use with a smt335 SMT317 User Manual Comm port 1 SMT335 have to be connected to the Comm port 3 SMT317 SDB SMT317 is linked with the SDB B SMT335 include lt stdio h gt include lt sema h gt include thread h include smt317v2 h include Fast FpgaConf c include sdb h VA E o Ae Ae e d PROTOTYPES ok kk ak oe o oo void fil internal b void void Fast FpgaConf int len unsigned int b int link no void calloc size t num size t size J BK KKK e ke e ee e eoe ee e ee e eoe e eoe e eoe e HK define BURSTIK IntClk IntTrigger low IntSync 0X49ea0101 SEMA internal filled b int samplestore main Corresponds to the only bitstream in the Dat2asm bat file extern far int fpga count extern far unsigned int fpga data l int control word Version 6 1 24 24 SMT317 User Manual Allocation of a memory space to store the samples samplestore int calloc BUFFER SIZE sizeof int if samplestore NULL amp samplestore_slave NULL p
4. 4 Outline Desc 7 5 Power UP Em 8 6 ADC Sub Sy Sei 8 x Input SUR a ie 8 627 Ou tp t ees Ne 8 7 Communication ports nn ain ee 9 Pla OVVIE TT 9 B SDB eee 10 9 Data formatting METER 10 MEE GEI em 11 10 1 ADCS Sampling Glock eee eee 11 10 2 SDB output CIOGKR eue esse 11 10 9 COVENT WEG PFIEDS ex xn reete EU xxu eene 12 12 11 4 configuration em 12 12 ADOSUIOOR ese 12 ADO 13 1341 Programmable Clock Divider 14 13 27 MED T TT 14 13 3 Synchronization SIGN Alls usa cuo eee eee 14 Qn nn 14 13 5 Control register description ss 15 14 Connectors and Jumpers Positions 17 Version 6 1 Page 4 of 24 SMT317 User Manual 1B 18 M Ugo CCS 19 16 1 JMP1 Control Comm port 19 16 2 2 SDB Clock speed select and external trigger 20 ABLE CIO etr a eine 21 17 1 0 e 22 1B Example COC 23 Figure 1 Register FORMAN sese eee eee 6 Figure 2 Notational convention eee 6 Figure 3 Block Diagram assit ordeo ctp eee 7 Figure 4 ADCs control register
5. Manual 10 3 Overflowed FIFOs In the case the receiving device has a FIFO which is becoming full the ACK signal on the SDB connector can be used to suspend SDB data transmission whichever mode is selected continuous mode or burst mode As soon as the ACK signal is released the transmission continues Indeed when a data is written in a 511x16 bit FIFO this data is immediately read and sent via the SDB to the DSP But if the ACK signal on the SDB is active the sampled data are stored in the 511x16 bit FIFO The data are outputted on the SDB cable as soon as the ACK signal is not active anymore If the 511x16 bit FIFO becomes full when the ACK signal is still active the LED is lit In order to clear the overrun the user has to clear the SDB receiver s FIFO and send a new control word to the SMT317 11 FPGA A Field Programmable Gate Array FPGA is used to manage the ADC data acquisition implement one communication ports and one Sundance Digital Bus 11 1 Fpga configuration The Virtex FPGA from Xilinx is volatile in nature and requires reconfiguring every time the module is powered on The configuration data bitstream must be presented through Comm port 3 The bitstream is supplied on the distribution disk as fpga_smt317v2 bit Please refer to the SMT6500 help file in the section FPGA type TIM configuration for more information When the module is not configured LED5 will be illuminated Upon successful configu
6. User Manual Half pwr Half Power See ADC Datasheet AD7723 Half pwr 0 Continuous mode 1 selects the Continuous continuous mode Continuous mode mode Continuous mode 0 selects the burst mode Active level trigger 1 active high or rising edge trigger Active level E Active level trigger trigger 99 Active level trigger 0 active low or falling edge trigger Internal trigger 1 selects the Internal internal trigger Ws Trigger logic Internal trigger O selects the external trigger To drive the internal trigger in continuous mode only enable signal Trigger int Trigger signal Count data fifo 0000 256 samples Count data fifo 0001 512 samples Count data 1 0 0010 1 Number of data to be transferred during burst operation Count data fifo 0011 2 Count data Count data fifo 0100 Only used in burst mode Bit1 6Bit31 Bit3OBit29 Count data_fifo 0101 8Ksamples Count data fifo 0110 6Ksamples Elo up to Count data fifo 1111 8Msamples Table 1 Control Register description Continuous mode 0 Active level Trigger 0 Internal_ Trigger 0 Trigger_int l Count data fifo 3 0 0000 Version 6 1 Page 17 of 24 SMT317 User Manual Remark The trigger signal is different depending of the mode selected e n burst mode the trigger is an edge e n continuous mod
7. end is inserted in the opposite sense to the other One end must have the b ue backing facing out and the other must have the silver backing facing out The SMT320 SMT310Q motherboard communicates with the host PC using comm port 3 of the site 1 TIM You should not make any other connections to this comm port On the SMT317 e Comm port 3 is used for the FPGA configuration It is the only way to configure the FPGA e Comm port is used for both configuring the FPGA and afterwards for controlling the ADCs data acquisition In that configuration you save one connection in your system e Nevertheless if your application requires using a different Comm port to control the acquisition the FPGA configuration can only be done via Comm port3 please contact Sundance as a custom version of the firmware with more connections could be developed for you e The control comm port selection is achieved by setting e JMP1 Control Comm port Select The standard version of the firmware only provides Comm port 3 Version 6 1 10 of 24 SMT317 User Manual 8 SDB The SMT317 provides one Sundance Digital Bus SDB This 16 bit data parallel link for synchronous transmission can achieve high speed data transfer across 40 way flat ribbon cables with ground interlaced 3 3v signals Ref SMT3xx SDB CAB The SDB is connected directly to the Virtex device The SDB implementation on this module operates as an output only Th
8. SMT317 User Manual Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Version 6 1 Page 2 of 24 SMT317 User Manual Revision History Date Comments 16 11 01 Major changes 3 0 28 11 01 Reduction to Comm port 3 only for ADC control E 3 1 Comm port 13 12 01 SMT317v2 4 0 e Xilinx XCV300 Virtex FPGA only e Addition of a internal trigger e Addition of features in the ADC control 21 02 02 Addition of Bookmarks and hyperlinks 4 1 PL nm n 28 02 02 Explanation of the trigger signal 4 2 STT 21 04 02 Addition of paragraph 11 f 5 Up dates related to the firmware v2 2 08 07 02 14 2 jumper position correction 5 1 29 11 02 1 02 Minor changes 5 2 01 09 05 Data packeting detailed Addition of 1 extra bit E P 6 0 control register for burst size Remove of 100 MHz SDB clock option New SMT6500 support Version 6 1 Page 3 of 24 SMT317 User Manual Table of Contents Revision History sise 2 OT Contents SES an ne do roues 3 Table of UU Saeco ee ne tn a 4 Table SS 4 9 1 5 le H 6 CNN Oo 6 B Notational COTA MTN uoce e ent e ei ver elt uentus 6
9. e the trigger is a level The user has to make sure he inputs the right external trigger signal according to the mode selected 14 Connectors and Jumpers Positions dme SERIO SERIO om lt lt EIR in i S L 5855551858555518 5855551858555518 HHHEDHHHHIEHHLEHHHHEHHERHHHHEEHEDHHEFH HI JI gb 5 g TU am a cxx HN L RS 3902 BN T JMP1 JMP2 oo B Bes caa vu Figure 5 SMT317v2 top view Version 6 1 Page 18 of 24 SMT317 User Manual 15 Connectors SYN connector bottom right end side of the top view is for synchronising all ADCs operated from a common master clock It allows each ADC to simultaneously sample its analog input and update its output register See ADC Datasheet AD7723 CLOCK connector bottom right end side of the top view is for the external clock CH X are the analog inputs The connector of the channel 7 is very close to the 3 3V However the ADC female connector is connected to the ground It s very important to check that the ADC female connector and the 3 3V are not in contact to avoid any short cut which could damage the system The best is to have a straight ADC female connector instead of a right angled connector for this channel Version 6 1 19 of 24 SMT317 User Manual 16 Jumpers
10. e user defined pins UDO UD1 are not used The write enable pin WEN is driven active low by the SMT317 when it is transmitting data on the SDB The SDB drives at LVTTL levels The SDB pinout is described in Table 4 The SDB interface present in the SMT317 implements a flow control meaning that when the receiver on the other end stops receiving the data is not overwritten but pills up in the SMT317 s own FIFO until it is full Only then data is overwritten The SDB interface provides a 511 position FIFO Each position is 32 bit wide The 16 bit SDB interface only transfers multiples of 32 bit words Only one transfer speed is available on the SMT317 SDB released after 01 09 2005 The clock speed is 50 MHz You should refer to SDB specifications V2 0 and above for technical information 9 Data formatting The sampled data is output on the SDB Sundance Digital Bus connector The physical link presents ADC samples one at a time 16 bit wide but the SMT317 packets ADC data samples by pairs and sends multiples of 2 x 16 bit packets with the least significant bit being sent on DO The channels are paired in the following manner Cho Ch4 Ch1 Ch5 Ch2 Ch6 Ch3 Ch7 Version 6 1 Page 11 of 24 SMT317 User Manual Enabling a pair of channels is done by setting any one or both of the two control bits corresponding to the 2 channels from that pair in the control register described further down Only the data corresponding to the
11. elect External clock CONFIG CPLD Internal sync on Comm port3 omm por O External SYNC b 409 PRIMARY Figure 3 Block Diagram Version 6 1 Page 8 of 24 SMT317 User Manual 5 Power up sequence At power up the config CPLD waits for a bitstream to configure the FPGA The Virtex FPGA from Xilinx is volatile in nature and requires reconfiguring every time the module is powered on From the moment the module is powered on to the time when the FPGA is configured e The ADC sampling clock is the external clock beware to respect the maximum frequency rating see ADC Datasheet AD7723 e The ADC SYNC See ADC Datasheet AD7723 signal is maintained high to keep the ADCs in reset state After the FPGA is configured the ADC controls default to the values in Table 1 Control Register description 6 ADC Sub System It consists of 8 Analog Devices AD7723 converters These provide an overall system performance with an ENOB of 14 minimum for each of the eight channels All ADCs simultaneously sample using the same clock 6 1 Input Level The input to the ADC module is DC coupled with a pk pk level of 4v This is centred about Ov Vminz 2v Vmax 2v 6 2 Output Codes The converted samples are presented on the SDB connector as 16 bits twos complement binary Code 0x8000 is equivalent to Vmax Code 0x0000 is equivalent to OV Code Ox7FFF is equivalent t
12. enabled channel pairs will be output on the SDB On the start of a new acquisition in continuous or burst mode the data from the channel pair selected with the smallest channel number is always output first For example Ch0 Ch4 data is always output before Ch2 Ch6 data Then samples are output by increasing channel pair number for the selected channel pairs 10 Clock selection 10 1 ADCs Sampling clock All ADCs are sampled at the same time The clock source can either be the onboard oscillator or an external clock Therefore the sampling frequency is either given by the clock divider setting for the onboard clock or by the external clock the external clock is not affected by the clock divider setting 10 2 SDB output clock For firmware versions released before 01 09 2005 the SMT317 module allows for the SDB word rate to be set to either 50 or 100MHz as set by JMP2 SDB Clock speed select A lower word rate may be needed when the receiving device is not able to sustain the faster transfer speed In firmware versions released after 01 09 2005 the SDB clock is no more selectable and the samples are output at a default 50Mhz clock frequency which can easily sustain the data rate required by the ADC data If the SDB data transmission is not suspended by the ACK signal and that there are samples buffered in the SMT317 FIFO the samples are output at the SDB output clock frequency Version 6 1 12 of 24 SMT317 User
13. er the burst mode occurs as soon as an edge is detected on JP2 of JMP2 0 The trigger is edge selectable Bit26 1 the burst is triggered on a rising edge Bit26 0 the burst is triggered on a falling edge Version 6 1 Page 15 of 24 SMT317 User Manual 13 5 Control register description The following table describes how behave the different fields of the control register depending on their value FIELD DESCRIPTION ACTION DEFAULT ADC Clock Frequency CLKDIV 0 18 8 Mhz CLK DIV Clock divider CLKDIV 1 9 4 Mhz CLKDIV 15 CLKDIV 2 6 27 Mhz CLKDIV 3 4 7 Mhz CLKDIV 15 1 17 Mhz Rst_SDB 1 Clear outgoing SDB FIFO and send a Reset SDB for the receiving end Reset only valid Rst SDB Reset FIFO for SMT332 372 Rst SDB 0 Can be used to synchronise data at the receiving end ADC Channel 1 enables ADC channel CHx enable in outgoing CHx 1 SDB FIFO 0 disables channel x IM LEDx 0 lights LEDx LEDx illumination LED 4 2 101 LEDx 1 turns LEDx off EXT 1 selects external clock EXT Clock EXT 0 selects internal clock MODE MODE 0 e 0 1 See ADC Datasheet AD7723 G a 1 In 1 ace MODE 120 Internal SYNC 1 an internal pulse is sent to SYNC Internal Synchronisation Internal SYNC 0 an external Internal SYNC SYNC logic signal is used for SYNC 0 See ADC Datasheet AD7723 about SYNC function Version 6 1 16 of 24 SMT317
14. er for the analog components on this module All of the analog circuitry is shielded on the top and bottom of the module using custom RFI shielding cans 3 Notational convention The format of registers is described using a diagram of the following form SESS Ss LED 4 2 W 000000000000 W 100 W 000000000 W 10000000 Figure 1 Register Format The digits at the top of the diagram indicate bit positions within the register and the central section names bits or bit fields The bottom row describes what may be done to the field and its value after reset Shaded fields are reserved and should only ever be written with zeroes Readable by the CPU W Writeable by the CPU Readable and writeable by the CPU Binary digits indicate the value of the field after reset Figure 2 Notational convention Version 6 1 Page 7 of 24 SMT317 User Manual 4 Outline Description The SMT317v2 module is an ADC based size 1 TIM offering the following features e Eight 16 bits ADCs running at an output word rate of up to 1 2 MHz for input bandwidths up to 460 kHz Xilinx XCV300 Virtex FPGA e FPGA programming via communication port comm port3 e High bandwidth data via 1 Sundance Digital Bus SDB JUMPERS 7 0 ADC SUB SYSTEM Clock Buffer uonoejes 01 U09 42019 Sample clock Local clock VIRTEX 37 6 MHz Clock s
15. o Version 6 1 Page 9 of 24 SMT317 User Manual 7 Communication ports 7 1 Overview The SMT317 communication port is an 8 bit data parallel link that follows Texas Instruments TMS320C4x Communication Port standard Additional information on the standard is available in the TMS320C4x Users Guide chapter 12 Communication ports and the Texas Instrument Module Specification The standard gives a TIM six links numbered from 0 to 5 Each link can be a transmitter or a receiver and will switch automatically between these states depending on the way you use it Writing to a receiver or reading from a transmitter will cause a hardware negotiation token exchange that will reverse the state of both ends of the link Following a processor reset the first three links 0 1 and 2 initialise as transmitters and the remainder 3 4 and 5 initialise as receivers When you wire TIMs together you must make sure that you only ever connect links initialising as transmitters to links initialising as receivers never connect two transmitters or two receivers For example connecting link O of one TIM to link 4 of another is safe connecting link O of one TIM to link 2 of another could damage the hardware Always connect comm ports 0 1 or 2 to comm ports 3 4 or 5 On SMT320 SMT310Q carrier board the physical connection between comm ports is made with FMS cables You must be careful when connecting the cables and make sure that one
16. ration LED5 will extinguish LED5 located near TIM connector 12 ADCs Clock Source The sample rate of the ADCs is derived from one of two sources either from an external clock input or via the on board reference The on board reference clock is generated by a 37 6 MHz oscillator The highest ADC clock frequency generated by the on board clock is 18 8 MHz which can be divided up to 16 times See Table 1 Control Register description The maximum external ADC clock frequency is 19 2MHz This should be TTL compatible It is not possible to divide the external clock using the Programmable Clock Divider Version 6 1 Page 13 of 24 SMT317 User Manual The buffered external clock is used directly as the ADCs sample clock 13 ADC Control All of the ADCs are controlled via the comm port 3 The comm port 3 must be selected using the jumper bank JMP1 Control Comm port Select The ADC control is provided by configuring a single control register It allows control for the clock divider the clock selection the trigger source the mode the ADC enable and the state of three LEDs This register is described here bit Count data fifo LED 4 2 Trigger int Internal trigger Active trigger level Continuous mode Internal Sync Extra Count data fifo z o Not Used CLK DIV Figure 4 ADCs control register Version 6 1 Page 14 of 24 SMT317 User Manual
17. rintf memory allocation was successful n else exit 1 printf Address of samplestore 08x n samplestore Jo e e eoe CONFIGURATION xoc printf nFirst bitstream n Fast FpgaConf fpga count fpga data COMMPORT1 printf NnEND Mn JC eee ACOUISITION exeo e eoe e eoo SDB init SDB CLROF SDB CLRIF SDB CLK DB CLROF SDB CLRIF SDB control word BURSTIK IntClk IntTrigger link out word control word COMMPORT1 sema init amp internal filled b 0 thread new fill internal b 1000 0 sema wait amp internal filled Dp printf done n void fill internal b void x SDB read BUFFER SIZE sizeof int samplestore SDB B sema signal amp internal filled
18. sse esse eee 13 Figure 5 SMT317v2 1 ViIGW sse eee eee 17 Figure 6 JUMPER nement aE 19 Figure 7 ADC 21 Table of tables Table 1 Control Register description 16 Table 2 Comm port seleciion 19 Table 3 Clock speed selection 20 Table 4 SDB Pinous 22 Version 6 1 Page 5 of 24 SMT317 User Manual Overview The SMT317v2 is a size 1 TIM offering the following features e Communication ports for control e 8 channels 16 bit simultaneous sample ADC e High bandwidth data output via a single 16 bit SDB Sundance Digital Bus Version 6 1 Page 6 of 24 SMT317 User Manual 1 EMC This module is designed to operate from within an enclosed host system which is built to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot 2 Power This module must be fixed to a TIM40 compliant carrier board Additionally a 3v3 power source must be provided to the fixings This is normally achieved by means of a power source provided directly through conducting pillars on the carrier board On board dc dc converters provide pow
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