Home

MN101E01K/01L/01M/F01M LSI User`s Manual

1. L 4 2 114055 182005 01025 0 14025 u 5198098 LWd09S SI8S00S OWd00S YIG0OS 5098095 3dN09S 115005 92025 1005 15 1098 JMuHg800S lt LSN1T09S m 3788005 0SN109S 0005 L 0 zdWOooS 0 09 095 0 iawoos Y LNOZWL 1 5 x 1189 lt BUFO a 3 15 porem s Oul UOISSIUISUEJ 250 OulLOOS lt i 8 L Jejunoo r lt KAW 1 0025 5 AS8109S K uoneiouab 54 Y z lt sn 9019 ASHH09S 9481901 asna S 118025 dW3l00S 4 sneisyeag 4 d l lt 1 diN3H00S 34 ws 1 9185005 3 1354025 uono l p dois Wl S 534008 7 39008 Y 3uooos lt 3dN00S Y 5 993095 x o 9 515095 4 06d 8 goax L 1 Y Y 5195095 YY Y n 06d 80085 1 3085052
2. L T3S NL 1455 1 T3SPAL z 1e1siDoJ jeseud 9 1 peeu feuBis peo1 wed amp HZOOZWL IZ2OOZW1 0 z 19 s16 1 119 91 TASWL MM 154 4 0529011 TOW OSdZWL OMOZINL 9 a rh BERT L x t n X 1 x n T Py X n HS a n IW vOUINL 9 Ld 91018 S S N x y 1 T Y n L TOLWL Jepeoseud 950 Sd su 1 x 16 91 X 2k 13660 1 Indino 1 pesu Taseoul snouoJuou S x TEN 2 n W veoui eza o HIOOZINL edg eaWZW L 1 15 1 10 91 x j 2965 peo eed aindeg USES n 99939141 HTHdZWI TEAL x Lewes x W vzoulzzd JaysiBeu 1eseud 419 91 19651 eanideg n Torpan n LOHI LZd T IN
3. Transfer Transfer Direction Pointer Increment Control Transfer Operation Mods cycle Source Address Destination Address ATIMAP1 Transfer AT1MAPO AT1MAP1 I O area byte data transfer mode 0 Transfer 1 1 I O area byte data transfer mode 1 Transfer 1 AT1MAP 1 I O area 1 byte data transfer mode 2 Transfer AT1MAP1 area 1 5 byte data transfer mode 3 Transfer Si 1 1 1 I O area even ADR 1 word data transfer mode 4 2nd AT1MAPO AT1MAP0 1 AT1MAP1 I O area odd ADR 1 An even address must be set 1 1 Transfer S 1 1 area even ADR gt AT1MAP0 1 1 word data transfer mode 5 2nd 1 1 I O area odd ADR 1 1 1 An even address must be set ATTMAP1 Transfer S 1 1 I O area 1 Two 1 byte data tranfers mode 6 2nd 1 AT1MAP0 1 1 1 I O area 1 Transfer 1 1 area 1 Two 1 byte data tranfers mode 7 2nd AT1MAPO AT1MAP0 1 1 1 I O area Transfer 5 AT1MAP1 I O area even ADR
4. Faget Pull up resistor pd PS us D gt contorol Wek R ree p DIR 5 direction pa d PSDIR4 control WEK R ely k 9 hae P54 a P5OUTA LL Port output data x D 9 SOU Bl wo ya 777 Schmitt trigger input Port input data lt PSIN4 lt N R Address output External extension output contorl Figure 4 7 5 P54 Block Diagram ea Reset 5 P5PL Pull up resistor gt contorol WEK R Reset I O direction pR d PSDIRS N 5 control WEK R uc X 5 Y 55 5 P5OUT5 Port output data y b Q 2 Schmitt trigger input Port input data lt Role U R Address output External extension output contorl Figure 4 7 6 P55 Block Diagram IV 54 Port 5 Chapter 4 I O Ports tse pum P5PL Pull up resistor Rq SPED6 gt contorol WEK R PSDIR B direction PSPIR6 5 f control WEK R I X 5 i S T P Port output data ST PSOUT6 o WEK R KU X AKT Schmitt trigger input Port inp
5. L 2 2 HALOS 130108 WOILOS OWALOS 5195198 51951928 OlNd LOS YIGLOS 8509519285 3dNIOS 115198 INMOLOS ZONTLOS LSWLOS aiualos lt LONTIOS 13 osdios aya Los ODNTIOS GWO19S I 1noswi 1 0 zdWLos odWLOS Y _ 4 5 Ionuoo 4 lt 3 9 1 muno 48 o g 5 55 1 250 OulLLOS i 94 4 LWALOS 4Jejunoo uonoejep lt 105 2 OWJLOS e m 14 EUER 9 9 AS8119S uonei u 6 4 sn ASHHIOS 3491991 gt Snieis r d MEBI e d LL8S nouo 33419S uq dors 1 1 MddioOS lt 4 4 190195 5195195 3HOIOS Mq 3dN09S a 99393925 x 16108 R INOILOS Y dy y Y RT Sisios e1siBo1 IN Ionuoo 991195 1381691 4eis aE LORS uonpuoo ues 1145 uoissiusueu HIUS i nh Be LEd LOXd LIES 5085125 0106 215108 jane uoIssiwisued uonipuoo pes L 05 f 0DGHIOS 3419 8S1 28SlN dvMS 3osaros 2053105 1
6. Setup item Data output pin Data input pin Clock I O pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin P00 P90 1 91 P02 P92 Port pin selection Select used pin A B SCSEL SC0SEL SBIO SBOO selection SBI0 SBO0 independent SCOMD1 SCOIOM Function Serial data output Serial data input Serial clock input Serial clock input output output SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain POODC POODCO POODC POODC2 PSODC P9ODC2 PSODC P9ODCO Output mode Input mode Output mode Input mode PODIR PODIRO PODIR PODIR1 PODIR PODIR2 PSDIR P9DIR2 P9DIR P9DIRO P9DIR P9DIR1 Pull up setup Added Not added Added Not added Added Not added POPLU POPLUO POPLU POPLU2 P9PLU P9PLU2 PQ9PLU P9PLUO Operation B Pins Setup with 2 channels at transmission Table 11 3 10 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at trans mission SBIO pin can be used as a port Chapter 11 Serial interface 0 Table 11 3 10 Setup for Synchronous Serial Interface Pin with 2 channels at transmission Setup item Data output pin Serial unused pin Clock I O pin SBOOA pin SBIOA pin
7. R 2 PAINS oM Schmitt trigger input Z a R Figure 4 12 4 Block Diagram Pull up pull down resistor selection Pull up pull down resistor control I O directon control a Port output data 51 q PAOUT4 WEk Reset Input mode control PAIMD4 77 WEK R Schmitt trigger input Port input data 1 PAINE TO TN R Analog input Figure 4 12 5 PA4 Block Diagram M Reset PADWN Pull up pull down resistor q selection WEK R Y Reset 4 Pull up pull down resistor R PAPLUS gt control wek R Reset I O directon control PADIRS WEK R Port output data e PAOUTS Wek R Li Reget Input mode control DRQ PAIMDS K N R Wer Schmitt trigger input Port input data lt PAINS 7 R Analog input Reset 1 gt wek VR Reset Ra PADIRA gt E wex Va Figure 4 12 6 PA5 Block Diagram Port A Chapter 4 I O Ports gt v d T IV 103 4 I O Ports Pull up pull down resistor selection Pull up pull down resistor control I O d
8. e Table 16 1 1 shows the A D converter functions Table 16 1 1 A D Converter Functions A D Input Pins 8 pins Pins AN7 to ANO Interrupt ADIRQ Resolution 10 bits Conversion Time Min 8 10 us Tap as 500 ns Input range Vgs to Vngr Power Consumption Built in Ladder Resistance ON OFF conversion time above Actual conversion time is value that is added 1 to conversion 1 Sampling time of analog signal after enabled conversion start flag is not mentioned in time Overview 16 1 2 Block Diagram Chapter 16 A D Converter A D Converter Block Diagram ANCTR1 ANCHS0 ANCHS1 ANCHS2 VREF ae ake ee FOND AN7 VSS ANCTRO ANCTR2 0 ENGINE External ANLADE interrupt control P23 PD1 ANCKO f Reserved ANSTSEL1 A D Conversion ADIRQ ANSH1 ANST control ANBUF1 r ANBUF0 ANBUF10 ANBUF 11 ANBUF 12 ANBUF13 3 Y ANBUF14 25 ANBUF15 Y ANBUF16 ANBUF06 ANBUF17 ANBUF07 conversion dat upper 8 bits Sample and ObisAD MUX hold comparator 1 1 A D conversion data lower 2 bits Figure 16 1 1 A D Converter Block Diagram Overv
9. asbei 909008 i ls6 n la SQaoax1 00d 3 ma Ps UOISSILUSUEJ L uonipuoo ues Mus uolssiuisue r HUS a x x 40085 INOQXLL 5 0098 n 5 1 INL IW 00d 315006 Pe NETS n 5 551 uonipuoo pes WOI09S 4145008 L 90409S 2 L6d 024 0025 Hiaoos 891 8SW dvMS mE 0 80640006 2 225400925 2540095 L 025400025 0 lt 025 Figure 11 1 1 Serial interface 0 Block Diagram Overview 4 11 Serial interface 0 11 2 Control Registers 11 2 1 Registers Table 11 2 1 shows registers to control serial interface 0 Table 11 2 1 Serial interface 0 Control Registers Register Address Function SC0MD0 0x03F8F Serial interface 0 mode register 0 SCOMD1 OxO3F90 Serial interface 0 mode register 1 SCOMD2 0x03F91 Serial interface 0 mode register 2 SCOMD3 0x03F92 Serial interface 0 mode register 3 SCOSTR 0x03F93 Serial interface 0 status register RXBUFO 0x03F94 Serial interface 0 received data buffer TXBUFO 0x03F95 Serial interface 0 transmission data buffer SCSEL Ox03F4F Serial I O pin switching control register POODC 0x03F1C Port 0 Nch open drain control register PODIR 0x03F30 Po
10. Ie P6PLU2 Pull up resistor D gt WEK R Reset VO direction Ra PSPIR2 om gt E control WEK R lt y 5 Vd 5 P6OUT2 Port output data ort Pod 2 o WEK R x 77 Schmitt trigger input Port input data lt R Key interrupt input Address output External extension output contorl Figure 4 8 3 P62 Block Diagram Reset 5 P6PL Pull up resistor SEES contorol R p DIR direction ESPIRS control R el x gt ig s P63 Le Port output data ort D Q PeOUTS WEK R E x Schmitt trigger input Port input data lt EGINS lt U R Key interrupt input Address output External extension output contorl Figure 4 8 4 P63 Block Diagram IV 62 Port 6 Chapter 4 I O Ports M m P6PLU4 Pull up resistor D gt contorol WEK R Reset 3 direction pha 2 M control WEK R x 5 P64 D P T4 La Port output data 7 9 600 M LE E Schmitt trigger input Port input data lt lt L Key interrupt input Address output External exte
11. input control External interrupt 2 Timer 7 interrupt Timer 2 interrupt Timer 1 interrupt Synchronous output event selection Synchronous output control Figure 4 9 8 P77 Block Diagram Port 7 Chapter 4 I O Ports P7PL 222 21 DRdP7PLU7 JP WEK R Reset pRqP7DIR7 Su Sue Wek VR x 5 or d 2 q P 9UT7 b d U wek VR K 4 Schmitt trigger input lt U x 4 00 1 10 U 11 X ux P7SEV1 02 R D q Wek R Reset afd P7SYO7 WEK R IV 79 4 I O Ports IV 80 4 10 Port 8 4 10 1 Description General Port Setup To output the data to pins set the control flag of the port 8 direction control register P8DIR to 1 to write the value of the port 8 output register PBSOUT To read input data of pins set the control flag of the port 8 direction control register P8DIR to 0 to read the value of the port 8 input register P8IN Each bit can be set individually as either an input or output by the port 8 I O direction control register P8DIR The control flag of the port 8 direction control register P8DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 8 pull up resistor control register P8PLU Set the control flag of
12. input Figure 4 13 1 PDO Block Diagram PDPLU1 Pull up resistor gt contorol WEK R Reset I O direction PODIRI ss control WEK R Port output data D 5 I Schmitt trigger input Port input data lt P U R External interrupt 3 input Figure 4 13 2 PD1 Block Diagram IV 110 Port D Pull up resistor control direction control Port output data Port output control Port input data Timer 4 input Timer 4 output Pull up resistor control I O direction control Port output data Port output control Port input data Timer 5 input Timer 5 output 2 Reset PDPLU2 ro s PDDIR2 Y R m S p qPDOUT2 o T 5 WEK R PX Reset PDOMD2 PDIN2 Schmitt trigger input omen au 2 snq Figure 4 13 3 PD2 Block Diagram Reset PDPLU3 gt PD3 Schmitt trigger input Figure 4 13 4 Block Diagram Port D Chapter 4 Ports IV 111 4 I O Ports Pull up resistor control I O direction control Port output data Port output control Port input data Timer 7 input Timer 7 output Pull up resistor c
13. bp 7 6 5 4 3 2 1 0 Flag SC4TLV1 SC4TLVO SC4TIE SCATIR At reset 0 0 0 0 Access R W SC4TLV1 SC4TLVO Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of O to 3 to interrupt requests SC4TIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SC4TIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers III 43 Chapter 3 Interrupts B A D Conversion Interrupt Control Register ADICR The A D conversion interrupt control register ADICR controls interrupt level of A D conversion interrupt inter rupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 27 A D Conversion Interrupt Control Register ADICR 0x03FFA bp 7 6 5 4 3 2 1 0 Flag ADLV1 ADLVO ADIE ADIR At reset 0 0 i 0 0 Access R W Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated III 44 Control Registers 3 Interrupts B ATC11 Interrupt Cont
14. Pull up resistor control D gt WEK R Reset direction control P3DIR1 j WEK R P31 Port output data __ q P30UT1 wok VR 777 Schmitt trigger input Port input data lt lt J R Serial 1 UART 1 reception data input Figure 4 5 2 P31 Block Diagram IV 38 Port 3 Chapter 4 I O Ports Reset P3ODC2 R Nch open drain control K Reset P3PLU2 D R Pull up resistor control K I O direction control Reset PS3DIR2 K R P32 P3OUT2 on R Port output data D K Schmitt trigger input Port input data Serial 1 clock input Serial 1 clock output SC1MD1 SC1SBTS Figure 4 5 3 P32 Block Diagram Reset PSODC3 D R Nch open drain control K Reset A P3PLU3 D R Pull up resistor control K Reset D R direction control K P33 P3OUT3 or R Port output data snq eq 1 Schmitt trigger input Port input data Serial 3 IIC3 reception data input Serial 3 IIC3 transmission data output SC3MD1 SC3SBOS Figure 4 5 4 P33 Block Diagram Port 3 IV 39 4 I O Ports Reset 37 P3PLU4 Pull up resistor control gt b gt Wek R Reset direction contro
15. 4 7 LS NTrOS 13 osdyos 5 oovwos 5 anos 1 0 2 05 9 oawros 9 iawvos Y L 5 2 Ionuoo 55 9 OHlHPOS lt N 5 uq wo oso uoissiusue lt 5 i 5 Jejunoo 2 BE gt wquondeoeg XAN j NOOS ASELVOS uoneiouob zs ASSHvOS 4 Asna 2 1 dWadlvoOs 5 M 34 a 2 186 33347095 4 dos 1 1 lt 1 jaquoo 3s 139798 519705 3uoros lt ed 705 xr 9 uisoos fa WOIrOS vy Y Y Y je sigsros 9531798 gqurOS aspa 9 6 uoissiusueJ uonipuoo ueis ius uoissiusueJ yus r gt lt Ord raXL rOgdS gt 4 E 4 N lt D lt wamaxuimas 5 5 5 Gays uono l p 55 5 1 L 4ejynq uonipuoo uelis L 19 379 2 705 HIQr0S S8S1 8SW dVMS 5 5954798 LOSdvOS 0954798 0 5 75 Figure 15 1 1 Serial interface 4 Diagram Overview XV 4 15 2 Control Registers
16. snq eq T a Schmitt trigger input 41 1 input data Serial 4 UART 4 reception data input Figure 4 6 2 P41 Block Diagram IV 46 Port 4 Reset PADWN Pull up pull down resistor selection K R Reset Nch open drain control bR P40DC2 K R Reset Pull up pull down resistor pR P4PLU2 control K R Reset direction control P4DIR2 K R 9 P42 Port output data 5 p 1240072 0 o K R X Schmitt trigger input Port input data Serial 4 clock input Serial 4 clock output SC4MD1 SC4SBTS Figure 4 6 3 P42 Block Diagram Pull up pull down resistor pfa PADWM selection wc R Y Reset e 4 Pull up pull down resistor p a P4PLUS P control wc yr Reset direction control pR P4DIR3 gt gt 2 be Pes v ie ty ee Port output data 2 L p gj P4OUTS Schmitt trigger input P4IN3 71 Port input data A Figure 4 6 4 P43 Block Diagram Port 4 Chapter 4 I O Ports IV 47 4 I O Ports 4 7 Port5 4 7 1 Description General Port Setup To output the data to pins set the control flag of the port 5 direction control register P5DIR to 1 to write the value of the port 5 output register PSOUT To r
17. cO CO CO CO 60 TXD0B SBO0B P90 P63 KEY3 A11 RXDOB SBIOB P91 P62 KEY2 A10 SBTOB P92 P61 KEY1 A9 I SDA3B SBO3B P93 5 gt P60 KEYO A8 SBI3B P94 57 7 SCL3B SBT3B P95 lt gt 4 8 P56 A6 IRQ2B PDO lt gt gt 55 5 l IRQ3B PD1 7 P54 A4 TM4IOB PD2 gt P53 A3 TMSIOB PD3 52 2 TM7IOB PD4 gt P51 A1 BUZZER PD5 i 4 gt 5 SYSCLK PD6 MN101E01 Series 4 80 P35 SBT3A SCL3A 100 for general use P34 SBI3A PD7 gt P33 SBO3A SDA3A l Vss3 a P32 SBT1 lt P gt P31 SBI1 RXD1 AN1 PA1 lt gt 4 P30 SBO1 TXD1 AN2 PA2 lt i gt P25 IRQ5 24 4 AN4 PA4 lt gt lt gt P23 IRQ3A VDD3 AN5 PA5 lt gt 4 gt 22 2 13 0 to5 5V AN6 PA6 lt P21 IRQ1 AN7 PA7 lt O P20 IRQO VREF 4 P16 TM7IOA co Oot AS 1 1 NOS sc AS ye 50 Gare lt lt SEOOOOCES SO OS ao00 S 2555555 909 EFFFSS 422 5 E a 3 0 to 3 6 V o 9 I E
18. lt sng eq jewel lt gt 198694 91015 E eje JeJsueJ 7 50 IdVWLLV 7 OdVINLLV OdVINLIV OdVIALLV 81008 L 1 41519 LINOLLV 4 Jon LOWLLV z v tami S OGWL1V o lt 9 OLNOLLY Q 8 5 08704499 15 uelis jeuBig sng sng ssoeJppy 1 LOLV PEIS lt Ouldv lt 041798 lt 04555 lt 04698 lt 041105 lt lt 0818005 lt 05141095 andeo ZNL lt OUIIWL OUYIOWL edul 208 Oul 008 Figure 18 1 1 ATC1 Block Diagram XVIII 5 Automatic Transfer Controller 18 Automatic Transfer Controller 18 2 Control Registers 18 2 1 Registers Table 18 2 1 shows the registers used to control ATCI Table 18 2 1 ATC1 Control Registers Register Address RAN Function Page ATC1 AT1CNTO OX03FDO RW AT
19. Timer 6 Compare Register 6 0 03 69 7 6 5 4 3 2 1 0 TM6OC7 TM6OC6 TM6OC5 6 4 TM6OC3 TM6OC2 TM6OC1 TM6OCO X X X X X X X X Time base timer can be reset its operation by the software Time base timer can be cleared by writing an arbitrary value to the time base timer clear control register TBCLR Time Base Timer Clear Control Register TBCLR 0x03F6B 7 6 5 4 3 2 1 0 TBCLR7 6 TBCLR5 TBCLR4 TBCLR2 TBCLR1 TBCLRO w w w VII 6 Control Registers 7 Time Base Timer Free running Timer 7 2 3 Timer 6 Enable Registers Vr F This register controls the starting operation of the timer 6 and the time base timer Timer 6 Enable Register TM6BEN 0x03F6C 2 Reserved Access Description Reserved Set always to 0 Time base timer operation control TBEN 0 Stop 1 Operation Timer 6 operation control 0 Stop 1 Operation When the timer 6 is operated the operation is not started unless the TM6EN flag of the Y TM6BEN register is set to 1 When the time base timer is operated the operation is not started unless the TBEN flag of Y the TM6BEN register is set to 1 Control Registers VII 7 7 Time Base Timer Free running Timer 7 2 4 Timer Mode
20. 13 Serial Interface 2 Setup Procedure Description 5 Set ACK bit SC2CTR 0x03F9C bp0 SC2ACKO x bp1 SC2ACKS 1 6 Select the communication mode SC2CTR 0x03F9C bp4 SC2TMD 0 7 Select the communication type SC2CTR 0x03F9C bp2 SC2CMD 1 8 lt Transmission setup gt Selection of transmission reception SC2CTR 0x03F9C bp3 SC2REX 0 9 Initialize the monitor flag SC2CTR 0x03F9C bp6 IICSTC 0 10 Set the SC2MDO register Select the transfer bit count SC2MDO 0x03F96 bp2 0 SC2LNG2 0 111 Select the start condition SC2MDO 0x03F96 bp3 SC2STE 0 Select the first bit to be transferred SC2MDO 0x03F96 bp4 SC2DIR 0 Select the IIC communication edge SC2MD0 0x03F96 bp6 SC2CE1 1 11 Set the SC2MD1 register Select the transfer clock SC2MD1 0x03F97 bp2 SC2MST 1 Control of pin function SC2MD1 0x03F97 bp4 SC2SBOS 1 bp5 SC2SBIS 1 bp6 SC2SBTS 1 bp7 SC21OM 1 12 Set the interrupt level SC2ICR 0x03FF6 bp7 6 SC2LV1 0 10 b Set the SC2ACKS flag of the serial 2 control register SC2CTR to 1 to select receive ACK bit ACK bit is received at transmission and setup of the ACK bit level with the SC2ACKS flag is not necessary 6 Set the SC2TMD flag of the serial 2 control register SC2CTR to 0 to select NORMAL mode 7 Set the SC2CMD flag of the serial 2 control register SC2CTR to 1 to select IIC 8 Set the S
21. Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to 03FFF 1 1 2 hc T 2 4 3 Only lower 8 bits are valid ATMAPO 1 ATMAPO 2 ATMAPO 3 Figure 18 3 9 Transfer Mode 7 In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer In the first data byte transfer the I O space address 0x03F00 0x03FF in memory pointer 1 is the source address and the address in memory pointer 0 for any memory space is the destination address When the first data byte transfer ends the address in memory pointer 0 increments by one In the second data byte transfer the incremented address in memory pointer 0 becomes the source address and the I O space address 0 03 00 in memory pointer 1 becomes the destination address The address in memory pointer 0 remains unchanged after the second data byte transfer ends Set the I O address in lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH ATIMAPIM In transfer mode 7 executes a data byte transfer twice everytime when activated However the value in memory pointer 0 increments by one only after the first transfer ends As a result the source address for the next operation is one address higher than that for the previous operation Set the data transfer count for
22. f gt gt c Schmitt trigger P9IN5 lt Port input data 27 Serial 3 clock input Serial 3 IIC3 clock output SC3MD1 SC3SBTS Figure 4 11 6 P95 Block Diagram Port 9 IV 95 4 I O Ports IV 96 4 12 Port A 4 12 1 Description General Port Setup To output the data to pins set the control flag of the port A direction control register PADIR to 1 to write the value of the port A output register PAOUT To read input data of pins set the control flag of the port A direction control register PADIR to 0 to read the value of the port A input register PAIN Each bit can be set individually as either an input or output by the port A I O direction control register PADIR The control flag of the port A direction control register PADIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up or pull down resistor is added or not by the port A pull up pull down resistor control register PAPLU Set the control flag of the port A pull up pull down resistor control register PAPLU to 1 to add pull up pull down resistor Port can be selected to add pull up resistor or pull down resistor by bp2 of the pull up pull down resistor selec tion register SELUD Each bit can be selected individually as input mode by the port A input mode register PAIMD The port A input mode r
23. 14 Serial Interface 3 Setup Procedure Description 17 Start serial reception 17 Set the transfer clock to SBT3 pin and transfer data to Transfer clock Input to SBT3 pin SBI3 pin Reception data Input to SBI3 pin 18 Return from STANDBY mode 18 Serial 3 interrupt is generated at the same time with reception of 8 bits data and then CPU returns from STOP mode to NORMAL mode after oscillation stabilization wait time Note Procedures 6 9 11 12 and 13 to 14 can be set at once For slave reception in STANDBY mode disable the start condition With other setup normal Y reception is not guaranteed Set each flag in order of the setup procedures Set all the control registers refer toTa Y ble 14 2 1 except TXBUF3 before start communication Operation XIV 37 14 Serial Interface 3 14 3 3 Single Master IIC Serial Interface G sc x v Serial interface 3 is capable of IIC serial communication in single master Communication of this interface 15 based on the IIC BUS data transfer format of Philips Table 14 3 13 shows the functions of IIC serial interface Table 14 3 13 IIC Serial Interface Functions Communication type Single master IIC Interrupt SC3IRQ Pins SDA3 SCL3 Transfer bit count 1 to 8 bit First transfer bit ACK bit ACK bit level O Clock source fosc 2 fosc 4 fosc 8 fosc 16 fosc 32 fos
24. es R 9 P71 J P7OUT1 0 Port output data D X wek YR x 77 Le Schmitt trigger input P7IN1 Port input data lt 1 U R Address output External Extension output control 00 External 2 OM Timer 7 interrupt 10 Timer 2 interrupt ju Timer 1 interrupt Reset X P7SEV1 02 Synchronous output 5 71 2 event selection E R 5 P7SYO1 o Synchronous output pRa control WCK R Figure 4 9 2 P71 Block Diagram Port 7 IV 73 4 I O Ports R Pull up pull down resistor t q selection WEK R Pull up pull down resistor Jp a control WEK R direction control Rg WEK R gt gt c L Port output data ejeq UR P7IN2 gt gt c lt ve RD c7 Schmitt trigger input Port input data 5 5 Address output External Extension output control External interrupt 2 Timer 7 interrupt Timer 2 interrupt Timer 1 interrupt pee 75 1 0 Synchronous o
25. anas N1d9d 044009 TASWL L ELA3M dIG6d AASZd YLOAN qQINOLd NIVd NI6d NI8d NI9d NISd Nl d Nl d 10903 1nOvd 1 Af1O8d 100 1nOSd apow AGVX3 YANES 81504 YLOATG YLOdM HLONWSIN X34 0 X34 0 X84860 XVJ 0 6 60 8 60 X43 0 X94680 XS480 XvJ 0 60 Figure 2 2 6 Register Map Il 27 Memory Space 2 CPU Basics II 28 2 3 ROM Correction 2 3 1 Overview This LSI can correct and change max 3 parts in a program on mask ROM with ROM correction function The correct program is read from the external to the RAM space by using the external EEPROM or by using the serial transmission This function is valid to the system with the external EEPROM 2 3 2 Correction Sequence Progr
26. 8 Remote Control Functions 8 3 2 Setup Examples Remote Control Career Output Functions Setup The setup examples that 1 3 duty career pulse signal is output as 36 7 kHz for period from the RMOUT pin with the timer 0 are shown below The clock source of the timer 0 selects fs 2 at fs 8 MHz An example setup procedure with a description of each step is shown below Timer 0 base cycle Timer 0 base cycle 36 7 kMz lt gt JUUUUUUUL RMOUT output 1 3 duty Figure 8 3 3 Output Wave of RMOUT Output Pin Setup Procedure 1 Disable the remote control career output RMCTR 0x03F7F bp3 RMOEN 0 2 Select the base cycle setup timer RMCTR 0x03F7F bp0 RMBTMS 0 3 Select the career output duty RMCTR 0x03F7F bp2 1 RMDTY1 0 01 4 Confirm the counter stop TMOMD 0x03F54 bp3 TMOEN 0 5 Set the remote control career output of the particular function pin P1OMD 0x03F2B bp0 P1OMDO 1 P1DIR 0x03F31 bp0 P1DIRO 1 RMCTR 0x03F7F bp4 TMORM 1 Description 1 Set the RMOEN flag of the remote control career output control register RMCTR to 0 to disable the remote control career output 2 Set the RMBTMS flag of the RMCTR register to 0 to select the timer 0 as the setup timer of the base cycle 3 Set the RMDTY1 0 flag of the RMCTR register to 1 to select the duty to 1 3 4 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop coun
27. AT1MAP1 Figure 18 3 12 Transfer Mode Set the source address in 20 bit memory pointer 0 ATIMAPOH L and set the destination address in 20 bit memory pointer 1 ATIMAPOH M L Transfer mode does not have an increment function for the memory pointers and executes data transfer for a fixed address Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt ATC 1IIRQ occurs and the automatic transfer ends Operation XVIII 29 18 Automatic Transfer Controller 18 3 16 Transfer Mode B Ep a a aaa xx uwa In transfer mode B ATC1 automatically transfers one byte of data from any memory space to any other memory space everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 00000 to FFFFF 1 mm 1 1 1 1 1 1 1 2 1 1 2 1 1 1 3 Figure 18 3 13 Transfer Mode Set the source address in 20 bit memory pointer 1 ATIMAPIH M L and set the destination address 20 bit memory pointer 0 ATIMAPOH M L Transfer mode B does not have an increment function for the memory pointers and executes data transfer for a fixed address Set the da
28. Figure 13 3 20 Communication Sequence on Each Transfer Format Figure 13 3 21 Master Transmission Timing Figure 13 3 22 Master Reception Timing Clock Setup The transfer clock for communication is obtained by dividing clock source by 8 inside this serial The clock source is selected from the dedicated prescaler timer 2 or 3 output by the SC2MD3 register The clock source should be set in such a way that the transfer rate is under 100 kHz in NORMAL mode 400 kHz in high speed mode with the SC2MD3 register The dedicated prescaler starts as this register selects prescaler count enable Set the SC2MST flag of the SC2MDI register to 1 to select the internal clock clock master This interface can not be used with external clock clock slave Table 13 3 14 IIC Serial Interface Clock Sources Single master IIC Clcok source fosc 2 internal clock fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 15 2 15 4 timer 2 output timer 3 output Operation XIII 39 Chapter 13 Serial Interface 2 XIII 40 source should be set in such a way that the transfer rate is under 100 kHz in NORMAL mode a The transfer rate in communication is obtained by dividing clock source by 8 The clock 400 kHz in high speed mode with the SC2MD3 register a Set the SC2MST flag of the SC2MD1 register to 1 to select internal clock cl
29. fnt eo o IX 1 9 1 OYervIew ooo a eee bee oe T gem eve IX 2 9 1 T Block Diagr m eto eo Eee gre eine Eis IX 2 9 2 Control Register eom td e de e e de eto E ER a E aee to a eid IX 3 9 3 oe eee ue D D e dada aa Ea aes oit IX 4 9 3 T Operation uu asahan n E E EPOR EHE RET PERF NR IX 4 9 3 2 Setup Example ep p D IX 6 Chapter IO ed 1 10 1 OyervjeW e E X2 10 1 1 Block Diagram entente pitt re ret e REO ROI ER PPP ERES 2 10 2 Control RegISfer irn rre ect ee do v PEU X 3 10 3 Operation nieto oo EO OE DO EO e e Od HT Eis X 4 10 3 1 Operation zie Ssh e ana atts ete qe inc eiie stet e eee E ae X 4 10 32 Set p Example eet ite iet oie ce He te ee innt deed X 5 Chapter T1 Seral Interface D accion tdt T1 Overview eorr unheden moo ene He nO eer 2 11 1 Functions a cuc de eth Ee eet 2 11 12 Block Dia grain eiie piene e eret eee tet ee ett eee iwa a dents XI 4 11 2 Control Registers 5 12 1 REGIS ters naa RR ESOS epe EE m SD ao XI 5 11 2 2 Data Buffer eti et eet ee e rd ese n 6 11 23 Mode Registers aaa
30. ADD 8 Dm C D MOVW 8 DWm E F MOVW 8 Am JSR d12 label JSR d16 label MOV 8 abs8 abs12 PUSH An OR 8 AND 8 Dm When the exension code is b oo10 When the extension code is b 0011 MOV abs12 Dm MOV abs8 Dm MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV io8 Dm MOV d4 SP Dm MOV d8 An Dm MOV Dn io8 MOV Dn d4 SP MOV Dn d8 Am ADD 4 Dm SUB Dn Dn d7 BRA 47 BEQ d7 BNE 47 BCC d7 BCS d7 BLT d7 BLE d7 BEQ d4 BNE d4 MOVW DWn HA MOVW An HA d11 BRA 911 911 BNE 411 911 911 BLT 911 BLE 911 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp CMP 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVW DwWn abs8 CBNE 8 Dm d7 CMPW 16 Am MOVW 16 Am MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am BRA d4 MOVW DWn Extension code b 0010 2ndnible 3rd nibble 0 1 0 MOVW An Am MOVW An d4 SP CMPW An Am MOVW DWn d4 SP PUSH Dn A B MOVW SP Am MOVW An SP ADDW 8 SP ADDW 4 C D BTST 8 Dm JSRV 68 1 JMP A0 JSR A0 JMP A1 JSR 1 MOV PSW Dm REP 3 2 BE BGT d7 BHI d7 BLS
31. Address output External extension output contorl lt Address input External extension input contorl Figure 4 10 7 P86 Block Diagram Port 8 IV 87 4 I O Ports rege P8PLU7 m Pull up resistor control gt gt Le wek R P8DIR7 5 I O direction control 8 2 2 K R lx x WEK Y boty 5 P87 kj P8OUT7 Port output data a Pod 2 M o WEK R Pr x 77 Schmitt trigger input P8IN7 Port input data lt 8 R Address output External extension output contorl Address input External extension input contorl IV 88 Port 8 Figure 4 10 8 P87 Block Diagram Chapter 4 I O Ports 4 11 Port 9 4 11 1 Description General Port Setup To output the data to pins set the control flag of the port 9 direction control register P9DIR to 1 to write the value of the port 9 output register POOUT To read input data of pins set the control flag of the port 9 direction control register PODIR to 0 to read the value of the port 9 input register POIN Each bit can be set individually as either an input or output by the port 9 I O direction control register PODIR The control flag of the port 9 direction control register PODIR is set to 1 for output mode
32. Flag PAODCA2 P4ODCO At reset 0 0 Access R W R W bp gt O Q O Port 4 Flag P4ODC2 P4ODC0 Description Nch open drain output selection 0 Push pull output 1 Nch open drain output Chapter 4 I O Ports Pull up Pull down Resistor Selection Register SELUD 0x03F4B Port A pull up pull down selection 2 PADWN 0 Pull up 1 Pull down Port 7 pull up pull down selection 1 P7DWN 0 Pull up 1 Pull down Port 4 pull up pull down selection 0 P4DWN 0 Pull up 1 Pull down Port 4 IV 45 4 I O Ports 4 6 3 Block Diagram ac Hn r cI c WAa r Reset Pull up pull down resistor pR d PADWN selection K R Reset pR P4ODC0 K R Nch open drain control Reset R PAPLUO Pull up pull down resistor D control K R Reset n PADIRO direction control D K R P40 b P4OUTO K R 107 Port output data w E w Schmitt trigger input Port input data Serial 4 reception data input Serial 4 UART 4 transmission data output SC4MD1 SC4SBOS Figure 4 6 1 P40 Block Diagram Pull up pull down resistor D Q PADWN selection WEK R Y Pull up pull down resistor 4 control R VO direction control PR PADIRI m T Pa Port output data q K R Y
33. Figure 1 3 1 Pin Configuration 100QFP TOP VIEW 1 10 Pin Description 1 3 2 Pin Specification Chapter 1 Overview Table 1 3 1 Pin Specification Pins Special Functions I O Direction Pin Functions Description Control Control P00 SBOOA TXDOA in out PODIRO POPLUO SBOOA Serial 0 transmission data TXDOA UART 0 transmission data output output P01 SBIOA RXDOA in out PODIR1 POPLU1 SBIOA Serial 0 reception data input RXDOA UART 0 reception data input P02 SBTOA in out PODIR2 POPLU2 SBTOA Serial 0 clock input output SBO2 SDA2 in out PODIR3 POPLU3 SBO2 Serial 2 transmission data out SDA2 IIC2 data input output put P04 SBI2 in out PODIR4 POPLU4 SBI2 Serial 2 reception data input P05 SBT2 SCL2 in out PODIR5 POPLUS5 SBT2 Serial 2 clock input output SCL2 IIC2 clock input output P06 DAO in out PODIR6 POPLU6 DAO DAO output P10 in out P1DIRO P1PLUO TMOIO Timer 0 input output RMOUT Remote control carrier output P11 TM11IO in out P1DIR1 P1PLU1 1 Timer 1 input output P12 TM2IO in out P1DIR2 P1PLU2 TM2IO Timer 2 input output P13 TMS3IO in out P1DIR3 P1PLU3 TMGIO Timer input output P14 TM4IOA in out P1DIR4 P1PLU4 TM4IOA Timer 4 input output P15 TM5IOA in out P1DIR5 P1PLU5 TM5OA Timer 5 input output P16 TM7IOA in out P1DIR6 P1PLU6 TM7IOA Timer 7 input output P20 IRQO in out P2DIRO P2PLUO
34. SC2FDC1 flag SC2FDCO flag 0 0 Fixed to 1 High output 1 0 Fixed to 0 Low output 0 1 Hold last data 1 1 Reserved XIII 20 Operation 13 Serial Interface 2 B Transmission Timing at master at slave Tmax 25T T T f f Tmax 2T a lt I U Clock SBT2 pin Output data SBO2 pin Transfer bit counter SC2BSY Write data to TXBUF2 Interrupt SC2IRQ Figure 13 3 6 Transmission Timing Falling edge Start condition is enabled at master at slave Tmax 3 5T T f f 2 Clock SBT2 pin Output data SBO2 pin Transfer bit counter SC2BSY Write data to TXBUF2 Interrupt SC2IRQ Figure 13 3 7 Transmission Timing Falling edge Start condition is disabled Operation XIII 21 13 Serial Interface 2 at master at slave Tmax 25TT J T f 2 Clock x SBT2 pin Output data SBO2 pin Transfer bit counter SC2BSY Write data to 7 Interrupt SC2IRQ Figure 13 3 8 Transmission Timing Rising edge Start condition is enabled at master at slave Tmax 3 5T T f 2 Ss D Sau Clock SBT2 pin Output data SBO2 pin Transfer bit counter SC2BSY Write data to 2 Interrupt SC2IRQ Figure 13 3 9 Transmission Timing Rising edge Start condition is disabled XIII 22 Ope
35. Access R W Description TM6LV1 Interrupt level flag TM6LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated III 32 Control Registers 3 Interrupts Time Base Interrupt Control Register TBICR The time base interrupt control register TBICR controls interrupt level of time base interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 16 Time Base Interrupt Control Register TBICR 0x03FEF bp 7 6 5 4 3 2 1 0 Flag TBLV1 TBLVO TBIE TBIR At reset 0 0 i 0 0 Access R W Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of O to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers III 33 Chapter 3 Interrupts Timer 7 Interrupt Control Register TM7ICR The timer 7 interrupt control register TM7ICR controls interrupt level of timer 7 interrupt interrupt enable flag and interrupt r
36. Reset 0 1 00 Main program Set MIE IM1 0 11 Interrupt 1 generated zw Accepted because IL lt IM and MIE 1 xxxLV1 0 00 IM1 0 00 Interrupt acceptance cycle lt lt Interrupt 2 generated xxxLV1 0 10 2 RTI wor Interrupt acceptance 1 1 0 10 Interrupt service routine 2 RTI IM1 0 11 Not accepted bcause IM IL Interrupt generated xxxLV1 0 11 Y Parentheses indicates hardware processing 1 If during the processing of the first interrupt an interrupt request with an interrupt level IL numerically lower than the interrupt mask IM arrives it is accepted as a nested interrupt If IL gt IM however the interrupt is not accepted 2 The second interrupt postponed because its interrupt level IL was numerically greater than the interrupt mask IM for the first interrupt service routine is accepted when the first interrupt handler returns Figure 3 1 6 Processing Sequence for Maskable Interrupts Ill 12 Overview 3 Interrupts B Multiplex Interrupt of Maskable Interrupt When this LSI accepts an interrupt it automatically disables acceptance of subsequent interrupts with the same or lower priority level When the hardware accepts an interrupt it copies the interrupt level xxxLVn for the inter rupt to the interrupt mask
37. Yo 1 gt gt c EX P8PLU4 Pull up resistor control WEK R DIR4 I O direction control 3 WEK R 5 a P8OUTA Port output data gr D 80u WEK R Port input data cz f te Schmitt trigger input P8IN4 lt Address output External extension output contorl Address input External extension input contorl IV 86 Port 8 lt Figure 4 10 5 P84 Block Diagram Chapter 4 I O Ports PLU5 8 Pull up resistor control p a gt WEK R Me P8DIR5 direction control 2 gt Z WEK R x 10 9 y a P85 5 P8OUT5 Port output data ami D Q 1 Schmitt trigger input P8IN Port input data lt 1 SINS J R Address output External extension output contorl Address input External extension input contorl Figure 4 10 6 P85 Block Diagram Cl BE papLUe 1 Pull up resistor control D gt WEK R 18 direction control gt ESBIRS WEK R Gly X R Y P86 a P T Port output data Q Schmitt trigger input Port input data
38. 1 Overview 1 5 2 Operating Conditions Ta 40 C to 85 C Vppi7Vpp 73 0 V to 3 6 V Vpp3 Vpp1 to 5 5 V V ss1 V ss2 V sg3 0 V Rating Parameter Symbol Conditions Unit MIN TYP Power supply voltage 4 4 00 MHz lt fosc lt 32 0 MHz V DES Normal mode fs fosc 2 29 ae Power supply voltage 4 00 MHz lt fosc lt 10 0 MHz 2 Vppi Vpp2 Voo1 2 Normal mode fs fosc I 56 3 Vppi 3 32 768 kHz 3 0 3 6 4 Power supply voltage 1 4 00 MHz lt fosc lt 32 0 MHz Vppi l 5 5 Normal mode fs fosc 2 5 2 4 00 MHz lt fosc lt 32 0 MHz Vppi l 5 5 V Normal mode fs fosc 2 6 Vppa3 fx 32 768 kHz Vppi l 5 5 Voltage to maintain RAM 7 data Vppi 4 At STOP mode 1 8 3 6 Vppi Vpp2 8 Voltage to maintain RAM Vppas 4 At STOP mode Vppi l 3 6 data Vpps Operation speed 5 Vpp4 3 0 to 3 6 V 9 t 0 0625 E Normal mode fs fosc 2 gt Vpp 3 0 to 3 6 V 10 Instruction execution time 1 0 100 S ce Double speed mode fs fosc H Vpp 3 0 to 3 6 V 11 tog DD 61 0 l fs fx 2 High speed oscillator 1 Fig 1 5 1 12 Crystal frequency Vpp 3 0 to 3 6 V 4 0 32 0 MHz 13 15 External capacitors 6 pF 14 C12 15 15 Internal feedback resistor Rito 1 0 MQ 4 fosc Input clock frequency to OSC1 fx Input clock frequency to XI
39. Item Data pin Clock I O pin SDA3A pin SDA3B pin SCL3A pin SCL3B pin Clock master SC3MD1 SC3MS Pin P33 P93 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SDA3 SCL3 pins SBI3 SBO3 pin connection SC3MD1 SC3IOM Function Port Serial data output SC3MD1 SC3SBOS SC3MD1 SC3SBTS Serial data input SC3MD1 SC3SBIS Type N ch open drain N ch open drain P30DC P30DC3 P30DC P30DCS5 P9ODC P9ODC3 P9ODC P9ODC5 output mode output mode P3DIR P3DIR3 P DIR P9DIR3 P3DIR P3DIR5 P9DIR P9DIR5 Pull up added added P3PLU P3PLUS P9PLU P9PLU3 P3PLU P3PLU5 P9PLU P9PLUS5 Operation XIV 47 14 Serial Interface 3 14 3 4 Setup Example sIIV F SUIHSSSBAWYHII Master Transmission Setup Example Here is the setup example of the transmission of several bytes data to the all the devices on IIC bus using IIC serial Interface 3 Table 14 3 17 shows the conditions Table 14 3 17 Conditions Single Master Communication Setup Item Set to SBIS SBOS pins Connection 2 channels Transfer bit count 8 bits Start condition Enable disable after second communication First transfer bit MSB ACK bit Enable communication mode NORMAL mode Clock source fosc 32 Used pins selection A port3 SCL3 SDAS3 pin type N ch open drain SCL3 pull up resistance added SDAS3 pull up resistance
40. Note 5 6 7 can be set at the same time Operation 51 15 Serial interface 4 When the TXD4 RXD4 pin are connected for communication with 1 channel the TXD4 pin inputs outputs serial data The port direction control register PADIR switches I O At recep tion set SCASBIOS of the SC4MD1 register to 1 to select serial data input The RXD4 pin can be used as a general port This serial interface contains emergency reset function If communication need to be stopped by force set SCASBOS and SCASBIS of the SCAMD 1 register to O Each flag should be set as the setup procedure in order Activation of communication should be operated after all control registers refer to Table 15 2 1 TXBUF4 RXBUFA are set Timer 2 and timer 5 can be used as a baud rate timer Refer to Chapter 5 5 9 Serial Transfer Clock Output Operation 1 XV 52 Operation Chapter 16 Converter 16 A D Converter XVI 2 16 1 Overview This LSI has an A D converter with 10 bits resolutions It contains a built in sample hold circuit The channels 0 to 7 AN0 to AN7 of analog input can be switched by software When A D converter is stopped the power con sumption can be reduced by turning the built in ladder resistance OFF A D conversion is activated by a register setup and an external interrupt 16 1 1 Functions no
41. P8PLU1 Pull up resistor control 7e WEK R DIR1 VO direction control pR d PS M WEK R aly gt 9 de ka P81 5 P8OUT1 Le Port output data 7 0 q 800 M j Wek R PX T 1 Schmitt trigger input P8IN1 Port input data lt 8 lt J R Address output External extension output contorl Address input External extension input contorl Figure 4 10 2 P81 Block Diagram 1 p PLU 2 r Pull up resistor control pRa 8 gt WEK R DIR I O direction control Ro 8 2 WEK R X X g UA 1 Yd 0 5 P8OUT2 Le Port output data SOLE v 1 Schmitt trigger input P8IN2 Port input data lt 1 8 J R Address output External extension output contorl Address input External extension input contorl Figure 4 10 3 P82 Block Diagram Port 8 IV 85 4 I O Ports Xy gt gt c ay Yo lt Schmitt trigger input 1 P8PLU3 Pull up resistor control Lepa WEK R P8DIR3 direction control Wek R Port output data 2 1 BOUT Wek R Port input data lt U R Address output External extension output contorl Address input External extension input contorl Figure 4 10 4 P83 Block Diagram
42. Pull up resistor control 2 P1PLU4 gt WEK Reset VO direction control pRdP1DIR4 00 01 1054 v DE wek x x 1 Port output data d P1OUTA 0 00 11 6 X 9 WEK R Reset 3 PIOMD4 gt Port output control 9 WEK R Port input data Schmitt trigger input 2 27 Timer 4 input Timer 4 output Reset 2 P1CNT05 4 Output control K R snq eq H o lt Figure 4 3 5 P14 Block Diagram IV 24 Port 1 P14 Pull up resistor control direction control Port output data o Port output control s o Schmitt trigger input P1IN Port input data lt 2 U R Timer 5 input Timer 5 output Pull up resistor control direction control Port output data Port output control Port input data q BUNG J R Timer 7 input Timer 7 output snq eq Figure 4 3 6 P15 Block Diagram m X T c 1 Schmitt trigger input Figure 4 3 7 P16 Block Diagram P15 P16 Port 1 Chapter 4 I O Ports IV 25 4 I O Ports IV 26 44 2 4 4 1 Description General Port Setup To outpu
43. 7 Timer 7 compare register 2 lower 8 bits TM7OC2H 0x03F7B Timer 7 compare register 2 upper 8 bits TM7PR2L 0x03F7C Timer 7 preset register 2 lower 8 bits TM7PR2H 0x03F7D Timer 7 preset register 2 upper 8 bits TM7ICR 0x03FF0 Timer 7 interrupt control register T7OC2ICR 0x03FF1 Timer 7 compare register 2 match interrupt control register P1OMD 0x03F2B Port 1 output mode register P1DIR 0x03F31 Port 1 direction control register PDOMD 0x03F1B Port D output mode register PDDIR 0x03F3D Port D direction control register TMSEL 0x03F3F Timer I O pin switching register Control Registers 6 16 bit Timer 6 2 2 Programmable Timer Registers Timer 7 has a set of 16 bit programmable timer registers which contains a compare register a preset register a binary counter and a capture register Each register has 2 sets of 8 bit register Operate these registers by 16 bit access A compare register is a 16 bit register which stores comparative value of the compare register and the binary counter B Timer 7 Compare Register 1 Lower 8 bits TM7OC1L 0x03F72 Flag TM7OC1L7 TM7OC1L6 TM7OC1L5 TM70C1L4 TM7OC1L3 TM7OC1L2 TM7OC1L1 TM7OC1LO At reset X X X X X X X X Access R R R R R Timer 7 Compare Register 1 Upper 8 bits TM7OC1H 0x03F73 Flag TM7OC1H7 TM7OC1H
44. eoe rte ee ie E XI 7 113 Operation ces eed Ieronimus XI 13 11 3 1 Clock Synchronous Serial Interface sess nee XI 13 11 32 Setup Example enit Pe eut en pies XI 33 11 3 3 UART Serial Interface rette ete tenter re edet eene XI 39 11 54 Setup Example XI 54 Contents 8 Chapter 12 Serial intertace Es 1 12 2 Overview eem ti epo er DR HU o EP Dr XII2 12 11 Runctions ane eee etm UR qi XII2 12 12 Block Di grain ee ORT anh n UTERE TEE Ruas XII 4 12 2 Control Registers a usni a uama C ORO UE DO PER REED RED XII 5 12 2 Registers ggg RE RSS Sua tee XII 5 12 2 2 Data Buffer Registers ee RIDE PIER EUR UU ER EIER UPS XII 6 12 2 3 Mode Registers ens pet ep ER UD GAS Re 7 12 3 Operation eoe DU XII 12 12 3 1 Clock Synchronous Serial Interface 1 2298 XII 12 12 3 2 Setup Examples tee eei eiie befreien rr te ERU XII 32 12 3 3 UART Serial Interface eee eere e XII 38 12 54 Set p Example ette ete qn E epe d ves Hoe cie bote XII 50 Chapter L3 Serral Merl ace XIII 1 13 T Overview no AI QR etaient ione XIII 2 13 1 Functions pe dieu d diede XIII 2 13 12 Block Diagram eren ete petri CR ttes tes XIII 4 13 2 Control eese XIII 5 13 2 1 Registers Last
45. 15 4 400 ns O 15 8 800 ns 30 5 us fosc 20 MHz fx 32 768 kHz fs fosc 2 10 MHz When fs 2 fs 4 fs 8 are used as clock source they are counted at the rising of the count Y clock and when others are used they are counted at the falling of the count clock 8 bit Timer Count V 27 5 8 bit Timers V 28 Count Timing of Timer Operation Timers 0 1 2 3 4 5 Binary counter counts up with selected clock source as a count clock The basic operation of the whole function of 8 bit timer is as follows Count clock TMnEN flag Compare register D A counter A B C E Interrupt request flag Figure 5 4 1 Count Timing of Timer Operation Timers 0 1 2 3 4 and 5 e A If the value is written to the compare register during the TMnEN flag is stopped 0 the binary counter is cleared to 0x00 at the writing cycle B If the TMnEN flag is operated 1 the binary counter is started to count The counter starts to count up at the falling edge of the count clock e the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock then the binary counter is cleared to 0x00 and the counting is restarted D Even if the compare register is rewritten during the TMnEN flag is enabled 1 the binary counter is not cleared E If the TMnEN f
46. in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an 1 is activated after one byte of data has been transferred twice When it reaches 0x00 an interrupt ATCIIRQ occurs and the automatic transfer ends XVIII 24 Operation 18 Automatic Transfer Controller 18 3 13 Transfer Mode 8 X X sauna In transfer mode 8 ATC1 automatically transfers one byte of data two times everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to O3FFF 1 ATMAP 1 even D 2 2 3 1 odd 4 BELL RAE Only lower 8 bits are valid 2 3 Figure 18 3 10 Transfer Mode 8 In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer In the first data byte transfer the I O space address 0x03F00 0x03FFF in memory pointer 1 is the source address and the address in memory pointer 0 for any memory space is the destination address When the first data byte transfer ends the address in memory pointer 0 increments by one In the second data byte transfer the incremented address in memory pointer 0 becomes the source address and the I O space address 0x03F00 0x03FFF in memory pointer 1 becomes the destination address When the sec ond data byte transfer ends the address in memory poi
47. 1 2 1100 00Dm imm8 abs8 mem8 abs8 imm8 PSW eeee 6 3 0000 0100 imm8 abs12 mem8 abs12 imm8 PSW 0000 0101 8 20616 mem8 absi6 imm8 PSW 9 5 1101 1000 PW DWn DWm DWm DWn PSW 1000 01Dd CMPW DWn Am Am DWn PSW e o oeo 0101 11Da PW An Am Am An PSW 3 0000 01Aa PW imm16 DWm DWm imm16 PSW 3 1100 110d PW imm16 Am Am imm16 PSW 6 3 1101 110a Logical manipulation instructions AND AND Dn Dm Dm amp Dn 5Dm 0 oe 3 2 0011 0111 DnDm AND imm8 Dm Dm amp imm8 Dm 0 oe 4 2 0001 11Dm lt 8 gt AND imm8 PSW PSW amp imm8 PSW oeo 5 3 0010 1001 0010 lt 8 gt OR OR Dn Dm DmIDn Dm 0 oe 3 2 0011 0110 DnDm OR imm8 Dm Dmlimm8 gt Dm 4 2 0001 10Dm lt 8 gt OR imm8 PSW PSWlimm8 gt PSW 5 3 0010 1001 0011 lt 8 gt XOR Dn Dm Dm Dn 5Dm 3 2 0011 1010 DnDm 9 XOR imm8 Dm 8 5 3 0011 1010DmDm 48 gt 1 D DWn d DWm 5 D DWm 9 2 6 4 sign extension 3 d DWm 7 8 sign extension 4 D DWk 8 Dn zero extension Instruction Set XIX 3 19 Appendix MN101E SERIES INSTRUCTION SET Group Mnemonic Operation 8 Dn Dn Dn msbtemp Dn Isb CF Dn gt gt 1 Dn temp Dn msb Dn Isb gt CF Dn gt gt 1 Dn 0 Dn msb Dn Isb temp Dn gt gt 1 Dn CF Dn msb temp
48. 16 20 Transmission ends gt lt communication end processing Set the IICSTPC flag SC3CTR 0x03FAA bp5 IICSTPC 1 14 Set 1 to the SCSIE flag of the SC3ICR register to enable the interrupt If the interrupt request flag SC3IR of the SCSICR register is already set clear SC3IR before the interrupt is enabled Chapter 3 3 1 4 Interrupt Flag Setup 15 Set the transmission data to the transmission reception shift register TXBUF3 Then the transfer clock is generated to start transmission If the ACK bit is received after data transmission the communication end interrupt SC3IRQ is generated 16 Confirm the IICSTC flag of the serial 3 control register SC3CTR When the previous transmission is completed properly IICSTC 0 If IICSTC 1 the communication should be re executed 17 Confirm the level of the ACK bit received by the SC3ACKO flag of the serial 3 control register SC3CTR When SC3ACKO 0 you can continue the transmission When SC3ACKO 1 the reception at slave may not be operated properly so finish the communication 18 To change the transfer count bit set the transfer count bit by the SC3LNG2 0 flag of the serial 3 mode register SC3MDO 19 Set the transmission data to to start the transmission 16 20 Set the IICSTPC flag of the serial 3 control register SC3CTR to 1 so that the stop condition is automatically generated to finish
49. Flag PODIR6 PODIR5 PODIR4 PODIR3 PODIR2 PODIR1 PODIRO At reset 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W bp Flag Description 7 6 PODIR6 5 PODIR5 ponina PODS ut mode 2 PoDIR2 1 PODIR1 0 PODIRO IV 8 Port 0 Chapter 4 I O Ports Port O Pull up Resistor Control Register POPLU 0x03F40 POPLU6 POPLUS POPLU4 POPLU3 POPLU2 POPLU1 POPLUO 0 0 0 0 0 0 0 7 6 POPLU6 2 Pull up resistor selection 4 POPLU4 i 0 Not added 3 POPLUS 1 Added 2 POPLU2 1 POPLU1 0 POPLU0 Port 0 Nch Open drain Control Register POODC 0x03F1C Flag 5 2 POODCO At reset 0 0 0 0 Access R W R W R W R W bp Flag Description 7 6 5 5 FOODS Nch open drain output selection 4 E 0 Push pull output 3 POODC3 1 Nch o en drain output 2 POODC2 P P 1 I 0 POODCO Port 0 IV 9 4 I O Ports 4 2 3 Block Diagram ao Reset Nch open drain control Pull up resistor control direction control Port output data Schmitt trigger input Port input data Serial 0 reception data input Serial 0 UART 0 transmission data output SCOMD1 SCOSBOS Figure 4 2 1 Block Diagram Reset 5 1 Pull up
50. R W R W R W n E EXADV3 P70 P71 P72 P73 Address output control 0 port 1 address output EXADV2 P64 P65 P66 P67 Address output control 0 port 1 address output EXADV1 P60 P61 P62 P63 Address output control 0 1 0 port 1 address output Port 6 Chapter 4 I O Ports 4 8 3 Block Diagram 1 d P6PLUO Pull up resistor gt gt contorol Wek R Reset IR VO direction pug PSDIR0 5 control WEK R lt X 5 Se x P6OUT Port output data ot q SOUTO ali VR PX Schmitt trigger input P6IN Port input data lt SING lt U R Key interrupt input Address output External extension output contorl Figure 4 8 1 P60 Block Diagram E p PLU 1 Pull up resistor Rq 9 D gt contorol R icm IR 3 VO direction _ PSPIRI 5 control WEK R lx S 61 S P6OUT1 Port output data o s 2500 v J Schmitt trigger input Port input data lt EOIN R Key interrupt input Address output External extension output contorl Figure 4 8 2 P61 Block Diagram Port 6 IV 61 4 I O Ports
51. SBT4 pin Y Y x Y Y Y x Input SBI4 SBO4 Transfer bit counter SC4RBSY Interrupt SC4TIRQ Figure 15 3 12 Reception Timing at falling edge start condition is enabled At master Tmax 3 5T T Clock SBT4 pin Input pin 5 4 SBO4 pin Transfer bit counter SC4RBSY 4 Data set to TXBUFA Interrupt SCATIRQ x Figure 15 3 13 Reception Timing at falling edge start condition is disabled Operation 15 Serial interface 4 B Transmission Reception Timing When transmission and reception are operated at the same time set the SCACEI flag of the SCAMDO register to 0 or 1 Data is received at the opposite output edge of the transmission data so that the input edge of the received data should be the opposite output edge of the transmission data from the other side Also in the case transmission reception is done with the start condition opposite of the communication should be done with the same condition to communicate properly SBT4 pin Data is received at the rising edge of clock SBI4 pin Data is output at the falling edge of clock Figure 15 3 14 Transmission Reception Timing Reception at rising edge Transmission at falling edge SBT4 Data is received at the rising edge of clock SBI4 pin Data is output at the falling edge of clock SBO4 pin Figure 15 3 15 Transmission Reception Timing Rece
52. Key interrupt input Address output External extension output contorl IV 64 Port 6 Figure 4 8 8 P67 Block Diagram Chapter 4 I O Ports 4 9 Port 7 4 9 1 Description General Port Setup To output the data to pins set the control flag of the port 7 direction control register P7DIR to 1 to write the value of the port 7 output register P7OUT To read input data of pins set the control flag of the port 7 direction control register P7DIR to 0 to read the value of the port 7 input register P7IN Each bit can be set individually as either an input or output by the port 7 I O direction control register P7DIR The control flag of the port 7 direction control register P7DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up or pull down resistor is added or not by the port 7 pull up pull down resistor control register P7PLU Set the control flag of the port 7 pull up pull down resistor control register P7PLU to 1 to add pull up pull down resistor Port 7 can be selected to add pull up resistor or pull down resistor by bp1 of the pull up pull down resistor selec tion register SELUD Each bit can be selected individually as synchronous mode by the port 7 synchronous output control regiser P7SYO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and 0 for the general port Port 7 can b
53. Operation XIV 27 14 Serial Interface 3 B Pins Setup 3 channels at reception Table 14 3 7 shows the pins setup at synchronous serial interface reception with 3 channels SBO3 pin SBI3 pin SBT3 pin Table 14 3 7 Synchronous Serial Interface Pins Setup 3 channels at reception Item Data output pin Data input pin Clock I O pin SBO3A pin SBISA pin SBT3A pin SBT3B pin SBO3B pin SBI3B pin Clock master Clock slave SC3MD1 SC3MST Pin P33 P93 P34 P94 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SBI3 SBO3 pin SBI3 SBO3 independent selection SC3MD1 SC3IOM Function Port Serial data input Transfer clock I O Transfer clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBTS Type z Push pull N ch Push pull N ch open drain open drain P3ODC P3ODC5 P ODC P9ODC5 Input mode Output mode Input mode P3DIR P3DIR4 P3DIR P3DIR5 P9DIR P9DIR5 P9DIR P9DIR4 Pull up 2 added not added added not added P3PLU P3PLU5 P PLU P9PLU5 XIV 28 Operation Pins Setup 3 channels at reception transmission Chapter 14 Serial Interface 3 Table 14 3 8 Synchronous Serial Interface Pins Setup 3 channels at transmission reception P9PLU P9PLU3 P9PLU P9PLUS5 Item Data output pin Data input
54. Procedures of D A converter operation is as follows 1 Setthe DABUSY flag of the D A converter control register DA2CTR to 1 to send a ladder resistor current to start D A conversion 2 D A conversion is executed to the data set to the DA2DRO register and the result obtained from the conversion is output to the DAO pin Operation XVII 7 17 D A Converter 17 3 1 Fixed Channel D A Converter Setup Example D E B Fixed Channel D A Converter Setup Example Set the converter channel to DAO An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the port 0 pin PODIR 0x03F30 bp6 PODIR6 0 POPLU 0x03F40 bp6 POPLU6 0 2 Set the D A conversion mode DA2DR0 0x03FBF 3 Start the D A conversion DA2CTR 0x03FBE bp0 DABUSY 1 XVII 8 Operation 1 Set the analog output pin to input mode by the port 0 output direction control register PODIR and to no pull up resistor with the port 0 pull up resistor control register 2 Set the D A converter data by the D A converter input register 0 DA2DRO 3 Set the DABUSY flag of the D A converter control register DA2CTR to 1 to start the D A conversion the result obtained from the conversion is output to the DAO pin Chapter 18 Automatic Transfer Controller 18 Automatic Transfer Controller 18
55. added An example setup procedure with a description of each step is shown below Setup Procedure Description SC3MD3 0x03FA6 bp3 SC3PSCE 1 2 Select the clock source SC3MD3 0x03FA6 bp2 0 SC3PSC2 0 011 3 Used pins selection SC3MD3 0x03F4F bp3 SC3SEL 0 4 Control of pin type 0x03F2C bp5 3 5 3 1 1 5 Control of pin direction P3DIR 0x03F03 bp5 3 P3DIR5 1 1 1 Select prescaler operation 1 Set the SC3PSCE flag of the SC3MD3 register to 1 to select prescaler operation 2 SC3PSC2 0 flags of the SC3MD3 register to 001 to select fs 32 at clock source 3 Set the SC3PSC2 0 flag of the SC3MD3 register to 0 to select the used pin A port 3 4 Set the P3ODC5 3 flag of the P3ODC register to 1 1 to select N ch open drain for the SDA3 SCL3 pin type b Set the P3DIR5 flag of PO pin control direction register P3DIR to 1 1 to set P35 P33 to output mode XIV 48 Operation 14 Serial Interface 3 Setup Procedure Description 6 Set ACK bit SC3CTR 0x03F9C bp0 SC3ACKO x bp1 SC3ACKS 1 7 Select the communication mode SC3CTR 0x03F9C bp4 SC3TMD 0 8 Select the communication type SC3CTR 0x03FAA bp2 SC3CMD 1 9 lt Transmission setup gt Selection of transmission reception SC3CTR 0x03FAA bp3 SC3REX 0 10 Initialize the monitor flag SC3CTR 0x03FA
56. 3 Set the TMOPWM flag of the TMOMD register to 1 and the TMOMOD flag to 0 and the TMOPOP flag to 0 to select the PWM operation 4 Select the prescaler output to the clock source by the 2 to 0 flag of the TMOMD register 5 Select fs 2 to the prescaler output by the TMOPSC1 to 0 and TMOBAS flag of the timer 0 prescaler selection register 8 bit PWM Output V Chapter 5 8 bit Timers 43 5 8 bit Timers V 44 Setup Procedure Description 6 Set the period of PWM H output 0x03F52 0x40 7 Start the timer operation TMOMD 0x03F54 bp3 TMOEN 1 6 Set the H period of PWM output to the timer 0 compare register TM0OC The setting value is set to 256 4 64 0x40 because it should be the 1 4 duty of the full count 256 At that time the timer 0 binary counter is initialized to 0x00 7 Set the TM0EN flag of the TM0MD register to 1 to operate the timer 0 TM0BC counts up from 0x00 PWM source waveform outputs H till TM0BC reaches the setting value of the TMOOC register and outputs L after that Then TMOBC continues counting up and PWM source waveform outputs H again once overflow is happened and TMOBC restarts counting up from 0x00 TMOIO pin outputs the PWM source waveform with 1 count clock delay The initial setting of PWM output is changed from L output to H output at the selection o
57. 6 Input data 0 Pin is L VSS level 3 Rone 1 Pin is H VDD level 2 P5IN2 CUM BUB eyel 1 P5IN1 0 P5INO Port 5 Direction Control Register P5DIR 0x03F35 Flag P5DIR7 P5DIR6 P5DIR5 P5DIR4 P5DIR3 P5DIR2 P5DIR1 P5DIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description 7 P5DIR7 6 P5DIR6 5 P5DIR5 FOIE ut mode 2 P5DIR2 UP 1 P5DIR1 0 P5DIRO IV 50 Port 5 Chapter 4 I O Ports Port 5 Pull up Resistor Control Register P5PLU 0x03F45 P5PLU7 P5PLU6 5 P5PLU4 P5PLU3 P5PLU2 P5PLU1 PSPLUO 0 0 0 0 0 0 0 0 Description 7 P5PLU7 6 P5PLU6 2 FORES Pull up resistor selection 4 P5PLU4 i 0 Not added 3 P5PLU3 1 Added 2 P5PLU2 1 P5PLU1 0 P5PLU0 Port 5 IV 51 4 I O Ports 4 7 9 Block Diagram E 1 p PLU Pull up resistor SECO gt contorol WEK R p DIR direction pq PSPIR0 27 4 control WEK R X 5 5 S P5OUT Port output data o a SOU o WEK R x Schmitt trigger input Port input data lt Eon U R Address output External extension output contorl Figure 4 7 1 P50
58. 6 Set the value of the interrupt generation cycle to the timer 0 compare register TMOOC The cycle is 250 so that the setting value is set to 249 OxF9 At that time the timer 0 binary counter TMOBC is initialized to 0x00 7 Set the interrupt level by the TMOLV1 to 0 flag of the timer 0 interrupt control register TMOICR If the interrupt request flag may be already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setting 8 Set the TMOIE flag of the TMOICR register 1 to enable the interrupt 9 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 8 bit Timer Count 5 8 bit Timers The TM0BC starts to count up from 0x00 When the TM0BC reaches the setting value of the TM0OC register the timer 0 interrupt request flag is set at the next count clock then the value of the TM0BC becomes 0x00 and restart to count up 1 When the TMnEN flag of the TMnMD register is changed at the same time to other bit binary counter may start to count up by the switching operation 1 When the fx is selected for the count clock source and the value of the binary counter is read out during the operation incorrect value at count up may be read out To prevent this select the synchronous fs for the count clock source In this case the binary counter is count up by the signal which is synchronized to the timer n system clock therefore the correct value is always
59. At reset X X X X X X X X Access R W R W Timer 7 Preset Register 2 Upper 8 bits TM7PR1H 0x03F75 TM7PR1H7 TM7PR1H6 TM7PR1H5 TM7PR1H4 TM7PR1H3 TM7PR1H2 TM7PR1H1 TM7PR1HO X X X X X X X X B Timer 7 Preset Register 2 lower 8 bits TM7PR2L 0x03F7C TM7PR2L7 TM7PR2L6 TM7PR2L5 TM7PR2L4 TM7PR2L3 TM7PR2L2 TM7PR2L1 TM7PR2L0 X X X X X X X X R W TM7PR2H7 TM7PR2H6 TM7PR2H5 TM7PR2H4 TM7PR2H3 TM7PR2H2 TM7PR2H1 TM7PR2H0 X X X X X X X X VI 6 Control Registers 6 16 bit Timer Binary counter is a 16 bit up counter If any data is written to a preset register when the counting is stopped the binary counter is cleared to 0x0000 Timer 7 Binary Counter Lower 8 bits TM7BCL 0x03F70 TM7BCL7 TM7BCL6 TM7BCL5 TM7BCL4 TM7BCL3 TM7BCL2 TM7BCL1 TM7BCLO X X X X X X X X Flag TM7BCH7 R TM7BCH6 R TM7BCH5 R TM7BCH4 R TM7BCH3 R TM7BCH2 R TM7BCH1 R TM7BCHO At reset X X X X X X X X Access R R R R R R R R Input capture register is a register that hold
60. Clear MIE flag in the PSW all interrupt enable flags xxx IE Disable all interrupts in the maskable interrupt control register Enable interrupt which Set the xxx IE of the return factor triggers return and set MIE flag in the PSW Set HALT STOP mode HALT STOP mode Watchdog timer HALT stop counting STOP reset When returning from STOP Y mode wait for oscillation to stabilize x Return factor interrupt occured Wat ti NORMAL SLOW EA ee carino m ode STOP enabled Interrupt acceptance cycle Figure 2 5 3 Transition to from STANDBY Mode or higher than the mask level in PSW before transition to HALT or STOP mode it is impossi a If the interrupt is enabled but interrupt priority level of the interrupt to be used is not equal to ble to return to CPU operation mode by maskable interrupt Standby Function 49 2 CPU Basics Transition to HALT modes The system transfers from NORMAL mode to HALTO mode and from SLOW mode to HALT mode The CPU stops operating but the oscillators remain operational There are two ways to leave a HALT mode a reset or an interrupt reset produces a normal reset an interrupt an immediate return to the CPU state prior to the transition to the HALT mode The watchdog timer if enabled resumes counting Program 4 4 DO Set HALT mode MOV
61. Description X11 fs 8 TM1PSC1 TM1PSCO TM1BAS Select the clock source 000 fosc 4 010 fosc 16 100 fosc 64 110 fosc 128 X01 fs 2 Timer 2 prescaler selection register CK2MD 0x03F5E Description bp 7 5 4 3 2 1 0 Flag TM2PSC1 TM2PSC0 TM2BAS At reset 0 0 0 Access R W R W R W R W R W R W R W R W X11 fs 4 2 1 TM2PSCO TM2BAS Select the clock source 000 fosc 4 010 fosc 16 100 fosc 32 110 fosc 64 X01 fs 2 Control Registers V 11 5 8 bit Timers Timer 3 prescaler selection register CK3MD 0x03F5F 2 1 0 TM3PSC1 TM3PSC0 TM3BAS 0 0 0 Description TM3PSC1 TM3PSC0 TM3BAS Select the clock source 000 fosc 4 010 fosc 16 100 fosc 64 110 fosc 128 01 15 2 X11 fs 8 B Timer 4 prescaler selection register CK4MD 0x03F66 bp 7 6 5 4 3 2 1 0 Flag TM4PSC1 TM4PSCO TM4BAS At reset 0 0 0 Access R W R W R W R W R W R W R W R W Description TM4PSC1 TM4PSC0 TM4BAS Select the clock source 000 fosc 4 010 fosc 16 100 fosc 32 110 fosc 64 01 15 2 X11 fs 4 V 12 Control Registers 5 8 bit Timers Timer 5 prescaler selection register CK5MD 0x03F67 2 1 0 TM5PSC1 TM5PSCO TM5BAS
62. is a DMA block that enables the hardware to transfer the whole memory space 1 This section pro vides a description of and timing for the basic operations System clock fs DMA start request synchronous signal BREQ BGRNT CPU bus release adjustment cycle LDDMA STDMA Address Bus Gan eae Gay ATC1IRQ Loadcyde STORE cycle lt Byte data transfer cycle Figure 18 3 1 ATC1 Timing Chart ATC1 activation and internal bus acquisition 1 activates either when the selected interrupt factor occurs or when the software sets the activation flag Set the ATC trigger factor ATC1 control register 1 When ATC starts the 1 controller asserts the BREQ signal which requests the MCU core to release the bus When the core receives the BREQ signal it stops all normal executions even if it is in the middle of executing an instruction and releases the bus at the next available timing The core takes a maximum of five cycles from the time it receives the BREQ signal until it actu ally releases the bus After it releases the internal bus the core returns the bus granted signal BGRNT to 1 can then begin
63. 0 OHl2OS sod evas eoas lt 5085205 Z 0 10009 OUI Jejunoo 2115295 90152 0254205 259298 292542985 21959295 LM ndino osdzos PLnOgIA L 2 5 GONOZOS JejsueJ 2415211 Y lt 10 5 2 5 212854295 2954295 254295 0054225 IINZOS uonipuoo dojs uonipuoo Hes ALSZOS GNLZOS 18205 8S 1 78Sl dVMS 991295 YWIUS 1 1 42019 u N ASng jawieos x n IN 0d 21OS z1gS QWOZOS 6186208 O1JUOD z MOV SIGSZOS it E x Dx goa zias n n 5 2085 uono l p uonipuoo Hes INOIZOS Jeyng L t dWALZOS U Ee e c ri HlScos Figure 13 1 1 Serial Interface 2 Block Diagram Overview 4 13 Serial Interface 2 13 2 Control Registers 13 2 1 Registers List Table 13 2 1 shows the registers that control serial interface 2 Table 13 2 1
64. 5 001 BLT label if VFANF 1 PC 4 d7 label if VF NF 0 PC 4 PC 000 BLT label if VF NE 1 PC 54d11 label H gt PC if VFANF 0 PC 5 gt PC 1001 BLE label if VF NF IZF 1 PC 4 d7 label H PQ if VFANF ZF 0 PC 4PC 1000 BLE label if VFANF ZF 1 PC 5 d1 label H gt PG if VFANF ZF 0 PC 5PC 1001 BGT label if VF NF ZF 0 PC 5 d7 label H gt PC if VFANF ZF 1 PC 5PC 4 Instruction Set 0010 0010 1 d4sign extension 2 47 53 411 sign extension MN101E SERIES INSTRUCTION SET Chapter 19 Appendix 2 3 Machine Code 6 Bec BGT label if VF NF ZF 0 PC 6 d1 1 label H4PC 6 3 4 0010 0011 0001 dii H 3 if VFANF ZF 1 PC 6PC BHI label if CFIZF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0010 lt d7 2 if CFIZF 1 PC 52PC BHI label if CFIZF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0010 lt 11 H 33 if CFIZF 1 PC 62PC BLS label if CFIZF 1 PC 5 d7 label H PC 5 3 4 0010 0010 0011 lt d7 2 if CFIZF 0 5 BLS label if CFIZF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0011 lt dll aH 3 if CFIZF 0 PC 62PC B
65. 9 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 7 Set the value of PWM out put cycle to timer 7 preset register 1 TM7PR1 To set 400 Hz by dividing 10 MHz set as 25000 1 24999 0 61 7 At the same time the same value is loaded to the timer 7 compare register 1 7 1 the timer 7 binary counter is initialized to 0 0000 8 Set H period of the PWM output to the timer 7 preset register 2 TM7PR2 To set 1 4 duty of 25000 dividing set as 25000 4 6249 0x1869 At the same time the same value is loaded the timer compare register 2 TM7OC2 9 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 7 TM7BC counts up from 0x0000 The PWM source waveform outputs H until TM7BC matches the set value of the TM7OC2 register Once they matches it outputs L After that TM7BC continues to count up Once TM7BC matches the register to be cleared the PWM output waveform outputs again and TM7BC counts up from 0x0000 again In the initial state of the PWM output it is changed to H output from L output at the timing that the PWM operation is selected with the TM7PWM flag of the TM7MD register Set as the set value of TM7OC2 the set value of TM7OC1 If itis set as the set value of TM7OC2 gt the set value of TMnOC1 the PWM output is a H fixed output 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI
66. AT1MAP0 1 Two 1 byte data tranfers mode 8 2nd 1 AT1MAP0 1 1 1 I O area odd ADR 1 An even address must be set in ATTMAP1 Transfer 5 AT1MAP1 area even ADR 1 Two 1 byte data tranfers mode 9 2nd 1 AT1MAP0 1 1 1 I O area odd ADR An even address must be set 1 1 Transfer AT1MAPO AT1MAP1 1 byte data transfer whole memory area mode A Transfer AT1MAP1 1 byte data transfer whole memory area mode B Transfer AT1MAPO 1 1 1 1 1 1 1 data transfer whole memory area mode C Transfer AT1MAP1 1 1 1 1 1 1 data transfer whole memory area mode D Transfer AT1MAPO AT1MAP1 1 1 1 1 1 Burst transfer continues until AT1 TCR 0 mode E Transfer AT1MAP1 1 1 1 1 1 Burst transfer continues until AT1 TCR 0 mode F XVIII 4 When a memory pointer points to the I O space only the lower 8 bits of the pointer are valid Automatic Transfer Controller Chapter 18 Automatic Transfer Controller 18 1 3 Block Diagram OUILOLV lt Be 4 1s nb ui HI0Oti 1Is nb ti 1 YG VWGLS lt jeuBis 1senbeg peo1 viNa viNaan lt jeuBIS senbey
67. Frame 4 Character bit T Figure 15 3 17 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 15 3 15 shows its kinds to be set Table 15 3 15 UART Serial Interface Transmission Reception Data Start bit 1 bit Character bit 7 8 bit Parity bit fixed to 0 fixed to 1 odd even none Stop bit 1 2 bits The SC4FM1 to 0 flag of the SC4MD2 register sets the frame mode Table 15 3 16 shows the UART serial inter face frame mode settings If the SCACMD flag of the SCAMDI register is set to 1 and UART communication is selected the transfer bit count on SCALNG 2 to 0 flag of the SCAMDO register is no more valid Table 15 3 16 UART Serial Interface Frame Mode SC4MD2 register Frame mode SC4FM1 SC4FM0 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits XV 40 Operation 15 Serial interface 4 Parity bit is to detect wrong bits with transmission reception data Table 15 3 17 shows kinds of parity bit The SC4NPE SC4PMI to 0 flag of the SC4MD2 register set parity bit Table 15 3 17 Parity Bit of UART Serial Interface SC4MD2 Parity bit Setup SC4NPE SC4PM1 SC4PM0
68. SC3TEMP Clock SBT3 pin Data loading time Figure 14 3 1 Reception Data Buffer Use transmission reception shift register SC3TRB as reception data buffer The received data 15 stored to SC3TRB shifting by 1 bit If start condition is input for activation during communication again the transmission data becomes invalid To transmit the data set it to TXBUF3 again SC3TRB is overwritten in every communication In sequence reception read out the data in SC3TRB before the next reception is started Operation XIV 15 14 Serial Interface 3 Transmission Bit Count and First Transfer Bit When the transfer bit count is 1 to 7 bits data storage to the transmission reception shift register TXBUF3 depends on the first transfer bit When MSB is the first bit to be transferred the lower bits of TXBUF3 are used for storage In Figure 14 3 2 if data A to F are stored to bp2 to bp7 of SC3TRB as the transfer bit count is 6 bits data is transferred from F to A When LSB is the first bit to be transferred use the lower bits of TXBUF3 for storage In Figure 14 3 3 if data to F are stored to to bp5 of TXBUF3 as the transfer bit count is 6 bits data is transferred from A to F TXBUFS F E D C B Figure 14 3 2 Transfer Bit Count and First Transfer Bit MSB First TXBUF3 F E D C Figure 14 3 3
69. and the burst transfer ends For burst transfers the program must set the transfer counter to the number of data bytes in the burst transfer The external interrupt 0 can also be used to shut down 1 during a burst transfer To enable this function set the burst transfer stop enable bit BTSTP in control register 1 ATICNT1 to 1 When BTSTP 1 ATCI data transfers stop when the external interrupt 0 interrupt request flag IRQOIR flag in the IRQOICR register is set In an emergency shutdown the transfer counter and memory pointer save the values prior to the shutdown When the interrupt service routine ends a new activation factor restarts ATC1 and the burst transfer begins trans ferring data from the point at which it stopped a When burst transfer stop is enabled do not select external interrupt 0 for ATC1trigger factor XVIII 16 Operation 18 Automatic Transfer Controller 18 3 5 Transfer Mode 0 In transfer mode 0 ATC1 automatically transfers one byte of data from any memory space to the I O space spe cial registers 0x03F00 OxO3FFF everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to 03FFF 1 ATMAPO 1 Only lower 8 bits are valid ATMAPO 2 3 Figure 18 3 2 Transfer Mode 0 Set the source address in 20 bit memory pointer 0 ATIMAPOH
70. peyoads WE l yeubis 1SHIZINL eade TLOIZL idnuei euer N3OIZL HOIZWL 49181694 16 91 09939141 019121 OLOWL 9 pey 99 iagram 7 Block D 6 1 1 Timer Figure VI 3 Overview 6 16 bit Timer VI 4 6 2 Control Registers Timer 7 the binary counter TM7BC the compare register 1 TM7OCI and its double buffer present register TM7PR1 the compare register 2 7 2 and its double buffer preset register 2 TM7PR2 the capture reg ister TM7IC The mode register 1 TM7MD1 and mode register 2 TM7MD2 controls timer 7 6 2 1 Registers Table 6 2 1 shows the registers that control timer 7 Table 6 2 1 16 bit Timer Control Registers Register Address Function TM7BCL 0x03F70 Timer 7 binary counter lower 8 bits TM7BCH 0x03F71 R Timer7 binary counter upper 8 bits TM7OC1L 0x03F72 Timer 7 compare register 1 lower 8 bits TM7OC1H OxOSF73 Timer 7 compare register 1 upper 8 bits TM7PR1L 0x03F74 Timer 7 preset register 1 lower 8 bits TM7PR1H 0x03F75 Timer 7 preset register 1 upper 8 bits TM7ICL 0x03F76 Timer 7 capture register 1 lower 8 bits TM7ICH 0x03F77 Timer 7 capture register 1 upper 8 bits TM7MD1 0x03F78 Timer 7 mode register 1 TM7MD2 0x03F79 Timer 7 mode register 2 TM7OC2L
71. 1 is set to 1 to output the special func tion data and to use as the general port P13 is used as I O pin of the timer 3 as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register PIOMD is set to 1 to output the special func tion data and to use as the general port P14 is used as I O pin of the timer 4 as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register 1 is set to 1 to output the special func tion data and 0 to use as the general port P15 is used as I O pin of the timer 5 as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register 1 is set to 1 to output the special func tion data and 0 to use as the general port P16 is used as I O pin of the timer 7 as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register 1 is set to 1 to output the special func tion data and to use as the general port P10 P12 and P14 have the functions of the real time output control and can switch pin output to 0 1 Hi impedance at the event generation timing of the falling edge of the interrupt X The real time control is the func tion which can change the output signal
72. 1 Noise filter can be uses at the SLOW mode However sampling timing gets slow extremely External Interrupts Ill 67 Chapter 3 Interrupts Noise Filter Setup Example External interrupt 0 and 1 Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 IRQ0 at the rising edge The sampling clock is set to fs and the operation state is fs 10 MHz An example setup procedure with a description of each step is shown below Setup procedure Description 1 Specify the interrupt valid edge 1 Set the REDGO flag of the external interrupt 0 con IRQ0ICR 0x03FE2 trol register IRQ0ICR to 1 to specify the interrupt bp5 REDGO 1 valid edge to the rising edge 2 Select the sampling clock 2 Select the sampling clock to fosc by the NF0SCK1 NFCTR 0x03F2E to 0 flag of the noise filter control register NFCTR bp2 1 NF0SCK1 0 00 3 Set the noise filter operation 3 Set the NF0EN flag of the NFCTR register to 1 to NFCTR 0x03F2E add the noise filter operation bpO NFOEN 1 4 Set the interrupt level 4 Set the interrupt level by the IRQOLV1 to 0 flag of the IRQOICR OxOSFE2 IRQOICR register bp7 6 IRQOLV1 0 10 If the interrupt request flag has been already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup b Enable the interrupt 5 Set the IRQOIE flag of the IRQOICR register to 1 to IRQOICR OxOSFE2 enable the interrupt bp1 IRQOIE
73. 141X3 7195801 N31A1 STA 1X3 uonoejep Duil e 719501 78508 nou uonoelep 3497 Figure 3 3 4 External Interrupt 3 Interface Block Diagram External Interrupts III 50 3 Interrupts B External Interrupt 4 Interface Block Diagram senbei 1dnujeju POU OXTPOH _ CERE d qpuels e6p3 uoroejep YLEN A TASELAAM luno 1InO119 uonoejep A 1 DQ 2433 294 Dx 9433 994 DX sA3 i s9d DX Dx 3 9 Dx Dx Dx Figure 3 3 5 External Interrupt 4 Interface Block Diagram 51 External Interrupts Chapter 3 Interrupts B External Interrupt 5 Interface Block Diagram 1senbai 1dnujeiut GOHI 5795593 jeuBis Aqpuels 14S9d4 9391504 11604 3ISOdI 81808 uoroejep Puo uonoejep uono l p Duie4 SN
74. 15 2 1 Registers Chapter 15 Serial interface 4 Table 15 2 1 shows registers to control serial interface 4 Table 15 2 1 Serial interface 4 Control Registers Register Address Function SCAMDO OxOSFAB Serial interface 4 mode register 0 SC4MD1 OxOSFAC Serial interface 4 mode register 1 SCAMD2 OxOSFAD Serial interface 4 mode register 2 SC4MD3 OxOSFAE Serial interface 4 mode register 3 SCASTR OxOSFAF Serial interface 4 status register RXBUF4 OxOSFBO Serial interface 4 received data buffer TXBUF4 0x03FB1 Serial interface 4 transmission data buffer P4ODG Port 4 Nch open drain control register P4DIR 0x03F34 Port 4 direction control register P4PLU 0x03F44 Port 4 pull up pull down control register SC4RICR 0x03FF8 Serial 4 UART reception interrupt control register SC4TICR 0x03FF9 R W Readable Writable R Readable only Serial 4 UART transmission interrupt control register Control Registers XV 5 15 Serial interface 4 15 2 2 Data Buffer Registers TT Serial interface 4 has each 8 bit data buffer register for transmission and for reception Serial interface 4 Received Data Buffer RXBUF4 0x03FBO 7 6 5 4 3 2 1 0 RXBUF47 RXBUF46 RXBUF45 RXBUF44 RXBUF43 RXBUF42 RXBUF41 RXBUF40 Access Serial
75. 20 1 3 8 bit Timer 1 Serial Interface 1 AN3 TM4IOA P14 lt a gt PA2 AN2 lt gt 8 bit Timer 2 Serial Interface 2 PA1 AN1 IRQO P20 8 bit 3 Serial Interface 3 P95 SBT3B SCL3B IRQ1 P21 0 8 ES P94 SBI3B 5 8 bit Timer 4 Serial Interface 4 P93 SBO3B SDA3B IRQ4 P24 n P92 SBTOB IRQ5 P25 0 88 8 bit Timer 5 Time Base Timer 6 P91 SBIOB RXDOB NAST P27 P90 SBO0B TXD0B 16 bit Timer 7 Watchdog Timer P87 LED7 D7 TXD1 SBO1 P30 4 P86 LED6 D6 SBT1 P32 te P84 LED4 D4 SBO3A SDA3A P33 BMe gt P83 LED3 D3 SBI3A P34 External Interrupt Data Automatic Transfer P82 LED2 D2 SCL3A SBT3A P35 P81 LED1 D1 A D Converter D A Converter P80 LEDO DO SBO4 TXD4 P40 SBI4 RXD4 P41 4 8 Port 5 Port 6 Port 7 5 4 42 gt 7 B Tn Dor O tO cO WO LO LO LO LO LO LO 10 CO CO nnn nnn nn nnn nn nnn gt gt gt lo d 55555555 5559 59 CO 85882665 Y ox Gu Cu Cu u Cu u aaaaSggog9 00009090090 Figure 1 4 1 Block Diagram Depending on the models See 1 1 1 Product Summary Block Diagram 1 19 1 Overview 1 5 Electrical Characteristics Thi
76. 6 5 4 3 2 1 0 SC2TRB7 SC2TRB6 SC2TRB5 SC2TRB4 SC2TRB3 SC2TRB2 SC2TRB1 SC2TRBO Access XIII 6 X Control Registers X X X X X X X 13 2 4 Serialinterface 2 Mode Register Chapter 13 Serial Interface 2 Serial Interface 2 Mode Register 0 SC2MD0 0x03F96 bp 7 6 4 3 2 1 0 Flag At reset SC2BSY 0 SC2CE1 SC2DIR 0 0 SC2STE 0 SC2LNG2 1 SC2LNG1 1 SC2LNG0 1 Access bp R Flag SC2BSY Description 0 Other use R W 1 Serial transmission is in progress R W Serial bus status in clock synchronous communication R W R W SC2CE1 Transmission data output edge 0 Falling 1 Rising Reception data input edge Rising Falling SC2DIR First bit to be transferred 0 MSB first 1 LSB first SC2STE SC2LNG2 SC2LNG1 SC2LNG0 Start condition 0 Disable start condition 1 Enable start condition Transfer bit count 000 1 bit 001 2 bit 010 3 bit 011 4 bit 100 5 bit 101 6 bit 110 7 bit 111 8 bit Control Registers XIII 7 13 Serial Interface 2 Serial interface 2 Mode Register 1 SC2MD1 0x03F97 bp 7 6 5 4 2 Flag 2 SC2SBTS SC2SBIS SC2SBOS SC2MST At reset 0 0 0 0 0 Access SC2IOM
77. Control Registers Timer 4 Compare Register TM4OC 0x03F62 7 6 5 4 3 2 1 Chapter 5 8 bit Timers 0 TM40C7 TM40C6 TM40C5 TM4OC4 TM40C3 TMA4OC2 TM4OC1 TM4OC0 X X X X X X X X Timer 5 Compare Register TM50C 0x03F63 bp 7 6 5 4 3 2 1 0 Flag TM5OC7 TM5OC6 TM5OC5 TM5OC4 5 TM5OC2 TM50C1 TM5OCO At reset X X X X X X X X Access R W R W R W R W R W R W R W R W Binary counter is 8 bit up counter If any data is written to compare register the counting is stopped and binary counter is cleared to 0x00 Timer 0 Binary Counter TMOBC 0x03F50 7 6 5 4 3 2 1 0 TMOBC7 TMOBC6 TMOBC5 TMOBC4 TMOBC3 TMOBC2 TMOBC1 TMOBCO 0 0 0 0 0 0 0 0 Timer 1 Binary Counter TM1BC 0x03F51 R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 TM1BC7 TM1BC6 TM1BC5 TM1BC4 TM1BC3 TM1BC2 TM1BCO 0 0 0 0 0 0 0 0 R R R R R R R R Control Registers V 15 5 8 bit Timers Timer 2 Binary Counter TM2BC 0x03F58 V 16 7 6 5 4 3 2 1 0 TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2
78. E Initiating a Reset There are two methods to initiate areset 1 Drive the NRST pin low for at least four clock cycles NTST pin should be holded low for more than 4 clock cycles 200 ns a ta 20 NHz NRST pin F 4clock cycles 200 ns at a 20 MHz Figure 2 8 1 Minimum Reset PUlse Width 2 Setting the P2OUT7 flag of the P2OUT register to 0 outputs low level at Key information 27 NRST pin And transfering to reset by program software reset can be executed If the internal LSI is reset and register is initiated the 2 7 flag becomes 1 and reset is released Important information from the text On this LSI the starting mode is NORMAL mode that high oscillation i Precautions and ka s the base clock warnings hat gives pulse for enough low level time at sudeen unconnected And r in case set can be generated even if its pulse is low level as the oscillation Be sure to read these clock is under 4 clocks take notice of noise of lost functionality or damage 1 When the power voltage low circuit is connected to NTST pin circuit t Precautions are listed footer Page and section title 11 48 Reset About This Manual 1 gt mFinding Desired Information This manual provides three methods for finding desired information quickly and easily 1 Consult the index at the front of the manual to locate the beginning of each section
79. If the synchronous TMnIO input is selected the synchronous circuit output signal is inputted to the timer n count clock The synchronous circuit output signal is synchronization with the falling edge of the system clock derived the TMnIO input signal TMnIO input System clock fs Synchronous circuit output count clock TMnEN a flag Compare MES register i ow jo m i counter Interrupt request flag Figure 5 5 2 Count Timing of Synhronous TMnIO Input Timers 0 1 2 3 4 and 5 When the synchronous TMnIO input is selected as the count clock source thetimer ncounter counts up in synchronization with system clock therefore the correct value is always read out 8 bit Event Count 5 5 2 Setup Example Chapter 5 8 bit Timers Event Count Setup Example Timers 0 1 2 3 4 and 5 If the falling edge of the TMnIO input pin signal is detected 5 times an interrupt is generated A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 Disable the interrupt TMOICR 0x03FE8 bp1 TMOIE 0 3 Set the special function pin to input P1DIR 0x03F31 bp0 P1DIRO 0 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CK0MD 0x03F56 bp2 1 TMOPSC1 0 X0 bp0 TMOBAS 1 6 S
80. MOVW Dwn HA DWn memt6 HA 1001 010D MOVW An HA gt 16 1001 011 MOVW imm8 DWm sign imm8 gt DWm 0000 1109 48 gt 5 MOVW imm8 Am zero imm8 Am epe eme 0000 111a 8 gt 6 MOVW imm16 DWm imm16 DWm 1100 111d lt 16 1 d8sign extension 4 A An Instruction Set 2 04 2 48 zero extension 8 sign extension 6 8 zero extension 19 Appendix MN101E SERIES INSTRUCTION SET Group Mnemonic Operation Machine Code 6 8 MOVW imm16 Am imm16 Am 61 13 1101 111a lt 16 gt MOVW SP Am SP Am 3 3 0010 0000 100a MOVW An SP 5 3 3 0010 0000 101A MOVW DWn DWm DWn DWm 3 3 0010 1000 00Dd a MOVW DWn Am DWn Am 3 3 0010 0100 11Da MOVW An DWm An gt DWm 3 3 0010 1100 11Ad MOVW An Am An gt Am 3 3 0010 0000 00Aa 2 PUSH PUSH Dn SP 1 SP Dn mem8 SP 2 3 1111 10Dn PUSH An 5 2 gt 5 16 5 215 0001 011 mem8 SP gt Dn SP 1 SP lt S 2 3 1110 10Dn POP An 16 5 gt 5 2 5 214 0000 011A EXT EXT Dn DWm sign Dn DWm 3 3 0010 1001 000d 3
81. Memory pointer 1 is consists of three 8 bit registers ATIMAPIH ATIMAPIM and ATIMAPIL ATIMAPIH holds upper 4 bits of the 20 bit address ATIMAPIM contains the middle 8 bits and ATIMAPIL contains lower 8 bits Depending on the transfer mode either all 20 bits are valid or only the least significant 8 bits in ATIMAPIL are valid When only the 8 bits in ATIMAPIL are valid the value 0x03F is assigned to the 12 bits in and ATIMAPIM and the pointer points to the I O space special registers Memory pointer 1 also contains a computational function that enables it to increment the address based on the transfer state XVIII 14 Operation 18 Automatic Transfer Controller 18 8 8 Data Transfer Count Setting Transfer data counter AT1TRC function You can preset the data transfer count by ATC1 Set the value in the ATCI transfer counter ATI TRC The counter decrements everytime when transfers one byte of data The value in the transfer data counter is 0x00 at reset Set the data transfer counts before activating ATC1 Note that ATC1 cannot be activated if the transfer data counter is set to 0x00 B Data transfer operations using the transfer data counter AT1TRC There are two main types of ATC1 data transfers standard and burst transfers See section 15 3 4 Data Transfer Modes Setting The transfer counter operates differently depending on the transfer type 1 Standard transfers trans
82. Pin P33 P93 P34 P94 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SBI3 SBO3 pin SBI3 SBO3 independent x selection SC3MD1 SC3IOM Function Serial data output 1 input Transfer clock I O Transfer clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBIS Type Push pull N ch Push pull N ch Push pull N ch open drain open drain open drain P30DC P30DC3 P30DC P30DC5 9 005 P9ODC P9ODC3 Output mode Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR5 P9DIR P9DIR5 P9DIR P9DIR3 Pull up added not added added not added added not added P3PLU P3PLU3 P3PLU P3PLU5 P PLU P9PLU5 P9PLU P9PLU3 Operation Pins Setup 2 channels at reception Table 14 3 10 shows the pins setup at synchronous serial interface reception with 2 channels SBO3 pin SBT3 pin The 5 pin is not used so that it can be used as a general port Table 14 3 10 Synchronous Serial Interface Pins Setup 2 channels at reception Chapter 14 Serial Interface 3 Item Data output pin Data input pin Clock I O pin SBO3A pin pin SBT3A SBT3B pin SBOS3B pin 58138 pin Clock master Clock slave SC3MD1 SC3MST Pin P33 P93 P34 P94 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SBI3 SBO3 pin SBI3 SBO3 independent selection SC3MD1 SC3IOM Function Port Serial input Tran
83. a Acceptance of an interrupt does not reset the corresponding interrupt enable flag to p Ill 8 Overview 3 Interrupts MIE 0 and interrupts are disabled when MIE of the PSW is set to 0 by a program and when BE instruction is executed BKD isreset and MIE is set Reset is input MIE 1 and interrupts are enabled when MIE of the PSW is set to 1 by a program and BD instruction is executed BKD is set and MIE is set The interrupt mask level IM1 0 in the processor status word PSW changes when The program alters it directly A reset initializes it to 0 00b Maskable interrupt is accepted the interrupt level becomes the interrupt mask level Execution of the RTI instruction at the end of an interrupt service routine restores the processor status word PSW and thus the previous interrupt mask level The MN101C series does not reset the maskable interrupt enable MIE flag of the processor Y status word PSW to 0 when accepting interrupts Non maskable interrupt is prior to maskable interrupt when they are generated at the same time Non maskable interrupts have priority over maskable ones Refer to appendices 19 1 Instruction set for BE instruction and BD instruction Overview Ill 9 Chapter 3 Interrupts 10 Interrupt Acceptance Operation When accepting an interrupt this LSI hardware saves the handy address regis
84. 1 Overview 1 26 Ta 40 C to 85 Vpp1 Vpp2 3 0 V to 3 6 V Vpp3 Vpp1 to 5 5 V Vos1 Vss2 V553 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin MMOD MOD1 6 Input high voltage 1 0 8 Vpn1 1 7 Inputlow voltage 1 Viti 0 0 2 8 Input leakage current lua 0 V to 2 0 POO to P06 P10 to P16 P20 to P25 P30 to P35 P50 to P57 P60 to P67 Schmitt trigger input 9 Input high voltage Vine 0 8 Vpn1 1 y 10 Input low voltage 0 I 0 2 Vppi 11 Input leakage current li ko Vin 0 V to Vpp t2 0 12 Pull up resistor Rpu2 Vpp1 3 3 V Vin Vssi 30 100 350 kQ 13 Output high voltage Vpp423 3 V 2 0 2 4 14 Output low voltage VoL2 Vpp1 3 3 V loi 22 0 mA 5 0 4 pin P70 to P77 Schmitt trigger input 15 Input high voltage 0 8 Vpn1 Vppi1 16 Input low voltage 0 0 2 17 Input current li Vin 0 V to 2 0 18 Pull up resistor Rpus Vpp1 3 3 V Vin Vssi 30 100 350 22 19 Pull down resistor Rows 1 3 3 V Vin Vss1 30 100 350 20 Output high voltage Vpp423 0 V 2 0 mA 2 4 5 21 Output low voltage Voi3 Vpp1 3 0 V loj 22 0 mA 0 4 pin 3 P90 to P95 PD0 to PD7 Schmitt trigger input 22 In
85. 35 6 16 bit Timer VI 36 6 8 16 bit Timer Synchronous Output 6 8 1 Operation If the binary counter of the timer reaches the set value of the compare register port 7 outputs the port 7 output latched data at the next count clock 16 bit Timer Synchronous Output Operation Timer 7 Port 7 outputs the port 7 latched data at a 7 compare register reaches the binary counter or at the interrupt request generation by the full count overflow Only port 7 can be used in this operation and each bit can be set individually Count Timing of Synchronous Output Timer 7 TM7EN flag Compare register 1 Port 7 output latch data gt desee eee e counter Interrupt request flag Port 7 output Figure 6 8 1 Count Timing of Synchronous Output Timer 7 Output pin outputs the port 7 output latch data at the interrupt request generation by the match of a binary counter and a compare register 1 16 bit Timer Synchronous Output 6 8 Setup Example Chapter 6 16 bit Timer Synchronous Output Setup Example Timer 7 Here is an example to output the port 7 latch data from the synchronous output pin constantly in every 100 us with the timer 7 As the clock source of the timer 7 fs 4 fosc 4 MHZ is selected An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD 1 0x03F 78 bp4 TM7EN 0
86. 6 Set the SC3LNG2 0 flags of the serial 3 mode register SC3MDO to 111 to set the transfer bit count to 8 bits 7 Set the SC3STE flag of the SC3MDO register to 0 to disable start condition 8 Set the SC3DIR flag of the SC3MD0 register to 0 to set MSB as the first transfer bit 9 Set the SC3CE1 flag of the SC3MDO register to 1 to set the reception data input edge to falling 10 Set the SC3CMD flag of the SC3CTR register to 0 to select synchronous serial interface 11 Set the SC3MST flag of the SC3MD1 register to 0 to select clock slave external clock 12 Set the SC3SBOS flag of the SC3MD1 register to 0 and the SC3SBIS and theSC3SBTS flags of the SC3MD1 register to 1 to set the SBO3 pin to general port the 5813 pin to serial data input and the SBT3 to transfer clock I O Set the SC3IOM flag to 0 to set serial data input from the SBIS pin 13 Set the interrupt level to level 2 by the SC3LV1 0 flags of the serial 2 interrupt control register SC3ICR 14 Enable the interrupt by setting 1 to the SC3IE flag of the SCSICR register If the interrupt request flag 5 of the SC3ICR register is already set clear SC3IR before the interrupt is enabled Chapter 3 3 1 4 Interrupt Flag Setup 15 Set dummy data to the serial transmission data buffer 16 Set STOP flag of the CPUM register to 1 for transition to STOP mode XIV 36 Operation
87. 7 6 5 4 3 2 1 0 RXBUF17 RXBUF16 RXBUF15 RXBUF14 RXBUF13 RXBUF12 RXBUF11 RXBUF10 Access Serial interface 1 Transmission Data Buffer TXBUF1 0x03FA3 7 6 5 4 3 2 1 0 TXBUF17 TXBUF16 TXBUF15 TXBUF14 TXBUF13 TXBUF12 TXBUF11 TXBUF10 X X X X X X X X XII 6 Control Registers 12 2 3 Mode Registers Serial interface 1 Mode Register 0 SC1MDO 0xOS3F9D bp 7 4 3 2 1 Chapter 12 Serial interface 1 0 Flag Reset SC1CE1 0 SC1DIR 0 SC1ISTE 0 SC1LNG2 1 SC1LNG1 1 SC1LNGO 1 Access bp Flag SC1CE1 Description Transmission data output edge 0 falling 1 rising Reception data input edge O rising 1 falling R W R W R W R W SC1DIR First bit to be transferred 0 MSB first 1 LSB first SC1ISTE SC1LNG2 SC1LNG1 SC1LNGO Start condition selection 0 Disable start condition 1 Enable start condition Transfer bit 000 1bit 001 2bit 010 3bit 011 4bit 100 5bit 101 6bit 110 7bit 111 8bit Control Registers XII 7 12 Serial interface 1 Serial interface 1 Mode Register 1 SC1MD1 0x03F9E 7 6 5 4 3 2 0 SC1CKM SC1MST SC1CMD SC1IOM SC1SBTS SC1SBIS SC1SBOS XII 8 0 0 0 0 0 0 0 SC1IOM Description Serial data input se
88. CF Bit manipulation instructions BSET io8 bp mem8 IOTOP io8 amp bpdata PSW 1 mem 8 IOTOP io8 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 1 mem 8 abs8 bp BSET abs16 bp mem8 abs16 amp bpdata PSW 1 mem8 abs16 bp BCLR io8 bp mem8 IOTOP io8 amp bpdata PSW 0 meme8 IOTOP io8 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 0 mem 8 abs8 bp BCLR abs16 bp mema8 abs1 6 amp bpdata PSW 0 gt 8 16 BTST imm8 Dm Dm amp imm8 PSW BTST abs16 bp mem8 abs16 amp bpdata PSW Branch instructions if ZF 1 PC 3 d4 label H PC if ZF 0 PC 3 PC BEQ labe if ZF 1 PC 4 d7 label H PC if ZF 0 PC 4 PC 000 BEQ labe if ZF 1 PC 5 d11 if ZF 0 5 001 BNE labe if ZF 0 PC 3 d4 label H gt PC if ZF 1 3 001 BNE label if ZF 0 PC 4 d7 label H gt PC if ZF 1 4 000 BNE labe if ZF 0 PC 5 d11 label H PC if ZF 1 5 001 BGE labe if VF NF 0 PC 44d7 label H gt PC if VFANF 1 PC 4 PC BGE labe if VF NF 0 PC 54d1 label H gt PC if VFANF 1 PC 5 PC 000 001 BCC labe if CF 0 PC 4 d7 label H PC if 4 000 BCC labe 0 PC 5 d11 label H PO i 5 001 BCS labe i PC 4 d7 label H PC 4 000 BCS labe i 5 911 gt if CF 0
89. ER Compare P d FN E MEE register 5 d GE D ie pe C NE d 2200 EEN u counter Interrupt request flag TMnIO output IS Figure 5 6 1 Count Timing of Timer Pulse Output Timers 0 1 2 3 4 and 5 The TMnIO pin outputs signals of 2 x cycle of the setup value in the compare register If the binary counter reaches the compare register and the binary counter is cleared to 0x00 TMnIO output timer output is inverted The invension of the timer output is changed at the rising edge of the count clock This is happened to form waveform inside to correct the output cycle 8 bit Timer Pulse Output V 37 5 8 bit Timers 5 6 2 Setup Example Timer Pulse Output Setup Example Timers 0 1 2 3 4 and 5 TMOIO pin outputs 50 kHz pulse by using timer O For this select fs 2 for clock source and set a 1 2 cycle 100 kHz for the timer 0 compare register at fs 10 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0xOSF54 bp3 TMOEN 0 2 Set the special function pin to the output mode P1OMD 0x03F2B bp0 P1OMDO 1 P1DIR 0x03F31 bp0 P1DIRO 1 3 Select the normal timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 X0 bp0 TMOBAS
90. For example if baud rate should be 300 bps at timer clock source fs 4 fosc 8 MHz fs fosc 2 set value should be as follows Set value of compare register 8 106 2 4 300 2 8 1 207 Timer clock source and set value of timer compare register at standard rate shown following page 1 Transfer rate should be selected under 300 kbps Operation XI 47 11 Serial interface 0 XI 48 Transfer Speed bit s fosc Clock source 300 960 1200 2400 4800 MHz Timer SetValue 79 SetValue SetValue AS Set Value Value re 400 fosc 207 1202 103 2404 51 4808 foscl4 207 300 64 962 51 1202 25 2404 12 4808 105016 51 300 12 1202 fosc 32 25 300 fosc 64 12 300 6 2 207 300 64 962 51 1202 25 2404 12 4808 6 4 104 297 25 1202 12 2404 419 fosc 217 1201 108 2403 54 4761 foscl4 217 300 67 963 105016 16 963 6 2330 fosc 32 1056 64 6 2 217 300 67 963 fs 4 108 300 33 963 13 2338 8 00 fosc 207 2404 103 4808 foscl4 129 962 103 1202 51 2404 25 4808 fosc 16 103 300 25 1202 12 2404 fosc 32 51 300 12 1202 fosc 64 25 300 6 2 129 962 103 1202 51 2404 25 4808 fs
91. LOHI hour uonoejep jeuBis Aqpuels TOSIN OSTAN j POSON OXOSON YLOAN uono l p uonoejep Z S X JejeoseJd NOL ges 0 29 SION i 0 Figure 3 3 2 External Interrupt 1 Interface Block Diagram External Interrupts III 48 3 Interrupts B External Interrupt 2 Interface Block Diagram JojsueJ ejep 1senbaj 1dnu lul zo ul 9135943 9034 215550 6135943 3lcoul 91204 90108 uonoojep STA1X3 SN31 1 1A1X3 N31 T1 QNWTA1 71358041 135041 19504 Figure 3 3 3 External Interrupt 2 Interface Block Diagram III 49 External Interrupts Chapter 3 Interrupts B External Interrupt Interface Block Diagram 91359493 GEZE 6135943 5135903 1 eyep s nb 1dnuejur euis Aqpue s 31204 81204 STA1X3 SNITT
92. Setup Procedure Description 5 Control the pin direction PODIR 0x03F30 bp1 0 PODIR1 0 01 6 Set the SCOMDO register Select the start condition SCOMD0 0x03F8F bp3 SCOSTE 1 Select the first bit to be transferred SCOOMDO 0x03F8F bp4 SCODIR 0 7 Set the SCOMD2 register Control the output data SCOMD2 0x03F91 bp0 SCOBRKE 0 Select the added parity bit SCOMD2 0x03F91 bp3 SCONPE 0 bp5 4 SCOPM1 0 00 Specify the flame mode SCOMD2 0x03F91 bp7 6 SCOFM1 0 11 8 Set the SCOMD1 register Select the communication type SCOMD1 0x03F90 bp0 SCOCMD 1 Select the clock frequency SCOMD1 0x03F90 bp3 SCOCKM 1 bp2 SCOMST 1 Control the pin function SCOMD 1 0x03F90 bp4 SCOSBOS 1 bp5 SCOSBIS 1 bp7 SCOIOM 0 9 Select the interrupt level SCORICR 0x03FF2 bp1 SCORIE 1 SCOTICR 0x03FF3 bp1 SCOTIE 1 5 Set the PODIR1to 0 flag of the Port 0 pin direction control register PODIR to 1 to set POO to the output mode P01 to the input mode 6 Set the SCOSTE flag of the SCOMDO register to 1 to enable start condition Set the SCODIR flag of the SCOMDO register to O to select MSB as the first transfer bit 7 Set the SCOBRKE flag of the SCOMD2 register to 0 to select the serial data transmission Set the SCOPM1 to 0 flag of the SCOMD2 register to 00 to select 0 parity and set the SCONPE flag to 0 to enable add parity bit Set the SCOFM1 to 0 flag of the SC
93. The reception data y input to RXD4 b Set the SCASTE flag of the SCAMDO register to 1 to enable start condition Set the SCADIR flag of the SCAMDO register to O to select MSB as first transfer bit 6 Set the SCABRKE flag of the SC4MD2 register to 0 to select the serial data transmission Set the SC4PM1 to 0 flag of the SC4MD2 register to 00 to select 0 parity and set the SC4NPE flag to 0 to enable add parity bit Set the SC4FM1 to 0 flag of the SC4MD2 register to 11 to select 8 bits 2 stop bits at the flame mode 7 Set the SC4CMD flag of the SC4MD1 register to 1 to select full duplex UART Set the SC4CKM flag of the SC4MD1 register to 1 to select divided by 8 at source clock And the SCAMST flag should be always set to 1 to select clock master Set the SC4SBOS SCASBIS SC4IOM flag of the SCAMD register to 1 to set the TXD4 pin to serial data output and the RXD4 pin to serial data input 8 Setthe SCARIE flag of the SCARICR register to 1 and SCATIE flag of the SC4TICR register to 1 to enable the interrupt request If any the interrupt request already set clear them 9 The transmission is started by setting the transmission data to the serial transmission data buffer TXBUFA When the transmission is finished the serial 4 transmission interrupt SC4TIRQ is generated Also after the received data is stored to the RXBUFA the serial 4 reception interrupt SCARIRQ is generated
94. Vv Clock Prescaler output SC2TEMP Clock SBT2 pin Data loading time Figure 13 3 1 Reception Data Buffer Use transmission reception shift register SC2TRB as reception data buffer The received data is stored to SC2TRB shifting by 1 bit Operation 15 13 Serial Interface 2 If start condition is input for activation during communication again the transmission data becomes invalid To transmit the data set it to TXBUF2 again SC2TRB is overwritten in every communication In sequence reception read out the data in SC2TRB before the next reception is started B Transmission Bit Count and First Transfer Bit When the transfer bit count is 1 to 7 bits data storage to the transmission reception shift register TX BUF2 depends on the first transfer bit When MSB is the first bit to be transferred the lower bits of TXBUF2 are used for storage In Figure 13 3 2 if data A to F are stored to bp2 to bp7 of SC2TRB as the transfer bit count is 6 bits data is transferred from F to A When LSB is the first bit to be transferred use the lower bits of TXBUF2 for storage In Figure 13 3 3 if data to F are stored to to bp5 of TXBUF2 as the transfer bit count is 6 bits data is transferred from A to F TXBUF2 F E D C B Figure 13 3 2 Transfer Bit Count and First Transfer Bit MSB First TXBUF2 F
95. bp1 SC1RIE 1 SC1TICR 0x03FF5 bp1 SC1TIE 1 9 Start the serial transmission The transmission TXBUF1 0x03FA3 The reception data input to RXD1 b Set the SC1STE flag of the SC1MDO register to 1 to enable start condition Set the SC1DIR flag of the SC1MDO register to 0 to select MSB as first transfer bit 6 Set the SC1BRKE flag of the SC1MD2 register to 0 to select the serial data transmission Set the SC1PM1 to 0 flag of the SC1MD2 register to 00 to select 0 parity and set the SC1NPE flag to 0 to enable add parity bit Set the SC1FM1 to 0 flag of the SC1MD2 register to 11 to select 8 bits 2 stop bits at the flame mode 7 Set the SC1CMD flag of the SC1MD1 register to 1 to select full duplex UART Set the SC1CKM flag of the SC1MD1 register to 1 to select divided by 8 at source clock And the SC1MST flag should be always set to 1 to select clock master Set the SC1SBOS SC1SBIS SC1IOM flag of the SC1MD 1 register to 1 to set the RXD1 pin to serial data output and the RXD1 pin to serial data input 8 Setthe SC1RIE flag of the SC1RICR register to 1 and SCITIE flag of the SC1TICR register to 1 to enable the interrupt request If any the interrupt request already set clear them 9 The transmission is started by setting the transmission data to the serial transmission data buffer TXBUF1 When the transmission is finished the serial 1 transmission interrupt SC1TIRQ
96. counter TM71O output PWM output Figure 6 7 3 Count Timing of High Precision PWM Output At the compare register 2 the compere register 1 1 To output the high precision PWM output set the TM7BCR flag of the TM7MD2 register to 1 to select the TM7OC1 compare match as the clear source for the binary counter and the set H output source of the PWM output Also set the T7PWMLS flag to 1 to select the TM7OC2 compare match as the reset L output source of the PWM output 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI 33 6 16 bit Timer 6 7 2 Setup Example High Precision PWM Output Setup Example Timer 7 The TM7IO output pin outputs the 1 4 duty PWM output waveform at 400 Hz with the timer 7 Select fosc 2 at fosc 10 MHz as the clock source One cycle of the PWM output waveform is decided by the set value of the compare register 1 H period of the PWM output waveform is decided by the set value of the compare register 2 An example setup procedure with a description of each step is shown below TM7IOA output Figure 6 7 4 Waveform of TM7IOA Output Pin Setup Procedure Description 1 Stop the counter TM7MD 1 0x03F 78 bp4 TM7EN 0 2 Select the pin TMSEL 0x03F3F bp6 TM7SEL 0 3 Set the special function pin to output P1OMD 0x03F2B bp6 P1OMD6 1 P1DIR 0x03F31 bp6 P1DIR6 1 4 Set the PWM output TM7MD2 0x
97. eration The event is generated again it is switched to the setup value of the port 1 output control register PICNTO When the real time control is canceled set the port 1 output control register PICNTO to I O port real time control disabled In spite of the setup at the external interrupt O control register IRQOICR valid edge of IRQO is only the falling edge When the real time output control function is use the port 1 output register P1OUT in Y advance and clear the information of the edge event hold function Real Time Output Control IV 115 4 I O Ports Timing of Real Time Output Control P1CNTO setvalue 0 Low output Timer output External interrupt 0 IRQO P1TCNT I set value Timer output gt set value P1n output n20 2 4 Write operation to P10OUT register 4 Timer output ra Figure 4 14 1 Timing of Real Time Output Control IV 116 Real Time Output Control Chapter 4 I O Ports 4 15 Synchronous Output Port 7 has the synchronous output function that outputs the arbitrary set data to pins in synchronization with the generation of the specified event without setting program Synchronous event is selected from the external inter rupt 2 P22 IR Q2 timer 1 interrupt timer 2 interrupt or timer 7 interrupt signal 4 15 1 Registers Table 4 15 1 shows the synchronous output control registers of the
98. 0 Negative flag is used to handle a signed value Overflow Flag VF Overflow flag VF is set to 1 when the arithmetic operation results overflow as a signed value Otherwise overflow flag is cleared to 0 Overflow flag is used to handle a signed value Interrupt Mask Level IM1 and IMO Interrupt mask level IM1 and IMO controls the maskable interrupt acceptance in accordance with the interrupt factor interrupt priority for the interrupt control circuit in the CPU The two bit control flag defines levels 0 to 3 Level 0 is the highest mask level The interrupt request will be accepted only when the level set in the inter rupt level flag xxxLVn of the interrupt control register is higher than the interrupt mask level When the interrupt is accepted the level is reset to IM1 IMO and interrupts whose mask levels are the same or lower are rejected during the accepted interrupt processing Table 2 1 5 Interrupt Mask Level and Interrupt Acceptance Interrupt mask level Priority Acceptable interrupt level IM1 IMO Mask level 0 0 0 Highest Non maskable interrupt NMI only Mask level 1 High NMI level 0 Mask level 2 Low NMI level 0 to 1 Mask level 3 Lowest NMI level 0 to 2 B Maskable Interrupt Enable MIE Maskable interrupt enable flag MIE enables disables acceptance of maskable interrupts by the CPU s internal interrupt acceptance circuit A 1 enables maskable inte
99. 1 Above 3 and 2 can be set at the same time The input signal from P20 pin outputs the interrupt factor at the edge that is followed to the programmable active edge after passing through the noise filter a The noise filter should be setup before the interrupt is enabled The external interrupt pins are recommended to be pull up in advance 68 External Interrupts 3 Interrupts 3 3 9 External Interrupt At The Standby Mode External Interrupt at the Standby Mode External interrupt 0 to 5 It is possible from the standby mode by the external interrupt At the standby mode when the value which is set to the external interrupt valid edge specify flag and the external interrupt pin level are matched the interrupt is generated Therefore be aware of the value of the external inter rupt valid edge specify flag and the external interrupt pin level at the transition to the standby mode If the value which is set to the external interrupt valid edge specify flag and the external interrupt pin level are matched at the transition to the standby mode it recovers from the standby mode right away Setup Examples of the External Interrupt at the Standby Mode The generation of the external interrupt 0 IRQO can recover from STOP mode by the low level signal which is input from the external interrupt Setup procedure Description 1 Specify the interrupt valid edge IRQOICR OxOSFE2 bp5
100. 1 6 Set the timer pulse output cycle 0x03F52 0 31 7 Start the timer operation TMOMD 0x03F54 bp3 TMOEN 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop timer 0 counting 2 Set the P1OMDO flag of the port 1 output mode register P1OMD to 1 to set P10 pin to the special function pin Set the TMOMOD flag of the port 1 direction control register P1DIR to 1 to set the output mode Chapter 4 Port Function 3 Set the TMOMOD flag of the TMOMD register to 0 to select the normal timer operation 4 Select the prescaler output to the clock source by the TMOCK to 0 flag of the TMOMD register b Select fs 2 to the prescaler output by the TMOPSC 1 to 0 flag and TMOBAS flag of the timer 0 prescaler selection register CKOMD 6 Set the timer 0 compare register to the 1 2 of the timer pulse output cycle The setting value should be 50 1 49 0x31 for 100 kHz to be divided by 5 MHz At that time the timer 0 binary counter is initialized to 0 00 7 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 TMOBC counts up from 0x00 If TMOBC reaches the setting value of the TMOOC register then TMOBC is cleared to 0x00 TMOIO output signal is inverted and TMOBC restarts to count up from 0x00 If any data is written to compare register when the binary counter is stopped timer output is reset to L 8 bit Tim
101. 2 Select the synchronous output event P7SEV 0x03F2F bp1 0 P7SEV1 0 01 3 Set the synchronous output pin P7SYO 0x03F1F OxFF P7DIR 0x03F37 0xFF 4 Select the timer clear factor TM7MD2 0x03F79 bp5 TM7BCR 1 5 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 01 bp3 2 TM7PS1 0 10 6 Set the synchronous output event generation cycle TM7PR1 0x03F75 0x03F74 0 0063 7 Start the timer operation TM7MD1 0x03F78 TM7EN 1 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to to stop the timer 7 counting 2 Set the P7SEV1 to 0 flag of the pin control register P7SYO to 01 to set the synchronous output event to the timer 7 interrupt 3 Set the port 7 synchronous output control register P7SYO to OxFF to set the synchronous output pin P77 to P70 Synchronous output pin Set the port 7 direction control register P7DIR to OXFF to set the port 7 to the output pin Chapter 4 Ports 4 TSet the TM7BCR flag of the TM7MD2 register to 1 to select the compare match as the binary counter clear source b Select fs as the clock source by the TM7CK1 to 0 flag of theTM7MD 1 register Also select 1 4 dividing as the count clock source by the TM7PS1 to 0 flag 6 Set the synchronous output event generation cycle to the timer 7 preset register 1 TM7PR1 To set 10 kHz by dividing 1 MHz set as 100 1299 0x0063 At the same time the same value is load
102. 3 Set the SC3PSC2 0 flag of the SC3MD3 register to 100 to select fs 2 for clock source 4 Set the PSODC5 P3ODCS3 flags of the PSODC register to 0 0 to select push pull for the SBOS SBT3 pin type Set the P3PLU5 P3PLUS flags of the P3PLU register to 0 0 not to add pull up registor Operation XIV 35 14 Serial Interface 3 Setup Procedure Description 5 Control of pin direction P3DIR 0x03F33 bp5 3 P3DIR5 3 0 0 6 Transfer bit count selection SCS3MDO 0x03FA4 bp2 0 SC3LNG2 0 111 7 Start condition selection SC3MDO 0x03FA4 bp3 SC3STE 0 8 Select the first bit to be transferred SC3MD0 0x03FA4 bp4 SC3DIR 0 9 Select the transfer edge SC3MDO 0x03FA4 bp6 SC3CE1 1 10 Select the communication type SC3CTR 0x03FAA bp2 SC3CMD 0 11 Select the transfer clock SC3MD1 0x03FA5 bp2 SC3MST 0 12 Control of pin function SC3MD1 0x03FA5 bp4 SC3SBOS 0 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 5 0 13 Set the interrupt level SC3ICR 0x03FF7 bp7 6 SC3LV1 0 10 14 Enable the interrupt SC3ICR 0x03FF7 bp1 SCSIE1 0 10 15 Set the activation source of serial communication Dummy data TXBUFS 0 0 9 16 Transition to STOP mode CPUM 0x03F00 bp3 STOP 1 5 Set the P3DIR5 P3DIR3 flags of the Port 0 pin control direction register P3DIR to 0 0 and set to 0 to set P35 P33 to input mode
103. 4 Data set to Interrupt SCOTIRQ Figure 11 3 16 Reception Timing at Standby Mode Reception at rising edge start condition is disabled Operation XI 27 11 Serial interface 0 XI 28 B Pins Setup with 3 channels at transmission Table 11 3 7 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO pin SBTO pin at transmission Table 11 3 7 Setup for Synchronous Serial Interface Pin with 3 channels at transmission Setup item Data output pin Data input pin Clock I O pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOMD1 SCOMST Port pin P00 P90 1 91 P02 P92 Port pin selection Select used pin A B SCSEL SCOSEL SBIO SBOO selection SBIO SBOO independent SCOMD1 SCOIOM Function Serial data output 1 input Serial clock Serial clock SCOMD1 SCOSBO SCOMD1 SCOSBIS SCOMD1 SCOSBTS S Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain POODC POODCO POODC POODC2 PSODC P9ODC2 PSODC P9ODCO Output mode Output mode Input mode PODIR PODIRO PODIR PODIR2 PSDIR P9DIR2 P9DIR P9DIRO Pull up setup Added Not added Added Not added Added Not added POPLU POPLUO POPLU POPLU2 P9PLU P9PLU2 PQ9PLU P9PLUO Operation B Pins Setup with channels at r
104. 4 I O Ports 4 16 Input Rejection Function 4 16 1 Registers Table 4 16 1 shows the input rejection control registers Table 4 16 1 Input Rejection Control Registers Register Address Function Input rejection IOCTR R W Input rejection control register 4 16 2 Operation nz Input Rejection Control Register IOCTR 0x03F6E Reserved 0 Input data of 5V I O port Port 4 8 9 A and D is not read during input rejection by input Y rejection control register bp Flag Description Input rejection control 7 IOEN 0 normal input 1 input rejection 6 1 0 Reserved set always 0 IV 120 Input Rejection Function Chapter 5 8 bit Timers 5 8 bit Timers V 2 5 1 Overview This LSI contains two general purpose 8 bit timers Timers and 1 and four 8 bit timers Timers 2 3 4 and 5 combined baud rate timers Timers 0 and 1 or Timers 2 and 3 or Timers 4 and 5 can be used as 16 bit timer with cascade connection In a cascade connection Timers 0 2 and 4 form the timer 0 or the lower 8 bits of 16 bit counter and Timers 1 3 and 5 form the timer 1 or the upper 8 bits 8 bit timer contains two prescalers which can use at the same time Each prescaler counts fosc fs as the base clock Configurations of hard ware are shown below Prescaler 0 fosc base 7 bits Prescaler Prescaler
105. 55 tet tco OSC1 is the CPU clock ica XI is the CPU clock 6 Connect external capacitors that suits the used pin When crystal oscillator or ceramic oscillator is used the frequency is changed depending on the condenser rate Therefore consult the manufacturer of the pin for the appropriate external capacitor 22 Electrical Characteristics 1 Overview Ta 40 C to 85 C Vpp1 Vpp2 3 0 V to 3 6 V Vpp3 Vpp1 to 5 5 V Vos1 Vss2 V553 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Low speed oscillator 1 Fig 1 5 2 16 Crystal frequency fxtal2 Vpp 3 0 to 3 6 V 32 100 MHz 17 22 2 External capacitors 7 pF 18 Coo 22 19 Internal feedback resistor 7 0 MQ External clock input 1 OSC1 OSC2 is unconnected 20 Clock frequency fosc 4 0 32 0 MHz 21 High level pulse width 8 twh1 11 625 Fig 1 5 3 22 Low level pulse width 8 twit 11 625 ns 23 Rising time t 5 0 uid Fig 1 5 3 24 Falling time twet 5 0 External clock input 2 XI XO is unconnected 25 Clock frequency fx 32 100 kHz 26 High level pulse width 8 twh2 3 5 Fig 1 5 4 27 Low level pulse width 8 twi2 3 5 28 Rising time twr2 20 si Fig 1 5 4 ns 29 Falling time twre 20 7 Connect external capacitors that suits
106. 80250 80251 r e 0252 BUZOE 7 e Figure 10 1 1 Buzzer Block Diagram X 2 Overview 10 Buzzer 10 2 Control Register Oscillation Stabilization Wait Time Control Register Table 10 2 1 Oscilllation Stabilization Wait Time Control Register DLYCTR 0x03F03 Description Output selection 0 Buzzer stop 1 Buzzer operation Buzzer output frequency selection 000 214 001 fosc 213 010 fosc 212 011 fosc 21 100 fosc 210 101 fosc 2 110 fx 24 111 fx 29 Oscillation stabilization wait period selection 00 fs 214 01 fs 2 10 fs 2 1 11 fs 22 1 1 Do not use at high speed operation NORMAL mode Use at slow speed operation SLOW mode Control Register X 3 10 Buzzer 4 10 3 Operation 10 3 1 Operation B Buzzer Buzzer outputs the square wave having frequency 1 2 to 1 2 of the high oscillation clock fosc or 1 2 to 1 24 of the low oscillation clock fx The BUZS 2 1 0 flag of the oscillation stabilization wait control register DLYCTR set the frequency of the buzzer output The BUZOE flag of the oscillation stabilization wait control register DLYCTR sets buzzer output ON OFF B Buzzer Output Frequency The frequency of buzzer output is decided by the frequency of the high oscillation clock fosc or the low oscilla tion clock fx and the bit 6 5 4 BUZS2 BUZSI BUZSO of
107. A D Converter B Example of A D Converter Setup by the external factor P23 falling edge A D conversion is started by the external factor P23 falling edge The analog input pins are set to ANO the con verter clock is set to fs 4 and the sampling hold time is set to x 6 Then A D conversion complete interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the analog input pin PAIMD 0x03F3B PAIMDO 1 PAPLU 0x03F4A bp0 PAPLUO 0 2 Select the analog input pin ANCTR1 0x03FB3 bp2 0 ANCHS2 0 000 3 Select the A D converter clock ANCTRO 0x03FB2 bp5 4 ANCK1 0 01 4 Set the sample and hold time ANCTRO 0x03FB2 bp7 6 ANSH1 0 01 5 Set the interrupt level ADICR 0x03FFA bp7 6 ADLV1 0 10 6 Enable the interrupt ADICR Ox3FFA bp1 ADIE 1 7 Set the A D ladder resistance ANCTRO 0x03FB2 bp3 ANLADE 1 ANCTR2 0x03FB4 bp7 ANSTSEL1 1 9 Start the A D conversion Operation ANCTR2 0x03FB4 bp7 ANST 1 8 Select the A D Conversion Starting factor 1 Set the analog input pin set in a 2 as the special function pin with the port A input mode register PAIMD Also set no pull up resistance with the port A pull up resistance control register PAPLUD 2 Select the analog input pin from AN7 to ANO by the 2 0 flag of the A D converter control register1
108. Activation Factor for Communication Table 11 3 1 shows activation factors for communication At master communication the transfer clock is gener ated by setting data to the transmission data buffer TXBUFO or by receiving a start condition Except during communication the input signal from SBTO pin is masked to prevent errors by noise or so This mask can be released automatically by setting a data to TXBUFO access to the TXBUFO register or by inputting a start con dition to the data input pin Therefore at slave communication set data to TXBUFO or input an external clock after a start condition is input However the external clock should be input after more than 3 5 transfer clock interval after the data set to TXBUFO This wait time is needed to load the data from TXBUFO to the internal shift register Table 11 3 1 Synchronous Serial Interface Activation Factor Activation factor Transmission Reception At master Set transmission data Set dummy data Input start condition At slave Input clock after transmission data Input clock after dummy data is set is set Input clock after start condition is input B Transfer Bit Setup The transfer bit count is selected from 1 to 8 bits Set them by the SCOLNG 2 to 0 flag of the SCOMDO register at reset 111 The SCOLNG2 to 0 flag holds the former set value until it is set again Except during communication SBTO pin is masked to prevent errors by noise
109. At slave com Y munication set data to TXBUFO or input a clock to SBTO pin after a start condition is input To communicate properly more than 3 5 transfer clock after the data set to TXBUFO is Y needed to input the external clock Operation XI 13 11 Serial interface 0 XI 14 B Start Condition Setup The SCOSTE flag of the SCOMDO register sets if a start condition is enabled or not The start condition is regarded that when SCOCEI flag of SCOMDO is set to 0 and a clock line SBTO pin is H data line SBIO pin with 3 lines or SBOO pin with 2 lines is changed from to L Also it is regarded that when SCOCEI flag is set to 0 and a clock line SBTO is L data line SBIO pin with 3 lines or SBOO pin with 2 lines is changed from H to L Both the SCOSBOS flag and the SCOSBIS flag of the SCOMDI register should be set to 0 before the start con dition setup is changed Atthe selection of the start condition enable and master transmission reception after the start condition output start condition is input from the slave then data transmission is generated First Transfer Bit Setup The SCODIR flag of the SCOMDO register can set the transfer bit MSB first or LSB first can be selected B Transmission Data Buffer The transmission data buffer TXBUFO is a buffer of reserve that stores data to load the internal shift register Data to be transferred should be set to
110. CPU Basics 2 4 3 Fixed Wait Cycle Mode mr m i This mode accesses ROM or other low speed devices connected to the external expansion bus by inserting the number of wait cycles specified in the external fixed wait counter EXW field of the memory control register MEMCTR Fixed wait cycle mode is used to automatically insert the number of wait cycles specified by the fixed wait counter EXW1 0 in the MEMCTR After reset MEMCTR specifies the fixed wait cycle to three wait cycles To change to handshake mode or to use a different number modify the appropriate bits in MEMCTR 2 4 4 Handshake Mode Handshake mode uses the interlock control method in the data transfer sequence with a transfer enable signals NRE NWE and a data acknowledge signal NDK Handshake mode adjusts the wait cycle for each external device that has a different access speed when the DK generation circuit is provided for each device CPU of this LSI keeps waiting until the reception of data acknowl edge signal to ensure sufficient wait time so that external device can reception data with no error During single chip mode do not set handshake mode a Automatic data trasnsfer function ATC1 that accesses an external memory cannot be used handshake mode Bus Interface Il 41 2 CPU Basics Access Timing with No Wait Cycles Syetem clock fs Address A19 to 0 Data D7 to 0 NCS NRE
111. Interrupt Flag Setting 8 bit Event Count V 35 5 8 bit Timers Setup Procedure Description 10 Enable the interrupt TM0ICR 0x03FE8 bp1 TMOIE 1 11 Start the event count TMOMD 0x03F54 bp3 TMOEN 1 10 Set the TMOIE flag of the TMOICR register to 1 to enable the interrupt 11 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 Every time TMOBC detects the falling edge of TMOIO input TMOBC counts up from 0x00 When TMOBC reaches the setting value of TMOOC register the timer 0 interrupt request flag is set at the next count clock then the value of TMOBC becomes 0x00 and counting up is restarted 36 8 bit Event Count 5 8 bit Timers 5 6 8 bit Timer Pulse Output 5 6 1 Operation The TMnIO pin can output a pulse signal at any frequency Operation of Timer Pulse Output Timers 0 1 2 3 4 and 5 The timers can output signals of 2 x cycle of the setup value in the compare register TMnOC Output pins are as follows Table 5 6 1 Timer Pusle Output Pin Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Pulse output pin TM0IO TM1IO TM2IO TMSIO TM5IO output output output output output output P10 P11 P12 P13 P14 PD2 P15 Count Timing of Timer Pulse Output Timers 0 1 2 3 4 and 5 Count clock TMnEN Te E 2 NE flag RI wi ES
112. SC3TEMP is 0 when communication end interrupt SC3IRQ is generated SC3BSY is cleared to 0 B Forced Reset You can shut down the communication by setting both of the SC3SBOS flag and the SC3SBIS flag of the SC3MDI register to 0 the SBO3 pin function port input data input 1 When a forced reset is done the SC3BSY flag of the SC3MDO register is cleared but other control registers hold their set values B Last Bit of Transmission Data Table 14 3 4 shows last bit data output holding time at transmission and the minimum data input time of the last bit at reception At slave internal clock setup is necessary to reserve data holding time at data transmission Table 14 3 4 Last Bit Data Length of Transmission Data at transmission Last bit data holding period at reception Last bit data input period At master 1 bit data length 1 bit data length min At slave 1 bit data length of external clock x 1 2 internal clock cycle x 1 2 to 3 2 When start condition is disabled SC3STE flag 0 SBO3 output after last bit data output hold time can be set with SC3FDC1 0 of the SC3MD3 register as shown in Table 14 3 5 After reset release output before serial transfer is regardless of the set value of SC3FDC1 0 flags When start condition is enabled SC3STE flag 1 H is output regardless of the set value of SC3FDCI 0 flags Operation XIV 19 14 Serial Interface 3 Table 14 3 5 S
113. SC4CMD 0 Select the transfer clock SC4MD1 0x03FAC bp2 SCAMST 1 bp3 5 4 0 Select the transfer clock SC4MD1 0x03FAC bp4 SC4SBOS 1 bp5 SC4SBIS 1 bp6 SC4SBTS 1 bp7 SC4IOM 0 8 Set the interrupt level SC4TICR 0x03FF9 bp7 6 SC4LV1 0 10 9 Enable the interrupt SC4TICR 0x03FF9 bp1 SCATIE 1 4 Set the PAODC2 PAODCO flags of the PAODC register to 1 1 to select open drain for the SBO4 SBT4 type Set the PAPLU2 PAPLUO flags of the PAPLU register to 1 1 to select enable pull up resistor 5 Set the PADIR2 P4DIRO flag of the Port 4 pin direction control register PADIR to 1 1 and the P4DIR3 flag to 0 to set P42 P40 to the output mode P41 to the input mode 6 Set the SCALNG2 to 0 flag of the serial 4 mode register 0 SCAMDO to 111 to set the transfer bit count 8 bits Set the SCASTE flag of the SCAMDO register to 0 to disable the start condition Set the SCADIR flag of the SCAMDO register to O to set MSB as a transfer first bit Set the SC4CE1 flag of the SCAMDO register to 1 to set the reception data input edge falling and the transmission data output edge rising 7 Set the SC4CMD flag of the SC4MD1 register to 0 to select the synchronous serial Set the SCAMST flag of the SC4MD1 register to 0 to select the clock master internal clock Set the SCACKM flag to 0 to select not divided by 8 for the clock source Set the SC4SBOS SC4SBI
114. SC4SBIS Serial input control selection 0 Input 1 1 Input serial SC4SBOS SBO4 TXD4 pin function 0 Port 1 Output serial data SC4CKM 1 8 dividing of transfer clock selection 0 Not divided by 8 1 8 cycle SC4MST Clock master slave selection 0 Clock slave 1 Clock master SC4CMD Control Registers Synchronous serial full duplex UART selection 0 Synchronous serial 1 Full duplex UART 15 Serial interface 4 B Serial interface 4 Mode Register 2 SC4MD2 0x03FAD bp 7 6 5 4 3 1 0 Flag SC4FM1 SC4FMO SC4PM1 SCAPMO SC4NPE SC4BRKF SC4BRKE Reset 0 0 0 0 0 0 0 Access R W R W R Description Frame mode specification 00 7 data bit 1 stop bit 01 7 data bit 2 stop bit 10 8 data bit 1 stop bit 11 8 data bit 2 stop bit SC4FM1 SC4FMO Added bit specification Transmission Reception SC4PM1 00 Add 0 Check for 0 SC4PMO 01 Add 1 Check for 1 10 Add odd parity Check for odd parity 11 Add even parity Check for even parity Parity enable SC4NPE 0 Enable parity bit 1 Disable parity bit Break status receive monitor SC4BRKF 0 Data reception 1 Break reception Break status transmit control SC4BRKE 0 Data transmission 1 Break transmission Control Registers XV 9 15 Serial interface 4 B Serial interface 4 Mode Register 3 SC4MD3 0x03FAE 7 6 3 2 1 0 SC4FDC1 SC4FDCO SC4PSCE SCAPSC
115. Set p erre aec eec e e e ee i ete aod sedie eds XVIII 35 Chapter 19 Appendik S sn ea XIX 1 19 1 Instruction Set enun ni date RE RR P s XIX 2 19 2 Instruction Map ORG PR Dum pere XIX 8 Contents 11 gt Contents 12 Chapter 1 Overview 1 Overview 1 1 Overview 1 1 1 Overview The MN101E series of 8 bit single chip microcomputers the memory expansion version of MN101C series incorporate multiple types of peripheral functions This chip series is well suited for camera VCR MD TV CD LD printer telephone home automation pager air conditioner PPC remote con trol fax machine music instrument and other applications This LSI brings to embedded microcomputer applications flexible optimized hardware configurations and a simple efficient instruction set The MN101E01L has an internal 320 KB of ROM and 14 KB of RAM Peripheral functions include 6 external interrupts 20 internal interrupts including NMI 9 timer counters 5 sets of serial interfaces A D converter D A converter watchdog timer automatic data transfer synchronous output function buzzer output and remote control output The configuration of this microcomputer is well suited for application as a system controller in a air conditioner camera timer selector for VCR CD player or MD With two oscillation system max 32 MHz 32 kHz contained on the chip the system clock can be s
116. Specify the valid edge by the EDGSELO flag of the both edges interrupt control register EDGDT and the REDGO flag of the external factor P23 PD1 L level control register 0 7 A D conversion After sampling with the sample and hold time set in 4 A D conversion is decided in comparison with MBS in order 8 Complete the A D conversion When A D conversion is finished the ANST flag is cleared to 0 and the result of the conversion is stored to the A D buffer ANBUFO 1 Then the A D complete interrupt request ADIRQ is generated XVI 8 Operation 16 A D Converter a 2 conversion clocks are needed to start A D conversion after you set ANLADE flag to 1 ANST to 0 more than 2 system clock 2 converter clock time is needed to start A D 1 In the middle of A D conversion when you restart after crushing A D conversion by setting conversion A D conversion clock 1 A D conversion complate ANST flag i E _ lt conversion ma Ts dcs TE daie bit 9 comparison bit 0 comparison Determine Determine Determine Determine bo bi bio E Ald interrupt ADIRQ Figure 16 3 1 Operation of A D Conversion prevent noise error by confirming the match of level by program or by using the average a To read out the value of the A D conversion A D con
117. TM2BC1 TM2BC0 0 0 0 0 0 0 0 0 Timer 3 Binary Counter TM3BC 0x03F59 R R R R R R R R bp 7 6 5 4 3 2 1 0 Flag TM3BC7 6 TM3BC5 4 2 TM3BC1 reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Timer 4 Binary Counter TM4BC 0x03F60 bp 7 6 5 4 3 2 1 0 Flag TM4BC7 TM4BC6 TM4BC5 4 TMABC3 TMABC2 TMABC1 TMABCO At reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Timer 5 Binary Counter TM5BC 0x03F61 bp 7 6 5 4 3 2 1 0 Flag 5 7 TM5BC6 TM5BC5 5 4 5 TM5BC2 5 1 TM5BCO At reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Control Registers 5 8 bit Timers 5 2 4 Timer Mode Registers a n V OF iO Timer mode register is readable writable register that controls timers 0 to 5 Timer 0 Mode Register TM0MD 0x03F54 6 5 4 2 1 0 TMOPOP TMOMOD TMOPWM TMOCK2 TMOCK1 TMOCKO Access Description TMOPOP On PWM mode select start compulsion of output signal O timer output LH HL 1 timer output HL TMOMOD Pulse width measurement control 0 Normal timer operation 1 P22 PDO pulse width measurement TMOPWM Select timer 0 operation mode 0 Normal timer opera
118. XVI 7 16 3 eens XVI 8 16 3 L entity Ege rd P Rp XVI 10 16 3 2 Setup Example Garten eee one ee e Ies XVI 13 16 3 3 Cautions eruca t D ree toes XVI 17 Chapter c last nt pM p S SEEEN 1 17 1 OVGEVIe Wi cte RERO a Sh EUR XVII 2 17 1 1 Functions oce Hv A eta Uc XVII 2 17 1 2 D A Converter Block Diagram XVII 3 17 2 D A Converter Control Registers e 4 17 2 1 D A Converter Control Registers XVII 4 17 2 2 D A Converter Control Register DA2CTR eese nennen XVII 5 lt Contents 10 gt 17 2 3 D A Converter Input Data Register essen XVII 6 17 3 Op ration ice eaten XVII 7 17 3 1 Fixed Channel D A Converter Setup Example serene XVII 8 Chapter 18 Automatic Transfer Controller esee XVIII 1 18 1 Automatic Transfer Controller esses seen ener nennen enne nnn enne XVIII 2 18 1 1 Overview seo ARS eee dede hide ribi XVIII 2 18 1 2 Bunctlons ecd eec d eee eie p ees XVIII 3 18 1 3 Block Diagram 5 5 eee rete XVIII 5 18 2 Control Registers oceani eee XVIII 6 182 T R gist
119. access to the TXBUF2 register or enabling start condition to the data input pin Therefore at slave communication set data to TXBUF2 or input start condition before input external clock Wait more than 3 5 transfer clocks before input the external clock after the data set to TXBUF2 This wait time is used for data loading from TXBUF2 to internal shift register Table 13 3 1 Synchronous Serial Interface Activation Source Activation source Transmission Reception Master Set the transmission data Set dummy data communication Input start condition Slave Input clock after the transmission Input clock after dummy data is set communication data is set Input clock after start condition is input B Transfer Bit Count Setup The transfer bit count can be selected from bit to 8 bits Set the SC2LNG 2 to 0 flag of the SC2MDO register at reset 111 The SC2LNG 2 to 0 flag holds the previous value until other value is set during communication At slave set data to SC2TRB or input start condition before input a The SBT2 pin is masked inside serial interface to prevent operating errors by noise except clock to the TXBUF2 pin Wait more than 3 5 transfer clocks before input the external clock after the data set to Y TXBUF2 Otherwise normal operation is not guaranteed Operation 13 Serial Interface 2 B Start Condition Setup Enable or disable of start condition ca
120. is generated Also after the received data is stored to the RXBUF1 the serial 1 reception interrupt SC1RIRQ is generated Note 6 7 8 can be set at the same time Operation XII 51 12 Serial interface 1 When the TXD1 RXD1 pin are connected for communication with 1 channel the TXD1 pin inputs outputs serial data The port direction control register P3DIR switches At recep tion set SC1SBIOS of the SC1MD1 register to 1 to select serial data input The RXD1 pin can be used as a general port This serial interface contains emergency reset function If communication need to be stopped by force set SC1SBOS and SC1SBIS of the SC1MD1 register to 0 Each flag should be set as the setup procedure in order Activation of communication should be operated after all control registers refer to Table 12 2 1 TXBUF1 RXBUF 1 are set Timer 4 and timer 5 can be used as a baud rate timer Refer to Chapter 6 6 8 Serial Transfer Clock Output Operation 1 XII 52 Operation Chapter 13 Serial Interface 2 13 Serial Interface 2 XIII 2 13 1 Overview This LSI contains a serial interface 2 that is capable of both clock synchronous IIC single master serial commu nication 13 1 1 Functions Table 13 1 1 shows the serial interface 2 functions Table 13 1 1 Serial Interface 2 Functions Communication style Clock synchronou
121. lt d7 El if mem8 io bp 0 PC 72PC 2 io8 bp label if memB io bpzt PC 8 di abe eHOPC 0 8 67 0011 0101 1bp lt 08 gt dii 2 if mem8 io bp 0 PC 82PC abs16 bp label if mem8 abst6 bpst PC 9 d7 labe HOPC 0 e 0 e 9 78 0011 1111 abs 16 gt lt 47 if memB8 abs16 bp 0 PC 92PC TBNZ abs16 bp label ifmemB abst6 bp 1 PC t0 dtt labe HOPC O 0 10 7 8 0011 1111 1bp abs 16 dii H 72 if mem8 abs16 bp 0 PC 10 PC JMP JMP 02PC 17 16An2PC 15 02PC H 3 4 0010 0001 00A0 JMP label abs18 label H PC 7 5 0011 1001 OaaH abs 18b 15 0 75 JMP label abs20 label H2PC 9 6 0011 1101 1010 000B bbbH abs 20 b 15 0 gt 6 7 JSR JSR An SP 3 SP PC 3 bp7 0 mem8 SP 3 7 0010 0001 00A1 3 0 15 8 8 5 1 PC 3 H5mem8 SP 2 bp7 0 8 2 6 4 PC 3 bp19 16 mem8 SP 2 bp3 0 0PC bp19 16 AnPC bp15 0 0 PC H JSR label SP 3 SP PC 5 bp7 0 mem amp SP 5 6 0001 OOOH lt 912 gt 3 PC 5 bp15 8mem8 SP 1 5 5 2 7 0 8 2 6 4 PC 5 bp19 16 mem8 SP 2 bp3 0 PC 5 d12 label H PC JSR label SP 3 SP PC 6 bp7 0 mem8 SP 6 7 0001 001H lt 916 gt 4 6 15 8 amp 8 5 1 6 8 2 6 7 0 8 2 6 4 PC 6 bp19 16 sm
122. receive properly q Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 11 2 1 except TXBUF0 RXBUF0 are set Operation 11 Serial interface 0 11 33 UART Serial Interface serial 0 can be used for full duplex UART communication Table 11 3 14 shows UART serial interface functions Table 11 3 14 URAT Serial Interface Functions Communication style UART full duplex Interrupt SCOTIRQ transmission SCORIRQ reception Used pins TXDO output input RXDO input Specification the first transfer bit MSB LSB Selection of parity bit Parity bit control 0 parity 1 parity odd parity even parity Frame selection 7 bits 1 STOP 7 bits 2 STOP 8 bits 1 STOP 8 bits 2 STOP Continuous operation Maximum transfer rate 300 kbps standard 300 bps to 38 4 kbps with baud rate timer Activation Factor for Communication At transmission if any data is set to the transmission data buffer TXBUFO a start condition is generated to start transfer At reception if a start condition is received communication is started At reception if the data length of L for start bit is longer than 0 5 bit that can be regarded as a start condition B Transmission Data transfer is automatically started by setting data to the transmission data buffer TXBUFO When the
123. uoIsOul 801008 OLY Hi dVIN HOdVIN INOdVIN lod viN LNOLLY 401991109 WOH HdV 1 4 1 Boyeuy 0udeva ul1oeva LANENV OANENV d 1ONV Ld1ONV 0 1 psanaxl 4 jenas 815705 9 79 camNvos LANTOS O0qIWrOS 919595 34n8XL 991698 915898 EQWEOS 19 555 001605 YLSLOS ZOWLOS LOWLOS 09 198 919295 1 991295 915698 eaWzos LaWeoS 04 598 918098 1005 005 OGWO0OS 151995 YLOWY OLNOId ZOOZWL ZOOLWL LOWZWL HOIZWL LOOZWL LOOZWL HO ZWL 041000 QWOSd YLOOl anin 9 91991 1 9 QINS3O QIWr3O GQWSWL SOSN1 QINEIN L JOZNL QN EMO awoyo GIN LALL 19595 719504
124. 0 IOTOP i08 Figure 2 1 8 Address Space Specifies the address using an address register wi Speci register wi Speci counter with 4 bit displacement and H bit Specifi counter with 7 bit displacement and H bit Speci counter with 16 bit displacement and H bit Speci pointer with 4 bit displacement Speci pointer with 8 bit displacement Speci pointer with 16 bit displacement Specifies the address using the operand value appended to the instruction code Optimum operand length can be used to specify the address h 8 bit displacement ies the address using an address h 16 bit displacement ies the address using the program he address using the program ies the address using the program ies the address using the program ies the address using the program ies the address using the stack ies the address using the stack ies the address using the stack Specifies an 8 bit offset from the address Specifies an 8 bit offset from the top address x 03F00 of the special function register area x 00000 Reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combined use with absolute addressing reduces code size 1 H half byte bit Chapter 2 CPU Basics 2 1 10 Machine Clock A aw
125. 0 and data line SBI3 pin 3 channels or SBO3 pin 2 channels changes from H to L while the clock line SBT3 pin is H It is also detected when the SC3CE1 flag of the SC3MDO register is set to 1 and data line SBI3 pin 3 channels or SBO3 pin 2 channels changes from to L while the clock line SBT3 pin is L Set the SC3SBOS flag of the SC3MDI register to 0 before change the start condition edge Atthe selection of the start condition enable and master transmission reception after the start condition output start condition is input from the slave then data transmission is generated First Transfer Bit Setup The SC3DIR flag of the SC3MDO register sets the first bit to be transferred LSB or MSB can be selected Transmission Reception Data Buffer The transfer data buffer TXBUF3 is the spare buffer which stores data to be loaded to internal shift register Set the data to be transferred to transfer data buffer TXBUF3 and the data is automatically loaded to internal shift register The data loading takes more than 3 clock cycles Data setting to TXBUF3 again during data loading may not be operated properly You can determine whether or not data loanding is in progress by monitoring transfer buffer empty flag SC3TEMP of the SC3STR SC3TEMP flag is set to 1 when data is set to TXBUF3 and cleared to 0 when data loading ends Set data to gt I Clock x Prescaler output
126. 0 mem8 SP 2 PC bp15 8 mem8 SP 3 bp7 PC H mem8 SP 3 bp3 0 PC bp19 16 8 5 4 1 mem8 SP 5 HA h SP 6 SP 2 11 0000 0011 Contorl instructions REP REP imm3 imm3 1 RPC 3 2 0010 0001 1 BE BE PSW x 3F 2PSW 3 3 0010 0010 0000 BD BD PSW 2PSW 3 0010 0011 0000 1 repeat whn imm3 0 rep imm3 1 Chapter 19 Appendix Other than the instruction of MN101E Series the assembler of this Series has the following instructions as macro instructions The assembler will interpret the macro instructions below as the assembler instructions macro instructions replaced instructions remarks INC Dn ADD 1 Dn DEC Dn ADD 1 Dn INC An ADDW 1 An DEC An ADDW 1 An INC2 An ADDW 2 DEC2 An ADDW 2An CLR Dn SUB Dn Dm ASL Dn ADD Dn Dm LSL Dn ADD Dn Dm ROL Dn ADDC _ Dn Dm NEG Dn NOT Dn ADD 1 Dn NOPL MOVW DWn DWm MOV MOV 0 5 MOV MOV Dn 0 SP MOVW MOVW 0 SP DWn MOVW MOVW DWn 0 SP MOVW MOVW 0 SP An MOVW MOVW 0 5 Ver3 3 2002 01 31 Instruction Set XIX 7 19 Appendix 19 2 Instruction Map MN101E SERIES INSTRUCTION MAP 1st nibble 2nd nibble MOV 808 CMP 8 8658 20512
127. 0 0 0 Fixed to 0 Set parity bit to 0 0 0 1 Fixed to 1 Set parity bit to 1 0 1 0 Odd parity Control that the total of 1 of parity bit and character bit should be odd 0 1 1 Even parity Control that the total of 1 of parity bit and character bit should be even 1 None Do not add parity bit Break Status Transmission Control Setup The SC4BRKE flag of the SC4MD2 register generates the brake status If SC4BRKE is set to 1 to select the brake transmission all bits from start bits to stop bits transfer 0 B Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be deter mined by the SCAORE SC4PEK SCAFEF flag of the SCASTR register Even one of those errors is detected the SC4ERE flag of the SCASTR register is set to 1 SCAPEK the SC4FEF flags in reception error flag are renewed at generation of the reception complete interrupt SCARIRQ The SCAORE flag is cleared at the same time of next communication complete interrupt SC4RIRQ generation after the data of the RXBUF4 is read out The decision of the received error flag should be operated until the next communication is finished Those error flag has no effect on communication operation Table 15 3 18 shows the list of reception error source Table 15 3 18 Reception Error Source of UART Serial Interface Flag Error SC4ORE Overrun error Next data is receiv
128. 00 1 port real time control disabled 01 1 High output 10 0 Low output 11 Hi z output P1CNT03 P1CNT02 P10 Real time control 00 1 port real time control disabled 01 1 High output 10 0 Low output 11 Hi z output P1CNTO01 1 00 Port 1 IV 19 4 I O Ports 4 3 3 Block Diagram External interrupt 0 IRQ0 Pull up resistor control P1PLU0 gt N K R direction control 27 00 01 e gt U WEK R 5 P10 Port output data dP1OUT0 ali 00 11 VT Px 5 Reset 1 Port output control Q WEK Port input data lt 1 J R Timer 0 input Timer 0 remote control career output Schmitt trigger input Reset P1CNTO1 Q Data bus m Output control Figure 4 3 1 P10 Block Diagram IV 20 Port 1 Reset Pull up resistor control I O direction control Q Reset E R P1DIR1 Port output data snq geq Port output control Port input data P10UT1 R 2 Dra s P1OMD1 0 p R 1 s P1IN1 R Schmitt trigg
129. 1 3 Select the A D converter clock by the ANCK1 flag of the A D converter control ANCTRO 4 Set the sample and hold time by the ANSH1 ANSHO flag of the A D converter control register ANCTRO 5 Set the interrupt level by the ADLV1 0 flag of the A D conversion complete interrupt control register ADICR If any interrupt request flag is already set clear it Chapter 3 3 1 4 Interrupt Flag Setup 6 Enable the interrupt by setting the ADIE flag the ADICR register to 1 7 Set the ANLADE flag of the A D converter control register ANCTRO to 1 to send a current to the ladder resistance for the A D conversion 8 Set the ANSTSEL flag of the A D converter control register2 ANCTR2 to 1 then setup the A D conversion starting factor to the external factor P23 and the ANST flag of the A D converter control register2 ANCTR2 9 When the external factor P23 falling edge is generated the ANST flag of the A D converter control register2 ANCTR2 is set to 1 then the A D conversion is started Also even if the external factor P23 is not generated the A D conversion can be started by setting the ANST flag of the A D converter control register2 ANCTR2 Operation XVI 15 16 A D Converter Setup Procedure Description 10 Complete A D conversion 10 After A D conversion operation the result of conversion ANBUFO 0xO3FB5 is stored at
130. 1 Parity bit is to detect wrong bits with transmission reception data Table 12 3 17 shows kinds of parity bit The SCINPE SCIPMI to 0 flag of the SC1MD2 register set parity bit Table 12 3 17 Parity Bit of UART Serial Interface SC1MD2 Parity bit Setup 1 SC1PM1 SC1PMO 0 0 0 Fixed to 0 Set parity bit to 0 0 0 1 Fixed to 1 Set parity bit to 1 0 1 0 Odd parity Control that the total of 1 of parity bit and character bit should be odd 0 1 1 Even parity Control that the total of 1 of parity bit and character bit should be even 1 Do not add parity bit Break Status Transmission Control Setup The 5 flag of the SC1MD2 register generates the brake status If SCIBRKE is set to 1 to select the brake transmission all bits from start bits to stop bits transfer 0 Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be deter mined by the SCIORE SC1PEK SCIFEF flag of the SCISTR register Even one of those errors is detected the SCIERE flag of the SCISTR register is set to 1 SCIPEK the SCIFEF flags in reception error flag are renewed at generation of the reception complete interrupt SCIRIRQ The SCIORE flag is cleared at the same time of next communication complete interrupt SC1RIRQ generation after the data of the RXBUFI is read out The decision of the received erro
131. 1 MOV Dn d16 Am Dn mem8 d16 Am 0010 0111 1 lt d16 gt Dn d4 SP Dn mem8 d4 SP 3 2 0111 01Dn d4 MOV Dn d8 SP Dn mem8 d8 SP 5 3 0010 0111 O1Dn dB gt E MOV Dn d16 SP Dn mem8 d16 SP 7 4 0010 0111 OODn lt df6 gt MOV Dn io8 08 4 2 0111 OODn lt 08 gt Dn abs8 Dn mem8 abs8 4 2 0101 01Dn lt abs 8 gt MOV Dn abs12 Dn mem 8 abs12 5 2 0101 00Dn abs 12 gt MOV Dn abs16 Dn mem8 abs16 7 4 0010 1101 O0Dn abs 16 gt MOV imm8 i08 imm8 mem8 IOTOP io8 6 3 0000 0010 lt 08 gt lt 8 gt MOV imm8 abs8 imm8 mem8 abs8 6 3 0001 0100 abs 8 gt lt 8 gt MOV imm8 abs12 imm8 memg8 abs12 7 3 0001 0101 abs 12 gt B gt MOV imm8 abs16 imm8 gt mem8 abs16 9 5 0011 1101 1001 abs 16 gt B gt MOV Dn HA Dnmem8 HA 2 2 1101 00Dn MOVW MOVW An DWm mem16 An gt DWm 55 2 1110 O0Ad MOVW mem16 An gt Am 3 4 0010 1110 10 4 MOVW 84 DWm 16 04 5 1110 0119 lt d4 gt 2 MOVW 84 5 mem16 d4 SP Am 3 1110 010a lt d4 gt MOVW d8 SP DWm mem16 d8 SP gt DWm 5 4 0010 1110 0119 d8 gt MOVW d8 SP Am 16 98 5 gt 5 4 0010 1110 010a d8 gt 3 M
132. 1 1 P7SEV1 Synchronous output 5 2 pRa e event selection 8 WEK R 122 Reset a P7SYO5 Synchronous output pRo control WEK R Figure 4 9 6 P75 Block Diagram Port 7 IV 77 4 I O Ports Pull up pull down resistor selection Pull up pull down resistor control direction control Port output data Port input data snq eed Write enable signal External Extension output control External interrupt 2 Timer 7 interrupt Timer 2 interrupt Timer 1 interrupt Synchronous output event selection Synchronous output control IV 78 Port 7 5 Reset P7PLU6 R Res b d P7DIR6 H R E P7OUT6 xcz Ho ue U lt lt 2j Yo 277 He Schmitt trigger input E P7ING M S amp eed Figure 4 9 7 P76 Block Diagram Pull up pull down resistor selection Pull up pull down resistor control direction control Port output data Port input data Data aknowledge signal External expancion P7DWN 2 2
133. 1 bit to 7 bits the data storing method to the received data buffer RXBUFI is differ ent depending on the first transfer bit At MSB first data are stored to the lower bits of RXBUF1 When there are 6 bits to be transferred as shown on figure Figure 12 3 4 if data to are stored to bpO to bp5 of RXBUFI the transmission is operated from F to A At LSB first data are stored to the upper bits of RXBUFI When there are 6 bits to be transferred as shown on Figure 12 3 5 if data A to F are stored to bp2 to bp7 of RXBUFI the transmission is operated from A to F RXBUF1 A B D E F Figure 12 3 4 Receive Bit Count and Transfer First Bit starting with MSB bit RXBUF1 F E D C B A Figure 12 3 5 Receive Bit Count and Transfer First Bit starting with LSB bit When the serial transfer bit is set between 1 to 7 the data except for received data of the specified transfer bit count is unknown Use the received data after being masked by AND OR instruction Operation XII 15 12 Serial interface 1 XII 16 Continuous Mode This serial has a function for continuous communication If data is set to the transmission data buffer TXBUFI during communication the transmission buffer empty flag SCITEMP is automatically set to interrupt SCITIRQ is generated after the former data is set Data setup to should be done till the co
134. 11 Serial interface 0 B Frame Mode and Parity Check Setup Figure 11 3 17 shows the data format at UART communication Frame Character bit TQ Figure 11 3 17 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 11 3 15 shows its kinds to be set Table 11 3 15 UART Serial Interface Transmission Reception Data Start bit 1 bit Character bit 7 8 bit Parity bit fixed to 0 fixed to 1 odd even none Stop bit 1 2 bits The 5 to 0 flag of the SC0MD2 register sets the frame mode Table 11 3 16 shows the serial inter face frame mode settings If the SCOCMD flag of the SCOMDI register is set to 1 and UART communication is selected the transfer bit count on the SCOLNG2 to 0 flag of the SCOMDO register is no more valid Table 11 3 16 UART Serial Interface Frame Mode SCOMD2 register Frame mode SCOFM1 SCOFMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits Operation XI 41 11 Serial interface 0 Parity bit is to detect wrong bits with transmission reception data Table 11 3 17 shows kinds of parity bit The SCONPE SCOPMI to 0 flag of the SCOMD2 register set parity bit Table 11 3 17
135. 11 3 24 UART Interface Transmission Reception Setup Setup item SEt to TXDO RXDO pin Independent with 2 channels Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source Timer 4 Used pins A TXDO RXDO pin type Nch open drain Pull up resistor of TXDO pin Added Parity bit add check 0 added check Serial 0 transmission complete interrupt Enable Serial 0 reception complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the baud rate timer 1 Set the baud rate timer by the TM4MD register the 4 register Set the TM4EN flag to 1 to start timer 4 Chapter 5 5 9 Serial Transfer Clock Output Operation 2 Select the clock source SCOMD3 0x03F92 bp2 0 SCOPSC2 0 111 3 Select the used pins SCSEL 0x03F4F SCOSEL 0 4 Control the pin type POODC 0x03F1C POODCO 1 POPLU 0x03F40 POPLUO 1 2 Set the to 0 flag of the SCOMD3 register to 111 to select Timer 4 output as a clock source 3 Set the SCOSEL flag of SCSEL register to 0 to select the I O pin to A portO 4 Set the POODCO flag of the POODC register to 1 to select Nch open drain for the TXDO pin POPLUO flag of the POPLU register to 1 to add pull up register XI 54 Operation 11 Serial interface 0
136. 19JSue1 2415011 NE 0054205 5 LOSdEOS SLESEOS 2084608 5188628 3064608 6088606 ndino 1ejeose1g ETENIM ALSZOS 989628 15205 c o x 5 0 aweos 8 a s 250 99598 iino 1868628 A 1 x sed ae1as ae os HINDI N 3 s H e Xbeaive1asive1os x 10d 135626 n x n QWNOEOS 30606 N MOV 6188608 gt JejsueJ 020 625 8254625 8054625 254625 0254625 59 595 100 606 J dols uonipuoo uelis 991205 1 151 1 1145 1165605 9 455 1 3198955 8 1 lt gt 5 dvMS uonoejep uelis luwpe tu l CE 5 1 WOIEOS Figure 14 1 1 Serial Interface 3 Block Diagram Overview XIV 4 14 Serial Interface 3 14 2 Control Registers 14 2 1 Registers List Table 14 2 1 shows the registers that control serial interface 3 Table 14 2 1 Serial Interface 3 Control Registers List Register Address Function SC3MDO Ox03
137. 2 12 9615 3 31250 fs 4 1 31250 8 38 fosc 54 9523 26 19398 fosc 4 fosc 16 fosc 32 fosc 64 16 2 16 4 12 00 fosc 77 9615 38 19231 25 28846 23 31250 fosc 4 5 31250 fosc 16 fosc 32 fosc 64 16 2 5 31250 fs 4 2 31250 16 00 fosc 103 9615 51 19231 31 31250 25 38462 fosc 4 25 9615 12 19231 7 31250 105016 1056 32 1056 64 6 2 25 9615 7 31250 fs 4 12 9615 3 31250 Figure 11 3 25 Setup Value of UART Serial Interface Transfer Speed Operation XI 49 11 Serial interface 0 B Pin Setup with 1 2 channels at transmission Table 11 3 20 shows the pins setup at UART serial interface transmission The pins setup is common to the TXDO pin RXDO pin regardless of those pins are independent connected Table 11 3 20 UART Serial Interface Pin Setup with 1 2 channels at transmission Setup item Data output pin Data input pin TXDOA pin TXDOB pin RXDOA pin RXDOB pin Port pin P00 P90 P01 P91 Port pin selection Select the used pin A B SCSEL SCOSEL TXDO RXDO pin selection TXDO RXDO pin independent connect SCOMD1 SCOIOM Function Serial data output 1 input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Push pull Nch open drain POOD
138. 2 Consult the table of contents at the front of the manual to locate desired titles 3 A chapter number and its chapter title are located at the top corner of each page and section titles are located at the bottom corner of each page mRelated Manuals Note that the following related documents are available MNIOIE Series Instruction Manual Describes the instruction set e Series C E Compiler User s Manual Usage Guide Describes the installation the commands and options of the C Compiler MNIOIC Series C Compiler User s Manual Language Description Describes the syntax of the C Compiler MNIOIC Series C Compiler User s Manual Library Reference Describes the standard library of the C Compiler e MNIOI C E Series Cross assembler User s Manual Describes the assembler syntax and notation MNIOIE Series C Source Code Debugger User s Manual Describes the use of C source code debugger gt e About This Manual MNIOIE Series PanaX Series Installation Manual Describes the installation of C compiler cross assembler and C source code debugger and the procedure for bringing up the in circuit emulator About This Manual 2 lt About This Manual 3 gt Contents Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 Ports Chapter 5 8 Bit Timers Chapter 6 16 Bit Timers Chapter 7 Time Base Timer 8 Bit Free running Timer Chapter 8 Remote Control Fu
139. 3 Set CPUM to HALT or STOP mode Do not set STANDBY function STOP HALT OSC1 and OSC2 flags and clock swiching function OSCDBL OSCSEL1 and OSCSEL2 flags at the same time Set the IRWE flag of the memory control register MEMCTR to clear interrupt request flag by software 46 Standby Function Chapter 2 CPU Basics 2 5 3 Transition between SLOW and NORMAL Ra 3 c _ This LSI has two CPU operating modes NORMAL SLOW Transition from SLOW to NORMAL requires passing through IDLE mode A sample program for transition from NORMAL to SLOW mode is given below Program 1 MOV DO Set SLOW mode MOV DO CPUM Transition from NORMAL to SLOW mode when the low frequency clock has fully stabilized can be done by writing to the CPU mode control register In this case transition through IDLE is not needed For transition from SLOW to NORMAL mode the program must maintain the idle state until high frequency clock oscillation is fully stable In IDLE mode the CPU operates on the low frequency clock as that after reset Software must count that time We recommend selecting the oscillation a For transition from SLOW to NORMAL oscillation stabilization waiting time is required same stabilization time after consulting with oscillator manufacturers 1 Set the clock frequency more than four before transition from SLOW to NORMAL IDLE state mode 2 Use the RAM
140. 3 3 1 to 3 3 6 So i flag is 0 and pin is 0 or flag is 1 and pin is 1 before standby interrupt is gener ated at the standby mode and CPU can be returned Ill 64 External Interrupts 3 3 7 Key Input Interrupt Chapter 3 Interrupts Key Input Interrupt External interrupt 4 This LSI can set port 6 P60 to P67 pin by 2 bit to key input pin An interrupt can be generated at the falling edge if at least 1 key input pin outputs low level Standby mode can be recovered by the key interrupt Key input pin should be pull up in advance Key Input Interrupt Setup Example External interrupt 4 After P60 to P63 of port 6 are set to key input pins and key is input L level the external interrupt 4 IRQ4 is generated An example setup procedure with a description of each step is shown below Setup Procedure 1 Set the key input to input P6DIR 0x03F36 bp3 0 P4DIR3 0 0000 2 Set the pull up resistor P6PLU 0x03F46 bp3 0 P6PLU3 0 1111 3 Select the key input interrupt KEYT3_1IMD 0x03F3E bp7 KEYT3_1SEL 1 4 Select the key input pin KEYT3_1IMD 0x03F3E bp1 0 KEYT3_1EN1 0 11 5 Set the interrupt level IRQ4ICR 0x03FE6 bp7 6 IRQ4LV1 0 10 6 Enable the interrupt IRQ4ICR 0x03FE6 bp1 IRQ4IE 1 Above 3 and 4 can be set at the same time Description 1 Set the P6DIR3 to 0 flag of the port 6 direction con trol register P6DIR to 0000 to set P40 to P43
141. 331 3789 EUROPE OG Europe Sales Office Panasonic Industrial Europe GmbH PIE U K Sales Office Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Germany Sales Office Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE Tel 65 6390 3688 Fax 65 6390 3689 e Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60 3 7951 6601 60 3 7954 5968 Fax 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2003 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang MALAYSIA Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Oe Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division of Matsushita Ele
142. 35 12 Serial interface 1 XII 36 Setup Procedure Description 5 Select the transfer bit count SC1MD0 0x03F9D bp2 0 SC1LNG2 0 111 6 Select the start condition SC1MD0 0x03F9D bp3 SC1STE 0 7 Select the first bit to be transferred SC1MD0 0x03F9D bp4 SC1DIR 0 8 Select the transfer edge SC1MD0 0x03F9D bp7 SC1CE1 1 9 Select the communication type SC1MD1 0x03F9E bp0 SC1CMD 0 10 Select the transfer clock SC1MD1 0x03F9E bp2 SC1MST 0 bp3 SC1CKM 0 11 Control the pin function SC1MD1 0x03F9E bp4 SC1SBOS 0 bp5 SC1SBIS 1 bp6 SC1SBTS 1 bp7 5 1 0 12 Set the interrupt level SC1TICR 0x03FF5 bp7 6 SC1LV1 0 10 13 Enable the interrupt SC1TICR 0x03FF5 bp1 SC1TIE 1 14 Set the startup factor of the serial communication Dummy data y TXBUF1 0x03FA3 15 Transfer to STOP mode CPUM 0x03F00 bp3 STOP 1 16 Start the serial communication Transmission clock y input SBT1 pin Received data y input SBI1 pin 5 Set the SC1LNG2 to 0 flag of the serial 1 mode register SC1MD0 to 111 to set the transfer bit count 8 bits 6 Set the SC1LNG2 to 0 flag of the serial 1 mode register SC1MD O to 111 to disable the start condition 7 Set the SC1DIR flag of the SC1MDO register to O to set MSB as a transfer first bit 8 Set the SC1CE1 flag of the SC1MDO register to 1 to set the reception data input edge falling 9
143. 4 217 300 67 963 12 00 fosc 155 4808 fosc 4 194 962 155 1202 77 2404 38 4808 fosc 16 155 300 38 1202 1050 32 77 300 fosc 64 38 300 fs 2 194 962 155 1202 77 2404 38 4808 16 4 77 1202 38 2404 16 00 fosc 207 4808 fosc 4 207 1202 103 2404 51 4808 fosc 16 207 300 64 962 51 1202 25 2404 12 4808 fosc 32 103 300 25 1202 12 2404 fosc 64 51 300 12 1202 16 2 207 1202 103 2404 51 4808 16 4 129 962 103 1202 51 2404 25 4808 Operation Figure 15 3 24 Setup Value of UART Serial Interface Transfer Speed Transfer Speed 61 5 Chapter 15 Serial interface 4 fosc MHz Timer Clock source 9600 19200 28800 31250 38400 caluculated Set Set Value caluculated value Set Value caluculated value luculated Set Value Set Value 008 value 4 00 fosc 25 9615 12 19281 7 31250 fosc 4 1 fosc 16 31250 1056 32 1056 64 16 2 31250 16 4 4 19 fosc 26 fosc 4 9699 fosc 16 1056 32 1056 64 16 2 16 4 8 00 fosc 51 9615 25 19281 31250 38462 fosc 4 fosc 16 9615 31250 1056 32 1056 64 16 2 9615 31250 16 4 8 38 fosc 54 9523 26 19398 31250 fosc 4 fosc 16 105
144. 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Panasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 1 858 715 5545 e Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 CANADA Tel 1 905 238 2315 1 905 238 2414 LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 335 9000 55 12
145. ANO the converter clock is set to fs 4 and the sampling hold time is set to Tap x 6 Then A D conversion complete interrupt is generated example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the analog input pin PAIMD 0x03F3B PAIMDO 1 PAPLU 0x03F4A bp0 PAPLUO 0 2 Select the analog input pin ANCTR1 0x03FB3 bp2 0 ANCHS2 0 000 3 Select the A D converter clock ANCTRO 0x03FB2 bp5 4 ANCK1 0 01 4 Set the sample and hold time ANCTRO 0x03FB2 bp7 6 ANSH1 0 01 5 Set the interrupt level ADICR 0x03FFA bp7 6 ADLV1 0 00 6 Enable the interrupt ADICR 0x03FFA bp1 ADIE 1 7 Set the A D ladder resistance ANCTRO 0x03FB2 bp3 ANLADE 1 8 Start A D conversion ANCTR2 0x03FB4 bp6 ANSTSEL1 0 9 Start A D conversion operation ANCTR2 0x03FB4 bp7 ANST 1 1 Set the analog input pin set in a 2 as the special function pin with the port A input mode register PAIMD Also set no pull up pull down resistance with the port A pull up pull down resistance control register PAPLUD 2 Select the analog input pin from AN7 to ANO by the ANCH2 0 flag of the A D converter control register1 ANCTR1 3 Select the A D converter clock by the ANCK1 ANCKO flag of the A D converter control register ANCTRO 4 Set the sample and hold time by the ANSH1 ANSHO flag of the A D converter control register A
146. At reset 0 0 0 0 0 Access R W IRQ4LV1 IRQ4LV0 Description External interrupt level flag The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for inter rupt requests REDG4 External interrupt valid edge flag 0 Falling edge 1 Rising edge IRQ4IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt III 24 IRQ4IR Control Registers External interrupt request flag 0 No interrupt request 1 Interrupt request generated 3 Interrupts B External Interrupt 5 Control Register IRQ5ICR The external interrupt 5 control register IRQSICR controls interrupt level of external interrupt 5 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSE is 0 Table 3 2 8 External Interrupt 5 Control Register IRQ5ICR 0x03FE7 bp 7 6 5 1 0 Flag IRQ5LV1 IRQ5LVO REDG5 IRQSIE IRQSIR At reset 0 0 0 0 0 Access R W Description IRQ5LV1 External interrupt level flag at the standby mode IRQ5LV0 The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for inter rupt requests REDG5 External interrupt valid edge flag 0 Falling edge low level 1 Rising edge high level IRQSIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQ5IR E
147. Chapter 15 Serial interface 4 Table 15 3 7 shows the setup for synchronous serial interface pin with 3 channels SBO4 pin SBI4 pin SBT4 pin at transmission Table 15 3 7 Setup for Synchronous Serial Interface Pin with 3 channels at transmission Setup item Data output pin Data input pin Clock I O pin SBOA pin SBI4 pin SBT4 pin Clock master Clock slave SC4MD1 SC4MST Port pin P40 P41 P42 Serial data input SBI4 selection SC4MD1 SC4IOM Function Serial data output 1 input Transfer clock input Transfer clock input output output SCAMD1 SCASBO SC4MD1 SC4SBIS SC4MD1 SC4SBTS S Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain P4ODC PA4ODCO PAODC PAODC2 Output mode Output mode Input mode P4DIR P4DIR0 P4DIR P4DIR2 Pull up setup Added Not added Added Not added Added Not added PAPLU PAPLUO PAPLU PAPLU2 Operation XV 27 15 Serial interface 4 XV 28 B Pins Setup with channels at reception Table 15 3 8 shows the setup for synchronous serial interface pin with 3 channels 5804 pin SBI4 pin SBT4 pin at reception Table 15 3 8 Setup for Synchronous Serial Interface Pin with 3 channels at reception Setup item Data output pin Data input pin Clock I O pin SBOAA pin SBI4 pin SBT4 pin Clock m
148. E D Figure 13 3 3 Transfer Bit Count and First Transfer Bit LSB First Receive Bit Count and First Transfer Bit When the transfer bit count is 1 to 7 bits data storage to the transmit receive shift register SC2TRB depends on the first transfer bit When MSB is the first bit to be transferred the lower bits of SC2TRB are used for storage In Figure 13 3 4 as the transfer bit count is 6 bits data A to are stored to bp5 to bp0 of SC2TRB and they are transferred from to When LSB is the first bit to be transferred use the upper bits of SC2TRB for storage In Figure 13 3 5 data A to F are stored to bp2 to bp7 of SC2TRB as the transfer bit count is 6 bits and they are transferred from A to F SC2TRB D E F Figure 13 3 4 Receive Bit Count and First Transfer Bit MSB First XIII 16 Operation 13 Serial Interface 2 SC2TRB F D C B Figure 13 3 5 Receive Bit Count and First Transfer Bit LSB First When the serial transfer bit is set between 1 to 7 the data except for received data of the specified transfer bit count is unknown Use the received data after being masked by AND OR instruction Continuous Mode Serial interface 2 is capable of continuous transmission If data is set to transmission data buffer TXBUF2 during transmission transmission buffer empty flag SC2TEMP is set and the set data is automatic
149. Flag P2DIR5 P2DIR4 P2DIR3 P2DIR2 P2DIR1 P2DIR0 At reset 0 0 0 0 0 0 Access R W R W R W R W R W R W bp Flag Description 7 6 5 P2DIR5 I i pene ut mode 2 PeDIR2 1 P2DIR1 0 P2DIR0 IV 28 Port 2 Port 2 Pull up Resistor Control Register P2PLU 0x03F42 P2PLU5 P2PLU4 P2PLU3 P2PLU2 P2PLU1 Chapter 4 I O Ports P2PLUO 0 0 0 0 0 0 gt O Q O P2PLU5 P2PLU4 P2PLU3 P2PLU2 P2PLU1 P2PLU0 Description Pull up resistor selection 0 Not added 1 Added Port 2 IV 29 4 I O Ports 4 4 3 Block Diagram Y g Schmitt trigger input 777 Figure 4 4 1 P20 Block Diagram L Schmitt trigger input POPLUO Pull up resistor WEK R m P2DIRO direction Pg control WEK R 5 S 2 Port output data o t Q EUIS 5 WEK R P2IN Port input data lt J R Externa interrupt 0 input P2PLU1 Pull up resistor t contorol WEK R b DIR I O direction Ro 5 I control WEK R P2OUT1 Port output data WEK R Port input data lt 1 R Externa interrupt 1 input IV 30 Port 2 Figure 4 4 2 P21 Block Diagram X i P2PLU2 Pull up resist
150. IM in the PSW As a result subsequent interrupts with the same or lower priority lev els are automatically masked Only interrupts with higher priority levels are accepted The net result is that interrupts are normally processed in decreasing order of priority It is however possible to alter this arrangement 1 To disable interrupt nesting Reset the MIE bit in the PSW to 0 Raise the priority level of the interrupt mask IM in the PSW 2 To enable interrupts with lower priority than the currently accepted interrupt Lower the priority level or the interrupt mask IM in the PSW Multiplex interrupts are only enables for interrupts with levels higher than the PSW interrupt mask level IM It is possible to forcibly rewrite IM to accept an interrupt with a priority lower than the interrupt being processed but the careful of stack overflow Do not operate the maskable interrupt control register xxxICR when multiple interrupts are Y enabled If operation is necessary first clear the PSW MIE flag Overview Ill 13 Chapter 3 Interrupts B Multiple Interrupt of Non maskable On the acceptance of nim interrupt when other nmi interrupt factor is generated this interrupt is processed right away Also when the same nmi interrupt factor is generated before nmi interrupt flag is be soft cleared it is not accepted Unless nmi interrupt clears the flag by the soft the following same nmi interrupt is no
151. IRQO External interrupt input 0 P21 IRQ1 in out P2DIR1 P2PLU1 IRQ1 External interrupt input 1 P22 IRQ2A in out P2DIR2 P2PLU2 IRQ2A External interrupt input 2 P23 IRQ3A in out P2DIR3 P2PLU3 IRQ3A External interrupt input P24 IRQ4 in out P2DIR4 P2PLU4 IRQ4 External interrupt input 4 P25 IRQ5 in out P2DIR5 P2PLU5 IRQ5 External interrupt input 5 P27 NRST in NRST Reset P30 SBO1 TXD1 in out PSDIRO P38PLUO 5801 Serial 1 transmission data out TXD1 UART 1 transmission data put output P31 SBI1 RXD1 in out P3DIR1 P3PLU1 SBI1 Serial 1 reception data input RXD1 UART 1 reception data input P32 SBTI in out P3DIR2 P3PLU2 SBT1 Serial 1 clock input output P33 5 5 in out P3DIR3 P3PLU3 Serial transmission data IIC3 data input output output P34 in out P3DIR4 P3PLU4 SBI3A Serial reception data input P35 SBT3A SCL3A in out P3DIR5 P3PLU4 SBT3A Serial 3 clock input output clock input output P40 SBO4 TXD4 in out P4DIRO P4PLUO 5804 Serial 4 transmission data out TXD4 UART 4 transmission data put output P41 SBI4 RXD4 in out P4DIR1 P4PLU1 SBI4 Serial 4 reception data input RXD4 UART 4 reception data input P42 SBT4 in out P4DIR2 P4PLU2 SBT4 Serial 4 clock input output P43 in out P4DIR3 P4PLU3 P50 AO in out P5DIRO P5PLUO 0 Address output bpO P51 Al in out P5DIR1 P5PLU1 1 Address output bp1 P52 A2 in out P5DIR2 P5PLU2 A2 Addre
152. J 2 Machine clock is generated based on the system clock dividing the source oscillation frequency The machine clock is the base timing for control of CPU Internal Memory Access no wait cycle NORMAL mode Source oscillation zT pm spe 3 frequency System clock fs ZEE EN NE ESL i 1 machine clock 1 bus cycle Figure 2 1 9 Machine Clock no wait cycle External Memory Access 0 1 2 3 wait cycle NORMAL mode Source oscillation sip eese EN frequency System clock fs r T qe 7 i No wait cycle 1 wait insert i gt i 2 insert i x 3 wait insert Figure 2 1 10 Machine Clock memory wait cycle Wait cycle is set to fixed three wait cycle mode at reset start a Oscillation frequency of system clock differs depending on the CPUM register settings Chapter 2 2 6 Clock Switching Overview 15 2 CPU Basics 16 2 2 Memory Space 2 2 1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable writable data In addition to these peripheral resources such as memory mapped special registers are allocated The MNIOIE series supports three memory modes single chip mode memory expansion mode processor mode in its memory model This LSI supports three memory modes single chip mode memory expan
153. L and set the destination I O address in lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH and ATIMAPIM Transfer mode 0 does not have an increment function for the memory pointers and executes data transfer for a fixed address Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt occurs and the automatic transfer ends Operation XVIII 17 18 Automatic Transfer Controller 18 3 6 Transfer Mode 1 Sf In transfer mode 1 ATC1 automatically transfers one byte of data from the I O space special registers 0x03F00 Ox03FFF to any memory space everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to O3FFF 1 he Only lower 8 bits are valid ATMAPO 1 ATMAPO 2 __ 3 Figure 18 3 3 Transfer 1 Set the source I O address in lower 8 bits of memory pointer 1 ATIMAPIL and set the destination address in 20 bit memory pointer 0 ATIMAPOH M L You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH and ATIMAPIM Transfer mode 1 does not have an increment function for the memory pointers and executes data transfer for a fixed address
154. MHz at operation is selected as a clock source to generate an interrupt every 1000 cycles 100 ms An example setup procedure with a description of each step 15 shown below Setup Procedure Description 1 Stop the counter TM7MD 1 0x03F78 bp4 TM7EN 0 2 Disable the interrupt TM7ICR 0x03FFO TM7IE 0 3 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 4 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 01 5 Set the interrupt generation cycle TM7PR1 0x03F75 0x03F74 0x03E7 6 Set the interrupt level TM7ICR OxOSFFO bp7 6 TM7LV1 0 10 7 Enable the interrupt TM7ICR 0x03FF0 TM7IE 1 8 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD to 0 to stop the timer 7 counting 2 Set the TM7IE flag of the TM7CIR register to 0 to disable the interrupt 3 Set the TM7BCR flag of the timer 7 mode register 2 TM7MD2 to 1 to select the compare match to the binary counter clear source 4 Select fosc to the clock source by the TM7CK1 to 0 flag of the TM7MD1 register Besides select 1 2 fosc to the count clock source by the TM7PS1 to 0 flag b Set the interrupt generation cycle to the timer 7 preset register 1 TM7PR1 The cycle is 1000 The set value should be 1000 1 999 0x03E7 At the time the same value is loaded to the timer 7 compare regis
155. NWE lt Read j Write Figure 2 4 2 ROM and RAM Access Timing with No Wait Cycles Access Timing with 1 Wait Cycle Access timing with 2 or 3 wait cycles follows the same pattern The latter part of the cycle is extended and the timing is the same Syetem clock fs NCS NRE NWE Eg I Read Write Figure 2 4 3 ROM and RAM Accoess Timing with 1 Wait Cycle II 42 Bus Interface 2 4 5 External Memory Connection Example Chapter 2 CPU Basics ROM Connection Example memory expansion mode This example shows connection to 128 KB ROM This LSI ROM 0x00000 A19 to AO A19 to D7 to DO lt D7 to DO 0x70000 NCS gt NCS NRE gt External ROM area MMOD 4 77 Ox8FFFF Figure 2 4 4 ROM Connection Example ROM Connection Example processor mode This example shows connection to ROM The external expansion RAM area is 0x02F00 to 0x3EFF This LSI ROM 0x00000 A19 to AO gt A19 to AO D7 to 00 lt D7 to DO 0x04000 NCS NCS NRE gt MMOD 0x53FFF Figure 2 4 5 ROM Connection Example processor mode Bus Interface 43 2 CPU Basics II 44 2 5 Standby Function 2 5 1 Overview This LSI has two sets of system clock oscillator high speed oscill
156. O Ports 0x03F35 Port 5 Direction Control Register 0x03F45 Port 5 Pull up Resistor Control Register 0x03F16 Port 6 Output Register 0x03F26 Port 6 Input Register 0x03F36 Port 6 Direction Control Register 0x03F46 Port 6 Pull up Resistor Control Register 0x03F0E Address Output Control Register 0x03F17 Port 7 Output Register 0x03F27 Port 7 Input Register 0x03F37 Port 7 Direction Control Register 0x03F47 Port 7 Pull up Pull down Resistor Control Regis ter 0x03F1F Port 7 Synchronous Output Control Register 0x03F2F Port 7 Synchronous Output Event Selection Reg ister 0x03F4B Pull up Pull down Resistor Selection Register 0x03F0E Address Output Control Register 0x03F18 Port 8 Output Register 0x03F28 Port 8 Input Register 0x03F38 Port 8 Direction Control Register 0x03F48 Port 8 Pull up Resistor Control Register 0x03F19 Port 9 Output Register 0x03F29 Port 9 Input Register 0x03F39 Port 9 Direction Control Register 0x03F49 Port 9 Pull up Resistor Control Register OxOSF4C Port 9 Nch Open drain Control Register OxOSF1A Port A Output Register OxOSF2A Port A Input Register Port A Direction Control Register 0x03F4A Port A Pull up Pull down Resistor Control Regis ter 0x03F4A Port A Input Mode Register 0x03F1D
157. OIZIALL 22X 5 4 dois 1unoOo H gOti peed uonez 5 indu 158 OSZWL x Jejunoo G n OuIEIA L Y 050 90J9 j euesS x 4e1siDoJ indino OIgIALL f uA pe ti x HSH OGeWL n Jejunoo 9 8 IN uonez iuouuouAS indu OIEWL OOEIA L 4 49 1 w A Ses EMOESIAL OMOEIALL Figure 5 1 3 Timers 2 and 3 Block Diagram Overview V 6 5 8 bit Timers Timers 4 and 5 Block Diagram dOdvIN L 19JsueJ jeuog vINMdAndino zx rm 5 Navn dois OulSIA L 158 Jejunoo 1198 X90j9 ELAS 1ndino OISIALL Jejunoo 198 1 eiuwpeeu 2 juoyuou S 05891 250 uonez 1uojuogu S Hindu x V
158. OxF0000 to OxF3DFF 0x00000 to 0x03DFF Mapped to same RAM space Special function register oxosEoo 0 5KB 0x04000 48KB 0x10000 0 0000 15 5 Mirror OxF3E00 64KB Physical s RAM 48 5KB Figure 2 2 1 RAM Space Memory Space Il 21 2 CPU Basics How to use mirror RAM Space Sub routine Address bank 15 mov x OF SBNKR Source side mov DBNKR Distination side Transfer data 15 between memories 1 mov x XYZZ dn mov dn x ABCD XYZZ gt x ABCD x ABCD x XYZZ are address of abs16 Sub routine B Address bank 0 mov x ABCD 1 Use mirror function 2 Execute the same access ignoring the upper 4 bits 2 Data fetch Special function register g 5KB 0x04000 48KB 0x10000 0 0000 15 5KB Mirror RAM OxF3000 Physical RAM 1 Data trans 48 5KB OxFFFFF Figure 2 2 2 How to use mirror RAM Space 22 Memory Space Chapter 2 CPU Basics 2 2 4 Single chip Mode In single chip mode the system consists of only internal memory This is the optimized memory mode and allows construction of systems with the highest performance The single chip mode uses only internal ROM and internal RAM The MNIOIE series devices offer up to 64 KB of RAM and up to 944 KB of ROM This LSI offers 14
159. P05 is H Transmission data TXBUF2 0x03F9B 15 Transmission ends Setup of the next data transmission Judge the monitor flag SC2CTR 0x03F9C bp6 IICSTC 16 Judge the ACK bit level SC2CTR 0x03F9C bp0 SC2ACKO 17 Set the SC2MDO register Select the transfer bit count SC2MDO 0x03F96 bp2 0 SC2LNG2 0 18 Next data transmission is started Serial transmission is started 14 19 Transmission ends lt communication end processing Set the IICSTPC flag SC2CTR 0x03F9C bp5 IICSTPC 1 13 Set 1 to the SC2IE flag of the SC2ICR register to enable the interrupt If the interrupt request flag SC2IR of the SC2ICR register is already set clear SC2IR before the interrupt is enabled Chapter 3 3 1 4 Interrupt Flag Setup 14 Set the transmission data to the transmission reception shift register TXBUF2 Then the transfer clock is generated to start transmission If the ACK bit is received after data transmission the communication end interrupt SC2IRQ is generated 15 Confirm the IICSTC flag of the serial 2 control register SC2CTR When the previous transmission is completed properly IICSTC 0 If IICSTC 1 the communication should be re executed 16 Confirm the level of the ACK bit received by the SC2ACKO flag of the serial 2 control register SC2CTR When SC2ACKO 0 you can continue the transmission When SC2ACKO 1 the reception at slave ma
160. P23 or PD1 by setting of the external interrupt pin switching control register IRQSEL When IRQ3SEL flag of the external interrupt pin switching control register IRQSEL is 0 P23 is selected and 1 PD1 is selected P24 1s used as external interrupt 4 pin as well P25 is used as external interrupt 5 pin as well Port 2 Chapter 4 I O Ports 4 4 2 Registers The following Table shows registers that control the Port 2 Table 4 4 1 Port 2 Control register Registers Address R W Function Page P2OUT 0x03F12 R W Port 2 Output Register IV 27 R 0x03F22 0x03F32 R W Port 2 Direction Control Register 0x03F42 RAN Port 2 Pull up Resistor Control Register Port 2 Input Register R W Readable Writable Port 2 Output Register P2OUT 0x03F 12 Ee 5 14 90 387 44 6 5 P2OUT7 P2OUT5 P2OUT4 P2OUT3 P2OUT2 P2OUT1 P2OUTO At reset x x x x x x x bp Flag Description P2OUT7 P2OUT5 P2OUT4 Output data 0 Output L VSS level 1 Output H VDD level P2OUT3 P2OUT2 P2OUT1 P2OUTO O S G OQ O Port 2 IV 27 4 I O Ports Port 2 Input Register P2IN 0x03F22 bp Flag Description 7 P2IN7 6 E Input data 0 Pin is L VSS level 3 Pee 1 Pin is H VDD level 2 P2IN2 level 1 P2IN1 0 P2IN0 Port 2 Direction Control Register P2DIR 0x03F32
161. P64 P65 P66 P67 Address output control 0 l O port 1 address output EXADV1 P60 P61 P62 P63 Address output control 0 l O port 1 address output Port 7 IV 71 4 I O Ports 4 9 3 Block Diagram rN Reset PZDWN Pull up pull down resistor t selection WEK R Y Reget Pull up pull down resistor P7PLU0 control Wek YR Reset direction control 7180 2j WEK lx g or 5 P7OUT Port output data q Q 0 21 M WC A e K R EK x Y ____ gt Schmitt trigger input 1 lt EANO vJ R Address output External Extension output control External interrupt 2 00 Timer 7 interrupt T M Timer 2 interrupt WU Timer 1 interrupt x Reset Synchronous output 2 pRa lection 2 WE event selection S K R g Reset Bey 7 Synchronous output control WEK R RE Figure 4 9 1 P70 Block Diagram IV 72 Port 7 Chapter 4 I O Ports A Reget PZDWN Pull up pull down resistor if selection Wek R 57 Reset P7PLU1 Pull up pull down resistor control Reset P7DIR1 direction control H c
162. RXD1 34 P04 SBI1 Pull up and pull down resistors can be selected by the POPLU RXD4 73 P41 SBI4 P3PLU P4PLU and P9PLUregisters Select the input mode with the PODIR PSDIR P4DIR and P9DIR registers and serial input mode by serial mode register 1 SCOMD1 SC1MD1 SC4MD1 These can be used as normal I O pins when the serial interface is not used SDA2 7 yo SBO2 IIC data pins In the serial interface in mode this pin is configured as the SDA3A 36 P33 SBO3A data output pin SDA3B 79 P93 SBO3B The output configuration n channel open drain can be selected and select pull up resistor with the PODC and P9DC reg ister Pull up and pull down resistors can be selected by the POPLU and registers Select output mode with the PODIR P3DIR and P9DIR register and serial data I O at the serial mode register 1 SC2MD1 SC3MD1 These can be used as normal I O pins when the serial interface is not used Pin Description 1 15 1 Overview Name NO Other Function Function Description SCL2 9 Output P05 SBT2 IIC clock output In the serial interface in IIC mode this pin is configured as the SCL3A 38 P35 SBT3A pins clock output pin SCL3B 81 P95 SBT3B The output configuration n channel open drain can be selected and select pull up resistor with the PODC P3DC and P9DC reg ister Pull up and pull down resistors can be selected by the POPLU P
163. Registers This is readable writable register that controls timer 6 and time base timer Timer 6 Mode Register TM6MD 0x03F6A 7 6 5 4 3 2 1 0 At reset TM6CLR TM6IR2 TM6IR1 TM6IR0 TM6CK3 TM6CK2 TM6CK1 TM6ICKO Access bp Flag TM6CLRS Description Timer 6 binary counter clear selection flag 0 Enable the initialization of TM6BC as TM6OC is written 1 Disable the initialization of TM6BC as 6 is written TM6IRQ is disable as TM6CLRS 0 TM6IRQ is enable as TM6CLRS 1 TM6IR2 TM6IR1 TM6IR0 TM6CK3 TM6CK2 TM6CK1 Time base timer interrupt cycle selection 000 Time base selection clock x 1 2 001 Time base selection clock x 1 28 010 Time base selection clock x 1 29 011 Time base selection clock x 1 210 10 Time base selection clock x 1 21 11 Time base selection clock x 1 219 Timer 6 clock source selection 000 fosc 001 fs 010 fx 011 Synchronous fx 100 Time base selection clock x 1 2 3 101 Synchronous time base selection clock x 1 213 110 Time base selection clock x 1 212 111 Synchronous time base selection clock x 1 21 TM6CKO Control Registers Time base timer clock source selection 0 fosc 1 fx 7 Time Base Timer Free running Timer 7 3 8 bit Free running Timer 7 3 1 Operation 8 bit Free running Timer Timer 6 The generation cycle of the timer interrupt should be set in advance by the
164. SBTO TXDO RXDO 3 channels type 2 channels type O SBOO SBTO 1 channel type TXDO Specification of transfer bit count Frame 1 to 8 bits 7 bit 1STOP selection 7 bit 28TOP 8 bit 1 STOP 8 bit 2STOP Selection of parity bit Parity bit control 0 parity 1 parity odd parity even parity Selection of start condition Only enable start condition is available Specification of the first transfer bit O Specification of input edge output edge Overview 11 Serial interface 0 SBOO output control after final data H L final data hold moved out At the standby mode Only slave reception is available Continuous operation O O Internal clock 1 8 dividing O Only 1 8 dividing is available Clock source fosc 2 fosc 2 fosc 4 fosc 4 fosc 16 fosc 16 fosc 64 fosc 64 fs 2 fs 2 fs 4 fs 4 External clock Timer 2 output Timer 2 output Timer 4 output Timer 4 output Maximum transfer rate 5 0 MHz 300 kbps fosc Machine clock High speed oscillation fs System clock 1 Set the transfer rate slower than system clock fs Overview XI 3 11 Serial interface 0 Block Diagram 11 1 2 Serial interface 0 Block Diagram
165. SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin P00 P90 P01 P91 P02 P92 Set port pin Select used pin A B SCSEL SCOSEL SBIO SBOO selection SBI0 SBO0 connection SCOMD1 SCOIOM Function Serial data input 1 input Serial clock input Serialclock input output output SCOMD1 SCOSBO SCOMD1 SCOSBIS SCOMD1 SCOSBIS S Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain POODC POODCO POODC POODC2 PSODC P9ODC2 PSODC P9ODCO Output mode Output mode Input mode PODIR PODIRO PODIR PODIR2 PSDIR P9DIR2 P6DIR P6DIRO Pull up setup Added Not added Added Not added Added Not added POPLU POPLUO POPLU POPLU2 PSPLU P9PLUO P9PLU P9PLU2 Operation XI 81 11 Serial interface 0 XI 32 B Pins Setup with 2 channels at reception Table 11 3 11 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at reception SBIO pin can be used as a port Table 11 3 11 Setup for Synchronous Serial Interface Pin with 2 channels at reception Setup item Data output pin Serial unused pin Clock I O pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin P00 P90 P01 P91 P02 P92 Port pin selection Select used pin A B SCSEL SC0SEL SBIO SBOO selection S
166. SC1MDO 0x0O3F9D bp3 SC1STE 0 Select the first bit to be transferred SC1MDO0 0x03F9D bp4 SC1DIR 0 Select the transfer edge SC1MDO 0x0O3F9D bp7 SC1CE1 1 7 Set the SC1MD1 register Select the communication style SC1MD1 0x03F9E bp0 SC1CMD 0 Select the transfer clock SC1MD1 0x03F9E bp2 SC1MST 1 bp3 SC1CKM 0 Select the transfer clock SC1MD1 0x03F9E bp4 SC1SBOS 1 bp5 SC1SBIS 1 bp6 SC1SBTS 1 bp7 SC1IOM 0 8 Set the interrupt level SC1TICR 0x03FF5 bp7 6 SC1LV1 0 10 9 Enable the interrupt SC1TICR 0x03FF5 bp1 SC1TIE 1 4 Set the PSODC2 P3ODCO flag of the P3ODC register P3DIR to 1 1 and select the Nch open drain at SBO1 SBT1 pins Then set the P1PLU2 P1PLUO flag of the register to 1 1 and select enable pull up resistance 5 Set the P3DIR2 P3DIRO flag of the Port 3 pin direction control register PSDIR to 1 1 and the PSDIRS flag to 0 to set P32 P30 to the output mode P31 to the input mode 6 Set the SC1LNG2 to 0 flag of the serial 1 mode register 0 SC1MDO to 111 to set the transfer bit count 8 bits Set the SC1STE flag of the SC1MDO register to 0 to disable the start condition Set the SC1DIR flag of the SC1MDO register to 0 to set MSB as a transfer first bit Set the SC1CE1 flag of the SC1MDO register to 1 to set the reception data input edge falling and the transmission data output edge rising 7 Set the SC1CMD flag of the
167. SCOSBTS 1 bp7 SCOIOM 0 13 Set the interrupt level SCOTICR 0x03FF3 bp7 6 SCOLV1 0 10 14 Enable the interrupt SCOTICR 0x03FF3 bp1 SCOTIE 1 4 Set the POODC2 0 flag of POODC register to 1 1 to select the Nch open drain as SBOOA SBTOA pin Set POPLU2 0 flag of POPLU register to 1 1 to select pull up resistor 5 Set the PODIR2 PODIR3 flag of the Port 0 pin direction control register PODIR to 0 0 and the PODIRO flag to 1 to set P02 to the input mode 6 Set the SCOLNG2 to 0 flag of the serial 0 mode register SCOMDO to 111 to set the transfer bit count 8 bits 7 Set the SCOLNG2 to 0 flag of the serial 0 mode register SCOMDO to 111 to disable the start condition 8 Set the SCODIR flag of the SCOMDO register to 0 to set MSB as a transfer first bit 9 Set the SCOCE1 flag of the SCOMDO register to 1 to set the reception data input edge falling 10 Set the SCOCMD flag of the SCOMD1 register to 0 to select the synchronous serial 11 Set the SCOMST flag of the SCOMD1 register to 0 to select the clock slave external slave Set the SCOCKM flag to 0 to select not divided by 8 for the clock source 12 Set the SCOSBOS flag of the SCOMD1 register to 0 the SCOSBTS flag of the SCOSBIS register to 1 to set the SBIO pin to the serial data input as the SBOO pin general port the SBTO pin to the transfer clock input output Set the SCOIOM flag O to set the s
168. Serial Interface 2 Control Registers List Register Address Function Page SC2MDO Ox03F96 Serial interface 2 mode register 0 XIII 7 SC2MD1 0x03F97 Serial interface 2 mode register 1 XIII 8 SC2MD3 0x03F98 Serial interface 2 mode register 3 XIII 9 SC2STR 0x03F99 Serial interface 2 status register XIII 10 SC2TRB 0x03F9A Serial interface 2 transmission reception shift register XIII 6 TXBUF2 0x03F9B Serial interface 2 transmission data buffer XIII 6 SC2CTR OxOSF9C Serial interface 2 control register XIII 11 POODC OxOSF1C Port 0 N ch open drain control register 28 PODIR 0x03F30 Port 0 direction control register IV 28 POPLU 0x03F40 Port 0 pull up control register IV 28 SC2ICR 0x03FF6 Serial interface 2 interrupt control register III 33 SCCKSEL 0x03F8E Serial interface Clock Cycle Switching Register XIII 13 R W Readable Writable R Readable Control Registers XIII 5 13 Serial Interface 2 13 2 2 Data Buffer Register Serial interface 2 has a 8 bit serial data buffer register for transmission Serial Interface 2 Transmission Data Buffer TXBUF2 0x03F9B 7 6 5 4 3 2 1 0 TXBUF27 TXBUF26 TXBUF25 TXBUF24 TXBUF23 TXBUF22 TXBUF21 TXBUF20 Access X 13 2 3 Data Register Serial interface 2 has a 8 bit serial data register Serial Interface 2 Transmission Reception Shift Register SC2TRB 0x03F9A 7
169. Set MN101E SERIES INSTRUCTION SET Group Mnemonic I Operation Flag Machine Code Notes VE NFICE ZF Size peat Ex 1 2 3 4 5 6 7 8 9 10 11 Data Move Instructions MOV MOV Dn Dm DnDm 211 1010 DnDm MOV imm8 Dm imm8 Dm 4 2 1010DmDm lt 8 gt MOV Dn PSW Dn PSW eee o 3 3 0010 1001 01Dn MOV PSW Dm PSW gt Dm 3 2 0010 0001 01Dm MOV An Di 8 gt 21 2 0100 1ADm d8 An Dm 8 98 4 2 0110 1ADm lt 08 gt MOV d16 An Dm mem8 d16 An Dm 7 4 0010 0110 1 lt d16 gt d4 SP Dm mem8 d4 SP Dm 3 2 0110 01Dm lt d4 gt 2 MOV d8 SP Dm mem8 d8 SP Dm 5473 0010 0110 01Dm lt d8 gt MOV d16 SP Dm 8 816 5 eee x 0010 0110 00Dm 46 gt MOV i08 Di mem8 IOTOP io8 Dm 4 2 0110 00Dm io8 gt MOV aa Dm mem8 abs8 gt Dm 4 2 0100 01Dm abs 8 MOV abs12 Dm mem8 abs12 5Dm 5 2 0100 00Dm abs 12 gt MOV abs16 Dm mem8 abs16 5 Dm 7 4 0010 1100 00Dm abs 16 gt MOV Dn Am 21 2 0101 1aDn MOV Dn d8 Am Dn mem8 d8 Am 4 2 0111 1aDn lt 08 gt
170. Timer 4 Simple pulse width External interrupt 2 P22 External interrupt 3 P23 External interrupt 4 P24 measurement enable pin IRQ2A PDO IRQ2B IRQ3A PD1 IRQ3B IRQ4 Count Timing of Simple Pulse Width Measurement Timers 0 2 and 4 Count clock source External interrupt i IRQ n 2 2 i TMnEN flag Compare register counter Figure 5 10 1 Count Timing of Simple Pulse Width Measurement Timers 0 2 and 4 When the input signal of the external interrupt pin for simple pulse width measurement is L at TMnEN flag operation is 1 the timer counts up Simple Pulse Width Measurement 49 5 8 bit Timers 5 10 2 Setup Example Setup Example of Simple Width Measurement by 8 bit Timer Timers 0 2 and 4 The pulse width of L period of the external interrupt 2 IRQ2 input signal is measured by the timer 0 The clock source of the timer 0 is selected to fs 2 A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 Set the pulse width measurement operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 1 3 Select the count clock source TMOMD 0x03F54 bp2 0 TMOCK2 0 001 4 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 0 TMOBAS 1 5 Set the compare register TMOOC 0x03F52 0x FF 6
171. Timer 7 Count clock fs EUN AR o TM7EN flag Compare register Binary 40111 ovtaportajor ra 5558555655575558 N counter External interrupr m input signal Capture trigger synchronous to fs Capture 0000 0111 0114 5555 5558 register Figure 6 9 1 Capture Count Timing as Both Edges of External Interrupt Signal is selected as Trigger Timer 7 T A capture trigger is generated at the both edges of the external interrupt m input signal In synchronized with this capture trigger the value of binary counter is loaded to the input capture register The value loaded to the capture register is depending on the value of the binary counter at the falling edge of the capture trigger When the speci fied edge is selected as the capture trigger source the capture trigger is generated only at that edge The other count timing is the same as the count timing of the timer operation 16 bit Timer Capture VI 39 6 16 bit Timer P20 P21 it is not possible to measure the precision width which can measure continuously 1 When caputer trigger is generated at the both edges of the external interrupt input pin between H and L working with the automatic transfer controller ATC1 When the binary counter is used as a free counter which counts 0x0000 to 0xFFFF set the compare register 1 to 0xFFFF or set the TM7BCR flag of
172. Timing of High Precision PWM Output at Normal 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI 31 6 16 bit Timer PWM source waveform A shows H until the binary counter reaches the compare register from 0x0000 e B shows L after the TM7OC2 compare match the binary counter then counts up until the binary counter reaches the TM7OC1 compare register is cleared C shows H again when the binary counter is cleared Count Timing of High Precision PWM Output When the compare register 2 is 0x0000 Timer 7 Here is the count timing as the compare register 2 is set to 0x0000 Count clock TM7EN flag Compare register 1 Compare og 0000 register 2 Hid 1 dias 1 counter TM71O output PWM output L Figure 6 7 2 Count Timing of High Precision PWM Output When the compare register 2 is 0x0000 When the TM7EN flag is stopped at 0 the PWM output shows 32 16 bit High Precision PWM Output Cycle Duty can be changed consecutively 6 16 bit Timer Count Timing of High Precision PWM Output At the compare register 2 the compere register 1 1 Timer 7 Count timng Compare register 2 2 Compare register 1 1 is shown below Count clock TM7EN flag Compare register 1 Compare register 2 pinay 0000 0001 0000 0001
173. V 8 3 2 2 Timer Prescaler V 10 5 2 3 Programmable Timer Registers a en trennen V 14 5 2 4 Timer Mode Registers n eie esee V 17 Contents 5 5 3 PresCalep uu a ERR NIRE US V 25 5 3 iet od c eoe tre V 25 5 3 2 Setup Example ao n Shu emen emo peres V 26 5 4 8 bit Timer Count amma pO TE e dpi dedi pres 27 94 1 8 bit Timer Operation H ha tete tite cete V 27 2 d2 Setup Exarniple oiii hee ee teo gei e d tie festes V 30 5 2 o bit Event Count oer e Ut e tec e ir eie eee V 32 Sea sl Operation RERO EE UR nitet deis V 32 23 5 2 Setup Exa niple rei tetendit ii en tete ipte e ie eh cete vies V 35 5 6 8 bit Timer Pulse Outputs eem obere te ERE V 37 5 6 1 Operation iie pere Dro etc n ODER DH CHE RE V 37 5 62 Setup Example noU RR ege eie RT EE QE V 38 5 7 8 bit PWM e m E ees ee RI Ne Ebene ee ues V 40 5 7 T Operation sss oaths sects atte e e PERDER IPOD d V 40 252 Setup Example esee ROI RH Ue V 43 9 8 Synchronous Output eoe tei een ette eee tiere eet terne t e bene eee V 45 9 6 1 V 45 5 8 2 Setup sonet eec ere P
174. Vss2 63 Ves Vss2 and 53 Vss3 a 10 17 Vpp2 89 Vpp3 OSC1 13 Input Clock input pins Connect these oscillation pins to ceramic or crystal ocsillators for OSC2 12 Output Clock output pins high frequency clock operation If the clock is an external input connect it to OSC1 and leave OSC2 open The chip will not operate with an external clock when using either the STOP or SLOW modes XI 15 Input Clock input pins Connect these oscillation pins to crystal oscillators for low fre XO 16 Output Clock output pins quency clock operation If the clock is an external input connect it to XI and leave XO open the chip will not operate with an external clock when using the STOP mode If these pins are not used connect XI to Vss and leave XO open NRST 19 Input P27 Reset pins This pin resets the chip when power is turned on is allocated as Active low P27 and contains an internal pull up resistor Type 100 kQ Setting this pin low initialize the internal state of the device Thereafter setting the input to high releases the reset The hardware waits for the system clock to stabilize then processes the reset interrupt Also if 0 is written to P27 and the reset is initiated by software a low level will be output The output has an n channel open drain configuration If a capacitor is to be inserted between NRST and Vss it is recommended that a discharge diode be placed between NRST and Vpp 4 yo SBOOA TXDOA p
175. Wait Time At recovering from STOP mode the bit 3 2 DLYS1 DLYSO of the oscillation stabilization wait time Chapter 2 CPU Basics control register can be set to select the oscillation stabilization wait time from 214 210 26 22x system clock The DLYCTR register is also used for controlling of buzzer functions At releasing from reset the oscillation stabilization wait time is fixed to determined by the CPU mode control register CPUM Table 2 7 2 Oscillation Stabilization Wait Time 214 x system clock System clock is DLYS1 DLYS0 Oscillation stabilization wait time 0 0 214 yx System clock 0 1 210 x System clock 1 0 26 x System clock 1 1 1 2 x System clock 1 Do not use in high speed operation NORMAL mode Use in low speed operation SLOW mode Reset Il 57 2 CPU Basics II 58 Reset Chapter 3 Interrupts Chapter 3 Interrupts III 2 3 1 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corre sponding interrupt service routine from an interrupt vector table reset non maskable interrupts NMI 20 maskable peripheral interrupts and 6 external interrupts For interrupts other than reset the interrupts processing sequence consists of interrupt request interrupt accep tance and hardware processing After the interrupt is accepted the program counter PC and processor st
176. XI 10 Control Registers 7 Serial interface 0 Status Register SC0STR 0x03F93 6 5 4 3 2 1 Chapter 11 Serial interface 0 0 SCOTBSY SCORBSY SCOTEMP SCOREMP SCOFEF SCOPEK SCOORE SCOERE 0 0 0 0 0 0 0 0 R SCOTBSY R R R R Description Serial bus status 0 Other use 1 Serial transmission in progress R R R SCORBSY Serial bus status 0 Other use 1 Serial reception in progress SCOTEMP Transfer buffer empty flag 0 Empty 1 Full SCOREMP Receive buffer empty flag 0 Empty 1 Full SCOFEF Framing error detection 0 No error 1 Error SCOPEK Parity error detection 0 No error 1 Error SCOORE Overrun error detection 0 No error 1 Error SCOERE Error monitor flag 0 No error 1 Error Control Registers XI 11 11 Serial interface 0 Serial I O Pin Switching Register SCSEL 0x03F4F bp 3 0 Flag SC3SEL SCOSEL Reset 0 0 Access Description 7 4 Serial 3 pin switching 3 SC3SEL 0 P93 P95 1 P33 P35 2 1 Serial 0 pin switching 0 SCOSEL 0 P90 P92 1 00 02 XI 12 Control Registers 11 Serial interface 0 11 3 Operation Serial interface 0 can be used for both clock synchronous and full duplex UART 11 3 1 Clock Synchronous Serial Interface
177. XVIII 31 18 Automatic Transfer Controller 18 3 18 Transfer Mode D Eu s ov rr In transfer mode D ATC1 automatically transfers one byte of data from any memory space to any other memory space everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 00000 to FFFFF 2 a ATMAPO m 1 2 2 1 1 ATMAPO 2 1 2 1 Figure 18 3 15 Transfer Mode D Set the source address in 20 bit memory pointer 1 L and set the destination address 20 bit memory pointer 0 ATIMAPOH M L In transfer mode D the values in memory pointers 0 and 1 increment everytime a byte length data transfer ends As a result the source and destination addresses for the next transfer are one address higher than those for the original transfer Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt ATC 1IIRQ occurs and the automatic transfer ends XVIII 32 Operation 18 Automatic Transfer Controller 18 3 19 Transfer Mode E Ei Transfer mode E is a burst mode In this mode when is activated it automatically transfers the number of data bytes set in the transfer data counter A
178. added Added Not added Added Not added P4PLU P4PLU0 P4PLU P4PLU2 Operation XV 29 15 Serial interface 4 XV 30 B Pins Setup with 2 channels at transmission Table 15 3 10 shows the setup for synchronous serial interface pin with 2 channels SBO4 pin SBT4 pin at trans mission SBIA pin can be used as a port Table 15 3 10 Setup for Synchronous Serial Interface Pin with 2 channels at transmission Setup item Data output pin Serial unused pin Clock pin SBO4 pin SBI4 pin SBT4 pin Clock master Clock slave SC4MD1 SC4MST Port pin P40 P41 P42 Serial data input 584 selection SC4MD1 SC4IOM Function Serial data input 1 input Transfer clock input Transfer clock input output output SC4MD1 SC4SBOS SC4MD1 SC4SBIS SC4MD1 SC4SBIS Style Push pull Nch open Push pull Nch open Push pull Nch open drain drain drain P4ODC P4ODC0 P4ODC P4ODC2 Output mode Output mode Input mode P4DIR P4DIR0 P4DIR P4DIR2 Pull up setup Added Not added Added Not added Added Not added P4PLU P4PLU0 P4PLU P4PLU2 Operation B Pins Setup with 2 channels at reception Chapter 15 Serial interface 4 Table 15 3 11 shows the setup for synchronous serial interface pin with 2 channels 5804 pin SBT4 pin at reception SBIA pin can be used as a port Table 15 3 11 Setup for Synchronous Serial Interface Pin wi
179. after the data output holding period of the final bit can be set as Table 12 3 5 by the setting value of the SCIFDCI to 0 flag of the SC1MD3 register After released the reset despite of the setting value of the SCIFDCI to 0 flag output before the serial transfer is H In the case of the enabled start condition at SCISTE flag 1 is output despite of the setting value of the SCIFDCI to 0 Table 12 3 5 SBO1 Output after the Data Output Holding Period of the Last Bit without start condition SBO output after the data SC1FDC1 flag SC1FDCO flag output holding period of the last bit 0 0 1 High output fix 1 0 Last data holding 0 1 O Low output fix 1 1 Reserved Operation XII 19 12 Serial interface 1 Other Control Flag Setup Table 12 3 6 shows flags that are not used at clock synchronous communication So they are not needed to set or monitor Table 12 3 6 Other Control Flag Register Flag Detail SC1MD2 SC1BRKE Break status transmission control SC1BRKF Break status reception monitor SC1NPE Parity enable SC1PM1 to 0 Added mode specification SC1FM1 to 0 Frame mode specification SC1STR SC1PEK Parity error detection SC1FEF Frame error detection XII 20 Operation 12 Serial interface 1 B Transmission Timing At master At slave Tmax 2 5T T 2 m gt T T Clock SBT
180. and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 9 pull up resistor control register POPLU Set the control flag of the port 9 pull up resistor control register POPLU to 1 to add pull up resistor P90 P92 P93 and P95 can select the Nch open drain output by each bit by the port 9 Nch open drain control reg ister POODC The port 9 Nch open drain control register P9ODC is set to 1 for the Nch open drain output and 0 for the push pull output Special Function Pin Setup P90 is used as output pin of the serial 0 transmission data or the UART 0 transmission data as well When the SCOSBOS flag of the serial interface 0 mode register 1 SCOMD1 is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 9 Nch open drain control register P9ODC P91 is used as input pin of the serial 0 reception data or the UART 0 reception data as well P92 is used as I O pin of the serial 0 clock as well When the SCOSBTS flag of the serial interface 0 mode regis ter 1 SCOMDI is set to 1 it is output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the port 9 Nch open drain control register P9ODC Also serial 0 I O pin can be selected by setting of serial I O pin switching control register SCSEL When SCOSEL flag of serial I O
181. and a new trigger factor occurs the burst transfer restarts from the point at which it stopped 1 When burst transfer stop is enabled do not select external interrupt 0 for ATC1trigger factor Operation XVIII 33 18 Automatic Transfer Controller 18 3 20 Transfer Mode F E u sawas rr Transfer mode F is a burst mode In this mode when 1 is activated it automatically transfers the number of data bytes set in the transfer data counter in one continuous operation Memory pointer O Memory pointer 1 00000 to FFFFF 00000 to FFFFF Gy S OE 2 ATMAPO SEI 1 2 5 2 1 4 4 ATMAP1 1 4 2 7 ATMAP1 2 n ATMAPO 3 1 3 2 Figure 18 3 17 Transfer Mode F Set the source address in 20 bit memory pointer 1 ATIMAPIH M L and set the destination address in 20 bit memory pointer 0 ATIMAPOH M L Once is activated memory pointers 0 and 1 increment everytime byte length data transfer ends For burst transfers set the number of data bytes to be transferred in the transfer data counter ATI TRC Up to 255 transfers can be set Once the burst transfer starts the counter decrements everytime ATC1 transfers one byte of data When it reaches 0x00 an interrupt occurs and the burst transfer ends You can shut down ATC1 dur
182. any memory space is the destination address When the first data byte transfer ends the address in memory pointer 0 increments by one In the second data byte transfer the incremented address in memory pointer 0 becomes the source address and the I O space address 0 03 00 in memory pointer 1 becomes the destination address The address in memory pointer 0 remains unchanged after the second data byte transfer ends Set an even I O address in lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH ATIMAPIM Always set an even I O address in memory pointer 1 In this double transfer of a data byte from and to the I O space ATC1 targets the even I O address set in memory pointer 1 and the consecutive odd address In this mode the first data byte transfer accesses an even I O address and the second data byte transfer accesses an odd I O address Operation XVIII 27 18 Automatic Transfer Controller Transfer mode 9 can be used to support continuous transmission reception for serial inter face 0 1 and 2 Set the memory pointer 1 to point to the serial reception buffer RXBUF0 RXBUF1 and select serial interrupts as the ATC1 trigger factor In this way everytime a serial communication ends the MCU continuously reads the reception data first data byte transfer then writes the transmission data to the transmission buff
183. as the first transfer bit 8 Set the SC2CE1 flag of the SC2MDO register to 1 to set the reception data input edge to falling 9 Set the SC2CMD flag of the SC2CTR register to 0 to select synchronous serial interface 10 Set the SC2MST flag of the SC2MD1 register to 0 to select clock slave external clock 11 Set the SC2SBOS SC2SBIS SC2SBTS flags of the SC2MD1 register to 1 to set the SBO2 pin to general port the SBI2 pin to serial data input and the SBT2 pin to transfer clock I O Set the SC2IOM flag to 0 to set serial data input from the SBI2 pin 12 Set the interrupt level to level 2 by the SC2LV1 0 flags of the serial 2 interrupt control register SC2ICR 13 Enable the interrupt by setting 1 to the SC2IE flag of the SC2ICR register If the interrupt request flag SC2IR of the SC2ICR register is already set clear SC2IR before the interrupt is enabled Chapter 3 3 1 4 Interrupt Flag Setup 14 Set dummy data to the serial transmission data buffer TXBUF2 15 Set the STOP flag of the CPUM register to 1 for transition to STOP mode 16 Set the transfer clock to SBT2 pin and transfer data to SBI2 pin Operation 13 Serial Interface 2 Setup Procedure Description 17 Return from STANDBY mode stabilization wait time 17 Serial 2 interrupt is generated at the same time with reception of 8 bits data and then CPU returns from STOP mod
184. baud rate timer Square wave output timer pulse output Event count Serial transfer clock 16 bit cascade connection function connected to timer 2 Remote control carrier output Clock source fosc fosc 4 fosc 16 fosc 64 fosc 128 fs 2 fs 8 fx external clock Timer 4 8 bit timer also serves as UART baud rate timer Square wave output timer pulse output PWM output Event count Simple pulse with measurement Serial transfer clock Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock Timer 5 8 bit timer also serves as UART baud rate timer Square wave output timer pulse output PWM output Event count Serial transfer clock 16 bit cascade connection function connected to timer 4 Clock source fosc fosc 4 fosc 16 fosc 64 fosc 128 fs 2 fs 8 fx external clock Timer 6 8 bit free running timer Time base timer 8 bit free running timer Clock source fosc fosc 2 fosc 213 fs fx 212 fx 213 Time base timer Interrupt generation cycle fosc 2 fosc 29 fosc 2 fosc 219 fosc 2 3 fosc 219 fx 2 fx 28 fx 29 fx 210 fx 213 fx 215 Timer 7 16 bit timer for general use Square wave output Timer pulse output Event count High precision PWM output Cycle Duty can be changed constantly Timer synchronous output Input capture function Both edges can be operated Real time output control at tthe falling edge of external interrupt IRQ0 the value of PWM outpu
185. be used as a nor KEY4 51 P64 A12 mal I O pins KEY5 52 P65 A13 KEY6 53 P66 A14 KEY7 54 P67 A15 LEDO 64 VO P80 DO LED drive pins Large current output pins LED1 65 P81 D1 When not used for LED output these pins can be used as a nor LED2 66 P82 D2 mal I O pins LED3 67 P83 D3 LED4 68 P84 D4 LED5 69 P85 D5 LED6 70 P86 D6 LED7 71 87 7 MMOD 11 Input Memory mode These pins sets memory expansion mode switch pin When used in processor mode input H and input L in other use Do not change the setup after reset release MOD1 18 Input Set always to H Pin Description 1 17 1 Overview Name NO Other Function Function Description NWE 61 Output P61 SDO6 Write enable pins Memory control signal used when the memory area is expanded Active low to the external NRE 60 Output P75 005 Read enable pins NWE is the strove signal output for the write operation of the Active low external memory and NRE is the strove signal output for the read operation of the external memory NCS 59 P74 004 Tip select pins NCS is the tip selection signal outputs the external memory at the Active low access NDK 62 Input P77 007 Data aknowledge NDK is the aknowledge signal that indicates end of access to the pins Active low external memory SYSCLK 88 Output PD6 System clock pin SYSCLK is the internal system clock
186. bp18 P73 SDOS3 A18 in out P7DIR3 P7PLU3 SDOS Timer synchrpnous output 19 Address output bp19 P74 SDO4 NCS in out P7DIR4 P7PLU4 5004 Timer synchrpnous output 4 NCS Chip selection signal P75 005 in out P7DIR5 P7PLU5 SDO5 Timer synchrpnous output 5 NRE Read enable signal P76 SDO6 NWE in out P7DIRe P7PLU6 SDO6 Timer synchrpnous output 6 NWE Write enable signal P77 SDO7 NDK in out P7DIR7 P7PLU7 5007 Timer synchrpnous output 7 NDK Data acknowledge signal P80 LEDO DO in out P8DIRO P8PLUO LEDO LED driver pin 0 DO Data bp0 P81 LED1 D1 in out P8DIR1 P8PLU1 LED1 LED driver pin 1 D1 Data I O bp1 P82 LED2 D2 in out P8DIR2 P8PLU2 LED2 LED driver pin 2 D2 Data I O bp2 P83 LED3 D3 in out P8DIRS P8PLU3 LED3 LED driver pin D3 Data I O bp3 P84 LED4 D4 in out P8DIR4 P8PLU4 LED4 LED driver pin 4 D4 Data I O bp4 P85 LED5 D5 in out P8DIR5 X P8PLUS LED5 LED driver pin 5 D5 Data I O bp5 P86 LED6 D6 in out P8DIR6 P8PLU6 LED6 LED driver pin 6 D6 Data I O bp6 P87 LED7 D7 in out P8DIR7 P8PLU7 LED7 LED driver pin 7 D7 Data bp7 P90 SBOOB TXDOB_ in out P9DIRO P9PLUO 58008 Serial 0 transmission data TXDOB UART 0 transmission data output output P91 SBIOB RXDOB_ in out P9DIR1 P9PLU1 SBIOB Serial 0 reception data input _ RXDOB UART 0 reception data input P92 SBTOB in out P9DIR2 P9PLU2 SBTOB Serial 0 clock input output P93 SBOSB SDASB in out P9DIR3 X SBOSB Serial 3
187. bp5 SCOSBIS 1 bp6 SCOSBTS 1 bp7 SCOIOM 0 9 Set the interrupt level SCOTICR 0x03FF3 bp7 6 SCOLV1 0 10 4 SCOSEL flag of SCSEL register to O to set I O used pin to A portO b Set the POODC2 0 flag of POODC register to 1 1 to select the Nch open drain as SBOOA SBTOA pin Set POPLU2 0 flag of POPLU register to 1 1 to select pull up resistor 6 Set the PODIR2 PODIRO flag of the Port 0 pin direction control register PODIR to 1 1 and the PODIRS flag to to set PO2 POO to the output mode P01 to the input mode 7 Set the SCOLNG2 to 0 flag of the serial 0 mode register 0 SCOMDO to 111 to set the transfer bit count 8 bits Set the SCOSTE flag of the SCOMDO register to 0 to disable the start condition Set the SCODIR flag of the SCOMDO register to 0 to set MSB as a transfer first bit Set the SCOCE1 flag of the SCOMDO register to 1 to set the reception data input edge falling and the transmission data output edge rising 8 Set the SCOCMD flag of the SCOMD1 register to 0 to select the synchronous serial Set the SCOMST flag of the SCOMD1 register to 0 to select the clock master internal clock Set the SCOCKM flag to 0 to select not divided by 8 for the clock source Set the SCOSBOS SCOSBIS SCOSBTS flag of the SCOMD register to 1 to set the SBOO pin to the serial data output the SBIO pin to the serial input SBTO pin to the transfer clock input out
188. buffer empty flag 0 Empty 1 Full XIV 10 Control Registers B Serial interface 3 Control Register SC3CTR 0x03FAA bp 7 6 5 4 3 2 1 Chapter 14 Serial Interface 3 0 Flag IICBSY IICSTC IICSTPC SCSTMD SC3REX SC3CMD SC3ACKS 5 At reset 0 0 0 0 0 0 0 0 Access R IICBSY Description Serial bus status in IIC communication 0 Other use 1 Serial transmission is in progress IICSTC Start condition 0 Disable start condition 1 Enable start condition IICSTPC Stop condition detection flag in IIC communication 0 undetected 1 detected SC3TMD Communication mode 0 NORMAL mode 1 High speed mode SC3REX Transmission reception mode selection 0 Transmission 1 Reception SC3CMD Synchronous IIC selection 0 Synchronous 1 SC3ACKS ACK bit enable 0 Enable 1 Disable SC3ACK0 ACK bit level selection 0 L level 1 H level Control Registers XIV 11 14 Serial Interface 3 1 1 is not writable 2 This is not writable when the emergency reset of communication is not cancelled 3 The written data is not readable before generation of the IIC communication XIV 12 Control Registers B Serial interface Clock Cycle Switching Register SCCKSEL bp 7 6 5 4 Chapter 14 Serial Interface 3
189. d7 BNC d7 BNS d7 BVC 07 BVS 47 NOT Dn ROR Dn 3 BD BGTd11 BHI d11 BLS d11 d11 BNS 411 BVC d11 5 411 ASR Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 SUBW DWn Am MOVW DWn Am ADDW DWn DWm ADDW 16 DWm ADDW 16 ADDW DWn Am CMPW DWn Am MOV d16 SP Dm MOV d8 SP Dm MOV d16 An Dm MOV Dn d16 SP MOV Dn d8 SP MOV Dn d16 Am MOVW DWn DWm NOPL n m CMPW DWn DWm ADDUW Dn Am EXT Dn DWm AND 8 PSW OR 8 PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC MOV abs16 Dm 8 MOVW abs16 Am MOVW abs16 DWm CBEQ 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d12 CBEQ 8 2658 7101 8 abs8 d7 d1 1 MOVW d16 SP Am MOVW d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 Am DIVU MOVW An d16 SP Instruction Map MOVW DWn d16 SP MOVW An d8 SP MOVW DWn d8 SP MOVW An Am ADDW 16 SP MULU Extension code b 0011 2nd nibble 3rd nibble 0 1 2 8 9 A B C D E F TBZ abs8 bp d11 TBNZ abs8 bp d7 TBNZ abs8 bp d11 CMP Dn Dm ADD Dn Dm TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 TBNZ io8 bp d11 BSET io8 bp BCLR io8 bp JMP ab
190. direction control register IV 108 TMSEL 0x03F3F R W Timer pin switching register V 23 Timer 5 5 0x03F61 R Timer 5 binary counter V 16 TM5OC OxO3F63 R W Timer 5 compare register V 15 TM5MD Ox03F65 R W Timer 5 mode register V 22 CK5MD Ox03F67 R W Timer 5 prescaler selection register V 13 TMBICR OxOSFED R W Timer 5 interrupt control register 31 P1OMD 0x03F2B R W Port 1 output mode register IV 49 P1DIR 0x03F31 R W Port 1 direction control register IV 50 PDOMD 0x03F1B R W Port D output control register IV 107 PDDIR 0x03F3D R W Port D direction control register IV 108 TMSEL 0x03F3F R W Timer pin switching register V 23 R W Readable Writable R Readable only Control Registers V 9 5 8 bit Timers 5 2 2 Timer Prescaler Registers s OT _ Timer prescaler selection register selects the count clock for 8 bit timer The register which selects prescaler output is consisted by the timer prescaler selection register CKnMD Timer 0 prescaler selection register CK0MD 0x03F56 2 1 0 TM0PSC1 TMOPSCO TMOBAS 0 0 0 Description Select the clock source 000 fosc 4 5 1 010 fosc 16 TMOPSCO 100 fosc 32 TMOBAS 110 fosc 64 X01 fs 2 X11 fs 4 V 10 Control Registers Timer 1 prescaler selection register CK1MD 0x03F57 2 1 Chapter 5 8 bit Timers 0 TM1PSC1 TM1PSCO TM1BAS 0 0 0
191. divided fs 2 8 MHz the setup value is set to fs 2 MHz 73 4 kHz 1 54 0x36 10 Set the TMOEN flag of the TMOMD register to 1 to start the timer O 11 Set the RMOEN flag of the RMCTR register to 1 to enable the remote control career output TMOBC starts the count up from 0x00 As The base cycle pulse that is set at the TMOOC is output from the timer 0 1 3 of the remote control career pulse signal is output If the RMOEN flag of the RMCTR register is set to 0 the output signal of the remote control career pulse is stopped Operations VIIL 9 8 Remote Control Functions VIII 10 Operations 9 Watchdog Timer 9 Watchdog Timer 2 9 1 Overview This LSI has a watchdog timer This timer is used to detect software processing errors It is controlled by the watchdog timer control register WDCTR And once an overflow of watchdog timer is generated a watchdog interrupt WDIRQ is generated If the watchdog interrupt is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware 9 1 1 Block Diagram Watchdog Timer Block Diagram NRST gt x STOP writeWDCTR Y HALT d R R R Pi 12 124 wes 1 22 s gt inter
192. external interrupt valid input switching control register LVLMD to 1 to specify the interrupt valid input level as the level interrupt H level 3 Set the EXLVL flag of the external interrupt valid input switching control register LVLMD to 1 to specify the interrupt valid input level as the level interrupt H level 4 Set the interrupt priority level in the IRQ2LV1 to 0 flag of the IRQ2ICR register The interrupt request flag of the IRQ2ICR register may be set so make sure to clear the interrupt request flag IRQ2IR 5 Set the IRQ2IE flag of the IRQ2ICR register to 1 enable the interrupt External interrupt 2 is generated at the H level of the input signal from P22 External Interrupts Interrupts III 63 Chapter 3 Interrupts 1 Set the external interrupt valid input level equal to the polarity of the interrupt valid edge External interrupt valid input level level Interrupt valid edge rising edge External interrupt valid input level L level Interrupt valid edge falling edge valid edge before the interrupt permission a The interrupt request flag can be set at switching the interrupt edge so specify the interrupt The external interrupt pin is recommended to be pull up in advance At the standby mode if the value that is set to the external interrupt valid specified flag and the external interrupt pin level are matched the interrupt is generated refer to figure
193. flag of the timer 6 mode register TM6MD 3 Select the selected clock x 1 21 as an interrupt generation cycle by the TM6IR2 to 0 flag of the TM6MD register 4 Write value to the time base timer clear control register TBCLR to initialize time base timer b Set the interrupt level by the TBLV1 to 0 flag of the time base interrupt control register TBICR If any interrupt request flag may be already set clear them Chapter 3 3 1 4 Interrupt Flag Setup 6 Set the TBIE flag of the TBICR register to 1 to enable the interrupt 7 Set the TBEN of the 6 register to 1 to start the time base timer When the selected interrupt generation cycle is passed the interrupt request flag of the time base interrupt con trol register TBICR is set to 1 Time Base Timer VII 17 7 Time Base Timer Free running Timer VII 18 Time Base Timer Chapter8 Remote Control Functions FE 8 Remote Control Functions 8 1 Overview Remote control career output functions can create the career wave for the remote control and output 8 1 1 Functions Table 8 1 1 shows the remote control career output functions Table 8 1 1 The remote control career output functions Remote control career output base timer Timer 0 selection Timer 3 Duty selection 1 2 1 3 Timer output Remote control career output enable factor RMOEN Remote control career o
194. i P9IN2 Port input data lt 1 lt Serial 0 clock input Serial 0 clock output SCOMD1 SCOSBTS Figure 4 11 3 P92 Block Diagram aw Reset P9ODC3 Nch open drain control Q wex Y Reset Pull up resistor control pFq gt WEK R Reset P9DIR3 direction control Q Wek 1290073 9 WEK R P93 Port output data snq lt Schmitt trigger input lt Port input data lt RINS Serial 3 IIC3 reception data input Serial 3 IIC3 transmission data output SC3MD1 SC3SBOS Figure 4 11 4 P93 Block Diagram IV 94 Port 9 Chapter 4 I O Ports P9PLUA Pull up resistor control t Rq gt Le WEK R Reset 5 direction control pfa P9DIR4 R Js 9 P94 Port output data E a P9OQUT4 a wok VR Schmitt trigger input Porti ort input data lt J R Serial 3 transmission data input Figure 4 11 5 P94 Block Diagram Reset R P9ODC5 Nch open drain control wex Y Pull up resistor control D I O direction control pfa PSDIR5 gt Le WEK R Port output data sng v O
195. in the IRQOLV1 to 0 IRQOICR 0x03FE2 flag of the IRQOICR register bp7 6 IRQOLV1 0 10 The interrupt request flag of the IRQOICR register may be set so make sure to clear the interrupt request flag IRQOIR Chapter 3 3 1 4 Interrupt flag setup 3 Enable the interrupt 3 Set the IRQOIE flag of the IRQOICR register to 1 IRQOICR 0x03FE2 enable the interrupt bp1 IRQOIE 1 External interrupt 0 is generated at the rising edge of the input signal from P20 The interrupt request flag can be set at switching the interrupt edge so specify the interrupt Y valid edge before the interrupt permission The external interrupt pin is recommended to be pull up in advance At the standby mode if the value that is set to the external interrupt valid specified flag and the external interrupt pin level are matched the interrupt is generated refer to figure 3 3 1 to 3 3 6 So when flag is 0 and pin is 0 or flag is 1 and pin is 1 before standby interrupt is gener ated at the standby mode and CPU can be returned External Interrupts 3 3 5 Both Edges Interrupt Chapter 3 Both Edges Interrupt External interrupt 2 3 and 5 Both edges interrupt can generate interrupt at both the falling edge and the rising edge by the input signal from external input pins CPU also can be returned from standby mode the external interrupt pin level are matched the interrupt is generated refer to figure 3
196. input 41 Input high voltage 0 8 Vppi 42 Input low voltage 7 0 0 15 Vppi 43 Pull up resistor Rpu7 1 3 3 V Vin Vss1 30 100 350 kQ Electrical Characteristics 1 27 1 Overview 1 5 4 A D Converter Characteristics s 3 Ta 40 C to 85 C Vppi Vppo2 3 0 V to 3 6 V Vpp3 Vpp1 to 5 5 V Vssi Vss Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Non linearity error NLE 5 0 V Vssi 0 V 5 V 5 0 V LSB Differential non linearity REF as 3 error DNLE TAp 500 ns 3 4 Zero transition voltage 5 0 V Vssi 0 V 30 100 V 5 0 V mV Full scale transition volt REF 5 dde Tap 500 ns 4900 4970 6 500 ns 8 10 z A D conversion time 7 Tap 15 26 us 488 41 us 8 500 ns 1 0 9 0 Sampling time 9 15 26 us 30 52 274 68 10 Reference voltage VREF V 11 Analog input voltage Vssi VREF 12 Analog input leakage cur When channel is OFF 2 VapiN 0 Vto5V c Reference voltage When is OFF _ _ 20 input leakage current Vss3 Vngr lt iN 5 0 V 14 Ladder resistance 15 35 50 ss 0 V The values of 2 to 5 are guaranteed in the condition that Vpp3 Vier 5 0 V 28 Electrical Cha
197. interface 4 Transmission Data Buffer TXBUF4 0x03FB1 7 6 5 4 3 2 1 0 TXBUF47 TXBUF46 TXBUF45 TXBUF44 TXBUF43 TXBUF42 TXBUF41 TXBUF40 X X X X X X X X XV 6 Control Registers 15 2 3 Mode Registers B Serial interface 4 Mode Register 0 SC4MD0 0x03FAB bp 7 4 3 2 1 Chapter 15 Serial interface 4 0 Flag Reset SC4CE1 0 SC4DIR 0 SC4STE 0 SC4LNG2 1 SC4LNG1 1 SC4LNGO 1 Access bp Flag SC4CE1 Description Transmission data output edge 0 falling 1 rising Reception data input edge O rising 1 falling R W R W R W R W SC4DIR First bit to be transferred 0 MSB first 1 LSB first SC4STE SC4LNG2 SC4LNG1 SC4LNGO Start condition selection 0 Disable start condition 1 Enable start condition Transfer bit 000 1bit 001 2bit 010 3bit 011 4bit 100 5bit 101 6bit 110 7bit 111 8bit Control Registers XV 7 15 Serial interface 4 Serial interface 4 Mode Register 1 SC4MD1 0x03FAC 7 6 5 4 3 2 0 SC4CKM SC4MST SC4CMD SC4IOM 5 45 5 SC4SBIS SC4SBOS XV 8 0 0 0 0 0 0 0 SC4IOM Description Serial data input selection 0 Data input from 5 4 RXD4 1 Data input from SBO4 TXD4 SC4SBTS SBT4 pin function selection 0 Port 1 Transfer clock I O
198. interrupt and reception complete interrupt are available Maximum transfer clock of each serial interface 5 MHz LED driver LED large current driver ports 8 ports 1 8 Hardware Functions 1 Overview Port Package ports I F port for 5 V I O Usable as A D input ports I F port for 3 V I O LED large current driver ports Usable as D A output Special function pins Analog reference voltage input pin Operation mode input pin Reset input pin Power pin Internal power pin External power pin Oscillator pins 1 Voltage for internal power pin 3 0 V to 3 6 V 2 Voltage for external power pin 3 0 V to 5 5 V 100 pinQFP 18 mm square 0 65 mm pitch 34 ports 8 ports 50 ports 8 ports push pull configuration 1 port 16 pins 3 pins 2 pins 1 pin 8 pins pins 1 3pins 2 4 pins Hardware Functions 1 Overview 1 3 Pin Description 1 3 1 Pin configuration Wao cc XC ECC D IE n m C E X MEE l I l m I I lt o m 5 S n S NGO 00828858 222255552555 S I gt 5 gt gt gt 4 44 1 q s os Sus e s 00 CO CO CO CO Qaagdadaanannasnaaoaonaaaanaand l I l l I On CO LO e
199. is cleared 0 And during continuous communication the SCOTBSY flag is always set If the transmission buffer empty flag SCOTEMP is cleared to 0 as the communication complete interrupt SCOTIRQ is generated S COTBSY is cleared to 0 If the SCOSBOS flag is set to 0 during communication the SCOTBSy flag is cleared to 0 B Emergency Reset This serial interface contains emergency reset for abnormal operation For emergency reset the SCOSBOS flag and the SCOSBIOS flag of SCOMDI register should be set to 0 SBOO pin port input data 1 input At emergency reset the status register the SCOBRKF flag of the SCOMD2 register all flags of the SCOSTR reg ister are initialized as they are set at reset but the control register holds the set value Last Bit of Transfer Data Table 11 3 4 shows the data output holding period of the last bit at transmission and the minimum data input period of the last bit at reception The internal clock should be set up at slave to keep the data hold time at recep tion Table 11 3 4 Last Bit Data Length of Transfer Data The last bit data holding period at transmission The last data input period at reception At master 1 bit data length 1 bit data length Minimum At slave 1 bit data length of external clock x 1 2 internal clock cycle x 1 2 3 2 In the case of disabled start condition at SCOSTE flag 0 the SBOO output after the data output holding perio
200. is disabled XIII 26 Operation B Pins Setup 3 channels at transmission Chapter 13 Serial Interface 2 Table 13 3 6 shows the pins setup at synchronous serial interface transmission with 3 channels SBO2 pin SBI2 pin SBT2 pin Table 13 3 6 Synchronous Serial Interface Pins Setup 3 channels at transmission Item Data output pin Data input pin Clock pin 5802 pin SBI2 pin SBT2 pin Clock master Clock slave Pin 4 5 Serial data input SBI2 selection SC2MD1 SC2IOM Function Serial data output 1 input Transfer clock I O Transfer clock I O SC2MD1 SC2SBOS SC2MD1 SC2SBIS SC2MD1 SC2SBTS Type Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain POODC POODC3 POODC POODC5 Output mode Output mode Input mode PODIR PODIR3 PODIR PODIR5 Pull up added not added added not added added not added POPLU POPLUS POPLU POPLUS Pins Setup 3 channels at reception Table 13 3 7 shows the pins setup at synchronous serial interface reception with 3 channels 5802 pin 5812 pin SBT2 pin Table 13 3 7 Synchronous Serial Interface Pins Setup 3 channels at reception Item Data output pin Data input pin Clock I O pin 5802 pin SBI2 pin SBT2 pin Clock master Clock slave Pin P04 P05 Serial data input SBI2 sele
201. mode SC3REX 0 gt 1 Set data to TXBUF3 4 Receive ACK bit 5 Interrupt Communication ends clear the IICBSY flag 6 Generates stop condition Operation XIV 45 Chapter 14 Serial Interface 3 B Pin Setup 2 channels at transmission Table 14 3 15 shows the pins setup in IIC serial interface transmission with 2 channels SDA3 pin SCL3 pin Table 14 3 15 Pin Setup 2 channels at transmission Item Data pin Clock I O pin SDA3A pin SDA3B pin SCL3A pin SCL3B pin Clock master SC3MD1 SC3MS Pin P33 P93 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SDA3 SCL3 pins SBI3 SDA3 pin connection SC3MD1 SC3IOM Function Serial data output Transfer clock output SC3MD1 SC3SBOS SC3MD1 SC3SBTS Serial data input SC3MD1 SC3SBIS Type N ch open drain N ch open drain P30DC P30DC3 P30DC P30DCS5 P9ODC P9ODC5 output mode output mode P3DIR P3DIR3 P DIR P9DIR3 P3DIR P3DIR5 P DIR P9DIR5 Pull up selection added added P3PLU P3PLUS P9PLU P9PLU3 P3PLU P3PLU5 P9PLU P9PLUS5 XIV 46 Operation B Pin Setup 2 channels at reception Chapter 14 Serial Interface 3 Table 14 3 16 shows the pins setup in IIC serial interface reception with 2 channels SDA3 pin SCL3 pin Table 14 3 16 Pin Setup 2 channels at reception
202. modes automatically P55 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically P56 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically P57 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically IV 48 Port 5 Chapter 4 I O Ports 4 7 2 Registers The following Table shows registers that control the Port 5 Table 4 7 1 Port 5control register Registers Address R W Function Page P5OUT 0x03F15 R W Port 5 Output Register IV 49 R 0x03F25 0x03F35 R W Port 5 Direction Control Register 0x03F45 RAN Port 5 Pull up Resistor Control Register Port 5 Input Register R W Readable Writable Port 5 Output Register PBOUT 0xOSF15 LEEREN CENE Flag P5OUT7 P5OUT6 P5OUT5 P5OUT4 P5OUT3 P5OUT2 P5OUT1 P5OUTO At reset x x x x x x x x bp Flag Description P5OUT7 P5OUT6 P5OUT5 P5OUT4 Output data 0 Output L VSS level 1 Output H VDD level P5OUT3 P5OUT2 P5OUT1 P5OUTO O S G OQ O Port 5 IV 49 4 I O Ports Port 5 Input Register P5IN 0x03F25 bp Flag Description 7 P5IN7 6
203. moved out At the standby mode Only slave reception is available Continuous operation Internal clock 1 8 dividing O Only 1 8 dividing is available Overview 15 Serial interface 4 Clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 External clock Timer 2 output Timer 5 output fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 2 output Timer 5 output Maximum transfer rate 5 0 MHz 300 kbps fosc Machine clock High speed oscillation fs System clock a Set the transfer rate slower than system clock fs Overview 3 15 Serial interface 4 15 1 2 Block Diagram B Serial interface 4 Block Diagram Z L Z HAJVOS L39r9S WOIFOS 0 379 E 5195795 LWdrOS 3 5195705 0 479 HIQvos Sogsros 3dNrOS 31SvOS WNXOvOS 5 415 795 ndino
204. of the data of the received data buffer RXBUF1 overrun error is generated and the SCIORE flag of the SCISTR register is set to 1 At the same time the error monitor flag SC1ERE is set to indicate that error is occurred on reception The SCIERE flag is not cleared till the next communication complete interrupt SC1TIRQ is generated after loading data of the RXBUFI SCIERE is cleared as SCIORE flag is cleared These error flags have no effect on communication operation Reception BUSY Flag If the data is set to the TXBUF1 or recognized the start condition when the SCISBIS flag of SCIMDI register is set to serial data input the BUSY flag SCIRBSY of the SCISTR register is set to 1 And on the genera tion of the communication complete interrupt SCITIRQ the flag is cleared to 0 And during continuous com munication the SCIRBSY flag is always set If the transmission buffer empty flag SCITEMP is cleared to 0 as the communication complete interrupt SC1TIRQ is generated SCIRBSY is cleared to 0 If the SCISBIS flag is set to 0 during communication the SCIRBSY flag is cleared to 0 Operation 12 Serial interface 1 B Transmission BUSY Flag Data is set to the TXBUFI or recognized the start condition when the SCISBOS flag of the SCIMDI register is set to serial data output if the SCISBOS flag of the SCIMDI register is 1 SCITBSY flag of the SCISTR register is set And on the generation of the communicatio
205. overflow cycle set value of compare register 1 x timer clock cycle therefore set value of compare register timer clock frequency baud rate x 2 x 8 1 For example if baud rate should be 300 bps at timer clock source fs 4 fosc 8 MHz fs fosc 2 set value should be as follows Set value of compare register 8 x 106 2 4 300 2 8 1 207 Timer clock source and the set value of timer compare register at the standard rate are shown in the following page a Transfer rate should be selected under 300 kbps Operation XII 45 12 Serial interface 1 Transfer Speed bit s fosc Clock source 300 960 1200 2400 4800 MHz Timer Set Value Set Value 25 SetValue set Value mi Set Value me 4 00 fosc 207 1202 103 2404 51 4808 1050 4 207 300 64 962 51 1202 25 2404 12 4808 1050 16 51 300 12 1202 fosc 32 25 300 fosc 64 12 300 15 2 207 300 64 962 51 1202 25 2404 12 4808 15 4 104 297 25 1202 12 2404 4 19 fosc 217 1201 108 2403 54 4761 fosc 4 217 300 67 963 fosc 16 16 963 6 2338 fosc 32 fosc 64 fs 2 217 300 67 963 fs 4 108 300 33 963 13 2338 8 00 fosc 207 2404 108 4808 fosc 4 129 96
206. pin Table 13 3 15 Pin Setup 2 channels at transmission Item Data pin Clock output pin SDA pin SCL2 pin Pin 5 SDA2 SCL2 pins SBI2 SBO2 pin connection gt SC2MD1 SC2IOM Function Serial data output Transfer clock output SC2MD1 SC2SBOS SC2MD1 SC2SBTS Serial data input SC2MD1 SC2SBIS Type N ch open drain N ch open drain POODC POODC3 POODC POODC5 output mode output mode PODIR PODIR3 PODIR PODIR5 Pull up added added POPLU POPLUS POPLU POPLUS5 44 Operation B Pin Setup 2 channels at reception Chapter 13 Serial Interface 2 Table 13 3 16 shows the pins setup in serial interface reception with 2 channels SDA2 pin SCL2 pin Table 13 3 16 Pin Setup 2 channels at reception Item Data pin Clock output pin SDA SCL2 pin Pin 5 SDA2 SCL2 pins SBI2 SBO2 pin connection gt SC2MD1 SC2IOM Function Port Transfer clock output SC2MD1 SC2SBOS SC2MD1 SC2SBTS Serial data input SC2MD1 SC2SBIS Type N ch open drain N ch open drain POODC POODC3 POODC POODC5 output mode output mode PODIR PODIR3 PODIR PODIR5 Pull up added added POPLU POPLUS POPLU POPLUS5 Operation 45 13 Serial Interface 2 13 3 4 Setup Example Master Transmission Setup Example Here is the setup example of the transmissio
207. pin Clock I O pin SBO3A pin SBISA pin SBT3A pin SBT3B pin SBO3B pin SBI3B pin Clock master Clock slave SC3MD1 SC3MST Pin P33 P93 P34 P94 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SBI3 SBO3 pin SBI3 SBO3 independent selection SC3MD1 SC3IOM Function Serial data output Serial data input Transfer clock I O Transfer clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBTS Type Push pull N ch Push pull N ch Push pull N ch open drain open drain open drain P30DC P30DC3 P30DC P30DC5 P ODC P9ODC5 P9ODC P9ODC3 Output mode Input mode Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR4 P3DIR P3DIR5 P9DIR P9DIR5 P9DIR P9DIR3 P9DIR P9DIR4 Pull up added not added added not added added not added P3PLU P3PLU3 PSPLU PSPLUS Operation XIV 29 14 Serial Interface 3 B Pins Setup 2 channels at transmission Table 14 3 9 shows the pins setup at synchronous serial interface transmission with 2 channels SBO3pin SBT3 pin The 5 pin is not used so that it can be used as a general port Table 14 3 9 Synchronous Serial Interface Pins Setup 2 channels at transmission XIV 30 Item Data output pin Data input pin Clock I O pin SBO3A pin pin SBT3A pin SBT3B SBOS3B pin SBI3B pin Clock master Clock slave SC3MD1 SC3MST
208. pins to input pins 2 Set the PePLUS to 0 flag of the port 6 pull up resis tor control register PAPLU to 1111 to add the pull up resistors to P60 to P63 pins 3 Set the KEYT3SEL flag of the key interrupt control register KEYT3_1IMD to 1 to enable the port 6 key interrupt at the external interrupt 4 4 Set the KEYT3_1EN1 to 0 of the key interrupt con trol register KEYT3_1IMD to 11 to set P60 to P63 pins to key input pins 5 Set the interrupt level by the IRQ4LV1 to 0 flag of the IRQ4ICR register If the interrupt request flag has been already set clear the request flag IRQ4IR Chapter 3 3 1 4 Interrupt Flag Setup 6 Set the IRQ4IE flag of the IRQ4ICR register to 1 to enable the interrupt If there is at least one input signal from the P60 to P63 pins shows low level the external interrupt 4 is generated at the falling edge The key input should be setup before the interrupt is accepted External Interrupts Chapter 3 Interrupts III 66 3 3 8 Noise Filter Ra saa asr Noise Filter External interrupts 0 and 1 Noise filter reduce noise by sampling the input waveform from the external interrupt pins IRQO IRQ1 Its sam pling cycle can be selected from 4 types fs fs 28 fs 2 fs 210 Noise Remove Selection External interrupts 0 and 1 Noise remove function can be selected by setting the NFnEN flag of the noise filter control regis
209. port 4 Table 4 15 1 Synchronous Output Control Registers Register Address Function P7OUT 0x03F17 Port 7 output register P7DIR 0x03F37 Port 7 direction control register P7PLU 0x03F47 Port 7 pull up pull down resistor control register P7SYO 0x03F1F Port 7 synchronous output control register P7SEV 0x03F2F Port 7 synchronous output event selection register Synchronous Output IV 117 4 I O Ports 4 15 2 Operation a t n Tr ri Synchronous Output Setup The synchronous output control register P7S YO selects the synchronous output pin of the port 7 in each bit The synchronous output event is selected by the pin control register P7SEV When the external interrupt 2 IRQ2 is selected it is synchronized with the falling edge in spite of the edge spec ification of IRQ2ICR Synchronous Output Operation When the synchronous output control register P7S YO is set to disable the synchronous output I O port the port 7 is functioned as a general port When the port 7 is set to disable the synchronous output the same value to the port 7 output register P7OUT is always loaded to the synchronous output value stored register After the output mode is selected by the port 7 direction control register P7DIR if the synchronous output is enabled by the synchronous output control register P7S YO the value of the synchronous output value stored register is output from
210. preset register is loaded to the compare register at the next count clock And the interrupt request flag is set at the next count clock and the binary counter is cleared to 0x0000 to restart counting up E When the TM7EN flag is 1 the binary counter is stopped Operation VI 13 6 16 bit Timer VI 14 When the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock and the binary counter is cleared So set the compare register as the set value of the compare register the counts till the interrupt generation 1 When the timer 7 compare register 2 match interrupt is generated and the 7 1 compare match is selected as a binary counter clear source the set value of the compare register 2 should be smaller than the set value of the compare register 1 On the interrupt service routine clear the timer interrupt request flag before the timer is started When the binary counter is used as a free counter that counts 0x0000 to OxFFFF set OxFFFF to the compare register set the TM7BCR flag of the TM7MD2 register to Setup of 16 bit timer count clock should be done when the timer interrupt is disabled lt Operation 6 3 2 Setup Example Chapter 6 16 bit Timer Timer Operation Setup Example Timer 7 generates an interrupt constantly for timer function Fosc 2 fosc 20
211. register The transmission reception shift register SC3TRB is not operated by the ACK bit reception clock When the received ACK bit level is L the reception is normal at slave and the next data can be received If the level is H the reception maybe completed at slave so set the IICSTPC flag of the SC3CTR register to 0 to end com munication Data transmission Interrupt Figure 14 3 18 ACK Bit Reception Timing after Transmission of 8 Bit Data B Transmission of Confirming ACK Bit of Data Reception Selection of enable disable of ACK bit is same with at the transmission When ACK bit is enabled ACK bit and clock are output after data 1 to 8 bits is received When the reception is continued ACK bit outputs L And when the reception is finished it outputs The SC3ACKO of the SC3CTR register sets the output ACK bit level Data reception erio period Interrupt Figure 14 3 19 ACK Bit Transmission Timing after Reception of 8 Bit Data 40 Operation 14 Serial Interface 3 B Transfer Format There are two transfer format used on IIC bus are the addressing format that transmits receives data after 1 byte data address data that consists of slave address 7 bits and R W bit 1 bit is transferred after start condition and the free data format that transmits data right after the start condition The serial interface of this LSI supports 2 communication format
212. register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the fx input is selected as a clock source and the value of timer 6 binary counter is read out at operation an incorrect value could be read out To prevent this select a synchronous fs as the count clock source If the smaller value than the binary counter is set to the compare register at counting opera tion the binary counter continues counting till overflow VII 12 8 bit Free running Timer 7 Time Base Timer Free running Timer 7 3 2 Setup Example VV ls TO Timer Operation Setup Timer 6 Timer 6 generates interrupts constantly for timer function Interrupts are generated in every 250 dividing 25 us by selecting fs fosc 10 MHz at operation as clock source An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Enable the binary counter TM6MD 0x03F6A bp7 TM6CLRS 0 2 Disable the interrupt TM6ICR 0x03FEE bp1 TM6IE 0 3 Select the clock source TM6MD 0x03F6A bp3 1 TM6CK3 1 001 4 Set the interrupt generation cycle TM6OC 0x03F69 0xF9 5 Enable the interrupt request TM6MD 0x03F6A bp7 TM6CLRS 1 6 Set the interrupt level TM6ICR 0x03FEE bp7 6 TM6LV1 0 01 7 Enable th
213. source 2 Set the bp3 to 0 flag of the SC1MD3 register to 111 to SC1MD3 0x03FA0 select Timer 5 output as a clock source bp2 0 SC1PSC2 0 110 3 Control the pin style 3 Set the PSODCO flag of the register to 1 to P30DC 0x03F2C select Nch open drain for the TXD1 pin P3PLUO flag bp0 1 of the P3PLU register to 1 to add pull up register P3PLU 0x03F33 bp0 P3PLU0 1 4 Control the pin direction 4 Set the PSDIRO flag of the Port pin direction control P3DIR 0x03F43 register P3DIR 1 and the P3DIR3 flag to 0 to set bp1 0 P3DIR1 0 0 1 P30 to the output mode P31 to the input mode XII 50 Operation 12 Serial interface 1 Setup Procedure Description 5 Set the SC1MDO register Select the start condition SC1MDO 0xOSF9D bp3 SC1STE 1 Select the first bit to be transferred SC1MDO 0x0O3F9D bp4 SC1DIR 0 6 Set the SC1MD2 register Control the output data SC1MD2 0x03F9F bp0 SC1BRKE 0 Select the added parity bit SC1MD2 0x03F9F bp3 SC1NPE 0 bp5 4 SC1PM1 0 00 Specify the flame mode SC1MD2 0x03F9F bp7 6 SC1FM1 0 11 7 Set the SC1MD1 register Select the communication type SC1MD1 0x03F9E bp0 SC1CMD 1 Select the clock frequency SC1MD1 0x03F9E bp3 SC1CKM 1 bp2 SC1MST 1 Control the pin function SC1MD1 0x03F9E bp4 SC1SBOS 1 bp5 SC1SBIS 1 bp7 SC1IOM 0 8 Enable the interrupt SCARICR 0xOS3FFA
214. space for transition from SLOW to NORMAL NORMAL IDLE state mode a In transition from SLOW to NORMAL execute following program 1 or 2 Sample program for transition from SLOW to NORMAL mode is given below Program 2 MOV x38 D ADD 00 CPUM BNE 31 DO SUB 00 00 MOV DO CPUM Standby Function 47 2 CPU Basics Program 3 MOV x 05 DO A loop to keep approx 6 7ms with low frequency clock 32 kHz LOOP ADD 1 DO operation when changed to high frequency clock 20 MHz BNE LOOP SUB DO MOV x 30 DO MOV DO CPUM Set NORMAL mode MOV x 00 DO MOV DO CPUM 48 Standby Function Chapter 2 CPU Basics 2 5 4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY HALT STOP modes by specifying the new mode in the CPU mode control register CPUM Interrupts initiate the return to the former CPU operating mode Before initiating a transition to a STANDBY mode however the program must 1 Set the maskable interrupt enable flag MIE in the processor status word PSW to 0 to disable all maskable interrupts temporarily 2 Set the interrupt enable flags xxxIE in the interrupt control registers xxxICR to 1 or 0 to specify which interrupts do and do not initiate the return from the STANDBY mode Set MIE 1 to enable those maskable inter rupts NORMAL SLOW SLOW mode
215. the TM7MD2 to 0 Even if an event is generated before the value of the input capture register is read out the value of the input capture register can be rewritten clock So when the interrupt input singal is faster than the system clock cycle the external interrupt input edge may not be detected Also the capture function can not be used during STOP mode because the system clock is stopped a Capture trigger is generated by sampling the external interrupt input singal at the system In the initial state after releasing the reset the generation of trigger by the external interrupt signal is disabled Set the T7ICEN flag of the TM7MD2 register to 1 to enable the trigger generation VI 40 16 bit Timer Capture 6 16 bit Timer Capture Operation Triggered by Writing Software Timer 7 A capture trigger can be generated by writing an arbitrary value to the input capture register TM7IC and at the same timing the value of the binary counter can be stored to the input capture register Count clock TM7EN flag Compare register i sir ins A a di m counter Capture trigger Synchronous to writing signal Sapure 0000 0114 5558 register Figure 6 9 2 Capture Count Timing Triggered by Writing Software Timer 7 The capture trigger is generated at the writing signal to the input capture register The
216. the communication Note Procedures 1 to 2 can be set at once Note Procedures 6 to 10 can be set at once Note Procedures 11 to 12 can be set at once Set each flag in order of the setup procedures Set all the control registers refer toTa ble 14 2 1 except TXBUF2 before start communication XIV 50 Operation Chapter 15 Serial interface 4 15 Serial interface 4 XV 2 15 1 Overview This LSI contains a serial interface 4 that can be used for both communication types of clock synchronous and UART full duplex 15 1 1 Functions Table 15 1 1 shows functions of serial interface 4 Table 15 1 1 Serial Interface 4 functions Communication style Clock synchronous UART full duplex Interrupt SC4TIRQ SC4TIRQ on transmission completion SC4RIRQ on reception completion Used pins SBO4 SBI4 SBT4 TXD4 RXD4 3 channels type 2 channels type O SBO4 SBT4 1 channel type TXD4 Specification of transfer bit count Frame 1 to 8 bits 7 bit 1STOP selection 7 bit 2STOP 8 bit 1 STOP 8 bit 2STOP Selection of parity bit Parity bit control 0 parity 1 parity odd parity even parity Selection of start condition Only enable start condition is available Specify of the first transfer bit Specify of input edge output edge SBO4 output control after final data H L final data hold
217. the communication by setting both of the SC2SBOS flag and the SC2SBIS flag of the SC2MDI register to 0 the 5802 pin function port input data input 1 When a forced reset is done the status register all flag of the SC2STR register and SC2BSY flag of the SC2MDO register are cleared but other control registers hold their set values B Last Bit of Transmission Data Table 13 3 4 shows last bit data output holding time at transmission and the minimum data input time of the last bit at reception At slave internal clock setup is necessary to reserve data holding time at data transmission Table 13 3 4 Last Bit Data Length of Transmission Data at transmission Last bit data holding period at reception Last bit data input period At master 1 bit data length 1 bit data length min At slave 1 bit data length of external clock x 1 2 internal clock cycle x 1 2 to 3 2 When start condition is disabled SC2STE flag 0 SBO2 output after last bit data output hold time can be set with SC2FDC1 0 of the SC2MD3 register as shown in Table 13 3 5 After reset release output before serial transfer is regardless of the set value of SC2FDC1 0 flags When start condition is enabled SC2STE flag 1 H is output regardless of the set value of SC2FDC1 0 flags Operation XIII 19 13 Serial Interface 2 Table 13 3 5 SBO2 Output after Last Bit Data Output Hold Time without start condition
218. the oscillation stabilization wait control register DLYCTR Table 10 3 1 Buzzer Output Frequency fosc fx BUZS2 BUZS1 BUZSO Buzzer output frequency 20 MHz 0 0 0 1 22 kHz 20 MHz 0 0 1 2 44 kHz 20 MHz 0 1 0 4 88 kHz 8 39 MHz 0 1 0 2 05 kHz 8 39 MHz 0 1 1 4 10 kHz 2 MHz 1 0 0 1 95 kHz 2 MHz 1 0 1 3 91 kHz 32 kHz 1 1 0 2 kHz 32 kHz 1 1 1 4 kHz Operation 10 Buzzer 10 3 2 Setup Example Setup Example Buzzer outputs the square wave of 2 kHz from PD5 pin It is used 8 39 MHz as the high oscillation clock fosc An example of setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the buzzer frequency 1 Set BUZS2 to BUZSO flag of the oscillation stabilization DLYCTR 0x03F03 wait control register DLYCTR to 010 to select fosc bp6 4 BUZS2 0 010 212 to the buzzer frequency When the high oscillation clock fosc is 8 39 MHz the buzzer output frequency is 2 05 kHz 2 Set PD5 pin 2 Set the output data PDOUTS of PD5 pin to 0 and set PDOUT 0x03F1D the direction control PDDIR5 of PD5 pin to 1 to select bp5 PDOUT5 0 output mode PDDIR 0x03F3D Port D5 pin outputs low level bp5 PDDIRS5 1 3 Buzzer output ON 3 Set the BUZSE flag of the oscillation stabilization wait DLYCTR 0x03F03 control register DLYCTR to 1 to output the square bp7 BUZOE 1 wave of the buz
219. the used pin When crystal oscillator or ceramic oscillator is used the frequency is changed depending on the condenser rate Therefore consult the manufacturer of the pin for the appropriate external capacitor 8 8 Clock duty rate should be 45 to 55 09861 ne fxtalt e fxtal2 Lr MN101E01 Osea MN101E01 o C12 C22 The feedback resistor is built in The feedback resistor is built in Figure 1 5 1 Hlgh speed oscillator Figure 1 5 2 Low speed oscillator Electrical Characteristics 1 23 1 Overview KS S ss ss sss 0 9VDD Mese Mee MM 0 1VDD gt twh1 gt lt twit gt Figure 1 5 3 OSC1 Timing Chart n__n 0 9VDD n 0 1 lt twh2 gt lt twl2 gt twr2 twf2 Figure 1 5 4 XI Timing Chart 1 24 Electrical Characteristics 1 5 3 DC Characteristics Chapter 1 Overview Ta 40 C to 85 C Vppi7Vpp 73 0 V to 3 6 V Vpp3 Vpp1 to 5 5 V V ss1 V ss2 V ss3 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply current 9 fosc 32 0 MHz Vppi 3 3 V 11 30 Es fs fosc 2 48 0 80 2 Power supply current fosc 20 0 MHz Vpp1 3 3 V 5 8 22 REX DD tts tosc 2 43 75 3 i 1x 32 768 kHz Vpp1 3 3 V 30 120 BER fs fx 2 60 180 Supply current during B 33V apa fx 32 768 kHz Vpp 3 3 12 30 u Vpp1 3 3 V 5 Ipps pp1 3 3 0 3 3 0 Sup
220. to add pull up resistor 4 Set the PODIR5 PODIR3 flags of the Port 0 pin control direction register PODIR to 0 0 04050304 Operation XIII 33 13 Serial Interface 2 XIII 34 Setup Procedure Description 5 Select the transfer bit count SC2MDO 0x03F96 bp2 0 SC2LNG2 0 111 6 Select the start condition SC2MDO 0x03F96 bp3 SC2STE 0 7 Select the first bit to be transferred SC2MDO 0x03F96 bp4 SC2DIR 0 8 Select the transfer edge SC2MDO 0x03F96 bp6 SC2CE1 1 9 Select the communication style SC2CTR 0 0 9 bp2 SC2CMD 0 10 Select the transfer clock SC2MD1 0x03F97 bp2 SC2MST 0 11 Control of pin function SC2MD1 0x03F97 bp4 SC2SBOS 0 bp5 SC2SBIS 1 bp6 SC2SBTS 1 bp7 SC2IOM 0 12 Set the interrupt level SC2ICR 0x03FF6 bp7 6 SC2LV1 0 10 13 Enable the interrupt SC2ICR 0x03FF6 bp1 SC2IE 1 14 Set the activation source of serial communication Dummy data TXBUF2 0x03F9B 15 Transition to STOP mode CPUM 0x03F00 bp3 STOP 1 16 Start serial reception Transfer clock Input to SBT2 pin Reception data Input to SBI2 pin 5 Set the SC2LNG2 0 flags of the serial 2 mode register SC2MD O to 111 to set the transfer bit count to 8 bits 6 Set the SC2STE flag of the SC2MDO register to 0 to disable start condition 7 Set the SC2DIR flag of the SC2MDO register to O to set MSB
221. transmission complete interrupt SCITIRQ is generated the 5 is cleared to 0 If the SCISBOS flag is set to 0 the SCITBSY flag is reset to O Operation XII 39 12 Serial interface 1 B Frame Mode and Parity Check Setup Figure 11 3 17 shows the data format at UART communication Frame Character bit T Figure 12 3 17 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 12 3 15 shows its kinds to be set Table 12 3 15 UART Serial Interface Transmission Reception Data Start bit 1 bit Character bit 7 8 bit Parity bit fixed to 0 fixed to 1 odd even none Stop bit 1 2 bits The SCIFMI to 0 flag of the SC1MD2 register sets the frame mode Table 12 3 16 shows the UART serial inter face frame mode settings If the SCICMD flag of the SCIMDI register is set to 1 and communication is selected the transfer bit count on the SCILNG2 to 0 flag of the SCIMDO register is no more valid Table 12 3 16 UART Serial Interface Frame Mode SC1MD2 register Frame mode SC1FM1 SC1FMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits XII 40 Operation 12 Serial interface
222. type Timer 7 high function 16 bit timer has 2 sets of compare registers with double buffering Also as an independent inter rupt it has a timer 7 interrupt and timer 7 compare register 2 match interrupt 6 1 1 Functions Table 6 1 1 shows the functions of each timer Table 6 1 1 16 bit Timer functions Timer 7 High precision 16 bit timer Input source TM7IRQ T7OC2IRQ Timer operation Event count O TM7IO input SynchronousTM7IO input Timer pulse output O TM7IO output PWM output duty is changeable O TM7IO output High precision PWM output duty cycle are 7 output changeable Synchronous output O Capture function Pulse width measurement Clock source fosc fosc 2 fosc 4 fosc 16 fs fs 2 fs 4 fs 16 TM71O input TM7IO input 2 TM7IO input 4 7 input 16 SynchronousTM71O input SynchronousTM7IO input 2 SynchronousTM7IO input 4 SynchronousTM7IO input 16 fosc Machine clock High frequency oscillation fs System clock Chapter 2 2 6 Clock Switching Overview 6 16 bit Timer Block Diagram 6 1 2 Timer 7 Block Diagram luwpe t
223. used BUZZER 87 yo PD5 Buzzer output Piezoelectric buzzer driver pin The driving frequency can be selected by the DLYCTR register Select output mode with the PDDIR regieter and buzzer output with the DLYCTR register These can be used as normal I O pins when not used as buzzer output pin TM7IOA 26 VO P16 Timer I O pins Event counter clock input pin timer output and PWM signal out TM7IOB 86 PD4 put pin for 16 bit timer 7 To use this pin as event clock input configure this as input by the P1DIR PDD Rregister In the input mode pull up pull down resistors can be selected by the P1PLU and PDPLU register For timer output PWM signal output select the special function pin by the port 1 output mode register P1OMD and the port D output mode register PDOMD and set to the output mode at the P1DIR and PDDIRregister These can be used as normal I O pins when not used as timer O pins SDOO 55 Output P70 A16 Synchronous out 8 bit synchronous output pins 001 56 71 17 put pins Synchronous output for each bit can be selected individually by SDO2 57 P72 A18 the port 7 synchronous output control register P7SYO Set to 003 58 P73 19 the output mode the P7DIR register SDO4 59 P74 NCS When not used for synchronous output these pins can be used SDO5 60 P75 NRE as a normal pins SDO6 61 P76 NWE SDO7 62 P77 NDK VREF 100 power supply for Reference power supply pins for the A D converter
224. without the interposition with synchronized to the interrupt event Port 1 Chapter 4 I O Ports 4 3 2 Registers The following Table shows registers that control the Port 1 Table 4 3 1 Port 1control register Registers Address Function Page P1OUT 0x03F11 Port 1 Output Register IV 15 P1IN 0x03F21 Port 1 Input Register P1DIR 0x03F31 Port 1 Direction Control Register P1PLU 0x03F41 Port 1 Pull up Resistor Control Register P1OMD 0x03F2B Port 1 Output Mode Register P1CNTO OxOSF7E Port 1 Real Time Output Control Register 0 R W Readable Writable Port 1 Output Register P1OUT 0x03F11 bp Flag Description P1OUT6 P1OUT5 P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0 Output data 0 Output L VSS level 1 Output H VDD level O 1 IV 15 4 I O Ports Port 1 Input Register P1IN 0x03F21 bp Flag Description 7 E 6 P1IN6 b s Input data 0 Pin is L VSS level 3 PTSS 1 Pin is H VDD level 2 P1IN2 evel 1 P1IN1 0 P1IN0 Port 1 Direction Control Register P1DIR 0x03F31 IV 16 Flag P1DIR6 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO At reset 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W bp Flag Description O gt O Q O Port 1 P1DIR6 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0 I O mode selec
225. writing signal is generated at the last cycle of the writing instruction In synchronized with this capture trigger the value of the binary counter is loaded to the input capture register The value is depending on the value of the binary counter at the falling edge of the capture trigger The other timing is the same as the timer operation The writing to the input capture to generate the capture trigger should be done with 8 bit access instruction of the TM7ICL register or the TM7ICH register At this time data is not actually written to the TM7IC register On hardware there is no flag to disable the capture operation triggered by writing software Capture operation is enabled regardless of the T7ICEN flag of the TM7MD2 register counting up may be written to the input capture register To prevent this use the event count by the synchronous TM71O input Chapter 6 6 4 1 16 bit Event Count Operation a If the capture operation is done during TM7IO input or the operation at fosc incorrect data at 16 bit Timer Capture VI 41 6 16 bit Timer 6 9 2 Setup Example S OO O Capture Function Setup Example Pulse width measurement is enabled by storing the value of the binary counter to the capture register at the inter rupt generation edge of the external interrupt 0 input singal with timer 7 The interrupt generation edge is speci fied to be the rising edge An example setup prcedur
226. 0 0 0 Description TM5PSC1 TM5PSCO TM5BAS Select the clock source 000 fosc 4 010 fosc 16 100 fosc 64 110 fosc 128 X01 fs 2 X11 fs 8 Control Registers V 13 5 8 bit Timers 5 2 3 Programmable Timer Registers Each of timers 0 to 5 has 8 bit programmable timer registers Programmable timer register consists of compare register and binary counter Compare register is 8 bit register which stores the value to be compared to binary counter are stocked Timer 0 Compare Register TMO0OC 0x03F52 7 6 5 4 3 2 1 0 TMOOC7 TMOOC6 TMOOC5 TM0OC2 TM0OC1 TM0OC0 X X X X X X X X Timer 1 Compare Register TM1OC 0x03F53 7 6 5 4 2 1 0 TM1OC7 TM1OC6 TM1OC5 TM1OC4 TM1OC2 TM1OC1 TM1OC0 X X X X X X X Timer 2 Compare Register TM20C 0x03F5A 7 6 5 4 2 1 0 20 7 TM20C6 TM20C5 TM20C4 2 2 2 1 20 0 X X X X X X X Timer 3 Compare Register TM30C 0x03F5B 7 6 5 4 2 1 0 TM3OC7 TM30C6 5 4 2 1 TM3OC0 X X X X X X X V 14
227. 0 1 These registers are used as address pointers specifying data locations in memory They support the operations involved in address calculations i e addition subtraction and comparison Those pointers are 2 bytes data Transfers between these registers and memory are always in 16 bit units Either odd or even address can be trans ferred At reset the value of address register is undefined 15 0 1 A Figure 2 1 4 Address Registers Stack Pointer SP This register gives the address of the byte at the top of the stack It is decremented during push operations and incremented during pop operations Ar reset the value of SP is undefined 15 0 Stack pointe Figure 2 1 5 Stack Pointer Overview Chapter 2 CPU Basics 2 1 6 Registers for Data uz u TT Registers for data include four data registers DO D1 D2 D3 Data Registers DO 01 D2 03 Data registers DO to D3 are 8 bit general purpose registers that support all arithmetic logical and shift operations registers can be used for data transfers with memory The four data registers may be paired to form the 16 bit data registers DWO D0 D1 and DW1 D2 D3 At reset the value of Dn is undefined 15 87 0 Data register Figure 2 1 6 Data Registers Overview 1 9 2 CPU Basics 2 1 7 Processor Status Word Processor status word PSW is 8 bit registe
228. 00 CPUM After written in CPUM some NOP instructions three or less are executed Transition to STOP mode The system transfers from NORMAL mode to STOPO mode and from SLOW mode to STOP1 mode In both cases oscillation and the CPU are both halted There are two ways to leave a STOP mode a reset or an interrupt Program 5 MOV x8 DO Set STOP mode CPUM After written in CPUM some NOP instructions three or less are executed a Insert three NOP instructions right after the instruction of the transition to HALT STOP mode 50 Standby Function Chapter 2 CPU Basics 2 6 Clock Switching This LSI can select the best operation clock for system by switching clock cycle division factor by program Divi sion factor is determined by flag of the CPU mode control register CPUM At the highest frequency CPU can be operated in the same clock cycle to the external clock hence providing wider operating frequency range B CPU Mode Control Register CPUM Table 2 6 1 CPU Mode Control Register CPUM 0x03F00 bp 7 6 5 4 3 2 1 0 Flag Reserved OSCSEL1 OSCSELO OSCDBL STOP HALT OSC1 OSCO Atreset 0 0 0 0 0 0 0 0 Access R W Reserved Set always to 0 OSCSEL1 Clock Frequency OSCSELO 00 1 01 4 10 16 11 64 Internal System Clock 0 Standard Input the oscillation clock cycle divided by 2 1 2x speed Input the oscillation cloc
229. 0000 The PWM source waveform outputs H until TM7BC reaches the set value of the TM7OCI register then after the match it outputs L After that TM7BC continues to count up Once a overflow occurs the PWM source waveform outputs H again and TM7BC counts up from 0x0000 again In the initial state of the PWM output it is changed to H output from L output at the timing that the PWM operation is selected with the TM7PWM flag of the TM7MD register 16 bit Standard PWM Output Only duty can be changed consecutively 6 16 bit Timer 6 7 16 bit High Precision PWM Output Cycle Duty can be changed consec utively The TM71O pin outputs high precision PWM output which is determined by the match timing of the timer binary counter and the compare register 1 and match timing of the binary counter and the compare register 2 6 7 1 Operation B 16 bit High Precision PWM Output Operation Timer 7 The PWM waveform of any cycle duty is generated by setting the cycle of PWM to the compare register 1 TM7OC1 and setting the duty of H period to the compare register 2 TM7OC2 Count Timing of High Precision PWM Output at Normal Timer 7 TM7EN flag Compare register 1 Compare register 2 M em en edo lcs ed je counter TM7IO output PWM output 8 Setup time for compare register PWM basic component Setup time for compare register 1 Figure 6 7 1 Count
230. 03F79 bp4 TM7PWM 1 5 Set the high precision PWM output TM7MD2 0x03F79 bp5 TM7BCR 1 bp6 T7PWMSL 1 6 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 01 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Timer pin switching Set TM7SEL flag of the register TMSEL to 0 and select TM71OA as the output pin 3 Set the P1OMD6 flag of the port P1 output mode register P1OMD to 1 to set P16 pin as the special function pin Set the P1DIR6 flag of the port P1 direction control register P1DIR to 1 to set the output mode Chapter 4 Ports 4 Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 to 1 to select the PWM output 5 Set the TM7BCR flag of the TM7MD2 register to 1 to select the TM7OC1 compare match as the binary counter clear decision And set the T7WMSL flag to 1 to select the TM7OC2 compare match as the duty decision source of the PWM output 6 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 2 dividing as the count clock source by 7 51 to 0 flag 16 bit High Precision PWM Output Cycle Duty can be changed consecutively 6 16 bit Timer Setup Procedure Description 7 Set the PWM output cycle TM7PR1 0x03F75 0x03F74 0x61a7 8 Set the H period of the PWM output TM7PR2 0x03F7D 0x03F7C 0x1869
231. 1 bp 7 6 5 4 3 1 0 Flag SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE SCOBRKF SCOBRKE Reset 0 0 0 0 0 0 0 Access R W R W R Description Frame mode specification 00 7 data bit 1 stop bit 01 7 data bit 2 stop bit 10 8 data bit 1 stop bit 11 8 data bit 2 stop bit SCOFM1 SCOFMO Added bit specification Transmission Reception SCOPM1 00 Add 0 Check for 0 SCOPMO 01 Add 1 Check for 1 10 Add odd parity Check for odd parity 11 Add even parity Check for even parity Parity enable SCONPE 0 Enable parity bit 1 Disable parity bit Break status receive monitor SCOBRKF O Data reception 1 Break reception Break status transmit control SCOBRKE 0 Data transmission 1 Break transmission Control Registers XI 11 Serial interface 0 Serial interface 0 Mode Register 3 SC0MD3 0x03F92 bp 7 6 3 2 1 0 SCOPSC E Flag SCOFDC1 SCOFDCO SCOPSC2 SCOPSC1 SCOPSCO Reset 0 0 0 0 0 0 Access Description Output selection after SBOO final data transmission 00 Fix at 1 High output 01 Final data hold 10 Fix at 0 Low output 11 Reserved SCOFDC1 SCOFDCO Prescaler count control SCOPSCE 0 Count is forbidden 1 Count is allowed Selection clock 000 fosc 2 001 fosc 4 SCOPSC2 010 fosc 16 SCOPSC1 011 fosc 64 SCOPSCO 100 fs 2 101 fs 4 110 Timer 2 output 111 Timer 4 output
232. 1 fs base 3 bits Prescaler Prescaler outputs fosc 4 fosc 16 fosc 32 fosc 64 fosc 128 Prescaler 1 outputs fs 2 fs 4 fs 8 Fosc or fs can be selected as the clock source for each timer by using the prescaler Overview 5 1 1 Functions Chapter 5 8 bit Timers Table 5 1 1 shows functions that can be used with each timer Table 5 1 1 Timer Functions Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit Interrupt TM0IRQ TM1IRQ TM2IRQ TMSIRQ TM4IRQ TM5IRQ source Timer O O O O O operation Event count TMOIO input TM1IO input TM2IO input TMSIO input TMAIO input TMBIO input P10 P11 P12 P13 P14 P15 Timer pulse TMOIO output output TM2IO output TMSIO output TMAIO output TMBIO output output P10 P11 P12 P13 P14 PD2 P15 PD3 PWM output TMOIO output 21 output TMAIO output pin pin pin P10 P12 P14 PD2 Synchronous Port 7 Port 7 output Serialtransfer clock output Pulse width External External measurement interrupt 2 interrupt 3 interrupt 4 P22 IRQ2A P23 IRQ3A P24 IRQ4 PDO IRQ2B PD1 IRQ3B Cascade O connection Clock source fosc fosc fosc fosc fosc fosc fosc 4 fosc 4 fosc 4 fosc 4 fosc 4 fosc 4 fosc 16 fosc 16 fosc 16 fosc 16 fosc 16 fosc 16 fosc 32 fosc 64 fosc 32 fosc 64 fosc 32 fosc 64 fosc 64 fosc 128 fosc 64 fosc
233. 1 90 0018 90 06C2 00 0019 00 et the correction address setting register and the vector table STEP 2 Set the ROM ddr greg d the RC Setup for the first correction Set the head address of the program to be The first program to be corrected internal ROM corrected at first to the ROM correction The head 2 address setting register RCOAP Address Data 79 Set value o RCOAPL 0x19 10916 D900A0 cbne 0 d1 1091E 22 109197 005 50 40 POEM ae 1091B 58 mov 90 RC0APH 0x01 1091C 8940 10920 5 1091 4 Set the internal RAM address 0x06B4 that sub 40 00 stored first correct program to the RC vector ho godless ToU aene table address RC0V L RC0V H f RC0V L 0xB4 The first correct program internal RAM RC0V H 0x06 The head address of the correction program Data the set value of RCOV 006847 A000 mov 0 do 006 6 58 d0 a0 00687 392C190 bra 1091 The addres for recover ROM Correction 35 2 CPU Basics II 36 Setup for the second correction Set the head address of the program to be cor rected at second to the ROM correction address 1 setting register 0 0 08 0 01 Set the internal RAM address 0 06 that stored second correct program to the RC vec tor table address RC1V L RC1V L 0xBC RC1V H 0x06 STEP 3 Set the bit 0 RCO
234. 1 Automatic Transfer Controller 18 1 1 Overview This LSI contains an automatic transfer controller that uses direct memory access to transfer the contents of the whole memory space 1 MB using the hardware This ATC block is called ATC1 1 is activated by an interrupt or a flag set by the software Once this occurs even if it is in the middle of exe cuting an instruction the microcontroller waits for a time when it can release the bus stops normal operation and transfers bus control to ATC1 1 then uses the released bus for the hardware data transfer The software sets the activation factor in control register 1 then data transfer begins when the flag in ATCI control register 0 ATICNTO is set to 1 flag is automatically cleared to 0 when 1 is activated The transfer data counter ATITRC determines the number of transfers that ATC1 makes up to a maximum of 255 times There are also 16 transfer modes set in ATCI control register 0 ATI CNTO The interrupt enable flag xxxlE for interrupt as a trigger factor needs not to be set This is because the automatic data transfer occurs in the hardware without going through an inter rupt service routine If the interrupt enable flag is set for the type of interrupt ATC1 a regular interrupt is generated after the automatic transfer ends In processor mode and memory expansion m
235. 1 and a vector 4 set to level 2 request interrupt simultaneously vector 3 will be accepted Vector 1 an Priority Interrupt vector No interrupt 8 1 1 g Level 0 Vector 2 5 6 2 Vector 2 8 3 Vector 5 o Level 1 Vector 3 4 Vector 6 s 5 Vector 3 8 Level 2 Vector 4 8 6 Vector 4 7 Vector 8 Figure 3 1 3 Interrupt Priority Outline Overview III 7 Chapter 3 Interrupts Determination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance 1 The interrupt request flag xxxR in the corresponding external interrupt control register IROnICR and inter nal interrupt control register xxxICR are set to 1 2 An interrupt request is input to the CPU If the interrupt enable flag xxxIE of the same register is 1 3 The interrupt request signal is set for each interrupt The interrupt level IL is input to the CPU 4 The interrupt request is accepted If IL has higher priority than IM and MIE is 1 5 Acceptance of an interrupt does not reset the corresponding interrupt enable flag xxxIE to 0 Current interrupt mask level IM ZF PSW MIE IM1 IM0 NF Level judgement Accepted if IL lt IM PN 7 A XXxlE xxxlR Generated interrupt level IL Figure 3 1 4 Determination of Interrupt Acceptance
236. 1 parity odd parity even parity Selection of start condition Only enable start condition is available Specify of the first transfer bit Specify of input edge output edge SBO1 output control after final data H L final data hold moved out At the standby mode Only slave reception is available Continuous operation Internal clock 1 8 dividing O Only 1 8 dividing is available Overview 12 Serial interface 1 Clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 External clock Timer 4 output Timer 5 output fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 4 output Timer 5 output Maximum transfer rate 5 0 MHz 300 kbps fosc Machine clock High speed oscillation fs System clock a Set the transfer rate slower than system clock fs Overview XII 3 12 Serial interface 1 12 1 2 Block Diagram B Serial interface 1 Block Diagram
237. 1 pin Output pin SBO1 pin Transfer bit counter SC1TBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 6 Transmission Timing at falling edge start condition is enabled At master At slave Tmax 3 5T T 2 Clock 58711 pin Output SBO1 Transfer bit counter SC1 TBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 7 Transmission Timing at falling edge start condition is disabled Operation XII 21 12 Serial interface 1 At master At slave Tmax 2 5T T T f 2 E U Clock SBT1 pin Output pin SBO1 pin Transfer bit counter SC1TBSY Data set to TXBUF 1 Interrupt SC1TIRQ Figure 12 3 8 Transmission Timing at rising edge start condition is enabled At master At slave 3 5 T 2 Clock SBT1 pin Output pin SBO1 pin Transfer bit counter SC1TBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 9 Transmission Timing at rising edge start condition is disabled XII 22 Operation 12 Serial interface 1 B Reception Timing Clock SBT1 pin Input pin SBO1 SBI1 pin Transfer bit counter SC1RBSY Interrupt SC1TIRQ Figure 12 3 10 Reception Timing at rising edge start condition is enabled At master Tmax 3 5T T Clock SBT1 p
238. 11 26 TM1ICR OxO3FE9 R W Timer 1 interrupt control register Timer 1 compare match 11 27 TM2ICR OxOSFEA R W Timer 2 interrupt control register Timer 2 compare match III 28 TMSICR OxO3FEB R W Timer 3 interrupt control register Timer compare match 11 29 TM4ICR OxO3FEC R W Timer 4 interrupt control register Timer 4 compare match III 30 TM5ICR OxOSFED R W Timer 5 interrupt control register Timer 5 compare match III 31 TM6ICR OxO3FEE R W Timer 6 interrupt control register Timer 6 compare match III 32 TBICR OxOSFEF R W Time base interrupt control register Time base period III 33 TM7ICR OxOSFFO R W Timer 7 interrupt control register Timer 7 compare match III 34 T7OC2ICR 0x03FF1 R W Timer 7 compare register 2 match interrupt control register 111 35 SCORICR OxO3FF2 R W Serial 0 UART reception interrupt control register III 36 SCOUART reception completion SCOTICR Ox03FF3 R W Serial O UART transmission interrupt control register III 37 SCOUART transmission completion SC1RICR OxO3FF4 R W Serial 1 UART reception interrupt control register 11 38 SC1UART reception completion SC1TICR OxO3FF5 R W Serial 1 UART transmission interrupt control register 111 39 SC1UART transmission completion SC2ICR OxO3FF6 R W Serial 2 interrupt control register SC2 transfer completion 40 SC3ICR OxOSFF7 R W Serial interrupt control register SC3 transfer completion 111 41 SC4RICR OxOSFF8 R
239. 1101 Transfer mode D 1110 Transfer mode E 1111 Transfer mode F AT1MDS3 AT1MD2 AT1MD1 AT1MDO Reserved Set always to 0 1 transfer enable flag AT1EN 0 ATC1 transfer disable 1 ATC1 transfer enable Control Registers XVIII 7 18 Automatic Transfer Controller ATC1 Control Register 1 AT1CNT1 0x03FD1 Flag Reserved AT1IR2 AT1IR1 AT1IR0 At reset 0 0 0 0 0 Access Description Reserved Set always to 0 Burst transfer stop enable 0 Burst transfer stop disable 1 Burst transfer stop enable Transfer stops when external interrupt 0 occurs BTSTP ATC1 trigger factor settings 0000 External interrupt 0 0001 External interrupt 1 0010 Serial interface 0 UART transmission interrupt 0011 Serial interface 1 UART transmission interrupt 0100 Timer 7 interrupt 0101 Timer 7 capture trigger 0110 A D converter interrupt 0111 Software activation 1000 External interrupt 2 1001 External interrupt 3 1010 Serial interface 2 interrupt 1011 Serial interface 3 interrupt 1100 Serial interface 4 UART transmission interrupt 1101 Serial interface 0 UART reception interrupt 1110 Timer 0 interrupt 1111 Timer 1 interrupt AT1IR3 AT1IR2 AT1IR1 AT1IR0 1 When burst transfer stop is enabled do not select external interrupt 0 for ATC1trigger factor 8 Control Registers 18 Automat
240. 128 fosc 64 fosc 128 fs 2 fs 2 fs 2 fs 2 fs 2 fs 2 fs 4 15 8 15 4 15 8 15 4 15 8 fx fx fx fx fx TMOIO input TM11O input 210 input TMSIO input TMAIO input TMBIO input synchronous fx synchronous fx synchronous fx synchronous fx synchronous fx synchronous fx synchronous synchronous synchronous synchronous synchronous synchronous TMOIO input TM11O input 210 input TMSIO input TMAIO input TMBIO input fosc Machine clock High frequency oscillation fx Machine clock Low frequency oscillation fs System clock Chapter 2 2 5 Clock Switching Overview V 3 5 8 bit Timers 5 1 2 Block Diagram Prescaler Block Diagram Times xc TM4PSC0 TM4PSC1 TM4BAS 2 M z Timer 4 bp7 CK5MD TM5BAS TM5PSC0 bp0 7bit prescaler s 3bit prescaler s fosc ck PSC0 fs ck PSC1 CKOMD TMOBAS F 3 TM0PSC0 TM0PSC1 2 P M n NUN 4 T Timer 0 __ __ X __ ___ TM1BAS 3 TM1PSCO UM L 2 N M SENE 4 dI u Timer x CK2MD TM2BAS 3 TM2PSC0 TM2PSC1 2 __ bi M per x 3 TM3PSC0 1 2 4 TI 3 gt 4 ___ c 2 pev cer U x 4 xo eo sre ER BBA OOO G c 8 83 22 33 Figure 5 1 1 Prescaler Block Diagram V 4 Overview 5 8 bit Timers Timers and 1 Block Diagram
241. 17 6 4 2 Setup Example ore eee gem eee o e na pere hend VI 20 6 5 16 bit Timer Pulse eet eter ree ett re ERU ip ete Re SE VI 22 6 5 T Operation sie oec Ut ea gs ee EROR IE er e eines VI 22 6 5 2 Setup Exarniple i e eiecit tte eh e VI 24 6 6 16 bit Standard PWM Output Only duty can be changed consecutively VI 26 6 6 T Operation A A VI 26 6 62 Setup Example reet eo ione b ie bee piece ete eet ges VI 29 6 7 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI 31 6 7 T Oper tion si eere tum e pU PRI D eee end VI 31 6 7 2 Setup Example noo ARRIERE gue ee ie i VI 34 6 8 16 bit Timer Synchronous Output n VI 36 6 8 I eene HOT eed one Re ERREUR re HE VI 36 6 8 2 Setup Example eaa eR REORUM VI 37 6 9 16 bit Timer Capture epa BL he ted e Doe ier eee VI 38 6 9 T OperatiOD ee pec pac it beet i eie iicet VI 38 6 9 2 Setup Examples u n a S SN A SS SU VI 42 Chapter 7 Time Base Timer Free running Timer essere VII 1 FARO C EE VII 2 FANE x P VII 2 7 1 2 1 n 4 7 2 Control Registers auqa D am as VII 5 7 2 J Con
242. 18 ACK Bit Reception Timing after Transmission of 8 Bit Data B Transmission of Confirming ACK Bit of Data Reception Selection of enable disable of ACK bit is same with at the transmission When ACK bit is enabled ACK bit and clock are output after data 1 to 8 bits is received When the reception is continued ACK bit outputs L And when the reception is finished it outputs The SC2ACKO of the SC2CTR register sets the output ACK bit level Data reception erio period Interrupt Figure 13 3 19 ACK Bit Transmission Timing after Reception of 8 Bit Data XIII 38 Operation 13 Serial Interface 2 B Transfer Format There are two transfer format used on IIC bus are the addressing format that transmits receives data after 1 byte data address data that consists of slave address 7 bits and R W bit 1 bit is transferred after start condition and the free data format that transmits data right after the start condition The serial interface of this LSI supports 2 communication formats for only master transmission and master reception in IIC communication Sequence of communication is shown below The shaded part shows the data transferred from slave Start Stop condition Slave address R W ACK Data ACK condition Start no Stop condition Slave address R W ACK Data ACK condition Start Stop condition Data ACK condition
243. 2 SC4PSC1 SCAPSCA 0 0 0 0 0 0 Description Output selection after SBO4 final data transmit 00 Fix at 1 High output 01 Final data hold 10 Fix at 0 Low output 11 Reserved SC4FDC1 SC4FDCO Prescaler count control SC4PSCE 0 Count is forbidden 1 Count is allowed Selection clock 000 fosc 2 001 fosc 4 SC4PSC2 010 fosc 16 SC4PSC1 011 fosc 64 SC4PSC4 100 fs 2 101 fs 4 110 Timer 2 output 111 Timer 5 output XV 10 Control Registers Serial interface 4 Status Register SC4STR 0x03FAF bp 7 6 5 4 3 2 1 Chapter 15 Serial interface 4 0 Flag SC4TBSY SC4RBSY SCATEMP SC4REMP SC4FEF SC4PEK SC4ORE SC4ERE Reset 0 0 0 0 0 0 0 0 Access R SC4TBSY R R R R R Description Serial bus status 0 Other use 1 Serial transmission in progress R R SC4RBSY Serial bus status 0 Other use 1 Serial reception in progress SC4TEMP Transfer buffer empty flag 0 Empty 1 Full SC4REMP Receive buffer empty flag 0 Empty 1 Full SC4FEF Framing error detection 0 No error 1 Error SC4PEK Parity error detection 0 No error 1 Error SC4ORE Overrun error detection 0 No error 1 Error SC4ERE Error monitor flag 0 No error 1 Error Control Registers XV 11 15 Serial interface 4 XV 12 15 3 Opera
244. 2 Serial interface 1 B Transmission Timing TXD1 pin Parity gt Stop bit bit bit SC1TBSY Data set to TXBUF1 lt Interrupt SCiTIRQ Figure 12 3 20 Transmission Timing parity bit is enabled TXD1 pin Stop bit SC1TBSY Data setto TXBUF1 x Interrupt SC1TIR Figure 12 3 21 Transmission Timing parity bit is disabled Operation XII 48 12 Serial interface 1 B Reception Timing Tmin 0 5T T Stop RXD1 pin bit SC1RBSY Input start condition Interrupt bord SC1RIRQ Figure 12 3 22 Reception Timing parity bit is enabled Tmin 0 5T T gt Stop RXD1 pin bit SC1RBSY Input start Honiton Interrupt SC1RIRQ Figure 12 3 23 Reception Timing parity bit is disabled XII 44 Operation 12 Serial interface 1 B Transfer Speed Setup Baud rate timer timer 1 timer 2 can set any transfer rate Table 12 3 19 shows the setup example of the transfer speed Table 12 3 19 UART Serial Interface Transfer Speed Setup Register Page Serial 1 clock source timer 4 timer 5 SC1MD3 XII 10 Timer 4 clock source TM4MD V 21 Timer 4 compare register TM10C V 15 Timer 5 clock source TM5MD V 22 Timer 5 compare register TM50C V 15 Timer compare register is set as follows baud rate 1 overflow cycle 2x 8 8 means that clock source is divided by 8
245. 2 103 1202 51 2404 25 4808 1050 16 103 300 25 1202 12 2404 fosc 32 51 300 12 1202 fosc 64 25 300 15 2 129 962 103 1202 51 2404 25 4808 15 4 207 300 64 962 51 1202 25 2404 12 4808 8 8 fosc 217 2403 108 4805 fosc 4 135 963 108 1201 fosc 16 108 300 33 963 13 2338 056 32 16 963 6 2338 fosc 64 15 2 135 963 108 1201 15 4 217 300 67 963 12 00 fosc 155 4808 fosc 4 194 962 155 1202 77 2404 38 4808 fosc 16 155 300 38 1202 fosc 32 TI 300 fosc 64 38 300 15 2 194 962 155 1202 77 2404 38 4808 15 4 77 1202 38 2404 16 00 fosc 207 4808 fosc 4 207 1202 103 2404 51 4808 1050 16 207 300 64 962 51 1202 25 2404 12 4808 105 32 103 300 25 1202 12 2404 fosc 64 51 300 12 1202 1 2 207 1202 103 2404 51 4808 15 4 129 962 103 1202 51 2404 25 4808 Figure 12 3 24 Setup Value of UART Serial Interface Transfer Speed XII 46 Operation 12 Serial interface 1 Transfer Speed bit s Clock source 9600 19200 28800 31250 38400 Timer SetValue 588 Set Value SetValue Set Value aH Set Value fosc 25 9615 12 19231 7 31250 fosc 4 1 31250 05016 1056 32 fosc 64 6 2
246. 207 Timer clock source and the set value of compare register at the standard rate shown in following page 1 Transfer rate should be selected under 300 kbps Operation XV 45 15 Serial interface 4 XV 46 Transfer Speed bit s fosc Clock source 300 960 1200 2400 4800 MHz Timer Set Value Set Value SetValue SetValue Nave Set Value 004888 400 fosc 207 1202 103 2404 51 4808 fosc 4 207 300 64 962 51 1202 25 2404 12 4808 fosc 16 51 300 12 1202 1050 32 25 300 fosc 64 12 300 6 2 207 300 64 962 51 1202 25 2404 12 4808 16 4 104 297 25 1202 12 2404 419 fosc 217 1201 108 2403 54 4761 fosc 4 217 300 67 963 fosc 16 16 963 6 2338 fosc 32 fosc 64 16 2 217 300 67 963 154 108 300 33 963 13 2338 8 00 fosc 207 2404 103 4808 fosc 4 129 962 103 1202 51 2404 25 4808 fosc 16 103 300 25 1202 12 2404 fosc 32 51 300 12 1202 fosc 64 25 300 16 2 129 962 103 1202 51 2404 25 4808 16 4 207 300 64 962 51 1202 25 2404 12 4808 8 38 fosc 217 2403 108 4805 fosc 4 135 963 108 1201 fosc 16 108 300 33 963 13 2338 fosc 32 16 963 6 2338 fosc 64 15 2 135 963 108 1201 16
247. 254105 7 0954195 0 amwNros Figure 12 1 1 Serial interface 1 Block Diagram Overview XII 4 12 2 Control Registers 12 2 1 Registers Serial Chapter 12 interface 1 Table 12 2 1 shows registers to control serial interface 1 Table 12 2 1 Serial interface 1 Control Registers Register Address Function SC1MDO OxOSF9D Serial interface 1 mode register 0 SC1MD1 OxOSF9E Serial interface 1 mode register 1 SC1MD2 OxOSF9F Serial interface 1 mode register 2 SC1MD3 Serial interface 1 mode register 3 SC1STR 0x03FA1 Serial interface 1 status register RXBUF 1 OxOSFA2 Serial interface 1 received data buffer TXBUF1 Serial interface 1 transmission data buffer PSODC OxOSF2C Port 3 Nch open drain control register P3DIR 43 Port 3 pull up control register P3PLU 0x03F33 Port 3 direction control register SC1RICR 0x03FF4 Serial 1 UART reception interrupt control register SC1TICR 0x03FF5 R W Readable Writable R Readable only Serial 1 UART transmission interrupt control register Control Registers XII 5 12 Serial interface 1 12 2 2 Data Buffer Registers Ez sV n IE m Serial interface 1 has each 8 bit data buffer register for transmission and for reception Serial interface 1 Received Data Buffer RXBUF1 0x03FA2
248. 3 1 a At the standby mode if the value that is set to the external interrupt valid specified flag and to 3 3 6 So when flag is 0 and pin is 0 or flag is 1 and pin is 1 before standby interrupt is gener ated at the standby mode and CPU can be returned Both Edges Interrupt Setup Example External interrupt 2 External interrupt 3 External interrupt 2 IRQ2 is generated at the both edges of the input signal from P22 pin The table below shows a setup example of IRQ2 Setup Procedure 1 Select the both edges interrupt EDGDT 0x03F1E bp2 EDGSEL1 1 2 Set the interrupt level IRQ2ICR 0x03FE4 bp7 6 IRQ2LV1 0 10 3 Enable the interrupt IRQ2ICR 0x03FE4 bp1 IRQ2IE 1 Description 1 Set the EDGSEL2 flag of the both edges interrupt control register EDGDT to 1 to select the both edges interrupt 2 Set the interrupt level by the IRQ2LV1 to 0 flag of the IRQ2ICR register The interrupt request flag of the IRQ2ICR register be set so make sure to clear the interrupt request flag IRQ2IR Chapter 3 3 1 4 Interrupt flag setup 3 Set the IRQ2IE flag of the IRQ2ICR register to 1 to enable the interrupt At the both edges of the input signal from P22 pin an external interrupt 2 is generated When the both edges interrupt is selected the interrupt request is generated at the both edge regardless of the REDGn flag of the external interrupt control register IRQnICR
249. 3 Block Diagram ote ette teo repete IV 93 A TZ POIUA 1 ui dien PER dede nre tede tee eter IV 96 4 12 T Description s eene EC eee IV 96 4 12 2 Registers e the tere ip rte oett aer eo ees IV 97 4 12 3 Block Diagram nue yn eR ala ee eee e IV 101 She nis Sd he AS IV 105 4 13 TL DeserIptien n t teg imet IV 105 4132 Registers onore bU HI P ED D ae ae IV 107 4 133 Block cmo Ru de etae e cei et erede ete ge IV 110 4 14 Real Time Output Control eese enne EEE EE nennen tren nennen nennen IV 114 4 IA IV 114 4 14 2 Operation PRG eee e eese eese IV 115 4 15 Synchronous Output cernentes te ere tue tae en ect eee eee IV 117 4151 Registets RR Dia Oi aee o ede n s IV 117 4 15 2 Operation RH D enn ee DER RIBD UH EE ERR IV 118 4 16 Input Rejection Function u nre eie i petere p che IV 120 4 16 T reo etico D IV 120 4 16 2 ioni Ge IV 120 Chapter d 1 S L V 2 ST dtt i bg eee eee he ERO V 3 5 1 2 Block Diagram oett pem pt RHEINE ERE Rene ende 4 5 2 Control Registers iota ree V 8 5241 Registers yz ans Ae is Q a I RE SAIS SU A aee BO
250. 31250 6 4 fosc osc 4 osc 16 fosc 32 fosc 64 fs 2 fs 4 fosc osc 4 osc 16 fosc 32 fosc 64 fs 2 fs 4 fosc osc 4 osc 16 fosc 32 fosc 64 16 2 15 4 fosc osc 4 osc 16 fosc 32 fosc 64 fs 2 fs 4 fosc osc 4 osc 16 fosc 32 fosc 64 16 2 16 4 4 Figure 12 3 25 Setup Value of UART Serial Interface Transfer Speed Operation XII 47 12 Serial interface 1 XII 48 B Pin Setup with 1 2 channels at transmission Table 12 3 20 shows the pins setup at UART serial interface transmission The pins setup is common to the TXDI pin RXDI pin regardless of those pins are independent connected Table 12 3 20 UART Serial Interface Pin Setup with 1 2 channels at transmission Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port pin P30 P31 TXD1 RXD1 pins selection TXD1 RXD1 pins independent connect SC1MD1 SC1IOM Function Serial data output 1 output SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Push pull Nch open drain P30DC P30DC0 Output mode P3DIR P3DIR0 Pull up setup Added not added P3PLU P3PLU0 B Pin Setup with 2 channels at reception Table 12 3 21 shows the pins setup at UART serial interface reception wit
251. 3CTR register to 0 by program Start condition Stop condition SDA a M E Serial data SCL 1 pp s Serial clock Figure 14 3 17 Start Condition and Stop Condition Input Edge Output Edge Setup In IIC communication data is always received at the falling edge of the clock Even if the SC3CEI flag is set to 0 the received data is stored in the falling edge of the clock Switch the used pin Switch the used pins to A SDA3A SCL3A or B SDA3B SCL3B by SC3SEL flag of SCSEL register Data I O Pin Setup The SDA3 pin used as SBO3 pin too is used to input output data Set the SC3IOM flag of the SC3MDI register to 1 to input serial data from the SBO3 pin As the SBI3 pin is not used at that time it can be used as a general port But always set the SC3SBIS flag of the above register to 1 to set input serial data To detect start condition set the SC3SBIS flag of the SC3MD1 register to input serial data regardless of transmission reception Operation XIV 39 14 Serial Interface 3 Reception of Confirming Bit after Data Transmission The SC3ACKS flag of the SC3CTR register selects if ACK bit is enabled or not If ACK bit is enabled ACK bit 15 received from the slave station after data 1 to 8 bits is transferred At reception of ACK bit the SDA3 line is automatically released To receive ACK bit 1 clock is output to store ACK bit to the SC3ACKO of the SC3CTR
252. 3FC8 bp 7 6 5 4 3 2 1 0 Flag E RC2APH3 RC2APH2 RC2APH1 RC2APHO Atreset gt 0 0 0 0 Access R W 1 Do not set the same address to more than two RCnAP H M L register If there are several registers set the same address the order of priority is as follows RCOAP gt RC1AP gt RC2AP II 32 ROM Correction Here is the correspondence of the ROM correction address setting register a ROM correction control flag of ROM correction control register and the RC vector table Chapter 2 CPU Basics ROM Correction address setting register ROM correction RC vector table control flag Register address vector address PR RCOAPM 0x3FC1 RC0EN RC0APH Ox3FC2 RCOV H 0 0011 RC1APL 0x3FC3 RC1V L 0x0012 TN RC1APM Ox3FC4 RC1EN RC1APH Ox3FC5 RC1V H 90019 correction RC2APM Ox3FC7 RC2EN RC2APH Ox3FC8 RC2V H 0x0015 ROM Correction 33 2 CPU Basics 2 3 4 ROM Correction Setup Example initial Routine with ROM Correction The following routine should be set to correct the program Also store the ROM correction setup and the correct program to the external EEPROM in advance Here is the steps for ROM correction execution Initial Setup ROM Correction is used or not yes Step 1 Develop the correct program of the external EEPROM to RAM area Step 2 Set the ROM co
253. 3PLU and P9PLU registers Select output mode with the PODIR P3DIR and P9DIR register and serial data I O at the serial mode register 1 SC2MD1 SC3MD1 These can be used as normal I O pins when the serial interface is not used TMOIO 20 VO P10 RMOUT Timer I O pins Event counter clock input pin timer output and PWM signal out TM1IO 21 P11 put pin for 8 bit timer 0 to 5 2 22 12 use this as event clock input configure this as input by the 23 P13 P1DIR and PDDIR register In the input mode pull up pull 24 14 down resistors can be selected by the P1PLU and PDPLU regis TM4IOB 84 PD2 ter TM5IOA 25 P15 For timer output PWM signal output select the special function TM5IOB 85 PD3 pin by the port 1 output mode register P1OMD and the port D output mode register PDOMD and set to the output mode at the P1DIE register These can be used as normal I O pins when the serial interface is not used RMOUT 20 VO P10 TMOIO Remote control Output pin for remote control transmission signal with a carrier transmission sig signal nal output pins For remote control carrier output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register Select the remote control carrier output with the remote control carrier output control register RMCTR at the same time These can be used as normal I O pins when the serial interface is not
254. 3TA1 pomi enna o ENIN qNWTA1 DX soul sed Figure 3 3 6 External Interrupt 5 Interface Block Diagram External Interrupts 52 3 Interrupts 3 3 3 Control Registers The external interrupt input signals which passed through each internal interrupt interface 0 to 5 generate inter rupt requests External interrupt 0 to 5 interface are controlled by the external interrupt control register IRQnICR External interrupt interface 0 to 1 are controlled by the noise filter control register and the prescaler control reg ister PSCMD and external interrupt interface 2 to 3 5 is controlled by the both edges interrupt control register EDGDT and external interrupt interface 4 is controlled by the key interrupt control register and external interrupt interface 2 to 3 are controlled by the external interrupt pin switching control register IRQSEL and external interrupt interface 2 to 3 5 are controlled by the external interrupt valid input switching control register LVLMD Table 3 3 2 shows the list of registers which control external interrupt 0 to 5 Table 3 3 2 External Interrupt Control Register External interrupt Register Address R W Function Page External inter IRQOICR OxOSFE2 R W External inter
255. 4 00 7 9 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 1 Set the TM7EN flag of the Timer 7 mode register 1 TM7MD1 to 0 to stop the Timer 7 counting 2 Switch the timer pin Set the TM7SEL flag of the TMSEL register to to select the TM7I0A as the input pin 3 Set the P1OMD6 flag of the port 1 output mode register P1OMD to 1 to set P16 as the special function pin Set the P1DIR6 flag of the port 1 direction control register P1DIR to 1 to set the output mode Chapter 4 Ports 4 Set TM7PWM flag of TM7MD2 register to 0 to select the timer pulse output 5 Set the TM7CL flag of the TM7MD1 register to 0 to enable the pulse output 6 Set the TM7BCR flag of the TM7MD2 register to 1 to select the compare match as the binary counter clear source 7 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing as the clock source by the TM7PS1 to 0 flag 8 Set 1 2 of the timer pulse output cycle to the Timer 7 preset register 1 TM7PR1 To set 100 kHz by dividing 20 MHz set as 200 1 199 0xC7 At the same time the same value is loaded to the Timer 7 compare register 1 TM7BC and the Timer 7 binary counter TM7BC is initialized to 0x0000 9 Set the TM7EN flag of the TM7MD1 register to 1 to operate the Timer 7 16 bit Timer Pulse Output 6 16 bit Timer TM7BC counts up from 0x0000 If
256. 4 207 300 64 962 51 1202 25 2404 12 4808 8 38 fosc 217 2403 108 4805 foscl4 135 963 108 1201 105016 108 300 33 963 13 2330 fosc 32 16 963 6 2330 fosc 64 6 2 135 963 108 1201 fs 4 217 300 67 963 12 00 fosc 155 4808 foscl4 194 962 155 1202 77 2404 38 4808 fosc 16 155 300 38 1202 fosc 32 300 fosc 64 38 300 6 2 194 962 155 1202 77 2404 38 4808 6 4 77 1202 38 2404 16 00 fosc 207 4808 foscl4 207 1202 103 2404 51 4808 105016 207 300 64 962 51 1202 25 2404 12 4808 fosc 32 103 300 25 1202 12 2404 1056 64 51 300 12 1202 6 2 207 1202 103 2404 51 4808 fs 4 129 962 103 1202 51 2404 25 4808 Figure 11 3 24 Setup Value of UART Serial Interface Transfer Speed Operation 11 Serial interface 0 Transfer Speed bit s fosc Clock source 9600 19200 28800 31250 38400 MHz Timer SetValue 2 SetValue Set Value Set Value Set Value 400 fosc 25 965 12 199 7 305 fosc 4 1 31250 1050 16 E z E E fosc 32 fosc 64 A 4 1 31250 fs 4 419 fosc 26 9699 fosc 4 105016 1050 32 1050 64 16 2 16 4 8 00 fosc 51 9615 25 19231 15 31250 12 38462 fosc 4 12 9615 3 31250 fosc 16 fosc 32 1056 64 i fs
257. 4030 Timer 4 interrupt TM4IRQ TM4ICR 0x03FEC 13 0x04034 Timer 5 interrupt TM5IRQ TM5ICR OxOSFED 14 0x04038 Timer 6 interrupt TM6IRQ TM6ICR OxOSFEE 15 0x0403C Time base interrupt TBIRQ TBICR OxOSFEF 16 0x04040 Timer 7 interrupt TM7IRQ TM7ICR 0x03FF0 17 0x04044 Timer 7 compare 2 match T7OC2IRQ T7OC2ICR 0x03FF1 interrupt 18 0x04048 Serial OUART reception interrupt SCORIRQ SCORICR OxO3FF2 19 0x0404C Serial transmission interrupt SCOTIRQ SCOTICR OxO3FF3 20 0x04050 Serial 1UART reception interrupt SC1RIRQ SC1RICR Ox03FF4 21 0x04054 Serial 1 UART transmission inter SC1TIRQ SC1TICR Ox03FF5 rupt 22 0x04058 Serial 2 interrupt SC2IRQ SC2ICR Ox03FF6 23 0x0405C Serial 3 interrupt SC3IRQ SC3ICR OxO3FF7 24 0x04060 Serial 4UART reception interrupt SC4RIRQ SC4RICR OX03FF8 25 0x04064 Serial 4 UART transmission interrupt SC4TIRQ SC4TICR OX03FF9 26 0x04068 A D conversion interrupt ADIRQ ADICR OXOSFFA 27 0x0406C 1 interrupt ATCAIRQ ATCAIRC OX03FFB 6 Overview 3 Interrupts Interrupt Level and Priority This LSI allocated vector numbers and interrupt control registers except reset interrupt to each interrupt The interrupt level except reset interrupt non maskable interrupt can be set by software per each interrupt group There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority For example if a vector 3 set to level
258. 45 111 55 PSCMD 111 44 PSCMD 111 54 EDGDT 11 46 EDGDT 11 56 IRQSEL 46 IRQSEL 1 58 LVLMD 11 46 LVLMD 11 59 IRQ1ICR 1 20 IRQ1ICR 11 21 IRQSICR 11 46 IRQ3ICR 111 23 IRQ4ICR 111 22 IRQ4ICR 11 24 IRQ5ICR 11 46 IRQ5ICR 111 31 IV 6 53 Change The Port 0 output mode register POOMD The Port 0 NcH open drain control register is POODO is IV 12 Figure Change 4 2 6 66 8 bottom lt Record of Changes 1 gt Defini Page Section ion Previous Edition Ver 0 65 New Edition Ver 0 7 IV 79 Figiure Change 4 9 8 J T IV 95 Figiure Change 4 11 6 gt LE Port input d gms i Port input data qu mm IV Table Change Page No Page No 119 4 16 1 P7OUT IV 110 P7DIR P7PLU P7SYO P7SEV V 30 Table Change Description 6 Description 6 50 that the setting value is set to 249 S0 that the setting value is set to 249 0x49 OxF9 V 33 Note 4 Change Timer can be recovered from STOP mode CPU can be recovered from STOP mode V 54 Table Addition Setup Procedure Setup Proce
259. 4CMD 0 10 Select the transfer clock SC4MD1 0x03FAC bp2 SC4MST 0 bp3 SC4CKM 0 11 Control the pin function SC4MD1 0x03FAC bp4 SC4SBOS 0 bp5 SC4SBIS 1 bp6 SC4SBTS 1 bp7 SC4IOM 0 12 Set the interrupt level SC4TICR 0x03FF9 bp7 6 SC4LV1 0 10 13 Enable the interrupt SC4TICR 0x03FF9 bp1 SCATIE 1 14 Set the startup factor of the serial communication Dummy data TXBUF4 0x03FB1 4 Set the PADIR2 P4DIR3 flag of the Port 4 pin direction control register PADIR to 0 0 to set P42 P41 to the input mode 5 Set the SCALNG2 to 0 flag of the serial 4 mode register SCAMDO to 111 to set the transfer bit count 8 bits 6 Set the SCALNG2 to 0 flag of the serial 4 mode register SCAMDO to 111 to disable the start condition 7 Set the SC4DIR flag of the SCAMDO register to 0 to set MSB as a transfer first bit 8 Set the SC4CE1 flag of the SCAMDO register to 1 to set the reception data input edge falling 9 Set the SC4CMD flag of the SC4MD1 register to 0 to select the synchronous serial 10 Set the SC4MST flag of the SC4MD1 register to 0 to select the clock slave external slave Set the SCACKM flag to 0 to select not divided by 8 for the clock source 11 Set the SCASBOS of the SC4MD1 register to 0 the SC4SBTS flag of the SC4SBIS register to 1 to set the SBI4 pin to the serial data input as the SBO4 general port the SBT4 pin to the transfer c
260. 5 44 AN5 abled high impedance output P56 45 AN6 P57 46 AN7 P60 47 VO KEYO A8 port 6 8 bit COMS tri state I O port P61 48 KEY1 A9 Each bit can be set individually as either an input or output by the P62 49 KEY2 A10 P6DIR register A pull up pull down resistor for each bit can be P63 50 KEYS A11 selected individually by the PePLU register P64 51 KEY4 A12 At reset the input mode is selected and pull up resistors are dis 65 52 KEY5 A13 abled high impedance output P66 53 KEY6 A14 P67 54 KEY7 15 P70 55 yo SDOO A16 port 7 8 bit COMS tri state I O port P71 56 SDOO A17 Each bit can be set individually as either an input or output by the P72 57 SDOO 18 P7DIR register A pull up pull down resistor for each port can be P73 58 SDOO A19 selected individually by the SELUD register However pull up P74 59 000 NCS and pull down resistors cannot be mixed P75 60 000 NRE At reset the input mode is selected and pull up resistors are dis P76 61 SDOO NWE abled high impedance output P77 62 SDOO NDK P80 64 VO LEDO DO port 8 8 bit COMS tri state I O port P81 65 LEDO D1 Each bit can be set individually as either an input or output by the P82 66 LEDO D2 P8DIR register A pull up pull down resistor for each bit can be P83 67 LEDO D3 selected individually by the P8PLU register Direct LED drive is P84 68 LEDO D4 available at output P85 69 LEDO D5 At reset the input mode is selected and p
261. 6 TM7OC1H5 TM7OC1H4 TM7OC1H3 R TM7OC1H2 R TM7OC1H1 R TM7OC1HO0 At reset X X X X X X X X Access R R R R R Timer 7 Compare Register 2 Lower 8 bits TM7OC2L 0x03F7A TM7OC2L7 TM7OC2L6 TM7OC2L5 TM70C2L4 TM70C2L3 R TM70C2L2 R TM70C2L1 R TM70C2L0 X X X X X X X X R R R R R Timer 7 Compare Register 2 Upper 8 bits TM7OC2H 0x03F7B TM7OC2H7 TM7OC2H6 TM7OC2H5 TM70C2H4 TM70C2H3 R TM7OC2H2 R TM7OC2H1 R TM7OC2H0 X X X X X X X X R R R R R R R Control Registers VI R 6 16 bit Timer Timer 7 preset registers 1 2 are buffer registers of the compare registers 1 2 of timer 7 If the set value is written to the timer 7 preset registers 1 2 when the counting is stopped the same set value is loaded to the timer 7 com pare register If set value is written to the timer 7 preset registers 1 2 during counting the set value of the timer 7 preset registers 1 2 is loaded to the timer 7 compare registers 1 2 at the timing that the timer 7 binary counter is cleared Timer 7 Preset Register 1 Lower 8 bits TM7PR1L 0x03F74 Flag TM7PR1L7 TM7PR1L6 TM7PR1L5 TM7PR1L4 TM7PR1LS38 TM7PR1L2 TM7PR1L1 TM7PR1LO
262. 6 32 1056 64 16 2 16 4 12 00 31250 16 00 fosc 77 38 25 23 31250 fosc 4 9615 19281 28046 31250 fosc 16 1056 32 1056 64 16 2 31250 16 4 fosc 103 9615 51 19231 31 31250 25 38462 fosc 4 25 fosc 16 9615 19231 31250 1056 32 1056 64 16 2 25 9615 31250 16 4 12 9615 31250 Figure 15 3 25 Setup Value of UART Serial Interface Transfer Speed Operation XV 47 15 Serial interface 4 XV 48 B Pin Setup with 1 2 channels at transmission Table 15 3 20 shows the pins setup at UART serial interface transmission The pins setup is common to the TXD4 pin RXD4 pin regardless of those pins are independent connected Table 15 3 20 UART Serial Interface Pin Setup with 1 2 channels at transmission Setup item Data output pin Data input pin TXD4 pin RXD4 pin Port pin P40 P41 Serial data input selection RXD4 SC4MD1 SC4IOM Function Serial data output 1 output SC4MD1 SC4SBOS SC4MD1 SC4SBIS Style Push pull Nch open drain P4ODC P4ODC0 Output mode P4DIR P4DIR0 Pull up setup Added not added P4PLU P4PLU0 B Pin Setup with 2 channels at reception Table 15 3 21 shows the pins setup at UART serial interface reception with 2 chan
263. 6 7 0010 1101 1101 abs 8 gt lt 8 gt dii 8 if mem8 abs8 4imm8 PC 10 PC CBEQ imm8 abs16 label _ if mem8 abs16 imm8 PC 11 d7 label H PC 11 7 8 0011 1101 1100 abs 16 gt lt gt dz 2 if mem8 abs16 4imm8 PC 1 1 2PC CBEQ imm8 abs16 label _ if mem8 abst6 imm8 PC 124d1 tabe HPC 12 78 0011 1101 1101 lt abs 16 gt lt gt dii 2 2 if mem8 abs16 zimm8 PC 122 PC CBNE CBNE imm8 Dm label if Dm imm8 PC 6 d7 label H2PC 6 3 4 1101 10Dm 48 gt lt 97 H 2 if Dmzimm8 PC 62PC CBNE imm8 Dm label if Dmzimm8 PC 8 d11 label H2PC 8 45 0010 1101 10Dm 48 gt lt d11 sH 3 if Dmzimm8 PC 82PC CBNE imm8 abs8 label _ if mem8 abs8 4imm8 PC 9 d7 label H PC 9 6 7 0010 1101 1110 abs 8 48 gt lt 7 2 if mem8 abs8 imm8 PC 9 PC CBNE imm8 abs8 label _ if mem8 abs8 imm8 PC 10 d1 label H PC 10 6 7 0010 1101 1111 abs 8 lt 8 gt lt 11 if mem8 abs8 imm8 PC 10 PC CBNE imm8 abs16 label if mem8 abst6 imm8 PC 114 d7 label sH3PC 11 7 8 0011 1101 1110 abs 16 gt lt gt lt d7 2 if mem8 abs16 imm8 PC 115PC CBNE imm8 abs16 label if mem8 abs16 4imm8 PC 12 d1 1 abel sHPC 12 7 8 0011 1101 1111 lt abs 16 gt lt gt did if mem8 abs16 imm8 PC 122PC TBZ TBZ abs8 bp label if mem abs8 bp 0 PC 7 d7 label sHPC 7 6 7 0011 0000 Obp abs 8 d7 2 if memB8 abs8 bp 1 PC 72PC TBZ
264. 61 0us 32 768kHz 3 0 V to 3 6 V mode Operation modes NORMAL mode High speed mode SLOW mode Low speed mode HALT mode STOP mode The operation clock can be switched in each mode Oscilalting circuit Internal memory ROM 320 KB RAM 14 KB Memory bank Data memory space is expanded by the bank system Bank for the source address Bank for the destination address ROM correction Maximum parts of the program can be corrected Operating tempre gt 40 C to 85 C Mask ROM version ture Interrupts 20 Internal interrupts Incorrect code execution interrupts Non maskable interrupt NMI Timer interrupts Timer 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt 1 4 Hardware Functions Chapter 1 Overview Timer 6 interrupt Time base interrupt Timer 7 interrupt Match interrupt for Timer 7 compare register 2 Serial interrupts Serial 0 interrupt Serial 0 UART reception interrupt Serial 1 interrupt Serial 1 UART reception interrupt Serial 2 interrupt Serial 3 interrupt Serial 4 interrupt Serial 4 UART reception interrupt A D interrupt A D conversion interrupt Automatic data transfer interrupts ATC1 interrupt 6 External interrupts IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Edge selectable noise filter connectable Edge selectable noise filter connectable Edge selectable both edges interrupt STOP HALT recovered at b
265. 6MD Time base timer is controlled by mode register TM6MD and time base timer clear register TBCLR Both timers are operated by the enable signal of the TM6BEN 7 2 1 Control Registers THI Table 7 2 1 shows the registers that control timer 6 time base timer Table 7 2 1 Control Registers Register Address Function Timer 6 TM6BG 0x03F68 Timer 6 binary counter TM6OC 0x03F69 Timer 6 compare register TM6MD 0x03F6A Timer 6 mode register TM6BEN 0x03F6C Timer 6 enable register TM6ICR 0x03FEE R W Timer 6 interrupt control register III 32 Time base timer TM6MD OxOSF6A R W Timer 6 mode register VII 8 TBCLR 0x03F6B W Time base timer clear control register VII 6 TBICR OxOSFEF R W Time base interrupt control register 33 Control Registers VII 5 7 Time Base Timer Free running Timer 7 2 2 Programmable Timer Registers u s FDIKI Timer 6 is a 8 bit programmable counter Programmable counter consists of compare register TM6OC and binary counter TM6BC Binary counter is 8 bit up counter When the TM6CLRS flag of the timer 6 mode register TM6MD is 0 and the interrupt cycle data is written to the compare register TM6OC the timer 6 binary counter TM6BC is cleared to 0x00 Timer 6 Binary Counter TM6BC 0x03F68 7 6 5 4 3 2 1 0 TM6BC7 6 5 4 TM6BC3 TM6BC2 TM6BC1 TM6BCO 0 0 0 0 0 0 0 0 R R R R R R R R
266. 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 TAIWAN Tel 886 7 346 3815 886 7 236 8362 e Korea Sales Office Panasonic Industrial Korea Co Ltd PIKL Kukje Center Bldg 11th Fl 191 Hangangro 2ga Youngsan ku Seoul 140 702 KOREA Tel 82 2 795 9600 Fax 82 2 795 1542 220103 Printed in JAPAN
267. 7 bp1 SCSIE 1 11 Start serial transmission Transmission data TXBUFS 0x03FA8 Reception data Input to SBI3 pin b Set the P3DIR5 P3DIR3 flags of the Port 0 pin control direction register P3DIR to 1 1 and set P3DIR4 to 101 to set P35 P33 to output mode to set P34 to input mode 6 Set the SC3LNG2 0 flag of the serial mode register SC3MDO to 111 to set the transfer bit count to 8 bits Set the SC3STE flag of the SC3MDO register to 0 to disable start condition Set the SC3DIR flag of the SC3MDO register to 0 to set MSB as the first transfer bit Set the SC3CE1 flag of the SC3MDO register to 1 to set the transmission data output edge to rising and the received data input edge to falling 7 Set the SC3CMD flag of the SC3CTR register to 0 to select serial data tansmission 8 Set the SC3MST flag of the SC3MD1 register to 1 to select clock master internal clock Set the SC3SBOS SC3SBIS SC3SBTS flags of the SC3MD register to 1 to set the SBOS pin to serial data output the 5813 pin to serial data input and the SBT3 pin to serial clock I O Set the SC3IOM flag to 0 to set serial data input from the 5813 pin 9 Set the interrupt level by the SC3LV1 0 flag of the serial interrupt control register SC3ICR 10 Enable the interrupt to by setting 1 to the SCSIE flag of the SC3ICR register If the interrupt request flag 5 of the SC3ICR register is alread
268. 7 binary counter TM7BC is initialized to 0x0000 6 Select the external interrupt 0 IRQO input as the capture trigger generation source by the T7ICT1 to 0 flag of the TM7MD2 register 7 Set the T7ICEDG1 flag of the TM7MD1 register to 1 to select the rising edge as the capture trigger generation edge Also set the T7ICEDGO flag of the TM7MD2 register to 1 to enable the specify edge as the capture trigger generation source 16 bit Timer Capture 6 16 bit Timer Setup Procedure Description 8 Select the interrupt generation valid edge IRQ0ICR 0x03FE2 bp5 REDGO 1 9 Set the interrupt level IRQ0ICR 0x03FE2 bp7 6 IRQOLV1 0 10 10 Enable the interrupt IRQ0ICR 0x033FE2 bp1 IRQ0IE 1 11 Enable the capture trigger generation TM7MD2 0x03F79 bp2 T7ICEN 1 12 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 8 Set the REDGO flag of the external interrupt 0 control register IRQ0ICR to 1 to select the rising edge as the interrupt generation valid edge 9 Set the interrupt level by the IRQOLV1 to 0 flag of the IRQ0ICR register If the interrupt request flag is already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 10 Set the IRQOIE flag of the IRQ0ICR register to 1 to enable the interrupt 11 Set the T7ICEN flag of the TM7MD2 register to 1 to enable the capture trigger generation 12 Set the TM7EN flag of the TM7MD1
269. A bp6 IICSTC 0 11 Set the SC3MDO0 register Select the transfer bit count SC3MD0 0x03FA4 bp2 0 SC3LNG2 0 111 Select the start condition SC3MD0 0x03FA4 bp3 SC3STE 1 Select the first bit to be transferred SC3MDO 0x03FA4 bp4 SC3DIR 0 Select the IIC communication edge SC3MD0 0x03FA4 bp6 SC3CE1 1 12 Set the SC3MD1 register Select the transfer clock SC3MD1 0x03FA5 bp2 SC3MST 1 Control of pin function SC3MD1 0x03FA5 bp4 SC3SBOS 1 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 SC3IOM 1 13 Set the interrupt level SC3ICR 0x03FF7 bp7 6 SC3LV1 0 10 6 Set the SC3ACKS flag of the serial 3 control register SC3CTR to 1 to select receive ACK bit ACK bit is received at transmission and setup of the ACK bit level with the SC3ACKS flag is not necessary 7 Set the SC3TMD flag of the serial 3 control register SC3CTR to 0 to select NORMAL mode 8 Set the SC3CMD flag of the serial 3 control register SC3CTR to 1 to select IIC 9 Set the SC3REX flag of the serial 3 control register SC3CTR to 0 to select the transmission mode 10 Set the IICSTC flag of the serial 3 control register SC3CTR to 0 0 to initialize the start condition detection flag 11 Set the SC3LNG2 0 flag of the serial 3 mode register SC3MDO to 111 to set the transfer bit count to 8 bits Set the SC3STE flag of the SC3MDO register to 1 to disable start condition And start condition is not
270. A D buffer ANBUF 0 1 the ANST flag of ANBUF1 0x03FB6 control register 2 ANCTR2 is reset and then A D conversion complete interrupt is generated The above 3 to 4 can be set at the same time Even if the external interrupt is generated in the middle of the A D conversion operation is done as usual Also after finished the A D conversion is never be started again register ANCTRO to 0 and confirm the analog stop before changing the setup a After the A D conversion when you restart set the ANLADE of the A D converter control Operations of other than this order are not guaranteed XVI 16 Operation 16 A D Converter 16 3 3 Cautions pIl H c A D conversion can be damaged by noise easily therefore anti noise measures should be taken adequately Anti noise measures To A D input analog input pin add condenser near the Vss pins of micro controller Digital Voo Analog Vss sees c Vaer Power ANO lt to supply AN7 4 D Vss Set near the Vss Figure 16 3 2 A D Converter Recommended Example 1 E Vss Voo Vss Power to supply AN7 Figure 16 3 3 A D Converter Recommended Example 2 Set near the Vss pin Operation XVI 17 16 A D Converter 1 The input impedance R of A D input pin should
271. A D converter Normally the values of Vnge is used 1 16 Pin Description Chapter 1 Overview Name NO Other Function Function Description AN0 92 Input PA0 Analog input pins Analog input pins for an 8 channel 10 bit A D converter AN1 93 PA1 When not used for analog input these pins can be used as nor AN2 94 PA2 mal input pins AN3 95 PA3 AN4 96 PA4 AN5 97 PA5 AN6 98 6 7 99 7 DAvpp 1 D A converter power Reference power supply voltage pin for D A converter Normally DAyss 3 D A converter power used as DAypp Vpp1 2 DAvss Vss DAO 2 Output P06 Analog output Analog input pins for an 1 channel 8 bit A D converter When not used for analog input these pins can be used as nor mal input pins IRQO 27 Input P20 External interrupt External interrupt input pins IRQ1 28 P21 input pins The valid edge for IRQO to 5 can be selected with the IRQnICR IRQ2A 29 P22 register IRQ2B 82 PDO IRQ2 3 and 5 can be set at both edges at pin voltage level IRQ3A 30 P23 When not used for interrupts these can be used as normal input IRQ3B 83 PD1 pins IRQ4 31 P24 IRQ5 32 P25 KEYO 47 Input P60 8 Key interrupt input Key interrupt pins activated on input ORed condition KEY1 48 P61 A9 pins These can be set to key input pins by 2 bit with the key interrupt KEY2 49 P62 A10 control register KEYT3_1IMD KEY3 50 P63 A11 When not used for KEY input these pins can
272. A2CTR DABUSY Figure 17 1 1 D A Converter Block Diagram Overview XVII 3 17 D A Converter 17 2 D A Converter Control Registers 17 2 1 D A Converter Control Registers Following table shows the registers to control the D A converter of this LSI Table 17 2 1 D A Converter Control Registers Register Address Function DA2CTR R W D A converter control register XVII 5 DA2DR0 0x03FBF R W D A converter input data register 0 XVII 6 PODIR 0x03F30 R W Port 0 direction control register IV 8 POPLU 0x03F40 R W Port 0 pull up resistor control register IV 9 R W Readable Writable XVII 4 D A Converter Control Registers 17 D A Converter 17 2 2 D A Converter Control Register DA2C TR This is the 8 bit readable writable register that controls the D A conversion D A Converter Control Register DA2CTR D A conversion enable flag DABUSY 0 Stop D A converter operation ladder resistance OFF 1 Enable D A converter operation D A Converter Control Registers XVII 5 17 D A Converter 17 2 3 D A Converter Input Data Register This readable writable register stores the D A converter data D A Converter Input Data Register 01 DA2DR0 0x03FBF This register stores the D A converter data for channel Access XVII 6 D A Converter Control Registers 17 D A Converter 17 3 Operation
273. ADV controls address output to pins Memory areas can be externally expanded as follows ROM 0x70000 0xEFFFF 512 KB K 256 bytes 000000 0x00100 Internal RAM 14 KB 16KB Special function egister area short BANKO Y addressing space A 48 KB Internal ROM 320 KB BANK1 164 KB lt gt BANK2 164 KB Instruction code Table data BANK3 164 KB BANK4 64 BANKS 64 KB BANK6 7 64 64 gt _ gt tt tet et 4 cu BANK8 BANK9 64 64 BANK10 BANK11 64 KB 64 KB q p e lt gt 6 BANK12 164 KB BANK13 64 0xD0000 BANK14 454 KB 0xE0000 14KB TOME Mirror RAM Space p et a et P a d BANK15 64 KB Y Y MMOD pin L EXMEM flag 1 Figure 2 2 4 Memory Expansion Mode The value of internal RAM is uncertain when power is applied to it Y It needs to be initialized before used 24 Memory Space Chapter 2 CPU Basics 2 2 6 Processor Mode iw s mOOo QR ga VO I s In processor mode internal RAM and externaly expanded ROM RAM can be used Internal ROM cannot be used in this mode This mode is not available in Flash version MN101EF01M Setting MMOD pin to H sets the processor mode Memory areas can be externally expanded as follows ROM 0x04000 0x3FFFF 944 KB A 256 byles 2000000 0 00100
274. Access R W R W R W R W R W R W bp Flag Description 7 6 3 5 P3DIR5 Fais lore 3 FSDIRS co ut mode 2 P3DIR2 pp 1 P3DIR1 0 P3DIRO IV 36 Port 3 Port 3 Pull up Resistor Control Register P3PLU 0x03F43 PSPLUS P3PLU4 P3PLU3 P3PLU2 P3PLU1 Chapter 4 Ports P3PLU0 0 0 0 0 0 0 bp gt O Q O P3PLU5 P3PLU4 P3PLU3 P3PLU2 P3PLU1 P3PLU0 Flag Description 1 Added Pull up resistor selection 0 Not added Port 3 Nch Open drain Control Register P3ODC 0x03F2C Flag P3ODC5 P3ODC2 P3ODC0 At reset 0 0 0 0 Access R W R W R W R W bp O gt O Q O P30DC5 P30DC3 P30DC2 P30DCO Flag Description Nch open drain output selection 0 Push pull output 1 Nch open drain output Port 3 IV 37 4 I O Ports 4 5 3 Block Diagram Reset pR P3ODC0 R Nch open drain control K Reset P3PLUO D R Pull up resistor control K Reset R P3DIR0 D R direction control K P30 P3OUTO or R rx Port output data 1 Schmitt trigger input Port input data Serial 1 reception data input Serial 1 UART 1 transmission data output SC1MD1 SC1SBOS Figure 4 5 1 P30 Block Diagram rM Reset E
275. Arithmetic manupulation instructions ADD Dn Dm Dm Dn gt Dm 2 0011 DnDm ADD imm4 Dm 4 2 1000 00Dm lt 4 gt ADD imm8 Dm Dm imm8 Dm 412 0000 10Dm lt 8 ADDC Dn Dm Dm Dn CF 5Dm 3 2 1011 DnDm ADDW DWn DWm DWm DWn gt DWm 3 3 0101 00Dd ADDW DWn Am Am DWn gt Am 3 3 0101 10Da ADDW imm4 Am Am sign imm4 gt Am 3 2 1110 110a lt 4 gt ADDW imm8 Am Am sign imm8 Am 5 3 1110 110a lt 8 ADDW imm16 Am Am imm16 Am 7 4 0101 011a H6 ADDW imm4 SP SP sign imm4 gt SP 312 1111 1101 lt gt ADDW imm8 SP SP sign imm8 SP 4 2 1111 1100 lt 8 ADDW imm16 SP SP imm16 SP s ue 7 4 1111 1100 H6 ADDW imm16 DWm DWm imm16 5DWm 074 0101 010d H6 ADDUW Dn Am Am zero Dn gt Am 1000 1aDn ADDSW Dn Am Am sign Dn gt Am 3 1001 1aDn SUB Dn Dm when Dm Dn 5 Dm 2 1010 DnDm SUB Dn Dn Dn Dn Dn 010 0 1 2 1 1000 01Dn SUB imm8 Dm Dm imm8 Dm 3 1010 DmDm lt 8 SUBC Dn Dm Dm Dn CF Dm e eee 2 1011 DnDm SUBW DWn DWm DWm DWn DWm 0100 00Dd SUBW DWn Am Am DWn Am 3 0100 10Da SUBW imm16 DWm DWm imm16 DWm 4 0100 010d SUBW imm16 Am Am imm16 Am 0100 011a MULU Dn Dm Dm DnDWk 3 8 1111 111D DIVU Dn DWm DWm Dn DWm l DWm h 3 9 1110 111d Dn Dm Dm Dn PSW 52 0010 DnDm imm8 Dm Dm imm8 PSW
276. BI0 SBO0 connection SCOMD1 SCOIOM Function Port Serial data input Transfer clock input Transfer clock input output output SCOMD1 SCOSBO SCOMD1 SCOSBIS SCOMD1 SCOSBIS S Style Push pull Nch open Push pull Nch open drain drain POODC POODC2 Input mode Output mode Input mode PODIR PODIRO PODIR PODIR2 PSDIR P9DIR2 P9DIR P9DIRO Pull up setup Added Not added Added Not added POPLU POPLU2 P9PLU P9PLU2 Operation 11 3 2 Setup Example B Transmission Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown Table 11 3 12 shows the conditions at transmission reception Chapter 11 Serial interface 0 Table 11 3 12 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item Set to Serial data input pin Independent 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Output edge Rising edge Clock Clock master Clock source Clock source 1 8 dividing fs 2 Not div ided by 8 Used pins A SBTO SBOO pin style Nch open drain interrupt SBTO pin pull up resistor Added 5800 pin pull up resistor Added serial 0 communication complete Enable SBOO output after last data output 1 fix An example setup procedure with a description of each step is shown below Setu
277. BO3 Output after Last Bit Data Output Hold Time without start condition SC3FDC1 flag SC3FDCO flag 2 0 0 Fixed to 1 High output 1 0 Fixed to 0 Low output 0 1 Hold last data 1 1 Reserved XIV 20 Operation 14 Serial Interface 3 B Transmission Timing at master at slave Tmax 25T T T f f Tmax 2T a lt I U Clock SBT3 pin Output data SBO3 pin Transfer bit counter SC3BSY Write data to TXBUF3 Interrupt SC3IRQ Figure 14 3 6 Transmission Timing Falling edge Start condition is enabled at master at slave Tmax 3 5T T f f 2 Clock SBT3 pin Output data SBOS pin Transfer bit counter SC3BSY Write data to TXBUF3 Interrupt SC3IRQ Figure 14 3 7 Transmission Timing Falling edge Start condition is disabled Operation XIV 21 14 Serial Interface 3 at master at slave Tmax 25TT J T f 2 Clock x SBT3 pin Output data SBO3 pin Transfer bit counter SC3BSY Write data to TXBUF3 7 Interrupt SC3IRQ Figure 14 3 8 Transmission Timing Rising edge Start condition is enabled at master at slave Tmax 3 5T T 2 Ss D Sau Clock SBT3 pin Output data SBO3 pin Transfer bit counter SC3BSY Write data to 7 Interrupt SC3IRQ Figure 14 3 9 Transmis
278. BOO pin Transfer bit count SCORBSY Data set to TXBUFO Interrupt SCOTIRQ Figure 11 3 11 Reception Timing at rising edge start condition is disabled XI 24 Operation 11 Serial interface 0 Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY Interrupt SCOTIRQ Figure 11 3 12 Reception Timing at falling edge start condition is enabled At master Tmax 3 5T T Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY Data set to TXBUFO 7 Interrupt SCOTIRQ Figure 11 3 13 Reception Timing at falling edge start condition is disabled Operation XI 25 11 Serial interface 0 B Transmission Reception Timing When transmission and reception are operated at the same time set the SCOCEI flag of the SCOMDO register to 0 or 1 Data is received at the opposite output edge of the transmission data so that the input edge of the received data should be the opposite output edge of the transmission data from the other side Also in the case transmission reception is done with the start condition opposite of the communication should be done with the same condition to communicate properly SBTO pin Data is received at the rising edge of clock SBIO pin Data is output at the falling edge of clock Figure 11 3 14 Transmission Reception Timing Reception at rising edge Transmission a
279. Block Diagram Reset Pull up resistor 7 ESPLUI contorol WEK R 8 DIR VO direction PSPIRI control WEK R I X g 1 S P5OUT1 Port output data grt Q SQU o WEK R rti x BIN Schmitt trigger input Port input data lt J R Address output External extension output contorl IV 52 Port 5 Figure 4 7 2 P51 Block Diagram P50 P51 Chapter 4 I O Ports PLU2 Pull up resistor 5 gt Wek R p DIR direction prq PSDIR2 control WEK R ely M F P52 4 Port output data ort D dPSOUT2 Schmitt trigger input 2 Port input data lt lt U R Address output External extension output contorl Figure 4 7 3 P52 Block Diagram Reset BEI Pull up resistor SPEUS gt contorol Wek R Reset VO direction vpn PSDIR3 2 M n control WEK R lt X 5 kwa 5 P5OUT Port output data 7 q SOUTS 2j M o WEK R ki X C Pn Schmitt trigger input Port input data lt PSINS WwW R Address output External extension output contorl Figure 4 7 4 P53 Block Diagram Port 5 IV 53 4 I O Ports
280. C POODOO P ODC P9ODC0 Output mode PODIR PODIRO P9DIR P9DIR0 Pull up setup Added not added E POPLU POPLUO P9PLU P9PLUO XI 50 Operation 11 Serial interface 0 B Pin Setup with 2 channels at reception Table 11 3 21 shows the pins setup at UART serial interface reception with 2 channels TXDO RXDOpin Table 11 3 21 UART Serial Interface Pin Setup with 2 channels at reception Setup item Data output pin Data input pin TXDOA pin TXDOB pin RXDOA pin RXDOB pin Port pin P90 P01 P91 Port pin selection Select the used pin A B SCSEL SCOSEL Serial data input selection TXDO RXDO pin independent SCOMD1 SCOIOM Function Port Serial data input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Input mode PODIR PODIR1 P9DIR P9DIR1 Pull up setup XI 51 11 Serial interface 0 B Pin Setup with 1 channel at reception Table 11 3 22 shows the pin setup at UART serial interface reception with 1 channel TXDO pin The RXDO pin in not used so can be used as a port Table 11 3 22 UART Serial Interface Pin Setup with 1 channel at reception Setup item Data output pin Data input pin TXDOA pin TXDOBpin RXDOA pin RXDOB pin Port pin P90 P01 P91 Port pin selection Select the used pin A B SCSEL SCOSEL Serial data input selectio
281. C1 control register 0 XVIII 7 0X03FD1 R W ATC1 control register 1 XVIII 8 AT1TRC OXOSFD2 R W ATC1 transfer data counter XVIII 9 AT1MAPOL OX03FD3 R W ATC1 memory pointer 0 lower 8 bits XVIII 10 AT1MAPOM OX03FD4 R W ATC1 memory pointer 0 middle 8 bits XVIII 10 AT1MAPOH OXOSFD5 RAN ATC1 memory pointer 0 upper 4 bits XVIII 10 AT1MAP1L OXOSFD6 RAN ATC1 memory pointer 1 lower 8 bits XVIII 11 0X03FD7 R W ATC1 memory pointer 1 middle 8 bits XVIII 11 1 1 0X03FD8 R W ATC1 memory pointer 1 upper 4 bits XVIII 11 R W Readable Writable XVIIl 6 Control Registers 18 Automatic Transfer Controller ATC1 Control Register 0 AT1CNT0 0x03FD0 Flag AT1ACT ATIMD3 AT1MD2 1 1 Reserved At reset 0 0 0 0 0 0 Access Description Increment control flag for memory pointer 0 0 Increment depending on transfer mode 1 Disable incrementing of memory pointer 0 ATC1 software activation flag AT1ACT 0 Do not activate ATC1 1 Activate ATC1 ATC1 data transfer mode 0000 Transfer mode 0 0001 Transfer mode 1 0010 Transfer mode 2 0011 Transfer mode 3 0100 Transfer mode 4 0101 Transfer mode 5 0110 Transfer mode 6 0111 Transfer mode 7 1000 Transfer mode 8 1001 Transfer mode 9 1010 Transfer mode A 1011 Transfer mode B 1100 Transfer mode C
282. C2REX flag of the serial 2 control register SC2CTR to 0 to select the transmission mode 9 Set the IICSTC flag of the serial 2 control register SC2CTR to 0 0 to initialize the start condition detection flag 10 Set the SC2LNG2 0 flag of the serial 2 mode register SC2MD0 to 111 to set the transfer bit count to 8 bits Set the SC2STE flag of the SC2MDO register to 0 to disable start condition And start condition is not added over the second communication Set the SC2DIR flag of the SC2MDO register to 0 to set MSB as the first bit to be transferred In IIC communication set the SC2CE1 flag of the SC2MD O register to 1 11 Set the SC2MST flag of the SC2MD 1 register to 1 to select clock master internal clock In communication do not select external clock Set the SC2SBOS SC2SBIS SC2SBTS flags of the SC2MD1 register to 1 to set the SDA2 pin the SBO2 pin to serial data output the SBI2 pin to serial data input and the SCL2 pin the SBT2 pin to serial clock O Set the SC2IOM flag to 1 to set serial data input from the SDA2 pin the SBO2 pin 12 Set the interrupt level by the SC2LV1 0 flag of the serial 2 interrupt control register SC2ICR Operation XIII 47 13 Serial Interface 2 Setup Procedure Description 13 Enable the interrupt SC2ICR 0x03FF6 bp1 SC2IE 1 14 Start serial transmission Start serial transmission Confirm that SCL2
283. CharactepIStIcSu a nh ee teen een ER Re A I 25 1 5 4 A D Converter Characteristics atieeg nette eene edet ieri denis 1 28 1 5 5 D A Converter CharacterISfI s a Rm Nan eren enne tree 1 29 1 6 Package Dimensions eem epe ended e a ep mee e npe 1 30 1 7 Cautions for Circuit 1 31 I I General meme tee neo RP D suu pa Bs I 31 1 7 2 Unused pins eire e aen RERO Ren ee ee I 32 13 3 Power Supply e eo RERO spe d ED I 34 1 7 4 Power Supply Circuit c tte I 35 Cliapter E s II 1 21 OVERVIEW c see e Aet ep ee eee dame 2 ZAM Block reet rte Poet ede ed it dede bere 3 2 2 CPU Control Registers roto nee Pee Re ette ege II 5 2 1 3 Instruction Execution II 6 2 T A Pipeline Process sis a ite tem REED n Qp u an RUE REDIERE 7 21 59 Registers for Address otio a A OAAS TS II 8 2 1 6 Registers for Dali ue ent Ob e e EE GERI URS 9 2 1 7 Processor Status Word tm rettet een S II 10 21 8 pU e due e e UHR E II 12 2 1 9 Addressing Modes tete pe ete b RE Ee he eiie n II 13 Del LO Machine Clock eae eb paypis aahh II 15 2 2 Memory Space deep REB Renee II 16 Contents 2 gt 2 2 Memory Mode uns l aa
284. Control Register 0x03F1F R W Port 7 Synchronous Output Control Register 0x03F2F R W Port 7 Synchronous Output Event Selection Register 0x03F4B R W Pull up Pull down Resistor Selection Register 0x03F0E Address Output Control Register R W Readable Writable Port 7 Output Register P7OUT 0x03F 17 P7OUT7 P7OUT6 P7OUT5 P7OUT4 7 P7OUT2 P7OUT1 P7OUTO x x x x x x x x bp Description Output data 0 Output L VSS level 1 Output H VDD level S O Q O Port 7 IV 67 4 I O Ports Port 7 Input Register P7IN 0x03F27 bp Flag Description 7 P7IN7 6 P7IN6 E Input data 0 Pin is L VSS level 3 P7IN3 1 Pin is H VDD level 2 P7IN2 PINIS EWDD level 1 P7IN1 0 P7IN0 Port 7 Direction Control Register P7DIR 0x03F37 IV 68 Flag P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O gt O Q O Port 7 P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIR0 I O mode selection 0 Input mode 1 Output mode Chapter 4 I O Ports Port 7 Pull up Pull down Resistor Control Register P7PLU 0x03F47 P7PLU7 P7PLU6 P7PLU5 7 P7PLU3 P7PLU2 P7PLU1 P7PLUO 0 0 0 0 0 0 0 0 bp Fla
285. DOUT7 a E Schmitt trigger input Port input data lt 1 PDIN7 lt U R Figure 4 13 8 PD7 Block Diagram Port D IV 113 4 I O Ports 4 14 Real Time Output Control P10 P12 P14 have the real time output function that can switch pin output at the falling edge event of the exter nal interrupt 0 pin P20 IRQ0 The real time control is the function that can change the timer output signal PWM output timer pulse output remote control career output synchronized with the external event without setting the program Switchable out put values at the event generation are 0 1 Hi impedance Hi z 4 14 1 Registers Table 4 14 1 shows the real time output control registers of port 1 Table 4 14 1 Real Time Outpt Control Registers Register Address Function P1OUT 0x03F11 Port 1 output register P1DIR 0x03F31 Port 1 direction control register P1PLU 0x03F41 Port 1 pull up resistor control register P1OMD 0x03F2B Port 1 output mode register P1CNTO OxOSF7E Port 1 real time output control register IV 114 Real Time Output Control Chapter 4 I O Ports 4 14 2 Operation O s Issx n Real Time Output Pin Setup The real time output pin setup should be done at the port 1 output control register PICNTO Selectable pins are P10 P12 P14 and each of them can be specified by each bit The output mode should be selected at the port 1 direction control r
286. Data is output at the falling edge of the clock Figure 13 3 14 Transmission Reception Timing Reception Rising edge Transmission Falling edge SBT2 pin Data is input at the rising edge of the clock SBI2 pin Data is output at the falling edge of the clock SBO2 Figure 13 3 15 Transmission Reception Timing Reception Falling edge Transmission Rising edge Operation XIII 25 13 Serial Interface 2 B Communication in STANDBY mode This serial interface is capable of slave reception in STANDBY mode You can return the CPU operation from STANDBY mode to NORMAL mode using communication end interrupt SC2IRQ which is generated after the slave reception In STANDBY mode continuous reception is desabled after data of transfer bit count set by SC2LNG2 0 flags of the SC2MDO register is received Read out the received data from transmission reception shift register SC2TRB after returning to NORMAL mode In STANDBY mode reception with start condition is not available thus disable start condition And set dummy data to tramsmission data buffer TXBUF2 before transition to STANDBY mode NORMAL mode STANDBY mode NORMAL mode Oscillation stabilization T f f waittime Clock SBT2 pin Input pin 5812 5802 pin Transfer bit counter SC2BSY 4 Write data to TXBUF2 Interrupt SC2IRQ Figure 13 3 16 Reception Timing Rising edge Start condition
287. Description Serial data input selection 0 Data input from SBI2 1 Data input from SBO2 SDA2 SC2SBTS SBT2 pin function 0 Port 1 Transfer clock input output SC2SBIS Serial input control 0 1 input 1 Serial data input SC2SBOS SBO2 SDA2 pin function 0 Port 1 Serial data output SC2MST Clock master slave selection 0 Slave 1 Master XIII 8 Control Registers 13 Serial Interface 2 Serial interface 2 Mode Register 3 SC2MD03 0x03F98 7 6 3 2 1 0 SC2FDC1 SC2FDC0 SC2PSCE SC2PSC2 SC2PSC1 SC2PSC0 0 0 0 0 0 0 SC2FDC1 SC2FDC0 Description SBO2 output selection after transfer of last data 00 Fixed to 1 High output 01 Hold last data 10 Fixed to O Low output 11 Reserved SC2PSCE Prescaler count control 0 Disable the count 1 Enable the count SC2PSC2 SC2PSC1 SC2PSCO Clock selection 000 fosc 2 fosc 4 fosc 8 001 fosc 4 fosc 8 fosc 16 010 fosc 16 fosc 32 fosc 64 011 fosc 32 fosc 64 fosc 128 100 fs 2 101 fs 4 110 timer 2 output 111 timer 3 output 1 This depends on SCCKSEL5 flag and SCCKSEL4 flag of SCCKSEL register refer to table 13 2 9 serial clock cycle switching control register Control Registers XIII 9 Chapter 13 Serial Interface 2 Serial interface 2 Status Register SC2STR 0x03F99
288. E TORRE REO IV 34 452 Register s enam agde ame IV 35 43 3 Block Diagrams uc RR memi terti R E ttes IV 38 iu d IV 41 4 6 T Description sedeo SSS a IV 41 AO MEER IV 42 4 6 3 Block Diagram etae en o eO DIRE ET RU ERRORI De IV 46 p ep ee e Up pt epa i e eH E PU Dt e EO Fuit IV 48 4 11 Descriptions e Eee aee e ERIT Ue IV 48 CERAM a En IV 49 4 7 3 Block Diagram ite eee ee He eR eas IV 52 4 8 esha oe eee Ana ooa dieci IV 56 4 8 1 Description oH RUE pe ie pe t Ie UR es IV 56 4 8 2 Registers o ne ape eot ue D RED EE IV 58 4 8 3 Block Di gr tn i eee co Re e trt ee IV 61 Contents 4 gt 4 9 Port 7 NESSUN UIDES De EE IV 65 4 9 1 ener ete e ED I D IV 65 4 9 2 Registers eto em Donee oet e Dur IV 67 49 3 Block aeger deb eet rU IV 72 4 10 Port 8 reo pera eti m e ah IV 80 2 10 T Description dero Serre e he enit p ede e e tor cede IV 80 4 10 2 Registers Gee EB IEEE IV 81 4 10 3 Block Diagratm eet em ener ERE ge e Op IV 84 ATT Pott O TV 89 4 11 1 Description ss nire t DROPS D eee et IV 89 ALVA 2 Registers EE IV 90 4 11
289. EDGDT selects interrupt edges of IRQ2 and IRQ3 Interrupts are gen erated at both edges or at single edge The external interrupt control register IRQ2ICR IRQ3ICR specifies whether interrupts are generated Table 3 3 5 Both Edges Interrupt Control Register EDGDT 0x03F1E bp 7 6 5 4 3 2 1 0 Flag EDGSEL5 EDGSEL3 EDGSEL2 At 0 0 0 reset Access R W Description EDGSEL5 IRQ5 both edges interrupt selection 0 Programmable active edge interrupt selection 1 Both edges interrupt selection EDGSEL3 IRQ3 both edges interrupt selection 0 Programmable active edge interrupt selection 1 Both edges interrupt selection EDGSEL2 1 2 both edges interrupt selection 0 Programmable active edge interrupt selection 1 Both edges interrupt selection Ill 56 External Interrupts Key Interrupt Control Register KEYT3_1IMD The key interrupt control register selects if key interrupt is accepted and external interrupt IRQ4 is accepted Also this register assigns KEY interrupt input pin to key interrupt in 2 bit unit Table 3 3 6 Key Interrupt Control Register 1 KEYT3_1IMD 0x03F3E bp 7 6 5 4 3 2 1 0 Flag KEYTSSEL KEYTS __ _ _ _ 1EN3 1EN2 1EN1 1ENO At 0 0 0 0 0 reset Access R W KEYTSSEL Description IRQ4 interrupt source selection 0 External in
290. EN and the bit 1 RC1EN of the ROM correction control register RCCTR to 1 After the main program is started the instruction fetched address and the set address to the ROM correction address setting register RCnAP are always compared then once they are matched program counter indirectly The second program to be corrected internal ROM The head address of the correction Address Data the set value of RC1AP 108FC 85 sub d1 di 108FDr Aom mov 11 90 108FF 58 mov 90 a0 10900 1 addw 1 a0 109011 A081 mov _Msyscom_edge 0 The address for recover The second correct program internal RAM The head address of the correction program Data the set value of RC1V 00680 A041 14 40 006 58 90 a0 006 3920090 jmp 10900 The address for recover branches to the address in RAM area that are stored to the RC vector table RCn V The correction program in RAM area is executed Program counter recovers to the program in ROM area ROM Correction Chapter 2 CPU Basics 2 4 Bus Interface 2 4 1 Bus Controller The MNIOIE series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation There are four such buses ROM bus RAM bus peripheral expansion bus and external expansion bus They con nect to the internal ROM internal RAM internal peripheral circuits and ex
291. ERS V 46 5 9 Serial Transfer Clock Output V 47 5 9 1 47 5 9 2 Setup Example eoi eate du reed HG PERI RE V 48 5 10 Simple Pulse Width Measurement eese ener eere nennen nennen treten trennt V 49 5 10 T Operation cl nee m veel ele Ral Ai ee V 49 3102 Setup Exanmple u gunu isa eoe dig buie edd V 50 DAD Cascade Connection eei ete eec tg ler eee et eene V 52 LL Ji Operations oui L S s S A a S V 52 23 12 Setup Example x5 ree V 54 Chapter 6 TO bit aes TEE E VI 1 6 TO V6SPVISWS usyananpaq a VI 2 6 1 l BUN Les BLOY a ee vg SE i eee VI 2 6 12 Block Diagram Ub d eie ie P EE HE e UR RES eet VI 3 6 2 Control RegiStets ete niit nee em iro id eic VIA 6 21 Registers spare E CO aep teqq eee oS VIA 6 2 2 Programmable Timer Registers VI 5 6 2 3 Timer Mode ResISterS eee e ent ce eque pepe Hn VI 8 6 3 OperatioD iter rente de Ree ete PO Ot e HER p VI 12 63 1 Operation wie ke ek eke int nese en qup VI 12 6 3 2 Setp EXammple sess fs ee diete e en ko Re e e iie sette VI 15 Contents 6 6 4 16 bit Event Count 3 ERREUR VI 17 6 4 T Operation ie Dette ete iri n eb eO Re egre rto he ined VI
292. Ee des II 16 2 2 2 duum C i ipa u a 17 223 RAM maet e oes ee 21 2 2 4 eie EE eee tee Ee II 23 2 2 3 Memory Expansi on Mode II 24 2 2 6 Processor ee n DERE REOR II 25 2 2 7 Special Function o eet dte dei Heer eere II 27 2 3 ROM eet ERR a taber e cei eed etes II 28 2 3 1 QVerVIeW coconut ee rete DOO oH OU PEU EE Mcr eere p II 28 2 3 2 Correction Sequence eee tet ee tee UE pu II 28 2 3 3 ROM Correction Control 2200000 II 30 2 3 4 ROM Correction Setup Example sess eee enne neret II 34 2 4 Bus Interface u ee RR ere te EA reis rep estate ed Da ee eee eee II 37 DAT BUS E eene II 37 2 4 2 Control Registers i ssepe ape Rie gae RE RR II 38 2 4 3 Fixed Wait Cycle eter ttti II 41 24 4 Handshake he pF p EE tb EU PES II 41 2 4 5 External Memory Connection Example sess II 43 2 5 Standby Function ete ee ia ER ea II 44 2 5 NOVEN IE 44 2 5 2 CPU Mode Control II 46 2 5 3 Transition between SLOW and NORMAL eene ens II 47 2 5 4 Tr
293. F4F bp3 SC3SEL 0 4 Control of pin type 0x03F2C bp5 3 PSODCS 3 1 1 P3PLU 0x03F49 bp5 P3PLU5 3 1 1 1 Set the SC3PSCE flag of the SC3MD3 register to 1 to select prescaler operation 2 Set the SC3PSC2 0 flag of the SC3MD3 register to 100 to select fs 2 for clock source 3 Set the SC3SEL flag of SCSEL register to 0 to select I O pin to A port 3 4 Set the PSODC5 P3ODCS3 flags of the PSODC register to 1 1 to select N ch open drain for the SBO3 SBT3 pin type Set the PSODC5 P3ODC3 flags of the P3PLU register to 1 1 to add pull up resistor XIV 32 Operation 14 Serial Interface 3 Setup Procedure Description 5 Control of pin direction P3DIR 0x03F33 bp5 3 P3DIR5 3 101 6 Set the SC3MDO register Select the transfer bit count SC3MDO 0x03FA8 bp2 0 SC3LNG2 0 111 Select the start condition SC3MDO 0x03FA8 bp3 SCSSTE 0 Select the first bit to be transferred SC3MDO 0x03FA4 bp4 SC3DIR 0 Select the transfer edge SC3MDO 0x03FA8 bp6 SC3CE1 1 7 Set the SC3CTR register SC3CTR 0x03FAA bp2 SC3CMD 0 8 Set the SC3MD1 register Select the transfer clock SC3MD1 0x03FA9 bp2 SC3MST 1 Control of pin function SC3MD1 0x03FA5 bp4 SC3SBOS 1 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 5 0 9 Set the interrupt level SC3ICR 0x03FF7 bp7 6 SC3LV1 0 10 10 Enable the interrupt SC3ICR 0x03FF
294. FA4 Serial interface 3 mode register 0 SC3MD1 OxOSFA5 Serial interface 3 mode register 1 SC3MD3 0x03FA6 Serial interface 3 mode register 3 SC3STR 0x03FA7 Serial interface 3 status register SC3TRB 0x03FA8 Serial interface 3 transmission reception shift register TXBUF3 0x03FA9 Serial interface 3 transmission data buffer SC3CTR OxOSFAA Serial interface 3 control register SCSEL 0x03F4F Serial pin switching control register P3ODG OxOSF2C Port 3 N ch open drain control register P3DIR 0x03F33 Port 3 direction control register P3PLU 0x03F49 Port 3 pull up control register P9ODG 4 Port 9 open drain control register P9DIR 0x03F39 R W Port 9 direction control register IV 91 P9PLU 0x03F49 R W Port 9 pull up control register IV 92 SC3ICR OxOSFF7 R W Serial interface 3 interrupt control register III 41 SCCKSEL 0x03F8E R W Serial clock cycle switching control register XIII 13 R W Readable Writable R Readable Control Registers XIV 5 14 Serial Interface 3 14 2 2 Data Buffer Register Serial interface 3 has a 8 bit serial data buffer register for transmission Serial Interface Transmission Data Buffer TXBUF3 0x03FA9 1 0 TXBUF30 7 6 5 4 3 2 TXBUF37 TXBUF36 TXBUF35 TXBUF34 TXBUF33 TXBUF32 TXBUF31 X Access 14 2 3 Data Register Serial interface 3 has a 8 bit serial data register Serial Interface Transm
295. Flag SCCKSEL SCCKSEL 6 SCCKSEL SCCKSEL 5 4 At reset 0 0 0 Access SCCKSEL7 SCCKSEL6 Description Serial 3 clock fosc cycle switching 00 fosc 01 fosc 2 10 fosc 4 11 Reserved SCCKSEL5 SCCKSEL4 Serial 2 clock fosc cycle switching 00 fosc 01 fosc 2 10 fosc 4 11 Reserved Table 14 2 2 SCCKSEL bp5 SCCKSEL bp5 Serial 2 clock fosc selection SC3PSC2 SC3PSC1 SC3PSCO 0 fosc 2 fosc 4 fosc 16 fosc 32 fosc 4 fosc 8 fosc 32 fosc 64 fosc 8 fosc 16 fosc 64 fosc 128 Control Registers XIV 18 14 Serial Interface 3 14 3 Operation Serial interface 3 is used as both clock synchronous single master IIC serial interface 14 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 14 3 1 shows the activation source for communication At master a transfer clock is generated by setting data to the transfer data buffer TXBUF3 or by enabling start condition Signals input from SBT3 pin inside serial interface are masked to prevent operating errors by noise except during communication This mask is automati cally released by setting data to TXBUF3 access to the TXBUF3 register or enabling start condition to the data input pin Therefore at slave communication set data to TXBUF3 or input st
296. Input some 10 kQ Input Pin Figure 1 7 1 Unused Pins only for input Current 4 Through Current Pch Input Pin Input Nch 0 3 Input Voltage 3 V Input Inverter Characteristics Input Inverter Organization Figure 1 7 2 Input Inverter Organization and Characteristics 1 32 Cautions for Circuit Setup Chapter 1 Overview Unused Pins for Unused I O pins should be set according to pins condition at reset If the output is high impedance Pch Nch transistor output off at reset to stabilize input set some 10 kQ resistor to be pull up or pull down If the output is on at reset set them open Pins used as both LCD and port pins should be set to open to be used as LCD output pins Output Control Output Control some 10 Output OFF Output OFF Data Data some 10 Input Output OFF Output OFF some 10 kQ Data some 10 kQ Figure 1 7 3 Unused Pins high impedance output at reset Cautions for Circuit Setup 1 33 1 Overview 1 7 3 Power Supply Eu s B The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on If this order is reversed the destruction of micro controller by a large current flow could be occurred Input Input Protection Resistance Forward current generates N VDD Figure 1 7 4 Vpp and Input Pin Voltage B The Relation between Vpp and Re
297. Internal RAM 14 16 KB I 128 bytes 48 64 bytes gt lt BANK1 164 BANK2 4 64 BANKS 164 BANK4 64 KB BANKS 164 KB 0x60000 External expansion expansion BANK6 464 KB memory area ROM RAM 944 KB 0x70000 BANK7 164 KB il i tt op tt BANKS 64 0 80000 54 BANK10164 11 64 KB 4 P 12 164 KB BANK13 64 KB lt gt 4 BANK14 454 KB 14 KB BANK15 64 KB OxF3800 Y Y OxFFFFF gt lt i gt tt et et d d o et o od se MMOD pin L EXMEM flag don t care Figure 2 2 5 Memory Expansion Mode Memory Space II 25 2 CPU Basics 1 Processor mode is not available in Flash version MN101EF01M The value of internal RAM is uncertain when power is applied to it Y It needs to be initialized before used 26 Memory Space Chapter 2 CPU Basics Special Function Registers 2 2 7 The MNIOIE series locates the special function registers I O spaces at the addresses 0x03F00 to 0x03FFF in memory space The special function registers of this LSI are located as shown below Ionuoo 1dnuueju YOILOLV 3917958 3914795 39695 991298 391105 9919105 9911098 3913095 821020 1 981 HOI9A L YOIOWL
298. KB of RAM and 320 KB of ROM A A 40x00000 RAM short 256 bylesy addressing area _ 0x00100 Data Internal RAM 14 KB 16 KB 0x03800 li bytes 0 03 00 A0x03F00 36 bylesy 128 bytes 48 KB BANK1 64 KB lt gt lt Internal ROM 320 KB BANK2 64 KB Instruction code 64 Table data BANK4 4 64 5 64 BANK6 64 KB 7 BANK8 64 KB lt gt v84 KB BANK9 64 10 gt P4 et et 4 et 4 BANK11 164 KB BANK1 12 13 Y ey BANK14 P ey Mirror RAM space BANK15 64 KB MMOD pin L Y Y EXMEM flag 0 Figure 2 2 3 Single chip Mode It needs to be initialized before used 1 The value of internal RAM is uncertain when power is applied to it Memory Space 23 2 CPU Basics 2 2 5 Memory Expansion Mode llpiio gt a ay i i x r The MN10IE series can connect external ROM RAM and external devices for operation in memory expansion mode This is the mode to expand to external memory while using internal ROM and RAM The memory expansion mode is set by assigning EXMEM flag bp4 of the memory control register MEMCTR on single chip mode The address expansion control register EX
299. LILI 1Hz 1s Figure 7 3 1 Waveform of TM6BC Register bp1 Timer 6 VII 10 8 bit Free running Timer 7 Time Base Timer Free running Timer Count Timing of Timer Operation Timer 6 Binary counter counts up with the selected clock source as a count clock Count clock TM6CLRS flag Compare register Binary counter Interrupt request flag Figure 7 3 2 Count Timing of Timer Operation Timer 6 1 When any data is written to the compare register as the TM6CLRS flag is 0 the binary counter is cleared to 0x00 2 Even if any data is written to the compare register as the TM6CLRS flag is 1 the binary counter is not changed 3 When the binary counter reaches the value of the compare register as the TM6CLRS flag is 1 an interrupt request flag is set at the next count clock 4 When an interrupt request flag is set the binary counter is cleared to 0x00 and restarts the counting 5 Even if the binary counter reaches the value of the compare register as the TM6CLRS flag is 0 no interrupt request flag is set 8 bit Free running Timer VII 11 7 Time Base Timer Free running Timer When fx is used to the clock source the binary counter should be cleared before starting the Y timer operation Also when 0x00 is set to the compare register the synchronous fx should be used lt When the binary counter reaches the value in the compare
300. LU3 1 1 Set the SC2PSCE flag of the SC2MD3 register to 1 to select prescaler operation 2 Set the SC2PSC2 0 flag of the SC2MD3 register to 100 to select fs 2 for clock source 3 Set the POODC5 P0ODC3 flags of the POODC register to 1 1 to select N ch open drain for the SBO2 SBT2 pin type Set the POODC5 POODC3 flags of the POPLU register to 1 1 to add pull up resistor XIII 30 Operation 13 Serial Interface 2 Setup Procedure Description 4 Control of pin direction PODIR 0x03F30 bp5 P0DIR5 1 bp4 P0DIR4 0 bp3 PODIR3 1 5 Set the SC2MDO register Select the transfer bit count SC2MDO 0x03F96 bp2 0 SC2LNG2 0 111 Select the start condition SC2MDO 0x03F96 bp3 SC2STE 0 Select the first bit to be transferred SC2MDO 0x03F96 bp4 SC2DIR 0 Select the transfer edge SC2MDO 0x03F96 bp6 SC2CE1 1 6 Set the SC2CTR register SC2CTR 0x03F9C bp2 SC2CMD 0 7 Set the SC2MD1 register Select the transfer clock SC2MD1 0x03F97 bp2 SC2MST 1 Control of pin function SC2MD1 0x03F97 bp4 SC2SBOS 1 bp5 SC2SBIS 1 bp6 SC2SBTS 1 bp7 SC21OM 0 8 Set the interrupt level SC2ICR 0x03FF6 bp7 6 SC2LV1 0 10 9 Enable the interrupt SC2ICR 0xO3FF6 bp1 SC2IE 1 10 Start serial transmission Reception data Input to SBI2 pin Transmission data TXBUF2 0x03F9B 4 Set the PODIR5 PODIR3 flags of the Port 0 p
301. LVO TM1IE TM1IR At reset 0 0 0 0 Access R W Description TM1LV1 Interrupt level flag TM1LV0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers III 27 Chapter 3 Interrupts Timer 2 Interrupt Control Register TM2ICR The timer 2 interrupt control register TM2ICR controls interrupt level of timer 2 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 11 Timer 2 Interrupt Control Register TM2ICR 0x03FEA bp 7 6 5 4 3 2 1 0 Flag TM2LV1 TM2LVO TM2IE TM2IR At reset 0 0 0 0 Access R W Description 2 1 Interrupt level flag 2 0 This 2 bit sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated III 28 Control Registers 3 Interrupts Timer 3 Interrupt Control Register TM3ICR The timer 3 interrupt control register TM3ICR controls interrupt level of timer 3 interrupt
302. M Correction Address 1 Setting Register lower 8 bits RC1APL 0 0 bp 7 6 5 4 3 2 1 0 Flag RC1APL7 RC1APL6 RC1APL5 RC1APL4 RC1APL3 RC1APL2 RC1APL1 RC1APLO Atreset 0 0 0 0 0 0 0 0 Access R W Table 2 3 6 ROM Correction Address 1 Setting Register middle 8 bits RC1APM 0x03FC4 bp 7 6 5 4 3 2 1 0 Flag RC1APM7 RC1APM6 RC1APM5 RC1APM4 RC1APM3 RC1APM2 RC1APM1 RC1APMO Atreset 0 0 0 0 0 0 0 0 Access R W ROM Correction 1 31 2 CPU Basics Table 2 3 7 ROM Correction Address 1 Setting Register upper 2 bits RC1APH 0x03FC5 bp 7 6 5 4 3 2 1 0 Flag 5 RC1APH3 RC1APH2 RC1APH1 RC1APHO Atreset 0 0 0 0 Access R W ROM Correction Address 2 Setting Register RC2AP Table 2 3 8 ROM Correction Address 2 Setting Register lower 8 bits RC2APL 0xO3FC6 bp 7 6 5 4 3 2 1 0 Flag RC2APL7 RC2APL6 RC2APL5 RC2APL4 RC2APL3 RC2APL2 RC2APL1 RC2APLO Atreset 0 0 0 0 0 0 0 0 Access R W Table 2 3 9 ROM Correction Address 2 Setting Register middle 8 bits RC2APM 0x03FCE7 bp 7 6 5 4 3 2 1 0 Flag RC2APM7 RC2APM6 RC2APMS5 RC2APM4 RC2APM3 RC2APM2 RC2APM1 RC2APMO Atreset 0 0 0 0 0 0 0 0 Access R W Table 2 3 10 ROM Correction Address 2 Setting Register upper 2 bits RC2APH 0x0
303. M1IO input 21 input input input TMBIO input P10 P11 P12 P13 P14 PD2 P15 PD3 Synchronous Synchronous Synchronous Synchronous Synchronous Synchronous TMOIO input TM11O input TM2IO input TMSIO input input TMBIO input 5 8 bit Timers lt When the binary counter is stopped even any value is written to the compare register it might not be cleared To clear the binary counter definitely any value should be written to the compare register after the synchronous TMnIO input is selected When the TMnIO input is selected for count clock source and the value of the timer n binary counter is read out during operation incorrect value at count up may be read out To prevent this use the event count by synchronous TMnIO input as the following page When the event input TMnIO input is used clear the binary count before the timer tion Also when 0x00 is set to the compare register use the event count by the synchronous TMnIO input as the following page f CPU can be recovered from STOP mode by the timer interrupt only at the TMnIO input selec tion When TMnIO input is used at STOP mode fs should be selected for the count clock and set the value to TMnOC then select TMnIO input 8 bit Event Count V 33 5 8 bit Timers V 34 Count Timing of Synchronous TMnIO Input Timers 0 1 2 3 4 and 5
304. M1LV1 to 0 flag of the timer 1 interrupt control register TM1ICR If any interrupt request flag may be already set clear all request flags Chapter 3 3 1 4 Interrupt Flag Setup Cascade Connection 5 8 bit Timers Setup Procedure Description 9 Enable the upper timer interrupt TM1ICR 0x03FE9 TM1IE 1 10 Start the upper timer operation TM1MD 0x03F55 bp3 TM1EN 1 11 Start the lower timer operation TM0MD 0x03F54 bp3 TMOEN 1 9 Set the TM1IE flag of the TM1ICR register to 1 to enable the interrupt 10 Set the TM1EN flag of the TM1MD register to 1 to operate the timer 1 11 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 TMIBC TMOBC counts up from 0x0000 as a 16 bit timer When TMOBC reaches the set value of TMOBC register the timer 1 interrupt request flag is set at the next count clock and the value of TM1BC TMOBC becomes 0 0000 and restarts count up Use a 16 bit access instruction to set the TM1OC register Start the upper timer operation before the lower timer operation Cascade Connection V 55 5 8 bit Timers 56 Connection Chapter6 16 bit Timer 6 16 bit Timer VI 2 6 1 Overview This LSI contains a general purpose 16 bit timer Timer 7 Its compare register is double buffer
305. MOSIALL OMOSIALL oolq Jejeoselg Figure 5 1 4 Timers 4 and 5 Block Diagram V 7 Overview 5 8 bit Timers V 8 5 2 Control Registers Timers 0 to 5 consist of the binary counter TMnBC and the compare register TMnOC And they are controlled by the mode register TMnMD When the prescaler output is selected as the count clock source of timers 0 to 5 they should be controlled by the prescaler selection register CKnMD 5 2 1 Registers Table 5 2 1 shows registers that control timers 0 to 5 Table 5 2 1 8 bit Timer Control Registers Register Address Function TMOBC 0x03F50 Timer 0 binary counter TMOOC OxO3F52 Timer 0 compare register TMOMD 0x03F54 Timer 0 mode register CK0MD 0x03F56 Timer 0 prescaler selection register TM0ICR 0x03FE8 Timer 0 interrupt control register P1OMD 0x03F2B Port 1 output mode register IV 13 P1DIR 0x03F31 Port 1 direction control register IV 13 IRQSEL 0x03F4E External interrupt pin switching control register IV 13 TM1BC 0x03F51 Timer 1 binary counter V 15 TM10C 0x03F53 Timer 1 compare register V 14 TM1MD 0x03F55 Timer 1 mode register V 18 CK1MD 0x03F57 Timer 1 prescaler selection register V 11 TM1ICR 0x03FE9 Timer 1 interrupt control register 1 27 P1OMD 0x03F2B Port 1 output mode register IV 13 P1DIR 0x03F31 Port 1 direction control register IV 13 TM2BC 0x03F58 Timer 2 binary counte
306. NC labe if NF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0100 d7 H 2 1 5 label if NF 0 PC 6 d1 1 label H PC 6 3 4 0010 0011 0100 lt d11 8 if NF 1 PC 63PC BNS label if NF 1 PC 5 d7 label H PC 5 3 4 0010 0010 0101 d7 2 if NF 0 PC 5PC BNS label if NF 1 PC 6 d11 1 6 3 4 0010 0011 0101 dti H 3 0 6 BVC label if VF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0110 d7 9 if VF 1 PC 5PC BVC label if VF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0110 dt1 H 8 1 65 BVS label if VF 1 PC 5 d7 label HPC 5 3 4 0010 0010 0111 lt 97 H 9 if VF 0 PC 53PC BVS label if VF 1 PC 6 d11 label HPC 6 3 4 0010 0011 0111 dti H 3 if VF20 PC 62PC BRA label PC 3 d4 label H PC 3 1110 111H lt d4 gt 1 BRA label PC 4 d7 label H gt PC 4 1000 1001 lt d7 2 BRA label PC 5 d11 label H PC 5 1001 1001 lt d11 H 3 CBEQ CBEQ imm8 Dm label if Dmzimm8 PC 6 d7 label H2PC 6 3 4 1100 10Dm 48 gt lt 97 20 if DmZimm8 PC 62PC CBEQ imm8 Dm label if Dmzimm8 PC 8 d11 label H2PC 8 45 0010 1100 10Dm 48 gt lt d11 M i 8 if DmZimm8 PC 82PC CBEQ imm8 abs8 label f mem8 abs8 imm8 PC 9 d7 label HPC 9 6 7 0010 1101 1100 abs 8 4 8 gt lt d7 2 if mem8 abs8 imm8 PC 9 gt PC CBEQ imm8 abs8 label if mem8 abs8 imm8 PC 10 d11 label H PC 10
307. NCTRO 5 Set the interrupt level by the ADLV1 0 flag of the A D conversion complete interrupt control register ADICR If any interrupt request flag is already set clear it 6 Enable the interrupt by setting the ADIE flag the ADICR register to 1 Chapter 3 3 1 4 Interrupt Flag Setup 7 Set the ANLADE flag of the A D converter control registerO ANCTRO to 1 to send a current to the ladder resistance for the A D conversion 8 Clear the ANSTSEL1 flag of the A D converter control register2 ANCTR2 to 0 to set A D conversion starting factor to ANST flag of the A D converter control register2 ANCTR2 9 Set the ANST flag of the A D converter control register2 ANCTR2 to 1 to start the A D conversion Operation XVI 13 16 A D Converter Setup Procedure Description 10 Complete A D conversion operation 10 After A D conversion operation the result of conversion ANBUFO 0xO3FB5 is stored at A D buffer ANBUF 0 1 the ANST flag of ANBUF1 0x03FB6 A D control register 2 ANCTR2 is reset and then A D conversion complete interrupt is generated The above 3 to 4 can be set at the same time register ANCTRO to 0 and confirm the analog stop before changing the setup a After the A D conversion when you restart set the ANLADE of the A D converter control Operations of other than this order are not guaranteed XVI 14 Operation 16
308. NG2 to 0 flag holds the former set value until it is set again Except during communication SBT4 pin is masked to prevent errors by noise At slave com Y munication set data to TXBUF4 or input a clock to SBT4 pin after a start condition is input communicate properly more than 3 5 transfer clock after the data to TXBUF4 is Y needed to input the external clock Operation 15 Serial interface 4 B Start Condition Setup The SCASTE flag of SC4MD0 register sets if a start condition is enabled or not The start condition is regarded that when SCACEI flag of SCAMDO is set to 0 and a clock line SBT4 pin is H data line SBIA pin with 3 lines or SBO4 pin with 2 lines is changed from H to L Also it is regarded that when SCACEI flag is set to 0 and a clock line SBT4 is L data line SBIA pin with 3 lines SBO4 pin with 2 lines is changed from H to Both the SCASBOS flag and the SC4SBIS flag of the SCAMDI register should be set to 0 before the start con dition setup is changed At the selection of the start condition enable and master transmission reception after the start condition output start condition is input from the slave then data transmission is generated B First Transfer Bit Setup The SC4DIR flag of the SCAMDO register can set the transfer bit MSB first or LSB first can be selected B Transmission Data Buffer The transmission data bu
309. OMD2 register to 11 to select 8 bits 2 stop bits at the flame mode 8 Set the SCOCMD flag of the SCOMD1 register to 1 to select full duplex UART Set the SCOCKM flag of the SCOMD1 register to 1 to select divided by 8 at source clock And the SCOMST flag should be always set to 1 to select clock master Set the SCOSBOS SCOSBIS flag of the SCOMD1 register to 1 to set the TXDOA pin to serial data output and the RXDOA pin to serial data input 9 Setthe SCORIE flag of the SCORICR register to 1 and SCOTIE flag of the SCOTICR register to 1 to enable the interrupt request If any the interrupt request already set clear them Operation XI 55 11 Serial interface 0 Setup Procedure Description 10 Start the serial transmission 10 The transmission is started by setting the transmission The transmission TXBUF0 0x03F95 data to the serial transmission data buffer TXBUFO The reception data input to RXDO When the transmission is finished the serial 0 transmission interrupt SCOTIRQ is generated Also after the received data is stored to the RXBUFO the serial 0 reception interrupt SCORIRQ is generated Note 6 7 8 can be set at the same time When the TXDO RXDO pin are connected for communication with 1 channel the TXDO pin inputs outputs serial data The port direction control register PODIR switches At recep tion set SCOSBIOS of the
310. OVW d16 SP DWm mem16 d16 SP gt DWm 7 5 0010 1110 0014 lt 916 EM MOVW 816 5 16 416 5 Am ee 715 0010 1110 000a lt d16 gt 4 3 ab 715 715 2 3 3 4 3 3 5 4 5 4 7 5 4 3 4 3 72195 715 2 3 2 3 4 2 4 2 6 3 MOVW abs8 DWm mem16 abs8 DWm 1100 0114 abs 8 gt MOVW abs8 A mem16 abs8 5Am 1100 010a abs 8 gt MOVW s16 DWm mem16 abs16 5DWm aa 0010 1100 0114 abs 16 gt MOVW abs16 Am mem16 abs16 5Am E Es os feux 0010 1100 010a abs 16 gt MOVW DWn Am DWn mem16 Am 1 1111 00aD MOVW An Am An mem16 Am 0010 1111 10 4 MOVW DWn d4SP DWn mem16 d4 SP 1111 0110 lt d4 gt 2 MOVW An d4 SP An mem16 d4 SP 1111 010A lt d4 gt MOVW DWn d8 SP DWn mem16 d8 SP Sel Em l 0010 1111 0110 lt d8 gt a MOVW An d8 SP 16 98 0010 1111 010 lt 88 gt MOVW DWn d16 SP DWn mem16 d16 SP Ex Visa kes 0010 1111 0010 lt 916 NETS MOVW 916 3 16 016 5 ERE SES 0010 1111 000A lt 016 gt MOVW DWn abs8 DWn mem16 abs8 1101 0110 abs 8 gt MOVW 4158 An mem16 abs8 sS Aes es 1101 010A abs 8 gt MOVW DWn abs16 DWn memt6 abs16 ES 0010 1101 O11D abs 16 p MOVW An abs16 16 6516 1 0010 1101 010A abs 16 gt
311. OYIONL 22X 7350 zoya DP lt veourzza F dOdOWL IGOWOWL NS C 1SH 22Xh Ou OINMd Andino OIOW L 2 1 indino snououuoSu S Oti LIN L Jejsuea jeues indino OILNL o b Jejunoo 4e1si884 Y 1SH OgONWL Jejunoo 19 8 OSOOOWL eiu peeu dois Naon ZADONL uonez tuoiuou S 5 ZADLNL uonez IuouuouA S 22x 22x x indu OI LIALL x 2 gt OMOOWL GWOWL indu OIOIALL EMO OMOLWL 49019 Figure 5 1 2 Timers 0 and 1 Block Diagram V 5 Overview Timers 2 and 3 Block Diagram Chapter 5 8 bit Timers 1aseoul 1 0 T veouveeza snououuou AS OHIZIA L 5 LHOCWL anenL DN s C nd 154 2WMdAndino
312. Operation XVI 11 16 A D Converter A D Conversion Starting Factor Setup A D conversion starting factor is set with the ANSTSELI flag of the ANCTR2 register The ANSTSELI flag of the ANCTR2 register is set to start A D conversion by the external P23 PD1 PD1 falling edge factor Also the ANST flag of ANCTR2 register is set to 1 is possible Table 16 3 5 A D Conversion Starting Factor Setup ANSTSEL A D Conversion Starting Factor 0 Set ANST flag to 1 1 Set ANST flag and external factor P23 falling edge to 1 A D Conversion Starting Setup A D conversion starting is set with the ANST flag of the ANCTR2 register The ANST flag of the ANCTR2 reg ister is set to 1 to start A D conversion ANST flag of the ANCTR2 register is set to 1 after the external factor P23 falling edge to start A D conversion by the external P23 PD1 falling edge factor Also the ANST flag of ANCTR2 register is set to 1 during A D conversion then cleared to 0 Table 16 3 6 A D Conversion Starting Setup ANST A D Conversion Starting Factor 0 A D conversion start and A D conversion is during conversion 1 After the conversion ends A D conversion stop XVI 12 Operation 16 3 2 Setup Example 16 A D Converter B Example of A D Converter Setup by Registers A D conversion is started by setting registers The analog input pins are set to
313. PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMDO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O gt O Q O PAIMD7 PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMDO Analog input selection 0 port 1 Analog input Port A IV 99 4 I O Ports Pull up Pull down Resistor Selection Register SELUD 0x03F4B Port A pull up pull down selection 2 PADWN 0 Pull up 1 Pull down Port 7 pull up pull down selection 1 P7DWN 0 Pull up 1 Pull down Port 4 pull up pull down selection 0 P4DWN 0 Pull up 1 Pull down IV 100 Port A Chapter 4 I O Ports 4 12 3 Block Diagram r Reset RJ PADWN Pull up pull down resistor t Q selection WEK R Y Reset Pull up pull down resistor PAPLUO 4 p control Reset I O directon control R PADIRO H R 5 EE Y PA0 Port output data 591 q PAOUTO Reset Input mode control DRA PAIMDO 7 K ZR WEK Schmitt trigger input Port input data q PAINO 47 U R Analog input Figure 4 12 1 Block Diagram N Reset PADWN Pull u
314. Pana NSeries TheOnetoWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER MN101E MN101E01K 01L 01M FO1M LSI User s Manual Pub No 21601 007E Panasonic PanaXSeries is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations Request for your special attention and precautions in using the technical information 1 2 3 4 5 6 7 8 semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products It neither warrants non infringement of intellectual property right or any other rights owned by our company or a third party nor grants any license We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this book The products described in this book are intended to be used for standard applications or general electronic equipment such as office equipment commun
315. Parity Bit of UART Serial Interface SCOMD2 Parity bit Setup SCONPE SCOPM1 SCOPMO 0 0 0 Fixed to 0 Set parity bit to 0 0 0 1 Fixed to 1 Set parity bit to 1 0 1 0 Odd parity Control that the total of 1 of parity bit and character bit should be odd 0 1 1 Even parity Control that the total of 1 of parity bit and character bit should be even 1 None Do not add parity bit Break Status Transmission Control Setup The SCOBRKE flag of the SCOMD2 register generates the brake status If SCOBRKE is set to 1 to select the brake transmission all bits from start bits to stop bits transfer 0 B Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be deter mined by the SCOORE SCOPEK SCOFEF flag of the SCOSTR register Even one of those errors is detected the SCOERE flag of the SCOSTR register is set to 1 SCOPEK the SCOFEF flags in reception error flag are renewed at generation of the reception complete interrupt SCORIRQ The SCOORE flag is cleared at the same time of next communication complete interrupt SCORIRQ generation after the data of the RXBUFO is read out The decision of the received error flag should be operated until the next communication is finished Those error flag has no effect on communication operation Table 11 3 18 shows the list of reception error source Table 11 3 18 Reception Error Sou
316. Port D Output Register 0x03F2D Port D Input Register 0x03F3D Port D Direction Control Register 0x03F4D Port D Pull up Resistor Control Register 0x03F1B Port D Output Mode Register Overview 4 I O Ports 6 4 2 Porto 4 2 1 Description General Port Setup To output the data to pins set the control flag of the port 0 direction control register PODIR to 1 to write the value of the port 0 output register POOUT To read input data of pins set the control flag of the port 0 direction control register PODIR to 0 to read the value of the port 0 input register POIN Each bit can be set individually as either an input or output by the port 0 I O direction control register PODIR The control flag of the port 0 direction control register PODIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 0 pull up resistor control register POPLU Set the control flag of the port 0 pull up resistor control register POPLU to 1 to add pull up resistor P02 and P5 can select the Nch open drain output by each bit by the port 0 Nch open drain control reg ister POODC The port 0 Nch open drain control register POODC is set to 1 for the Nch open drain output and for the push pull output Special Function Pin Setup is used as output pin of the seri
317. Q3ICR The external interrupt 3 control register IRQ3ICR controls interrupt level of external interrupt 3 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSE is 0 Table 3 2 6 External Interrupt Control Register IRQ3ICR 0x03FE5 bp 7 6 5 1 0 Flag IRQ3LV1 IRQ3LV0 REDG3 IRQSIE IRQSIR At reset 0 0 0 0 0 Access R W Description IRQSLV1 External interrupt level flag IRQSLVO The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for inter rupt requests REDGS3 External interrupt valid edge flag 0 Falling edge 1 Rising edge IRQSIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQSIR External interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers III 23 Chapter 3 Interrupts B External Interrupt 4 Control Register IRQ4ICR The external interrupt 4 control register IRQ4ICR controls interrupt level of external interrupt 4 valid edge interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 7 External Interrupt 4 Control Register IRQ4ICR 0x03FE6 bp 7 6 5 4 3 2 1 0 Flag IRQ4LV1 IRQ4LVO REDG4 IRQ4IE IRQ4IR
318. R W R W bp Flag Description 7 P8DIR7 6 P8DIR6 5 P8DIR5 PODIAS ut mode 2 PaDIR2 UP 1 P8DIR1 0 P8DIR0 IV 82 Port 8 Chapter 4 I O Ports Port 8 Pull up Resistor Control Register P8PLU 0x03F48 P8PLU7 P8PLU6 5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLUO 0 0 0 0 0 0 0 0 Description 7 P8PLU7 6 P8PLU6 2 PSPLUS Pull up resistor selection 4 P8PLU4 i 0 Not added 3 P8PLU3 1 Added 2 P8PLU2 1 P8PLU1 0 P8PLU0 Port 8 IV 83 4 I O Ports 4 10 3 Block Diagram Reset 8 0 Pull up resistor control D gt be WEK R Reset I O direction control e p 2 2 M gt E WEK R x x g 1 ry x P80 2 P8OUTO Port output data Sr Q 2 WEK R mX Schmitt trigger input P8IN Port input data lt 1 a lt L wJ R Address output External extension output contorl Address input External extension input contorl Figure 4 10 1 P80 Block Diagram IV 84 Port 8 Chapter 4 I O Ports Reset
319. REDGO 0 2 Set the external interrupt pin The external interrupt 0 pin is pulled up in advance 3 Set the interrupt level IRQOICR OxO3FE2 bp7 6 IRQOLV1 0 210 4 Enable the interrupt IRQOICR OxOSFE2 bp1 IRQOIE 21 b Set the STOP mode CPUM 0x03F00 bp3 STOP 1 1 Set the REDGO of the external interrupt O control register IRQOICR to 0 to specify the interrupt valid edge to the rising edge 2 The value of the REDGO flag of the IRQOICR regis ter and the external interrupt pin level is different 3 Set the interrupt level by the IRQOLV1 to 0 flag of the IRQOICR register If the interrupt request has been already set clear the interrupt request flag IRQOIR 4 Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt b Transfer to the STOP mode by setting STOP flag of the CPU mode control register CPUM to 1 Chapter 2 2 4 4 Transfer to Standby Mode If the low level of the signal is input to the external interrupt O pin then the value of the external interrupt valid edge specify flag and the external interrupt 0 pin are matched the external interrupt 0 is accepted and recover from the STOP mode set at the oscillation stabilization wait control register DLYCTR is passed after the accep a Recovering from the STOP mode is done when the oscillation stabilization wait time which is tance of the external interrupt Chapter 2 2 8 4 Oscillation Stabilization Wa
320. RXD1 pin can be used only for serial data input The TXDI pin can be used for serial data input or output The SCIIOM flag of the SCIMDI register can specify which RXD1 or TXD1 inputs the serial data If data input from TXDI pin is selected to be with 1 line com munication transmission reception is switched by controlling TXD1 pin s direction by the P3DIRO flag of the P3DIR register At the same time the RXD1 pin can be used as a general port Reception Buffer Empty Flag When SCIRIRQ is generated data is stored to RXBUFI from the internal shift register automatically If data is stored to RXBUFI1 from the shift register the reception buffer empty flag SCIREMP of the SCISTR register is set to 1 That indicates that the received data is going to be read out SCIREMP is cleared to 0 by reading out the data of RXBUFI Reception BUSY Flag When the start condition is regarded the SCIRBSY flag of the SCISTR register is set to 1 That is cleared to by the generation of the reception complete interrupt SC1TIRQ If the SCISBIS flag is set to 0 during reception the SCIRBSY flag is reset to 0 B Transmission BUSY Flag When any data is set to TXBUFI the SCITBSY flag of the SCISTR register is set to 1 That is cleared to 0 by the generation of the transmission complete interrupt SCITIRQ During continuous communication the SCITBSY flag is always set If the transmission buffer empty flag SCITEMP is set to O as the
321. Registers XII 9 12 Serial interface 1 Serial interface 1 Mode Register 3 SC1MD3 0x03FA0 bp 7 6 3 2 1 0 1 5 Flag SC1FDC1 SC1FDCO SC1PSC2 SC1PSC1 SC1PSC1 Reset 0 0 0 0 0 0 Access Description Output selection after SBO1 final data transmit 00 Fix at 1 High output 01 Final data hold 10 Fix at 0 Low output 11 Reserved SC1FDC1 SC1FDCO Prescaler count control SC1PSCE 0 Count is forbidden 1 Count is allowed Selection clock 000 fosc 2 001 fosc 4 SC1PSC2 010 fosc 16 SC1PSC1 011 fosc 64 SC1PSC1 100 fs 2 101 fs 4 110 Timer 4 output 111 Timer 5 output XII 10 Control Registers Serial interface 1 Status Register SC1STR 0x03FA1 bp 7 6 5 4 3 2 1 Chapter 12 Serial interface 1 0 Flag SC1TBSY SC1RBSY SC1TEMP SC1REMP SC1FEF SC1PEK SC1ORE SC1ERE Reset 0 0 0 0 0 0 0 0 Access R SC1TBSY R R R R R Description Serial bus status 0 Other use 1 Serial transmission in progress R R SC1RBSY Serial bus status 0 Other use 1 Serial reception in progress SC1TEMP Transfer buffer empty flag 0 Empty 1 Full SC1REMP Receive buffer empty flag 0 Empty 1 Full SC1FEF Framing error detection 0 No error 1 Error SC1PEK Parity error detection 0 No error 1 Error SC1ORE Overr
322. S SC4SBTS flag of the SCAMD register to 1 to set the 5804 pin to the serial data output the SBIA pin to the serial input SBT4 pin to the transfer clock input output Set the SC4IOM flag 0 to set the serial data input from the SBIA pin 8 Set the interrupt level by the SC4TLV1 to 0 flag of the serial 4 UART transmission interrupt control register SCATICR 9 Set the SC4TIE flag of the SC4TICR register to 1 to enable the interrupt If any interrupt request flag SC4TIR of the SCATICR register is already set clear SC4TIR before the interrupt is enabled Operation XV 38 15 Serial interface 4 XV 34 Setup Procedure Description 10 Start the serial transmission 10 Set the transmission data to the serial transmission Transmission data y TXBUF4 0x03FB1 data buffer TXBUF4 The transmission or reception is Received data y input SBI4 pin started by the internal clock generation When the transmission finished the serial 4 UART transmission interrupt SCATIRQ is generated Chapter 3 3 1 4 Setup Each procedure 1 to 3 6 and 8 can be set at the same time to 0 and set the serial input to 1 input The SBIA pin can be used as a general port Also when only transmission is operated set the SC4SBOS of the SCAMD register to 0 to select a port a When only reception with 3 channels is operated set the SC4SBIS of the SC4MD1 register When communicate w
323. SC1MD1 register to 0 to select the synchronous serial Set the SC1MST flag of the SC1MD1 register to 0 to select the clock master internal clock Set the SC1CKM flag to 0 to select not divided by 8 for the clock source Set the SC1SBOS SC1SBIS SC1SBTS flag of the SC1MD 1 register to 1 to set the SBO1 pin to the serial data output the SBI1 pin to the serial input SBT1 pin to the transfer clock input output Set the SC1IOM flag 0 to set the serial data input from the SBI1 pin 8 Set the interrupt level by the SC1TLV1 to 0 flag of the serial 1 UART transmission interrupt control register SC1TICR 9 Set the SC1TIE flag of the SC1TICR register to 1 to enable the interrupt If any interrupt request flag SC1TIR of the SC1TICR register is already set clear SC1TIR before the interrupt is enabled Operation XII 38 12 Serial interface 1 XII 34 Setup Procedure Description 10 Start the serial transmission 10 Set the transmission data to the serial transmission Transmission data y TXBUF1 0x03FA3 data buffer TXBUF1 The transmission or reception is Received data y input SBI1 pin started by the internal clock generation When the transmission finished the serial 1 UART transmission interrupt SC1TIRQ is generated Chapter 3 3 1 4 Setup Each procedure 1 to 3 6 7 and 8 can be set at the same time to 0 and set the serial input to 1 input
324. SC2MD1 SC2SBOS SC2MD1 SC2SBIS SC2MD1 SC2SBIS Type Push pull N ch open Push pull N ch open drain drain POODC POODC5 Input mode Output mode Input mode PODIR PODIR3 PODIR PODIR5 Pull up added not added added not added POPLU POPLUS Operation XIII 29 13 Serial Interface 2 13 3 2 Setup Example B Transmission Reception Setup Example Here is the setup example at transmission reception with serial interface 2 Table 13 3 11 shows the conditions Table 13 3 11 Conditions for Synchronous Serial Interface at transmission reception Item set to Serial data input pin SBI2 SBO2 Independent 3 channels Transfer bit count 8 bits Start condition Disabled First bit to be transferred MSB Input clock edge Falling Output clock edge Rising Clock Clock master Clock source SBT2 SB02 pin type fs 2 N ch open drain SBT2 pull up resistor Added SB02 pull up resistor Added Serial interface 2 communication end interrupt Enabled An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation SC2MDS 0 03 98 bp3 SC2PSCE 1 2 Select the clock source SC2MD3 0x03F 98 bp2 0 SC2PSC2 0 100 3 Control of pin type POODC 0x03F1C bp5 POODC5 1 1 0 0 40 bp5 POPLU5 1 bp3 POP
325. SCOMD 1 register to 1 to select serial data input The RXDO pin can be used as a general port This serial interface contains emergency reset function If communication need to be stopped by force set SCOSBOS and SCOSBIS of the SCOMD 1 register to O Each flag should be set as the setup procedure in order Activation of communication should be operated after all control registers refer to Table 11 2 1 TXBUFO RXBUFO are set Timer 2 and timer 4 can be used as a baud rate timer Refer to Chapter 5 5 9 Serial Transfer Clock Output Operation 1 1 XI 56 Operation Chapter 12 Serial interface 1 12 Serial interface 1 XII 2 12 1 Overview This LSI contains a serial interface 1 that can be used for both communication types of clock synchronous and UART full duplex 12 1 1 Functions Table 12 1 1 shows functions of serial interface 1 Table 12 1 1 Serial Interface 1 functions Communication style Clock synchronous UART full duplex Interrupt SC1TIRQ SC1TIRQ on transmission completion SC1RIRQ on reception completion Used pins SBO1 SBI1 SBT1 TXD1 RXD1 3 channels type 2 channels type O SBO1 SBT1 1 channel type TXD1 Specification of transfer bit count Frame 1 to 8 bits 7 bit 1STOP selection 7 bit 2STOP 8 bit 1 STOP 8 bit 2STOP Selection of parity bit Parity bit control 0 parity
326. Set the SC1CMD flag of the SC1MD1 register to 0 to select the synchronous serial 10 Set the SC1MST flag of the SC1MD1 register to 0 to select the clock slave external slave Set the SC1CKM flag to 0 to select not divided by 8 for the clock source 11 Set the SC1SBOS of the SC1MD1 register to 0 the SC1SBTS flag of the SC1SBIS register to 1 to set the SBI1 pin to the serial data input as the SBO1 general port the SBT1 pin to the transfer clock input output Set the SC1IOM flag 0 to set the serial data input from the 5 pin 12 Set the interrupt level by the SC1LV1 to 0 flag of the serial 1 UART transmission interrupt control register SCATICR Set level 2 13 Set the SC1TIE flag of the SC1TICR register to 1 to enable the interrupt If any interrupt request flag SC1TIR of the SC1TICR register is already set clear SC1TIR before the interrupt is enabled Chapter 3 3 1 4 Setup 14 Set the dummy data to the serial transmission data buffer TXBUF1 15 Set the STOP flag of the CPUM register to 1 to transfer to the stop mode 16 Input the transfer clock to the SBT1 pin and transfer data to the pin Operation 12 Serial interface 1 Setup Procedure Description 17 Recover from the standby mode 17 The serial 1 UART transmission interrupt SC1TIRQ is generated at the same time of the 8 bits data reception then CPU is recovered f
327. Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt ATC 1IIRQ occurs and the automatic transfer ends XVIII 18 Operation 18 Automatic Transfer Controller 18 3 7 Transfer Mode 2 In transfer mode 2 1 automatically transfers one byte of data from any memory space to the space spe cial registers 0x03F00 OxO3FFF everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to O3FFF Nd 1 2 4 Only lower 8 bits valid 1 2 3 Figure 18 3 4 Transfer Mode 2 Set the source address in 20 bit memory pointer 0 ATIMAPOH M L and set the destination I O address in lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH and ATIMAPIM In transfer mode 2 the value in memory pointer 0 increments everytime a byte length data transfer ends As a result the source address for the next transfer is one address higher than that for the previous transfer Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00
328. Set the interrupt pin IRQ2ICR OxOSFAE bp2 IRQ2SEL 0 7 Set the interrupt valid input IRQ2ICR OxOSF6D bp0 LVLEN2 0 8 Set the interrupt level IRQ2ICR 0x03FE4 bp7 6 IRQ2LV1 0 XX 9 Set the interrupt valid edge IRQ2ICR 0x03FE4 bp5 REDG2 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the timer 0 counting 2 Set the TMOPWM flag of the TMOMD register to 0 and TMOMOD flag to 1 to enable the timer operation during L period to be measured 3 Select the prescaler output to the clock source by the 2 to 0 flag of the TMOMD register 4 Select fs 2 to the prescaler output by the TMOPSC1 to 0 flag and the TMOBAS flag of the timer 0 prescaler selection register CKOMD b Set the timer 0 compare register TMOOC to the bigger value than L period the cycle of fs 2 of measured pulse width At that time the timer 0 binary counter TMOBC is initialized to 0x00 6 Set the external interrupt 2 pin to IRQ2A by the IRQ2SEL flag of the external interrupt 2 control register IRQSEL 7 Set the IRQ2A valid input to edge by LVLENe flag of external interrupt valid input switching control register LVLMD 8 Set the interrupt level by IRQ2LV1 0 flag of external interrupt 2 control register Reset the request flag when interrupt request flag is already set Chapter3 3 1 4 Interrupt Flag Setup 9 Set the REDG2 flag of the IRQ2ICR register to 1 to spec
329. T1 pin Input pin SBO1 SBI1 pin Transfer bit counter SC1RBSY 4 Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 16 Reception Timing at Standby Mode Reception at rising edge start condition is dis abled Operation B Pins Setup with channels at transmission Chapter 12 Serial interface 1 Table 12 3 7 shows the setup for synchronous serial interface pin with 3 channels SBO1 pin 5 pin SBTI pin at transmission Table 12 3 7 Setup for Synchronous Serial Interface Pin with 3 channels at transmission Setup item Data output pin Data input pin Clock I O pin 5801 pin SBI1 pin SBT1 pin Clock master Clock slave SC1MD1 SC1MST Port pin P30 P31 P32 Serial data input SBI1 selection SC1MD1 SC1IOM Function Serial data output 1 input Transfer clock input Transfer clock input output output SC1MD1 SC1SBO SC1MD1 SC1SBIS SC1MD1 SC1SBTS 5 Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain P3ODC P3ODC0 P3ODC P3ODC2 Output mode Output mode Input mode P3DIR P3DIR0 P3DIR P3DIR2 Pull up setup Added Not added Added Not added Added Not added PSPLU PSPLUO P3PLU P3PLU2 Operation XII 27 12 Serial interface 1 XII 28 B Pins Setup with channels at reception Table 12 3 8 shows the setup for synchronous serial interface pin with 3 chan
330. T3 PAOUT2 PAOUTO x x x x x x x x bp Flag Description PAOUT7 PAOUT6 PAOUT5 PAOUT4 PAOUT3 PAOUT2 1 Output data 0 Output L VSS level 1 Output H VDD level S O Q O Port A IV 97 4 I O Ports Port A Input Register PAIN 0x03F2A bp Flag Description 7 PAIN7 6 PAIN6 5 PAIN5 Input data x PANT 0 Pin is L VSS level 3 PAINS 1 Pin is H VDD level 2 PAIN2 PIS ARE eyel 1 PAIN1 0 PAIN0 Port A Direction Control Register PADIR 0x03F3A IV 98 Flag PADIR7 PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O gt O Q O Port A PADIR7 PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIRO mode selection 0 Input mode 1 Output mode Port A Pull up Pull down Resistor Control Register PAPLU 0x03F4A 7 PAPLU6 5 PAPLUA PAPLU3 PAPLU2 PAPLU1 Chapter 4 Ports PAPLUO 0 0 0 0 0 0 0 0 bp Flag Description O gt O Q O PAPLU7 PAPLU6 PAPLU5 PAPLU4 PAPLU3 PAPLU2 PAPLU1 PAPLU0 1 Added Pull up pull down resistor selection 0 Not added Port A Input Mode Register PAIMD 0x03F3B Flag PAIMD7
331. TI TRC in one continuous operation Memory pointer 0 Memory pointer 1 00000 to FFFFF 00000 to FFFFF AY S sss 2 ATMAPO 1 2 5 2 1 1 1 4 2 gt 1 2 6 6 3 1 3 Figure 18 3 16 Transfer Mode E Set the source address in 20 bit memory pointer 0 ATIMAPOH M L and set the destination address in 20 bit memory pointer 1 ATIMAPIH L Once ATC is activated memory pointers 0 and 1 increment everytime byte length data transfer ends For burst transfers set the number of data bytes to be transferred in the transfer data counter ATI TRC Up to 255 transfers can be set Once the burst transfer starts the counter decrements everytime an transfers one byte of data When it reaches 0x00 an interrupt ATC1IRQ occurs and the burst transfer ends You can shut down ATC1 during burst transfers using external interrupt 0 You can enable or disable 1 shut down with the burst transfer stop enable flag BSTP of control register 1 ATICNTI When 1 and the interrupt request flag for external interrupt 0 the IRQOIR flag in the IRQOICR register is set the ATCI data transfer shuts down immediately During this shutdown the transfer counter and the memory pointers save the values they contained prior to the shutdown When the interrupt service routine ends
332. TM4CK2 TM4CK1 TM4CKO Select the clock source X00 fosc X01 TM4PSC Prescaler output 010 fx 011 Synchronou fx 110 TM4IO input 111 Synchronous TM4IO output Control Registers V 21 5 8 bit Timers Timer 5 Mode Register TM5MD 0x03F65 4 2 1 0 TM5CAS TM5CK2 5 1 TM5CK0 0 0 0 0 Description 7 5 4 TM5CAS Select timer 5 operation mode 0 Normal timer operation 1 Cascade connection 3 TM5EN Timer 5 count control 0 Halt the count 1 Operate the count 2 0 TM5CK2 Select clock source TM5CK1 X00 fosc TM5CKO X01 TM5PSC Prescaler output 010 fx 011 Synchronous fx 110 TMBIO input 111 Synchronous TMBIO input V 22 Control Registers Timer I O pin Switching Control Register TMSEL 0x03F3F 6 5 4 Chapter 5 8 bit Timers TM7SEL TM5SEL TM4SEL 0 0 0 Description TM7SEL Switch timer 7 pin 0 P16 TM7IOA 1 PD4 TM7IOB TM5SEL Switch timer 5 pin 0 P15 TM5IOA 1 5 TM4SEL Switch timer 4 pin 0 P14 TM4IOA 1 PD2 TM4IOB Control Registers V 23 5 8 bit Timers V 24 B External Interrupt Pin Switching Control Register IRQSEL 0x03F4E 3 2 IRQSSEL IRQ2SEL 0 0 Description IRQ3SEL External interrupt 3 input pin switching 0 P23 1 PD1 IRQ2SEL Ex
333. TM6OC register but in that state the timer 6 interrupt is disabled If the timer 6 interrupt should be used set the TM6CLRS flag to 1 after rewriting the TM6OC register On the timer 6 clock source selection if the time base timer output or the time base timer synchronous output is selected the clock setup of time base timer is necessary VII 14 8 bit Free running Timer 7 Time Base Timer Free running Timer 7 4 Time Base Timer 7 4 1 Operation Time Base Timer Time Base Timer Interrupt is constantly generated by a selected clock source and a interrupt generation cycle Table 7 4 1 shows the interrupt cycle is combination with the clock source Table 7 4 1 Selection of Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle fosc fosc x 1 27 6 4 us fosc x 1 28 12 8 us fosc x 1 29 25 6 us fosc x 1 210 51 2 us fosc x 1 213 409 6 us fosc x 1 215 1 64 ms fx fx x 1 27 3 9 ms fx x 1 28 7 8 ms fx x 1 29 15 6 ms fx x 1 210 31 2 ms fx x 1 213 250 ms fx x 1 215 1s fosc 20 MHz fx 232 768 kHz Time Base Timer VII 15 7 Time Base Timer Free running Timer Count Timing Timer Operation Time Base Timer The counter counts up with the selected clock source as a counter clock 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 13 10 9 8 7 1 2 1 2 1 2 1 2 1 2 1 2 Figure 7 4 1 Count Ti
334. TM7BC reaches the set value of the register and TM7BC is cleared to 0x0000 the signal of the TM7IO output is inverted and TM7BC counts up from 0x0000 again Regardless of whether the binary counter is stopped or operated the timer output is L when the TM7CL flag of the TM7MD1 register is set to 1 16 bit Timer Pulse Output VI 25 6 16 bit Timer 6 6 16 bit Standard PWM Output Only duty can be changed consecutively pin outputs the standard PWM output which is determined by the overflow timing of the binary counter and the match timing of the timer binary counter and the compare register 6 6 1 Operation 16 bit Standard PWM Output Timer 7 PWM waveform with an arbitrary duty is generated by setting a duty of PWM period to the compare register 1 TMnOC 1 Its cycle is the time of the 16 bit timer full count overflow Table 6 6 1 shows the PWM output pin Table 6 6 1 PWM output pin Timer 7 Pulse output TM71O output P16 PD4 pin Count Timing of Standard PWM Output at Normal Timer 7 TM7EN flag Compare register 1 si ee 2 i _ di uu n 20 bi counter TM7IO output PWM output VOUS mM gt Setup time for compare register 1 PWM basic component overflow time of the binary counter N Figure 6 6 1 Count Timing of Standard PWM Output at Normal VI 26 16 bit Standard PWM Output Only d
335. TM7ICR OxOSFFO bp1 TM7IE 0 3 Select the pin bp6 TM7SEL 0 4 Set the special function pin to input P1DIR 0x03F31 bp6 P1DIR6 0 5 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 01 bp3 2 TM7PS1 0 00 6 Set the interrupt generation cycle TM7PR1 0x03F75 0x03F74 0x0004 7 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 8 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 10 bp3 2 TM7PS1 0 00 9 Set the interrupt level TM7ICR 0x03FF0 bp7 6 TM7LV1 0 10 1 Set the TM7EN flag of the Timer 7 mode register 1 TM7MD1 to 0 to stop the Timer 7 counting 2 Set the TM7IE flag of the TM7ICR register to to disable the interrupt 3 Switch the timer I O pin Set the TM7SEL flag of the TMSEL register to select the TM7IOA as the input pin 4 Set the P1DIR6 flag of the port 1 direction control register P1DIR to 0 to set P16 pin to the input mode Add pull up pull down resistor if necessary Chapter 4 ports b Select fs to the clock source by the TM7CK1 to 0 flag of the TM7MD1 register Besides select 1 1 to the count clock source by the TM7PS1 to 0 flag 6 Set the interrupt generation cycle to the Timer 7 preset register 1 TM7PR1 The set value should be 4 because the counting is 5 times At that time the same value is loaded to the Timer 7 compare register 1 TM7OC1 and the Timer 7 binary cou
336. TXBUF1 a start condition is generated to start transfer At reception if a start condition is received communication is started At reception if the data length of L for start bit is longer than 0 5 bit that can be regarded as a start condition B Transmission Data transfer is automatically started by setting data to the transmission data buffer TXBUF1 When the trans mission is completed the serial 1 transmission interrupt SCITIRQ is generated Reception Once a start condition is received reception is started after the transfer bit counter that counts transfer bit is cleared When the reception is completed the serial 1 reception interrupt SC1RIRQ is generated Full duplex communication On full duplex communication the transmission and reception can be operated separately at the same time The frame mode and parity bit of the used data on transmission reception should have the same polarity B Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SC1FM1 to 0 flag of the SCIMD2 register If the SCICMD flag of the SCIMDI register is set to 1 and UART communication is selected the setup by the synchronous serial transfer bit count selection flag SCILNG2 to 0 is no more valid Data Input Pin Setup The communication mode can be selected from with 2 channels data output pin TXD1 pin data input pin RXDI pin or with 1 channel data pin TXDI pin The
337. TXD1 port 3 6 bit COMS tri state port P31 34 581 RXD1 Each bit can be set individually as either an input or output by the P32 35 SBT1 P3DIR register A pull up pull down resistor for each bit can be P33 36 SBO3A SDA3A selected individually by the P3PLU register P34 37 SBI3A At reset the input mode is selected and pull up resistors are dis P35 38 SBT3A SCL3A abled high impedance output Pin Description 1 13 1 Overview Name NO Other Function Function Description P40 72 VO SBO4 TXD4 port 4 4 bit COMS tri state port P41 73 5814 RXD4 Each bit can be set individually as either an input or output by the P42 74 SBT4 P4DIR register A pull up pull down resistor for each bit can be P43 75 selected individually by the P4PLU register A pull up pull down resistor for each port can be selected individually by the SELUD register However pull up and pull down resistors cannot be mixed At reset the input mode is selected and pull up resistors are dis abled high impedance output P50 39 VO ANO port 5 8 bit COMS tri state I O port P51 40 AN1 Each bit can be set individually as either an input or output by the P52 41 2 P5DIR register A pull up pull down resistor for each bit can be P53 42 AN3 selected individually by the P5PLU register P54 43 AN4 At reset the input mode is selected and pull up resistors are dis P5
338. The SBI1 pin can be used as a general port Also when only transmission is operated set the SC1SBOS of the SC1MD1 register to 0 to select a port a When only reception with 3 channels is operated set the SC1SBIS of the SC1MD1 register When communicate with 2 channels the SBO1 pin inputs outputs serial data The port direction control register P3DIR switches I O At reception set SC1SBIS of the SC1MD1 register to 1 always to select serial input The SBI1 pin can be used as a general port This serial interface contains a emergency reset function If the communication should be stopped by force set SC1SBOS and SC1SBIS of the SC1MD1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 12 2 1 except TXBUF1 are set Transfer rate of transfer clock set by the SC1MD3 register should be under 5 0 MHz Operation 12 Serial interface 1 B Transmission Reception Setup Example Standby Mode Reception The setup example for clock synchronous serial communication with serial 1 is shown Table 12 3 13 shows the condition at standby mode reception Table 12 3 13 Setup Examples for Synchronous Serial Interface Transmission Reception Standby Mode Reception Setup item Set to Serial data input pin Independent 2channels
339. Transfer Bit Count and First Transfer Bit LSB First Receive Bit Count and First Transfer Bit When the transfer bit count is 1 to 7 bits data storage to the transmit receive shift register SC3TRB depends on the first transfer bit When MSB is the first bit to be transferred the lower bits of SC3TRB are used for storage In Figure 14 3 4 as the transfer bit count is 6 bits data A to F are stored to bp5 to bp0 of SC3TRB and they are transferred from F to A When LSB is the first bit to be transferred use the upper bits of SC3TRB for storage In Figure 14 3 5 data A to F are stored to bp2 to bp7 of SC3TRB as the transfer bit count is 6 bits and they are transferred from A to F SC3TRB JEDE E Figure 14 3 4 Receive Bit Count and First Transfer Bit MSB First 7 6 5 4 3 2 1 0 scarme Figure 14 3 5 Receive Bit Count and First Transfer Bit LSB First When the serial transfer bit is set between 1 to 7 the data except for received data of the specified transfer bit count is unknown Use the received data after being masked by AND OR instruction XIV 16 Operation 14 Serial Interface 3 Continuous Mode Serial interface 3 is capable of continuous transmission If data is set to transmission data buffer TXBUF3 during transmission transmission buffer empty flag SC3TEMP is set and the set data is automatically transmit Se
340. Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Clock Clock slave Operation mode Stop mode Clock source fs 2 Clock source 1 8 dividing Not divided by 8 SBT1 SBO1 pin style Push pull SBT1 pin pull up resistor Not added SBO pin pull up resistor Not added serial 1 communication complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation SC1MD3 0x03FA0 bp3 SC1PSCE 1 2 Select the clock source SC1MD3 0x03FA0 bp2 0 SC1PSC2 0 100 3 Control the pin style P30DC 0x03F2C bp2 0 P3ODC2 0 0 0 P3PLU 0x03F43 bp2 0 P3PLU2 0 0 0 4 Control the pin direction P3DIR 0x03F43 bp2 P3DIR2 0 P3DIR1 0 bp0 P3DIR0 1 1 Set the SC1PSCE flag of the SC1MD3 register to 1 to select prescaler operation 2 Set the SC1PSC2 to 0 flag of the SC1MD3 register to 100 to select fs 2 as the clock source 3 Set the PSODC2 P3ODCO flag of the P3ODC register P3DIR to 0 0 and select the Nch open drain at SBO1 SBT1 pins Then set the P1PLU2 P1PLUO flag of the P3PLU register to 0 0 and select enable pull up resistance 4 Set the P3DIR2 P3DIR3 flag of the Port pin direction control register P3DIR to 0 0 and the P3DIRO flag to 1 to set P32 P31 to the input mode Operation XII
341. VLENS External interrupt 5 valid input set 0 Hedge 1 Level EXLVL3 External interrupt 3 valid input level set O L level 1 H level External interrupt 3 valid input set 0 Hedg 1 Levele EXLVL2 External interrupt 2 valid input level set O L level 1 H level LVLEN2 External interrupt 2 valid input set 0 Hedge 1 Level External Interrupts III 59 Chapter 3 Interrupts III 60 3 3 4 Programmable Active Edge Interrupt Programmable Active Edge Interrupts External interrupts 0 to 5 The programmable active edge interrupt can select the rising falling edge about the signal which is input from the external interrupt input pin and generate the interrupt at the selected edge Also if the value which is set to the external interrupt valid edge specify flag and the level of the external interrupt pin are matched it is possible from the standby mode Programmable Active Edge Interrupt Setup Example External interrupt 0 to 5 External interrupt 0 IRQO is generated at the rising edge of the input signal from P20 The table below shows a setup example of IRQO Setup Procedure Description 1 Specify the interrupt active edge 1 Set the REDGO flag of the external interrupt O control IRQOICR 0x03FE2 register IRQOICR to 1 to specify the rising edge as bp5AFREDGO 1 the active edge for interrupts 2 Set the interrupt level 2 Set the interrupt priority level
342. W Serial 4 UART reception interrupt control register III 42 SC4UART reception completion Control Registers Chapter 3 Interrupts SC4TICR OxOSFF9 R W Serial 4 UART transmission interrupt control register III 43 SC4UART transmission completion ADICR OxO3FFA R W A D conversion interrupt control register A D conversion III 44 completion ATC1ICR OxO3FFB R W ATC1 interrupt control register ATC1 transmission comple 11 45 tion rupt enable flag and interrupt request flag a If the interrupt level flag xxxLVn is set to level 3 its vector is disabled regardless of inter Writing to the interrupt control register should be done after that maskable interrupts are set to be disable by the MIE flag of the PSW register 18 Control Registers 3 Interrupts 3 2 2 Interrupt Control Registers gz ss The interrupt control registers include the non maskable interrupt control register NMICTR the external inter rupt control register and the internal interrupt control registers xxxICR Interrupt Control Register NMICR 0x03FE1 The non maskable interrupt control register NMICR is stored the non maskable interrupt request When the non maskable interrupt request is generated the interrupt is accepted regardless of the interrupt mask level IMn of PSW The hardware then branches program to the address stored at
343. Y is cleared to 0 If the SCASBOS flag is set to 0 during communication the SC4TBSy flag is cleared to 0 B Emergency Reset This serial interface contains emergency reset for abnormal operation For emergency reset the SCASBOS flag and the SCASBIOS flag of SCAMDI register should be set to 0 SBO4 pin port input data 1 input At emergency reset the status register the SCABRKF flag of the SCAMD2 register all flags of the SC4STR reg ister are initialized as they are set at reset but the control register holds the set value B Last Bit of Transfer Data Table 15 3 4 shows the data output holding period of the last bit at transmission and the minimum data input period of the last bit at reception The internal clock should be set up at slave to keep the data hold time at recep tion Table 15 3 4 Last Bit Data Length of Transfer Data The last bit data holding period at transmission The last data input period at reception At master 1 bit data length 1 bit data length Minimum At slave 1 bit data length of external clock x 1 2 internal clock cycle x 1 2 3 2 In the case of disabled start condition at SCASTE flag 0 the SBO4 output after the data output holding period of the final bit can be set as Table 15 3 5 by the setting value of the SCAFDCI to 0 flag of the SC4MD3 register After released the reset despite of the setting value of the SCAFDCI to 0 flag output before the seria
344. abs8 bp label if mem8 abs8 bp 0 PC 8 d1 1 label eHPC 8 6 7 0011 0000 ibp abs 8 dii 3 if mem8 abs8 bp 1 PC 82PC 1 4 sign extension d7 sign extension d11 sign extension Instruction Set XIX 5 Chapter 19 Appendix MN101E SERIES INSTRUCTION SET VF NF CF peat son 1 2 3 4 5 6 7 8 9 10 11 TBZ TBZ i08 bp label if mem8 lOTOPsi08 bp 0 PC 7 d7 label sH 4PC O e 0 7 6 7 0011 0100 lt 08 gt lt d7 4 if mem8 IOTOP io8 bp 1 PC 7 PC TBZ i08 bp label if mem8 IOTOP i08 op 0 PC 8 d1 label H3PG 0 0 6 8 67 0011 0100 1bp lt 08 gt lt dll 72 if mem8 IOTOP i08 bp 1 PC 8 PC TBZ abs16 bp label if mem8 abs16 bp 0 PC 9 d7 label HPC 0 0 9 7 8 0011 1110 abs 16 gt d7 if mem8 abs16 bp 1 PC 9 PC TBZ abs16 bp label l mem8 abst6 op 0 PC 10 d1 label sH9PC 6 0 10 78 0011 1110 16 abs 16 gt di 2 lif mem8 abs16 bp 1 PC 10 PC TBNZ 2 abs8 bp label if mem8 abs8 bp 1 PC 7 d7 label HPC O 0 e 7 6 7 0011 0001 abs 8 lt 97 t if mema abs8 bp 0 PC 72PC TBNZ abs8 bp label If mem8 abs8 bp 1 PC 8 d1 1 label HPC O o 8 6 7 0011 0001 16 abs 8 dii 72 if mem8 abs8 bp 0 PC 82 PC 2 io8 bp label if mem8 io bp 1 PC 7 d7 labe HOPC O 0 7 67 0011 0101 lt 08 gt
345. added SBO4 pin pull up resistor Not added serial 4 communication complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation SC4MD3 0x03FAE bp3 SC4PSCE 1 2 Select the clock source SC4MD3 0x03FAE bp2 0 SC4PSC2 0 100 3 Control of pin type PAODOC 0x03F3C bp2 P4ODC2 0 bp1 P4ODC1 0 P4PLU 0x03F44 bp2 P4PLU2 0 P4PLU1 0 1 Set the SC4PSCE flag of the SC4MD3 register to 1 to select prescaler operation 2 Set the SC4PSC2 to 0 flag of the SC4MD3 register to 100 to select fs 2 as the clock source 3 Set the PAODC2 P4ODC1 flags of the PAODC register to 0 0 to select push pull for the SBIA SBTA pin type Set the PAPLU2 P4PLU1 flags of the PAPLU register to 0 0 to select disable pull up resistor Operation XV 35 15 Serial interface 4 XV 36 Setup Procedure Description 4 Control the pin direction P4DIR 0x03F34 bp2 P4DIR2 0 bp1 P4DIR1 0 bp0 P4DIR0 1 5 Select the transfer bit count SC4MD0 0x03FAB bp2 0 SC4LNG2 0 111 6 Select the start condition SC4MD0 0x03FAB bp3 SC4STE 0 7 Select the first bit to be transferred SC4MD0 0x03FAB bp4 SC4DIR 0 8 Select the transfer edge SC4MD0 0x03FAB bp7 SC4CE1 1 9 Select the communication type SC4MD1 0x03FAC bp0 SC
346. added serial 0 communication complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation SCOMD3 0x03F92 bp3 SCOPSCE 1 2 Select the clock source SCOMD3 0x03F 92 bp2 0 SCOPSC2 0 100 3 Select the used pins SCSELO 0x03F4F bp0 SCOSEL 0 1 Set the SCOPSCE flag of the SCOMDS register to 1 to select prescaler operation 2 Set the SCOPSC2 to 0 flag of the SCOMD3 register to 100 to select fs 2 as the clock source 3 SCOSEL flag of SCSEL register O to set I O used pin to A portO Operation 11 Serial interface 0 Setup Procedure Description 4 Pin style controlt POODC 0x03F1C bp2 0 POODC2 0 1 1 POPLU 0x03F40 bp2 0 POPLU2 0 1 1 5 Control the pin direction PODIR 0x03F49 bp2 0 PODIR2 0 1 0 1 6 iSelect the transfer bit count SCOMDO 0xOS3F8F bp2 0 SCOLNG2 0 111 7 Select the start condition SCOMDO 0x0OSF8F bp3 SCOSTE 0 8 Select the first bit to be transferred SCOMDO 0xOSF8F bp4 SCODIR 0 9 Select the transfer edge SCOMDO 0xOSF8F bp7 SCOCE1 1 10 Select the communication type SCOMD1 0x03F90 bp0 SCOCMD 0 11 Select the transfer clock SCOMD1 0x03F90 bp2 SCOMST 0 bp3 SCOCKM 0 12 Control the pin function SCOMD1 0x03F90 bp4 SCOSBOS 0 bp5 SCOSBIS 1 bp6
347. added over the second communication Set the SC3DIR flag of the SC3MDO register to 0 to set MSB as the first bit to be transferred In IIC communication set the SC3CE1 flag of the SC3MDO register to 1 12 Set the SC3MST flag of the SC3MD1 register to 1 to select clock master internal clock In communication do not select external clock Set the SC3SBOS SC3SBIS SC3SBTS flags of the SC3MD1 register to 1 to set the SDA3 pin the SBO3 pin to serial data output the SBI3 pin to serial data input and the SCL3 pin the SBT3 pin to serial clock O Set the SC3IOM flag to 1 to set serial data input from the SDAG pin the SBOS pin 13 Set the interrupt level by the SC3LV1 0 flag of the serial 3 interrupt control register SC3ICR Operation XIV 49 14 Serial Interface 3 Setup Procedure Description 14 Enable the interrupt SC3ICR 0x03FF7 bp1 SCSIE 1 15 Start serial transmission Start serial transmission Confirm that SCL3 P35 is H Transmission data TXBUFS 0x03FA8 16 Transmission ends Setup of the next data transmission Judge the monitor flag SC3CTR 0x03FAA bp6 IICSTC 17 Judge the ACK bit level SC3CTR 0x03FAA 5 18 Set the SC3MDO0 register Select the transfer bit count SC3MDO 0x03FA4 bp2 0 SC3LNG2 0 19 lt Next data transmission is started gt Serial transmission is started
348. ain output by each bit by the port 3 Nch open drain control reg ister P3ODC The port output mode register is set to 1 for the Nch open drain output and 0 for the push pull output Special Function Pin Setup P30 is used as output pin of the serial 1 transmission data or the UART 1 transmission data as well When the SCISBOS flag of the serial interface 1 mode register 1 SCIMD1 is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 3 Nch open drain control register P3ODC P31 is used as input pin of the serial 1 reception data or the UART 1 reception data as well P32 is used as pin of the serial 1 clock as well When the SCISBTS flag of the serial interface 1 mode regis ter 1 SCIMDI is set to 1 itis output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the port 3 Nch open drain control register PSODC P33 is used as output pin of the serial 3 transmission data or the IIC3 transmission data as well When the SC3SBOS flag of the serial interface 3 mode register 1 SC3MD1 is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 3 Nch open drain control register PSODC P34 is used as input pin of the serial 3 reception data P35 is used as I O pin of th
349. al Interface essere XIV 38 14 3 4 Setup Examples oae RE UR ERE XIV 48 Chapter tetas 1 LD A E 2 151 1 Eunctions one rette 2 15 12 Block Diagram aie 4 15 2 Control XV 5 15 2 1 een terere le sees ov da ERE DI ERU RP RR XV 5 15 2 2 Data Buffer 151 u S XV 6 15 2 3 Mode 7 15 3 Oper t on EET XV 12 15 3 1 Clock Synchronous Serial Interface sss eene XV 12 15 3 2 Setup Example ec oet a ee itte us re i Rs 32 15 3 3 UART Serial un caede eere pats te Dreier XV 38 15 34 Setup Example et eR UE E XV 50 Chapter 16 A7D CUOWlVOFler a E XVI 1 16 17 e ed ott eiue ee ai ee E i E Reenter XVI 2 1611 quiso emn os beaut te pe re e eg Rede XVI 2 16 1 2 Block Diagram D ee re n ubere Sateen lone ete ie tend XVI 3 16 2 Control Registers 5 oec nti c rn e ee Ree E ooh e a XVI 4 16 2 1 inte aep HERR DRE RERO IO EURO Seno XVI 4 16 2 2 Control ee ee XVI 5 16 23 Data
350. al O transmission data or the UART 0 transmission data as well When the SCOSBOS flag of the serial interface 0 mode register 1 POODC is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 0 Nch open drain control register POODC P01 is used as input pin of the serial 0 reception data or the UART 0 reception data as well P02 is used as I O pin of the serial O clock as well When the SCOSBTS flag of the serial interface 0 mode regis ter 1 SCOMDI is set to 1 it is output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the port 0 Nch open drain control register POODC P03 is used as output pin of the serial 2 transmission data or the IIC2 transmission data as well When the SC2SBOS flag of the serial interface 2 mode register 1 SC2MD1 is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 0 Nch open drain control register POODC P04 is used as input pin of the serial 2 reception data or the 2 reception data P05 is used as I O pin of the serial 2 clock as well When the SC2SBTS flag of the serial interface 2 mode regis ter 1 SC2MD1 is set to 1 it is output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the po
351. ally transmit Set data to TXBUF2 in the period that after data is loaded to internal shift register and before communication end interrupt SC2IRQ is generated In master communication communication blank from SC2IRQ generation to next transfer clock output is 4 transfer clock Automatic Continuous Transfer by the automatic data transfer function built in this LSI can activate Serial interface 2 It enables continuous transfer of data up to 255 byte For activation using refer to chapter 18 Automatic Transfer Controller Transfer mode 8 to 9 Input edge output edge Setup The 2 1 flag of the SC2MDO register sets the output edge of the transmission data and the input edge of the received data Data at transmission is output at the falling edge of clock as the SC2CEI flag 0 and at the ris ing edge of clock as the SC2CEI 1 Data at reception is input at the rising edge of clock as the SC2CEI 0 and at the falling edge of clock as the SC2CEI flag 1 Table 13 3 2 Input Edge Output Edge of Transmission and Reception Data SC2CE1 Transmission data output edge Received data input edge 0 1 Operation XIII 17 13 Serial Interface 2 Clock Setup Clock source is selected from the dedicated prescaler and timers 2 3 output 2 channels with the SC2PSC2 to 0 of the SC2MD3 register The dedicated prescaler is started by selecting count e
352. am is corrected as following steps 1 The instruction execution address is compared to the correction address 2 Program counter is branched indirectly to the RAM address the head address of the correct program stored to the RC vector table RCnV L RCnV H after matching the above addresses This instruction needs 6 cycle 3 The corrected program at the RAM area is executed 4 Program counter is branched back to the program at ROM area ROnV L RCnV H Lee When a match occurs the program counter branches indirectly to the start address of the correct program Correct program Development data label1 G Instruction X the head address to be corrected from the external EEPROM label2 44 JMP label2 _ recover internal ROM internal RAM Figure 2 3 1 ROM Correction ROM Correction Chapter 2 CPU Basics The ROM correction setup procedure is as follows 1 Set the head address of the program to be corrected to the ROM correction address setting register RCnAPH M L 2 Set the correct program at RAM area 3 Set the head address of the correct program to RC vector table RCnV L RCnV H 4 Set the RCnEN flag of ROM correction control register RCCTR to enable the ROM correction When the instruction of the corrected program head address is the half byte instruction th
353. ame time SCITIRQ is generated SCIREMP is cleared to 0 after RXBUFI is read out Operation XII 18 12 Serial interface 1 If a start condition is input to restart during communication the transmission data is not valid Set the transmission data to TXBUF1 again to operate the transmission again RXBUF1 is rewritten every time when communication is completed At continuous communi cation data of RXBUF1 should be read out until the next reception is completed Transfer Bit Count and First Transfer Bit When the transfer bit is 1 bit to 7bit the data storing method to the transmission data buffer TXBUFI is different depending on the first transfer bit selection At MSB first use the upper bits of TXBUFI for storing When there are 6 bits to be transferred as shown on Figure 12 3 2 if data A to are stored to bp2 to bp7 of TXBUFI the transmission is operated from F to A At LSB first use the lower bits of TXBUFI for storing When there are 6 bits to be transferred as shown on Figure 12 3 3 if data A to F are stored to bpO to bp5 of TXBUFI the transmission is operated from A to F TXBUF1 F E D C B TXBUF1 Figure 12 3 3 Transfer Bit Count and First Transfer Bit starting with LSB XII 14 Operation 12 Serial interface 1 Receive Bit Count and First Transfer Bit When the transfer bit count is
354. an interrupt ATC 1IIRQ occurs and the automatic transfer ends Operation XVIII 19 18 Automatic Transfer Controller 18 3 8 Transfer Mode 3 Ep usu OO O IMM In transfer mode 3 1 automatically transfers one byte of data from the I O space special registers 0x03F00 0x03FFF to any memory space everytime ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to 03FFF 1 ATMAP1 2 Only lower 8 bits are valid 1 2 3 Figure 18 3 5 Transfer Mode 3 Set the source I O address in lower 8 bits of memory pointer 1 ATIMAPIL and set the destination address in 20 bit memory pointer 0 ATIMAPOH L You do not have to set the upper 12 bits of the I O space address Ox3F in ATIMAPIH and ATIMAPIM In transfer mode 3 the value in memory pointer 0 increments everytime a byte length data transfer ends As a result the destination address for the next transfer is one address higher than that for the previous transfer Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt ATC 1IIRQ occurs and the automatic transfer ends XVIII 20 Operation 18 Automatic Transfer Controller 18 3 9 Transfer Mode 4 In
355. and Binary Counter Clear Source Timer 7 TM7MD2 register Interrupt source Binary counter clear source TM7IRS1 TM7BCR flag 1 1 TM7OC1 compare match TM7OC1 compare match 0 1 TM7OC1 compare match TM7OC1 compare match 1 0 TM7OC1 compare match Full count overflow 0 0 Full count overflow Full count overflow Timer 7 can generate another set of an independent interrupt Timer 7 compare register 2 match interrupt by the set value of the Timer 7 compare register TM7OC2 At that timer the binary counter is cleared as the above setup The compare register is double buffer type So when the value of the preset registers is changed during the count ing the changed value is stored to the compare register when the binary counter is cleared This function can change the compare register value constantly without disturbing the cycle during timer operation Reload func tion units even if it is a 16 bit MOVW instruction As a result it will read the data incorrectly if a carry from the lower 8 bits to the upper 8 bits occurs during counting operation To read the correct value of the 16 bit counting TM7BC use the writing program function to the input capture register TM71C By writing to the TM7IC the counting data of TM7BC can be stored to TM7IC to read out the correct counting value during timer operation chapter 6 9 1 Operation a When the CPU reads the 16 bit binary counter TM7BC the read
356. ansition to STANDBY Modes seen nennen nennen treten II 49 2 6 Clock Switching T A Asas Sie heed ets case sisted ee DIRE II 51 2 T Reset desse ttt Sia II 53 2 T tette s ER II 53 2 7 2 Oscillation Stabilization Wait time eese eene enne enne netten nete II 55 Chapter 5 Infermupls a so loe eb podio mes Deae an m i uu nha a III 1 III 2 3 TL T FUNCHONS IIS MH EE E h ES III 3 3 1 2 Block Diagram oit eet tee DERE RD REGERE III 4 3 1 3 Operation REUS ERA III 5 3 1 4 Interrupt Setup RU ee t iere pe E RR URL Ui s III 16 3 2 Control oe rt be Ner e eie eee eere ete III 17 3 22 Registers L1st23 N Sa S eae III 17 3 2 2 Interrupt Control Registers ana apasasduypa qia nennen nennen trees III 19 3 3 External Interrupts l eU UU NEU QU UO E UE e ens III 46 3 9 T ONeEVIeEW i s eraat pete qd e PD EIE ERR III 46 3 3 2 Block Diagram ee np m eee e tete aee t tec e III 47 3 3 3 Contro E edd rae es III 53 Contents 3 3 3 4 Programmable Active Edge III 60 3 35 Both Edges Interrupt edet tor Eee rig
357. art condition before input external clock Wait more than 3 5 transfer clocks before input the external clock after the data set to TXBUF3 This wait time is used for data loading from TXBUF3 to internal shift register Table 14 3 1 Synchronous Serial Interface Activation Source Activation source Transmission Reception Master Set the transmission data Set dummy data communication Input start condition Slave Input clock after the transmission Input clock after dummy data is set communication data is set Input clock after start condition is input B Transfer Bit Count Setup The transfer bit count can be selected from bit to 8 bits Set the SC3LNG 2 to 0 flag of the SC3MDO register at reset 111 The SC3LNG 2 to 0 flag holds the previous value until other value is set during communication At slave set data to SC3TRB or input start condition before input a The SBTS pin is masked inside serial interface to prevent operating errors by noise except clock to the TXBUF3 pin Wait more than3 5 transfer clocks before input the external clock after the data set to Y TXBUF3 Otherwise normal operation is not guaranteed XIV 14 Operation 14 Serial Interface 3 B Start Condition Setup Enable or disable of start condition can be selected with the SC3STE flag of SC3MDO register Start condition is detected when the SC3CEI flag of the SC3MDO register is set to
358. aster Clock slave SC4MD1 SC4MST Port pin P40 P41 P42 Serial data input 584 selection SC4MD1 SC4IOM Function Port Serial input Transfer clock input Transfer clock input output output P4DIR P4DIR0 SC4MD1 SC4SBIS SC4MD1 SC4SBTS Style Push pull Nch open Push pull Nch open drain drain P4ODC P4ODC2 Input mode Output mode Input mode P4DIR P4DIR1 P4DIR P4DIR2 Pull up setup Added Not added Added Not added P4PLU P4PLU2 Operation B Pins Setup with channels at transmission reception Chapter 15 Serial interface 4 Table 15 3 9 shows the setup for synchronous serial interface pin with 3 channels SBO4 pin SBI4 pin SBT4 pin at transmission reception Table 15 3 9 Setup for Synchronous Serial Interface Pin with 3 channels at transmission reception Setup item Data output pin Data input pin Clock I O pin SBOA pin SBI4 pin SBTA pin Clock master Clock slave SC4MD1 SC4MST Port pin P40 P41 P42 Serial data input SBI4 selection SC4MD1 SC4IOM Function Serial data output Serial input Transfer clock input Transfer clock input output output SC4MD1 SC4SBOS SC4MD1 SC4SBIS SC4MD1 SC4SBTS Style Push pull Nch open Push pull Nch open Push pull Nch open drain drain drain P4ODC P4ODC0 P4ODC P4ODC2 Output mode Input mode Output mode Input mode P4DIR P4DIR0 P4DIR P4DIR1 P4DIR P4DIR2 Pull up setup Added Not
359. ata input selection RXD4 SC4MD1 SC4IOM Function Serial data output Serial data input SC4MD1 SC4SBOS SC4MD1 SC4SBIS Style Push pull Nch open drain P4ODC P4ODC0 Output mode Input mode P4DIR P4DIR0 P4DIR P4DIR1 Pull up setup Added not added P4PLU P4PLU0 Operation XV 49 15 Serial interface 4 15 3 4 Setup Example B Transmission Reception Setup The setup example at UART transmission reception with serial 4 is shown Table 15 3 24 shows the condition at transmission reception Table 15 3 24 UART Interface Transmission Reception Setup Setup item SEtto TXD4 RXD4 pin Independent with 2 channels Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source Timer 2 TXD4 RXD4 pin type Nch open drain Pull up resistor of TXD4 pin Added Parity bit add check 0 added check Serial 4 transmission complete Enable interrupt Serial 4 reception complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the baud rate timer 1 Set the baud rate timer by the TM2MD register the 2 register Set the TM2EN flag to 1 to start timer 2 Chapter 5 5 9 Serial Transfer Clock Output Operation 2 Select the clock source 2 Set the bp2 to 0 flag of the SC4MD3 register to 110 to SC4MD3 0x03FAE select Timer 2 output as a clock s
360. ation low speed oscillation for two CPU oper ating modes NORMAL and SLOW each with two standby modes HALT and STOP Power consumption can be decreased with using those modes CPU operation mode STANDBY mode Interrupt sTOP0 NORMAL mode EOSC Hat Program 5 TE XI Oscillation NORMAL Reset OSC Oscillation y XI Oscillation HALTO EOSC Oscillatio E Oscillation Program 4 Program 3 STOP mode IDLE OSC Oscillation 1 HALT mode Program 2 Interrupt SLOW Oscillatior OSC Halt Programas XI Oscillation Z a Interrupt SLOW mode Program 4 CPU halt Wait period for oscillation stabilization is inserted OSC High frequency oscillation clock Xl Low frequency oscillation clock 32 kHz Figure 2 5 1 Transition Between Operation Modes Standby Function Chapter 2 CPU Basics HALT Modes HALT1 The CPU stops operating But both of the oscillators remain operational in HALTO and only the high frequency oscillator stops operating in HALTI An interrupt returns the CPU to the previous CPU operating mode that is to NORMAL from HALTO or SLOW from HALTI STOP Modes STOPO STOP1 The CPU and both of the oscillators stop operating An i
361. atus word PSW and handy addressing data are saved onto the stack And an interrupts handler ends by restor ing using the POP instruction and other means the contents of any registers used during processing and then exe cuting the return from interrupt RTI instruction to return to the point at which execution was interrupted Max 12 machine cycles before execution and max 11 machine cycles after execution Each interrupt has a interrupt control register which controls the interrupts Interrupt control register consists of the interrupt level field LV1 to 0 interrupt enable flag IE and interrupt request flag IR Interrupt request flag IR is set to 1 by an interrupt request and cleared to 0 by the interrupt acceptance This flag is managed by hardware but can be rewritten by software Interrupt enable flag IE is the flag that enables interrupts in the group There is no interrupt enable flag in non maskable interrupt NMI Once this interrupt request flag is set it is accepted without any conditions Interrupts enable flag is set in maskable interrupt Interrupt enable flag of maskable interrupt is valid when the maskable interrupt enable flag MIE flag of PSW is 1 Maskable interrupts have had vector numbers by hardware but their priority can be changed by setting interrupts level field There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowe
362. ax 64 KB for data Instruction data space External bus Address 20 bit Data 8 bit Minimum bus cycle 1 system clock cycle Interrupt Vector interrupt 3 interrupt levels Low power con STOP mode sumption mode HALT mode Overview 2 1 1 Block Diagram Chapter 2 CPU Basics Address registers A0 A1 Stack pointer SP ABUS BBUS Program counter Incrementer N Z Data registers D0 D1 D2 D3 ry Processor status word PSW Program address Operand address Y clksys Clock Source oscillation generator Instruction execution controller Instruction decoder Bus controller 1 ROM bus RAM bus Y External interface Internal ROM Internal RAM External expansion bus Figure 2 1 1 CPU Block Diagram y Instruction Interrupt queue controller Interrupt bus 1 Peripheral expansion wS T Internal peripheral functions Overview 1 3 2 CPU Basics 1 4 Table 2 1 2 Block Diagram Function Clock generator Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals to CPU blocks Program counter Generates addresses for the instru
363. be under 500 and the external capacitor C more than 1000 pF under 1 uF should be connected to it 2 The A D conversion frequency should be set in regard to C 3 At the A D conversion if the input level of microcontroller is changed or the peripheral added circuit is switched to ON OFF the A D conversion could work wrongly as the analog input pins and power pins cannot be fixed At the setup checking confirm the wave form of analog input pins a For high precision of A D conversion the following cautions on A D converter should be kept Equivalent circuit block that outputs analog signal microcontroller A D input pin Vss Figure 16 3 4 Recommended Circuit XVI 18 Operation Chapter 17 D A Converter 17 D A Converter XVII 2 17 1 Overview This LSI has a built in D A converter with 8 bits solution There is 1 output channel and 8 bit data registers for the channel This LSI supports D A conversion mode When the D A converter is not used the built in ladder resis tance can be set to OFF to save the power consumption 17 1 1 Functions Here is the list of D A converter functions Table 17 1 1 D A converter functions Resolution 8 bit Pin DAO pin Power consumption saving Built in ladder resistance ON OFF Overview 17 D A Converter 17 1 2 D A Converter Block Diagram DAOUT Reference voltage X DA0 P06 generation section D
364. bp 5 Flag SC2TEMP At reset 0 Access R Description SC2TEMP Transfer buffer empty flag 0 Empty 1 Full XIII 10 Control Registers Serial interface 2 Control Register SC2CTR 0 0 9 bp 7 6 5 4 3 2 1 Chapter 13 Serial Interface 2 0 Flag IICBSY IICSTG IICSTPC SC2TMD SC2REX SC2CMD SC2ACKS SC2ACK0 At reset 0 0 0 0 0 0 0 0 Access R IICBSY Description Serial bus status in IIC communication 0 Other use 1 Serial transmission is in progress IICSTC Start condition 1 0 Disable start condition 1 Enable start condition IICSTPC Stop condition detection flag in IIC communication 2 0 undetected 1 detected SC2TMD Communication mode 0 NORMAL mode 1 High speed mode SC2REX Transmission reception mode selection 0 Transmission 1 Reception SC2CMD Synchronous IIC selection 0 Synchronous 1 SC2ACKS ACK bit enable 0 Enable 1 Disable SC2ACK0 ACK bit level selection 3 0 L level 1 H level Control Registers XIII 11 13 Serial Interface 2 1 1 is not writable 2 This is not writable when the emergency reset of communication is not cancelled 3 The written data is not readable before generation of the IIC communication XIII 12 Co
365. c 64 fosc 128 fs 2 fs 4 timer 3 output timer 5 output The transfer rate is the clock source divided by 8 Activation factor for Communication Set data at transmission or dummy data at reception to the transmission reception shift register TXBUF3 Start condition and transfer clock are generated to start communication regardless of transmission reception This serial interface can not be used for slave communication B Start Condition Setup In IIC communication enable start condition by the SC3STE flag of the SC3MDO register at the first communica tion after reset release From the second communication the SC3STE flag of the SC3MDO register can select if start condition is enabled or not If start condition is detected during data communication in which the start condition is enabled the SC3STC flag of the SC3CTR register is set to 1 and the communication end interrupt SC3IRQ is generated to end the trans mission This means that the communication is not executed properly and needs to be re executed Clear the SC3STC flag by program When data line SDA3 pin is changed from to L while clock line the SCL3 pin 15 start condition is generated XIV 38 Operation 14 Serial Interface 3 Generation of Stop Condition Stop condition is generated as the SDA3 line is changed from L to H while the SCL3 line is H Stop condi tion can be generated by setting the IICSTPC flag of the SC
366. ccess to the special function register area 0x03F00 to OxOSFFF For access to the memory space 0x13F00 to Ox13FFF 0x23F00 to Ox23FFF 0x33F00 to OxS3FFF 0x43F00 to Ox43FFF 0x53F00 to 0x53FFF 0x63F00 to Ox63FFF 0x73F00 to Ox73FFF 0x83F00 to Ox83FFF 0x93F00 to Ox93FFF to 0xA3FFF 0xB3F00 to OxB3FFF 0xC3F00 to OxC3FFF 0xD3F00 to OxD3FFF 0xE3F00 to OxESFFF to OxF3FFF both instructions of register indirect and register relative indirect should be used Chapter 2 2 1 9 Addressing Modes Set the stack area to bank 0 Provided C compiler for this series does not support the bank function Our linker supports function that prevents data straddling over bank boundaries MN101C Series Cross assembler User s Manual for details 18 Memory Space Bank Register for Source Address Chapter 2 CPU Basics The SBNKR register is used to specify bank area for loading instruction from memory to register Once this regis ter is specified bank control is valid for all addressing modes except I O short instruction and stack relative indi rect instruction Chapter 2 2 1 9 Addressing modes Table 2 2 4 Bank Register for Source Address SBNKR 0x03F0A bp 5 4 3 2 1 0 Flag SBA3 SBA2 SBA1 SBAO At reset 0 0 0 0 Bank for source address selection bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 ba
367. cess R W R W R W R W bp Flag Description Transmission data output edge 0 falling 1 rising Reception data input edge 0 rising 1 falling SCOCE1 First bit to be transferred SCODIR 0 MSB first 1 LSB first Start condition selection SCOSTE 0 Disable start condition 1 Enable start condition Transfer bit 000 1bit 001 2bit SCOLNG2 010 3bit SCOLNG1 011 4bit SCOLNGO 100 5bit 101 6bit 110 7bit 111 8bit N Control Registers XI 11 Serial interface 0 Serial interface 0 Mode Register 1 SC0MD1 0x03F90 XI 8 7 6 5 4 3 2 0 SCOIOM SCOSBTS SCOSBIS SCOSBOS SCOCKM SCOMST SCOCMD 0 0 0 0 0 0 0 SCOIOM Description Serial data input selection 0 Data input from SBIO RXDO 1 Data input from SBOO TXDO SCOSBTS SBTO pin function selection 0 Port 1 Transfer clock I O SCOSBIS Serial input control selection 0 Input 1 1 Input serial SCOSBOS SBOO TXDO pin function 0 Port 1 Output serial data SCOCKM 8 cycle of transfer clock selection 0 No 8 cycle 1 8 cycle SCOMST Clock master slave selection 0 Clock slave 1 Clock master SCOCMD Control Registers Synchronous serial full duplex UART selection 0 Synchronous serial 1 full duplex UART 11 Serial interface 0 Serial interface 0 Mode Register 2 SC0MD2 0x03F9
368. ch Open drain Control Register P9ODC 0x03F4C Flag P9ODC5 P9ODC3 P9ODC2 P9ODCO At reset 0 0 0 0 Access R W R W R W R W bp O gt O Q O IV 92 Port 9 P9ODC5 P9ODC3 P9ODC2 P9ODC0 Flag Description Nch open drain output selection 0 Push pull output 1 Nch open drain output 4 11 3 Block Diagram Nch open drain control Pull up resistor control direction control Port output data Port input data Serial 0 reception data input Serial 0 UART 0 transmission data output SCOMD SCOSBOS Pull up resistor control direction control Port output data Port input data snq eq Serial 0 UART 0 reception data input snq Schmitt trigger input Figure 4 11 1 P90 Block Diagram Reset A P9PLU1 Reset A P9DIR1 P9OUT1 P9IN1 Schmitt trigger input Chapter 4 I O Ports P90 P91 Figure 4 11 2 P91 Block Diagram Port 9 IV 93 4 I O Ports t amp P9ODC2 Nch open drain control y Y Pull up resistor control Y U direction control pd P9DIR2 Port output data 9 c N E 9 2 Yo gt gt x Schmitt trigger input
369. ck Diagram prq P2PLus s R Reset _ 2 5 2 WEK R Y P25 5 p 209 5 amp wek R LET Schmitt trigger input lt P2IN5 R Port output data Port input data Reset Chapter 4 I O Ports Y AAA P27 E P2OUT7 5 gt I5 WEK R LIT Schmitt trigger input q P2IN7 lt 1 lt J R Figure 4 4 7 P27 Block Diagram Port 2 IV 38 4 I O Ports IV 34 4 5 Port3 4 5 1 Description General Port Setup To output the data to pins set the control flag of the port 3 direction control register P3DIR to 1 to write the value of the port 3 output register To read input data of pins set the control flag of the port 3 direction control register P3DIR to 0 to read the value of the port 3 input register P3IN Each bit can be set individually as either an input or output by the port 3 I O direction control register P3DIR The control flag of the port 3 direction control register P3DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 3 pull up resistor control register P3PLU Set the control flag of the port 3 pull up resistor control register P3PLU to 1 to add pull up resistor P30 P32 P33 and P35 can select the Nch open dr
370. clock after start condition is input B Transfer Bit Setup The transfer bit count is selected from 1 to 8 bits Set them by the SCILNG 2 to 0 flag of the SCIMDO register at reset 111 The SCILNG2 to 0 flag holds the former set value until it is set again Except during communication SBT1 pin is masked to prevent errors by noise At slave com Y munication set data to 1 or input a clock to SBT1 pin after a start condition is input To communicate properly more than 3 5 transfer clock after the data to TXBUF1 is Y needed to input the external clock Operation 12 Serial interface 1 B Start Condition Setup The SCISTE flag of the SCIMDO register sets if a start condition is enabled or not The start condition is regarded that when SCICEI flag of SCIMDO is set to 0 and a clock line SBTI pin is H data line SBII pin with 3 lines or SBOI pin with 2 lines is changed from H to L Also it is regarded that when SCICEI flag is set to 0 and a clock line SBT1 pin is L data line SBII pin with 3 lines or SBO1 pin with 2 lines is changed from H to L Both the SC1SBOS flag and the SCISBIS flag of the SCIMDI register should be set to 0 before the start con dition setup is changed At the selection of the start condition enable and master transmission reception after the start condition output start condition is input from the slave then data transmi
371. control register DLYCTR is set to 1 the buzzer output is enabled PD6 is uses as output pin of the system clock at the processor mode or the memory extension mode These modes are set to the output mode automatically IV 106 Port D Chapter 4 I O Ports 4 13 2 Registers The following Table shows registers that control the Port D Table 4 13 1 Port D control register Registers Address Function PDOUT 0x03F1D Port D Output Register PDIN 0x03F2D Port D Input Register IV 108 PDDIR 0x03F3D R W Port D Direction Control Register IV 108 PDPLU 0x03F4D R W Port D Pull up Resistor Control Register IV 109 PDOMD 0x03F1B R W Port D Output Mode Register IV 109 R W Readable Writable Port D Output Register PDOUT 0x03F 1D p CF F E p T p At reset Access R W RAN R W R W R W R W R W R W bp Flag Description Output data 0 Output L VSS level 1 Output H VDD level O Q O Port D IV 107 4 I O Ports Port D Input Register PDIN 0x03F2D bp Flag Description 7 PDIN7 6 PDIN6 Input data 0 Pin is L VSS level 3 PDAS 1 Pin is H VDD level 2 PDIN2 FINIS ELWODD level 1 PDIN1 0 PDIN0 Port D Direction Control Register PDDIR 0x03F3D IV 108 Flag PDDIR7 PDDIR6 PDDIR5 PDDIR4 PDDIR3 PDDIR2 PDDIR1 PDDIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W b
372. ct the normal timer operation b Select the prescaler output to the clock source by the 1 2 to 0 flag of the TM1MD register 6 Select fs 2 to the prescaler output by the TM1PSC1 to 0 and TM1BAS flag of the timer 1 prescaler selection register CK1MD 7 Set the synchronous output generation cycle to the timer 1 compare register 1 The setting value is set to 100 1299 0x63 because 1 MHz is divided by 10 KHz At that time the timer 1 binary counter TM1BC is initialized to 0x00 8 Set the TM1EN flag of the TM1MD register to 1 to operate the timer 1 e TMIBC counts up from 0x00 If any data is written to the port 7 output register P7OUT the data of port 7 is output from the synchronous output pin in every time an interrupt request is generated by the match of and the set value of the TM1OC register Synchronous Output 5 8 bit Timers 5 9 Serial Transfer Clock Output 5 9 1 Operation Serial transfer clock can be created by using the timer output signal Serial transfer clock operation by 8 bit timer Timers 2 3 4 and 5 Timer 2 Serial interface 0 2 and 4 Timer 3 Serial interface 2 and 3 Timer 4 Serial interface 0 1 Timer 5 Serial interface 1 3 and 4 Timing of Serial Transfer Clock Timers 2 3 4 and 5 Count Compare register e AEAEE counter Interrupt request flag Timer output Serial
373. ction register direct and immediate can be used Refer to instruction s manual for the MN101E series This LSI is designed for 8 bit data access It is possible to tranfer data in 16 bit increments with odd or all even addresses Overview 13 2 CPU Basics 1 14 Addressing mode Register direct Immediate Register indirect Dn DWn An SP PSW imm4 imm8 imm16 An Effective address Explanation Directly specifies the register Only internal registers can be specified Directly specifies the operand or mask value appended to the instruction code 15 0 Specifies the address using an address register Register relative indirect Stack relative indirect Absolute RAM short short Overview d16 An d4 PC i branch instructions only d7 PC d11 PC branch instructions only Speci counter with 12 bit displacement and H bit d12 PC i branch instructions only d16 PC i branch instructions only d4 SP d8 SP d16 SP abs8 abs18 i branch instructions only abs 20 branch instructions only Speci counter with 11 bit displacement and H bit branch instructions only 0 An d16 17 OH ______ 4 17 0 _____ 7 _____ 17 OH PC d11 17 OH PC d12 15 0 15 0 SP d8 15 0 SP d16 15
374. ction 5 2 01 5 210 Function Port Serial data input Transfer clock I O Transfer clock I O SC2MD1 SC2SBOS SC2MD1 SC2SBIS SC2MD1 SC2SBTS Type Push pull N ch open Push pull N ch open drain drain POODC POODC5 Input mode Output mode Input mode PODIR PODIR4 PODIR PODIR5 Pull up added not added added not added POPLU POPLUS Operation XIII 27 13 Serial Interface 2 XIII 28 Pins Setup 3 channels at reception transmission Table 13 3 8 Synchronous Serial Interface Pins Setup 3 channels at transmission reception Item Data output pin Data input pin Clock I O pin 5802 pin SBI2 pin SBT2 pin Clock master Clock slave Pin P04 P05 Serial data input SBI2 selection SC2MD1 SC2IOM Function Serial data output Serial data output Transfer clock I O Transfer clock I O SC2MD1 SC2SBOS SC2MD1 SC2SBIS SC2MD1 SC2SBTS Type Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain POODC POODC3 POODC POODC5 Output mode Input mode Output mode Input mode PODIR PODIR3 PODIR PODIR4 PODIR PODIR5 Pull up added not added added not added added not added POPLU POPLUS POPLU POPLUS B Pins Setup 2 channels at transmission Table 13 3 9 shows the pins setup at synchronous serial interface transmission with 2 channels SBO2pin SBT2 pin The SBI2 pin is
375. ctions are fetched in 1 byte units and temporarily stored in the 2 byte instruction queue Transfer is made in 1 byte or half byte units from the instruction queue to the instruction register to be decoded by the instruction decoder 7 0 Cr _ mi Memory B 15 0 1 byte or a half byte Instruction register NE Instruction decoder Instruction decoding CPU control signals Instruction queue Figure 2 1 2 Instruction Execution Controller Configuration Overview Chapter 2 CPU Basics 2 1 4 Pipeline Process IO s M s O II r Pipeline process means that reading and decoding are executed at the same time on different instructions then instructions are executed without stopping Pipeline process makes instruction execution continual and speedy This process is executed with instruction queue and instruction decoder Instruction queue is buffer that fetches the second instruction in advance That is controlled to fetch the next instruction when instruction queue 15 empty at each cycle on execution At the last cycle of instruction execution the first word operation code of executed instruction is stored to instruction register At that time the next oper and or operation code is fetched to instruction queue so that the next instruction can be executed immediately even if register direct da or immediate data imm is needed at the first cycle of the next instruction executio
376. ctions to be inserted into the instruction queue Normally incremented by sequencer indication but may be set to branch destination address or ALU operation result when branch instructions or interrupts occur Instruction queue Stores up to 2 bytes of pre fetched instructions Instruction decoder Decodes the instruction queue sequentially generates the control signals needed for instruction execution and executes the instruction by controlling the blocks within the chip Instruction execution controller Controls CPU block operations in response to the result decoded by the instruction decoder and interrupt requests ALU Executes arithmetic operations logic operations shift operations and calculates operand addresses for register relative indirect addressing mode Internal ROM RAM Assigned to the execution program data and stack region Address register Stores the addresses specifying memory for data transfer Stores the base address for register relative indirect addressing mode Data register Holds data for operations Two 8 bit registers can be connected to form a 16 bit register Interrupt controller Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing Bus controller Controls connection of CPU internal bus and CPU external bus Includes bus usage arbitration function Internal peripheral functions Includes peri
377. ctric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 lndia Sales Office National Panasonic India Ltd NPI E Block 510 International Trade Tower Nehru Place New Delhi_110019 INDIA Tel 91 11 629 2870 91 11 629 2877 Indonesia Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 62 21 801 5675 China Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin Co Ltd PI TJ Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 CHINA Tel 86 22 2313 9771 Fax 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 7 107 International Bussiness amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 CHINA Tel 86 755 8359 8500 Fax 86 755 8359 8516 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai HONG KONG Tel 852 2529 7322 Fax 852 2865 3697 e Taiwan Sales Office Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 TAIWAN Tel 886 2 2757 1900 Fax 886 2 2757 1906 Kaohsiung Office
378. d of the final bit can be set as Table 11 3 5 by the setting value of the SCOFDCI to 0 flag of the SCOMD3 register After released the reset despite of the setting value of the SCOFDCI to 0 flag output before the serial transfer is H In the case of the enabled start condition at SCOSTE flag 1 is output despite of the setting value of the SCOFDCI to 0 Table 11 3 5 SBOO Output after the Data Output Holding Period of the Last Bit without start condition SBOO output after the data SCOFDC1 flag SCOFDCO flag output holding period of the last bit 0 0 High output fix 1 0 O Low output fix 0 1 Last data holding 1 1 Reserved Operation 11 Serial interface 0 Other Control Flag Setup Table 11 3 6 shows flags that are not used at clock synchronous communication So they are not needed to set or monitor Table 11 3 6 Other Control Flag Register Flag Detail SC0MD2 SCOBRKE Break status transmission control SCOBRKF Break status reception monitor SCONPE Parity enable SCOPM to 0 Added bit specification SCOFM1 to 0 Frame mode specification SCOSTR SCOPEK Parity error detection SCOFEF Frame error detection Operation XI 21 11 Serial interface 0 B Transmission Timing At master At slave Tmax 25T T gt 2 _ a a U as Clock SBTO pin Output pin SBOO pin Transfe
379. d by setting data to the transmission data buffer TXBUF4 When the trans mission is completed the serial 4 transmission interrupt SCATIRQ is generated Reception Once a start condition is received reception is started after the transfer bit counter that counts transfer bit is cleared When the reception is completed the serial 4 reception interrupt SCARIRQ is generated Full duplex communication On full duplex communication the transmission and reception can be operated separately at the same time The frame mode and parity bit of the used data on transmission reception should have the same polarity B Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SCAFMI to 0 flag of the SCAMD2 register If the SCACMD flag of the SCAMDI register is set to 1 and UART communication is selected the setup by the synchronous serial transfer bit count selection flag SCALNG2 to 0 is no more valid Data Input Pin Setup The communication mode can be selected from with 2 channels data output pin TXD4 pin data input pin RXD4 pin or with 1 channel data I O pin TXD4 pin The RXD4 pin can be used only for serial data input The TXD4 pin can be used for serial data input or output The SC4IOM flag of the SCAMDI register can specify which pin RXD4 or TXD4 inputs the serial data If data input from TXD4 pin is selected to be with 1 line com munication transmission reception is
380. d everytime when activated The value in memory pointer 0 increments by one each time a byte length data transfer ends As a result the destina tion address for the next 1 operation is two addresses higher than that for the previous operation In this word length transfer 1 transfers the first data byte from an even address in the I O space and the sec ond data byte from an odd address in the I O space Set the data transfer count for 1 in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an 1 is activated after each word transfer When it reaches 0x00 an interrupt ATCIIRQ occurs and the automatic transfer ends XVIII 22 Operation 18 Automatic Transfer Controller 18 3 11 Transfer Mode 6 In transfer mode 6 ATC1 automatically transfers one byte of data two times everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to 03FFF 1 1 2 ue m 3 Only lower 8 bits valid 4 1 2 3 Figure 18 3 8 Transfer Mode 6 In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer In the first data byte transfer the I O space address 0x03F00 in memory pointer 1 is the source address and the address in memory po
381. data is handled in 8 bits To count properly do not switch the count clock on the timer operation To switch the count Y clock stop the timer operation Operation Table 6 3 2 shows clock source that can be selected Table 6 3 2 Clock Source at Timer Operation Timer 7 Clock source 1count time fosc 50 ns fosc 2 100 ns fosc 4 200 ns fosc 16 800 ns fs 100 ns fs 2 200 ns fs 4 400 ns fs 16 1 6 us fosc 20 MHz fs fosc 2 10 MHz Count Timing of Timer Operation Timer 7 Chapter 6 16 bit Timer The binary counter counts up with the selected clock source as the count clock The basic operation of whole 16 bit timer functions is as below TM7EN flag Preset register A Compare register Binary counter 0000 A A B E Interrupt request flag Figure 6 3 1 Count Timing of Timer Operation Timer 7 Count Clock A When a data is written to the preset register while the TM7EN flag is stopped 0 the same value is loaded during the writing cycle and the binary counter is cleared to 0x0000 B When TM7EN flag is 1 the binary counter starts counting The counting starts at the rising edge of the count clock C Even if the preset register is rewritten when the TM7EN flag is 1 the binary counter is not changed D When the binary counter reaches value of compare register 1 the set value of the
382. dis PD5 87 BUZZER abled high impedance output PD6 88 SYSLK PD7 90 1 14 Pin Description 1 Overview Name NO Other Function Function Description SBOOA 4 VO TXDOA Serial interface Transmission data output pins for serial interface 0 to 4 SBOOB 76 P90 TXDOB transmission The output configuration either COMS push pull or n channel SBO1 33 P30 TXD1 reception data I O open drain can be selected with the POODC PSODC P4ODC SBO2 7 SDA2 pins and P9ODC registers SBO3A 36 P33 SDA3A Pull up and pull down registers can be selected by the POPLU SBO3B 79 P93 SDA3B P3PLU P4PLU and P9PLU registers Select the output mode at SBO4 72 P40 TXD4 the PODIR P3DIR P4DIR and P9DIR registers and serial data output mode by serial mode register 1 SCOMD1 SC1MD1 SC2MD1 SC3MD1 SC4MD1 These can be used as normal I O pins when the serial interface is not used SBIOA 5 Input P01 RXDOA Serial interface Received data output pins for serial interface 0 to 4 SBIOB 77 P91 RXDOB received data Pull up and pull down resistors can be selected by the POPLU SBI1 34 P31 RXD1 input pins P3PLU P4PLU and P9PLUregisters Select input mode by the SBI2 8 P04 PODIR P3DIR P4DIR and P9DIR registers and serial output SBI3A 37 P34 mode by the serial mode register 1 SCOMD1 SC1MD1 SBI3B 80 P94 SC2MD1 SC3MD1 SC4MD1 SBI4 73 P41 RXD4 These can be used as normal I O pins when the serial interface is n
383. dure 2 TM1ICR Ox03FEQ9 bp1 TM1IE 0 VI 4 Table Change Timer 7 binary counter lower 8 bit Timer 7 compare register 2 match interrupt 6 2 1 control register VI 20 Table Deletion Setup Procedure 3 Setup Procedure 3 TMSEL7 TMSEL VIII 5 1 Change RMCTR 0x03F6E RMCTR 0x03F7F lt Record of Changes 2 gt Page Section ur Previous Edition Ver 0 65 New Edition Ver 0 7 8 Table Change Setup Procedure 6 Setup Procedure 6 bp6 TMOPOP 0 Description 6 Description 6 Set the TMOPWM flag of the TMOMD regis Set the TMOPWM flag and TMOMOD flag of ter the TM0MD register XIV Figure Change Write data to TXBUF2 Write data to TXBUF3 44 45 14 3 21 14 3 22 XV Table Change TM50G TM5OC 45 15 3 19 XVI 6 Table Change bp6 bp6 bottom 1 PD1 P23 L level 1 P23 PD1 Falling edge XVI Table Change fxx2 fxx2 10 16 3 2 XVI 3 Change and the sampling hold time is setto and the sampling hold time is set to 15 TAD x 2 TAD x 6 XVIII Figure Change 5 18 1 1 Record of Changes 3 MN101E01K 01L 01M F01M LSI User s Manual January 2003 Ver 0 7 Issued by Matsushita Electric Industrial Co Ltd O Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617
384. e ROM correction checks the execution instruction of the half byte Therefore set the address by a byte to the ROM correction address setting register When the instruction of the corrected program last address is the half byte instruction the recover address should be set by half byte ROM Correction 29 2 CPU Basics 2 3 3 ROM Correction Control Register ROM correction control register RCCTR and ROM correction address setting register RCnAPL RCnAPM RCnAPH control the ROM correction ROM correction control register RCCTR enables disables the ROM correction function to 3 parts of the pro gram to be corrected When the RCnEN flag 15 set the ROM correction is activated And when the ROM address the instruction execution address reaches the set address to the ROM correction address setting register it branches indirectly to the RAM address set on the RC vector table RCnV L RCnV H Set the RCnEN flag after setting the ROM correction address setting register ROM Correction Control Register RCCTR Table 2 3 1 ROM Correction Control Regiser RCCTR 0x03F09 bp 7 6 5 4 3 2 1 0 Flag 2 RC1EN RCOEN At reset 5 z 0 0 0 Access R W 3rd address ROM correction control 0 disable 1 enable 2nd address ROM correction control 0 disable 1 enable 1st address ROM correction control 0 disable 1 enable Thi
385. e clock cycle or lower to the external clock by the SC4MD3 register Table 15 3 3 Synchronous Serial Interface Clock Source serial 4 Clock source fosc 2 internal clock fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 2 output Timer 5 output When the clock setup is switched the SC4SBIS flag and SCASBOS flag of the SC4MD1 reg Y ister should be set to 0 When the slave reception is done with enabled start condition set the speed of the transfer Y clock slower than the system clock B Operation XV 17 15 Serial interface 4 XV 18 m Data Input Pin Setup 3 channels type clock pin SBT4 pin data output pin SBO4 pin data input pin SBIA pin or 2 channels type clock pin SBT4 pin data I O pin SBO4 pin can be selected as a communication mode 14 pin can be used for only serial data input SBO4 pin can select serial data input or output The SC4IOM flag of the SCAMDI reg ister can select if the serial data is input to SBI4 pin or SBO4 pin When data input from SBO4 pin is selected to set the 2 lines type the PADIRO flag of the PADIR register controls direction of SBO4 pin to switch transmis sion reception At this time SBI4 pin can be used as a general port too The transfer speed should be up to 5 0 MHz If the transfer clock is over 5 0 MHz the trans Y mission data may not be sent correctly At reception if SC4IOM of t
386. e with a description of each step is shown below interrupt interrupt External interrupt O P20 IRQO input Pulse width to be measured Figure 6 9 3 Pulse Width Measurement of External Interrupt 0 Setup Procedure Description 1 Stop the counter TM7MD 1 0x03F 78 bp4 TM7EN 0 2 Disable the interrupt IRQOICR OxOSFE2 bp1 IRQOIE 0 3 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 4 Select the count clock source TM7MD 1 0x03F78 bp1 0 TM7CK1 0 200 bp3 2 TM7PS1 0 200 5 Set the compare register TM7PR1 0x03F75 0x03F74 0xFFFF 6 Select the capture trigger generation interrupt source TM7MD2 0x03F79 bp1 0 7ICT1 0 200 7 Select the capture trigger generation edge TM7MD1 0x03F78 bp6 7ICEDG1 1 TM7MD2 0x03F79 bp7 T7ICEDGO 1 1 1 Set the TM7EN flag of the Timer 7 mode register 1 TM7MD1 to 0 to stop the Timer 7 counting 2 Set the IRQOIE flag of the IRQOICR register to 0 to disable the interrupt 3 Set the TM7BCR flag of the Timer 7 mode register 2 TM7MD2 to 1 to select the compare match as the binary counter clear source 4 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing of fosc as the count clock source by the TM7PS1 to 0 flag 5 Set OxFFFF to the Timer 7 preset register 1 TM7PR1 At that time the same value is loaded to the Timer 7 compare register 1 TM7OC1 the Timer
387. e SC3PSCE of the 5 register The SC3MST flag of the SC3MDI register selects the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock with same frequency to the external clock with the SC3MD3 register as the interrupt flag SC3IRQ is generated by the internal clock 14 3 3 shows the internal clock source which can be set with the SC3MD3 register Table 14 3 3 Synchronous Serial Interface Inside Clock Source Serial 3 Clock source fosc 2 Internal clock fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 fs 2 fs 4 timer 3 output timer 5 output a Set 0 to the SC3SBIS and SC3SBOS flags of the SC3MD register before change the clock setup Set transfer clock frequency in slave reception in which start condition is to be smaller than Y that of the system clock Switch the used pins Switch the used pins to A SBO3A SBI3A SBT3A B SBO3B 5 SBT3B by SC3SEL flag of SCSEL register Data Input Pin Setup There are 2 communication modes to be selected 3 channels clock pin SBT3 pin data output pin SBO3 pin data input pin SBI3 pin 2 channels clock pin SBT3 pin data I O pin SBO3 pin The SBI3 pin can be used only for serial data input The SBO3 pin can be used for serial data input and output The SC3IOM flag of the SC3MDI regist
388. e e ole piede III 61 3 3 6 Level Interrupt a s err 63 3 3 7 Key Input Interr pt diee maie eerie III 65 3 9 8 Noise Filter bete a E 66 3 3 9 External Interrupt At The Standby Mode seen III 69 Chapter 4 Ports ir viet OU veto bet qe IV 1 OVerVIe Were toU EU eee diate th aiding Du D DOS IV 2 4 1 1 O0 Poft OVerviIeW ope eh eret ree e liq dieere IV 2 4 1 2 Port Status at tenete netten IV 2 4 13 Control Registers a i cederent ferire rt e eani eee des IV 4 Lv In ai Saa IV 6 42 1 Descnptonz i gane eunte RR d dedu n S IV 6 4 2 2 E e ce a po ei EE ges eerte Sana eer PEE IV 7 4 23 Block Diagram ier tee eei irre eg edt e as IV 10 4 3 P0Et T iE EIE D di ram RO IV 14 4 3 1 Desc Ap ON te ERR RE E RU IV 14 432 aeo EUR te is eie ds bed eei ips nete ete etes IV 15 4 3 3 Block Diagra ug ms s D eau eh PIPER RE IV 20 4 4 Pott ER Su SI Su uY IV 26 4 4 1 DesenptiOD soe erp E eR UE UE IV 26 4 42 R glSletS iet ste on I REED CERERI DE RU IV 27 44 3 Block Diagram ss isi Re RE red eese eiit quieti rte etie erede IV 30 AS POEUS iie teta Go ee S Em Een IV 34 4 5 1 Deseription inier ore HR DURO PETERS GR
389. e interrupt TM6ICR 0x03FEE bp1 TM6IE 1 8 Start the TM6 operation TM6BEN 0x03F6C bp0 TM6EN 1 1 Set the TM6CLRS flag of the timer 6 mode register TM6MD to 0 At the time the initialization of the timer 6 binary counter TM6BC is enabled 2 Set the TMGIE flag of the TM6ICR register to 0 to disable the interrupt 3 Clock source can be selected by the TM6CKS3 to 1 flag of the TM6MD register Actually fs is selected 4 Set the interrupt generation cycle to the timer 6 compare register TM6OC At that time TM6BC is initialized to 0x00 5 Set the TM6CLRS flag of the TM6MD register to 1 to enable the interrupt request generation 6 Set the interrupt level by the TM6LV1 to 0 flag of the timer 6 interrupt control register TM6ICR If the interrupt request flag may be already set clear them Chapter 3 3 1 4 Interrupt Flag Setup 7 Set the flag of the TM6ICR register to 1 to enable the interrupt 8 Set the TM6EN flag of the TM6BEN register to 1 to start the timer 6 As TM60C is set TM6BC is initialized to 0x00 to count up When TM6BC matches the timer 6 interrupt request flag is set at the next count clock and TM6BC is cleared to 0x00 to restart counting 8 bit Free running Timer VII 7 Time Base Timer Free running Timer If the TM6CLRS flag of the TM6MD register is set to 0 TM6BC can be initialized at every rewriting of
390. e selected to address output pin to the external extension memory or the general port pin at the mem ory extension mode by the address output control register EXADV Special Function Pin Setup P70 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P71 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P72 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set
391. e serial 3 clock as well When the SC3SBTS flag of the serial interface 3 mode regis ter 1 SC3MDI is set to 1 it is output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the port 3 Nch open drain control register PSODC Port 3 Chapter 4 I O Ports 4 5 2 Registers The following Table shows registers that control the Port 3 Table 4 5 1 Port 3control register P3OUT 0x03F13 Port 3 Output Register IV 35 P3IN 0x03F23 Port 3 Input Register IV 36 P3DIR 0x03F33 R W Port 3 Direction Control Register IV 36 P3PLU 0x03F43 RAN Port 3 Pull up Resistor Control Register IV 37 P3ODG OxOSF2C R W Port 3 Nch Open drain Control Register IV 37 R W Readable Writable Port 3 Output Register PSOUT 0xOSF13 2 EET E E TF p TT At reset Access R W R W R W R W R W R W Flag Description P3OUT5 P3OUT4 P30UT3 P30UT2 P30UT1 P30UTO Output data 0 Output L VSS level 1 Output H VDD level O S O Q O Port 3 IV 35 4 I O Ports Port 3 Input Register P3IN 0x03F23 bp Flag Description 7 6 Input data 0 Pin is L VSS level 3 FSINS 1 Pin is H VDD level 2 P3IN2 1 P3IN1 0 P3IN0 Port 3 Direction Control Register P3DIR 0x03F33 Flag P3DIR5 P3DIR4 P3DIR3 P3DIR2 P3DIR1 P3DIR0 At reset 0 0 0 0 0 0
392. e to NORMAL mode after oscillation Note Procedures 5 to 8 10 to 11 and 12 to 13 can be set at once For slave reception in STANDBY mode disable the start condition With other setup normal a reception is not guaranteed Set each flag in order of the setup procedures Set all the control registers refer toTa a ble 13 2 1 except TXBUF2 before start communication Operation XIII 35 13 Serial Interface 2 13 3 3 Single Master IIC Serial Interface aun nn VV n Serial interface 2 is capable of IIC serial communication in single master Communication of this IIC interface is based on the IIC BUS data transfer format of Philips Table 13 3 13 shows the functions of IIC serial interface Table 13 3 13 IIC Serial Interface Functions Communication type Single master IIC Interrupt SC2IRQ Pins SDA2 SCL2 Transfer bit count 1 to 8 bit First transfer bit ACK bit ACK bit level O Clock source fosc 2 fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 fs 2 fs 4 timer 2 output timer 3 output The transfer rate is the clock source divided by 8 1 Transfer rate needs to be set to slower rate than the system clock fs m Activation factor for Communication Set data at transmission or dummy data at reception to the transmission reception shift register TXBUF2 Start condition and transfer clock are generated to start communica
393. ead input data of pins set the control flag of the port 5 direction control register PSDIR to 0 to read the value of the port 5 input register PSIN Each bit can be set individually as either an input or output by the port 5 I O direction control register P5DIR The control flag of the port 5 direction control register P5DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 5 pull up resistor control register PSPLU Set the control flag of the port 5 pull up resistor control register PSPLU to 1 to add pull up resistor Special Function Pin Setup P50 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically P51 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically P52 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically P53 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output modes automatically P54 is address output pin to the external extension memory at the processor mode or the memory extension mode These modes are set to the output
394. eception Chapter 11 Serial interface 0 Table 11 3 8 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO pin SBTO pin at reception Table 11 3 8 Setup for Synchronous Serial Interface Pin with 3 channels at reception Setup item Data output pin Data input pin Clock I O pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOMD1 SCOMST Port pin P00 P90 1 91 02 92 Port selection Select used pin A B SCSEL SC0SEL SBIO SBOO selection SBIO SBOO independent SCOMD1 SCOIOM Function Port Serial data input Serial clock input Serial clock input output output SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Style Push pull Nch open Push pull Nch open drain drain POODC POODC2 PSODC P9ODC2 Input mode Output mode Input mode PODIR PODIR1 PODIR PODIR2 PSDIR P9DIR2 PSDIR P9DIR1 Pull up setup Added Not added Added Not added POPLU POPLU2 P9PLU P9PLU2 Operation XI 29 11 Serial interface 0 XI 30 B Pins Setup with channels at transmission reception Table 11 3 9 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO pin SBTO pin at transmission reception Table 11 3 9 Setup for Synchronous Serial Interface Pin with 3 channels at transmission reception
395. ed serial 4 communication complete Enable interrupt SBO4 output after last data output 1 H fix An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation 1 Set the SC4PSCE flag of the SC4MD3 register to 1 to SC4MD3 0x03FAE select prescaler operation bp3 SC4PSCE 1 2 Select the clock source 2 Set the SC4PSC2 to 0 flag of the SCAMDS register to SC4MD3 0x03FAE 100 to select the fs 2 to clock source bp2 0 SC4PSC2 0 100 3 SBO4A output control after the last data 3 Set the SC4FDC1 to 0 flag of the SCAMDS register to output 00 to select 1 High fix of the SBO4 last data SC4MD3 0x03FAE output bp7 6 SC4FDC1 0 00 XV 32 Operation 15 Serial interface 4 Setup Procedure Description 4 Control of pin type P4ODC 0x03F3C bp2 P4ODC2 1 1 P4PLU 0x03F44 b2 P4PLU2 1 bp0 P4PLU0 1 5 Control the pin direction P4DIR 0x03F34 bp2 P4DIR2 1 bp1 P4DIR1 0 bp0 P4DIR0 1 6 Set the SCAMDO register Select the transfer bit count SC4MD0 0x03FAB bp2 0 SC4LNG2 0 111 Select the start condition SC4MD0 0x03FAB bp3 SCASTE 0 Select the first bit to be transferred SC4MD0 0x03FAB bp4 SC4DIR 0 Select the transfer edge SC4MD0 0x03FAB bp7 SC4CE1 1 7 Set the SC4MD1 register Select the communication style SC4MD1 0x03FAC bp0
396. ed again At recep tion the SDA line is automatically released to wait for reception After the storage of data is finished confirma tion of the reception ACK bit is output Figure 14 3 21 Master Transmission Timing Figure 14 3 22 Master Reception Timing B IIC BUSY Flag Operation As data is set to the transmission reception shift register TXBUF3 the IICBSY flag of the SC3CTR register is set to 1 then the IICBSY flag is cleared to 0 at transmission reception end communication with ACK or at last bit communication end communication without ACK Setting 1 to the stop condition generation flag IIS TPC sets IICBSY flag to 1 After stop condition ends it is cleared to 0 If start condition is detected during communication the communication end interrupt SC3IRQ is generated and the IICBSY flag is automatically cleared B Forced Reset You can shut down the communication by setting both of the SCOSBOS flag and the SCOSBIS flag of the SCOMDI register to 0 the SBOO pin function port input data input 1 When a forced reset is done the status register all flag of the SC2STR register and SC2BSY flag of the SC2MDO register are cleared but other control registers hold their set values Forced reset is operated at IICBSY is And generate the stop condition and end the communication XIV 42 Operation 14 Serial Interface 3 B First Transfer Bit Setup Refer to XIV 15 Transmission Rec
397. ed before reading the receive buffer SC4PEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 When parity bit is 0 Odd parity The total of 1 of parity bit and character bit is even Even parity The total of 1 of parity bit and character bit is odd SC4FEF Framing error Stop bit is not detected B Judgement of Break Status Reception Reception at break status can be judge If all received data from start bit and stop bit is 0 the SCABRKF flag of the SC4MD2 register is set and regards the break status The SCABRKF flag is set at generation of the reception complete interrupt SCARIRQ Operation XV 41 15 Serial interface 4 Continuous Communication This serial interface has continuous communication function If data is set to the transmission data buffer TXBUFA during communication the transmission buffer empty flag SCATEMP is set to continue automatic com munication This does not generate any blank in communication Set data to TXBUF between previous data setup and generation of the communication complete interrupt SCATIRQ Clock Setup Transfer clock is not necessary for UART communication itself but necessary for setup of data transmission reception timing in the serial interface Select the timer to be used as a baud rate timer by the SC4MD3 register Receive Bit Count and First Transfer Bit In the case of reception when the transfer bit count is 7 bits the data stor
398. ed to the timer 7 compare register 1 7 1 the timer 7 binary counter TM7BC is initialized to 0x0000 7 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer TM7BC counts up from 0x0000 If any data is written to the port 7 output register TM7BC is set to the set value of TM7OCI register and the synchronous output pin outputs data of the port 7 in every time the interrupt request is generated 16 bit Timer Synchronous Output VI 37 6 16 bit Timer VI 38 6 9 16 bit Timer Capture 6 9 1 Operation The value of the binary counter is read out at the timing of the external interrupt input signal which is synchro nized to fosc fs or the external event signal or at the timing of the writing operation with any value to the capture register Capture Operation with External Interrupt Signal as the Trigger Timer 7 Input capture trigger is generated at the external interrupt signal The capture trigger is selected by the Timer 7 mode register 1 TM7MD1 and the timer mode register 2 TM7MD2 Selectable capture triggers and the inter rupt flag setup are shown below Table 6 9 1 Capture Trigger Capture trigger source Timer 7 mode register 2 Timer 7 mode External interrupt pin register 1 switching control register T7ICT1 0 T7ICEDGO T7ICEDG1 IRQ2SEL IRQ3SEL P20 IRQO falling edge 00 1 0 x x P20 IRQO risin
399. egister PAIMD is set to 1 to input the special function data and 1 is read out from the portA input regis ter PAIN and 0 to use as the general port Special Function Pin Setup is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as the analog input pin set the port input mode register to 1 Then the value of the port A is read to be 1 1 is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as the analog input pin set the port input mode register to 1 Then the value of the port A is read to be 1 PA2 is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as the analog input pin set the port A input mode register to 1 Then the value of the port A is read to be 1 is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as the analog input pin set the port input mode register to 1 Then the value of the port A is read to be 1 PA4 is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as the analog input pin set the port input mode
400. egister PIDIR The pin output that is switched at the falling edge event of the external interrupt 0 pin P20 IRQO is 0 1 Hi impedance Port is input mode at the hi impedance The real time control is the function that changes the timer output signal PWM output timer pulse output remote control career output synchronized with the external event It is also available to normal port output When port real time control disabled is selected at the port 1 output control register PICNTO if switching event is generated the value is not be changed Set this mode when it is used as the general port Real Time Output Control Operation After the setup of the port 1 output control register PICNTO selected function at the port 1 output mode register is output to the pin until the falling edge is generated at the external interrupt 0 pin P20 IRQO When the falling edge is generated pin output is switched to the set value The falling edge event is taken in the edge event hold function that is shown below and the setup value of the port 1 output control register PICNTO is held until that information is cleared Real Time Output Release Clearance of edge event hold function After the event generation when the write operation is done to the port 1 output register PIOUT the informa tion of the edge event hold function is cleared and all output pins are reset to the output data before the event gen
401. ems SP 2 bp3 0 PC 6 d16 label H gt PC JSR label SP 3 9SP PC 7 bp7 0 smem8 SP PC 7 bp15 8 gt mem8 SP 1 7 5 2 7 0 8 2 6 4 PC 7 bp19 16 smems8 SP 2 bp3 0 abs18 label H PC JSR label SP 3 9SP PC 7 bp7 0 smem8 SP 0011 1101 1011 0008 bbbH abs 20b 15 0 6 PC 7 bp15 8 gt mem8 SP 1 PC 7 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 7 bp19 16 smem8 SP 2 bp3 0 abs20 label H PC JSRV tbl4 SP 3 9SP PC 3 bp7 0 mem8 SP PC 3 bp15 8 mem8 SP 1 PC 3 H gt mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 3 bp19 16 mem8 SP 2 bp3 0 mem8 x 004080 tbl4 lt lt 2 PC bp7 0 mem8 x 004080 tbl4 lt lt 2 1 PC bp15 8 mem8 x 004080 tbl4 lt lt 2 2 bp7 PC H mem8 x 004080 tbl4 lt lt 2 2 bp3 0 gt PC bp19 16 NOP NOP 2 2 11 0000 0000 0011 1001 1aaH abs 18b 15 0 gt bd 1111 1110 t4 1 d7 sign extension 2 4211 sign extension 3 412 sign extension 4 916 sign extension 5 aa abs18 17 16 6 B abs20 19 7 bbb abs20 18 16 XIX 6 Instruction Set MN101E SERIES INSTRUCTION SET RTS Mnemonic RTS Operation mem8 SP PC bp7 0 mem8 SP 1 PC bp15 8 mem8 SP 2 bp7 PC H mem8 SP 2 bp3 0 PC bp19 16 SP 3 SP 2 7 0000 0001 Machine Code 6 7 RTI 8 5 gt 5 mem8 SP 1 PC bp7
402. eption Data Buffer Refer to XIV 15 B Transfer Bit Count and First Transfer Bit Refer to XIV 16 Continuous Communication Refer to XIV 17 Auto Continuous Transfer By Refer to XIV 17 In communication set Nch open drain for pin type as the hardware switches if bus is used Y released In reception set the SDA3 pin SBOS3 pin direction to output Operation XIV 43 14 Serial Interface 3 Master Transmission Timing 1 0 8 lt 4 4 gt B bits transmission gt lt 4 gt 4 x transmission SDA SCL Interrupt IICBSY j U i Write data to TXBUF3 Write data to TXBUF3 IICSTPC flag set Figure 14 3 21 Master Transmission Timing 1 Output start condition 2 Bus released period ACK bit is received 3 Interrupt Set data to TXBUF3 4 Receive ACK bit 5 Interrupt Communication ends clear the IICBSY flag 6 Generates stop condition XIV 44 Operation 14 Serial Interface 3 Master Reception Timing 2 x G0 0 806 gt lt gt 8 bits transmission lt transmission i SDA 2 SCL Interrupt IICBSY Write data to TXBUF3 Write data to flag set Set dummy data Figure 14 3 22 Master Reception Timing 1 Output start condition 2 Bus released period ACK bit is received 3 Interrupt Set to reception
403. equest Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 17 Timer 7 Interrupt Control Register TM7ICR 0x03FFO bp 7 6 5 4 3 2 1 0 Flag TM7LV1 TM7LVO TM7IE TM7IR At reset 0 0 0 0 Access R W Description TM7LV1 Interrupt level flag TM7LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 34 Control Registers 3 Interrupts Timer 7 Compare Register 2 match Interrupt Control Register T7OC21CR The timer 7 compare register 2 match interrupt control register T7OC2ICR controls interrupt level of timer 7 compare register 2 match interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 18 Timer 7 Compare Register 2 match Interrupt Control Register T7OC2ICR 0x03FF1 bp 7 6 5 4 3 2 1 0 Flag T7OC2LV1 T7OC2LVO T7OC2IE T7OC2IR Atreset 0 0 0 0 Access R W T7OC2LV1 T7OC2LVO Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level
404. equest flag 0 No interrupt request 1 Interrupt request generated III 30 Control Registers 3 Interrupts Timer 5 Interrupt Control Register TM5ICR The timer 5 interrupt control register TM5ICR controls interrupt level of timer 5 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 14 Timer 5 Interrupt Control Register TM5ICR 0x03FED bp 7 6 1 0 Flag TM5LV1 TM5LVO TM5IE TM5IR At reset 0 0 0 0 Access R W Description TM5LV1 Interrupt level flag TM5LV0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Ill 31 Chapter 3 Interrupts Timer 6 Interrupt Control Register TM6ICR The timer 6 interrupt control register TM6ICR controls interrupt level of timer 6 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 15 Timer 6 Interrupt Control Register TM6ICR 0x03FEE bp 7 6 5 4 3 2 1 0 Flag TM6LV1 TM6LVO TM6IE TM6IR At reset 0 0 0 0
405. er TXBUF0 TXBUF1 second data byte transfer up to 255 times entirely through the hardware Before execute a continuous serial transaction store the serial transmission data in the memory space that memory pointer 0 points once the serial communication ends the MCU has written to the reception data over the transmission data so that only reception data remains in the memory In transfer mode 9 ATC1 executes a data byte transfer twice everytime when activated However the value in memory pointer 0 increments by one only after the first transfer ends As a result the source address for the next 1 operation is one address higher than that for the previous operation Set the data transfer count for ATC1 in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated after one byte of data is transferred twice When it reaches 0x00 an interrupt ATC1IRQ occurs and the automatic transfer ends XVIII 28 Operation 18 Automatic Transfer Controller 18 3 15 Transfer mode A Ep ssrr In transfer mode A ATC1 automatically transfers one byte of data from any memory space to any other memory space everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 00000 to FFFFF AT1MAPO ATIMAP 1 1 1 1 1 2 AT1MAP1 2
406. er Pulse Output 5 8 bit Timers At TMnOC 0x00 timer pulse output has the same waveform to at 0x01 If any data is written to compare register when the binary counter is stopped timer output is reset to L Compare register Compare register Timer pulse output Selection clock cycle x 2 1 8 bit Timer Pulse Output V 39 5 8 bit Timers 40 5 7 8 bit PWM Output The TMnIO pin outputs the PWM waveform which is determined by the match timing for the compare register and the overflow timing of the binary counter 5 7 1 Operation Operation of 8 bit PWM Output Timers 0 2 and 4 The PWM waveform with an arbitrary duty cycle is generated by setting the duty cycle of period to the compare register The cycle is the period from the full count to the overflow of the 8 bit timer Table 5 7 1 shows PWM output pins Table 5 7 1 Output Pins of PWM Output Timer 0 Timer 2 Timer 4 PWM output pin TMOIO output pin P10 TM2IO output pin P12 TM4IO output 14 PD2 8 bit PWM Output 5 8 bit Timers Count Timing of PWM Output at Normal Timers 0 2 and 4 Count clock TMnEN TE ARE ab ae EO NT E flag EE m die d D d ME Compare TE E a a register EN DNE n e I cec eee counter PWM source wave form A B C TMnIO
407. er input Timer 1 input 2 27 1 output Figure 4 3 2 11 Diagram gt gt Ad Te 11 1 Chapter 4 I O Ports IV 21 4 I O Ports External interrupt 0 IRQ0 Pull up resistor control DQ WEK VR direction control PpRdPIDIR2 00 01 10 WEK VR x 9 i Port output data 5 qhiout2 o Port output control Q WEK VR P1IN2 gt lt Schmitt trigger input lt Port input data Timer 2 input Timer 2 output 2 Reset P1CNT03 2 Output control R snq ea 2 Figure 4 3 3 P12 Block Diagram IV 22 Port 1 Pull up resistor control pRq Wek ZR direction control WEK Port output data snq eq a c wo Port output control Q Wek R Schmitt trigger input Port input data lt PAINS J R Timer 3 input Timer 3 output Figure 4 3 4 P13 Block Diagram Port 1 Chapter 4 I O Ports IV 23 4 I O Ports i Ed t External interrupt 0 IRQ0
408. er selects either serial data is input from the SBI3 pin or SBO3 pin When data input from the SBO3 pin is selected for communication with 2 channels the P3DIR3 flag of the P3DIR register is used to switch the transmission reception of the SBO3 pin The SBI3 pin not used at that time can be used as a general port XIV 18 Operation 14 Serial Interface 3 Maximum transfer speed should be under 5 0 MHz If transfer clock exceeds 5 0 MHz data Y may not be transferred properly In reception you can use 5813 pin as general port by setting SC3IOM of the SC3MD1 regis ter to 1 to select serial data input from SBOS B Transmission Buffer Empty Flag If any data is set to TXBUF3 during communication after setting data to TXBUF3 before generating the commu nication complete interrupt SC3IRQ the transmission buffer empty flag SC3TEMP of the SC3STR register is set to 1 That indicates that the next transmission data is going to be loaded Data is loaded to inside shift register from TXBUF3 by generation of SC3TIRQ and the next transfer is started as SC3TEMP is cleared to 0 B BUSY flag If data is set to the transmission reception shift register TXBUF3 or start condition is enabled the busy flag SC3BSY is set That is cleared to 0 by the generation of the communication end interrupt SC3IRQ The SC3BSY flag setup is maintained during continuous communication If transmission buffer empty flag
409. eration XIII 41 Chapter Serial In 13 terface 2 Master Transmission Timing XIII 42 Um 0 8 0 65 0 lt 805 j transmission gt 4 gt lt gt lt 6bitstransmissin lt SDA SCL Interrupt IICBSY E i Write data to TXBUF2 Write data to TXBUF2 IICSTPC flag set Figure 13 3 21 Master Transmission Timing 1 Output start condition 2 Bus released period ACK bit is received 3 Interrupt Set data to TXBUF2 4 Receive ACK bit 5 Interrupt Communication ends clear the IICBSY flag 6 Generates stop condition Operation 13 Serial Interface 2 Master Reception Timing 2 x 0 89 DD M 806 gt lt gt 8 bits transmission lt lt gt transmission i SDA 2 SCL Interrupt IICBSY Write data to TXBUF2 Write data to TXBUF2 flag set Set dummy data Figure 13 3 22 Master Reception Timing 1 Output start condition 2 Bus released period ACK bit is received 3 Interrupt Set to reception mode SC2REX 0 gt 1 Set data to TXBUF2 4 Receive ACK bit 5 Interrupt Communication ends clear the IICBSY flag 6 Generates stop condition Operation 43 13 Serial Interface 2 Pin Setup 2 channels at transmission Table 13 3 15 shows the pins setup in serial interface transmission with 2 channels SDA2 SCL2
410. erial Interface 3 source should be set in such a way that the transfer rate is under 100 kHz in NORMAL mode a The transfer rate in communication is obtained by dividing clock source by 8 The clock 400 kHz in high speed mode with the SC3MD3 register a Set the SC3MST flag of the SC3MD1 register to 1 to select internal clock clock master Set the SC3SBIS and SC3SBOS flags of the SC3MD1 register to 0 before change the Y clock setup B Transmission Reception Mode Setup and Operation The SC3REX flag of the SC3CTR register selects the status of the transmission or the reception The first data is always added start condition for communication regardless of the value of the SC2STE flag The start condition is output from this serial master The start condition is not added over the second communication select the start condition none at the first set ting And the start condition is added over the second communication select the start condition enable at the first setting At addressing format slave address and R W bit are set to the first data after start condition for transmission At master reception switch to the reception mode at the interrupt transaction after the transmission of the first 1 byte data is finished after the ACK signal from slave is confirmed If the communication should be continued to other device without stop transmit slave address and R W bit again after start condition is generat
411. erial data input from the SBIO pin 13 Set the interrupt level by the SCOLV1 to 0 flag of the serial 0 UART transmission interrupt control register SCOTICR Set level 2 14 Set the SCOTIE flag of the SCOTICR register to 1 to enable the interrupt If any interrupt request flag SCOTIR of the SCOTICR register is already set clear SCOTIR before the interrupt is enabled Chapter 3 3 1 4 Setup Operation XI 37 11 Serial interface 0 XI 38 Dummy data y 0 03 95 Received data y input SBIO pin Setup Procedure Description 15 Set the startup factor of the serial 15 Set the dummy data to the serial transmission data communication buffer TXBUFO 16 Transfer to STOP mode 16 Set the STOP flag of the CPUM register to 1 to CPUM 0x03F00 transfer to the stop mode bp3 STOP 1 17 Start the serial communication 17 Input the transfer clock to the SBTO pin and transfer Transmission clock y input SBTO pin data to the SBIO pin 18 Recover from the standby mode 18 The serial 0 UART transmission interrupt SCOTIRQ is generated at the same time of the 8 bits data reception then CPU is recovered from the stop mode to the normal mode after the oscillation stabilization wait Note Each procedure 1 to 2 6 to 9 and 10 to 12 can be set at the same time 1 The slave reception at the standby mode should be used without the start condition to
412. erial data input selection 0 Data input from SBI3 1 Data input from SBO3 SDA3 SC3SBTS SBT3 pin function 0 Port 1 Transfer clock input output SC3SBIS Serial input control 0 1 input 1 Serial data input SC3SBOS SBOS SDA3 pin function 0 Port 1 Serial data output SC3MST Clock master slave selection 0 Slave 1 Master XIV 8 Control Registers 14 Serial Interface 3 Serial interface 3 Mode Register 3 SC3MD03 0x03FA6 7 6 3 2 1 0 SCSFDC1 SC3FDCO SC3PSCE SC3PSC3 SC3PSC1 SC3PSCO 0 0 0 0 0 0 Description SBO3 output selection after transfer of last data 00 Fixed to 1 High output 01 Hold last data 10 Fixed to O Low output 11 Reserved SC3FDC1 SCSFDCO Prescaler count control SC3PSCE 0 Disable the count 1 Enable the count Clock selection 000 fosc 2 001 fosc 4 SC3PSC3 010 fosc 16 SC3PSC1 011 fosc 32 SC3PSCO 100 fs 2 101 fs 4 110 timer 3 output 111 timer 5 output This depends on SCCKSEL5 flag and SCCKSEL4 flag of SCCKSEL register Y refer to table 13 2 9 serial clock cycle switching control register Control Registers XIV 9 14 Serial Interface 3 Serial interface 3 Status Register SC3STR 0x03FA7 bp 5 Flag SC3TEMP At reset 0 Access R Description SC3TEMP Transfer
413. et by using timer 0 that generates the constant interrupt Interrupt is generated every 250 cycles 100 us by selecting fs 2 at fs 2 5 MHz operation as a clock source A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 Disable the interrupt TMOICR 0x03FE8 bp1 TMOIE 0 3 Select the normal timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 001 5 Select and enable the prescaler output CK0MD 0x03F56 bp2 1 TMOPSC1 0 X0 bp0 TMOBAS 1 6 Set the cycle of the interrupt generation 0x03F52 0xF9 7 Set the interrupt level TMOICR 0x03FE8 bp7 6 TMOLV1 0 10 8 Enable the interrupt TMOICR 0x03FE8 bp1 TMOIE 1 9 Start the timer operation TMOMD 0x03F54 bp3 TMOEN 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the counting of the timer 0 2 Set the TMOIE flag of the TMOICR register to 0 to disable the interrupt 3 Set the TMOPWM flag and the TMOMOD flag of the TMOMD register to 0 to select the normal timer operation 4 Select the prescaler output to the clock source by the TM0CK2 to 0 flag of the TMOMD register 5 Select fs 2 to the prescaler output by the TMOPSC 1 to 0 flag and TMOBAS flag of the timer 0 prescaler selection register CKOMD
414. et the data transfer data count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime is activated after each word transfer When it reaches x 00 an inter rupt occurs and the automatic transfer ends Operation XVIII 21 18 Automatic Transfer Controller 18 3 10 Transfer Mode 5 EV WOIIrmp Es In transfer mode 5 ATC1 automatically transfers two bytes one word of data from the 1 space special regis ters 0x03F00 0x03FFF to any memory space everytime ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF_ 03F00 to 1 ATMAP even ATMAPO 20 f 9 odd 4 1 Only 1 EH 2 Only lower 8 bits are valid 3 Figure 18 3 7 Transfer Mode 5 Set the source I O address in lower 8 bits of memory pointer 1 ATIMAPIL and set the destination address in 20 bit memory pointer 0 ATIMAPOH M L You do not have to set the upper 12 bits of the I O space address Ox3F in ATIMAPIH and ATIMAPIM Always set an even address as the source I O address in memory pointer 1 When ATC1 transfers one word from the I O space ATC1 can transfer the even address set in memory pointer 1 and the consecutive odd address In transfer mode 5 1 executes a data byte transfer twice to send one data wor
415. et the interrupt generation cycle TMOOC 0x03F52 20x04 7 Select the normal timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 8 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 110 9 Set the interrupt level TMOICR 0x03FE8 bp7 6 TMOLV1 0 10 1 Set the TMOEN flag of the timer 0 mode register to 0 to stop timer 0 counting 2 Set the TMOIE flag of the TMOICR register to 0 to disable the interrupt 3 Set the P1DIRO flag of the port 1 direction control register P1DIR to 0 to set P10 pin to input mode Chapter 4 Port Function 4 Select the prescaler output to the clock source by the 2 to 0 flag of the TMOMD register b Select the fs 2 to the prescaler output by the TMOPSC1 to 0 flag and the TMOBAS flag of the timer 0 prescaler selection register CKOMD 6 Set the interrupt generation cycle to the timer 0 compare register TMOOC Counting is 5 so the setting value should be 4 At the time the timer 0 binary counter TMOBO is initializes to 0 00 7 Set the TMOPWM flag and the TMOMOD flag of the TMOMD register to 0 to select the normal timer operation 8 Select the TMOIO input to the clock source by the TMOCK to 0 flag of the TMOMD register 9 Set the interrupt level by the TMOLV1 to 0 flag of the timer 0 interrupt control register TMOICR If the interrupt request flag may be already set clear the request flag Chapter 3 3 1 4
416. ets ce ed RR Hp E eint ee nte sisaqa sa XVIII 6 18 3 ease b ede 12 18 3 1 Basic Operations and Timing sees 12 18 3 2 Memory Address XVIII 14 18 3 3 Data Transfer Count u RI XVIII 15 18 3 4 Data Transfer Modes 0 XVIII 16 16 3 5 lt Transter Mode ode RUSSE OS EIER XVIII 17 18 3 6 Transfer etka a Ae ni ete XVIII 18 18 3 7 Transfer Mode2 dui fetten tes XVIII 19 18 3 8 Transfer Mode nece c ecce es hed ee t Yin XVIII 20 18 3 9 Transfer Mode 4 sese e nee eire vedere XVIII 21 1673 10 Transfer Mode S ho eec ui Rd XVIII 22 18 3 TT Transter iced het AAG heist act teet 23 16 312 Transfer Mode 5 5 HEIDI i oes XVIII 24 18 3 13 Transter Ae ui t ERE XVIII 25 18 3 14 Transfer Mode 9 esse cedere der XVIII 27 16 32 15 Transfer mode eee hg tere XVIII 29 18 3 16 Transfer Mode B eee ee eee Ree XVIII 30 15 3 17 Transfer Mode i eR eth ade tecto deo ied XVIII 31 18 3 I8 Transter cientos eee A HER se XVIII 32 18 3 19 Transter Mode E uie XVIII 33 18 320 Transfer sa e e e te RR EEG Ae ed XVIII 34 18 4
417. etup 1 7 1 General Usage Connection of Vpp pin and Vss pin of the VDD and VSS pins should be connected directly to the power source and ground in the external Put them on printed circuit board after the location of LSI package pin is confirmed Connection error may lead a fusion and breakdown of a micro controller Cautions for Operation 1 If you install the product close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 Operation temperature should be well considered Each product has different condition For example if the operation temperature is over the condition improper operation could be occurred 3 Operation voltage should be also well considered Each product has different operating range If the operation voltage is over the operating range duration of the product could be shortened If the operation voltage is below the operating range improper operation could be occurred Cautions for Circuit Setup 1 31 1 Overview 1 7 2 Unused pins C lt g r ses Unused Pins only for input Insert some 10 resistor to unused pins only for input for pull up or pull down If the input is unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and causes power supply noise Input Pin some 10
418. f PWM operation by the TMnPWM flag of the TMnMD register 8 bit PWM Output 5 8 bit Timers 5 8 Synchronous Output 5 8 1 Operation When the binary counter of the timer reaches the set value of the compare register the latch data is output from port 7 at the next count clock Synchronous Output Operation by 8 bit Timer Timers 1 and 2 The port 7 latched data is output from the output pin in synchronization with the interrupt request generation by the match of the binary counter and the compare register Only port 7 can perform synchronous output operation and individual bits can be set 8 bit timers that have syn chronous output operation are the Timers 1 and 2 Table 5 8 1 Synchronous Output Port iTimers 1 and 2 j Timer 1 Timer 2 Synchronous Port 7 Port 7 output port Timing of Synchronous Output Timers 1 and 2 TMnEN flag Compare register 1 Port 7 output n 2 2 latch dafa 2 CERE Pu uS EC EE UE euni net ner 7 counter Interrupt request flag synchronous output data Figure 5 8 1 Timing of Synchronous Output Timers 1 and 2 The port 7 output latched data is output from the output pin in synchronization with the interrupt request gen eration by the match of binary counter and compare register Synchronous Output V 45 5 8 bit Timers 5 8 2 Setup Example S
419. fer mode with the AT1MD flag in the AT1CNTO register No matter which mode you select setting the FMODE flag disables the increment function in memory pointer 0 Normally set this flag to 0 Note that you must set the ATC1 enable flag ATTEN to 0 at this step Only enable ATC1 after setting all the other registers 2 Set the source or destination address in the registers depending on the transfer mode you select 3 Set the source or destination address in the AT1MAP1 registers depending on the transfer mode you select 4 Set the ATC1 data transfer count in the ATTTRC register b Select the ATC1 activation factor with the AT1IR flag in the register If you select a burst type transfer mode then you must also enable or disable ATC1 shutdown at this step by setting the BTSTP 6 Enable ATC1 data transfers with the AT1EN flag in the AT1CNTO register To activate ATC1 in the software first complete steps 1 to 6 then set the AT1ACT flag in the AT1CNTO register After the AT1ACT flag is set ATC1 is started and data transfer is started The hardware automatically clears AT1ACT flag when 1 is activated In standard transfer mode set a program that sets flags as many as necessary for the the data transfer Setup Example XVIII 35 18 Automatic Transfer Controller XVIII 36 Setup Example Chapter 19 Appendix 19 Appendix 19 1 Instruction
420. fer modes 0 to D In standard transfers the transfer counter decrements everytime when 1 is activated When the counter reaches 0x00 after data transfer ATC1 generates an interrupt ATCIIRQ This means that for standard trans fers the program must set the counter to the number of times needs to be activated 2 Burst transfers transfer modes E to F In burst transfers one activation of ATC1 continuously transfers multiple bytes of data In this case the program must set the counter to the number of data bytes contained in the burst transfer When the burst transfer starts the transfer counter decrements everytime when one byte of data is transferred When the counter reaches 0x00 generates an interrupt It is also possible to force to shut down during a burst transfer using external interrupt 0 See section 18 3 4 Data Transfer Modes Setting B The transfer data counter AT1TRC The transfer data counter can be set to maximum 255 transfers for standard transfers or 255 bytes for burst transfers Note that setting the counter to 0x00 disables transfers Operation XVIII 15 18 Automatic Transfer Controller 18 8 4 Data Transfer Modes Setting B Data transfer modes There are two types of 1 transfers standard and burst and sixteen transfer modes Set the transfer mode in control register 0 ATI CNTO Table 18 1 2 Transfer Modes Standa
421. ffer TXBUF4 is a buffer of reserve that stores data to load the internal shift register Data to be transferred should be set to the transmission data buffer TXBUF4 to be loaded to the internal shift reg ister automatically The data load time of 3 5 transfer clock is needed to load the data On loading setting the data to TXBUFA again may cause error On loading or not is determined by monitoring the transmission buffer empty flag of the SCASTR When the data is set to TXBUF4 SCATEMP flag is set to 1 and when loading is finished it is cleared 0 automatically Clock prescaler output SCOTEMP Data set to TXBUF4 Clock SBTO pin Data road period Figure 15 3 1 Received Date Buffer The received data buffer RXBUF4 is a buffer of reserve that pushed the received data in the internal shift register After the communication complete interrupt SCATIRQ is generated all data stored in the internal shift register are stored to the received data buffer RXBUF4 automatically RXBUF4 can store data up to 1 byte RXBUF4 is rewritten in every time when communication is completed so read out data of RXBUF4 till the next receive is completed The received data buffer empty flag SCAREMP is set to 1 at the same time SCATIRQ is generated SCAREMP is cleared to 0 after RXBUF4 is read out Operation XV 13 15 Serial interface 4 If a start condition is input to restart during communication the t
422. flag of the port 1 direction P1DIR 0x03F31 control register P1DIR to 1 to set the output mode bp6 P1DIR6 1 Chapter 4 Ports 4 Set the PWM output 4 Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 0x3F79 TM7MD2 to 1 to select the PWM output bp4 TM7PWM 1 5 Set the standard PWM output b Set the TM7BCR flag of the TM7MD2 register to 0 to 7 2 0x3F79 select the full count overflow as the binary counter bp5 TM7BCR 0 clear source 6 Select the count clock source 6 Select fosc as the clock source by the TM7CK1 to 0 flag TM7MD 1 0 3 78 of the TM7MD 1 register Also select 1 1 dividing as the bp1 0 TM7CK1 0 200 count clock source by the TM7PS1 to 0 flag bp3 2 TM7PS1 0 200 16 bit Standard PWM Output Only duty can be changed consecutively VI 29 6 16 bit Timer VI 30 Setup Procedure Description 7 Set H period of the PWM output TM7PR1 0x3F75 0x3F74 20x4000 8 Start the timer operation TM7MD 1 0x3F78 bp4 TM7EN 1 7 Set H period of the PWM output to the timer 7 preset register 1 TM7PR1 To set 1 4 duty of the full count 65536 set as 65536 4 1 16383 0x03FFF At the same time the same value is loaded to the timer 7 compare register 1 7 1 and the timer 7 binary counter TM7BC is initialized to 0x0000 8 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 TM7BC counts up from 0x
423. fs is as clock source After oscillation stabilization wait time it continues counting as a watchdog timer Block Diagram of Oscillation Stabilization Wait Time watchdog timer STOP 9 writeWDCTR HALT R R R fs 1 2 1 214 1 215 1 222 internal reset release 14 internal reset P e es WDEN 15 28 MUX DLYCTR fs 2 YYYY fs 222 15 220 16 fs 2 gt lt 7 Figure 2 7 3 Block Diagram of Osillation Stabilization Wait Time watchdog timer Reset 55 2 CPU Basics Oscillation Stabilization Wait Time Control Register Table 2 7 1 Oscillation Stabilization Wait Time Control Register DLYCTR 0x03F03 bp 7 6 5 4 3 2 1 0 Flag BUZOE BUZS2 BUZS1 BUZSO DLYS1 DLYSO At reset 0 0 0 0 0 0 Access R W Output selection 0 Port data output 1 Buzzer output Buzzer output frequency selection 000 fosc 214 001 fosc 213 010 fosc 21 011 fosc 2 100 fosc 20 101 fosc 29 110 fx 24 111 fx 23 Oscillation stabilization wait period selection 00 fs 214 01 15 210 10 15 28 1 11 6 2 1 Do not use in high speed operation NORMAL mode Use in low speed operation SLOW mode Il 56 Reset Control the Oscillation Stabilization
424. g Description gt O Q O P7PLU7 P7PLU6 P7PLU5 P7PLU4 P7PLU3 P7PLU2 P7PLU1 P7PLU0 Pull up pull down resistor selection 0 Not added 1 Added Port 7 Synchronous Output Control Register P7SYO 0x03F 1F Flag P7SYO7 P7SYO6 P7SYO5 P7SYO4 75 75 2 75 1 P7SYOO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O gt O Q O P7SYO7 P7SYO6 P7SYO5 P7SYO4 P7SYO3 P7SYO2 P7SYO1 P7SYOO Synchronous output selection 0 l O port 1 Synchronous output Port 7 IV 69 4 I O Ports IV 70 Port 7 Synchronous Output Event Selection Register P7SEV 0x03F2F P7SEV1 P7SEVO 0 0 Synchronous output event selection 00 IRQ2 P22 IRQ2A input 01 TM7IRQ 10 TM2IRQ 11 TM1IRQ P7SEV1 P7SEVO Pull up Pull down Resistor Selection Register SELUD 0x03F4B bp Port A pull up pull down selection 0 Pull up 1 Pull down Port 7 pull up pull down selection 0 Pull up 1 Pull down Port 4 pull up pull down selection 0 Pull up 1 Pull down Port 7 Chapter 4 I O Ports Address Output Control Register EXADV 0x03F0E EXADV3 0 EXADV3 Description P70 P71 P72 P73 Address output control 0 port 1 address output EXADV2
425. g circuit output signal is changed at the falling edge of the system clock after the TM7IO input signal is changed The binary counter counts up at the falling edge of the synchronizing circuit output signal or the synchronizing circuit output signal that passed through the division circuit TM7IO input System clock fs Synchronous circuit output count clock TM7EN flag Compare register 1 counter Interrupt request flag Figure 6 4 2 Count Timing of Synchronous Input Timer 7 16 bit Event Count 6 16 bit Timer The timer 7 binary counter counts up the binary counter at the signal in synchronization with the system clock so that correct value is read out from the timer 7 binary counter then select the TM7IO input And the value is not writable at the preset register during the 1 When input is used select fs as a count clock set the value to the TM7PR1 register operation At 16 bit timer only TM7IO input can be returned from STOP mode 16 bit Event Count VI 19 6 16 bit Timer 6 4 2 Setup Example Event Count Setup Example When the falling edge of the TM7IO input pin signal is detected 5 times using Timer 7 an interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD 1 0 03 78 bp4 TM7EN 0 2 Disable the interrupt
426. g edge 00 1 1 x x P20 IRQO both edges 00 0 x x x P21 IRQ1 falling edge 01 1 0 x x P21 IRQ1 rising edge 01 1 1 x x P21 IRQ1 both edges 01 0 x x x P22 IRQ2A falling edge 10 1 0 0 x P22 IRQ2A rising edge 10 1 1 0 x P22 IRQ2A both edges 10 0 x 0 x P23 IRQ3A falling edge 11 1 0 x 0 P23 IRQ3A rising edge 11 1 1 x 0 P23IRQ3A both edges 11 0 x x 0 PDO IRQ2B falling edge 10 1 0 1 x PDO IRQ2B rising edge 10 1 1 1 x PDO IRQ2B both edge 10 0 x 1 x PD1 IRQ3B falling edge 11 1 0 x 1 PD1 IRQ3B rising edge 11 1 1 x 1 PD1 IRQ3B both edge 11 0 x x 1 16 bit Timer Capture 6 16 bit Timer can not used at the same time as there is no both edge interrupt in external interrupt IRQO a In the external interrupt input pin P20 P21 both edge input capture and both edge interrupt IRQ1 When the capture trigger is started at both edges of the external interrupt input signal if it is engaged with data automatic transfer ATC1 it is possible to measure the precision width which can measure the input signal between H and L continuously Set the address of the input capture register TM7ICL to the memory pointer 1 Transferring the value of the input capture register TM7ICL TM7ICH to the memory sequentially with every generation of the capture trigger make it possible to Measure the input signal between H and L continuously Capture Count Timing as Both Edges of External Interrupt Signal is selected as Trigger
427. gisters XVI 5 16 A D Converter A D Converter Control Register ANCTR1 0x03FB3 Flag Reset Access bp Flag Description 7 8 000 001 AN1 5 52 010 AN2 2 5 51 011 AN3 ANSHSO 100 4 PA4 101 AN5 PA5 110 AN6 PA6 111 AN7 PA7 B A D Converter Control Register2 ANCTR2 0x03FB4 Flag Reserved Reset 0 Access A D conversion status ANST 0 Finish Hold 1 Start Converting A D conversion starting factor select 0 Set ANST flag to 1 1 Set external factor P23 PD1 falling edge ANST flag to 1 ANSTSEL 1 Reserved Set always to 0 XVI 6 Control Registers 16 A D Converter 16 2 3 Data Buffers A D Conversion Data Storage ANBUFO 0xO3FB5 The lower 2 bits results from A D conversion are stored to this register ANBUF07 ANBUFO6 Reset X Nee CC A D Conversion Data Storage Buffer1 ANBUF1 0x03FB6 The upper 8 bits results from A D conversion are stored to this register Flag ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 X X Reset X X X X X X R R R Access R R R R R Control Registers XVI 7 16 A D Converter 16 3 Operation He
428. h 2 channels RXD 1 Table 12 3 21 UART Serial Interface Pin Setup with 2 channels at reception Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port pin P30 P31 TXD1 RXD1 pins selection TXD1 RXD1 pins independent SC1MD1 SC1IOM Function Port Serial data input SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Input mode P3DIR P3DIR1 Pull up setup Operation B Pin Setup with 1 channel at reception Chapter 12 Serial interface 1 Table 12 3 22 shows the pin setup at UART serial interface reception with 1 channel TXD1 pin The RXDI pin in not used so can be used as a port Table 12 3 22 UART Serial Interface Pin Setup with 1 channel at reception Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port pin P30 P31 TXD1 RXD1 pins selection TXD1 RXD1 pins connect SC1MD1 SC1IOM Function Port Serial data input SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Input mode P3DIR P3DIR1 Pull up setup B Pin Setup with 2 channels at transmission reception Table 12 3 23 shows the pin setup at UART serial interface transmission reception with 2 channels TXD1 pin RXDI pin Table 12 3 23 UART Serial Interface Pin Setup with 2 channels at transmission reception Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port
429. hardware configuration It is a high speed CPU with a simple and efficient instruction set Specific features are as follows 1 Minimized code sizes with instruction lengths based on 4 bit increments The series keeps code sizes down by adopting a basic instruction length of one byte and variable instruction lengths based on 4 bit increments 2 Minimum execution instruction time is one system clock cycle 62 5 ns 3 Minimized register set that simplifies the architecture and supports C language The instruction set has been determined depending on the size and capacity of hardware after on analysis of embedded application programing code and creation code by C language compiler Therefore the set is simple instruction using the minimal register set required for C language compiler Table 2 1 1 Basic Specifications Structure Load store architecture Six registers Data 8 bit x 4 Address 16 bit x 2 Others PC 21 bit PSW 8 bit SP 16 bit Instructions Number of instructions 39 Addressing modes 9 Instruction length Basic portion 1 byte min Extended portion 0 5 byte x n 0 lt lt 9 Basic Internal operating frequency max 16 MHz performance Instruction execution Min 1 cycle Inter register operation Min 2 cycle Load store Min 2 cycle Conditional branch 2 to 3 cycles Pipeline 3 stage instruction fetch decode execution Address space 1MB m
430. he arbitrary value written to 6 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation fs System clock Chapter 2 2 5 Clock Switching 1 Can be used when a clock source of time base timer is selected to fosc 2 Can be used when a clock source of time base timer is selected to fx VII 2 Overview 7 Time Base Timer Free running Timer When fs is used as a clock source it counts at rising of the count clock and in other uses Y it counts falling of the count clock Count clock source should changed with the timer interrupt is prohibited Overview VII 3 Block Diagram Timer 6 Time Base Timer Block Diagram 7 1 2 Time Base Timer Free running Timer Chapter 7 194 Lek g Z L oL g k N x x peris 391 N389W1 DX Oula L snouoJuou AS L amp 154 O89WL SHTOONE 1 lunoo 16 8 o raon omon uonoeiep 194816 1 R t I 0 Buruuni 894J 6 8 9 Figure 7 1 1 Block Diagram 6 Time Base Overview VII 4 7 Time Base Timer Free running Timer 7 2 Control Registers Timer 6 consists of binary counter TM6BC compare register TM6OC and is controlled by mode register TM
431. he SC4MD1 register is set to 1 and serial data input from 5804 is selected SBI4 pin can be used as a general port Reception Buffer Empty Flag After reception is completed SCATIRQ is generated data is automatically stored to RXBUFA from the internal shift register If data is stored to the shift register RXBUF4 when the SC4SBIS of the SCAMDI register is set to serial input the reception buffer empty flag SCAREMP of the SCASTR register is set to 1 This indicates that the received data is going to read out SCAREMP is cleared to 0 by reading out the data of RXBUFA Transmission Buffer Empty Flag During the communication after setting data to TXBUF4 and before the communication complete interrupt 5 is generated if any data is set to TXBUF4 again the transmission buffer empty flag SCAREMP of the SCASTR register is set to 1 This indicates that the next transmission data is going to be loaded Data is loaded to the inside shift register from TXBUFA by generation of SC4TIRQ and the next transfer is started as SCATEMP is cleared to 0 Overrun Error and Error Monitor Flag After reception complete if the next data has been already received before reading out of the data of the received data buffer RXBUFA overrun error is generated and the SCAORE flag of the SCASTR register is set to 1 At the same time the error monitor flag SCAERE is set to indicate that error is occurred on reception The SCAERE flag i
432. he SCIMDI register selects enable count The SCIMST flag of the SCIMDI register can select the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock that has the same clock cycle or lower to the external clock by the SCIMD3 register Table 12 3 3 Synchronous Serial Interface Clock Source serial 1 Clock source fosc 2 internal clock fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 4 output Timer 5 output When the clock setup is switched the SC1SBIS flag and SC1SBOS flag of the SC1MD1 reg Y ister should be set to 0 When the slave reception is done with enabled start condition set the speed of the transfer Y clock slower than the system clock B Operation XII 17 12 Serial interface 1 XII 18 m Data Input Pin Setup 3 channels type clock pin SBT1 pin data output pin 5 pin data input pin SBII pin or 2 channels type clock pin SBT1 pin data I O pin SBOI pin can be selected as a communication mode SBII pin be used for only serial data input SBOI pin can select serial data input or output The flag of the SCIMDI reg ister can select if the serial data is input to pin SBOI pin When data input from 5 pin is selected to set the 2 lines type the P3DIRO flag of the P3DIR register controls direction of SBO1 pin to switch tran
433. he transfer speed should be up to 5 0MHz Y If the transfer clock is over 5 0 MHz the transmission data may not be sent correctly At reception if SCOIOM of the SCOMD1 register is set to 1 and serial data input from 5800 is selected SBIO pin can be used as a general port Reception Buffer Empty Flag After reception is completed communication complete interrupt SCOTIRQ is generated data is automatically stored to RXBUFO from the internal shift register If data is stored to the shift register RXBUFO when the SCOSBIS of the SCOMD1 register is set to serial input the reception buffer empty flag SCOREMP of the SCOSTR register is set to 1 This indicates that the received data is going to read out SCOREMP is cleared to 0 by reading out the data of RXBUFO B Transmission Buffer Empty Flag During the communication after setting data to TXBUFO and before the communication complete interrupt SCOTIRQ is generated if any data is set to TXBUFO again the transmission buffer empty flag SCOREMP of the SCOSTR register is set to 1 This indicates that the next transmission data is going to be loaded Data is loaded to the inside shift register from TXBUFO by generation of SCOTIRQ and the next transfer is started as SCOTEMP is cleared to 0 Overrun Error and Error Monitor Flag After reception complete if the next data has been already received before reading out of the data of the received data buffer RXBUFO overrun err
434. ic Transfer Controller ATC1 Transfer Counter AT1TRC1 0x03FD2 Flag 1 7 ATITRC6 AT1TRC5 ATITRC4 AT1TRC3 ATTTRC2 1 1 ATITRC0 0 0 0 0 0 At reset 0 0 0 Access e me p _ E ATC1 Transfer Data Count Setting 7 0 AT1TRC7 0 For transfer modes 0 to D set this register to the number of ATC activations For transfer modes E and F set this register to number of burst transfers Control Registers XVIII 9 18 Automatic Transfer Controller 1 Memory Pointer Lower 8 bits AT1MAPOL 0x03FD3 Flag bp15 bp14 bp13 bp12 bp11 bp10 bp9 bp8 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Flag bp19 bp18 bp17 bp16 At reset 0 0 0 0 Access R W R W R W R W R W R W R W R W XVIII 10 Control Registers 1 Memory Pointer 1 Lower 8 bits AT1MAP1L 0x03FD6 Chapter 18 Automatic Transfer Controller Flag bp15 bp14 bp13 bp12 bp11 bp10 bp9 At reset 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W Flag bp19 bp18 bp17 At reset 0 0 0 Access R W R W R W R W R W R W R W Control Registers XVIII 11 18 Automatic Transfer Controller 18 3 Operation 18 3 1 Basic Operations and Timing
435. ic transfer ATC1 On start up by ATC1 255 bytes data trans fer can be operated Refer to chapter 18 Automatic Transfer Controller overview transfer mode 8 to 9 about the generation of ATCI B Input Edge Output Edge Setup The 1 flag of the SCOMDO register set an output edge of the transmission data an input edge of the received data As the SCOCEI flag 0 the transmission data is output at the falling edge and as 1 output at the rising edge As SCOCEI O the received data is received at the inversion edge to the output edge of trans mission data and as 1 stored at the same edge Table 11 3 2 Transmission Data Output Edge and Received Data Input Edge SCOCE1 Transmission data output edge Received data input edge 0 Operation XI 17 11 Serial interface 0 XI 18 Clock Setup SCOPSC2 to 0 of the SCOMD3 register selects the clock source from the special prescaler and timer 2 timer 4 2 lines output The special prescaler starts its operation after the SCOPSCE flag of the register selects enable count The SCOMST flag of the SCOMDI register can select the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock that has the same clock cycle or lower to the external clock by the SCOMD3 register Here is the internal clock source that ca
436. ications equipment measuring instruments and household appliances Consult our sales staff in advance for information on the following applications Special applications such as for airplanes aerospace automobiles traffic control equipment combustion equipment life support systems and safety devices in which exceptional quality and reliability are required or if the failure or malfunction of the products may directly Jeopardize life or harm the human body Any applications other than the standard applications intended The products and product specifications described in this book are subject to change without notice for modification and or improvement At the final stage of your design purchasing or use of the products therefore ask for the most up to date Product Standards in advance to make sure that the latest specifications satisfy your requirements When designing your equipment comply with the guaranteed values in particular those of maximum rating the range of operating power supply voltage and heat radiation characteristics Otherwise we will not be liable for any defect which may arise later in your equipment Even when the products are used within the guaranteed values take into the consideration of incidence of break down and failure mode possible to occur to semiconductor products Measures on the systems such as redundant design arresting the spread of fire or preventing glitch are recommended in order to prevent
437. iew XVI 3 16 A D Converter 16 2 Control Registers A D converter consists of the register ANCTRn and the data storage buffer ANBUFn 16 2 1 Registers Table 16 2 1 shows the registers used to control A D converter Table 16 2 1 A D Converter Control Registers Register Address Function ANCTRO 0x03FB2 RAN A D converter control register 0 XVI 5 1 0x03FB3 RAN A D converter control register 1 XVI 6 ANCTR2 0x03FB4 RAN A D converter control register 2 XVI 6 ANBUFO OxOSFB5 R A D converter data storage buffer 0 XVI 7 ANBUF1 0x03FB6 R A D converter data storage buffer 1 XVI 7 ADICR 0x03FFA RAN A D converter interrupt control register III 44 PAIMD 0x03F3B R W Port A input mode register IV 99 PAPLU 0x03F4A R W Port A Pull up resistance control register IV 99 R W Readable Writable R Readable only XVI 4 Control Registers 16 A D Converter 16 2 2 Control Registers B A D Converter Control RegisterO ANCTRO 0x03FB2 m p p p F E E F p J 0 0 0 0 0 Reset Access R W R W R W R W R W bp Flag Description Sample and hold time 00 Tap x 2 01 Tap x6 10 Tap x 18 11 Tap x 18 A D conversion clock ftadz1 TAp 00 16 2 01 fs 4 10 fs 8 11 fx x2 as TAp gt 500 ns A D ladder resistance control ANLADE 0 ladder resistance OFF 1 A D ladder resistance ON Control Re
438. ify the interrupt valid edge to the rising edge Simple Pulse Width Measurement 5 8 bit Timers Setup Procedure Description 10 Enable the interrupt 10 Set the IRQ2IE flag of the IRQ2ICR register to 1 to IRQ2ICR 0x03FE4 enable the interrupt bp5 RED2IE 1 11 Enable the timer operation 11 Set the TMOEN flag of TMOMD register to enable the TM0MD 0x03F54 timer 0 operation bp3 1 TM0BC2 starts to count up from 0x00 with negative edge of the external interrupt 2 IRQ2A input as a trig ger Timer 0 continues to count up during L period of IRQ2A input then stop the counting with positive edge of IRQ2A input as a trigger At the same time reading the value of TM2BC by interrupt handling can detects L period of IRQ2 input Simple Pulse Width Measurement V 51 5 8 bit Timers V 52 5 11 Cascade Connection 5 11 1 Operation Cascading Timers 0 and 1 or Timers 2 and 3 or Timers 4 and 5 forms a 16 bit timer 8 bit Timer Cascade Connection Operation Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timers 0 and 1 or Timers 2 and 3 or Timers 4 and 5 are combined to be a 16 bit timer Cascading timer is oper ated at the clock source of Timers 0 2 or 4 which are lower 8 bits Table 5 11 1 Timer Functions at Cascade Connection Timer 0 Timer1 Timer 24 Timer 3 Timer 44 Timer 5 16 bit 16 bit 16 bit Inte
439. ime when communication is completed At continuous communi cation data of RXBUFO should be read out until the next reception is completed Operation XI 15 11 Serial interface 0 Transfer Bit Count and First Transfer Bit When the transfer bit is 1 bit to 7bit the data storing method to the transmission data buffer TXBUFO is different depending on the first transfer bit selection At MSB first use the upper bits of TXBUFO for storing When there are 6 bits to be transferred as shown on Figure 11 3 2 if data to F are stored to bp2 to bp7 of TXBUFO the transmission is operated from F to A AtLSB first use the lower bits of TXBUFO for storing When there are 6 bits to be transferred as shown on Figure 11 3 3 if data to are stored to to of TXBUFO the transmission is operated from A to F TXBUFO F E D TXBUF0 7272121 Figure 11 3 3 Transfer Bit Count First Transfer Bit starting with LSB Receive Bit Count and First Transfer Bit When the transfer bit count is 1 bit to 7 bits the data storing method to the received data buffer RXBUF0 is differ ent depending on the first transfer bit At MSB first data are stored to the lower bits of RXBUF0 When there are 6 bits to be transferred as shown on figure Figure 11 3 4 if data A to F are stored to bp0 to bp5 of RXBUFO the transmission is operated f
440. imer control register WDCTR The watchdog timer can be cleared regardless of the writing data to the register The bit set BSET that does not change the value is recommended Operation Chapter 9 Watchdog Watchdog Time out Period The watchdog time out period is decided by the bp2 1 WDTS1 0 of the watchdog timer control register WDCTR and the system clock fs If the watchdog timer is not cleared by this set value that is regarded as an error and the watchdog interrupt WDIRQ of the non maskable interrupt NMI is generated Table 9 3 1 Watchdog Time out Period WDTS1 WDTSO Watchdog Time out Period 0 0 216 x system clock 0 1 218 x system clock 1 0 220 x system clock 1 1 222 x system clock The system clock is decided by the CPU mode control register CPUM Chapter2 2 6 Clock Switching The watchdog time out period is generally decided from the execution time for main routine of program That should be set the longer cycle than the value of the execution time or main routine divided by natural number 1 2 And set the command of the watchdog timer clear to the main routine as that value makes the same cycle Watchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features are as follows 1 In NORMAL IDLE SLOW mode the system clock is counted 2 The counting is continued regardless of swithching at NORMAL IDLE SLOW mode 3 In HALT mode
441. iming parity bit is enabled TXDO pin Stop bit bit SCOTBSY Data to TXBUFO 7 Interrupt SCOTIRQ Figure 11 3 21 Transmission Timing parity bit is disabled Operation XI 45 11 Serial interface 0 B Reception Timing Tmin 0 5T T Stop RXDO pin bit SCORBSY o Input start condition Interrupt b X SCORIRQ Figure 11 3 22 Reception Timing parity bit is enabled Tmin 0 5T T gt Stop RXDO pin bit SCORBSY A Input start condition Interrupt SCORIRQ Figure 11 3 23 Reception Timing parity bit is disabled XI 46 Operation B Transfer Speed Setup Baud rate timer timer 2 timer 4 can set any transfer rate Table 11 3 19 shows the setup example of the transfer speed Table 11 3 19 UART Serial Interface Transfer Speed Chapter 11 Serial interface 0 Setup Register Page Serial 0 clock source timer 2 timer 4 SCOMD3 10 2 lt TM2MD V 19 Timer 2 compare register TM1OC V 14 Timer 4 clock source TM4MD V 21 Timer 4 compare register TM4OC V 15 Timer compare register is set as follows baud rate 1 overflow cycle 2 8 8 means that clock source is divided by 8 overflow cycle set value of compare register 1 xtimer clock cycle therefore set value of compare register timer clock frequency baud rate x 2 x 8 1
442. in Input pin SBO1 SBI1 pin Transfer bit count SC1RBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 11 Reception Timing at rising edge start condition is disabled Operation XII 23 12 Serial interface 1 Clock SBT1 pin Input pin SBO1 SBI1 pin Transfer bit counter SC1RBSY Interrupt SC1TIRQ Figure 12 3 12 Reception Timing at falling edge start condition is enabled At master 3 5 T Clock SBT1 pin Input pin SBO1 SBI1 pin Transfer bit counter 1 Data set to 1 1 Interrupt SC1TIRQ Figure 12 3 13 Reception Timing at falling edge start condition is disabled XII 24 Operation 12 Serial interface 1 B Transmission Reception Timing When transmission and reception are operated at the same time set the SCICEI flag of the SCIMDO register to 0 or 1 Data is received at the opposite output edge of the transmission data so that the input edge of the received data should be the opposite output edge of the transmission data from the other side Also in the case transmission reception is done with the start condition opposite of the communication should be done with the same condition to communicate properly The normal communication may not be operated SBT1pin Data is received at the rising edge of clock SBI1pin Data is output at the falling edge of cl
443. in control direction register PODIR to 1 1 and set PODIR4 to 0 to set P05 to output mode to set P04 to input mode 5 Set the SC2LNG2 0 flag of the serial 2 mode register 0 SC2MD0 to 111 to set the transfer bit count to 8 bits Set the SC2STE flag of the SC2MDO register to 0 to disable start condition Set the SC2DIR flag of the SC2MDO register to 0 to set MSB as the first transfer bit Set the SC2CE1 flag of the SC2MDO register to 1 to set the transmission data output edge to rising and the received data input edge to falling 6 Set the SC2CMD flag of the SC2CTR register to 0 to select serial data tansmission 7 Set the SC2MST flag of the SC2MD1 register to 1 to select clock master internal clock Set the SC2SBOS SC2SBIS SC2SBTS flags of the SC2MD register to 1 to set the SBO2 pin to serial data output the SBI2 pin to serial data input and the SBT2 pin to transfer clock I O Set the SC2IOM flag to 0 to set serial data input from the SBI2 pin 8 Set the interrupt level by the SC2LV1 0 flag of the serial 2 interrupt control register SC2ICR 9 Enable the interrupt to by setting 1 to the SC2IE flag of the SC2ICR register If the interrupt request flag SC2IR of the SC2ICR register is already set clear SC2IR before enable interrupt 10 Set the transmission data to the serial transmission reception shift register TXBUF2 The internal clock is generated to start transmissio
444. inary counter clear source and the PWM output set H output source The TM7OC1 compare match or the TM7OC2 compare match can be selected as a PWM output reset L output source with the T7PWMSL flag of the TM7MD2 register VI 28 16 bit Standard PWM Output Only duty can be changed consecutively 6 16 bit Timer 6 6 2 Setup Example ea Standard PWM Output Setup Example The TM71O output pin outputs the 1 4 duty PWM output waveform at 305 18 Hz with the timer 7 at the high fre quency oscillation fosc 20 MHz One cycle of the PWM output waveform is decided by the overflow of the binary counter H period of the PWM output waveform is decided by the set value of the compare register 1 An example setup procedure with a description of each step 15 shown below TM7IOA 400 Hz Figure 6 6 4 Waveform of output pin Setup Procedure Description 1 Stop the counter 1 Set the TM7EN flag of the timer 7 mode register TM7MD 1 0x3F78 1 7 1 to 0 to stop the timer 7 counting bp4 TM7EN 0 2 Select the pin 2 Switch the timer pin TMSEL 0x03F3F Set the TM7SEL flag of the TMSEL register to 0 bp6 TM7SEL 0 toselect the TM710A as the input pin 3 Set the special function pin to output 3 Set the P1OMD6 flag of the port 1 output mode P1OMD 0x03F2B register P1OMD to 1 to set the P16 pin as aspecial bp6 P1OMD6 1 function pin Set the P1DIR6
445. ing burst transfers using external interrupt 0 You can enable or disable ATC1 shut down with the burst transfer stop enable flag BSTP of control register 1 ATICNTI When BTSTP 1 and the interrupt request flag for external interrupt 0 the IRQOIR flag in the IRQOICR register is set the ATCI data transfer shuts down immediately During this shutdown the transfer counter and the memory pointers save the values they contained prior to the shutdown When the interrupt service routine ends and a new trigger factor occurs the burst transfer restarts from the point at which it stopped 1 When burst transfer stop is enabled do not select external interrupt 0 for ATC1trigger factor XVIII 34 Operation 18 Automatic Transfer Controller 18 4 Setup Example An example setup procedure with a description of each step is as follows Setup Procedure Description 1 Set the data transfer mode AT1CNTO OxSFDO bp7 FMODE bp6 AT1ACT 0 bp5 2 AT1MD3 0 bp0 0 2 Set memory pointer 0 AT1MAPOL 0x03FD3 1 0x03FD4 AT1MAPOH 0x03FD5 3 Set memory pointer 1 AT1MAP1L 0x03FD6 AT1MAP1M 0x03FD7 AT1MAP1H 0x03FD8 4 Set the transfer data counter AT1TRC 0x03FD2 5 Select the ATC1 activation factor AT1CNT1 0x03FD1 bp4 BTSTP bp3 0 AT1IR3 0 6 Enable ATC operation AT1CNTO0 0x03FD0 AT1EN 1 1 Select the data trans
446. ing method to the received data buffer RXBUF4 is different depending on the first transfer bit selection At MSB first data are stored to the upper bits of RXBUF4 When there are 7 bits to be transferred as shown on Table 15 3 18 if data G to A are stored to bp7 to bp of RXBUF4 At LSB first data are stored to the lower bits of RXBUF4 When there are 7 bits to be transferred as shown on Table 15 3 19 if data A to G are stored to bpO to bp6 of RXBUFA RXBUF4 IHE G Figure 15 3 18 Transfer Bit Count and First Transfer Bit starting with MSB RXBUF4 G F E D Figure 15 3 19 Transfer Bit Count and First Transfer Bit starting with LSB The following items are the same as clock synchronous serial B First Transfer Bit Setup Refer to XV 13 B Transmission Data Buffer Refer to XV 13 B Received Data Buffer Refer to XV13 B Transfer Bit Count and First Transfer Bit Refer to XV 14 B Transmission Buffer Empty Flag Refer to XV 18 B Emergency Reset Refer to XV 19 XV 42 Operation 15 Serial interface 4 B Transmission Timing TXD4 pin Parity fStop Stop bit bit SC4TBSY Data settoTXBUF4 Z Interrupt SC4TIRQ Figure 15 3 20 Transmission Timing parity bit is enabled TXD4 pin Stop bit SCATBSY Data set to TXBUF4 T Interrupt SC4TIR Figure 15 3 21 Transmission Timing parity bi
447. ing of IOW is a function which CPU supports for special use for example when special function register or is expanded to external For this LSI wait cycle setting is not always necessary Select no wait cycle for high performance system construction Automatic data trasnsfer function ATC1 that accesses an external memory cannot be used Y in processsor mode and memory expansion mode sion mode at internal memory setting internal ROM internal RAM special register setting 1 To use the automatic data trasnsfer function ATC1 in processsor mode and memory set the NCS P74 NRE P75 NWE P76 pins to 1 output and pull up Bus Interface II 39 2 CPU Basics Expansion Address Control Register EXADV Table 2 4 2 Expansion Address Control Register EXADV 0x03F0E bp 7 6 5 4 3 2 1 0 Flag EXADV3 EXADV2 EXADV1 At reset 0 0 0 Access R W EXADV3 A19 to 16 address output during memory expansion mode 0 General port 1 19 to 16 address output A15 to 12 address output during memory expansion mode EXADV2 0 General port 1 15 to 12 address output EXADV1 A11 to 8 address output during memory expansion mode 0 General port 1 A11 to 8 address output In memory expansion mode unused address pins can be used as general ports 40 Bus Interface Chapter 2
448. input i POIN4 Port input data lt 1 lt I R Serial 2 transmission data input Figure 4 2 5 P04 Block Diagram Reset 5 R Nch open drain control K Reset DR POPLU5 R Pull up resistor control K Reset direction control DR PODIRS R K 05 POOUTS R Port output data 1 Schmitt trigger input Port input data Serial 2 clock input Serial 2 2 clock output SC2MD1 SC2SBTS Figure 4 2 6 P05 Block Diagram IV 12 Port 0 Chapter 4 I O Ports Reset Pull up resistor control pog POPEUS D gt WEK R Reset 5 direction control PODIRG gt m WEK R 5 EIE ae P06 D Port output data 2 1 POSUTO Schmitt trigger input 6 Port input data lt Z D A output control R D A output Figure 4 2 7 P06 Block Diagram Port 0 IV 18 4 I O Ports 14 4 3 Port 1 4 3 1 Description General Port Setup To output the data to pins set the control flag of the port 1 direction control register PIDIR to 1 to write the value of the port 1 output register PIOUT To read input data of pins set the control flag of the port 1 direction control register PIDIR to 0 to read the value of the port 1 input register Each bit can be set individuall
449. inter 0 for any memory space is the destination address When the first data byte transfer ends the address in memory pointer 0 increments by one In the second data byte transfer the incremented address in memory pointer 0 becomes the source address and the space address 0 03 00 OxO3FFF in memory pointer 1 becomes the destination address The adsdress in memory pointer 0 remains unchanged after the second data byte transfer ends Set the I O address in lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the space address 0x03F in In transfer mode 6 ATC1 executes a data byte transfer twice everytime when activated The value in memory pointer 0 increments by one everytime a byte length data transfer ends As a result the source address for the next operation is two addresses higher than that for the previous operation Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated after one byte of data is transferred twice When it reaches 0x00 an interrupt ATC1IRQ occurs and the automatic transfer ends Operation XVIII 23 18 Automatic Transfer Controller 18 3 12 Transfer Mode 7 In transfer mode 7 ATC1 automatically transfers one byte of data two times everytime an ATC1 activation request occurs
450. interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 12 Timer 3 Interrupt Control Register TM3ICR 0x03FEB bp 7 6 1 0 Flag TM3LV1 TM3LV0 TMSIR At reset 0 0 0 0 Access R W Description TM3LV1 Interrupt level flag TM3LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 29 Chapter 3 Interrupts Timer 4 Interrupt Control Register TM4ICR The timer 4 interrupt control register TM4ICR controls interrupt level of timer 4 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 13 Timer 4 Interrupt Control Register TM4ICR 0x03FEC bp 7 6 5 4 3 2 1 0 Flag TM4LV1 TM4LVO TMAIE TM4IR At reset 0 0 0 0 Access R W Description TM4LV1 Interrupt level flag TM4LV0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt r
451. irecton control Port output data Input mode control Port input data Analog input Pull up pull down resistor selection Pull up pull down resistor control directon control Port output data Input mode control Port input data Analog input IV 104 Port A snq eeg M ME Un PAIMD6 VR PAING M Schmitt trigger input g Bg TTE snq Figure 4 12 7 PA6 Block Diagram Reset PADWN m 2 Reset ro PAPLU7 m o S R PADIR7 Lee PAOUT7 R Reset R PAIMD7 D LO TT ew Y gt Schmitt trigger input 57 Z Figure 4 12 8 PA7 Block Diagram Chapter 4 I O Ports 4 13 Port D 4 13 1 Description General Port Setup To output the data to pins set the control flag of the port D direction control register PDDIR to 1 to write the value of the port D output register PDOUT To read input data of pins set the control flag of the port D direction control register PDDIR to 0 to read the value of the port D input register PDIN Each bit can be set individually as either an input or output by the port D I O direc
452. ission Reception Shift Register SC3TRB 0x03FA8 3 2 1 0 SC3TRB3 SC3TRB2 SC3TRB1 SC3TRBO 7 6 5 4 SC3TRB7 SC3TRB6 SC3TRB5 SC3TRB4 X X X X X X X X Access XIV 6 Control Registers 14 2 4 Serial interface Mode Register Chapter 14 Serial Interface 3 Serial Interface Mode Register 0 SC3MDO 0x03FA4 bp 7 6 4 3 2 1 0 Flag At reset SC3BSY 0 SC3CE1 SC3DIR 0 0 SC3STE 0 SC3LNG2 1 SC3LNG1 1 SC3LNGO 1 Access bp R Flag SC3BSY Description 0 Other use R W 1 Serial transmission is in progress R W Serial bus status in clock synchronous communication R W R W SC3CE1 Transmission data output edge 0 Falling 1 Rising Reception data input edge Rising Falling SC3DIR First bit to be transferred 0 MSB first 1 LSB first SC3STE SC3LNG2 SC3LNG1 SC3LNGO Start condition 0 Disable start condition 1 Enable start condition Transfer bit count 000 1 bit 001 2 bit 010 3 bit 011 4 bit 100 5 bit 101 6 bit 110 7 bit 111 8 bit Control Registers 7 14 Serial Interface 3 Serial interface 3 Mode Register 1 SC3MD1 0x03FA5 bp 7 6 5 4 2 Flag SC3IOM SC3SBTS SC3SBIS SC3SBOS SC3MST At reset 0 0 0 0 0 Access SC3IOM Description S
453. ist Register Address Function 0 03 10 Port 0 Output Register 0x03F20 Port 0 Input Register 0x03F30 Port 0 Direction Control Register 0x03F40 Port 0 Pull up Resistor Control Register 0x03F1C Port 0 Nch Open drain Control Register 0x03F11 Port 1 Output Register 0x03F21 Port 1 Input Register 0x03F31 Port 1 Direction Control Register 0x03F41 Port 1 Pull up Resistor Control Register 0x03F2B Port 1 Output Mode Register P1CNTO OxO3F7E Port 1 Output Control Register 0 P2OUT 0x03F12 Port 2 Output Register P2IN 0x03F22 Port 2 Input Register P2DIR 0x03F32 Port 2 Direction Control Register P2PLU 0x03F42 Port 2 Pull up Resistor Control Register P3OUT 0x03F13 Port 3 Output Register P3IN 0x03F23 Port 3 Input Register P3DIR 0x03F33 Port 3 Direction Control Register P3PLU 0x03F43 Port 3 Pull up Resistor Control Register P3ODG 0x03F2C Port 3 Nch Open drain Control Register P4OUT 0x03F14 Port 4 Output Register P4IN 0x03F24 Port 4 Input Register P4DIR 0x03F34 Port 4 Direction Control Register P4PLU 0x03F44 Port 4 Pull up Pull down Resistor Control Regis ter P4ODG Port 4 Control Register 0x03F4B Pull up Pull down Resistor Selection Register P5OUT 0x03F15 Port 5 Output Register Overview Register Address 0x03F25 Function Port 5 Input Register Chapter 4 I
454. it Time External Interrupts Chapter 3 Interrupts III 70 External Interrupts 4 Ports 4 I O Ports 2 4 1 Overview 4 1 1 Port Overview A total of 85pins on this LSI including those shared with special function pins are allocated for the I O ports of port 0 port 1 port 2 port 3 port 4 port 5 port port 7 port 8 port 9 port A and port D 4 1 2 I O Port Status at Reset Table 4 1 1 port status at reset single chip mode mode Input mode Pull up Pull down resistor No pull up resistor I O port special functions port Input mode No pull up resistor I O port Input mode P27 Pull up resistor Others No pull up resistor I O port Input mode No pull up resistor port Input mode No pull up pull down resistor port Input mode No pull up resistor port Input mode No pull up resistor port Input mode No pull up pull down resistor port Input mode No pull up resistor port Input mode No pull up resistor port Input mode No pull up pull down resistor port Input mode Overview No pull up resistor port Input mode Table 4 1 2 I O port status at reset processor mode Pull up Pull down resistor No pull up resistor Chapter 4 I O Ports I O port special functions
455. it settings for I O and external memory spaces apply The following is the access timing for each memory space assuming no wait situation Internal ROM RAM space 2 cycles space special registers 3 cycles In Figure 18 3 1 ATC1 Timing Chart the time from the rising of DMA activation request sig nal to the starting of LOAD cycle depends on the state of CPU but it takes max 9 cycles Operation XVIII 13 18 Automatic Transfer Controller 18 3 2 Memory Address Setting Setting of transfer addresses to the memory pointers The address of the memory space for an automatic data transfer ATC1 should be set in the both of memory pointer 0 ATIMAPO and memory pointer 1 In each transfer mode one of those pointer is the source address and another is the destination address Memory pointer 0 functions Memory pointer 0 is consists of three 8 bit registers ATIMAPOH ATIMAPOM and ATIMAPOL ATIMAPOH holds upper 4bits of the 20 bit address ATIMAPOM contains the middle 8 bits and ATIMAPOL contains lower 8 bits The 20 bit address set in memory pointer 0 points to a specific address in the total memory space of 1 MB Memory pointer 0 also contains a computational function that enables it to increment the address based on the transfer state You can disable this function for all transfer modes by setting the FMODE bit of control reg ister 0 to 1 Memory pointer 1 functions
456. ith 2 channels the SBO4 pin inputs outputs serial data The port direction control register PADIR switches I O At reception set SC4SBIS of the SC4MD1 register to 1 always to select serial input The SBIA pin can be used as a general port This serial interface contains a emergency reset function If the communication should be stopped by force set SCASBOS and SCASBIS of the SCAMD 1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 15 2 1 except TXBUF4 are set Transfer rate of transfer clock set by the SC4MD3 register should be under 5 0 MHz Operation 15 Serial interface 4 B Transmission Reception Setup Example Standby Mode Reception The setup example for clock synchronous serial communication with serial 4 is shown Table 15 3 13 shows the condition at standby mode reception Table 15 3 13 Setup Examples for Synchronous Serial Interface Transmission Reception Standby Mode Reception Setup item Set to Serial data input pin Select SBI4 Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Clock Clock slave Operation mode Stop mode Clock source fs 2 Clock source 1 8 dividing Not divided by 8 SBT4 SBO4 pin style Push pull SBT4 pin pull up resistor Not
457. ith the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register Port 8 Chapter 4 I O Ports P87 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register 4 10 2 Registers The following Table shows registers that control the Port 8 Table 4 10 1 Port 8control register Registers Address Function 0x03F18 Port 8 Output Register 0x03F28 Port 8 Input Register 0x03F38 Port 8 Direction Control Register 0x03F48 Port 8 Pull up Resistor Control Register R W Readable Writable Port 8 Output Register PBOUT 0xOSF18 P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUTO x x x x x x x x P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUTO Output data 0 Output L VSS level 1 Output H VDD level O Q O Port 8 IV 81 4 I O Ports Port 8 Input Register P8IN 0x03F28 bp Flag Description 7 P8IN7 6 P8ING in Input data 0 Pin is L VSS level 3 1 Pin is H VDD level 2 P8IN2 1 P8IN1 0 P8IN0 Port 8 Direction Control Register P8DIR 0x03F38 Flag P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W
458. k cycle See Fig 2 5 2 for setup of bp3 0 flags of the CPU mode control register CPUM Clock Switching Il 51 2 CPU Basics High speed 0 oscillation 0 Low speed oscillation E osc1 Dividing counter 2 dividing 4 dividing gt 8 dividing 16 dividing gt 32 dividing 64 dividing gt 128 dividing 001 000 011 010 101 100 111 110 System clock fs Oscse Oscsel0 OscdbL Figure 2 6 1 Clock Switching Circuit OSCSEL1 OSCSELO OSCDBL Oscillating frequency 0 0 0 2 0 0 1 1 0 1 0 8 0 1 1 4 1 0 0 32 1 0 1 16 1 1 0 128 1 1 1 64 Figure 2 6 2 Setting Division Factor at NORMAL mode by combination of OSCSEL and OSCDBL Do not set STANDBY function STOP HALT OSC1 and OSC2 flags and clock swiching function OSCDBL OSCSEL1 and OSCSEL2 flags at the same time a OSCDBL OSCSEL1 and OSCSELO flags can be set at the same time 52 Clock Switching Chapter 2 CPU Basics 2 Reset 2 7 1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin is pulled to low Initiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low NRST pin should be held low for more than OSC 4 clock cycles 100 ns at a 10 MHz NRST 4 Oscilla
459. l P3DIR4 wek VR gt P34 Port output data gPSOUT4 S wek R 777 Schmitt trigger input i P3IN4 Port input data lt J R Serial 3 transmission data input Nch open drain control Pull up resistor control direction control Port output data Port input data Serial 3 clock input Serial 3 IIC3 clock output SC3MD1 SC3SBTS IV 40 Port 3 Reset 5 K R Figure 4 5 5 P34 Block Diagram Reset P3PLU5 K R Reset 5 K R P3OUT5 o R P35 Schmitt trigger input Figure 4 5 6 P35 Block Diagram Chapter 4 I O Ports 46 Port 4 4 6 1 Description General Port Setup To output the data to pins set the control flag of the port 4 direction control register PADIR to 1 to write the value of the port 4 output register PAOUT To read input data of pins set the control flag of the port 4 direction control register PADIR to 0 to read the value of the port 4 input register PAIN Each bit can be set individually as either an input or output by the port 4 I O direction control register PADIR The control flag of the port 4 direction control register PADIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up or pull down resistor is added or not by the port 4 pull up pull down resistor control register PAPLU Set the control flag of the port 4 pull up pull do
460. l interface Transfer clock source fosc 2 fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 fs 2 fs 4 Timer 2 Timer 3 output External clock MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected Sequence transmission reception or both are available Single master IIC Single master IIC communication is available 9 bits transfer Serial 3 Single master Synchronous serial interface Synchronous serial interface Transfer clock source fosc 2 fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 fs 2 fs 4 Timer 3 Timer 5 output MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected Sequence transmission reception or both are available Single master IIC Single master IIC communication is available 9 bits transfer Serial 4 Full duplex UART Synchronous serial interface Synchronous serial interface Transfer clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 2 Timer 5 output External clock MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected Sequence transmission reception or both are available Full duplex UART Baud rate timer timer 2 or timer 5 Parity check Overrun error Framing error detection Transfer size 7 to 8 bits can be selected In UART communication transmission complete
461. l of 0 to 3 to interrupt requests SC1RIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SCARIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated III 38 Control Registers 3 Interrupts Serial 1 UART Transmission Interrupt Control Register SC1TICR The serial 1 UART transmission interrupt control register SCITICR controls interrupt level of serial 1 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 22 Serial 1 UART Transmission Interrupt Control Register SC1TICR 0x03FF5 bp 7 6 5 4 3 2 1 0 Flag SC1TLV1 SC1TLVO SC1TIE SCATIR At reset 0 0 0 0 Access R W SC1TLV1 SC1TLV0 Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests SC1TIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SC1TIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers III 39 Chapter 3 Interrupts Serial 2 Interrupt Control Register SC2ICR The serial 2 interrupt control register SC2ICR controls interrupt level of serial 2 interrupt interrupt enable flag and interrupt request Interrupt control regis
462. l register EXADV Memory Control Register MEMCTR Table 2 4 1 Memory Control Register MEMCTR 0x03F01 bp 7 6 5 4 3 2 1 0 Flag IOW1 IOWO IVBM EXMEM EXWH IRWE EXW1 EXWO At reset 1 1 0 0 1 0 1 1 Access R W b Flag Description Wait cycles when accessing special register area 00 No wait cycles 01 1 wait cycle 10 2 wait cycles 11 3 wait cycles Base address setting for interrupt vector table Interrupt vector base 0x04000 Interrupt vector base 0x00100 Memory expansion mode Do not expand external memory Expand external memory Fixed wait cycle mode or handshake mode Handshake mode Fixed wait cycle mode Software write enable flag for interrupt request flag Software write disable Even if data is written to each interrupt control register xxxICR the state of the interrupt request flag xxxIR will not change Fixed wait cycles 00 No wait cycles 01 1 wait cycle 10 2 wait cycles 11 3 wait cycles Il 38 Bus Interface Chapter 2 CPU Basics The EXW1 EXWO wait settings affect accesses to external devices in the processor mode and memory expansion mode After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles The IOW1 IOWO wait settings affect accesses to the special registers located at the addresses 0x3E00 0x3FFF After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles Wait sett
463. l transfer is In the case of the enabled start condition at SCASTE flag 1 is output despite of the setting value of the SCAFDCI to 0 Table 15 3 5 SBO4 Output after the Data Output Holding Period of the Last Bit without start condition SBO4 output after the data SC4FDC1 flag SC4FDCO flag output holding period of the last bit 0 0 1 High output fix 1 0 Last data holding 0 1 O Low output fix 1 1 Reserved Operation XV 19 15 Serial interface 4 Other Control Flag Setup Table 15 3 6 shows flags that are not used at clock synchronous communication So they are not needed to set or monitor Table 15 3 6 Other Control Flag Register Flag Detail SC4MD2 SC4BRKE Break status transmission control SC4BRKF Break status reception monitor SC4NPE Parity enable SC4PM1 to 0 Added mode specification SC4FM1 to 0 Frame mode specification SC4STR SC4PEK Parity error detection SC4FEF Frame error detection XV 20 Operation 15 Serial interface 4 B Transmission Timing At master At slave Tmax 2 57 T T 2 Clock SBT4 pin Output pin SBO4 pin Transfer bit counter SC4 TBSY Data set to TXBU F4 Interrupt SCATIRQ Figure 15 3 6 Transmission Timing at falling edge start condition is enabled At master At slave Tmax 3 5T T 2 Clock SBTOM pin Output pi
464. lag is stopped 0 the binary counter is stopped 8 bit Timer Count 5 8 bit Timers When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the compare register is set the smaller than the binary counter during the count operation the binary counter counts up to the overflow at first If the interrupt is enabled the timer interrupt request flag should be cleared before timer is started The timer n interrupt request generation at TMnOC 0x00 has the same waveform at TMnOC 0x01 At NORMAL operation when fx is selected as the clock source even the value is written to the compare register with stopped the binary counter it might not be cleared To clear the binary counter definitely any value should be written to the compare register after the clock source which is synchronized to fosc or fs is selected When fx is used as the clock source clear the binary counter before starting the timer tion Also when 0x00 is set to the compare register use the synchronous fx 8 bit Timer Count V 29 5 8 bit Timers 5 4 2 Setup Example Timer Operation Setup Example Timers 0 1 2 3 4 and 5 Timer function can be s
465. lag of the ANCTRO register The sampling time of A D converter depends on external circuit so set the right value by analog input impedance Table 16 3 3 Sampling Time of A D Conversion and A D Conversion Time ANSH1 ANSHO Sampling A D conversion time us time Ts at high speed at low speed fx fs 10 MHz 8 19 kHz at TAD at TAD at TAD at TAD at TAD 800 ns 954 65 ns 1 91 us 15 26 us 15 26 us 0 0 Tap x 2 12 95 15 42 30 71 244 31 427 31 1 Tap X6 16 15 19 24 38 35 305 35 488 35 1 0 18 25 75 30 70 61 27 488 47 671 47 1 Tap X18 25 75 30 70 61 27 488 47 671 47 Calculated as fosc 20 MHz fx 32 768 kHz fs fosc 2 fx 4 conversion time above Actual conversion time is value that is added 1 Tap to conversion time Calculus Conversion Time Ts 14TAp 1 5 fs a Sampling time of analog signal after enabled A D conversion start flag is not mentioned in Built in Ladder Resistance Control The ANLADE flag to the ANCTRO register is set to 1 to send a current to the ladder resistance for A D conver sion When A D converter is stopped the ANLADE flag of the ANCTRO register is set to 0 to save the power consumption Table 16 3 4 A D Ladder Resistance Control ANLADE A D ladder resistance control 0 A D ladder resistance control disabled A D conversion stop 1 A D ladder resistance control enabled A D conversion halt
466. lection 0 Data input from SBI1 RXD1 1 Data input from SBO1 TXD1 SC1SBTS SBT1 pin function selection 0 Port 1 Transfer clock I O SC1SBIS Serial input control selection 0 Input 1 1 Input serial SC1SBOS SBO1 TXD1 pin function 0 Port 1 Output serial data SC1CKM 1 8 dividing of transfer clock selection 0 Not divided by 8 1 Divided 1 8 SC1MST Clock master slave selection 0 Clock slave 1 Clock master SC1CMD Control Registers Synchronous serial full duplex UART selection 0 Synchronous serial 1 Full duplex UART 12 Serial interface 1 Serial interface 1 Mode Register 2 SC1MD2 0x03F9F bp 7 6 5 4 3 1 0 Flag SC1FM1 SC1FMO SCIPM1 SC1PMO 5 SC1BRKF SC1BRKE Reset 0 0 0 0 0 0 0 Access R W R W R Description Frame mode specification 00 7 data bit 1 stop bit 01 7 data bit 2 stop bit 10 8 data bit 1 stop bit 11 8 data bit 2 stop bit SC1FM1 SC1FM0 Added bit specification Transmission Reception SC1PM1 00 Add 0 Check for 0 SC1PMO 01 Add 1 Check for 1 10 Add odd parity Check for odd parity 11 Add even parity Check for even parity Parity enable SC1NPE 0 Enable parity bit 1 Disable parity bit Break status receive monitor SC1BRKF 0 Data reception 1 Break reception Break status transmit control SC1BRKE 0 Data transmission 1 Break transmission Control
467. location 0x04004 in the interrupt vector table The watchdog timer overflow interrupt request flag IRQNWDG is set to 1 when the watchdog timer overflows The program interrupt request flag IRQNPG is set to 1 when the undefined instruction is executed Setting PIR or WDIR flag to be 1 enable non maskable interrupt request to be set compulsory Table 3 2 2 Non maskable Interrupt Control Register NMICR 0x03FE1 bp 7 6 5 4 3 2 1 0 Flag IRQNPG IRQNWDG Reserved At reset 5 0 0 0 Access R W Description IRQNPG Program interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQNWDG Watchdog interrupt request flag 0 No interrupt request 1 Interrupt request generated Reserved Set always to 0 interrupt at the same time of the setting of the program interrupt request flag IRQNPG When the setting of the IRQNPG flag is confirmed by the non maskable interrupt process program the softreset is recommended by outputting 0 to the reset pin P27 a When the undefined instruction is going to be executed this LSI generates the non maskable Control Registers Ill 19 Chapter 3 Interrupts External Interrupt 0 Control Register IRQOICR The external interrupt 0 control register IRQOICR controls interrupt level of the external interrupt 0 valid edge interrupt enable and interrupt request Interrupt con
468. lock 5 3 pin Input pin SBI3 pin Transfer bit counter SC3BSY 4 Write data to TXBUF3 Interrupt SC3IRQ Figure 14 3 16 Reception Timing Rising edge Start condition is disabled XIV 26 Operation B Pins Setup 3 channels at transmission Chapter 14 Serial Interface 3 Table 14 3 6 shows the pins setup at synchronous serial interface transmission with 3 channels SBO3 pin SBI3 pin SBT3 pin Table 14 3 6 Synchronous Serial Interface Pins Setup 3 channels at transmission Item Data output pin Data input pin Clock I O pin pin SBISA pin SBT3A SBT3B SBO3B pin pin Clock master Clock slave SC3MD1 SC3MST Pin P33 P93 P34 P94 P35 P95 Port pin selection Select the used pin A B SCSEL SC3SEL SBI3 SBO3 pin SBI3 SBO3 independent selection SC3MD1 SC3IOM Function Serial data output 1 input Transfer clock I O Transfer clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBTS Type Push pull N ch open Push pull N ch Push pull N ch drain open drain open drain P30DC P30DC5 POODC P9ODC5 P9ODC P9ODC3 Output mode Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR5 P9DIR P9DIR5 P9DIR P9DIR3 Pull up added not added added not added added not added P3PLU P3PLU3 P3PLU P3PLU5 P PLU P9PLU5 P9PLU P9PLU3
469. lock input output Set the SC4IOM flag 0 to set the serial data input from the SBIA pin 12 Set the interrupt level by the SC4LV1 to 0 flag of the serial 4 UART transmission interrupt control register SCATICR Set level 2 13 Set the SC4TIE flag of the SCATICR register to 1 to enable the interrupt If any interrupt request flag SC4TIR of the SCATICR register is already set clear SC4TIR before the interrupt is enabled Chapter 3 3 1 4 Setup 14 Set the dummy data to the serial transmission data buffer TXBUFA Operation 15 Serial interface 4 Setup Procedure Description 15 Transfer to STOP mode CPUM 0x03F00 bp3 STOP 1 16 Start the serial communication Transmission clock y input SBT4 pin Received data input 5814 pin 17 Recover from the standby mode 15 Set the STOP flag of the CPUM register to 1 to transfer to the stop mode 16 Input the transfer clock to the SBT4 pin and transfer data to the SBI4 pin 17 The serial 4 UART transmission interrupt SC4TIRQ is generated at the same time of the 8 bits data reception then CPU is recovered from the stop mode to the normal mode after the oscillation stabilization wait Note Each procedure 1 to 2 5 to 8 9 to 11 can be set at the same time The slave reception at the standby mode should be used without the start condition to Y receive properly be operated after all c
470. lock is output after the SCATIRQ generation Automatic Continuous Transfer This serial enables the start up by the data automatic transfer ATC1 On start up by ATC1 255 bytes data trans fer can be operated Refer to chapter 18 Automatic Transfer Controller overview transfer mode 8 to 9 about the generation of ATCI B Input Edge Output Edge Setup The 4 1 flag of the SCAMDO register set an output edge of the transmission data an input edge of the received data As the SCACEI flag 0 the transmission data is output at the falling edge and as 1 output at the rising edge As SCACEI O the received data is received at the inversion edge to the output edge of trans mission data and as 1 stored at the same edge Table 15 3 2 Transmission Data Output Edge and Received Data Input Edge SC4CE1 Transmission data output edge Received data input edge 0 Operation 15 Serial interface 4 Clock Setup The SC4PSC2 to 0 of the SC4MD3 register selects the clock source from the special prescaler and timer 2 timer 5 2 lines output The special prescaler starts its operation after the SC4PSCE flag of the SCAMDI register selects enable count The SCAMST flag of the SCAMDI register can select the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock that has the sam
471. m1 0 11 Figure 3 1 7 Processing Sequence for Non Maskable Multiple Interrupt Overview Ill 15 Chapter 3 Interrupts 3 1 4 Interrupt Flag Setup Interrupt Request Flag IR Setup by the Software The interrupt request flag is operated by the hardware That is set to 1 when any interrupt factor is generated and cleared to 0 when the interrupt is accepted If you want to operate it by the software the IRWE flag of MEMCTR should be set to 1 B Interrupt Flag Setup Procedure A setup procedure of the interrupt request flag set by the hardware and the software shows as follows Setup Procedure Description 1 Disable all maskable interrupts PSW bp6 MIE 0 2 Select the interrupt factor 3 Enable the interrupt request flag to be rewritten MEMCTR 0x03F01 bp2 IRWE 1 4 Rewrite the interrupt request flag bp0 xxxIR 5 Disable the interrupt request flag to be rewritten MEMCTR 0x bp2 IRWE 0 6 Set the interrupt level xxxICR bp7 6 xxxLV1 0 PSW bp5 4 IM1 0 7 Enable the interrupt xxxICR 21 8 Enable all maskable interrupts PSW bp6 MIE 1 16 Overview 1 Clear the MIE flag of PSW to disable all maskable interrupts This is necessary especially when the inter rupt control register is changed 2 Select the interrupt doctor such as interrupt edge selection or timer interrupt cycle change 3 Set the IRWE flag of MEMCTR to enable the in
472. ming of Timer Operation Time Base Timer When the selected interrupt cycle is passed the interrupt request flag of the time base interrupt control register TBICR is set An interrupt may be generated at switching of the clock source Enable the interrupt after switching the clock source The initialization can be done by writing an arbitrary value to the time base timer clear control register TBCLR VII 16 Time Base Timer 7 4 2 Setup Example Chapter 7 Time Base Timer Free running Timer Timer Operation Setup Time Base Timer An interrupt can be generated constantly with time base timer in the selected interrupt cycle The interrupt gener ation cycle is fosc x 1 213 1 ms fosc 8 192 MHz to generate interrupts An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Disable the interrupt TBICR OxOSFEF bp1 TBIE 0 2 Select the clock source TM6MD 0x03F6A bp0 TM6CKO 0 3 Select the interrupt generation cycle TM6MD 0x03F6A bp6 4 TM6IR2 0 100 4 Initialize the time base timer TBCLR 0x03F6B 0x00 5 Set the interrupt level TBICR 0x03FEF bp7 6 TBLV1 0 01 6 Enable the interrupt TBICR OxOSFEF bp1 TBIE 1 7 Start the time base timer operation TM6BEN 0x03F6C bp1 TBEN 1 1 Set the TBIE flag of the TBICR register to 0 to disable the interrupt 2 Select fosc as a clock source by the TM6CKO
473. mmunication complete interrupt is generated after the data is loaded to the internal shift register At master communication there is output after the pension of communication for 4 transfer clocks till the next transmission clock is output after the SCITIRQ generation Automatic Continuous Transfer This serial enables the start up by the data automatic transfer ATC1 On start up by ATC1 255 bytes data trans fer can be operated Refer to chapter 18 Automatic Transfer Controller overview transfer mode 8 to 9 about the generation of ATCI B Input Edge Output Edge Setup The 5 flag of the SCIMDO register set an output edge of the transmission data an input edge of the received data As the SCICEI flag 0 the transmission data is output at the falling edge and as 1 output at the rising edge As SCICEI O the received data is received at the inversion edge to the output edge of trans mission data and as 1 stored at the same edge Table 12 3 2 Transmission Data Output Edge and Received Data Input Edge SC1CE1 Transmission data output edge Received data input edge 0 Operation 12 Serial interface 1 Clock Setup The SCIPSC2 to 0 of the SC1MD3 register selects the clock source from the special prescaler and timer 4 timer 5 2 lines output The special prescaler starts its operation after the SCIPSCE flag of t
474. mode automatically P73 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp7 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp7 of the address output control register EXADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P74 1s output pin of the data chip select signal at the processor mode or the memory extension mode These modes are set to the output modes automatically P75 is output pin of the data read enable signal at the processor mode or the memory extension mode These modes are set to the output modes automatically P76 is output pin of the data write enable signal at the processor mode or the memory extension mode These modes are set to the output modes automatically P77 is input pin of the data acknowledge signal at the processor mode or the memory extension mode These modes are set to the input modes automatically Port 7 Chapter 4 I O Ports 4 9 2 Registers C raf The following Table shows registers that control the Port 7 Table 4 9 1 Port 7control register Registers Address R W Function Page P7OUT 0 03 17 R W Port 7 Output Register IV 67 R 0x03F27 Port 7 Input Register 0x03F37 R W Port 7 Direction Control Register 0x03F47 R W Port 7 Pull up Pull down Resistor
475. n But on some other instruction such as branch instruction instruction queue becomes empty on the time that the next operation code to be executed is stored to instruction register at the last cycle Therefore only when instruc tion queue is empty and direct address da or immediate data imm are needed instruction queue keeps waiting for a cycle Instruction queue is controlled automatically by hardware so that there is no need to be controlled by software But when instruction execution time is estimated operation of instruction queue should be into consideration Instruction decoder generates control signal at each cycle of instruction execution by micro program control Instruction decoder uses pipeline process to decode instruction queue at one cycle before control signal is needed Overview Il 7 2 CPU Basics 2 1 5 Registers for Address B s V lt m s Registers for address include program counter PC address registers A0 A1 and stack pointer SP Program Counter PC This register gives the address of the currently executing instruction It is 21 bits wide to provide access to a 1 MB address space in half byte 4 bit increments The LSB of the program counter is used to indicate half byte instruc tion The program counter after reset is stored from the value of vector table at the address of 0x04000 Program counter Figure 2 1 3 Program Counter Address Registers
476. n SBO4 pin Transfer bit counter SC4 TBSY 4 Data set to TXBUF4 Interrupt SCATIRQ Figure 15 3 7 Transmission Timing at falling edge start condition is disabled Operation XV 21 15 Serial interface 4 At master At slave Tmax 2 5T T T 2 e MM EON Clock SBT4 pin Output pin SBO4 pin Transfer bit counter SCATBSY Data set to TXBUF4 Interrupt SCATIRQ Figure 15 3 8 Transmission Timing at rising edge start condition is enabled At master At slave Tmax 3 5T 2 i Clock SBT4 pin Output pin SBO4 pin Transfer bit counter SC4TBSY 7 Data set to TXBUF4 Interrupt SCATIRQ Figure 15 3 9 Transmission Timing at rising edge start condition is disabled XV 22 Operation 15 Serial interface 4 B Reception Timing Clock SBT4 pin Input pin SBO4 pin Transfer bit counter SC4RBSY Interrupt SC4TIRQ Figure 15 3 10 Reception Timing at rising edge start condition is enabled At master Tmax 3 5T T Clock SBTO pin Input pin 5814 5804 pin Transfer bit count SC4RBSY Data set to TXBUF4 Interrupt SCATIRQ Figure 15 3 11 Reception Timing at rising edge start condition is disabled Operation XV 23 15 Serial interface 4 XV 24 T T Clock
477. n TM1MD 0x03F55 bp4 TM1CAS 1 5 Select the count clock source TMOMD 0x03F54 bp2 0 TMOCK2 0 001 6 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 X0 bp0 TMOBAS 1 7 Set the interrupt generation cycle TMnOC 0x03F53 0x03F52 0x09C3 8 Set the level of the upper timer interrupt TM1ICR OxOSFE9 bp7 6 TM1LV1 0 10 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 the TM1EN flag of the timer 1 mode register to 0 to stop the timer 0 and the timer 1 counting 2 Set the TMOIE flag of the timer O interrupt control register TMOICR and the TM1IE flag of the timer 1 interrupt control register TM1ICR to 0 and to disable the interrupt 3 Set the TMOPWM flag and the TMOMOD flag of the TMOMD register to 0 to select the normal timer 0 operation 4 Set the TM1CAS flag of the TM1MD register to 1 to connect the timer 1 and the timer 0 to the cascade b Select the prescaler to the clock source by the 2 to 0 flag of the TMOMD register 6 Select fs 2 to the prescaler output by the TMOPSC1 to 0 flag and the TMOBAS flag of the timer O prescaler selection register CKOMD 7 Set the timer 1 compare register timer 0 compare register TM1OC TMOOO to the interrupt generation cycle 0x09C3 2500 cycles 1 At that time timer 1 binary counter timer 0 binary counter TM1BC TMOBO are initialized to 0 000 8 Set the interrupt level by the T
478. n TXDO RXDO pin connect SCOMD1 SCOIOM Function Port Serial data input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Input mode x PODIR PODIR1 PSDIR P9DIR1 Pull up setup XI 52 Operation B Pin Setup with 2 channels at transmission reception Chapter 11 Serial interface 0 Table 11 3 23 shows the pin setup at UART serial interface transmission reception with 2 channels TXDO pin pin Table 11 3 23 UART Serial Interface Pin Setup with 2 channels at transmission reception Setup item Data output pin Data input pin pin TXDOB pin RXDOA pin RXDOB pin Port pin P90 P01 P91 Port pin selection Select the used pin A B SCSEL SCOSEL Serial data input selection TXDO RXDO pin independent POPLU POPLUO P9PLU P9PLUO SCOMD1 SCOIOM Function Serial data output Serial data input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Push pull Nch open drain POODC POODOCO Output mode Input mode PODIR PODIRO P9DIR P9DIR0 PODIR PODIR1 PSDIR P9DIR1 Pull up setup Added not added Operation XI 58 11 Serial interface 0 11 3 4 Setup Example S ss rO lt OIsOUIIIO d B Transmission Reception Setup The setup example at UART transmission reception with serial 0 is shown Table 11 3 24 shows the condition at transmission reception Table
479. n be set by the SCOMD3 register Also the SCOCKM flag of the SCOMDI register can divide the internal clock by 8 Table 11 3 3 Synchronous Serial Interface Clock Source serial 0 Clock source fosc 2 internal clock fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 2 output Timer 4 output When the clock setup is switched the SCOSBIS flag and SCOSBOS flag of the SCOMD1 reg Y ister should be set to 0 When the slave reception is done with enabled start condition set the speed of the transfer Y clock slower than the system clock B Switching Unused Pins Used pin is switched A SBOOA SBIOA 5 or B SBOOB SBIOB SBTOB at the SCOSL flag of yjr SCSEL register Operation 11 Serial interface 0 Data Input Pin Setup 3 channels type clock pin SBTO pin data output pin SBOO pin data input pin SBIO pin or 2 channels type clock pin SBTO pin data I O pin SBOO pin can be selected as a communication mode SBIO pin can be used for only serial data input SBOO pin can select serial data input or output The SCOIOM flag of the SCOMDI reg ister can select if the serial data is input to SBIO pin or SBOO pin When data input from SBOO pin is selected to set the 2 lines type the PODIRO flag of the PODIR register controls direction of SBOO pin to switch transmis sion reception At this time SBIO pin can be used as a general port too T
480. n be selected with the SC2STE flag of SC2MDO register Start condition is detected when the SC2CEI flag of the SC2MDO register is set to 0 and data line 5812 pin 3 channels 5802 pin 2 channels changes from to L while the clock line SBT2 pin is It is also detected when the SC2CE1 flag of the SC2MDO register is set to 1 and data line 5812 pin 3 channels SBO2 pin 2 channels changes from to L while the clock line SBT2 pin is L Atthe selection of the start condition enable and master transmission reception after the start condition output start condition is input from the slave then data transmission is generated First Transfer Bit Setup The SC2DIR flag of the SC2MDO register sets the first bit to be transferred LSB MSB can be selected Transmission Reception Data Buffer The transfer data buffer TXBUF2 is the spare buffer which stores data to be loaded to internal shift register Set the data to be transferred to transfer data buffer TXBUF2 and the data is automatically loaded to internal shift register The data loading takes more than 3 5 clock cycles Data setting to TXBUF2 again during data loading may not be operated properly You can determine whether or not data loanding is in progress by monitoring trans fer buffer empty flag SC2TEMP of the SC2STR SC2TEMP flag is set to 1 when data is set to TXBUF2 and cleared to 0 when data loading ends Set data to TXBUF2 I
481. n complete interrupt SCITIRQ the flag is cleared 0 And during continuous communication the SCITBSY flag is always set If the transmission buffer empty flag SCITEMP is cleared to 0 as the communication complete interrupt SC1TIRQ is generated SCI TBS Y is cleared to 0 If the SCISBOS flag is set to 0 during communication the SCITBSy flag is cleared to 0 B Emergency Reset This serial interface contains emergency reset for abnormal operation For emergency reset the SCISBOS flag and the SCISBIOS flag of the SCIMDI register should be set to 0 SBOI pin port input data 1 input At emergency reset the status register the SCIBRKF flag of the SCIMD2 register all flags of the SCISTR reg ister are initialized as they are set at reset but the control register holds the set value B Last Bit of Transfer Data Table 12 3 4 shows the data output holding period of the last bit at transmission and the minimum data input period of the last bit at reception The internal clock should be set up at slave to keep the data hold time at recep tion Table 12 3 4 Last Bit Data Length of Transfer Data The last bit data holding period at transmission The last data input period at reception At master 1 bit data length 1 bit data length Minimum At slave 1 bit data length of external clock x 1 2 internal clock cycle x 1 2 3 2 In the case of disabled start condition at SCISTE flag 0 the SBOI output
482. n of several bytes data to the all the devices on IIC bus using IIC serial Interface 2 Table 13 3 17 shows the conditions Table 13 3 17 Conditions Single Master Communication Setup Item Set to SBI2 SBO2 pins Connection 2 channels Transfer bit count 8 bits Start condition Enable disable after second communication First transfer bit MSB ACK bit Enable communication mode NORMAL mode Clock source fosc 32 SCL2 SDA2 pin type N ch open drain SCL2 pull up resistance added SDA2 pull up resistance added An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation SC2MDS 0 03 98 bp3 SC2PSCE 1 2 Select the clock source SC2MD3 0x03F 98 bp2 0 SC2PSC2 0 011 3 Control of pin type POODC 0x03F1C bp2 POODC5 1 POODC3 1 4 Control of pin direction PODIR 0 0 bp2 POODC5 1 bp0 POODC3 1 1 Set the SC2PSCE flag of the SC2MD3 register to 1 to select prescaler operation 2 SC2PSC2 0 flags of the SC2MD3 register to 011 to select fs 32 at clock source 3 Set the POODCS 3 flag of the POODC register to 1 1 to select N ch open drain for the SDA2 SCL2 pin type 4 Set the PODIRS 3 flag of PO pin control direction register PODIR to 1 1 to set to output mode 46 Operation
483. n reception After communication ends the serial 2 interrupt SC2IRQ is generated Note Procedures 1 to 2 5 6 and 7 can be set at once Note Procedures 8 and 9 can be set at once Operation XIII 31 13 Serial Interface 2 XIII 32 For communication with 3 channels set the SC2BIS of the SC2MD1 register to 0 to set the serial input to 1 The SBI2 pin can be used as a general port For reception only set the SC2SBOS of the SC2MD1 register to 0 to select port The SBO2 pin can be used as a gen eral port For communication with 2 channels set the SBO2 pin to serial data I O The port direction control register PODIR switches the I O For reception set the SC2SBIS of the SC2MD1 reg ister to 1 to select serial input The SBO2 pin can be used as a general port You can shut down the communication by setting the SC2SBOS and the SC2SBIS of the SC2MD1 register to 0 Set each flag in order of the setup procedures Set all the control registers refer to Table 13 2 1 except TXBUF2 before start communication Set the transfer rate of the transfer clock to under 5 0 MHz with the SC2MD3 register Operation 13 Serial Interface 2 B Transmission Reception Setup Example reception in STANDBY mode Here is the setup example at transmission reception in STANDBY mode using serial interface 2 Table 13 3 12 show
484. nable with the SC2PSCE of the SC2MD3 register The SC2MST flag of the SC2MDI register selects the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock with same frequency to the external clock with the SC2MD3 register as the interrupt flag SC2IRQ is generated by the internal clock Table 13 3 3 shows the internal clock source which can be set with the SC2MD3 register Table 13 3 3 Synchronous Serial Interface Inside Clock Source Serial 2 Clock source fosc 2 Internal clock fosc 4 fosc 8 fosc 16 fosc 32 fosc 64 fosc 128 fs 2 fs 4 timer 2 output timer 3 output a Set 0 to the SC2SBIS and SC2SBOS flags of the SC2MD register before change the clock setup Set transfer clock frequency in slave reception in which start condition is to be smaller than Y that of the system clock Data Input Pin Setup There are 2 communication modes to be selected 3 channels clock pin SBT2 pin data output pin 5 2 pin data input pin SBI2 pin 2 channels clock pin SBT2 pin data I O pin SBO2 pin The SBI2 pin can be used only for serial data input The SBO2 pin can be used for serial data input and output The SC2IOM flag of the SC2MDI register selects either serial data is input from the 5812 pin or the 5802 pin When data input from the SBO2 pin is selected for communicati
485. nal reset release internal reset release san WDEN gt 5 26 MUX DLYCTR fs 22 t 0 gt fs 222 15 220 5 218 MUX WDIRQ fs 2 5 WDCTR WDEN 0 WDTSO worst Reserved Re d Figure 9 1 1 Block Diagram Watchdog Timer The watchdog timer is also used as a timer to count the oscillation stabilization wait time this is used as a watch dog timer except at recovering from STOP mode and at reset releasing The watchdog timer is initialized at reset or at STOP mode and counts system clock fs as a clock source from the initial value 0x0000 The oscillation stabilization wait time is set by the oscillation stabilization control reg ister DLYCTR Chapter2 2 8 Reset Overview Chapter 9 Watchdog Timer 9 2 Control Register The watchdog timer is formed by the control register WDCTR Watchdog Timer Control Register Table 9 2 1 Watchdog timer control register WDCTR 0x03F02 Reserved Reserved Reserved 0 0 0 Description Reserved Set always Watchdog time out period setup 00 218 of system clock 01 218 of system clock 10 22 of system clock 11 27 of system clock Watchdog timer enable 0 Watchdog timer is stopped 1 Watchdog timer is operated Control Register IX 3 9 Watchdog Timer IX 4 9 3 Operation 9 3 1 Operation The watchdog timer counts system clock fs as a clock s
486. nction Page 0x03F14 Port 4 Output Register IV 42 0x03F24 Port 4 Input Register 0x03F34 Port 4 Direction Control Register 0x03F44 Port 4 Pull up Pull down Resistor Control Register 0x03F3C Port 4 Nch Open drain Control Register 0x03F4B Pull up Pull down Resistor Selection Register R W Readable Writable Port 4 Output Register PAOUT 0xOSF14 Output data 0 Output L VSS level 1 Output H VDD level P4OUT3 P4OUT2 P4OUT1 P4OUT0 O gt O Q O IV 42 Port 4 Port 4 Input Register PAIN 0xO3F24 Chapter 4 I O Ports bp gt O Q O Input data 0 Pin is L VSS level 1 Pin is H VDD level Flag PADIR3 P4DIR2 P4DIR1 PADIRO At reset 0 0 0 0 Access RAN R W R W R W bp O Q O Flag P4DIR3 P4DIR2 P4DIR1 P4DIR0 Description mode selection 0 Input mode 1 Output mode Port 4 IV 43 4 I O Ports IV 44 Port 4 Pull up Pull down Resistor Control Register P4PLU 0x03F44 P4PLU3 P4PLU2 P4PLU1 P4PLUO 0 0 0 0 bp gt O Q O Flag P4PLU3 P4PLU2 P4PLU1 P4PLU0 Description Pull up pull down resistor selection 0 Not added 1 Added Port 4 Nch Open drain Control Register P4ODC 0x03F3C
487. nctions Chapter 9 Watchdog Timer Chapter 10 Buzzer Chapter 11 Serial Interface 0 Chapter 12 Serial Interface 1 21 ES ESI ERN ENS Chapter 13 Serial Interface 2 Chapter 14 Serial Interface 3 Chapter 15 Serial Interface 4 Chapter 16 A D Converter Chapter 17 D A Converter Chapter 18 Automatic Transfer Controller Chapter 19 Appendix EN Kool e gt 69 Contents Contents Chapter Wr na u a sam E E I 1 II M 1 2 TIT Overview ete RS HE REO NURSES 1 2 1 1 2 Product Summaty ie ttti ete Une e ect e b eb 1 3 1 2 Hardware FUNCIONS u u l l 1 4 1 3 Pin Description iue 1 10 1 3 1 Pim configuration ire etre ee RH P PRSE Re POP HE I 10 1 3 2 Pim Specification xc UR Ere ebbe ine eh I 11 13 3 Pm sa g o o uU sat a te ees I 13 14 Block Diagram onion eoe TR etie Hee elites ie Fee ee ote tee piemonte I 19 Block Diagram s ie a SS ea MIR tei ere I 19 1 5 Hlectrical Ch racteristics eene tete ree rre Pee pe trente snes p et eet 1 20 151 Absolute Maximum iei ettet ree ei teet etel enin I 21 15 2 Operating Conditions 1 22 15 3 DC
488. nd the TM2MOD flag of the TM2MD register to 0 to select the normal timer operation 3 Select the prescaler output to the clock source by the 2 2 to 0 flag of the TM2MD register 4 Select fs 2 to the prescaler output by the TM2PSC1 to 0 flag and the TM2BAS flag of the timer 2 prescaler selection register b Set the timer 2 compare register TM2OC such a value that the baud rate comes to 300 bps At that time the timer 2 binary counter TM2BC is initialized to 0x00 6 Set the TM2EN flag of the TM2MD register to 1 to operate the timer 2 TM2BC counts up from 0x00 Timer 2 output is the clock of the serial interface 4 at transmission and recep tion Refer to Chapter 15 about the value of compare register setting and serial operation setting Serial Transfer Clock Output 5 8 bit Timers 5 10 Simple Pulse Width Measurement 5 10 1 Operation Timer measures the L duration of the pulse signal input from the external interrupt pin Simple Pulse Width Measurement Operation by 8 bit Timer Timers 0 2 and 4 When the input signal of the external interrupt pin simple pulse width is L the binary counter of the timer counts up Pulse width L period can be measured by reading the count of timer 8 bit timers that have the sim ple pulse width measurement function are the Timers 0 2 and 4 Table 5 10 1 Simple Pulse Width Measurement Able Pins Timer 0 Timer 2
489. nels SBO1 5 pin SBTI pin at reception Table 12 3 8 Setup for Synchronous Serial Interface Pin with 3 channels at reception Setup item Data output pin Data input pin Clock I O pin 5801 pin SBI1 pin SBT1 pin Clock master Clock slave SC1MD1 SC1MST Port pin P30 P31 P32 Serial data input SBI1 selection SC1MD1 SC1IOM Function Port Serial input Transfer clock input Transfer clock input output output P3DIR P3DIRO SC1MD1 SC1SBIS SC1MD1 SC1SBTS Style Push pull Nch open Push pull Nch open drain drain P3ODC P3ODC2 Input mode Output mode Input mode P3DIR P3DIR1 P3DIR P3DIR2 Pull up setup Added Not added Added Not added P3PLU P3PLU2 Operation B Pins Setup with channels at transmission reception Chapter 12 Serial interface 1 Table 12 3 9 shows the setup for synchronous serial interface pin with 3 channels SBO1 pin 5 pin SBTI pin at transmission reception Table 12 3 9 Setup for Synchronous Serial Interface Pin with 3 channels at transmission reception Setup item Data output pin Data input pin Clock I O pin 5801 pin SBI1 pin SBT1 pin Clock master Clock slave SC1MD1 SC1MST Port pin P30 P31 P32 Serial data input SBI1 selection SC1MD1 SC1IOM Function Serial data output Serial input Transfer clock input Transfer clock inp
490. nels TXD4 pin RXD4pin Table 15 3 21 UART Serial Interface Pin Setup with 2 channels at reception Setup item Data output pin Data input pin TXD4 pin RXD4 pin Port pin 40 41 data input selection RXD4 SC4MD1 SC4IOM Function Port Serial data input SC4MD1 SC4SBOS SC4MD1 SC4SBIS Style Input mode P4DIR P4DIR1 Pull up setup Operation B Pin Setup with 1 channel at reception Chapter 15 Serial interface 4 Table 15 3 22 shows the pin setup at UART serial interface reception with 1 channel TXD4 pin The RXD4 pin in not used so can be used as a port Table 15 3 22 UART Serial Interface Pin Setup with 1 channel at reception Setup item Data output pin Data input pin TXD4 pin RXD4 pin Port pin P40 P41 Serial data input selection TXD4 SC4MD1 SC4IOM Function Port Serial data input SC4MD1 SC4SBOS SC4MD1 SC4SBIS Style Input mode P4DIR P4DIR1 Pull up setup 3 B Pin Setup with 2 channels at transmission reception Table 15 3 23 shows the pin setup at UART serial interface transmission reception with 2 channels TXD4 pin RXD4 pin Table 15 3 23 UART Serial Interface Pin Setup with 2 channels at transmission reception Setup item Data output pin Data input pin TXD4 pin RXD4 pin Port pin P40 P41 Serial d
491. nerated Control Registers 41 Chapter 3 Interrupts Serial 4 UART Reception Interrupt Control Register SCARICR The serial 4 UART reception interrupt control register SCARICR controls interrupt level of serial 4 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 25 Serial 4 UART Reception Interrupt Control Register SC4RICR 0x03FF8 bp 7 6 5 4 3 2 1 0 Flag SCARLV1 SC4RLVO SC4RIE SC4RIR At reset 0 0 i 0 0 Access R W Description SC4RLV1 Interrupt level flag SC4RLV0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests SC4RIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SC4RIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated III 42 Control Registers 3 Interrupts Serial 4 UART Transmission Interrupt Control Register SC4TICR The serial 4 UART transmission interrupt control register SC4TICR controls interrupt level of serial 4 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 26 Serial 4 UART Transmission Interrupt Control Register SC4TICR 0x03FF9
492. nerates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P70 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp7 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp7 of the address output control register EXADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P71 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp7 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp7 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P72 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp7 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp7 of the address output control register EXADV is 1 at the memory extension mode or at the processor mode it is output
493. nk 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 1111 bank 15 Memory Space Il 19 2 CPU Basics B Bank Register for Destination Address The DBNKR register is used to specify bank area for storing instruction from register to memory Once this regis ter is specified bank control is valid for all addressing modes except I O short instruction stack relative indirect instruction and bit manipulation instruction Chapter 2 2 1 9 Addressing modes Table 2 2 5 Bank Register for Destination Address DBNKR 0x03F0B bp 7 4 3 2 1 0 Flag DBA2 DBA1 DBA0 At reset 0 0 0 0 Bank for source address selection bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank A bank B bank C bank D bank E 1111 bank F Read modify write instruction such as bit manipulation BSET BCLR BTST depend on the value of the SBNKR register both of for reading and writing 11 20 Memory Space Chapter 2 CPU Basics 2 2 3 RAM Space TOIs vaisi RAM Space MNIOIE series has maximum 64 KB of RAM space RAM space is devided to be allocated to the address space Mirror RAM space is provided for effective utilization of the devided RAM spaces RAM space 0x00000 to 0x03DFF 15 5 KB to OxFFFFF 48 5 KB maximum 64KB Mirror RAM space
494. not used so that it can be used as a general port Table 13 3 9 Synchronous Serial Interface Pins Setup 2 channels at transmission Item Data output pin Data input pin Clock I O pin 5802 pin 5812 pin SBT2 pin Clock master Clock slave Pin 4 5 Serial data input SB02 selection SC2MD1 SC2IOM Function Serial data output 1 input Transfer clock Transfer clock SC2MD1 SC2SBOS SC2MD1 SC2SBIS SC2MD1 SC2SBIS Type Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain POODC POODC3 POODC POODC5 Output mode Output mode Input mode PODIR PODIR3 PODIR PODIR5 Pull up added not added added not added added not added POPLU POPLU3 POPLU POPLUS Operation B Pins Setup 2 channels at reception Chapter 13 Serial Interface 2 Table 13 3 10 shows the pins setup at synchronous serial interface reception with 2 channels SBO2 pin SBT2 pin The SBI2 pin is not used so that it can be used as a general port Table 13 3 10 Synchronous Serial Interface Pins Setup 2 channels at reception Item Data output pin Data input pin Clock pin SBO2 pin SBI2 pin SBT2 pin Clock master Clock slave Pin 4 P05 Serial data input SB02 selection SC2MD1 SC2IOM Function Port Serial input Transfer clock I O Transfer clock I O
495. nputs the serial data If data input from TXDO is selected to be with 1 line com munication transmission reception is switched by controlling TXDO pin s direction by the PODIRO flag of the PODIR register At the same time the RXDO pin can be used as a general port Reception Buffer Empty Flag When SCORIRQ is generated data is stored to RXBUFO from the internal shift register automatically If data is stored to RXBUFO from the shift register the reception buffer empty flag SCOREMP of the SCOSTR register is set to 1 That indicates that the received data is going to be read out SCOREMP is cleared to 0 by reading out the data of RXBUFO Reception BUSY Flag When the start condition is regarded the SCORBSY flag of the SCOSTR register is set to 1 That is cleared to 0 by the generation of the reception complete interrupt SCOTIRQ If the SCOSBIS flag is set to 0 during reception the SCORBSY flag is reset to 0 B Transmission BUSY Flag When any data is set to TXBUFO the SCOTBSY flag of the SCOSTR register is set to 1 That is cleared to 0 by the generation of the transmission complete interrupt SCOTIRQ During continuous communication the SCOTBSY flag is always set If the transmission buffer empty flag SCOTEMP is set to O as the transmission complete interrupt SCOTIRQ is generated the SCOTBSY is cleared to 0 If the SCOSBOS flag is set to O the SCOTBSY flag is reset to O Operation
496. nsion output contorl Figure 4 8 5 P64 Block Diagram P pepLus Pull up resistor Ro Le contorol R 8 DIR E VO direction p PEBIRS de control WEK R lt x ane P6OUT P Port output data WEK R PX 4 CFT Schmitt trigger input P6INS Port input data lt Key interrupt input Address output External extension output contorl Figure 4 8 6 P65 Diagram Port 6 IV 63 4 I O Ports M Reset Pull up resistor 7 gt contorol WEK R Reset I O direction pR d PSDIR6 2 M 3d control o WEK R lt x 2 Port output data S P6OUT6 2 M Wek VR 1 Port input data 777 Schmitt trigger input 1 J R Key interrupt input Address output External extension output contorl Figure 4 8 7 P66 Block Diagram fal P6PLU7 Pull up resistor gt contorol WEK R Poe p DIR7 direction pRd PS 4 m control E R x P 5 P6OUT7 Port output data 2 o WEK R kl X Schmitt trigger input Port input data lt P6IN7 lt
497. nsion memory or the general port pin at the mem ory extension mode by the address output control register EXADV Special Function Pin Setup P60 is used as input pin of KEY interrupt as well P61 is used as input pin of KEY interrupt as well P62 is used as input pin of KEY interrupt as well P63 is used as input pin of KEY interrupt as well P64 is used as input pin of KEY interrupt as well P65 is used as input pin of KEY interrupt as well P66 is used as input pin of KEY interrupt as well P67 is used as input pin of KEY interrupt as well P60 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp5 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp5 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P61 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp5 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp5 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P62 is address output pin to the external extension memory a
498. nt control 0 Halt the count 1 Operate the count TM2CK2 TM2CK1 TM2CKO Select the clock source X00 fosc X01 TM2PSC Prescaler output 010 fx 011 Synchronou fx 110 TM2IO input 111 Synchronous TM2IO output Control Registers V 19 5 8 bit Timers Timer 3 Mode Register TM3MD 0x03F5D 4 2 1 0 5 2 1 TM3CKO 0 0 0 0 Description 7 5 4 TM3CAS Select timer 3 operation mode 0 Normal timer operation 1 Cascade connection 3 TM3EN Timer 3 count control 0 Halt the count 1 Operate the count 2 0 TM3CK2 Select clock source TM3CK1 X00 fosc TM3CK0 X01 TM3PSC Prescaler output 010 fx 011 Synchronous fx 110 input 111 Synchronous TMSIO input 20 Control Registers Timer 4 Mode Register TM4MD 0x03F64 bp 6 5 4 2 1 Chapter 5 8 bit Timers 0 Flag TM4POP TM4MOD TM4PWM TM4CK2 TM4CK1 TM4CKO At reset 0 0 0 0 0 0 Access Description TM4POP On PWM mode select start compulsion of output signal O timer output HL 1 timer output TM4MOD Pulse width measurement control 0 Normal timer operation 1 P24 pulse width measurement TM4PWM Select timer 4 operation mode 0 Normal timer operation 1 PWM operation TM4EN Timer 4 count control 0 Halt the count 1 Operate the count
499. nter TM7BC is initialized to 0 0000 7 Set the TM7BCR flag of the Timer 7 mode register 2 TM7MD2 to 1 to select the compare match as a binary counter clear source 8 Select TM7IO to the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Besides select 1 1 no dividing to the count clock source by the TM7PS1 to 0 flag 9 Set the interrupt level by the TM7LV1 to 0 flag of the Timer 7 interrupt control register TM7ICR If the interrupt request flag is already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 16 bit Event Count 6 16 bit Timer Setup Procedure Description 10 Enable the interrupt TM7ICR 0x03FF0 bp1 TM7IE 1 11 Start the event count TM7MD1 0x03F78 bp4 TM7EN 1 10 Set the TM7IE flag of the TM7ICR register to 1 to enable the interrupt 11 Set the 7 flag of the TM7MD1 register to 1 to operate the Timer 7 Every time TM7BC reaches the falling edge of the TM7IO input it counts up from 0x0000 When the TM7BC reaches the set value of the register the Timer 7 interrupt request flag is set at the next count clock and the value of TM7BC becomes 0x0000 to restart counting up a In case the procedure of the step 5 to 8 the timer may be operated imperfectly 16 bit Event Count VI 21 6 16 bit Timer VI 22 6 5 16 bit Timer Pulse Output 6 5 1 O
500. nter 0 increments again Set an even address in the lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH ATIMAPIM Always set an even I O address in memory pointer 1 In this double transfer of a data byte from and to the I O space ATC1 targets the even I O address set in memory pointer 1 and the consecutive odd address In this mode the first data byte transfer accesses an even I O address and the second data byte transfer accesses an odd I O address Operation XVIII 25 18 Automatic Transfer Controller Transfer mode 8 can be used to support continuous transmission reception for serial inter face 0 1 and 2 Set the memory pointer 1 to point to the serial reception buffer RXBUF0 RXBUF1 and select serial interrupts as the ATC1 trigger factor In this way everytime the serial communication ends the MCU continuously reads the reception data first data byte transfer then writes the transmission data to the transmission buffer TXBUF0 TXBUF1 second data byte transfer up to 255 times entirely through the hardware Before execute a continuous serial transaction store the serial transmission data in the memory space that memory pointer 0 points the transmission data must fill every other address in the space Once the serial transaction ends the received data is stored in empty skipped addresses and the transmis
501. nterrupt restarts the oscillators and after allowing time for them to stabilize returns the CPU to the previous CPU operating mode that is to NORMAL from STOPO or to SLOW from 5 SLOW Mode This mode executes the software using the low frequency clock Since the high frequency oscillator is turned off the device consumes less power while executing the software B IDLE Mode This mode allows time for the high frequency oscillator to stabilize when the software is changing from SLOW to NORMAL mode To reduce power dissipation in STOP and HALT modes it is necessary to check the stability of both the output current from pins and port level of input pins For output pins the output level should match the external level or direction control should be changed to input mode For input pins the external level should be fixed This LSI has two system clock oscillation circuits OSC is for high frequency operation NORMAL mode and XI is for low frequency operation SLOW mode Transition between NORMAL and SLOW modes or to standby mode is controlled by the CPU mode control register CPUM Reset and interrupts are the return factors from standby mode A wait period is inserted for oscillation stabilization at reset and when returning from STOP mode but not when returning from HALT mode High low frequency oscillation mode is automatically returned to the same state as existed before entering standby mode To stabilize the synchroniza
502. ntrol Register TMSEL 0x03F3F TM7SEL TM5SEL TM4SEL 0 0 0 R W Description TM7SEL Timer 7 I O pin switching 0 P16 TM7IOA 1 PD4 TM7IOB TM5SEL Timer 5 I O pin switching 0 P15 TM5IOA 1 5 TM4SEL Timer 4 I O pin switching 0 P14 TM4IOA 1 PD2 TM4IOB Control Registers 6 16 bit Timer B External Interrupt Pin Switching Control Register IRQSEL 0x03F4E IRQ3SEL IRQ2SEL 0 0 Description 7 4 3 IRQ3SEL External interrupt 3 input pin switching 0 P23 1 PD1 2 IRQ2SEL External interrupt 2 input pin switching 0 P22 1 PD0 1 0 Control Registers VI 11 6 16 bit Timer VI 12 6 3 Operation 6 3 1 Operation The timer operation can constantly generate interrupts 16 bit Timer Operation Timer 7 The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register 1 TM7OC1 in advance When the binary counter TM7BC reaches the set value of the compare regis ter 1 the timer 7 interrupt request is generated at the next count clock There are 2 sources the TM7OCI com pare match or the full count over flow to be selected to clear the binary counter After the binary counter is cleared to 0x0000 the counting up is restarted from 0x0000 Table 6 3 1 16 bit Timer Interrupt Source
503. ntrol Registers B Serial interface Clock Cycle Switching Register SCCKSEL bp 7 6 5 4 Chapter 13 Serial Interface 2 Flag SCCKSEL SCCKSEL 6 SCCKSEL SCCKSEL 5 4 At reset 0 0 0 Access SCCKSEL7 SCCKSEL6 Description Serial 3 clock fosc cycle switching 00 fosc 01 fosc 2 10 fosc 4 11 Reserved SCCKSEL5 SCCKSEL4 Serial 2 clock fosc cycle switching 00 fosc 01 fosc 2 10 fosc 4 11 Reserved Table 13 2 2 SCCKSEL bp5 SCCKSEL bp5 Serial 2 clock fosc selection SC3PSC2 SC3PSC1 SC3PSCO 0 fosc 2 fosc 4 fosc 16 fosc 32 fosc 4 fosc 8 fosc 32 fosc 64 fosc 8 fosc 16 fosc 64 fosc 128 Control Registers XIII 13 Chapter 13 Serial Interface 2 XIII 14 13 3 Operation Serial interface 2 is used as both clock synchronous single master IIC serial interface 13 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 13 3 1 shows the activation source for communication At master a transfer clock is generated by setting data to the transfer data buffer TXBUF2 or by enabling start condition Signals input from SBT2 pin inside serial interface are masked to prevent operating errors by noise except during communication This mask is automati cally released by setting data to TXBUF2
504. ntrol register controls memory to be expanded 256 B RAM short addressing area 0x00100 12B 0x03E00 Special function register areal y Instruction code Table data Instruction code A 16 64 48 KB 1MB Y 1 Y 896 KB Y 64 KB Y Y OxF0000 OxFFFFF Overview Figure 2 1 7 Address Space RAM space Spscial register area Y ROM space RAM space Chapter 2 CPU Basics 2 1 9 Addressing Modes SS ooo This LSI supports the nine addressing modes Each instruction uses a combination of the following addressing 1 Register direct 2 Immediate 3 Register indirect 4 Register relative indirect 5 Stack relative indirect 6 Absolute 7 RAM short 8 I O short 9 Handy These addressing modes are well suited for C language compilers All of the addressing modes can be used for data transfer instructions In modes that allow half byte addressing the relative value can be specified in half byte 4 bit increments so that instruction length can be shorter Handy addressing reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combining handy addresssing with abso lute addressing reduces code size For transfer data between memory 8 addressing modes register indirect reg ister relative indirect stack relative indirect absolute RAM short I O short handy can be used For operation instru
505. ock Figure 12 3 14 Transmission Reception Timing Reception at rising edge Transmission at falling edge SBT1pin Data is received at the rising edge of clock SBI1pin Data is output at the falling edge of clock SBO1pin Figure 12 3 15 Transmission Reception Timing Reception at falling edge Transmission at rising edge Operation 25 12 Serial interface 1 Communication Function at Standby Mode This serial interface has the following way about the return from the standby mode This serial interface can do the slave reception at the standby mode CPU operation status be recovered from standby to normal by the communication complete interrupt SCITIRQ that is generated after the slave reception At the standby mode if the transfer bit count data is received once that is set by the SCILNG2 to 0 flag of the SCIMDO register the continuous reception is not available because the next data is not allowed The received data should be read out from the received data buffer RXBUFI after recovering the normal mode In the reception at the standby mode the communication with enabled start condition is not available Disable the start condition The dummy data should be set to the transmission data buffer TXBUFI before the transition to the standby mode XII 26 Normal mode Standby mode Normal mode gt lt gt lt gt lt Oscillation Stabilization Clock SB
506. ock master Set the SC2SBIS and SC2SBOS flags of the SC2MD1 register to 0 before change the Y clock setup B Transmission Reception Mode Setup and Operation The SC2REX flag of the SC2CTR register selects the status of the transmission or the reception The first data is always added start condition for communication The start condition is output from this serial master The start condition is not added over the second communication select the start condition none at the first set ting And the start condition is added over the second communication select the start condition enable at the first setting At addressing format slave address and R W bit are set to the first data after start condition for transmission At master reception switch to the reception mode at the interrupt transaction after the transmission of the first 1 byte data is finished after the ACK signal from slave is confirmed If the communication should be continued to other device without stop transmit slave address and R W bit again after start condition is generated again At recep tion the SDA line is automatically released to wait for reception After the storage of data is finished confirma tion of the reception ACK bit is output Figure 13 3 21 Master Transmission Timing Figure 13 3 22 Master Reception Timing B IIC BUSY Flag Operation As data is set to the transmission reception shift register TXBUF2 the IICBSY flag of the SC2CTR regi
507. ode the automatic data transfer control func Y tion ATC1 cannnot be used for access to external memory memory expansion mode and processor mode set the NCS P74 NRE P75 NWE P76 1 To use the automatic data transfer control function ATC1 for access to internal memory in pins to 1 and pull up XVIIl 2 Automatic Transfer Controller 18 1 2 Functions 2 Table 18 1 1 provides a list of the trigger factors and transfer modes ATC1 Trigger Factors Table 18 1 1 ATC1 Trigger Factors Chapter 18 Automatic Transfer Controller Trigger Factors External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 Timer 0 interrupt Timer 1 interrupt Timer 7 interrupt Timer 7 capture trigger Serial interface 0 UART transmission interrupt Serial interface 0 UART reception interrupt Serial interface 1 UART transmission interrupt Serial interface 2 interrupt Serial interface 3 interrupt Serial interface 4 UART transmission interrupt A D converter interrupt Software activation Automatic Transfer Controller XVIII 3 18 Automatic Transfer Controller B Transfer Modes Table 18 1 2 Transfer Modes
508. of 0 to 3 to interrupt requests T7OC2IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt T7OC2IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Ill 35 Chapter 3 Interrupts Serial 0 UART Reception Interrupt Control Register SCORICR The serial 0 UART reception interrupt control register SCORICR controls interrupt level of serial 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 19 Serial 0 UART Reception Interrupt Control Register SCORICR 0x03FF2 bp 7 6 5 4 3 2 1 0 Flag SCORLV1 SCORLVO SCORIE SCORIR At reset 0 0 i 0 0 Access R W Description SCORLV1 Interrupt level flag SCORLVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests SCORIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SCORIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Ill 36 Control Registers 3 Interrupts Serial 0 UART Transmission Interrupt Control Register SCOTICR The serial O UART transmission interrupt control register SCOTICR controls interrupt level of serial 0 interrupt interrupt enable flag and interrupt reque
509. of this microcontroller and AO 39 Output P50 Address pins used as reference signal to external control systems as well o 40 Output P51 0 19 is the address signal to the external memory 00 07 is A2 41 Output P52 the data I O signal to the external memory 42 Output P53 A4 43 Output P54 A5 44 Output P55 A6 45 Output P56 A7 46 Output P57 A8 47 Output P60 A9 48 Output P61 KEY1 A10 49 Output P62 KEY2 A11 50 Output P63 KEY3 A12 51 Output P64 KEY4 A13 52 Output P65 KEY5 A14 53 Output P66 KEY6 A15 54 Output P67 KEY7 A16 55 Output P70 SDO0 A17 56 Output P71 001 A18 57 Output P72 SDO2 A19 58 Output P73 SDO3 DO 64 VO P80 LEDO Data pins D1 65 81 LED1 2 66 P82 LED2 D3 67 y o P83 LED3 D4 68 Vo P84 LED4 D5 69 VO P85 LED5 D6 70 VO P86 LED6 D7 71 VO P87 LED7 1 18 Pin Description Chapter 1 Overview 1 4 Block Diagram 1 4 1 Block Diagram a 2 9 9 ag PES x O gt 22 s i NN PH PD7 SBIOARXDOAPO 24 ow cin High speed CPU PD6 SYSCLK v Oscillator Oscillator MN101E PD5 BUZZER Circuit circuit PD4 TM7IOB P04 PD3 TM5IOB SBT2 SCL2 P05 ROM RAM PDTS DAO PO6 320 KB 14 KB PD0 IRQ2B PA7 AN7 RMOUT TMOIO P1 I SERI pru e w 8 bit Timer 0 Serial Interface 0 PA6 AN6 TM2IO P12
510. on can be used by setting the proper bank area to the bank register for source address SBNKR or the bank register for destination address DBNKR At reset both of the SBNKR register and the DBNKR register indicate bank 0 Bank function is valid after setting any value except 00 to the SBNKR register or the DBNKR register When the both registers of SBNKR and DBNKR are operated at interrupt processing pushing onto the stack or popping are necessary Table 2 2 3 Address Range 5 SBA2 SBA1 SBAO Bank area Address range DBA2 DBA1 DBAO 0 0 0 0 bank 0 0x00000 to OxOFFFF 0 0 0 1 bank 1 0x10000 to Ox1FFFF 0 0 1 0 bank 2 0x20000 to Ox2FFFF 0 0 1 1 bank 3 0x30000 to 0x8FFFF 0 1 0 0 bank 4 0x40000 to Ox4FFFF 0 1 0 1 bank 5 0x50000 to 0x5FFFF 0 1 1 0 bank 6 0x60000 to Ox6FFFF 0 1 1 1 bank 7 0x70000 to Ox7FFFF 1 0 0 0 bank 8 0x80000 to Ox8FFFF 1 0 0 1 bank 9 0x90000 to Ox9FFFF 1 0 1 0 bank 10 0xA0000 to OXAFFFF 1 0 1 1 bank 11 0xB0000 to OXBFFFF 1 1 0 0 bank 12 0xC0000 to OxCFFFF 1 1 0 1 bank 13 0 00000 to OXDFFFF 1 1 1 0 bank 14 0 0000 to OXEFFFF 1 1 1 1 bank 15 OxF0000 to OxFFFFF When bank area is changed at interrupt processing pushing onto the stack or popping must be done by program if it necessary Memory Space Il 17 2 CPU Basics 1 During bank function is valid I O short instruction should be used for a
511. on with 2 channels the PODIR3 flag of the PODIR register is used to switch the transmission reception of the SBO2 pin The SBI2 pin not used at that time can be used as a general port XIII 18 Operation 13 Serial Interface 2 Maximum transfer speed should be under 5 0 MHz If transfer clock exceeds 5 0 MHz data Y may not be transferred properly In reception you can use 5812 as general port by setting SC2IOM of the SC2MD1 regis ter to 1 to select serial data input from SBO2 pin B Transmission Buffer Empty Flag If any data is set to TXBUF2 during communication after setting data to TXBUF2 before generating the commu nication complete interrupt SC2IRQ the transmission buffer empty flag SC2TEMP of the SC2STR register is set to 1 That indicates that the next transmission data is going to be loaded Data is loaded to inside shift register from TXBUF2 by generation of SC2TIRQ and the next transfer is started as SC2TEMP is cleared to 0 B BUSY flag If data is set to the transmission reception shift register TXBUF2 or start condition is enabled the busy flag SC2BSY is set That is cleared to 0 by the generation of the communication end interrupt SC2IRQ The SC2BSY flag setup is maintained during continuous communication If transmission buffer empty flag SC2TEMP is 0 when communication end interrupt SC2IRQ is generated SC2BSY is cleared to 0 B Forced Reset You can shut down
512. ontrol direction control Port output data Port input data BUZZER output DLAYCTR BUZOE IV 112 Port D Rege PDPLU4 Q R Reset R PDDIR4 R PDOUT4 0 snq 2120 Reset PDOMD4 Q PDIN4 PD4 Schmitt trigger input 2 2 Figure 4 13 5 PD4 Block Diagram 4 Reset Rd PDPLU5 gt WEK R Reset Rd PDDIR5 WEK R gt i Y Schmitt trigger input 1 PDINS N U R Figure 4 13 6 PD5 Block Diagram Chapter 4 I O Ports gt Em PDPLU6 Pull up resistor contorol Rg gt o Le YR EX PDDIR I O direction gt control K R X in p de PDOUT output data UIS 2 M o WEK R PX 1 Schmitt trigger input 6 Port input data lt I J R System clock output External extension output contorl Figure 4 13 7 PD6 Block Diagram N Reset Pull up resistor control pRq PDPLU7 D gt WEK R Reset direction control PDDIR7 4 M CK R gt P Port output data d A q P
513. ontrol registers refer to Table 15 2 1 except TXBUF4 are set a Each flag should be set as this setup procedure in order Activation of communication should Operation XV 37 15 Serial interface 4 15 3 3 UART Serial Interface REm serial 4 can be used for full duplex UART communication Table 15 3 14 shows UART serial interface functions Table 15 3 14 URAT Serial Interface Functions Communication style UART full duplex Interrupt SCATIRQ transmission SCARIRQ reception Used pins TXDA output input RXD4 input Specification the first transfer bit MSB LSB Selection of parity bit Parity bit control 0 parity 1 parity odd parity even parity Frame selection 7 bits 1 STOP 7 bits 2 STOP 8 bits 1 STOP 8 bits 2 STOP Continuous operation Maximum transfer rate 300 kbps standard 300 bps to 38 4 kbps with baud rate timer XV 38 Operation 15 Serial interface 4 Activation Factor for Communication At transmission if any data is set to the transmission data buffer TXBUF4 a start condition is generated to start transfer At reception if a start condition is received communication is started At reception if the data length of L for start bit is longer than 0 5 bit that can be regarded as a start condition B Transmission Data transfer is automatically starte
514. or Le contorol WEK R P2DIR2 E direction P2 p control WEK R Mn lt P2 S P2OUT2 be Port output data D Q ou Wek R 477 Schmitt trigger input P2IN2 Port input data lt J R Externa interrupt 2 input Figure 4 4 3 P22 Block Diagram Reat o Sj 5 Pull up resistor PREUS gt gt contorol WEK R P2DIR direction p m control WEK R oy t P23 Port output data u q P2OUTS 11 WEK R Schmitt trigger input Port input data lt P2INS lt L N R Externa interrupt 3 input Figure 4 4 4 P23 Block Diagram Port 2 Chapter 4 I O Ports IV 81 4 I O Ports Pull up resistor contorol I O direction control Port output data Port input data Externa interrupt 4 input Pull up resistor contorol I O direction control Port output data Port input data Externa interrupt 5 input IV 32 Port 2 Figure 4 4 6 P25 Block Diagram 1 Bm P2PLU4 gt WEK R H Le 2DIR4 2 WEK R 5 SS pas 2 9 20074 E a Wek R AKA Schmitt trigger input lt 1 2 4 Figure 4 4 5 24 Blo
515. or is generated and the SCOORE flag of the SCOSTR register is set to 1 At the same time the error monitor flag SCOERE is set to indicate that error is occurred on reception The SCOERE flag is not cleared till the next communication complete interrupt SCOTIRQ is generated after loading data of the RXBUFO 5 is cleared as SCOORE flag is cleared These error flags have no effect on communication operation Operation XI 19 11 Serial interface 0 XI 20 Reception BUSY Flag If the data is set to the TXBUFO or recognized the start condition when the SCOSBIS flag of the SCOMDI register is set to serial data input the BUSY flag SCORBSY of the SCOSTR register is set to 1 And on the genera tion of the communication complete interrupt SCOTIRQ the flag is cleared to 0 And during continuous com munication the SCORBSY flag is always set If the transmission buffer empty flag SCOTEMP is cleared to 0 as the communication complete interrupt SCOTIRQ is generated SCORBSY is cleared to 0 If the SCOSBIS flag is set to 0 during communication the SCORBSY flag is cleared to 0 B Transmission BUSY Flag Data is set to the TXBUFO or recognized the start condition when the SCOSBOS flag of the SCOMDI register is set to serial data output if the SCOSBOS flag of the SCOMDI register is 1 SCOTBSY flag of the SCOSTR register is set And on the generation of the communication complete interrupt SCOTIRQ the flag
516. ort 0 7 bit COMS tri state port P01 5 SBIOA RXDOA Each bit can be set individually as either an input or output by the P02 6 SBTOA PODIR register A pull up pull down resistor for each bit can be 7 SBO2 SDA2 selected individually by the POPLU register P04 8 5812 At reset the input mode is selected and pull up resistors are dis P05 9 SBT2 SCL2 abled high impedance output P06 2 DA0 P10 20 yo TMOIO RMOUT port 1 7 bit COMS tri state port P11 21 TM11IO Each bit can be set individually as either an input or output by the P12 22 TM2IO P1DIR register A pull up pull down resistor for each bit can be P13 23 TM3IO selected individually by the P1PLU register P14 24 TM4IOA At reset the input mode is selected and pull up resistors are dis P15 25 TM5IOA abled high impedance output P16 26 TM7IOA P20 27 VO IRQO port 2 6 bit COMS tri state I O port P21 28 IRQ1 Each bit can be set individually as either an input or output by the P22 29 IRQ2A P2DIR register A pull up pull down resistor for each bit can be P23 30 IRQ3A selected individually by the P2PLU register P24 31 IRQ4 At reset the input mode is selected and pull up resistors are dis P25 32 IRQ5 abled high impedance output P27 19 Input NRST port 2 Port P27 has an n channel open drain configuration When 0 is written and the reset is initiated by software a low level will be output Pull up resistors are built in P30 33 SBO1
517. ot used SBTOA 6 VO P02 Serial interface Clock I O pins for serial interface 0 to 4 SBTOB 78 P92 clock I O pins The output configuration either COMS push pull or n channel SBT1 35 P32 open drain can be selected with the POODC PSODC PAODC SBT2 9 P05 SCL2 and P9ODC registers Pull up and pull down registers can be SBT3A 38 P35 SCL3A selected by the POPLU P3PLU P4PLU and P9PLU registers SBT3B 81 P95 SCL3B Select the output mode at the PODIR P3DIR P4DIR and P9DIR SBT4 74 P42 registers and serial data output mode by serial mode register 1 SCOMD1 SC1MD1 SC2MD1 SC3MD1 SC4MD1 These can be used as normal I O pins when the serial interface is not used TXDOA 4 Output SBOOA UART transmis In the serial interface in UART mode this pin is configured as the TXDOB 76 P90 SBOOB sion data output transmission data output pin TXD1 33 P30 581 pins The output configuration either COMS push pull or n channel TXD4 72 P40 SBI4 open drain can be selected with the POODC PSODC PAODC and P9ODC registers Clock I O can be selected by the POPLU registers Select the output mode with the PODIR P3DIR P4DIR and P9DIR registers and serial data output mode by serial mode register 1 SCOMD1 SC1MD1 SC4MD1 These can be used as normal I O pins when the serial interface is not used RXDOA 5 Input P91 SBIOA UART received In the serial interface in UART mode this pin is configured as the RXDOB 77 P34 SBIOB data input pins reception data output pin
518. oth edges level interrupt Edge selectable both edges interrupt STOP HALT recovered at both edges level interrupt Edge selectable key interrupt Edge selectable both edges interrupt STOP HALT recovered at both edges level interrupt Timer Counters 9 Timers 8 can be operated independently 8 bit timer for general use 2 sets 8 bit timer also serves as UART baud rate timer 4 sets 8 bit free running timer 1 set Time base timer 1 set 16 bit timer for general use 1 set Timer 0 8 bit timer for general use Square wave output timer pulse output PWM output Event count Simple pulse with measurement Real time output control Remote control carrier output Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock Timer 1 8 bit timer for general use Square wave output timer pulse output Event count Timer synchronous output 16 bit cascade connection function connected to timer 0 Clock source fosc fosc 4 fosc 16 fosc 64 fosc 128 fs 2 fs 8 fx external clock Hardware Functions 1 5 1 Overview Timer 2 8 bit timer also serves as UART baud rate timer Square wave output timer pulse output PWM output Event count Serial transfer clock output Timer synchronous output Simple pulse with measurement Real time output control Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock Timer 3 8 bit timer also serves as UART
519. ount 8 bit Start condition None First transfer bit MSB Input edge Falling edge Output edge Rising edge Clock Clock master Clock source fs 2 Clock source 1 8 dividing Not divided by 8 SBT1 SBO1 pin style Nch open drain SBT1 pin pull up resistor Added SBO pin pull up resistor Added serial 1 communication complete Enable interrupt SBO1 output after last data output 1 fix An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation 1 Set the SC1PSCE flag of the SC1MD3 register to 1 to SC1MD3 0x03FA0 select prescaler operation bp3 SC1PSCE 1 2 Select the clock source 2 Set the SC1PSC2 to 0 flag of the SC1MD3 register to SC1MD3 0x03FA0 100 to select the fs 2 to clock source bp2 0 SC1PSC2 0 100 3 SBO1A output control after the last data 3 Set the SC1FDC1 to 0 flag of the SC1MD3 register to output 00 to select 1 High fix of the SBO1 last data SC1MD3 0x03FA0 output bp7 6 SC1FDC1 0 00 XII 32 Operation 12 Serial interface 1 Setup Procedure Description 4 Control the pin style P3ODC 0x03F2C bp2 0 P3ODC2 0 1 1 P3PLU 0x03F43 bp2 0 P3PLU2 0 1 1 5 Control the pin direction P3DIR 0x03F43 bp2 1 0 P3DIR2 1 0 1 0 1 6 Set the SC1MDO register Select the transfer bit count SC1MDO 0x0O3F9D bp2 0 SC1LNG2 0 111 Select the start condition
520. ount and First Transfer Bit In the case of reception when the transfer bit count is 7 bits the data storing method to the received data buffer RXBUFO is different depending on the first transfer bit selection At MSB first data are stored to the upper bits of RXBUFO When there are 7 bits to be transferred as shown on Table 11 3 18 if data to A are stored to bp7 to bp of RXBUFO At LSB first data are stored to the lower bits of RXBUFO When there are 7 bits to be transferred as shown on Table 11 3 19 if data to are stored to to bp6 of RXBUFO 7 6 5 4 3 2 1 0 RXBUFO A B C D E F Figure 11 3 18 Transfer Bit Count and First Transfer Bit starting with MSB RXBUFO DE IEEE Figure 11 3 19 Transfer Bit Count and First Transfer Bit starting with LSB Operation XI 43 11 Serial interface 0 XI 44 The following items are the same as clock synchronous serial B First Transfer Bit Setup Refer to XI 14 B Transmission Data Buffer Refer to XI 14 B Received Data Buffer Refer to XI14 Transfer Bit Count and First Transfer Bit Refer to XI 16 B Transmission Buffer Empty Flag Refer to XI 19 B Emergency Reset Refer to XI 20 Operation 11 Serial interface 0 B Transmission Timing TXDO pin Parity Stop bit bit bit SCOTBSY Data settoTXBUFO Interrupt SCOTIRQ Figure 11 3 20 Transmission T
521. ount control 0 Halt the count 1 Operate the count TM7PS1 Count clock selection TM7PS0 00 1 1 of clock 01 1 2 of clock 10 1 4 of clock 11 1 16 of clock TM7CK1 Clock source selection TM7CKO 00 fosc 01 fs 10 TM7IO input 11 Synchronous TM7IO input VI 8 Control Registers T7ICEDG0 Timer 7 Mode Register 2 TM7MD2 0x03F79 T7PWMSL TM7BCR TM7IRS1 T7ICEN T7ICT1 Chapter 6 16 bit Timer T7ICTO 0 0 0 0 0 0 T7ICEDG 0 Description Capture trigger edge selection 0 Select the both edges 1 Select the specified edge T7PWMS L PWM mode selection 0 Set duty by OC1 1 Set duty by OC2 TM7BCR Timer 7 count clear factor selection 0 Full count OVF 1 Match of BC and OC1 TM7PWM Timer output waveform selection 0 Output timer 1 Output PWM TM7IRS1 Timer 7 interrupt factor selection 0 Counter clear 1 Match of BC and OC1 T7ICEN Input capture operation enable flag 0 Disable capture operation 1 Enable capture operation T7ICT1 T7ICTO Capture trigger selection 00 External interrupt 0 input signal P20 IRQO input signal 01 External interrupt 1 input signal P21 IRQ1 input signal 10 External interrupt 2 input signal P22 IRQ2A PDO IRQ2B input signal 11 External interrupt 3 input signal P23 IRQ3A PD1 IRQ3B input signal Control Registers VI 6 16 bit Timer VI 10 Timer I O Pin Switching Co
522. ource bp2 0 SC4PSC2 0 110 3 Control the pin type 3 Set the PAODCO flag of the PAODC register to 1 to PAODC 0x0O3F3C select Nch open drain for the TXD4 P4PLUO flag bp0 1 of the PAPLU register to 1 to add pull up register P4PLU 0x03F44 P4PLUO 1 4 Control the pin direction 4 Set the P4DIRO flag of the Port 4 pin direction control P4DIR 0x03F34 register P4DIR 1 and the P4DIR3 flag to 0 to set bp1 0 P4DIR1 0 0 1 P40 to the output mode P41 to the input mode XV 50 Operation 15 Serial interface 4 Setup Procedure Description 5 Set the SCAMDO register Select the start condition SC4MD0 0x03FAB bp3 SC4STE 1 Select the first bit to be transferred SC4MD0 0x03FAB bp4 SC4DIR 0 6 Set the SC4MD2 register Control the output data SC4MD2 0x03FAD SC4BRKE 0 Select the added parity bit SC4MD2 0x03FAD bp3 SC4NPE 0 bp5 4 SC4PM1 0 00 Specify the flame mode SC4MD2 0x03FAD bp7 6 SC4FM1 0 11 7 Set the SC4MD1 register Select the communication type SC4MD1 0x03FAC bp0 SC4CMD 1 Select the clock frequency SC4MD1 0x03FAC bp3 SC4CKM 1 bp2 SCAMST 1 Control the pin function SC4MD1 0x03FAC bp4 SC4SBOS 1 bp5 SC4SBIS 1 bp7 SC4IOM 0 8 Enable the interrupt SC4RICR 0x03FF8 bp1 SC4RIE 1 SC4TICR 0x03FF9 bp1 SCATIE 1 9 Start the serial transmission The transmission y TXBUF4 0x03FB1
523. ource If the watchdog timer is overflowed the watch dog interrupt WDIRQ is generated as non maskable interrupt NMI At reset the watchdog timer is stopped but once the operation is enabled it cannot be stopped except at reset The watchdog timer control register WDCTR sets when the watchdog timer is released or how long the time out period should be If the watchdog interrupt WDIRQ is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware a The watchdog timer cannot stop once it starts operation Usage of Watchdog Timer When the watchdog timer is used constant clear in program is needed to prevent an overflow of the watchdog timer As result of the software failure the software cannot execute in the intended sequence thus the watchdog timer overflows to detect errors Programming of the watchdog is generally done in the last step of its programming How to Detect Incorrect Code Execution The watchdog timer is executed to be cleared in the certain cycle on the correct code execution In this LSI the watchdog timer detects errors when 1 the watchdog timer overflows When the watchdog timer detects any error the watchdog interrupt WDIRQ is generated as a non maskable interrupt NMI How to clear Watchdog Timer The watchdog timer can be cleared by writing to the watchdog t
524. output PWM output Time in the compare regiser PWM basic components overflow time of binary counter Figure 5 7 1 Count Timing of PWM Output at Normal Timers 0 2 and 4 PWM source waveform A is H while counting up from 0x00 to the value stored in the compare register B is L after the match to the value in the compare register then the binary counter continues counting up till the overflow e C is again if the binary counter is overflown The PWM outputs PWM source waveform with 1 count clock delay because the waveform is created inside to correct the output cycle 8 bit PWM Output V 41 5 8 bit Timers Count Timing of PWM Output when the compare register is 0x00 Timers 0 2 and 4 Here is the count timing when the compare register is set to 0 00 TMnEN flag Compare register wA DOZOBDOD hee DOO zo i counter H TMnIO output PWM output Figure 5 7 2 Count Timing of PWM Output when compare register is 0x00 When TMnEN flag is stopped 0 PWM output is Count Timing of PWM Output when the compare register is OxFF Timers 0 2 and 4 Here is the count timing when the compare register is set to OxFF Count clock TMnEN flag o relied NE MN Tr register ER DUEB AD E EN d i counter TMnIO output PWM output Figure 5 7 3 Count Timing of PWM Output when the compare register is OXFF Timer
525. output Remote control career base timer selection RMBTMS 0 Timer 0 output selection 1 Timer 3 output selection Control Registers VIII 5 8 Remote Control Functions 8 3 Operations 8 3 1 Operations Remote control career output functions can create the career pulse for the remote control Operation of the remote control career output Remote control career can be created by using the output signals of timer 0 and timer 3 Duty ratio is selectable from 1 2 1 3 and timer output Remote control career output signal is output from the RMOUT pin 10 Timer base cycle lt gt Timer base cycle timer output RMOUT 1 2 duty RMOUT 1 3 duty Figure 8 3 1 Remote Control Career Output Signal Duty Ratio Count Timing of Remote Control Career Output Functions timerO timer3 Timer base cycle timer output output ON output OFF RMOUT 1 3 duty 1 Figure 8 3 2 Count Timing of Remote Control Career Output Functions timer0 timer3 Even if the RMOEN flag is switched OFF at the career output the career wave is held by the synchronous circuit VIII 6 Operations 8 Remote Control Functions Set the P1OMDO flag of the P1OMD register to 1 at switched ON and 0 at switched OFF When the RMOEN flag is changed the base cycle and the duty cannot be changed at the same time That affects the career wave Operations VIII 7
526. p Flag Description gt O Q O Port D PDDIR7 PDDIR6 PDDIR5 PDDIR4 PDDIR3 PDDIR2 PDDIR1 PDDIR0 mode selection 0 Input mode 1 Output mode Port D Pull up Resistor Control Register PDPLU 0x03F4D PDPLU7 PDPLU6 PDPLUS5 PDPLU4 PDPLU3 PDPLU2 PDPLU1 Chapter 4 Ports PDPLUO 0 0 0 0 0 0 0 0 bp Flag Description gt O Q O PDPLU7 PDPLU6 PDPLU5 PDPLU4 PDPLU3 PDPLU2 PDPLU1 PDPLU0 1 Added Pull up resistor selection 0 Not added Port D Output Mode Register PDOMD 0x03F1B Flag PDOMDA PDOMD3 PDOMD2 At reset 0 0 0 Access R W R W R W bp Flag Description 7 6 i 5 I O port 7 selection 4 PDOMD4 0 0 port 1 TM7IO port TM5IO selection 3 PDOMD3 0 l O port 1 TMBIO port TM4IO selection 2 PDOMD2 01 0 port 1 TM4IO 1 E z 0 2 Port D IV 109 4 I O Ports 4 13 3 Block Diagram Reset PDPLUO Pull up resistor Q contorol WEK R PDDIR H I O direction Ro 0 control WEK ZR 95 Port output data Q EDOUTO WEK R snq eq Schmitt trigger input Port input data lt PDIN0 7 External interrupt 2
527. p Procedure Description 1 Select the prescaler operation SCOMD3 0x03F92 bp3 SCOPSCE 1 2 Select the clock source SCOMD3 0x03F 92 bp2 0 SCOPSC2 0 100 3 SBOOA output control after the last data output SCOMD3 0x03F92 bp7 6 SCOFDC1 0 00 1 Set the SCOPSCE flag of the SCOMDS register to 1 to select prescaler operation 2 Set the SCOPSC2 to 0 flag of the SCOMDS register to 100 to select the fs 2 to clock source 3 Set the SCOFDC1 to 0 flag of the SCOMDS register to 00 to select 1 High fix of the SBOO last data output Operation XI 38 11 Serial interface 0 Setup Procedure Description 4 Select the used pins SCSEL0 0x03F4F bp0 SC0SEL 0 5 Pin style controlt POODC 0x03F1C bp2 0 POODC2 0 1 1 POPLU 0x03F40 bp2 0 POPLU2 0 1 1 6 Control the pin direction PODIR 0x03F49 bp2 PODIR2 1 bp1 PODIR1 0 bp0 PODIRO 1 7 Set the SCOMDO register Select the transfer bit count SCOMD0 0x03F8F bp2 0 SCOLNG2 0 111 Select the start condition SCOMD0 0x03F8F bp3 SCOSTE 0 Select the first bit to be transferred SCOMD0 0x03F8F bp4 SCODIR 0 Select the transfer edge SCOMD0 0x03F8F bp7 SCOCE1 1 8 Set the SCOMD1 register Select the communication style SCOMD1 0x03F90 bp0 SCOCMD 0 Select the transfer clock SCOMD1 0x03F90 bp2 SCOMST 1 bp3 SCOCKM 0 Select the transfer clock SCOMD1 0x03F90 bp4 SCOSBOS 1
528. p pull down resistor 1 D Q selection WEK R Y Reset Pull up pull down resistor pRo PAPLU1 s control VR Res I O directon control PADIR1 p K R Ye ee Port output data iad PAOUTI Wek N R E Reget E Input mode control Rg PAIMD1 Wek R Schmitt trigger input Port input data lt 1 PAINI 17 U R Analog input Figure 4 12 2 PA1 Block Diagram Port A IV 101 4 I O Ports rM Reset i R JPADWN Pull up pull down resistor p Qa selection we R 1 Reset Pull up pull down resistor PAPLU2 control Reset directon control PADIR2 wex Port output data 21 p d PAOUT2 E ved Ve Y _ E Eee Reset Input mode control DRA PAIMD2 WEK R Schmitt trigger input Port input data lt 1 77 N R Analog input Figure 4 12 3 PA2 Block Diagram M Reset 5 PADWN Pull up pull down resistor selection Wek R Reset Pull up pull down resistor PAPLU3 gt control wek R Reset f directon control PADIR3 gt gt K R r V eT T Port output data 21 6 d PAOUTS 11 S wek R Y 077 Reset Input mode control DRA PAIMD3 Port input data Analog input IV 102 Port A
529. peration Pins Setup with 2 channels at reception Chapter 12 Serial interface 1 Table 12 3 11 shows the setup for synchronous serial interface pin with 2 channels SBOI pin SBT1 pin at reception SBII pin can be used as a port Table 12 3 11 Setup for Synchronous Serial Interface Pin with 2 channels at reception Setup item Data output pin Serial unused pin Clock I O pin SBO1 pin SBI1 pin SBT1 pin Clock master Clock slave SC1MD1 SC1MST Port pin P30 P31 P32 Serial data input SBI1 selection SC1MD1 SC1IOM Function Port Serial input Transfer clock input Transfer clock input output output SC1MD1 SC1SBO SC1MD1 SC1SBIS SC1MD1 SC1SBIS 5 Style Push pull Nch open Push pull Nch open drain drain P3ODC P3ODC2 Input mode Output mode Input mode P3DIR P3DIR0 P3DIR P3DIR2 Pull up setup Added Not added Added Not added P3PLU P3PLU2 Operation XII 31 12 Serial interface 1 12 3 2 Setup Example ECC I B Transmission Reception Setup Example The setup example for clock synchronous serial communication with serial 1 is shown Table 12 3 12 shows the conditions at transmission reception Table 12 3 12 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item Set to Serial data input pin Independent 3 channels Transfer bit c
530. peration TM7IO pin can output a pulse signal with a arbitrary frequency 16 bit Timer Pulse Output Operation Timer 7 These timers can output 2 x cycle signal compared with the set value of the compare register 1 TM7OC1 and the 16 bit full count Output pins are as follows Table 6 5 1 Timer Pulse Output Pin Timer 7 Pulse output pin TM71O output P16 PD4 Table 6 5 2 shows the timer interrupt generation sources and the flags that control the timer pulse output cycle Table 6 5 2 16 bit Timer Interrupt Generation Source and Timer Pulse Output Cycle Timer 7 TM7MD2 register Interrupt source Timer pulse output cycle TM7IRS1 flag TM7BCR flag 1 1 TM70C1 compare match Set value of TM7OC1 x 2 0 1 TM70C1 compare match Set value of TM7OC1 x 2 1 0 TM7OC1 compare match Full count of TM7BC x 2 0 0 Full count over flow Full count of TM7BC x 2 16 bit Timer Pulse Output 6 16 bit Timer TM7EN flag TM7IO input Compare register 1 Binary 0000 0001 0002 OE 00001 0001 counter Interrupt request flag output dL Figure 6 5 1 Count Timing of Timer Pulse Output Timer 7 TM71O output pin outputs 2 x cycle compared with the value of the compare register If the binary counter reaches the compare value or full count overflow is occurred the binary counter is cleared to 0x0000 and the output timer output is inverted In
531. pheral functions timer serial interface A D converter D A converter etc Peripheral functions vary depending on the model Overview 2 1 2 CPU Control Registers Chapter 2 CPU Basics This LSI locates the peripheral circuit registers in memory space 0x03F00 to 0x03FFF with memory mapped 1 O CPU control registers are also located in this memory space Table 2 1 3 CPU Control Registers data on interrupt process Registerss Address R W Function Pages CPUM 0x03F00 R W CPU mode control register 11 51 1 MEMCTR 0x03F01 R W Memory control register 11 38 Reserved 0x03F04 E For test RCCTR 0x03F09 R W ROM correction control register 11 30 SBNKR 0x03F0A R W Bank register for source address 11 19 DBNKR 0x03F0B R W Bank register for destination addres 20 Reserved 0x03F0F for test RCnAP OxO3FCO R W ROM correction address setting register 11 31 to 32 5 Reserved OxOSFEO For debugger NMICR OxOSFE1 R W Non maskable interrupt control register 111 19 xxxICR OxOSFE2 R W Maskable interrupt control register 20 to 45 Reserved 0x03FFF Reserved For reading interrupt vector a part of bit is for read only Overview 1 5 2 CPU Basics Il 6 2 1 3 Instruction Execution Controller The instruction execution controller consists of four blocks memory instruction queue instruction registers and instruction decoder Instru
532. physical injury fire social damages for example by using the products When using products for which damp proof packing is required observe the conditions including shelf life and amount of time let standing of unsealed items agreed upon when specification sheets are individually exchanged This book may be not reprinted or reproduced whether wholly or partially without the prior written permission of Matsushita Electric Industrial Co Ltd If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual mOrganization In this LSI manual this LSI functions are presented in the following order overview basic CPU functions interrupt functions port functions timer functions serial functions and other peripheral hardware functions Each section contains overview of function block diagram control register operation and setting example mManual Configuration Each section of this manual consists of a title summary main text key information precautions and warnings and references The layout and definition of each section are shown below Header Chapter number and Chapter title Section title Basic CPU Sub section title 2 8 Reset waww Fry Main text 8 1 Reset operation the CPU contents are reset and registers are intialized when the NRST pin 27 is pulled to low
533. pin P30 P31 TXD1 RXD1 pins selection TXD1 RXD1 pins independent SC1MD1 SC1IOM Function Serial data output Serial data input SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Push pull Nch open drain P30DC P30DC0 Output mode Input mode P3DIR P3DIR0 P3DIR P3DIR1 Pull up setup Added not added P3PLU P3PLU0 Operation XII 49 12 Serial interface 1 12 3 4 Setup Example c An sn oOsII r ssasCsrcsOr rr n rIr B Transmission Reception Setup The setup example at UART transmission reception with serial 1 is shown Table 12 3 24 shows the condition at transmission reception Table 12 3 24 UART Interface Transmission Reception Setup Setup item SEt to TXD1 RXD1 pin Independent with 2 channels Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source Timer 5 TXD1 RXD1 pin type Nch open drain Pull up resistor of TXD1 pin Added Parity bit add check 0 added check Serial 1 transmission complete Enable interrupt Serial 1 reception complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the baud rate timer 1 Set the baud rate timer by the TM5MD register the 5 register Set the TM5EN flag to 1 to start timer 5 Chapter 5 5 9 Serial Transfer Clock Output Operation 2 Select the clock
534. pin switching control register SCSEL is 0 for POO to P02 and 1 for P90 to P92 P93 is used as output pin of the serial 0 transmission data or the IIC3 transmission data as well When the SC3SBOS flag of the serial interface 3 mode register 1 SC3MD1 is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 9 Nch open drain control register P9ODC P94 is used as input pin of the serial 3 reception data or the IIC 3 reception data P95 is used as I O pin of the serial 3 clock as well When the SC3SBTS flag of the serial interface 3 mode regis ter 1 SC3MD1 is set to 1 it is output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the port 9 Nch open drain control register P9ODC Also serial 3 I O pin can be selected by setting of serial I O pin switching control register SCSEL When SC3SEL flag of serial I O pin switching control register SCSEL is 0 for P33 to P35 and for P93 to P95 Port 9 IV 89 4 I O Ports IV 90 4 11 2 Registers The following Table shows registers that control the Port 9 Table 4 11 1 Port 9control register Registers Address Function P9OUT OxO3F19 Port 9 Output Register P9IN 0x03F29 Port 9 Input Register IV 91 P9DIR 0x03F39 RAN Port 9 Direction Control Register IV 91 P9PLU 0x03F49 RAN Port 9 Pull
535. pins If the synchronous output event that is set by the pin control register P7SEV is never generated the synchronous output value stored register holds the same value when the synchronous output event is enabled Before the synchronous output is enabled by the synchronous output control register P7SYO set the initial value of the synchronous output to the port 7 output register P7OUT in advance IV 118 Synchronous Output Chapter 4 I O Ports Port 7 Synchronous Output External interrupt 2 IRQ2 The synchronous output timing when the synchronous output event is set to the external interrupt 2 is shown below The latched data on port 7 is output in synchronization with the falling edge of the IRQ2 Port 7 output X External interrupt IRQ2 X c Figure 4 15 1 Synchronous Output Timing by Event Generation IRQ2 Port 7 Synchronous Output Timer 1 Timer 2 Timer 7 The timer interrupt flag TMnIRQ is generated when the set values of binary counter and compare register are matched The latched data on port 7 is output from the port 7 in synchronization with the rising edge of the TMnIRQ Timer count clock RN MONS Timer compare i N register i i i i i i Port 7 output 7 Y Interrupt request flag Port 7 output X Y 2 Figure 4 15 2 Synchronous Output Timing by Event Generation Timer 1 Timer 2 Timer 7 Synchronous Output 119
536. ply current during STOP Ta 25 C mode 1 3 3 V DD1 3 988 85 86 9 Measured under conditions without load 10 The supply current during operation Ippi 602 are measured under the following conditions After all pins are set to input mode and the oscillation is set to NORMAL mode MMOD pin is at Vgs level the input pins are at Vpp level and 32 MHz 20 MHz square wave of Vpp and Vss amplitudes is input to the OSC1 pin The supply current during operation is measured under the following conditions After all I O pins are set to input mode and the oscillation is set to SLOW mode the MMOD pin is at Vss level the input pins are at Vpp level and a 32 768 kHz square wave of Vpp and Vss ampli tudes is input to the XI pin The supply current during HALT1 mode Ipp4 are measured under the following conditions After all pins are set to input mode and the oscillation is set to HALT mode the MMOD pin is at level the input pins are at Vpp level and 32 768 kHz square wave of Vpp and Vss ampli tudes is input to the XI pin The supply current during STOP mode Ipps is measured under the following conditions After the oscillation is set to STOP mode the MMOD pin is at level the input pins are at Vpp level and the OSC1 and XI pins are unconnected is for Flash version Electrical Characteristics 1 25
537. port Input mode No pull up resistor port Input mode P27 Pull up resistor Others No pull up resistor I O port Input mode No pull up resistor port Input mode No pull up pull down resistor port A7 A6 A5 A4 A3 A2 A1 AO Output mode No pull up resistor A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A 10 A9 A8 Output mode No pull up resistor A15 A14 A13 A12 A11 A10 A9 A8 NEW NRE NCS Output mode Others Input mode No pull up pull down resistor NEW NRE NCS I O port Input mode No pull up resistor D7 D6 D5 D4 D3 D2 D1 D0 Input mode No pull up resistor port Input mode No pull up pull down resistor port Input mode No pull up resistor port Overview 4 I O Ports 4 1 3 Control Registers port O port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port A port Dare controlled by the data output register PnOUT the data input register PnIN the I O direction control register PnDIR the pull up resistor control register PnPLU or the pull up pull down resistor control register PnPLUD and registers that control special function pin PIOMD PnIMD PnSYO PnSEV PnCNT EXADV PnODC port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port A port DThe following Table shows the reg isters to control Table 4 1 3 I O Port Control Registers L
538. prescaler 1 is selected to the count clock of the timer 0 A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Select the prescaler output 1 Select fs 2 to the prescaler output by the TMOPSC 1 to CKOMD 0x03F56 0 TMOBAS flag of the timer 0 prescaler selection bp2 1 TMOPSC1 0 2X0 register bp0 TMOBAS 1 At the timer prescaler output selection should be set up by the timer mode register V 26 Prescaler 5 8 bit Timers 5 4 8 bit Timer Count 5 4 1 8 bit Timer Operation Timer operation can constantly generates interrupts 8 bit Timer Operation Timers 0 1 2 3 4 and 5 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register TMnOC in advance If the binary counter TMnBC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from 0x00 Table shows clock source that can be selected by timer Clock source per Count Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit fosc 50 ns O O fosc 4 200 ns O O fosc 16 800 ns O O fosc 32 1 6 us fosc 64 3 2 us fosc 128 6 4 us 15 2 200 ns O
539. ption at falling edge Transmission at rising edge Operation XV 25 15 Serial interface 4 Communication Function at Standby Mode This serial interface has the following way about the return from the standby mode This serial interface can do the slave reception at the standby mode CPU operation status can be recovered from standby to normal by the communication complete interrupt SC4TIRQ that is generated after the slave reception At the standby mode if the transfer bit count data is received once that is set by the SC4LNG2 to 0 flag of the SC4MD0 register the continuous reception is not available because the next data is not allowed The received data should be read out from the received data buffer RXBUF4 after recovering the normal mode In the reception at the standby mode the communication with enabled start condition is not available Disable the start condition The dummy data should be set to the transmission data buffer TXBUFA before the transition to the standby mode XV 26 Normal mode Standby mode Normal mode lt gt lt lt Oscillation stabilization Clock SBT4 pin Input pin 5 4 SBO4 pin Transfer bit counter SC4RBSY Data set to TXBUF4 Interrupt SC4TIRQ Figure 15 3 16 Reception Timing at Standby Mode Reception at rising edge start condition is dis abled Operation B Pins Setup with channels at transmission
540. put Set the SCOIOM flag 0 to set the serial data input from the SBIO pin 9 Set the interrupt level by the SCOTLV1 to 0 flag of the serial 0 UART transmission interrupt control register SCOTICR Operation 11 Serial interface 0 Setup Procedure Description 10 Enable the interrupt 10 Setthe SC0TIE flag of the SC0TICR register to 1 to SCOTICR 0x03FF3 enable the interrupt bp1 SCOTIE 1 If any interrupt request flag SCOTIR of the SCOTICR register is already set clear SCOTIR before the interrupt is enabled 11 Start the serial transmission 11 Set the transmission data to the serial transmission Transmission data y TXBUFO 0x03F95 data buffer TXBUFO The transmission or reception is Received data y input SBIO pin started by the internal clock generation When the transmission finished the serial UART transmission interrupt SCOTIRQ is generated Chapter 3 3 1 4 Setup Note Each procedure 1 to 3 7 8 and 9 can be set at the same time ter to 0 and set the serial input to 1 input The SBIO pin can be used as a general port Also when only reception is operated set the SCOSBOS of the SCOMD 1 register to 0 to select a port a When only transmission with 3 channels is operated set the SCOSBIS of the SCOMD1 regis When communicate with 2 channels the SBOO pin inputs outputs serial data The port direction control register PODIR switches At
541. put high voltage Vina 0 8 23 Input low voltage 0 0 2 24 Input leakage current Vin 0 V to 2 0 uA 25 Pull up resistor Rpu4 Vpp3 9 0 V ljy21 5 V 10 30 120 26 Output high voltage Vpp3 0 0 V 0 5 mA 4 5 27 Output low voltage VoL4 Vpp3 9 0 V lo 21 0 mA 5 0 5 4 Vpp323 0 V to 5 5 V P40 to PAO Schmitt trigger input 28 Input high voltage Vins 0 8 Vppa 29 Input low voltage ViL5 0 5 0 2 30 Input leakage current 5 0 V to 2 0 31 Pull up resistor Reus Vpp3 9 0 V 1 5 10 30 120 T 32 Pull down resistor Rpws 5 0 V IN 3 5 10 30 120 33 Output high voltage Vous Vpp3 9 0 V 0 5 mA 4 5 34 Output low voltage VoLs Vpp3 9 0 V Io 21 0 mA 0 5 pin 5 P80 P87 Schmitt trigger input 35 Input high voltage Vine 0 8 Vpps 36 Input low voltage Vite 0 0 2 Electrical Characteristics Chapter 1 Overview Rating Parameter Symbol Conditions Unit MIN TYP MAX 37 leakage current lLKe Vin 0 V to 2 2 0 uA 38 Pull up resistor Rpue 5 0 1 5 10 30 120 39 Output high voltage 5 0 V 0 5 mA 4 5 40 Output low voltage Voie Vpp3 9 0 V loy 215 0 mA 1 0 I O pin 7 P27 NRST Schmitt trigger
542. put the special function data and 0 to use as the general port I O pins of the timer 4 can select either P14 or PD2 by setting of the timer I O pin switching control register TMSEL When TMASEL flag of the timer I O pin switching control register TMSEL is 0 P14 is selected and 1 PD2 is selected PD3 is used as I O pin of the timer 5 as well The output mode can be selected by bp3 of the port D output mode register PDOMD by each bit The port D output mode register PDOMD is set to 1 to output the special function data and 0 to use as the general port I O pins of the timer 5 can select either P15 or PD3 by setting of the timer I O pin switching control register TMSEL When TMSSEL flag of the timer I O pin switching control register TMSEL is 0 P15 is selected and 1 PD3 is selected PD4 is used as I O pin of the timer 7 as well The output mode can be selected by bp4 of the port D output mode register PDOMD by each bit The port D output mode register PDOMD is set to 1 to output the special function data and 0 to use as the general port Port D IV 105 4 I O Ports I O pins of the timer 7 can select either P16 or PD4 by setting of the the timer I O pin switching control register TMSEL When TM7SEL flag of the timer I O pin switching control register TMSEL is 0 P16 is selected and 1 PDA is selected PD5 is used as buzzer output pin as well When bp7 of the oscillation stabilization wait
543. r V 16 TM20C Timer 2 compare register V 14 TM2MD 0x03F5G Timer 2 mode register V 19 CK2MD 0x03F5E Timer 2 prescaler selection register V 11 TM2ICR 0x03FEA Timer 2 interrupt control register 28 P1OMD 0x03F2B Port 1 output mode register IV 13 P1DIR 0x03F31 Port 1 direction control register IV 13 IRQSEL 0x03F4E External interrupt pin switching control register 111 53 Control Registers 5 8 bit Timers Register Address Function Timer 3 TM3BG 0x03F59 R Timer 3 binary counter V 16 TM3OC 0x03F5B R W Timer 3 compare register V 14 TM3MD 0x03F5D R W Timer 3 mode register V 20 CK3MD 0x03F5F R W Timer 3 prescaler selection register V 12 TM3ICR 0x03FEB R W Timer 3 interrupt control register III 29 P1OMD 0x03F2B R W Port 1 output mode register IV 18 P1DIR 0x03F31 R W Port 1 direction control register IV 16 Timer 4 TM4BG 0x03F60 R Timer 4 binary counter V 16 TM40C 0x03F62 R W Timer 4 compare register V 15 TM4MD 0x03F64 R W Timer 4 mode register V 21 CK4MD 0x03F66 R W Timer 4 prescaler selection register V 12 TM4ICR 0x03FEC R W Timer 4 interrupt control register III 30 P1OMD 0x03F2B R W Port 1 output mode register IV 18 P1DIR 0x03F31 R W Port 1 direction control register IV 16 PDOMD 0x03F1B R W Port D output control register IV 107 PDDIR 0x03F3D R W Port D
544. r bit counter SCO TBSY Data set to TXBUF0 Interrupt SCOTIRQ Figure 11 3 6 Transmission Timing at falling edge start condition is enabled At master At slave Tmax 3 5T T 2 4 I Clock SBTO Output pin SBOO pin Transfer bit counter SCO TBSY Data set to TXBUF0 Interrupt SCOTIRQ Figure 11 3 7 Transmission Timing at falling edge start condition is disabled XI 22 Operation 11 Serial interface 0 At master At slave Tmax 25TT f 2 lt gt lt Clock SBTO pin Output pin SBOO pin Transfer bit counter SCOTBSY Data set to TXBUFO Interrupt SCOTIRQ Figure 11 3 8 Transmission Timing at rising edge start condition is enabled At master At slave Tmax 3 5T f _Tmax 2T Clock SBTO pin Output pin SBOO pin Transfer bit counter SCOTBSY Data setto Interrupt SCOTIRQ Figure 11 3 9 Transmission Timing at rising edge start condition is disabled Operation XI 23 11 Serial interface 0 B Reception Timing Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY Interrupt SCOTIRQ Figure 11 3 10 Reception Timing at rising edge start condition is enabled At master Tmax 3 5T T Clock SBTO pin Input pin SBIO S
545. r flag should be operated until the next communication is finished Those error flag has no effect on communication operation Table 12 3 18 shows the list of reception error source Table 12 3 18 Reception Error Source of UART Serial Interface Flag Error SC1ORE Overrun error Next data is received before reading the receive buffer SC1PEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 When parity bit is 0 Odd parity The total of 1 of parity bit and character bit is even Even parity The total of 1 of parity bit and character bit is odd SC1FEF Framing error Stop bit is not detected B Judgement of Break Status Reception Reception at break status can be judge If all received data from start bit and stop bit is 0 the SCIBRKF flag of the SCIMD2 register is set and regards the break status The SCIBRKF flag is set at generation of the reception complete interrupt SCIRIRQ Operation XII 41 12 Serial interface 1 Continuous Communication This serial interface has continuous communication function If data is set to the transmission data buffer TXBUFI during communication the transmission buffer empty flag SC1TEMP is set to continue automatic com munication This does not generate any blank in communication Set data to TXBUF between previous data setup and generation of the communication complete interrupt SC1TIRQ Clock Setup Transfer clock is not nece
546. r that stores flags for operation results interrupt mask level maskable interrupt enable PSW is automatically pushed onto the stack when an interrupt occurs and is automati cally popped when return from the interrupt service routine Table 2 1 4 Processor Status Word PSW bp 7 6 5 4 3 2 1 0 Flag BKD MIE IM1 IM0 VF NF CF ZF At reset 0 0 0 0 0 0 0 0 Bank disable flag 0 Bank addressing is enabled 1 Bank addressing is disabled Maskable interrupt enable 0 All maskable interrupts are disabled 1 xxxLVn xxxlE for each interrupt is enabled Interrupt mask level Controls maskable interrupt acceptance Overflow flag 0 Overflow did not occur 1 Overflow occured Negative flag 0 MSB of operation results is 0 1 MSB of operation results is 1 Carry flag 0 A carry or a borrow from MSB did not occur 1 A carry or a borrow from MSB occured Zero flag 0 Operation result is not O 1 Operation result is O 10 Overview Chapter 2 CPU Basics Zero Flag ZF Zero flag ZF is set to 1 when all bits are 0 in the operation result Otherwise zero flag is cleared to 0 Flag CF Carry flag CF is set to 1 when a carry from or a borrow to the MSB occurs Carry flag is cleared to 0 when no carry or borrow occurs Negative Flag NF Negative flag NF is set to 1 when MSB is 1 and reset to 0 when MSB is
547. racteristics 1 5 5 D A Converter Characteristics Chapter 1 Overview Ta 40 C to 85 C Vppi Vppo2 3 0 V to 3 6 V Vpp3 Vpp1 to 5 5 V Vos1 Vss2 V553 0 V input leakage current Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 8 Bits 2 ae voltage low 0 10 eve 3 3 V DAyss 0 V Reference voltage high D D7 to DO ALL L 3 jevel AVDD 2 0 Vppi V 4 Zero scale output voltage Vzs DAvpp 3 3 V DAvss 0 V 0 05 0 0 0 05 5 Full scale output voltage Ves D7 to DO ALL H 3 24 3 29 3 34 Analog output resistance 6 Minimum reference Roat 6 10 14 resistance 7 Non linearity error DAypp 3 3 V DAvss 0 V 20 3 0 Differential Non linearity 8 erar DNLE DAypp 3 3 V DAvss 0 V 2 0 3 0 Settling time External capacitor CL 35 pF ms T 2 3 SET All bits are set to ON or OFF s 3 0 10 Reference voltage pin _ 20 uA Ratings of items 1 4 to 9 are guaranteed at Vpp Daypp 3 3 V DAvss 0 0 V Electrical Characteristics 29 1 Overview 1 6 Package Dimension Package code QFP100 P 1818B Units mm Figure 1 6 1 Package Dimension The external dimensions of the package are subject to change Before using this product Y please obtain product specifications from the sales offices 1 30 Package Dimension 1 Overview 1 7 Cautions for Circuit S
548. ral port pin at the memory extension mode When bp6 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P66 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp6 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp6 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P67 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp6 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp6 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically Port 6 IV 57 4 I O Ports 4 8 2 Registers The following Table shows registers that control the Port 6 Table 4 8 1 Port 6control register P6OUT 0x03F16 Port 6 Output Register IV 58 P6IN 0x03F26 Port 6 Input Register IV 59 P6DIR 0x03F36 R W Port 6 Direction Control Register IV 59 P6PLU 0x03F46 R W Port 6 Pull up Resistor Control Register IV 60 EXADV 0x03F0E R W Address Outp
549. ransmission data is not valid Set the transmission data to TXBUF4 again to operate the transmission again RXBUFA is rewritten every time when communication is completed At continuous communi cation data of RXBUFA should be read out until the next reception is completed Transfer Bit Count and First Transfer Bit When the transfer bit is 1 bit to 7bit the data storing method to the transmission data buffer TXBUF4 is different depending on the first transfer bit selection At MSB first use the upper bits of TXBUF4 for storing When there are 6 bits to be transferred as shown on Figure 15 3 2 if data A to F are stored to bp2 to bp7 of TXBUFA the transmission is operated from F to A AtLSB first use the lower bits of TXBUFA for storing When there are 6 bits to be transferred as shown on Figure 15 3 3 if data to are stored to to bp5 of TXBUF4 the transmission is operated from A to F TXBUF0 F E D TXBUF0 Figure 15 3 3 Transfer Bit Count First Transfer Bit starting with LSB XV 14 Operation 15 Serial interface 4 Receive Bit Count and First Transfer Bit When the transfer bit count is 1 bit to 7 bits the data storing method to the received data buffer RXBUF4 is differ ent depending on the first transfer bit At MSB first data are stored to the lower bits of RXBUF4 When there are 6 bit
550. ration 13 Serial Interface 2 B Reception Timing Clock SBT2 pin Input pin SBI2 pin Transfer bit counter SC2BSY Interrupt SC2IRQ Figure 13 3 10 Reception Timing Rising edge Start condition is enabled at master Tmax 3 5T x o Clock 5 2 Input SBI2 pin Transfer bit counter SC2BSY Write data to TXBUF2 4 Interrupt SC2IRQ Figure 13 3 11 Reception Timing Rising edge Start condition is disabled Operation XIII 23 13 Serial Interface 2 Clock SBT2 pin Input pin SBI2 pin Transfer bit counter SC2BSY Interrupt SC2IRQ Figure 13 3 12 Reception Timing Falling edge Start condition is enabled at master Tmax 3 5T T H Clock SBT2 pin Input pin SBI2 pin Transfer bit counter SC2BSY Write data to TXBUF2 Interrupt SC2IRQ Figure 13 3 13 Reception Timing Falling edge Start condition is disabled XIII 24 Operation 13 Serial Interface 2 B Transmission Reception To operate transmission and reception at the same time set the SC2CEI flag of the SC2MDO register to 0 or 1 As data is recieved at the opposite edge of the transmission clock set the polarity of reception data input edge to opposite polarity of the transmission data output edge SBT2 pin Data is input at the rising edge of the clock SBI2 pin
551. rce of UART Serial Interface Flag Error SCOORE Overrun error Next data is received before reading the receive buffer SCOPEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 When parity bit is 0 Odd parity The total of 1 of parity bit and character bit is even Even parity The total of 1 of parity bit and character bit is odd SCOFEF Framing error Stop bit is not detected B Judgement of Break Status Reception Reception at break status can be judge If all received data from start bit and stop bit is 0 the SCOBRKF flag of the SCOMD2 register is set and regards the break status The SCOBRKF flag is set at generation of the reception complete interrupt SCORIRQ XI 42 Operation 11 Serial interface 0 Continuous Communication This serial interface has continuous communication function If data is set to the transmission data buffer TXBUFO during communication the transmission buffer empty flag SCOTEMP is set to continue automatic com munication This does not generate any blank in communication Set data to TXBUF between previous data setup and generation of the communication complete interrupt SCOTIRQ Clock Setup Transfer clock is not necessary for UART communication itself but necessary for setup of data transmission reception timing in the serial interface Select the timer to be used as a baud rate timer by SCOMD3 register Receive Bit C
552. rd and burst transfers The 1 transfer modes are divided into standard transfer modes and burst transfer modes There are fourteen standard modes 0 to D and two burst modes E and F In standard modes the operation specified for that mode executes everytime when is activated When the transfer ends the value set in the transfer counter ATI TRC decrements and bus control returns to the MCU core This operation repeats until the transfer counter reaches 0x00 When this happens 1 completes the final data transfer then generates an interrupt For instance if the initial transfer counter value is 0x05 and the activation factor is set to a timer 0 inter rupt ATCI is activated everytime when timer 0 overflows and the automatic transfer begins After fifth data transfers activated by fifth timer 0 overflow is completed the transfer counter value becomes 0x00 an ATC1 interrupt occurs and the operation ends Timer 0 overflows occurring after this point do not activate ATC1 For standard transfers the program must set the transfer counter to the number of 1 activations required In burst modes once is activated it transfers in one operation the number of bytes set in the transfer counter ATI TRC After the burst transfer begins the transfer counter decrements everytime when trans fers one byte of data When the counter reaches 0x00 generates an interrupt
553. re is a description of A D converter circuit setup procedure 1 Setthe analog pins Set the analog input pin set in 2 to special function pin by the port input mode register PAIMD Setup of the port A input mode register should be done before analog voltage is put to pins 2 Select the analog input pin Select the analog input pin from AN7 to ANO by the ANCHS2 0 flag of the A D converter control register ANCTR1 3 Select the A D converter clock Select the A D converter clock by the ANCK1 flag of the A D converter control register 0 ANCTRO Setup should be such a way that converter clock TAp does not drop less than 500 ns with resonator 4 Setthe sample hold time Set the sample hold time by the ANSH1 ANSHO flag of the A D converter control register O ANCTRO The sample hold time should be based on analog input impedance 2 to 4 are not in order 3 and 4 can be operated simultaneously 5 Set the A D ladder resistance Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 and a current flow through the ladder resistance and A D converter goes into the waiting 6 Select the A D converter activation factor then start A D conversion Set the ANST flag of the A D converter control register 2 ANCTR2 to 1 to start A D converter or set ANSTSELI flag of A D converter control register 2 ANCTR2 to 1 to start A D converter by the external trigger factor
554. read out When the fosc is selected to the count clock source the value of the binary counter may be not read out correctly Do not operate the TMnEN flag and the TMnCK 2 to 0 flag of the TMnMD register at the same time That may lead the mulfunction When the count clock source is changed set the timer interrupt enable 8 bit Timer Count V 31 5 8 bit Timers V 32 5 5 8 bit Event Count 5 5 1 Operation Event count operation has 2 types TMnIO input and synchrocous TMnIO input according to the clock source selection 8 bit Event Count Operation Timers 0 1 2 3 4 and 5 Event count operation means that the binary counter TMnBC counts the input signal from external to the TMnIO pin If the value of the binary counter reaches the setting value of the compare register TMnOC inter rupts can be generated at the next count clock Table 5 5 1 Event Count Input Clock Count Timing of TMnIO Input iTimers 0 1 2 3 4 and 5 When TMnIO input is selected TMnIO is input to the count clock of the timer n The binary counter is started to count up at the falling edge of the TMnIO input signal TMnIO input TMnEN flag Compare register Binary counter Interrupt request flag 8 bit Event Count Figure 5 5 1 Count Timing of TMnIO Input Timers 0 1 2 3 4 and 5 Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Event input TMOIO input T
555. reception set SCOSBIS of the SCOMD1 register to 1 always to select serial input The SBIO pin can be used as a general port This serial interface contains a emergency reset function If the communication should be stopped by force set SCOSBOS and SCOSBIS of the SCOMD 1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 11 2 1 except TXBUFO are set Transfer rate of transfer clock set by the SCOMD3 register should be under 5 0 MHz Operation XI 35 11 Serial interface 0 XI 36 B Transmission Reception Setup Example Standby Mode Reception The setup example for clock synchronous serial communication with serial 0 is shown Table 11 3 13 shows the condition at standby mode reception Table 11 3 13 Setup Examples for Synchronous Serial Interface Transmission Reception Standby Mode Reception Setup item Set to Serial data input pin Independent 2channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Clock Clock slave Operation mode Stop mode Clock source fs 2 Clock source 1 8 dividing Not divided by 8 Used pins A SBTO SBOO pin style Push pull SBTO pin pull up resistor Not added 5800 pin pull up resistor Not
556. register TM7OC an interrupt can be generated at the next count clock Table 6 4 1 Event Count Input Clock Timer 7 Event input TM71O input P16 PD4 Synchronous TM71O input Count Timing of TM7IO Input When TM7IO input is selected TM7IO input signal is input to the timer 7 count clock The binary counter counts up at the falling edge of the TM7IO input signal 7 input signal that passed the divider TM7IO input TM7EN flag Compare EE register1 Binary 0000 0001 ZONE 00004 0001 counter Interrupt ____ O __ request flag Figure 6 4 1 Count Timing TM7IO Input Timer 7 16 bit Event Count VI 17 6 16 bit Timer VI 18 And when the timer stops unexpected data may be read at the binary counter To prevent this use the event count by the synchronous TM7IO input which is shown in the following page a If the binary counter is read out during operation incorrect data at counting up may be read tion Also when the compare register is set to 0x0000 use the event count by the synchro a When the event input TM7IO input is used clear the binary counter before the timer opera nous 7 input as shown below Count Timing of Synchronous TM7IO Input Timer 7 If the synchronous TM71O input is selected the synchronizing circuit output signal is input to the timer 7 count clock The synchronizin
557. register to 1 Then the value of the port A is read to be 1 5 is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as the analog input pin set the port input mode register to 1 Then the value of the port A is read to be 1 is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as the analog input pin set the port input mode register to 1 Then the value of the port A is read to be 1 Port A Chapter 4 I O Ports PA7 15 used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as the analog input pin set the port A input mode register to 1 Then the value of the port A is read to be 1 4 12 2 Registers The following Table shows registers that control the Port A Table 4 12 1 Port A control register Registers Address Function Ox03F1A Port A Output Register 0x03F2A Port A Input Register Port Direction Control Register 0x03F4A Port A Pull up Pull down Resistor Control Register 0x03F3B Port A Input Mode Register 0x03F4B Pull up Pull down Resistor Selection Register R W Readable Writable Port A Output Register PAOUT 0x03F 1A PAOUT7 PAOUT6 5 4 PAOU
558. register to 1 to operate the Timer 7 TM7BC counts up from 0x0000 At the timing of the rising edge of the external interrupt 0 input signal the value of TM7BC is loaded to the TM7IC register At that time the pulse width between rising edge of the external interrupt input signal can be measured by reading the value of the TM7IC register through interrupt service rou tine and calculating the difference between the capture values 16 bit Timer Capture VI 43 6 16 bit Timer VI 44 16 bit Timer Capture Chapter 7 Time Base Timer Free running Timer 7 Time Base Timer Free running Timer 7 1 Overview This LSI has a time base timer and a 8 bit free running timer timer 6 Time base timer is a 15 bit timer counter 7 1 1 Functions Table 7 1 1 shows the clock source and the interrupt generation cycle that timer 6 and time base timer can use Table 7 1 1 Clock Source and Generation Cycle Time base timer Timer 6 8 bit free running 8 bit timer operation x Interrupt TBIRQ TM6IRQ Clock source fosc fosc fx fx fs fosc x 1 212 1 fosc x 1 213 1 fx x 1 212 2 fx x 1 213 2 Interrupt generation cycle fosc 1 27 1 fosc 1 28 4 fosc x 1 29 1 fosc x 1 210 1 fosc 1 219 4 fosc x 1 219 1 1 2 2 fx x 1 28 2 fxx 1 29 2 fx x 1 210 2 1 213 2 1 215 2 The interrupt generation cycle is decided by t
559. request flag before the interrupt acceptance Also select the both edges interrupt before the a The interrupt request flag may be set at switching the interrupt edge So clear the interrupt interrupt acceptance External Interrupts Interrupts Ill 61 Chapter 3 Interrupts The external interrupt pis is recommended to be pull up in advance III 62 External Interrupts 3 3 6 Level Interrupt su I T n Level Interrupt External interrupts 2 3 and 5 Chapter 3 The level interrupt can select the input level H or input level L about the signal which is input from the external interrupt input pin and generate the interrupt at the selected edge It is possible from the standby mode Level Interrupt Example External interrupts 2 3 and 5 External interrupt 2 IRQ2 is generated at the H level of the input signal from P20 The table below shows a setup example of IRQ2 Setup Procedure Description 1 Specify the interrupt valid edge IRQ2ICR 0 03 4 bp5 REDG2 1 2 Specify the interrupt valid input LVLMD 0x03F6D bp1 EXLVL2 1 3 Enable the level interrupt LVLMD 0x03F6D bp7 6 IRQ2LV1 0 10 4 Set the interrupt level IRQ2ICR 0x03FE4 bp7 6 IRQ2LV1 0 10 5 Enable the interrupt IRQ2ICR 0x03FE4 bp1 IRQ2IE 1 1 Set the REDG2 flag of the external interrupt 0 control register IRQ2ICR to 0 and specify the rising edge as the valid edge 2 Set the EXLVL flag of the
560. resistor control pq POPLUT T ic WEK R Reset I O direction control PODIR1 gt WC R 259 Port output data PXEON D o Schmitt trigger input Port input data lt POIN1 Serial 0 UART 0 reception data input Figure 4 2 2 P01 Block Diagram IV 10 Port 0 Chapter 4 I O Ports Reset Nch open drain control 2 WEK R Y s POPLU2 Pull up resistor control Rq gt gt WEK R Reset I O direction control b PODIR2 m Wek R B P02 Port output data qQPOOUT2 orm 4 5 WEK R y 777 Schmitt trigger input i POIN2 Port input data 1 lt 7 J R Serial 0 clock input Serial 0 clock output SCOMD1 SCOSBTS Figure 4 2 3 P02 Block Diagram Nch open drain control Pull up resistor control direction control Port output data Schmitt trigger input Port input data Serial 2 11 2 reception data input Serial 2 11 2 transmission data output SC2MD1 SC2SBOS Figure 4 2 4 Block Diagram Port 0 IV 11 4 I O Ports r Reset POPLU4 Pull up resistor control gt WEK R Reset direction control PODIR4 x yr gt P04 Port output data z x POOUT4 WEK R Schmitt trigger
561. restoring the contents of any registers saved to the stack during processing by the POP instruction and other means and the RTI instruction restores the program to the point at execution was inter rupted The following is the processing sequence invoked by the RTI instruction 1 The contents of the PSW are restored from the stack SP 2 The contents of the program counter PC i e then return address are restored from the stack SP 1 to SP 3 3 The contents of the handy address register HA restored from the stack SP 4 SP 5 4 The stack pointer is updated SP 6 SP 5 Execution branches program to the address in the program counter The handy address register is an internal register used by the handy addressing function The hardware saves its contents to the stack to prevent the interrupt from interfering with operation of the function Registers such as data register or address register are not saved so that PUSH instruction Y from program should be used to save them onto stack if necessary The address bp6 to bp4 when program counter PC19 16 H are saved to the stack are Y reserved Do not change it by program Overview Chapter 3 Interrupts Maskable Interrupt Figure 3 1 6 shows the processing flow when a second interrupt with a lower priority level xxxLV1 xxxLV0 107 arrives during the processing of the with a higher priority level xxxLV1 xxxLV0 00
562. rol Register ATC1ICR The 1 interrupt control register ATC1ICR controls interrupt level of ATC1 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 28 ATC1 Interrupt Control Register ATC1ICR 0x03FFB bp 7 6 1 0 Flag ATCLV1 ATCLVO ATCIE ATCIR At reset 0 0 0 0 Access R W Description ATCLV1 Interrupt level flag ATCLVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Ill 45 Chapter 3 Interrupts 3 3 External Interrupts There are 6 external interrupts in this LSI The circuit external interrupt interface operates the external interrupt input signal is built in between the external interrupt input pin and the external interrupt block This external interrupt interface can manage to do with any kind of external interrupts 3 3 1 h n rm v Table 3 3 1 shows the list of functions which external interrupts 0 to 5 are used Overview Table 3 3 1 External Interrupt Functions External Programmab Both edges Noise filter AC zero Key input interrupt le active interrupt built in cross inte
563. rom F to At LSB first data are stored to the upper bits of RXBUFO When there are 6 bits to be transferred as shown on Figure 11 3 5 if data A to F are stored to bp2 to bp7 of RXBUF0 the transmission is operated from to F RXBUFO AE PEE Figure 11 3 4 Receive Bit Count and Transfer First Bit starting with MSB bit RXBUFO F E Figure 11 3 5 Receive Bit Count and Transfer First Bit starting with LSB bit When the serial transfer bit is set between 1 to 7 the data except for received data of the specified transfer bit count is unknown Use the received data after being masked by AND OR instruction XI 16 Operation 11 Serial interface 0 Continuous Mode This serial has a function for continuous communication If data is set to the transmission data buffer TXBUF0 during communication the transmission buffer empty flag SCOTEMP is automatically set to interrupt SCOTIRQ is generated after the former data is set Data setup to TXBUFO should be done till the communication complete interrupt SCOTIRQ is generated after the data is loaded to the internal shift register At master communication there is output after the pension of communication for 4 transfer clocks till the next transmission clock is output after the SCOTIRQ generation Automatic Continuous Transfer This serial enables the start up by the data automat
564. rom the stop mode to the normal mode after the oscillation stabilization wait Note Each procedure 1 to 2 5 to 8 9 to 11 can be set at the same time The slave reception at the standby mode should be used without the start condition to Y receive properly be operated after all control registers refer to Table 12 2 1 except TXBUF1 are set 1 Each flag should be set as this setup procedure in order Activation of communication should LI Operation XII 37 12 Serial interface 1 12 3 8 UART Serial Interface E 3 serial 1 can be used for full duplex UART communication Table 12 3 14 shows UART serial interface functions Table 12 3 14 URAT Serial Interface Functions Communication style UART full duplex Interrupt SC1TIRQ transmission SC1RIRQ reception Used pins TXD1 output input RXD1 input Specification the first transfer bit MSB LSB Selection of parity bit Parity bit control 0 parity 1 parity odd parity even parity Frame selection 7 bits 1 STOP 7 bits 2 STOP 8 bits 1 STOP 8 bits 2 STOP Continuous operation O Maximum transfer rate 300 kbps standard 300 bps to 38 4 kbps with baud rate timer XII 38 Operation 12 Serial interface 1 Activation Factor for Communication At transmission if any data is set to the transmission data buffer
565. rrection address setting register and the RC vector table Step 3 Enable the ROM correction operation lt Main Program Figure 2 3 2 Initial Routine for ROM Correction 34 ROM Correction Chapter 2 CPU Basics ROM Correction Setup Example The setup procedure with ROM correction to correct 2 parts of the program is shown below For the step to exe cute the ROM correction refer to figure 2 3 2 Initial Routine for ROM correction on the previous page STEP 1 Develop the correct program of the external EEPROM to RAM area External EEPROM Address Data 0000 03 Program management version 0001 19 0002 09 Setvalue to the ROM correction address 0 setting register 0003 01 RCOAP PEDE E The head address of the development first correct program 0006 FD 0007 08 Setvalue to the ROM correction address 1 setting register Internal RAM 0008 01 RC1AP Address Data GO a The head address of the development second correct program 0684 0008 0 06 5 00 000G 00 06B6 85 000D 85 06B7 93 000E 93 The first correct program instruction code 06B8 C2 000F C2 06B9 91 0010 91 LY devel lt lt of FO 06 0012 FF Forhalf byte instruction adjustment 06BC 0013 need to the real ROM 06BD 14 0014 14 06BE 85 0015 85 06BF 93 0016 93 The second correct program instruction code 06C0 02 0017 02 06C
566. rrupt input pin edge detection External P20 O O interrupt 0 External P21 O O interrupt 1 External P22 O O O interrupt 2 External P23 interrupt 3 External P24 interrupt 4 External P25 interrupt 5 pulse which is shorter than the system clock cycle is neglected 1 Because the external interrupt event acknowledged by the rising of the system clock the external interrupt event from the pin because all synchronous circuits are inserted 1 System clock x 2 for the interrupt factor generation is needed at the maximum against the III 46 External Interrupts 3 Interrupts Block Diagram 3 3 2 B External Interrupt 0 Interface Block Diagram LAOS LAN OXOSLJN masa ECHE 81008 ol 0 LL 0198 X EXT 2 6 uono l p yore 1 ejep 25 ee 1s nb u 0Otii pe DUISIH uonoejep Se X jeubls Figure 3 3 1 External Interrupt 0 Interface Block Diagram Ill 47 External Interrupts Chapter 3 Interrupts B External Interrupt 1 Interface Block Diagram JejsueJ ejep 1senbai
567. rrupt source TM1IRQ operation Event count O TMOIO input TM2IO input TM4IO input PWM output Synchronous output Pulse width measurement Clock source fosc fosc fosc fosc 4 fosc 4 fosc 4 fosc 16 fosc 16 fosc 16 fosc 32 fosc 32 fosc 32 fosc 64 fosc 64 fosc 64 fs 2 fs 2 fs 2 fs 4 fs 4 fs 4 synchronous fx synchronous fx synchronous fx synchronous synchronous synchronous TMOIO input TM2IO input TM4IO input fosc Machine clock High frequency oscillation fx Machine clock Low frequency oscillation fs System clock Chapter 2 2 5 Clock Switching At cascade connection the binary counter and the compare register are operated as a 16 bit register At oper ation set the TMnEN flag of the upper and lower 8 bit timers to 1 to be operated Also select the clock source by the lower 8 bit timer Other setup and count timing is the same to the 8 bit timer at independently operation Cascade Connection 5 8 bit Timers When timer 0 and timer 1 are used in cascade connection timer 1 is used as an interrupt request flag Timer pulse output of timer 0 is L fixed output An interrupt request of timer 0 is not generated but the timer 0 interrupt should be disabled When timer 2 and timer 3 are used in cascade connection timer 3 is used as an interrupt request flag Timer pulse output of timer 2 is L fixed output An interrupt reque
568. rrupts a 0 disables all maskable interrupts regardless of the interrupt mask level IM1 IMO setting in PSW This flag is not changed by interrupts B Bank disable Bank disable flag BKD enables disables bank addressing of 64 KB unit When this flag is set to 0 bank addressing is enabled and you can access to total 16 banks by setting the bank register value When this flag is set to 1 bank addressing is disabled and the only area you can access is the first 64 KB On an interrupt generation BKD flag is automatically set to 1 and bank addressing is disabled At returning from interrupt service routine the value of BKD flag is returned to the previous one before the interrupt generation To enable bank addressing in an interrupt service routine reset the BKD flag to 0 before Y access to data Overview Il 11 2 CPU Basics Il 12 2 1 8 Address Space The address space of this LSI is 1 MB max The instruction and data areas are not separated The instruction area can be used as linear address space The data area needs bank spscification in every 64 KB The inicial value is first 64 KB space The data described in this section includes RAM data and ROM table data The data area consists of an area of 256 bytes that supports efficient access with RAM short addressing and an area of 256 bytes that supports efficient access with I O short addressing The memory co
569. rt 0 Nch open drain control register POODC P06 is used as the D A output pin of the DAO as well With the D A control register DACTR P06 is used as the D A output pin of the DAO during D A conversion it is used as a general purpose port for other times When the pin is used as the D A conversion 1 is read out from the port 0 input register POIN Port 0 Chapter 4 I O Ports 4 2 2 Registers The following Table shows registers that control the Port 0 Table 4 2 1 Port 0control register POOUT 0 03 10 Port 0 Output Register IV 7 POIN 0x03F20 Port 0 Input Register IV 8 PODIR 0x03F30 R W Port 0 Direction Control Register IV 8 POPLU 0x03F40 R W Port 0 Pull up Resistor Control Register IV 9 P0ODG 0x03F1C R W Port 0 Nch Open drain Control Register IV 9 R W Readable Writable Port 0 Output Register POOUT 0x03F 10 p p F E p p p TIT pan At reset Access R W R W R W R W R W R W R W bp Flag Description POOUT6 POOUTS POOUT4 POOUTS POOUT2 POOUT1 POOUTO Output data 0 Output L VSS level 1 Output H VDD level O S O Q O Port 0 7 4 I O Ports Port 0 Input Register POIN 0x03F20 bp Flag Description 7 6 6 don Input data 0 Pin is L VSS level 3 PONS 1 Pin is H VDD level 2 POIN2 PIR Hu DD level 1 POIN1 0 POINO Port 0 Direction Control Register PODIR 0x03F30
570. rt 0 direction control register POPLU 0x03F40 Port 0 pull up control register P9ODC 0x03F4C Port 9 Nch open drain control register P9DIR 0x03F39 R W Port 9 direction control register IV 91 P9PLU OxOSF49 R W Port 9 pull up control register IV 92 SCORICR Ox03FF2 R W Serial 0 UART reception interrupt control register III 38 SCOTICR Ox03FF3 R W Serial 0 UART transmission interrupt control register 39 R W Readable Writable R Readable only Control Registers XI 11 Serial interface 0 11 22 Data Buffer Registers G 2 Serial interface 0 has each 8 bit data buffer register for transmission and for reception Serial interface 0 Received Data Buffer 0 03 94 7 6 5 4 3 2 1 0 RXBUFO7 RXBUFO6 RXBUFOS RXBUF04 RXBUFO3 RXBUF02 RXBUFO1 RXBUFOO X X X X X X X X Access Serial interface 0 Transmission Data Buffer TXBUF0 0x03F95 7 6 5 4 3 2 1 0 TXBUF07 TXBUFO6 TXBUF05 04 TXBUFO3 TXBUFO2 TXBUF01 TXBUFOO X X X X X X X X Xl 6 Control Registers 11 Serial interface 0 11 23 Mode Registers Serial interface 0 Mode Register 0 SC0MD0 0x03F8F bp 7 4 3 2 1 0 Flag SCOCE1 SCODIR SCOSTE SCOLNG2 SCOLNG1 SCOLNGO Reset 0 0 0 1 1 1 Ac
571. rter 10 bits x8 channel D A converter 8 bits x1 channel Serial interface 5 types Serial 0 Full duplex UART Synchronous serial interface Synchronous serial interface Transfer clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 2 Timer 4 output MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected Sequence transmission reception or both are available Full duplex UART Baud rate timer timer 2 or timer 4 Parity check Overrun error Framing error detection Transfer size 7 to 8 bits can be selected In UART communication transmission complete interrupt and reception complete interrupt are available Serial 1 Full duplex UART Synchronous serial interface Synchronous serial interface Transfer clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 4 Timer 5 output Hardware Functions 1 7 1 Overview MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected Sequence transmission reception or both are available Full duplex UART Baud rate timer timer 4 or timer 5 Parity check Overrun error Framing error detection Transfer size 7 to 8 bits can be selected In UART communication transmission complete interrupt and reception complete interrupt are available Serial 2 Single master Synchronous serial interface Synchronous seria
572. rupt RTI instruction to return to the point at which execution was interrupted Interrupt service routine Main program Interrupt request flag cleared at head IN Hardware processing Save up PC PSW etc Interrupt generation Max 12 machine cycles 11 machine cycles Restart Restore PSW PC up etc RTI Figure 3 1 2 Interrupt Processing Sequence maskable interrupts Overview 5 Chapter 3 Interrupts Interrupt Group and Vector Addresses Table 3 1 2 shows the list of interrupt vector addresses and interrupt group Table 3 1 2 Interrupt Vector Addresses and Interrupt Group Vector Vector Interrupt group interrupt factor Control register address number addresses 0 0x04000 Reset 5 1 0x04004 Non maskable interrupt NMI NMICR 0x03FE1 2 0x04008 External interrupt 0 IRQ0 IRQ0ICR 0x03FE2 3 0 0400 External interrupt 1 IRQ1 IRQ1ICR 0x03FE3 4 0x04010 External interrupt 2 IRQ2 IRQ2ICR 0x03FE4 5 0x04014 External interrupt 3 IRQ3 IRQ3ICR 0x03FE5 6 0x04018 External interrupt 4 IRQ4 IRQ4ICR 0x03FE6 7 0 0401 External interrupt 5 IRQ5 IRQ5ICR 0x03FE7 8 0x04020 Timer 0 interrupt TM0IRQ TM0ICR 0x03FE8 9 0x04024 Timer 1 interrupt TM1IRQ TM1ICR 0x03FE9 10 0x04028 Timer 2 interrupt TM2IRQ TM2ICR OxO3FEA 11 0x0402C Timer 3 interrupt 0x03FEB 12 0x0
573. rupt O control register 20 ee NFCTR OxOSF2E R W Noise filter control register 55 PSCMD 0x03F6F R W Prescaler control register 11 54 External inter IRQ1ICR R W External interrupt 1 control register 1 21 Ox03F2E R W Noise filter control register 55 PSCMD 0x03F6F R W Prescaler control register III 54 External inter IRQ2ICR 0 03 4 R W External interrupt 2 control register III 22 7 EDGDT OxOSF1E R W Both edges interrupt control register 56 IRQSEL 0x03F4E R W External interrupt pin switching control 11 58 register LVLMD 0x03F6D R W External interrupt valid input switching 111 59 control register External IRQ3ICR OxOSFE5 R W External interrupt control register III 23 EDGDT OxOSF1E R W Both edges interrupt control register 56 IRQSEL 0x03F4E R W External interrupt pin switching control 11 58 register LVLMD 0x03F6D R W External interrupt valid input switching 111 59 control register External inter IRQ4ICR 0x03FE6 R W External interrupt 4 control register 11 24 1IMD OxOSFSE R W Key interrupt control register III 57 External inter IRQ5ICR OxOSFE7 R W External interrupt 5 control register III 31 mpra EDGDT OxOSF1E R W Both edges interrupt control register 56 LVLMD OxOSF6D R W External interrupt valid input switching 111 59 control register External Interrupts 53 Chapter 3 In
574. s IIC single master external clock timer 2 output timer 3 output Interrupt SC2IRQ SC2IRQ Pins SBO2 SBI2 SBT2 SDA2 SCL2 3 channels type 2 channels type O SBO2 SBT2 Transfer bit count 1 to 8 bit 1 to 8 bit Start condition First transfer bit Input edge Output edge 5802 output control after transfer of H L last data hold last data Function in STANDBY mode Slave reception only ACK bit ACK bit level Continuous operation with ATC1 Clock sources fosc 2 fosc 2 fosc 4 fosc 4 fosc 16 fosc 16 fosc 32 fosc 32 fs 2 fs 2 fs 4 fs 4 timer 2 output timer 3 output Maximum transfer rate 5 0 MHz NORMAL mode 100 kHz High speed mode 400 kHz fs system clock fosc machine clock for high speed ocillation In IIC communication transfer clock is obtained by dividing the clock source by 8 Overview 13 Serial Interface 2 Transfer rate should be set slower than system clock fs Overview XIII 3 13 Serial Interface 2 13 1 2 Block Diagram Serial Interface 2 Block Diagram AS8DII 21621 Od1SOII 1205 SMOVZOS 0 OMOVZOS YLOZOS ASS2OS 129298 16205 2931295 L NIZOS OON IcOS OGINZOS INOIZOS 5185205 SIHScOS 5085205 15 0295
575. s 0 2 and 4 V 42 8 bit PWM Output 5 7 2 Setup Example B PWM Output Setup Example Timers 0 2 and 4 The 1 4 duty cycle PWM output waveform is output from the TMOIO output pin at 19 53 kHz by using the timer 0 Fs 2 oscillates at 5 MHz Cycle period of PWM output waveform is decided by the overflow of the binary counter H period of the PWM output waveform is decided by the setting value of the compare register An example setup procedure with a description of each step is shown below TMOIO output 19 58 Hz lt Figure 5 7 4 Output Waveform of TM0IO Output Pin Setup Procedure Description 1 Stop the counter TM0MD 0x03F54 bp3 TMOEN 0 2 Set the special function pin to the output mode P1OMD 0x03F2B bp0 P1OMDO 1 P1DIR 0x03F31 bp0 P1DIR0 1 3 Select the PWM operation TM0MD 0x03F54 bp4 1 bp5 TM0MOD 0 bp6 0 4 Select the count clock source TM0MD 0x03F54 bp2 0 TM0CK2 0 001 5 Select and enable the prescaler output CK0MD 0x03F56 bp2 1 TMOPSC1 0 X0 TMOBAS 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the timer 0 counting 2 Set the P1OMDO flag of the port 1 output mode register P1OMD to 1 to set P10 pin to the special function pin Set the TMOMOD flag of the port 1 direction control register P1DIR to 1 to set the output mode Chapter 4 Port Function
576. s LSI manual describes the standard specification Machine cycle system clock fs is described based on the standard mode 1 2 of high oscillation at NORMAL mode or on the clock frequency 1 2 of low oscillation at SLOW mode Please ask our sales offices for the prod uct specifications Contents Structure CMOS integrated circuit Application General purpose Function CMOS 8 bit single chip micro controller 20 Electrical Characteristics 1 5 1 Absolute Maximum Ratings Chapter 1 Overview Parameter Symbol Rating Unit 1 Power supply voltage Vpp1 2 0 3 to 4 6 V 2 Vpp3 0 3 to 7 0 3 Input pin voltage 0 3 to Vpp1 2 0 3 4 0 3 to Vppi 2 0 3 V I O pin voltage 5 Vio2 0 3 to Vpp3 0 3 6 P8 peak 40 Other 7 Peak output current than P8 loi peak 20 peak 10 mA 9 P8 lou avg 30 Average output cur Other 10 rent 1 than P8 lota ava 13 11 lop avg 5 12 Power dissipation Pp 400 mW 13 Operation ambient tempera Tos 40 to 85 ture 14 Storage temperature Tstg 55 to 125 1 Applied to any 100 ms period 2 Connect at least one bypass capacitor of 0 1 or larger between the power supply pin and the ground for latch up prevention 3 The absolute maximum ratings the tolerance for the LSI to be operated properly Electrical Characteristics
577. s a n S PERENNI RE a XIII 5 13 2 2 Data Buffer eese e d HR eb ey XIII 6 13 2 3 Data E AG IRSE RSLS uper XIII 6 13 2 4 Serial interface 2 Mode Register XIII 7 13 3 Operation reato ree eT eet edes eue ete tide ite dts XIII 14 13 3 1 Clock Synchronous Serial Interface sess XIII 14 13 32 Setup Example odo eR ea aep E iet XIII 30 13 3 3 Single Master Serial Interface rennen XIII 36 13 3 4 Setup Example serae pn s edi SASS E eue XIII 46 Chapter 14 Serial Interface 9 esset eec e testet desdu Y eer ae e Re b EY usec Goede XIV 1 T4 T OVervie Ws iR EUR EE Od aH XIV 2 Functions RR teca et e Ete et e reat XIV 2 14 1 2 Block Di grain reet Da is XIV 4 14 2 Control Registers zu oe e e e e eet XIV 5 14 2 T Registers List iier ee Ge REA itp dese eet S Ie sss XIV 5 14 2 2 Data Buffer Register eot eene ome eet opere edet XIV 6 14 2 3 ipei PIER Sis Sin hae d Rd XIV 6 14 2 4 Serial interface 3 Mode Register sese een nre XIV 7 14 3 eee te Dente EOD dorem pP I Ie XIV 14 Contents 9 gt 14 3 1 Clock Synchronous Serial Interface XIV 14 14 3 2 Setup Example a ee eet eene entere ie rises XIV 32 14 3 3 Single Master Seri
578. s for only master transmission and master reception in IIC communication Sequence of communication is shown below The shaded part shows the data transferred from slave Start Stop condition Slave address R W ACK Data ACK condition Start no Stop condition Slave address R W ACK Data ACK condition Start Stop condition Data ACK condition Figure 14 3 20 Communication Sequence on Each Transfer Format Figure 14 3 21 Master Transmission Timing Figure 14 3 22 Master Reception Timing Clock Setup The transfer clock for communication is obtained by dividing clock source by 8 inside this serial The clock source is selected from the dedicated prescaler timer 3 or 5 output by the SC3MD3 register The clock source should be set in such a way that the transfer rate is under 100 kHz in NORMAL mode 400 kHz in high speed mode with the SC3MD3 register The dedicated prescaler starts as this register selects prescaler operation Set the SC3MST flag of the SC3MDI register to 1 to select the internal clock clock master This interface can not be used with external clock clock slave Table 14 3 14 1 Serial Interface Clock Sources Single master IIC Clcok source fosc 2 internal clock fosc 4 fosc 16 fosc 32 fs 2 15 4 timer 3 output timer 5 output Operation XIV 41 14 S
579. s not cleared till the next communication complete interrupt SCATIRQ is generated after loading data of the RXBUF4 SC4ERE is cleared as SCAORE flag is cleared These error flags have no effect on communication operation Reception BUSY Flag If the data is set to the TXBUF4 or recognized the start condition when the SC4SBIS flag of the SCAMDI register is set to serial data input the BUSY flag SCARBSY of the SCASTR register is set to 1 And on the genera tion of the communication complete interrupt SCATIRQ the flag is cleared to 0 And during continuous com munication the SCARBSY flag is always set If the transmission buffer empty flag SCATEMP is cleared to 0 as the communication complete interrupt SCATIRQ is generated SCARBSY is cleared to 0 If the SCASBIS flag is set to 0 during communication the SCARBSY flag is cleared to 0 Operation 15 Serial interface 4 B Transmission BUSY Flag Data is set to the TXBUF4 or recognized the start condition when the SCASBOS flag of the SCAMDI register is set to serial data output if the SCASBOS flag of the SCAMDI register is 1 SCATBSY flag of the SCASTR register is set And on the generation of the communication complete interrupt SCATIRQ the flag is cleared 0 And during continuous communication the SCATBSY flag is always set If the transmission buffer empty flag SC4TEMP is cleared to 0 as the communication complete interrupt SC4TIRQ is generated SCATBS
580. s register set the head address which instructions to be corrected are stored to Once the instruction execution address reaches to the set value to this register program counter branches indirectly to the set address to the RC vector table RCnV L RCnV H When the ROM correction should be valid set the RCnEN flag of the ROM correction control register RCCTR after setting the address to this register 30 ROM Correction Chapter 2 CPU Basics ROM Correction Address 0 Setting Register RCOAP Table 2 3 2 ROM Correction Address 0 Setting Register lower 8 bits RCOAPL 0x03FC0 bp 7 6 5 4 3 2 1 0 Flag RCOAPL7 RCOAPL6 5 RCOAPL4 RCOAPL3 RCOAPL2 RCOAPL1 RCOAPLO Atreset 0 0 0 0 0 0 0 0 Access R W Table 2 3 3 ROM Correction Address 0 Setting Register middle 8 bits RCOAPM 0x03FC1 bp 7 6 5 4 3 2 1 0 Flag RCOAPM7 RCOAPM6 5 RCOAPM4 RCOAPM3 RCOAPM2 RCOAPM1 RCOAPMO Atreset 0 0 0 0 0 0 0 0 Access R W Table 2 3 4 ROM Correction Address 0 Setting Register upper 2 bits RCOAPH 0x03FC2 bp 7 6 5 4 3 2 1 0 Flag 2 E B RCOAPH2 RCOAPH1 RCOAPHO Atreset 0 0 0 0 Access R W ROM Correction Address 1 Setting Register Table 2 3 5 RO
581. s set to 0 the received data is stored in the falling edge of the clock Data I O Pin Setup The SDA2 pin used as SBO2 pin too is used to input output data Set the SC2IOM flag of SC2MD1 register to 1 to input serial data from the 5802 pin As the 5812 pin is not used at that time it can be used as a general port But always set the SC2SBIS flag of the above register to 1 to set input serial data To detect start condition set the SC2SBIS flag of the SC2MD1 register to input serial data regardless of transmission reception Operation XIII 37 13 Serial Interface 2 Reception of Confirming Bit after Data Transmission The SC2ACKS flag of the SC2CTR register selects if ACK bit is enabled or not If bit is enabled bit 15 received from the slave station after data 1 to 8 bits is transferred At reception of bit the SDA2 line is automatically released To receive ACK bit 1 clock is output to store ACK bit to the SC2ACKO of the SC2CTR register The transmission reception shift register SC2TRB is not operated by the ACK bit reception clock When the received ACK bit level is L the reception is normal at slave and the next data can be received If the level is H the reception maybe completed at slave so set the IICSTPC flag of the SC2CTR register to 0 to end com munication Data transmission Bus release period Interrupt Figure 13 3
582. s the conditions Table 13 3 12 Conditions for Synchronous Serial Interface at transmission reception reception in STANDBY mode Item set to Serial data input pin SBl2 SBO2 Connection 2 channels Transfer bit count 8 bit Start condition Disabled First bit to be transfered MSB Input clock edge Falling Clock Clock slave Operation mode STOP mode Clock source fs 2 SBT2 SB02 pin type Push pull SBT2 pull up resistor Not added SBI2 pull up resistor Not added Serial interface 2 communication end interrupt Enabled An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation SC2MDS 0 03 98 bp3 SC2PSCE 1 2 Select the clock source SC2MD3 0x03F 98 bp2 0 SC2PSC2 0 100 3 Control of pin type POODC 0x03F1C bp7 POODC5 0 bp5 POODC3 0 POPLU 0x03F40 bp7 POPLU5 0 bp3 POPLU3 0 4 Control of pin direction PODIR 0x03F30 PODIR5 0 bp5 PODIR3 20 1 Set the SC2PSCE flag of the SC2MD3 register to 1 to select prescaler operation 2 Set the SC2PSC2 0 flag of the SC2MD3 register to 100 to select fs 2 for clock source 3 Set the POODC5 POODCS flags of the POODC register to 0 0 to select push pull for the SBO2 SBT2 pin type Set the POPLU5 POPLUS flags of the POPLU register to 0 0 not
583. s the value loaded from a binary counter by a capture trigger cap ture trigger is generated by an input signal from an external interrupt pin and when an arbitrary value is written to an input capture register Directly writing to the register by program is disabled B Timer 7 Input Capture Register Lower 8 bits TM7ICL 0x03F76 Flag TM7ICL7 TM7ICL6 TM7ICL5 TM7ICL4 TM7ICL3 TM7ICL2 TM7ICL1 TM7ICLO At reset X X X X X X X X Access R R R R R Timer 7 Input Capture Register Upper 8 bits TM7ICH Ox3F77 TM7ICH7 TM7ICH6 TM71CH5 TM7ICH4 TM7ICH3 R TM7ICH2 R TM7ICH1 R TM7ICHO X X X X X X X X R R R R R R R Control Registers VI R N 6 16 bit Timer 6 2 3 Timer Mode Registers k Fr s acshscx lt s lt s I This is a readable writable register that controls timer 7 Timer 7 Mode Register 1 TM7MD1 0x03F78 bp 7 6 5 4 3 2 1 0 Flag Reserved T ICEDG TM7CL TM7EN TM7PS1 TM7PSO TM7CK1 TM7CKO 1 At reset 0 0 1 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description Reserved Set always 0 T7ICEDG Capture trigger edge selection 1 0 Falling edge 1 Rising edge Timer output reset signal 0 Operate timer output 1 Disable timer output Timer 7 c
584. s to be transferred as shown on figure Figure 15 3 4 if data A to F are stored to bp0 to bp5 of RXBUF4 the transmission is operated from F to A At LSB first data are stored to the upper bits of RXBUF4 When there are 6 bits to be transferred as shown on Figure 15 3 5 if data A to F are stored to bp2 to bp7 of RXBUF4 the transmission is operated from A to F RXBUFO Figure 15 3 4 Receive Bit Count Transfer First Bit starting with MSB bit RXBUF0 Ani C Figure 15 3 5 Receive Bit Count and Transfer First Bit starting with LSB bit When the serial transfer bit is set between 1 to 7 the data except for received data of the specified transfer bit count is unknown Use the received data after being masked by AND OR instruction Operation XV 15 15 Serial interface 4 XV 16 Continuous Mode This serial has a function for continuous communication If data is set to the transmission data buffer TXBUF4 during communication the transmission buffer empty flag SCATEMP is automatically set to interrupt SCATIRQ is generated after the former data is set Data setup to TXBUF4 should be done till the communication complete interrupt SCATIRQ is generated after the data is loaded to the internal shift register At master communication there is output after the pension of communication for 4 transfer clocks till the next transmission c
585. s18 label JSR abs18 label Dn Dm 8 Dm ADDC Dn Dm BSET abs16 bp BCLR abs16 bp BTST abs16 bp emp 8 abs16 mov 8 86516 UVP abs20lbe ISR ebs2ebe CBEQ 8 abs16 d7 11 CBNE 8 abs16 d7 11 TBZ abs16 bp d7 TBZ abs16 bp d11 TBNZ abs16 bp d7 TBNZ abs16 bp d11 Ver2 1 2001 03 26 Instruction Map Chapter 19 Appendix XIX 9 Record of Changes MN101E01L LSI Users Manual Record of Changes Ver 0 65 to Ver 0 7 Page Section i Previous Edition Ver 0 65 New Edition Ver 0 7 1 35 Figure Change L 7 9 Power Voltage __ Power Voltage 5V voltage 2 4 Power Voltage internal voltage 779 Reset Input Voltage Reset pins Ed Reset pins Reset Input Voltage Low Level gt 277 Low Level gt Under Input Voltage xe d Under Input Voltage 0 Es Time Time d x Enough time is necessary to recognize as reset Enough time is necessary to recognize as reset 11 5 Table Change Page Page No 2 1 3 CPUM 11 44 Il 49 CPUM 11 51 MEMCTR 11 37 MEMCTR 1 38 RCCTR 1 29 11 30 SBNKR 11 18 SBNKR 11 19 DBNKR 1 19 11 20 RCnAP 11 30 11 32 RCnAP 11 31 to 32 11 53 Table Change Page No Page No 3 3 2 111
586. set Input Voltage After power supply is on reset pin voltage should be low for sufficient time before rising in order to be recog nized as a reset signal Refer to Chapter 2 2 7 1 Reset Operation Power Voltage 5V I O voltage Power Voltage internal voltage Reset pins Reset Input Voltage Low Level Under Input Voltage Enough time is necessary to recognize as reset Figure 1 7 5 Power Supply and Reset Input Voltage 1 34 Cautions for Circuit Setup 1 Overview 1 7 4 Power Supply Circuit A M Cautions for Setting Circuit with Vpp The MOS logic such a microcomputer is high speed and high density So the power circuit should be designed taking into consideration of AC line noise ripple caused by LED driver Figure 1 7 6 shows an example for a circuit with Vpp Emitter follower type B An Example for a Circuit with Vpp Emitter follower type Set condensors for noise filter near microcomputer power pins VDD Microcomputer Vss For Noise filter Figure 1 7 6 An Example for a Circuit of Supply Emitter follower type Cautions for Circuit Setup 1 35 1 Overview 1 36 Cautions for Circuit Setup Chapter 2 CPU Basics 2 CPU Basics 2 2 1 Overview The MN101E CPU has a flexible and optimized
587. set value of the compare register and the clock source selection When the binary counter TM6BC reaches the set value of the com pare register an interrupt request is generated at the next count clock and the binary counter is cleared to restart count up from 0x00 Table 7 3 1 shows selectable clock source Table 7 3 1 Clock Source at Timer Operation Timer 6 Clock source One count time At fosc 20 MHz At fosc 8 39 MHz At fosc 2 MHz fosc 50 ns 119 2 ns 500 ns fx 30 5 us fs 100 ns 238 4 ns 1000 ns fosc x 1 212 204 8 us 488 2us 2048 us fosc x 1 213 409 6 us 976 4 us 4096 us fx x 1 212 125 ms fx x 1 213 250 ms fosc 20 MHz 8 39 MHz 2 MHz fx 32 768 KHz fs fosc 2 8 bit Free running Timer VII 9 7 Time Base Timer Free running Timer 8 bit Free running Timer as a 1 Minute timer a 1 Second timer Table 7 3 2 shows the clock source selection and the register setup when a 8 bit free running timer is used as a 1 minute timer a 1 second timer Table 7 3 2 1 Minute timer 1 Second timer Timer 6 Setup interpr Generaian Clock source TM60CE Register Cycle 1 min fx x 1 213 OxEF 1s fx x 1 213 0x03 fx 2 32 768 kHz When the 1 minute timer 1 m is set on Table 7 3 2 the bp2 waveform frequency cycle of the TM6BC register is 1 Hz 1 s So that can be used for adjusting the seconds TM6BC JLILILILI
588. sfer clock I O Transfer clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBIS Type Push pull N ch Push pull N ch open drain open drain P30DC P30DC5 Input mode Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR5 P9DIR P9DIR3 P9DIR P9DIR5 Pull up added not added added not added P3PLU P3PLU5 P PLU P9PLU5 Operation XIV 31 14 Serial Interface 3 14 3 2 Setup Example B Transmission Reception Setup Example Here is the setup example at transmission reception with serial interface 3 Table 14 3 11 shows the conditions Table 14 3 11 Conditions for Synchronous Serial Interface at transmission reception Item set to SBI3 SBO2 pin selection Independent 3 channels Transfer bit count 8 bits Start condition Disabled First bit to be transferred MSB Input clock edge Falling Output clock edge Rising Clock Clock master Clock source fs 2 Used pins selection A port 3 SBT3 SB02 pin type N ch open drain interrupt SBT3 pull up resistor Added SB02 pull up resistor Added Serial interface 3 communication end Enabled An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation SC3MD3 0x03FA6 bp3 SC3PSCE 1 2 Select the clock source SC3MD3 0x03FA6 bp2 0 SC3PSC2 0 100 3 Select the used pins SCSEL 0x03
589. sion Timing Rising edge Start condition is disabled XIV 22 Operation 14 Serial Interface 3 B Reception Timing Clock SBT3 pin Input data 583 pin Transfer bit counter SC3BSY Interrupt SC3IRQ Figure 14 3 10 Reception Timing Rising edge Start condition is enabled at master Tmax 3 5T T 2 I Clock SBT3 pin Input data SBI3 pin Transfer bit counter SC3BSY Write data to Interrupt SC3IRQ Figure 14 3 11 Reception Timing Rising edge Start condition is disabled Operation XIV 23 14 Serial Interface 3 Clock SBT3 pin Input data SBI3 pin Transfer bit counter SC3BSY Interrupt SC3sIRQ Figure 14 3 12 Reception Timing Falling edge Start condition is enabled at master Tmax 3 5T H Clock 5 pin Input data pin Transfer bit counter SC3BSY Write data to TXBUF3 Interrupt SC3IRQ Figure 14 3 13 Reception Timing Falling edge Start condition is disabled XIV 24 Operation 14 Serial Interface 3 B Transmission Reception To operate transmission and reception at the same time set the SC3CEI flag of the SC3MDO register to 0 or 1 As data is recieved at the opposite edge of the transmission clock set the polarity of reception data input edge to opposite polarity of the transmission data output edge On the
590. sion and reception data at stored in an alternative pat tern In transfer mode 8 ATC1 executes a data byte transfer twice each time it is activated The value in memory pointer 0 increments by one everytime a byte length data transfer ends As a result the source address for the next 1 operation is two addresses higher than that for the previous operation Set the data transfer count for 1 in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime is activated after one byte of data is transferred twice When it reaches 0x00 an interrupt occurs and the automatic transfer ends XVIII 26 Operation 18 Automatic Transfer Controller 18 3 14 Transfer Mode 9 In transfer mode 9 ATC1 automatically transfers one byte of data two times everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to 03FFF 1 een T ATMAPO 2 3 1 A 1 Lee ATMAPO 2 Only lower 8 bits are valid ATMAPO 3 Figure 18 3 11 Transfer Mode 9 In this mode the transfer direction indicated by memory pointers 0 and reverses for the second data byte transfer In the first data byte transfer the I O space address 0x03F00 0x03FFF in memory pointer 1 is the source address and the address in memory pointer 0 for
591. sion mode processor mode in its memory model Setting of each mode is different In single chip mode the system consists of only internal memory In memory expansion mode and processor mode ROM RAM and external device for operation can be connected This LSI supports memory expansion mode and processor mode Processor mode is not available in Flash version MN101EF01M Settings for each modes are as follows Table 2 2 1 Mask ROM MN101EO1K L M Memory mode MMOD pin EXMEM flag EXADV3 to 1 flags MEMCTR register EXADV register Single chip mode L 0 Memory expansion mode L 1 1 Processor mode H 5 Loader program mode Table 2 2 2 Flash EEPROM MN101EF01M Memory mode MMOD pin EXMEM flag EXADV3 to 1 flags MEMCTR register EXADV register Single chip mode L 0 Memory expansion mode L 1 1 Processor mode Loader program mode H 1 Fix the MMOD pin always to L H level Do not change the settings of this pin after reset release Memory Space Chapter 2 CPU Basics 2 2 2 Bank Function CPU of MN101E series has basically 64 KB memory address space On this LSI address space can be expanded up to 16 banks 1 MB based on units of 64KB by bank function In the expanded space based on bank units each memory mode single chip mode memory expansion mode processor mode has a different data access Bank functi
592. smis sion reception At this time SBII pin can be used as a general port too The transfer speed should be up to 5 0 MHz If the transfer clock is over 5 0 MHz the trans Y mission data may not be sent correctly At reception if SC1IOM of the SC1MD1 register is set to 1 and serial data input from SBO1 is selected SBl1 pin can be used as a general port Reception Buffer Empty Flag After reception is completed SCITIRQ is generated data is automatically stored to RXBUFI from the internal shift register If data is stored to the shift register RXBUFI when the SCISBIS of the SCIMDI register is set to serial input the reception buffer empty flag SCIREMP of the SCISTR register is set to 1 This indicates that the received data is going to read out SCIREMP is cleared to by reading out the data of RXBUFI Transmission Buffer Empty Flag During the communication after setting data to TXBUF1 and before the communication complete interrupt SCITIRQ is generated if any data is set to TXBUFI again the transmission buffer empty flag SCIREMP of the SCISTR register is set to 1 This indicates that the next transmission data is going to be loaded Data is loaded to the inside shift register from TXBUFI by generation of SCITIRQ and the next transfer is started as SCITEMP is cleared to 0 Overrun Error and Error Monitor Flag After reception complete if the next data has been already received before reading out
593. ss output bp2 P53 in out P5DIR3 P5PLU3 Address output P54 A4 in out P5DIR4 P5PLU4 4 Address output bp4 P55 A5 in out P5DIR5 P5PLU5 A5 Address output bp5 P56 A6 in out P5DIR6 P5PLU6 A6 Address output bp6 P57 A7 in out P5DIR7 P5PLU7 A7 Address output bp7 Pin Description 1 11 1 Overview Pins Special Functions I O Direction Pin Functions Description Control Control P60 KEY0 A8 in out P6DIRO P6PLUO KEY0 KEY interrupt input 0 A8 Address output bp8 P61 KEY1 A9 in out P6DIR1 P6PLU1 KEY1 KEY interrupt input 1 A9 Address output bp9 P62 KEY2 A10 in out P6DIR2 P6PLU2 KEY2 KEY interrupt input 2 A10 Address output bp10 P63 KEYS A11 in out PeDIR3 P6PLU3 KEYS KEY interrupt input A11 Address output bp11 P64 4 12 in out P6DIR4 P6PLU4 KEY4 KEY interrupt input 4 A12 Address output bp12 P65 KEY5 A13 in out P6DIR5 P6PLU5 KEY5 KEY interrupt input 5 A13 Address output bp 13 P66 KEY6 14 in out PeDIRe P6PLU6 KEY interrupt input 6 A14 Address output bp14 P67 KEY7 A15 in out P6DIR7 P6PLU7 KEY7 KEY interrupt input 7 A15 Address output bp15 P70 SDOO A16 in out P7DIRO P7PLUO SDOO Timer synchrpnous output 0 16 Address output bp16 P71 001 16 in out P7DIR1 P7PLU1 SDO1 Timer synchrpnous output 1 A17 Address output bp17 P72 SDO2 A17 in out P7DIR2 P7PLU2 SDO2 Timer synchrpnous output 2 18 Address output
594. ssary for UART communication itself but necessary for setup of data transmission reception timing in the serial interface Select the timer to be used as a baud rate timer by SCIMD3 register Receive Bit Count and First Transfer Bit In the case of reception when the transfer bit count is 7 bits the data storing method to the received data buffer RXBUF1 is different depending on the first transfer bit selection At MSB first data are stored to the upper bits of RXBUFI When there are 7 bits to be transferred as shown on Table 12 3 18 if data G to A are stored to bp7 to bp of RXBUFI At LSB first data are stored to the lower bits of RXBUFI When there 7 bits to be transferred as shown on Table 12 3 19 if data to are stored to to bp6 of RXBUFI 7 6 b 4 3 2 1 0 peuri J E ao Figure 12 3 18 Transfer Bit Count and First Transfer Bit starting with MSB 7 6 5 4 3 2 1 0 RXBUF 1 E Figure 12 3 19 Transfer Bit Count and First Transfer Bit starting with LSB The following items are the same as clock synchronous serial B First Transfer Bit Setup Refer to XII 13 B Transmission Data Buffer Refer to XII 13 B Received Data Buffer Refer to XII13 B Transfer Bit Count and First Transfer Bit Refer to XII 14 B Transmission Buffer Empty Flag Refer to XII 18 B Emergency Reset Refer to XII 19 XII 42 Operation 1
595. ssion Reception Setup Example reception in STANDBY mode Here is the setup example at transmission reception in STANDBY mode using serial interface 3 Table 14 3 12 shows the conditions Table 14 3 12 Conditions for Synchronous Serial Interface at transmission reception reception in STANDBY mode Item set to SBO3 pin selection Connect 2 channels Transfer bit count 8 bit Start condition Disabled First bit to be transfered MSB Input clock edge Falling Clock Clock slave Operation mode STOP mode Clock source fs 2 Used pins selection A port3 SBTS SBOS pin type Push pull SBT3 pull up resistor Not added 5813 pull up resistor Not added Serial interface 3 communication end interrupt Enabled An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Prescaler operation selection SC3MD3 0x03FA6 bp3 SC3PSCE 1 2 Clock source selection SC3MD3 0x03FA6 bp2 0 SC3PSC2 0 100 3 Used pins selection SC3MD3 0x03F4F bp3 SC3SEL 0 4 Control of pin type 0x03F2C bp5 3 PSODCS5 0 0 P3PLU 0x03F43 bp5 P3PLU5 3 0 0 1 Set the SC3PSCE flag of the SC3MD3 register to 1 to select prescaler operation 2 Set the SC3PSC2 0 flag of the SC3MD3 register to 100 to select fs 2 for clock source
596. ssion is generated B First Transfer Bit Setup The SCIDIR flag of the SCIMDO register can set the transfer bit MSB first or LSB first can be selected B Transmission Data Buffer The transmission data buffer TXBUF1 is a buffer of reserve that stores data to load the internal shift register Data to be transferred should be set to the transmission data buffer TXBUF1 to be loaded to the internal shift reg ister automatically The data load time of 3 transfer clock is needed to load the data On loading setting the data to TXBUFI again may cause error On loading or not is determined by monitoring the transmission buffer empty flag of SCISTR When the data is set to TXBUF1 SCI TEMP flag is set to 1 and when loading is finished it is cleared 0 automatically Data set to TXBUF1 OY Clock U prescaler output 5 Clock SBT1 pin Data road period Figure 12 3 1 Received Date Buffer The received data buffer RXBUFI is a buffer of reserve that pushed the received data in the internal shift register After the communication complete interrupt SC1TIRQ is generated all data stored in the internal shift register are stored to the received data buffer RXBUFI automatically RXBUFI can store data up to 1 byte RXBUFI is rewritten in every time when communication is completed so read out data of RXBUFI till the next receive is completed The received data buffer empty flag SCIREMP is set to 1 at the s
597. st Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 20 Serial Transmission Interrupt Control Register SCOTICR 0x03FF3 bp 7 6 5 4 3 2 1 0 Flag SCOTLV1 SCOTLVO SCOTIE SCOTIR At reset 0 0 0 0 Access R W SCOTLV1 SCOTLVO Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests SCOTIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SCOTIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Ill 37 Chapter 3 Interrupts Serial 1 UART Reception Interrupt Control Register SC1RICR The serial 1 UART reception interrupt control register SCI RICR controls interrupt level of serial 1 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 21 Serial 1 UART Reception Interrupt Control Register SC1RICR 0x03FF4 bp 7 6 5 4 3 2 1 0 Flag SC1RLV1 SC1RLVO 5 reset 0 0 i 0 0 Access R W Description SC1RLV1 Interrupt level flag SC1RLVO This 2 bit flag sets the interrupt level by assigning an interrupt leve
598. st of timer 2 is not generated but the timer 2 interrupt should be disabled When timer 4 and timer 5 are used in cascade connection timer 5 is used as an interrupt request flag Timer pulse output of timer 4 is L fixed output An interrupt request of timer 4 is not generated but the timer 4 interrupt should be disabled At cascade connection when the clear of the binary counter is needed by rewriting the com pare register set the TMnEM flag of both the upper 8 bit timer and the lower 8 bit timer to to stop counting Cascade Connection V 53 5 8 bit Timers 5 11 2 Setup Example srsss TaUsi Cascade Connection Timer Setup Example Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Setting example of timer function that an interrupt is constantly generated by cascade connection of the timer 0 and the timer 1 as a 16 bit timer is shown An interrupt is generated 2500 times every 1 ms by selecting source clock fs 2 fs 5 MHz at operation An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 TM1MD 0x03F55 bp3 TM1EN 0 2 Disable the timer interrupt TMOICR 0x03FE8 bp1 TMOIE 0 TM1ICR 0x03FE9 TM1IE 0 3 Select the normal lower timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 4 Set the cascade connectio
599. st vector number takes priority Maskable interrupts are accepted when its level is higher than the inter rupt mask level IM1 to 0 of PSW Non maskable interrupts are always accepted regardless of the interrupt mask level Overview 3 1 1 Functions e 2 7 Table 3 1 1 Interrupt Functions Chapter 3 Interrupts Interrupt type Reset interrupt Non maskable interrupt Maskable interrupt Vector number Table address 0 0x04000 1 0x04004 2 to 27 0x04008 to 0x0406C Starting address Address specified by vector address Interrupt level Can be set to levels 0 to 2 by software Interrupt factor External RST pin input Errors detection PI inter rupt External pin input internal peripheral function Generated opera tion Accept operation Direct input to CPU core Always accepts Input to CPU core from non maskable interrupt control register NMICR Always accepts Input interrupt request level set in interrupt level flag xxxL Vn of maskable interrupt control register XxxICR to CPU core Acceptance only by the interrupt control of the reg ister xxxICR and the inter rupt mask level in PSW Machine cycles until accepted 12 12 12 PWS status after acceptance All flags are cleared to 0 The interrupt mask level flag in PSW is cleared to 00 Values of the interrupt level flag xxxLVn are se
600. ster is set to 1 then the IICBSY flag is cleared to 0 at transmission reception end communication with ACK or at last bit communication end communication without ACK Setting 1 to the stop condition generation flag IIS TPC sets IICBSY flag to 1 After stop condition ends it is cleared to 0 If start condition is detected during communication the communication end interrupt SC2IRQ is generated and the IICBSY flag is automatically cleared B Forced Reset You can shut down the communication by setting both of the SC2SBOS flag and the SC2SBIS flag of the SC2MDI register to 0 the SBO2 pin function port input data input 1 When a forced reset is done the status register all flag of the SC2STR register and SC2BSY flag of the SC2MDO register are cleared but other control registers hold their set values Forced reset is operated at IICBSY is 0 And generate the stop condition and end the communication Operation 13 Serial Interface 2 B First Transfer Bit Setup Refer to XIII 15 B Transmission Reception Data Buffer Refer to XIII 15 B Transfer Bit Count and First Transfer Bit Refer to XIII 16 Continuous Communication Refer to 17 Automatic Continuous Transfer by Refer to 17 In communication set Nch open drain for pin type as the hardware switches if bus is used Y released In reception set the SDA2 pin 5802 pin direction to output Op
601. switched by controlling TXD4 pin s direction by the PADIRO flag of the P4DIR register At the same time the RXD4 pin can be used as a general port Reception Buffer Empty Flag When SCARIRQ is generated data is stored to RXBUFA from the internal shift register automatically If data is stored to RXBUF4 from the shift register the reception buffer empty flag SC4REMP of the SCASTR register is set to 1 That indicates that the received data is going to be read out SC4REMP is cleared to 0 by reading out the data of RXBUFA Reception BUSY Flag When the start condition is regarded the SC4RBSY flag of the SCASTR register is set to 1 That is cleared to 0 by the generation of the reception complete interrupt SCATIRQ If the SCASBIS flag is set to 0 during reception the SCARBSY flag is reset to 0 B Transmission BUSY Flag When any data is set to TXBUF4 the SCATBSY flag of the SCASTR register is set to 1 That is cleared to 0 by the generation of the transmission complete interrupt SCATIRQ During continuous communication the SCATBSY flag is always set If the transmission buffer empty flag SCATEMP is set to O as the transmission complete interrupt SCATIRQ is generated the SCATBSY is cleared to 0 If the SCASBOS flag is set to 0 the SCATBSY flag is reset to O Operation XV 39 15 Serial interface 4 B Frame Mode and Parity Check Setup Figure 11 3 17 shows the data format at UART communication
602. t timer output is selected from these three values fixed to high fixed to low and Hi z Clock source fosc fosc 2 fosc 4 fosc 16 fs fs 2 fs 4 15 16 1 1 1 2 1 4 1 16 of the external clock Hardware organization Compare register with double buffer 2 sets Input capture register 1 set Timer interrupt 2 vectors 1 6 Hardware Functions 1 Overview Watchdog timer Time out period can be selected from 15 216 15 218 fs 220 fs 2 On detection of errors hard reset is done inside LSI NMI interrupt is generated in the first execution and it is hard reset in the continuous interrupts Remote control out Based on the timer 0 and timer 3 output a remote control carrier with duty cycle of 1 1 put 1 2 or 1 3 can be output Synchronous out Timer synchronous output interrupt synchronous output put function Port 7 outputs the latched data on the event timing of the synchronous output sig nal of timer 1 2 of 7 or of the external interrupt 2 IRQ2 Buzzer output Output frequency can be selected from fosc 29 fosc 219 fosc 21 fosc 21 fosc 219 fosc 21 fx 23 tx 2 Data automatic Data is transferred automatically in all memory space 1 MB transfer Startup the external interrupt internal event software 255 byte max can be transferred continuously Support continuous serial transmission reception Burst transfer function Urgent stop of interrupts is contained A D conve
603. t 1 to 8 bit Start condition First transfer bit Input edge Output edge SBO3 output control after transferof H L last data hold last data Function in STANDBY mode Slave reception only ACK bit ACK bit level Continuous operation with ATC1 Clock sources fosc 2 fosc 2 fosc 4 fosc 4 fosc 16 fosc 16 fosc 32 fosc 32 fosc 64 fosc 64 fosc 128 fosc 128 fs 2 fs 2 fs 4 fs 4 timer 3 output timer 5 output XIV 2 Overview 14 Serial Interface 3 Maximum transfer rate 5 0 MHz NORMAL mode 100 kHz High speed mode 400 kHz fosc machine clock for high speed ocillation fs system clock In IIC communication transfer clock is obtained by dividing the clock source by 8 Transfer rate should be set slower than system clock fs Overview XIV 3 14 Serial Interface 3 14 1 2 Block Diagram Serial Interface 3 Block Diagram Oul os 198098 1 3 S SEVQS 8 O8S 6d VeVOS VEO8S d AS89II 241501 195 21891 5 SMOVEDS 55 OMOVEOS 58205 2625 319555 315895 eONTEOS LONTEOS OONTEDS 919895 5085205 09 595 i Jejunoo
604. t accepted and valid nmi interrupt A generated nmi interrupt A generated L Interrupt acceptance cycle Interrupt acceptance cycle nmi interrupt A service routine 2 nmi interrupt A service routine mi Interrupt B generated 2 Multiple interrupt service of nmi interrupt B is generated though a flag of nmi interrupt A is 1 0 nmi Interrupt generated Multiple interrupt is generated when a flag of nmi interrupt A is cleared interrupt acceptance cycle Invalid when a flag of nmi C nmi interrupt B service routine D interrupt is not cleared RTI RTI During nmi interruptA IRQNPG nmi interruptB IRQNWDG During nmi interruptA RQNWDG nmi interruptB IRQNPG Ill 14 Overview 3 Interrupts Figure 3 1 7 shows the processing sequence of the multiple interrupt multiple interrupt xxxLV 1 to 0 10 xxxLV1 to 0 00 IM1 0 11 Interrupt 1 generated z Accepted because xxxLV1 0 IM xxxLV1 0 10 Interrupt acceptance cycle IM1 0 10 C Interrupt service routine 1 3 Interrupt 2 generated 2 gt Accepted because xxxLV1 0 IM xxxLV1 0 00 nterrupt acceptance cycle 11 0 00 Interrupt service routine 2 Restart interrupt processing program 1 mi o t0 RTI 1
605. t data to TXBUF3 in the period that after data is loaded to internal shift register and before communication end interrupt SC3IRQ is generated In master communication communication blank from SC3IRQ generation to next transfer clock output is 4 transfer clock Automatic Continuous Transfer by the automatic data transfer function built in this LSI can activate Serial interface 3 It enables continuous transfer of data up to 255 byte For activation using ATCI refer to chapter 18 Automatic Transfer Controller Transfer mode 8 to 9 Input edge output edge Setup The 1 flag of the SC3MDO register sets the output edge of the transmission data and the input edge of the received data Data at transmission is output at the falling edge of clock as the SC3CEI flag 0 and at the ris ing edge of clock as the SC3CEI 1 Data at reception is input at the rising edge of clock as the SC3CEI 0 and at the falling edge of clock as the SC3CEI flag 1 Table 14 3 2 Input Edge Output Edge of Transmission and Reception Data SC3CE1 Transmission data output edge Received data input edge 0 mum 1 Y Operation XIV 17 14 Serial Interface 3 Clock Setup Clock source is selected from the dedicated prescaler and timers 3 5 output 2 channels with the SC3PSC3 to 0 of the SC3MD3 register The dedicated prescaler is started by selecting count enable with th
606. t falling edge SBTO pin Data is received at the rising edge of clock SBIO pin Data is output at the falling edge of clock SBOO pin Figure 11 3 15 Transmission Reception Timing Reception at falling edge Transmission at rising edge XI 26 Operation 11 Serial interface 0 B Communication Function at Standby Mode This serial interface has the following way about the return from the standby mode This serial interface can do the slave reception at the standby mode CPU operation status can be recovered from standby to normal by the communication complete interrupt SCOTIRQ that is generated after the slave reception At the standby mode if the transfer bit count data is received once that is set by the SCOLNG2 to 0 flag of the SCOMDO register the continuous reception is not available because the next data is not allowed The received data should be read out from the received data buffer RXBUFO after recovering the normal mode In the reception at the standby mode the communication with enabled start condition is not available Disable the start condition The dummy data should be set to the transmission data buffer TXBUFO before the transition to the standby mode Normal mode Standby mode Normal mode gt gt gt Kappa Pu 6 Wait T Oscillation lt MS Stabilization Clock SBTO pin Input pin 5810 SBOO pin Transfer bit counter SCORBSY
607. t is disabled Operation XV 43 15 Serial interface 4 B Reception Timing Tmin 0 5T T Stop RXD4 pin bit SCARBSY Fm Input start condition Interrupt SC4RIRQ Figure 15 3 22 Reception Timing parity bit is enabled Tmin 0 5T T lt Stop RXD4 pin bit SC4RBSY Input start condition Interrupt P D SCARIRQ Figure 15 3 23 Reception Timing parity bit is disabled XV 44 Operation 15 Serial interface 4 B Transfer Speed Setup Baud rate timer timer 1 timer 2 can set any transfer rate Table 15 3 19 shows the setup example of the transfer speed Table 15 3 19 UART Serial Interface Transfer Speed Setup Register Page Serial 4 clock source timer 2 timer 5 SC4MD3 XV 10 Timer 2 clock source TM2MD V 19 Timer 2 compare register 2 V 14 Timer 5 clock source TM5MD V 22 Timer 5 compare register TM5OC V 15 Timer compare register is set as follows baud rate 1 overflow cycle 2x 8 8 means that clock source is divided by 8 overflow cycle set value of compare register 1 x timer clock cycle therefore set value of compare register timer clock frequency baud rate x 2x 8 1 For example if baud rate should be 300 bps at timer clock source fs 4 fosc 8 MHZ fs fosc 2 set value should be as follows Set value of compare register 8 x109 2 4 300x2x8 1
608. t levels from 0 to 3 This flag sets the interrupt level for inter rupt requests REDG1 External interrupt valid edge flag 0 Falling edge 1 Rising edge IRQ1IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQ1IR External interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 21 Chapter 3 Interrupts External Interrupt 2 Control Register IRQ2ICR The external interrupt 2 control register IRQ2ICR controls interrupt level of external interrupt 2 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSE is 0 Table 3 2 5 External Interrupt 2 Control Register IRQ2ICR 0x03FE4 bp 7 6 5 1 0 Flag IRQ2LV1 IRQ2LVO REDG2 IRQ2IE IRQ2IR At reset 0 0 0 0 0 Access R W Description IRQ2LV1 External interrupt level flag IRQ2LV0 The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for inter rupt requests REDG2 External interrupt valid edge flag 0 Falling edge 1 Rising edge IRQ2IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQ2IR External interrupt request flag 0 No interrupt request 1 Interrupt request generated 22 Control Registers 3 Interrupts B External Interrupt Control Register IR
609. t the data to pins set the control flag of the port 2 direction control register P2DIR to 1 to write the value of the port 2 output register P2OUT To read input data of pins set the control flag of the port 2 direction control register P2DIR to 0 to read the value of the port 2 input register P2IN Each bit can be set individually as either an input or output by the port 2 I O direction control register P2DIR The control flag of the port 2 direction control register P2DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 2 pull up resistor control register P2PLU Set the control flag of the port 2 pull up resistor control register P2PLU to 1 to add pull up resistor P27 is reset pin When the software is reset write 0 to the bp7 of the port 2 output register PZOUT Also P27 is always added pull up resistor Special Function Pin Setup P20 is used as external interrupt O pin as well P21 is used as external interrupt 1 pin as well P22 15 used as external interrupt 2 pin as well External interrupt 2 can select either P22 or PDO by setting of the external interrupt pin switching control register IRQSEL When IRQ2SEL flag of the external interrupt pin switching control register IRQSEL is 0 P22 is selected and 1 PDO is selected P23 is used as external interrupt 3 pin as well External interrupt 3 can select either
610. t the processor mode or the memory extension mode However bp5 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp5 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P63 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp5 of the address output control register EXADV should be set to use as the address output pin or the Port 6 Chapter 4 I O Ports general port pin at the memory extension mode When bp5 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P64 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp6 of the address output control register EXADV should be set to use as the address output pin or the general port pin at the memory extension mode When bp6 of the address output control register EX ADV is 1 at the memory extension mode or at the processor mode it is output mode automatically P65 is address output pin to the external extension memory at the processor mode or the memory extension mode However bp6 of the address output control register EXADV should be set to use as the address output pin or the gene
611. t to the interrupt mask level mask ing all interrupt requests with the same or the lower priority Overview 3 Chapter 3 Interrupts 3 1 2 Block Diagram Level deter gt Interrupt mination CPU core Vector 1 IRQNMI IRQLVL 2 0 WDOG IRQ0ICR xxxLV1 0 5 function XXxLV Interrupt Level xxxlE Interrupt Enable Interrupt Request XxxICR poxLV1 0 Peripheral PEU function 1 0 xxxLV Interrupt Level xxxIE Interrupt Enable xxxIR Interrupt Request Figure 3 1 1 4 Overview 3 Interrupts 3 1 3 Operation Interrupt Processing Sequence For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt accep tance and hardware processing The program counter PC and processor status word PSW and hard addressing data HA are saved onto the stack and program is branched to the address specified by the corresponding inter rupt vector interrupt handler ends by restoring the contents of any registers used during processing and then executing the return from inter
612. ta transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt occurs and the automatic transfer ends XVIII 30 Operation 18 Automatic Transfer Controller 18 3 17 Transfer Mode C Ep n aasan saan uwa In transfer mode C ATC1 automatically transfers one byte of data from any memory space to any other memory space everytime an ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 00000 to FFFFF 2 a ATMAPO E 1 2 2 1 1 2 1 2 3 1 3 Figure 18 3 14 Transfer Mode C Set the source address in 20 bit memory pointer 0 ATIMAPOH M L and set the destination address in 20 bit memory pointer 1 ATIMAPIH M L In transfer mode C the values in memory pointers and 1 increment everytime a byte length data transfer ends As a result the source and destination addresses for the next transfer are one address higher than those for the original transfer Set the data transfer count for in the transfer data counter ATI TRC Up to 255 transfers can be set The counter decrements everytime an is activated When it reaches 0x00 an interrupt ATC 1IIRQ occurs and the automatic transfer ends Operation
613. ter rupt request flag to be rewritten This is necessary only when the interrupt request flag is changed by the soft ware 4 Rewrite the interrupt request flag xxxIR of the inter rupt control register xxxICR b Clear the IRWE flag so that interrupt request flag can not be rewritten by the software 6 Set the interrupt level by the xxxLV1 0 flag of the interrupt control register XxxICR Set the IM1 0 flag of PSW then the interrupt accep tance level of CPU should be changed 7 Set the xxxIE flag of the interrupt control register xxxICR to enable the interrupt 8 Set the MIE flag of PSW to enable maskable inter rupts 3 2 Control Registers 3 2 1 Registers List23 Chapter 3 Interrupts Table 3 2 1 Interrupt Control Registers Register Address R W Functions Page NMICR OxOSFE1 RW Non maskable interrupt control register III 19 IRQ0ICR OxOSFE2 R W External interrupt 0 control register III 20 IRQ1ICR 0x03FE3 R W External interrupt 1 control register 111 21 IRQ2ICR 0 03 4 R W External interrupt 2 control register 11 22 IRQ3ICR 0x03FE5 R W External interrupt 3 control register 1 23 IRQ4ICR OxO3FE6 R W External interrupt 4 control register 111 24 IRQ5ICR OxOSFE7 R W External interrupt 5 control register 25 TMOICR OxO3FE8 R W Timer 0 interrupt control register Timer 0 compare match
614. ter NFCTR to Table 3 3 9 Addition of Noise Remove Function NFnEN IRQ input P20 IRQ input P21 0 IRQO noise filter OFF IRQ1 noise filter OFF 1 IRQO noise filter ON IRQ1 noise filter ON B Sampling Cycle Setup External interrupts 0 and 1 The sampling cycle of noise remove function can be set by the NFnSCK2 to 0 flag of the NFCTR register Table 3 3 10 Sampling Cycle Time of Noise Remove Function NFnCKS1 NFnCKSO Sampling cycle fs 10 MHz 0 fs 10 MHz 100 ns 1 15 28 39 06 kHz 25 6 us 0 fs 29 19 53 kHz 51 20 us 1 fs 210 9 76 kHz 102 40 us External Interrupts 3 Interrupts Noise Remove Function Operation External interrupts 0 and 1 After sampling the input signal to the external interrupt pins IRQ0 IRQ1 with the set sampling time if the same level comes continuously three times that level is sent to the inside of LSI If the same level does not come con tinuously three times the previous level is sent It means that only the signal with the amplitude of longer than Sampling time X 3 sampling clock can pass through the noise filter and other signals with amplitude shorter than this are removed because those are regarded as noise UM IRQn pin input signal Signal after filtering noise 0 0 1 1 1 1 1 0 0 Figure 3 3 7 Noise Remove Function Operation Noise filter cannot be used at STOP mode and HALT mode
615. ter the return address from the pro gram counter and the processor status word PSW to the stack and branches program to the interrupt handler using the starting address in the vector table The following is the hardware processing sequence invoked by interrupt acceptance 1 the stack pointer SP is updated SP 6 SP 2 The contents of the handy address register HA are saved to the stack Upper half of HA SP 5 Lower half of HA SP 4 3 The contents of the program counter PC i e the return address are saved to the stack PC bits 19 16 SP 3 PC bits 15 8 SP 2 PC bits 7 0 SP 1 4 The contents of the PSW are saved to the stack PSW SP 5 The interrupt level xxxLVn for the interrupt is copied to the interrupt mask IMn in the PSW Interrupt level xxxLVn IMn 6 BKD flag of the PSW is reset During interrupt acceptance bank register always address the first G4KB The bank register can be rewritten 7 The hardware branches program to the address in the vector table 7 0 New PSW Lower after interrupt to 0 acceptance PC1510 8 H reserved PC19 to 16 Address HA7 to 0 HA15 to 8 Higher Old SP before interrupt acceptance m E Figure 3 1 5 Stack Operation during Interrupt Acceptance Overview 3 Interrupts B Interrupt Return Operation An interrupt handler ends by
616. ter 1 7 1 and the timer 7 binary counter TM7BC is initialized to 0 0000 6 Set the interrupt level by the TM7LV1 to 0 flag of the timer 7 interrupt control register TM7ICR If the interrupt request flag is already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 7 Set the TM7IC flag of the TM7ICR register to 1 to enable the interrupt 8 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 TM7BC counts up from 0x0000 When TM7BC reaches the set value of the register the timer 7 inter rupt request flag is set at the next count clock and the TM7BC becomes 0x0000 and counts up again Operation VI 6 16 bit Timer When the TM7EN flag of the TM7MD register is changed with other bits the binary counter Y may count up by switching operation VI 16 Operation 6 16 bit Timer 6 4 16 bit Event Count 6 4 1 Operation Event count operation has 2 types TM7IO input and synchronous TM7IO input These can be selected as the count clock Each type can select 1 1 1 2 1 4 1 16 or 1 128 as a count clock source Also it is possible to select the count edge the falling edge and the both edge at the normal operation are selectable 16 bit Event Count Operation Timer 7 The binary counter TM7BC counts the external signal input to the TM7IO pin If the binary counter reaches the set value of the compare
617. ter should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 23 Serial 2 Interrupt Control Register SC2ICR 0x03FF6 bp 7 6 5 4 3 2 1 0 Flag SC2LV1 SC2LVO SC2IE SC2IR At reset 0 0 0 0 Access R W Description SC2LV1 Interrupt level flag SC2LV0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 40 Control Registers 3 Interrupts Serial Interrupt Control Register SC3ICR The serial 3 interrupt control register SC3ICR controls interrupt level of serial 3 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW 15 0 Table 3 2 24 Serial Interrupt Control Register SC3ICR 0x03FF7 bp 7 6 1 0 Flag SC3LV1 SC3LV0 SC3IE SCSIR At reset 0 0 0 0 Access R W Description SC3LV1 Interrupt level flag SC3LV0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request ge
618. ternal interfaces respectively The bus control block controls the parallel operation of instruction read and data access the access speed adjustment for low speed external devices and arbitration of bus access when using master devices on the external bus lines A functional block diagram of the bus controller is given below Instruction Interrupt queue Program address ATC Operand address control Bus open Bus open request signal enable signal NBR NBG Bus controller Y Bus arbitor Interrupt bus os Address decode 4 Address decode Memory mode setting Bus access wait control Memory control register Instruction input bus Data input bus Data output bus Internal RO Figure 2 4 1 Functional Block Diagram of the Bus Controller Internal In memory expansion mode or processor mode the external expansion bus can access external device Memory control register MEMCTR can be used to select the access mode B fixed wait cycle mode or B handshake mode Wait cycle setting to peripheral expansion bus connected to internal peripheral circuits is available Bus Interface 37 2 CPU Basics 2 4 2 Control Registers d n v lt ncrT hh Y Bus interface is controlled by 2 registers the memory control register MEMCTR and the expansion address contro
619. ternal interrupt 2 input pin switching 0 P22 1 PDO Control Registers 5 8 bit Timers 5 3 Prescaler 5 3 1 Prescaler Operation Prescaler Operation Prescaler 0 to 1 Prescaler 0 prescaler 1 are each free run counter of 7 bits 3 bits and output the dividing clock of the reference clock This count up operation starts automatically when any TMnEN flags of 8 bit timer are set to 1 and oper ate the timer n counting Also it stops automatically when all TMnEN flags of 8 bit timer are set to 0 and stop all timer counting Count Timing of Prescaler Operation Prescaler 0 to 1 Prescaler 0 counts up at the falling edge of fosc Prescaler 1 counts up at the rising edge of fs Peripheral Functions Peripheral functions which can use the prescaler output dividing clock or registers which control the dividing clock selections are shown below Timer 0 Count Clock CKOMD Timer 1 Count Clock CK1MD Timer 2 Count Clock CK2MD Timer 3 Count Clock CK3MD Timer 4 Count Clock CK4MD Timer 5 Count Clock CK5MD Start the timer operation after the prescaler setup Also at the timer the prescaler output should be set up by the timer mode register The prescaler starts counting at the start of the timer operation Prescaler V 25 5 8 bit Timers 5 3 2 Setup Example Prescaler Operation Setup Example fs 2 clock which is output from the
620. terrupt IRQ4 1 Key interrupt KEYT3_1EN3 KEY6 interrupt selection 0 Disable 1 Enable KEYT3_1EN2 KEY5 KEY4 interrupt selection 0 Disable 1 Enable KEYT3_1EN1 KEY3 KEY2 interrupt selection 0 Disable 1 Enable KEYT3_1ENO KEY1 KEYO interrupt selection 0 Disable 1 Enable External Interrupts Chapter 3 Interrupts III 57 Chapter 3 Interrupts B External Interrupt Pin Switching Control Register IRQSEL The external interrupt pin switching control register specifies interrupt input pin of external interrupt 2 and exter nal interrupt 3 Table 3 3 7 External Interrupt Pin Switching Control Register IRQSEL 0x03F4E bp 7 6 5 4 3 2 1 0 Flag IRQ3SEL IRQ2SEL At reset 0 0 Access R W Description IRQ3SEL External interrupt 3 input pin switching 0 P23 1 PD1 IRQ2SEL External interrupt 2 input pin switching 0 P22 1 PD0 58 External Interrupts B External Interrupt Valid Input Switching Control Register LVLMD Table 3 3 8 External Interrupt Valid Input Switching Control Register LVLMD 0x03F6D Chapter 3 Interrupts bp 7 6 5 4 3 2 1 0 Flag EXLVL5 LVLEN5 EXLVL3 LVLEN3 EXLVL2 LVLEN2 At reset 0 0 0 0 0 0 Access R W EXLVL5 Description External interrupt 5 valid input level set O L level 1 H level L
621. terrupts R W Readable Writable Prescaler Control Register PSCMD Prescaler control register enables or disables the prescaler count Prescaler is used when the dividing clock of fs base is used at IRQO IRQ1 Table 3 3 3 Prescaler Control Register PSCMD 0x03F6F bp 7 6 5 4 3 0 Flag 5 a PSCEN At reset 5 0 Access R W Prescaler count control 0 Disable count 1 Enable count 54 External Interrupts 3 Interrupts Noise Filter Control Register NFCTR The noise filter control register NFCTR sets the noise remove function to IRQO and IRQI and also selects the sampling cycle of noise remove function Table 3 3 4 Noise Filter Control Register NFCTR 0x03F2E bp 7 6 5 4 3 2 1 0 Flag Reserved NF1SCK1 NF1SCKO NF1EN NFOSCK1 NFOSCKO NFOEN Atreset 0 0 0 0 0 0 0 Access RAN Description Reserved Set always 0 NF1SCK1 IRQ1 noise sampling period NF1SCKO 00 fs 01 16 28 10 fs 29 11 16 210 IRQ1 noise filter setup 0 Noise filter OFF 1 Noise filter ON NF0SCK1 IRQ0 noise sampling period NF0SCK0 00 fs 01 fs 28 10 fs 29 11 1s 210 IRQO noise filter setup 0 Noise filter OFF 1 Noise filter ON External Interrupts Ill 55 Chapter 3 Interrupts Both Edges Interrupt Control Register EDGDT The both edges interrupt control register
622. th 2 channels at reception Setup item Data output pin Serial unused pin Clock I O pin SBO4 pin SBI4 pin SBT4 pin Clock master Clock slave SC4MD1 SC4MST Port pin P40 P41 P42 Serial data input 584 selection SC4MD1 SC4IOM Function Port Serial input Transfer clock input Transfer clock input output output SC4MD1 SC4SBO SC4MD1 SC4SBIS SC4MD1 SC4SBIS 5 Style Push pull Nch open Push pull Nch open drain drain P4ODC P4ODC2 Input mode Output mode Input mode P4DIR P4DIR0 P4DIR P4DIR2 Pull up setup s Added Not added Added Not added PAPLU PAPLU2 Operation XV 81 15 Serial interface 4 15 3 2 Setup Example o aMnLsairra e B Transmission Reception Setup Example The setup example for clock synchronous serial communication with serial 4 is shown Table 15 3 12 shows the conditions at transmission reception Table 15 3 12 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item Set to Serial data input pin Independent 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Output edge Rising edge Clock Clock master Clock source fs 2 Clock source 1 8 dividing Not divided by 8 SBT4 SBO4 pin style Nch open drain SBT4 pin pull up resistor Added SBO4 pin pull up resistor Add
623. the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P75 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P76 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P77 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that ge
624. the cycle up to 218 x system Writing to WOCTR 0x03F02 clock c f BSET WDEN The watchdog timer clear should be inserted in the bp0 WDEN 1 main routine with the same cycle and to be the set cycle The recommended instruction is the bit set BSET does not change value for clear B Interrupt Service Routine Setup Setup Procedure Description 1 Set the watchdog interrupt service routine 1 If the watchdog timer overflows the non maskable NMICR 0x03FE1 interrupt is generated TBNZ NMICR WDIR WDPRO Confirm that the WDIR flag of the non maskable interrupt service routine to manage the suitable execution The operation just before the WDOG interrupt may be executed wrongly Therefore if the Y WDOG interrupt is generated initialize the system IX 6 Operation Chapter 10 Buzzer 10 Buzzer 10 1 Overview This LSI has a buzzer It can output the square wave that multiply by 1 2 to 1 214 of the high frequency oscilla tion clock or by 1 2 to 1 24 of the low frequency oscillation clock 10 1 1 Block Diagram Buzzer Block Diagram fosc MUX e gt 1 2 1 214 R 1 fosc 2 1 fosc 213 12 t gt pz BUZZER TS fosc 2 fosc 2 0 MUX 9 DLYCTR x 4 E 0 Count clear PUE OO control circuit fx 2 DLYS1
625. the initial state after releasing reset the timer pulse output is reset and low output is fixed Therefore release the reset of the timer pulse output by setting the TM7CL flag of the TM7MD 1 register to O a Reset release of the timer pulse output should be done when the timer count is stopped When the prescaler is operated by the timer pulse output set the prescaler dividing rate after Y the reset release of the timer pulse output 16 bit Timer Pulse Output VI 23 6 16 bit Timer 6 5 2 Setup Example Timer Pulse Output Setup Example TM71IO output pin outputs a 50 kHz pulse using Timer 7 For this select fosc as the clock source and set 2x cycle 100 kHz to the Timer 7 compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counting TM7MD1 0x03F78 bp4 TM7EN 0 2 Select the pin TMSEL 0x03F3F bp6 TM7SEL 0 3 Set the special function pin P1OMD 0x03F2B bp6 P1OMD6 1 P1DIR 0x03F31 bp6 P1DIR6 1 4 Set the timer pulse output TM7MD2 0x03F79 bp4 TM7PWM 0 5 Release the reset of the timer pulse TM7MD1 0x03F78 bp5 TM7CL 0 6 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 7 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 8 Set the timer pulse output generation cycle TM7PR1 0x03F75 0x03F7
626. the port 8 pull up resistor control register P8PLU to 1 to add pull up resistor B Special Function Pin Setup P80 is used as LED drivering pin as well P81 is used as LED drivering pin as well P82 is used as LED drivering pin as well P83 is used as LED drivering pin as well P84 is used as LED drivering pin as well P85 is used as LED drivering pin as well P86 is used as LED drivering pin as well P87 is used as LED drivering pin as well P80 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register P81 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register P82 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register P83 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register P84 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register P85 is data I O pin with the external extension memory at the processor mode or the memory extension mode These modes can not be controlled to I O by the register P86 is data I O pin w
627. the transmission data buffer TXBUFO to be loaded to the internal shift reg ister automatically The data load time of 3 5 transfer clock is needed to load the data On loading setting the data to TXBUFO again may cause error On loading or not is determined by monitoring the transmission buffer empty flag of the SCOSTR When the data is set to TXBUFO SCOTEMP flag is set to 1 and when loading is finished it is cleared 0 automatically Data zu to TXBUFO Clock prescaler output x SCOTEMP Clock SBTO0 pin Data road period Figure 11 3 1 Received Date Buffer The received data buffer RXBUFO is a buffer of reserve that pushed the received data in the internal shift register After the communication complete interrupt SCOTIRQ is generated all data stored in the internal shift register are stored to the received data buffer RXBUFO automatically RXBUFO can store data up to 1 byte RXBUFO is rewritten in every time when communication is completed so read out data of RXBUFO till the next receive is completed The received data buffer empty flag SCOREMP is set to 1 at the same time SCOTIRQ is generated SCOREMP is cleared to 0 after RXBUFO is read out Operation 11 Serial interface 0 If a start condition is input to restart during communication the transmission data is not valid Set the transmission data to TXBUFO again to operate the transmission again RXBUFO is rewritten every t
628. the watchdog timer is stopped 4 In STOP mode the watchdog timer is cleared automatically 5 In STOP mode the watchdog interrupt cannot be generated 6 After recovering from STOP the counting is executed for the period of the oscillation stabilization wait time 7 After releasing reset the watchdog timer is cleared automatically and stop counting Generally in the system used STOP mode if the STOP mode is done or not is divided on the program execution but in this case the counting value of the watchdog timer differs Operation IX 5 9 Watchdog Timer 9 3 2 Setup Example _ The watchdog timer detects errors On the following example the time out period is set to 218 x system clock An example setup procedure with a description of each step is shown below Initial Setup Program Watchdog Timer Initial Setup Example Setup Procedure Description 1 Set the time out period 1 Set the WDTS1 0 flag of the watchdog timer control WDCTR OxOS3F02 register WDCTR to 01 to select the time out period bp2 1 WDTS1 0 01 to 218 x system clock 2 Start the watchdog timer operation 2 Set the flag of the WDCTR register to 1 to start WDCTR 0x03F02 the watchdog timer operation bp0 WDEN 1 B Main Routine Program Watchdog Timer Constant Clear Setup Example Setup Procedure Description 1 Set the watchdog timer for the constant clear 1 Clear the watchdog timer by
629. ting cloc Figure 2 7 1 Minimum Reset Pulse Width 2 Setting the PLOUT7 flag of the P2OUT register to 0 outputs low level at P27 NRST pin And transferring to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P20UT7 flag becomes 1 and reset is released a This LSI is activated in NORMAL mode in which the base clock is high frequency enough low level time at sudeen unconnected And reset be generated even if NRST pin 1 When NRST is connected to low power voltage detection circuit that gives pulse for is held for less than OSC 4 clock cycles take notice of noise 1 In this LSI the oscillation High speed oscillation Low speed oscillation is stopped Reset 53 2 CPU Basics Sequence at Reset 1 When reset pin comes to high level from low level the innternal 14 bit counter It can be used as watchdog timer too starts its operation by system clock The period from starting its count from its overflow is called oscillation stabilization wait time 2 During reset internal register and special function register are initiated Register Address R W Description Initial value PSW Processor status word 0x00 Addresss PG Program counter stored in 0x04000 An Address register undefined Dn Data register undefined CPUM Ox03F00 R W CPU mode control register 0
630. ting of the timer 0 b Set the P1OMDO flag of the port 1 output mode register P1OMD to 1 to set 1 pin to the particular function pin Set the P1DIRO flag of the port 1 direction control register PTMODIR to 1 to set the output mode Set the TMORM flag of the RMCTR register to 1 to select the remote control career output Operations 8 Remote Control Functions Setup Procedure Description 6 Select the timer general operation TM0MD 0x03F54 bp4 TMOPWM 0 bp5 TM0MOD 0 bp6 0 7 Select the count clock source TM0MD 0x03F54 bp2 0 TM0CK2 0 X01 8 Select and enable the prescaler output CK0MD 0x03F56 bp2 1 TMOPSC1 0 X0 bp0 TMOBAS 1 9 Set the base cycle of the remote control career TMOOC 0x03F52 20x36 10 Start the timer operation TMOMD 0x03F54 bp3 TMOEN 1 11 Enable the remote control career output RMCTR 0x03F7F bp3 RMOEN 1 6 Set the TMOPWM flag the TMOMOD flag and the TMOPOP flag of the TMOMD register to 0 to select the timer general operation 7 Select the prescaler output to the clock source by theTMOCK to 0 of the TMOMD register 8 Select the fs 2 to the prescaler output by the TMOPSC1 to 0 flag TMOBAS flag of the timer 0 prescaler selection register 9 Set the base cycle of the remote control career by writing 0x36 to the timer 0 compare register TMOOC To get 2x cycles of 36 7 kHz 73 4 kHz that is
631. tion Serial interface 4 can be used for both clock synchronous and full duplex UART 15 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 15 3 1 shows activation factors for communication At master communication the transfer clock is gener ated by setting data to the transmission data buffer TX BUFA or by receiving a start condition Except during communication the input signal from SBT4 pin is masked to prevent errors by noise or so This mask can be released automatically by setting a data to TXBUF4 access to the TXBUF4 register or by inputting a start con dition to the data input pin Therefore at slave communication set data to TXBUF4 or input an external clock after a start condition is input However the external clock should be input after more than 3 5 transfer clock interval after the data set to TXBUFA This wait time is needed to load the data from TXBUF4 to the internal shift register Table 15 3 1 Synchronous Serial Interface Activation Factor Activation factor Transmission Reception At master Set transmission data Set dummy data Input start condition At slave Input clock after transmission data Input clock after dummy data is set is set Input clock after start condition is input B Transfer Bit Setup The transfer bit count is selected from 1 to 8 bits Set them by the SCALNG 2 to 0 flag of the SCAMDO register at reset 111 The SC4L
632. tion 0 Input mode 1 Output mode Port 1 Pull up Resistor Control Register P1PLU 0x03F41 P1PLU6 1 5 PiPLU4 P1PLU3 P1PLU2 P1PLU1 Chapter 4 I O Ports P1PLU0 0 0 0 0 0 0 0 O gt O Q O P1PLU6 P1PLU5 P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0 Description Pull up resistor selection 0 Not added 1 Added Port 1 IV 17 4 I O Ports Port 1 Output Mode Register P1OMD 0x03F2B P1OMD6 P1OMD5 P1OMD4 P1OMD3 PIOMD2 P1OMD1 P1OMDO 0 0 0 0 0 0 0 Description I O port TM7IO selection P1OMDS6 0 l O port 1 TM7IO port TMBIO selection P1OMD5 0 l O port 1 TM5IO port TM4IO selection P1OMD4 0 l O port 1 TM4IO I O port TMSIO selection P1OMDS 0 l O port 1 TM3IO I O port TM2IO selection P1OMD2 0 l O port 1 TM2IO I O port TM1IO selection P1OMD1 0 l O port 1 TM1IO port TMOIO RMOUT selection P1OMDO 0 l O port 1 TMOIO RMOUT IV 18 Port 1 Chapter 4 I O Ports Port 1 Real Time Output Control Register 0 P1CNT0 0x03F7E P1CNTO5 04 P1CNTO3 PICNT02 PICNT01 P1CNTOO 0 0 0 0 0 0 Description P14 Real time control 00 1 port real time control disabled P1CNTO05 1 04 01 1 High output 10 0 Low output 11 Hi z output P12 Real time control
633. tion 1 PWM operation Timer 0 count control 0 Halt the count 1 Operate the count TMOCK2 Select the clock source TMOCK1 X00 fosc TMOCKO X01 TMOPSC Prescaler output 010 fx 011 Synchronous fx 110 TMOIO input 111 Synchronous TMOIO output Control Registers V 17 5 8 bit Timers Timer 1 Mode Register TM1MD 0x03F55 bp 4 2 1 0 Flag TM1CAS TM1CK2 TM1CK1 TM1CKO At reset 0 0 0 0 Access Description 7 5 4 TM1CAS Select timer 1 operation mode 0 Normal timer operation 1 Cascade connection 3 TM1EN Timer 1 count control 0 Halt the count 1 Operate the count 2 0 TM1CK2 Select the clock source TM1CK1 X00 fosc TM1CKO X01 TM1PSC Prescaler output 010 fx V 18 Control Registers 011 Synchronous fx 110 TM1IO input 111 Synchronous TMOIO input Timer 2 Mode Register TM2MD 0x03F5C bp 6 5 4 2 1 Chapter 5 8 bit Timers 0 Flag TM2POP TM2MOD TM2PWM TM2CK2 TM2CK1 TM2CKO At reset 0 0 0 0 0 0 Access Description TM2POP On PWM mode select start compulsion of output signal O timer output HL 1 timer output HL TM2MOD Pulse width measurement control 0 Normal timer operation 1 P23 PD1 pulse width measurement TM2PWM Select timer 2 operation mode 0 Normal timer operation 1 PWM operation TM2EN Timer 2 cou
634. tion regardless of transmission reception This serial interface can not be used for slave communication B Start Condition Setup In IIC communication enable start condition by the SC2STE flag of the SC2MDO register at the first communica tion after reset release From the second communication the SC2STE flag of the SC2MDO register can select if start condition is enabled or not If start condition is detected during data communication in which the start condition is enabled the SC2STC flag of the SC2CTR register is set to 1 and the communication end interrupt SC2IRQ is generated to end the trans mission This means that the communication is not executed properly and needs to be re executed Clear the SC2STC flag by program When data line SDA2 pin is changed from to L while clock line the SCL2 pin 15 start condition is generated XIII 36 Operation 13 Serial Interface 2 Generation of Stop Condition Stop condition is generated as the SDA2 line is changed from L to H while the SCL2 line is H Stop condi tion can be generated by setting the IICSTPC flag of the SC2CTR register to 0 by program Start condition Stop condition SDA a E Serial data SCL 1 pp s Serial clock Figure 13 3 17 Start Condition and Stop Condition Input Edge Output Edge Setup In communication data is always received at the falling edge of the clock Even if the SC2CEI flag i
635. tion at the moment of switching clock speed between high speed Y oscillation fosc and low speed oscillation fx fosc should be set to 2 5 times or higher Standby Function II 45 2 CPU Basics 2 5 2 CPU Mode Control Register Ja s Transition from one mode to another mode is controlled by the CPU mode control register CPUM 7 6 5 4 3 2 1 0 CPUM Reserved OSCSEL1 OSCSELO OSCDBL STOP HALT OSC1 OSCO At reset 0 0 0 0 0 0 0 0 Operation STOP HALT OSC1 osco losco NORMAL 0 0 0 OscillationOscillaion OSCI Operating IDLE 0 0 0 1 Oscillation Oscillation XI Operating SLOW 0 0 1 1 Halt Oscillation XI Operating HALTO 0 1 0 Oscillation Oscillaion OSCI Halt HALT1 0 1 1 1 Halt Oscillation XI Halt STOPO 1 0 0 0 Halt Halt Halt Halt STOP1 1 0 1 1 Halt Halt Halt Halt Figure 2 5 2 Operating Mode and Clock Oscillation CPUM 0x3F00 The procedure for transition from NORMAL to HALT or STOP mode is given below 1 If the return factor is a maskable interrupt set the MIE flag in the PSW to 1 and set the interrupt mask IM to a level permitting acceptance of the interrupt 2 Clear the interrupt request flag xxxIR in the maskable interrupt control register xxxICR set the interrupt enable flag xxxIE for the return factor and set the IE flag in the PSW
636. tion control register PDDIR The control flag of the port D direction control register PDDIR is set to 1 for output mode and for input mode Each bit can be set individually if pull up resistor is added or not by the port D pull up resistor control register PDPLU Set the control flag of the port D pull up resistor control register PDPLU to 1 to add pull up resis tor Each bit can be selected individually as output mode by the port D output mode register PDOMD The port D output mode register PDOMD is set to 1 to output the special function data and 0 to use as the general port B Special Function Pin Setup PDO is used as external interrupt 1 pin as well External interrupt 2 can select either P22 or PDO by setting of the external interrupt pin switching control register IRQSEL When IRQ2SEL flag of the external interrupt pin switching control register IRQSEL is 0 P22 is selected and 1 PDO is selected is used as external interrupt 3 pin as well External interrupt 3 can select either P23 or 1 by setting of the external interrupt pin switching control register IRQSEL When IRQ3SEL flag of the external interrupt pin switching control register IRQSEL is 0 P23 is selected and 1 PD1 is selected PD2 is used as I O pin of the timer 4 as well The output mode can be selected by bp2 of the port D output mode register PDOMD by each bit The port D output mode register PDOMD is set to 1 to out
637. to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ P73 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for the TM7IRQ 10 for the TM2IRQ 11 for the TM7IRQ Port 7 IV 65 4 I O Ports IV 66 P74 can be selected as synchronous output by each bit by the port 7 synchronous output control register P7S YO The port 7 synchronous output control register P7SYO is set to 1 for synchronous output and for general port The port 7 synchronous output event selection register P7SEV can select the event that generates synchro nous output When of the port 7 synchronous output event selection register P7SEV is 00 IRQ2 P22 IRQ2A input is selected and 01 for
638. trans mission is completed the serial 0 transmission interrupt SCOTIRQ is generated Reception Once a start condition is received reception is started after the transfer bit counter that counts transfer bit is cleared When the reception is completed the serial O reception interrupt SCORIRQ is generated Full duplex communication On full duplex communication the transmission and reception can be operated separately at the same time The frame mode and parity bit of the used data on transmission reception should have the same polarity B Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SCOFMI to 0 flag of the SCOMD2 register If the SCOCMD flag of the SCOMDI register is set to 1 and UART communication is selected the setup by the synchronous serial transfer bit count selection flag SCOLNG2 to 0 is no more valid Operation XI 39 11 Serial interface 0 XI 40 Switch the used pins Switch the used pins to A TXDOA RXDOA or B TXDOB RXDOB by SCOSEL flag of SCSEL register m Data Input Pin Setup The communication mode can be selected from with 2 channels data output pin TXDO pin data input pin RXDO pin or with 1 channel data pin TXDO pin The RXDO pin can be used only for serial data input The pin can be used for serial data input or output The SCOIOM flag of the SCOMDI register can specify which pin RXDO or TXDO i
639. transfer clock Figure 5 9 1 Timing of Serial Transfer Clock Timers 2 3 4 and 5 N The timer output is synchronized to the serial transfer clock by the timer count clock and its frequency is 1 2 of the set frequency set by the compare register Other count timings are the same as the timing of timer operation For the baud rate calculation and the serial interface setup refer to Serial Interface Serial Transfer Clock Output V 47 5 8 bit Timers 48 5 9 2 Setup Example Serial Transfer Clock Setup Example Timer 2 How to create a transfer clock for full duplex UART Serial 4 using with the timer 2 is shown below The baud rate is selected to be 300 bps the source clock of timer2 is selected to be fs 2 at fs 2 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD 0x03F5C bp3 TM2EN 0 2 Select the normal timer operation TM2MD 0x03F5C bp4 TM2PWM 0 bp5 TM2MOD 0 3 Select the count clock source TM2MD 0x03F5C bp2 0 TM2CK2 0 001 4 Select and enable the prescaler output CK2MD 0x03F5E bp2 1 TM2PSC1 0 0 bp0 TM2BAS 1 5 Set the baud rate 2 0x03F5A 6 Start the timer operation TM2MD 0x03F5C bp3 2 1 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the timer 2 counting 2 Set the TM2PWM flag a
640. transfer mode 4 ATC1 automatically transfers two bytes one word of data from any memory space to the I O space special registers 0x03F00 0x03FFF everytime ATC1 activation request occurs Memory pointer 0 Memory pointer 1 00000 to FFFFF 03F00 to 03FFF ATMAP 1 even 2 2 3 2 4 Only lower 8 bits valid 2 3 Figure 18 3 6 Transfer Mode 4 Set the source address in 20 bit memory pointer 0 1 L and set the destination address in the lower 8 bits of memory pointer 1 ATIMAPIL You do not have to set the upper 12 bits of the I O space address 0x03F in ATIMAPIH and ATIMAPIM Always set an even address as the destination I O address in memory pointer 1 When ATC1 transfers one word to the I O space ATC1 can transfer the even address set in memory pointer 1 and the consecutive odd address In transfer mode 4 ATC1 executes a data byte transfer twice to send one data word everytime when activated The value in memory pointer 0 increments everytime a byte length data transfer ends As a result the source address for the next 1 operation is two addresses higher than that for the previous operation In this word length transfer 1 transfers the first data byte to an even address in the I O space and the second data byte to an odd address in the I O space S
641. transmission reception at the start condition enable transmitter receiver should transmit receive at the start condition enable SBTS pin Data is input at the rising edge of the clock 5813 pin Data is output at the falling edge of the clock Figure 14 3 14 Transmission Reception Timing Reception Rising edge Transmission Falling edge SBTS pin Data is input at the rising edge of the clock SBIS pin Data is output at the falling edge of the clock SBOS pin Figure 14 3 15 Transmission Reception Timing Reception Falling edge Transmission Rising edge Operation XIV 25 14 Serial Interface 3 B Communication in STANDBY mode This serial interface is capable of slave reception in STANDBY mode You can return the CPU operation from STANDBY mode to NORMAL mode using communication end interrupt SC3IRQ which is generated after the slave reception In STANDBY mode continuous reception is desabled after data of transfer bit count set by SC3LNG2 0 flags of the SC3MDO register is received Read out the received data from transmission reception shift register SC3TRB after returning to NORMAL mode In STANDBY mode reception with start condition is not available thus disable start condition And set dummy data to tramsmission data buffer TXBUF3 before transition to STANDBY mode NORMAL mode STANDBY mode NORMAL mode Oscillation stabilization T f f waittime C
642. transmission data SDA3B data input output output P94 SBI3B in out P9DIR4 P9PLU4 SBI3B Serial reception data input P95 SBTSB SCL3B in out P9DIR5 P9PLUS5 SBT3B Serial 3 clock input output SCL3B clock input output PAO ANO in out PADIRO PAPLUO ANO Analog 0 input PA1 AN1 in out PADIR1 PAPLU1 AN1 Analog 1 input PA2 AN2 in out PADIR2 PAPLU2 AN2 Analog 2 input in out PADIR3 PAPLU3 AN3 Analog 3 input PA4 AN4 in out PADIR4 PAPLU4 AN4 Analog 4 input PA5 AN5 in out PADIR5 PAPLU5 Analog 5 input PA6 AN6 in out PADIR6 PAPLU6 AN6 Analog 6 input PA7 AN7 in out PADIR7 PAPLU7 ANT Analog 7 input PDO IRQ2B in out PDDIRO PDPLUO IRQ2B External interrupt input 2 PD1 IRQ3B in out PDDIR1 PDPLU1 IRQ3B External interrupt input 3 PD2 TM4IOB in out PDDIR2 PDPLU2 TM4IOB Timer 4 input output PD3 TM5IOB in out PDDIR3 PDPLU3 TM5IOB Timer 5 input output PD4 TM7IOB in out PDDIR4 PDPLU4 TM7IOB Timer 7 input output PD5 BUZZER in out PDDIR5 PDPLU5 BUZZER Buzzer output PD6 SYSCLK in out PDDIR6 PDPLU6 SYSCLK System clock output 12 Pin Description 1 3 3 Pin Functions gt Table 1 3 2 Pin Functions Chapter 1 Overview Name NO I O Other Function Function Description Vss1 14 Power supply pins Apply 3 0 V to 3 6 V to 1 2 3 0 V to 5 5 V to and 0 V to
643. trol Registers eet erit dpi iere op ce VII 5 7 2 2 Programmable Timer ene VII 6 7 2 3 Timer 6 Enable Registers ied ettet tte ete eet re VII 7 7 2 4 Timer Mode Registers IRURE VII 8 133 8 bit Freerunning TImet s c ecco ete eee ee te reete VII 9 7 3 Operation ek BANA iain EG dep REO ane teen dep VII 9 7 322 Setup Example eet Het RR i eh secte e ei VII 13 TA Time Base Timer oce RENDUM REA i VII 15 T A Operation ss i eter aoo ep epu VII 15 142 Setup Example op teh E HE ORG E ME repel 17 Chapter 8 Remote Control Functions a 1 S L OVertVIeW isnt ie Ri AE luma fee Rie tees VIII 2 8 11 F nctions sss eis Ae ee dede Una VIII 2 Contents 7 8 2 Block Diagram edet tene VIII 3 8 2 Control Registers s ceti Wee als detinentur epe egenis 4 8 21 Control Registers n aku RE e HR 4 8 2 2 Remote Control Career Output Control Register VIII 5 8 3 MS sie oh ETICHETTE d VIII 6 8 2 cien err ERREUR I RE ERE tre ciere prep SE ere Ld e re VIII 6 3 2 Set p ExampleSr uu Pe ayka en aaa 8 Chapt r 9 Watehdog
644. trol register should be operated when the maskable interrupt enable flag MIE of PSW 15 0 Table 3 2 3 External Interrupt 0 Control Register IRQOICR OxOSFE2 bp 7 6 5 4 3 2 1 0 Flag IRQOLV1 IRQOLVO REDGO IRQOIE IRQOIR At reset 0 0 0 0 0 Access R W IRQOLV1 IRQOLVO Description External interrupt level flag rupt requests The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for inter REDGO External interrupt valid edge flag at the standby mode 0 Falling edge 1 Rising edge IRQOIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt III 20 IRQOIR Control Registers External interrupt request flag 0 No interrupt request 1 Interrupt request generated 3 Interrupts B External Interrupt 1 Control Register IRQ1ICR The external interrupt control register controls interrupt level of external interrupt 1 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW 15 0 Table 3 2 4 External Interrupt 1 Control Register IRQ1ICR 0x03FE3 bp 7 6 5 1 0 Flag IRQ1LV1 IRQ1LVO REDG1 IRQ1IE IRQ1IR At reset 0 0 0 0 0 Access R W Description IRQ1LV1 External interrupt level flag IRQ1LV0 The CPU has interrup
645. ull up resistors are dis P86 70 LEDO D6 abled high impedance output P87 71 LEDO D7 P90 76 VO SBOOB TXDOB port 9 6 bit COMS tri state port P91 77 SBI0B RXD0B Each bit can be set individually as either an input or output by the P92 78 SBTOB P9DIR register A pull up pull down resistor for each bit can be P93 79 SBO3B SDA3B selected individually by the P9PLU register P94 80 SBI3B At reset the input mode is selected and pull up resistors are dis P95 81 SBT3B SCL3B abled high impedance output PAO 92 VO ANO Input port A 8 bit COMS tri state I O port PA1 93 AN1 Each bit can be set individually as either an input or output by the PA2 94 AN2 PADIR register A pull up pull down resistor for each bit can be PA3 95 AN3 selected individually by the PAPLU register A pull up pull down PA4 96 AN4 resistor for each port can be selected individually by the SELUD PA5 97 AN5 register However pull up and pull down resistors cannot be 6 98 AN6 mixed PA7 99 AN7 At reset the input mode is selected and pull up resistors are dis abled high impedance output PD0 82 VO IRQ2B Input port D 8 bit COMS tri state port PD1 83 IRQ3B Each bit can be set individually as either an input or output by the PD2 84 TM4IOB PDDIR register A pull up pull down resistor for each bit can be 85 TM5IOB selected individually by the PDPLU register PD4 86 TM7IOB At reset the input mode is selected and pull up resistors are
646. un error detection 0 No error 1 Error SC1ERE Error monitor flag 0 No error 1 Error Control Registers XII 11 12 Serial interface 1 XII 12 12 3 Operation Serial interface 1 can be used for both clock synchronous and full duplex UART 12 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 12 3 1 shows activation factors for communication At master communication the transfer clock is gener ated by setting data to the transmission data buffer TXBUF1 or by receiving a start condition Except during communication the input signal from is masked to prevent errors by noise or so This mask can be released automatically by setting a data to TXBUFI access to the register or by inputting a start con dition to the data input pin Therefore at slave communication set data to TXBUFI or input an external clock after a start condition is input However the external clock should be input after more than 3 5 transfer clock interval after the data set to TXBUFI This wait time is needed to load the data from TXBUFI to the internal shift register Table 12 3 1 Synchronous Serial Interface Activation Factor Activation factor Transmission Reception At master Set transmission data Set dummy data Input start condition At slave Input clock after transmission data Input clock after dummy data is set is set Input
647. up Resistor Control Register IV 92 P9ODC 4 R W Port 9 Nch Open drain Control Register IV 92 R W Readable Writable Port 9 Output Register P9OUT 0x03F 19 gt F E E TF p E RU At reset Access R W R W R W R W R W R W Flag Description P9OUT5 P9OUT4 P9OUT3 P9OUT2 P9OUT1 P9OUTO Output data 0 Output L VSS level 1 Output H VDD level S O Q O Port 9 Chapter 4 I O Ports Port 9 Input Register P9IN 0x03F29 bp gt O Q O Flag P9IN5 P9IN4 P9IN3 P9IN2 P9IN1 P9IN0 Description Input data 0 Pin is L VSS level 1 Pin is H VDD level Port 9 Direction Control Register P9DIR 0x03F39 Flag P9DIR5 P9DIR4 P9DIR3 P9DIR2 P9DIR1 P9DIRO At reset 0 0 0 0 0 0 Access R W R W R W R W R W R W bp gt O Q O Flag P9DIR5 P9DIR4 P9DIR3 P9DIR2 P9DIR1 P9DIR0 Description mode selection 0 Input mode 1 Output mode Port 9 IV 91 4 I O Ports Port 9 Pull up Resistor Control Register P9PLU 0x03F49 P9PLU5 P9PLU4 P9PLU3 P9PLU2 P9PLU1 P9PLUO 0 0 0 0 0 0 bp gt O Q O P9PLU5 P9PLU4 P9PLU3 P9PLU2 P9PLU1 P9PLUO Flag Description 1 Added Pull up resistor selection 0 Not added Port 9 N
648. using the bus to transfer data XVIII 12 Operation 18 Automatic Transfer Controller When an external interrupt is selected as an ATC1 trigger factor specify the activation valid edge by the REDGn flag of the external interrupt control register and the EDGSELn flag of the both edges interrupt control register EDGDT Chapter 3 3 3 1 External interrupts a Set the valid edge for external interrupts before ATC1 activates B Data transfer The basic operation cycle is the byte data transfer cycle in which ATCI transfers a single byte of data This operation consists of two instruction cycles a load and a store cycle In the load cycle ATC1 reads the data from the source address of the source memory and in the store cycle 1 stores the read data to the destination address of the destination memory ATC1 transfers word length data or a multi byte stream of data by repeating the byte data transfer cycle as many times as necessary B Transfer end Once it has transferred all the data ATC1 generates an interrupt and stop the automatic transfer In this way the ATCI block bypasses the software and automatically transfers data in a continuous DMA operation In both the load and store cycles the read and write access occurs to the memory exactly as it does in a normal instruction execution This means that the access timing is different depending on the memory space Also the wa
649. ut output output SC1MD1 SC1SBO SC1MD1 SC1SBIS SC1MD1 SC1SBTS S Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain PSODC P3ODCO P30DC P30DC2 Output mode Input mode Output mode Input mode P3DIR P3DIR0 P3DIR P3DIR1 P3DIR P3DIR2 Pull up setup Added Not added Added Not added Added Not added P3PLU PSPLUO P3PLU P3PLU2 Operation XII 29 12 Serial interface 1 XII 30 B Pins Setup with 2 channels at transmission Table 12 3 10 shows the setup for synchronous serial interface pin with 2 channels SBOI pin pin at trans mission SBII pin can be used as a port Table 12 3 10 Setup for Synchronous Serial Interface Pin with 2 channels at transmission Setup item Data output pin Serial unused pin Clock I O pin 5801 pin SBI1 pin SBT1 pin Clock master Clock slave SC1MD1 SC1MST Port pin P30 P31 P32 Serial data input SBI1 selection SC1MD1 SC11OM Function Serial data input 1 input Transfer clock input Transfer clock input output output SC1MD1 SC1SBO SC1MD1 SC1SBIS SC1MD1 SC1MST S Style Push pull Nch Push pull Nch open Push pull Nch open open drain drain drain P30DC P30DC0 P30DC P30DC2 Output mode Output mode Input mode P3DIR P3DIR0 P3DIR P3DIR2 Pull up setup Added Not added Added Not added Added Not added P3PLU P3PLU0 P3PLU P3PLU2 O
650. ut Control Register IV 60 R W Readable Writable Port 6 Output Register P6OUT 0x03F16 7 F p T E E T p At reset Access R W RAN R W R W R W R W R W R W bp Flag Description Output data 0 Output L VSS level 1 Output H VDD level S O Q O IV 58 Port 6 Chapter 4 I O Ports Port 6 Input Register P6IN 0x03F26 bp Flag Description gt O Q O P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6INO Input data 0 Pin is L VSS level 1 Pin is H VDD level Port 6 Direction Control Register P6DIR 0x03F36 Flag P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O gt O Q O P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0 I O mode selection 0 Input mode 1 Output mode Port 6 IV 59 4 I O Ports Port 6 Pull up Resistor Control Register P6PLU 0x03F46 PePLU7 P6PLU6 P6PLUS5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLUO 0 0 0 0 0 0 0 0 7 P6PLU7 6 P6PLU6 2 Pull up resistor selection 4 P6PLU4 i 0 Not added 3 P6PLU3 1 Added 2 P6PLU2 1 P6PLU1 0 P6PLU0 Address Output Control Register EXADV 0x03F0E IV 60 Flag EXADV3 EXADV2 EXADV1 l E E At reset 0 0 0 gt
651. ut data lt pointe U R Address output External extension output contorl Figure 4 7 7 P56 Block Diagram mE PLU7 Pull up resistor D gt contorol WEK R pege P5DIR7 VO direction 4 5 control WEK R lt X 1 s P5OUT7 Port output data D d o WEK R x ee BEIN Schmitt trigger input 7 Port input data lt a R Address output External extension output contorl Figure 4 7 8 P57 Block Diagram Port 5 IV 55 4 I O Ports IV 56 48 Port 6 4 8 1 Description General Port Setup To output the data to pins set the control flag of the port 6 direction control register P6DIR to 1 to write the value of the port 6 output register P6OUT To read input data of pins set the control flag of the port 6 direction control register P6DIR to 0 to read the value of the port 6 input register P6IN Each bit be set individually as either an input or output by the port 6 I O direction control register P6DIR The control flag of the port 6 direction control register P6DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 6 pull up resistor control register P6PLU Set the control flag of the port 6 pull up resistor control register P6PLU to 1 to add pull up resistor Port 6 can be selected to address output pin to the external exte
652. utput g event selection E Wek R Reset c o P7SYO2 Synchronous output Rg control Wek R IV 74 Port 7 Figure 4 9 3 P72 Block Diagram tse Pull up pull down resistor selection Pull up pull down resistor control I O direction control Port output data Port input data Address output External Extension output control External interrupt 2 Timer 7 interrupt Timer 2 interrupt Timer 1 interrupt Synchronous output event selection Synchronous output control EN lt no snq eq gt M wo D o WEK VR CK P7IN3 gt gt c 2p ESOS Schmitt trigger input A 5 amp Reset Ys P7SEV1 02 Wek Reset eq Rd P7SYO3 R WEK R Figure 4 9 4 P73 Block Diagram lt 4 Chapter 4 Port 7 I O Ports Mg pm IV 75 4 I O Ports Pull up pull down resistor selection Pull up pull down resistor control direction control Port output data Port input data Chip selection signal External Extension output control External interrupt 2 Timer 7 interrupt Timer 2 interrupt Timer 1 interrupt Synchronous output event selection S
653. utput enable L level output Remote control career output P10 particular function selection Timer 0 Remote control career output VIII 2 Overview 8 Remote Control Functions 8 1 2 Block Diagram B Remote Control Career Output Block Diagram TMOIO output Remote control areer output P 10 RMDTY1 RMOEN TMORM Reserved Timer 0 output Timer 3 output Figure 8 1 1 Remote Control Career Output Block Diagram Overview VIIL 3 Remote 8 Control Functions 8 2 Control Registers 8 2 1 Control Registers Table 8 2 1 shows the registers that control the remote control career output Table 8 2 1 Control Registers RMCTR 0x03F7F Remote control career output control register VIII 5 VIII 4 Control Registers 8 Remote Control Functions 8 2 2 Remote Control Career Output Control Register B Remote Control Career Output Control Register RMCTR 0x03F7F gt p e p p E FE F p j pee 0 0 0 0 0 0 At reset Access gt R W R W R W R W R W R W bp Flag Description Reserved Set always 0 P10 particular functions output selection TMORM 0 TMOIO 1 RMOUT Remote control career output enable 0 L level output 1 remote control career output Remote control career duty RMDTY1 00 1 2 duty RMDTYO 01 1 3 duty 1 Timer
654. uty can be changed consecutively 6 16 bit Timer PWM source waveform A shows H until the binary counter reaches the compare register value from 0x0000 B shows L after the compare match then the binary counter counts up till the overflow C shows again if the binary counter overflow Count Timing of Standard PWM Output when compare register 1 is 0x0000 Timer 7 Here is the count timing at setting 0x0000 to the compare register 1 Count clock TM7EN flag Compare register 1 Binary 0000 0001 moamm 0000 0001 1 counter H TM7IO output PWM output Figure 6 6 2 Count Timing of Standard PWM Output when compare register 1 is 0x0000 PWM output shows H when TM7EN flag is stopped at 0 Count Timing of Standard PWM Output when compare register 1 is 0xFFFF Timer 7 Here is the count timing at setting OxFFFF to the compare register 1 TM7EN flag Compare register 1 Binary oo00 0001 0000 0001 ANS N21 counter TM710O output PWM output L Figure 6 6 3 Count Timing of Standard PWM Output when compare register 1 is OXFFFF 16 bit Standard PWM Output Only duty can be changed consecutively VI 27 6 16 bit Timer To output the standard PWM output set the TM7BCR flag of the TM7MD2 register to 0 to select the full count overflow as the b
655. version should be done several times to value Operation XVI 9 16 A D Converter XV 16 3 1 Setup Input Pins of A D Converter Setup Input pins for A D converter is selected by the ANCH2 0 flag of the ANCTRI register Table 16 3 1 A D Conversion Input Pins Setup ANCHS2 1 0 A D pins 0 0 0 AN pinsO 1 AN pins1 1 0 AN pins2 1 AN pins3 1 0 0 AN pins4 1 AN pins5 1 0 AN pins6 1 AN pins7 A D Converter Clock Setup The A D converter clock is set with the ANCK1 to ANCKO flag of the ANCTRO register Set the A D converter clock Tap more than 500 ns and less than 15 26 ms Table 16 3 2 shows the machine clock fosc fx fs and the A D converter clock TAp calculated as fs fosc 2 fx 4 Table 16 3 2 A D Conversion Clock and A D Conversion Cycle ANCK1 ANCKO A D conversion A D conversion cycle TAp I at high speed oscillation at low speed oscillation fosc 32 MHz fosc 8 38 MHz fosc 32 768 kHz 0 0 fs 2 125 00 ns unusable 477 33 ns unusable 244 14 us 1 fs 4 250 00 ns unusable 954 65 ns 488 28 us 1 0 fs 8 500 00 ns 1 91 us 976 56 us 1 fx x 2 15 26 us 15 26 us 15 26 us For the system clock fs refer to Chapter 2 2 6 Clock Switching 10 Operation 16 A D Converter A D Converter Sampling Time Ts Setup The sampling time of A D converter is set with the ANSHI to 0 f
656. witched to high frequency input high speed mode or to low frequency input low speed mode The system clock is generated by dividing the oscillation clock The best operation clock for the system can be selected by switching its frequency by software A machine cycle min instructions execution in the normal mode is 250 ns when fosc is 8 MHz and when fosc is 20 MHz a machine cycle is 100 ns A machine cycle in the double speed mode is 62 5 ns when fosc is 32 MHz and 100 ns when fosc is 10 MHz The package is 100 pin QFP Overview 1 1 2 Product Summary r r Chapter 1 Overview This manual describes the following models of the MN101E01L series These products have identical functions Please note that mainly dealed here is MN101E01L and MN101EF01M is described in the separate volume Table 1 1 1 Product Summary Model ROM Size RAM Size Classification MN101E01K 256 KB 10 KB Mask ROM version MN101E01L 320 KB 14 KB Mask ROM version MN101E01M 384 KB 24 KB Mask ROM version MN101EF01M 384 KB 24 KB Flash EEPROM version Under development Overview 1 Overview 1 2Hardware Functions CPU Core MN101E Core LOAD STORE architecture 3 stage pipeline Half byte instruction set Handy addressing Memory space 1 MB instruction data share Machine cycle High speed Normal 62 5 5 32MHz 3 0Vto3 6 V mode 100 0 10 MHz 3 0 V to 3 6 V Low speed
657. wn resistor control register PAPLU to 1 to add pull up pull down resistor Port 4 can be selected to add pull up resistor or pull down resistor by bpO of the pull up pull down resistor selec tion register SELUD P40 P42 can select Nch open drain output by each bit by the port 4 Nch open drain control register PAODC The port 4 output mode register is set to 1 for the Nch open drain output and 0 for the push pull output Special Function Pin Setup P40 is used as output pin of the serial 4 transmission data or the UART 4 transmission data as well When the SC4SBOS flag of the serial interface 4 mode register 1 SC4MD1 is set to 1 it is output pin of the serial data Also the push pull output or the Nch open drain output can be selected by the setup of the port 4 Nch open drain control register P41 is used as input pin of the serial 4 reception data or the UART 4 reception data as well P42 is used as I O pin of the serial 4 clock as well When the SCASBTS flag of the serial interface 4 mode regis ter 1 SC4MD1 is set to 1 it is output pin of the serial clock Also the push pull output or the Nch open drain output can be selected by the setup of the port 4 Nch open drain control register Port 4 IV 41 4 I O Ports 4 6 2 Registers The following Table shows registers that control the Port 4 Table 4 6 1 Port 4control register Registers Address Fu
658. x00 MEMCTR Ox03F01 R W Memory control register OxCB OxO3FE2 XxxICR io R W 22 interrupt control 0x00 0x03FEF 9 3 After oscillation stabilization wait time internal reset is released and program is started from the address writen at address 0x4000 at interrupt rector table VDD NRST OSC2XO IRST nternal RS Oscillation stabilization wait time Figure 2 7 2 Reset Released Sequence The value of internal RAM is uncertain when power is applied to it Y It needs to be initialized before used 54 Reset Chapter 2 CPU Basics 2 7 2 Oscillation Stabilization Wait time E a rs Oscillation stabilization wait time is the period from the stop of oscillation circuit to the stablization for oscilla tion Oscillation stabilization wait time is automatically inserted at releasing from reset and at recovering from STOP mode At recovering from STOP mode the oscillation stabilization wait time control register DLYCTR is set to select the oscillation stabilization wait time At releasing from reset oscillation stabilization wait time is fixed The timer that counts oscillation stabilization wait time is also used as a watchdog timer That is used as a run away detective timer at anytime except at releasing from reset and at recovering from STOP mode Watchdog timer is initiated at reset and at STOP mode and starts counting from the initialize value 0x0000 when system clock
659. xternal interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Ill 25 Chapter 3 Interrupts Timer 0 Interrupt Control Register TMOICR The timer 0 interrupt control register TMOICR controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 9 Timer 0 Interrupt Control Register TMOICR 0x03FE8 bp 7 6 5 4 3 2 1 0 Flag TMOLV1 TMOLVO TMOIE TMOIR At reset 0 0 0 0 Access R W Description TMOLV1 Interrupt level flag TMOLVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Ill 26 Control Registers 3 Interrupts Timer 1 Interrupt Control Register TM1ICR The timer 1 interrupt control register controls interrupt level of timer interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 10 Timer 1 Interrupt Control Register TM1ICR 0x03FE9 bp 7 6 1 0 Flag TM1LV1 TM1
660. y as either an input or output by the port 1 I O direction control register PIDIR The control flag of the port 1 direction control register PI DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 1 pull up resistor control register PIPLU Set the control flag of the port 1 pull up resistor control register P1PLU to 1 to add pull up resistor Each bit can be selected individually as output mode by the port 1 output mode register The port 1 output mode register PIOMD is set to 1 to output the special function data and 0 to use as the general port Special Function Pin Setup P10 is used as I O pin of the timer 0 and output pin of the remote control career as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register is set to 1 to output the special function data and 0 to use as the general port P11 is used as I O pin of the timer 1 as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register is set to 1 to output the special func tion data and to use as the general port P12 is used as I O pin of the timer 2 as well The output mode can be selected by bpm of the port 1 output mode register PLOMD by each bit The port 1 output mode register
661. y not be operated properly so finish the communication 17 To change the transfer count bit set the transfer count bit by the SC2LNG2 0 flag of the serial 2 mode register SC2MDO 18 Set the transmission data to TXBUF2 to start the transmission 14 19 Set the IICSTPC flag of the serial 2 control register SC2CTR to 1 so that the stop condition is automatically generated to finish the communication Note Procedures 1 to 2 can be set at once Note Procedures 5 to 9 can be set at once Note Procedures 10 to 11 can be set at once Note Procedures 12 to 13 can be set at once Set each flag in order of the setup procedures Set all the control registers refer toTa ble 13 2 1 except TXBUF2 before start communication 48 Operation Chapter 14 Serial Interface 3 14 Serial Interface 3 14 1 Overview This LSI contains a serial interface 3 that is capable of both clock synchronous IIC single master serial commu nication 14 1 1 Functions Table 14 1 1 shows the serial interface 3 functions Table 14 1 1 Serial Interface 3 Functions Communication style Clock synchronous IIC single master external clock timer 3 output timer 5 output Interrupt SC3IRQ SC3IRQ Pins SBO3 SBI3 SBT3 SDA3 SCL3 3 channels type 2 channels type O SBO3 SBT3 Transfer bit count 1 to 8 bi
662. y set clear SCSIR before enable interrupt 11 Set the transmission data to the serial transmission data buffer TXBUFS The internal clock is generated to start transmission reception After communication ends the serial 3 interrupt SC3IRQ is generated Note Procedures 1 to 2 6 7 and 8 can be set at once Note Procedures 9 and 10 can be set at once Operation XIV 38 14 Serial Interface 3 For communication with 3 channels set the SC3BIS of the SC3MD1 register to 0 to set the serial input to 1 The SBI3 pin can be used as a general port For reception only set the SC3SBOS of the SC3MD1 register to 0 to select port The SBO3 pin can be used as a gen eral port For communication with 2 channels set the SBO3 pin to serial data I O The port direction control register P3DIR switches the For reception set the SC3SBIS of the SC3MD1 reg ister to 1 to select serial input The SBO3 pin can be used as a general port You can shut down the communication by setting the SC3SBOS and the SC3SBIS of the SC3MD 1 register to 0 Set each flag in order of the setup procedures Set all the control registers refer to Table 14 2 1 except TXBUF3 before start communication Set the transfer rate of the transfer clock to under 5 0 MHz with the SC3MD3 register XIV 34 Operation 14 Serial Interface 3 B Transmi
663. ynchronous Output Setup Example Timers 1 and 2 Setup example that latch data of port 7 is output constantly 100 us by using the timer 1 from the synchronous output pin is shown below The clock source of the timer is selected fs 2 fs 2 MHz at operation A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM1MD 0x03F55 bp3 TM1EN 0 2 Select the synchronous output event P7SEV 0x03F2F bp1 0 P7SEV1 0 11 3 Set the synchronous output pin P7SYO 0x03F1F OxFF P7DIR 0x03F37 OxFF 4 Select the normal timer operation TM1MD 0x03F55 bp4 TM1CAS 0 5 Select and enable the prescaler output TM1MD 0x03F55 bp2 0 TM1CK2 0 01 6 Select and enable the prescaler output CK1MD 0x03F57 bp2 1 TM1PSC1 0 X0 bp0 TM1BAS 1 7 Set the synchronous output event 1 0x03F53 0x63 8 Start the timer operation TM1MD 0x03F55 bp3 TM1EN 1 1 Set the TM1EN flag of the timer 1 mode register TM1MD to O to stop the timer 1 counting 2 Set the P7SEV1to 0 flag of the pin control register P7SEV to 11 to set the synchronous output event to the timer 1 interrupt 3 Set the port 7 synchronous output control register P7SYO to OxFF to set the synchronous output pin Set the port 7 direction control register P7DIR to OxFF to set port 7 to output mode 4 Set the TM1CAS flag of the TM1MD register to 0 to sele
664. ynchronous output control IV 76 Port 7 Rege r4 P7DWN ay Reset r4 R P7PLU4 Res R TOME Hn P7DIR4 VR 1 M 2 i P7OUT4 16 X o WEK VR 1 Schmitt trigger input 71 4 lt lt L J R 00 01 M 10 U 11 x Reset 2 P7SEV1 02 ort q S WEK R E Reset d P7SYO4 WEK R Figure 4 9 5 P74 Block Diagram 10277 Chapter 4 I O Ports 4 Reset P7DWN Pull up pull down resistor t Q selection WEK R Y re P7PLUS L gt L Pull up pull down resistor Rg control WEK R P7DIR direction control npa 2 E M gt WEK R x 5 T M Y 75 P7OUT5 U ha Port output data ory ali a WEK VR CK i ara Schmitt trigger input P7IN Port input data lt gt U R Read enable signal External Extension output control 2 00 External interrupt 2 91M Timer 7 interrupt 10 Timer 2 interrupt 11 1 interrupt X
665. zer output frequency set by PD5 pin 4 Buzzer output OFF 4 Set the BUZOE flag of the oscillation stabilization wait DLYCTR 0x03F03 control register to DLYCTR 0 to clear and PD5 pin bp7 BUZOE 0 outputs low level When the low oscillation clock fx dividing is selected as the buzzer output frequency and the buzzer output is switched ON from OFF the buzzer dividing counter is not cleared unless more than 1clock of the low oscillation clock is secured a Setup of the buzzer output ON should be done after setup of the buzzer frequency Operation 5 10 Buzzer X 6 Operation Chapter 11 Serial interface 0 11 Serial interface 0 XI 2 11 1 Overview This LSI contains a serial interface 0 that can be used for both communication types of clock synchronous and UART full duplex And the pin is changable to A POO SBOOA TXDOA PO1 SBIOA RXDOA PO2 SBTOA or B P90 SBOOB TXDOB P91 SBIOB RXDOB P92 SBTOB On this text if there are not much differences between port A and port B on the operation Y port A and B are omitted 11 1 1 Functions Table 11 1 1 shows functions of serial interface 0 Table 11 1 1 Serial Interface O functions Communication style Clock synchronous UART full duplex Interrupt SCOTIRQ SCOTIRQ on transmission completion SCORIRQ on reception completion Used pins SBOO SBIO

MN101E01K/01L/01M/F01M LSI User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents