FMC110 User Manual
Contents
1. 5 Controlling the FMC 110 MEE CEL cattails ena de OC NUN UNS 6 1 lemperature S MEME RR mm 6 3 1 Convection 6 3 2 Conduction 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com r1 6 FMC110 User Manual a JS r1 6 S Wana aS 23 Appendix A HPC 24 ADDENGIX CPLD 5 61 14 28 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 4 FMC110 User Manual ae 1 Acronyms and related documents 1 1 1 2 Acronyms ADC DDR ___ Double Data Rate FMC LED LSB Least Significant Bit s MGT MSB Most Significant Bit s PCB PLL Table 1 Glossary Related Documents FPGA Mezzanine Car2. ms oo memo ea oe meme es foun i hr 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 r1 6 FMC110 User Manual January 2011 www 4dsp com 25 FMC110 User Manual r1 6 Table 9 HPC signal description FMC110 ADCO_CLKA_N A D 0 Output Digital data clock from ADC This ADC can operate in ADCO CLKA P mux mode using data port A and data port B ADCO DA lt 11 0 gt A D 0 Output LVDS Data port A of 1 ADC Data is valid on both edges of ADCO DA lt 11 0 gt ADCO CLKA P N DDR ADCO OVRA N A D 0 Output LVDS Over range bit synchronous to the samples present on port ADCO OVRA P A of 13 ADC Can be used as sync signal ADCO DB lt 11 0 gt A D 0 Output LVDS Data port B of 1 ADC Data is valid on both edges of ADCO DB lt 11 0 gt ADCO CLKA P N DDR ADCO A D 0 Output LVDS Over range bit synchronous to the samples present on port ADCO OVRB P of 1 ADC Can be used as sync signal ADC1 CLKA N A D 1 Output LVDS Digital data clock from 2 ADC This ADC cannot operate in CLKA P mux mode using data port A only ADC1 DA 11 05 A D 1 Output LVDS Data port A of 2 ADC Data is valid on both edges of ADC1 DA lt 11 0 gt ADC1 CLKA P N DDR ADC1 OVRA N A D 1 Output LVDS Over range bit synchronous to the samples present on po
3. FMC110 User Manual 5 2 SPI Programming SWS no N RESET on the both DAC5681Z devices is shared The SPI programmable devices on the FMC110 can be accessed as described in their datasheet but each SPI communication cycle needs to be preceded with a pre selection byte The pre selection byte is used by the CPLD to forward the SPI command to the right destination The pre selection bytes are defined as follows CPLD ADS5400 1 ADS5400 2 DAC5681Z 1 DAC5681Z 2 AD9517 0x00 0x80 0x81 0x82 0x83 0x84 The CLPD has three internal registers which are described in Appendix B CPLD Register map The registers of the other devices are transparently mapped N CS SCLK SDIO N CS SCLK SDIO N CS SCLK SDIO p 8 bit pre selection P6 P5 P4 P3 P2 1 PO R A5 A4 1 A2 pep 9 T9 8 bit instruction 8 bit register data Figure 11 Write instruction to CPLD registers A1 A0 4 8 bit pre selection P6 P5 P4 P2 P1 RAW 5 A4 1 A2 REEERE 8 bit instruction 8 bit register data Figure 12 Read instruction to CPLD registers A1 A0 p P6 P5 P4 P2 e e e Tes e eT 8 bit pre selection 8 bit instruction 8 bit register data Figure 13 Write instruction to ADS5400 DAC5681Z registers A4 A0 4DSP est distribu par TECHW
4. Clock Reference Clock Sync 2 5V single ended 4 Tree Ira ea EE ET 1 Status amp Control LVDS Sync 1 LVDS Clock 1 E Trigger LVDS Trigger 1 Sync 26 9 LVDS Clock 1 Rx 621 LVDS Ovr Sync 2 1 3 3 e 5 LVDS Data 2x1 5 ADC A 295 8 lt 5 LVDSClock 4 amp e2 LVDS Ovr Sync 1 mmm i LVDS Data 12 ADC B E T 0 08 LVDS Clock 1 555 Rx 5 LVDS Data 16 3 giI cm DACA 9 D LVDS Sync 1 i 5 LVDS Clock 1 LVDS Data 16 DAC 5 Figure 1 FMC110 block diagram 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 6 FMC110 User Manual 1 Sr r1 6 3 Installation 3 1 Requirements and handling instructions The FMC110 daughter card must be installed on a carrier card compliant to the FMC standard e he FMC carrier card must support the high pin count connector HPC 400 pins e he FMC carrier card must support VADJ VIO B voltage of 2 5V LVDS support e Do not flex the card and prevent electrostatic discharges by observing ESD precautions when handling the card 3 2 LVDS requirements The A D channels based on 115 ADS5400 can operate in 1 bus or 2 bus mode In 1 bus mode all data is transferred to output port A at a maximum rate
5. FMC110 User Manual a JS r1 6 Parameter Device 1 address 1001 000 On chip temperature CSCS eT Table 8 Temperature and voltage parameters 6 3 Cooling Two different types of cooling will be available for the FMC110 6 3 1 Convection cooling The air flow provided by the chassis fans the FMC110 is enclosed in will dissipate the heat generated by the on board components A minimum airflow of 300 LFM is recommended Optionally low profile FANs can be glued on top of the A D devices The card has a FAN power connection that can be switch on and off under carrier card control individually driven from the CPLD For stand alone operations such as on a Xilinx development kit it is highly recommended to blow air across the FMC and ensure that the temperature of the devices is within the allowed range 4DSP s warranty does not cover boards on which the maximum allowed temperature has been exceeded 6 3 2 Conduction cooling In demanding environments the ambient temperature inside a chassis could be close to the operating temperature defined in this document It is very likely that in these conditions the junction temperature of power consuming devices will exceed the operating conditions recommended by the devices manufacturers mostly 85 C The FMC110 is designed for maximum heat transfer to conduction cooled ribs A customized cooling frame that connects directly to the surface of the A D devices is allowed con
6. 4 5 3000MHZz is used The maximum input voltage range is programmable in the A D device from 1 5Vp pto 2 0Vp p 4 5 Analog output channels The FMC110 has two single ended analog outputs AC coupled from the D A device An RF transformer TC4 1W 3 800MHZz is used The analog outputs are designed to drive a 500 load The maximum output voltage range is 1 0V p p 4 6 External clock input The external clock input can be configured in two ways see also Figure 5 1 Sample clock input connecting to the clock input of the AD9517 2 Reference clock input connecting to the reference input of the AD9517 4 7 External trigger sync input The external trigger input can be configured in different ways build options The trigger input can be 50Q terminated accepting most common high speed signalling standards like single ended LVPECL As a build option the 50O termination can be removed to support LVITL LVCMOS and similar input standards Differential input is also possible using the coax shield as inverted signal By default the input is DC coupled with a 10k termination to ground Optionally the trigger input can be used as sync input synchronizing local A D and D A converters or synchronizing multiple FMC110 cards to FMC RESET SYNCOUT to FMC ADC 1 TRIGGER Any Level to LVDS 1 2 Fanout SYNC_FROM_FPGA_P N Fs 4 from Clock Tree RESET SYNCOUT to FMC 0 ADC 2 SYNCSRC_SEL 1 0 Figure 3 A D Synchronization topology In o
7. of 1Gbps per DDR LVDS pair In 2 bus more the data is de multiplexed over output port A and B at a maximum rate of 500Mpbs per DDR LVDS pair Output port B of one A D channel is not available due to the limited amount of LVDS connections on the FMC connector In 2 bus mode the sync feature can be used to re align the data coming from the two separate paths on the carrier board Each D A channels have an independent DDR LVDS data bus The full rate of 1Gsps is supported but the digital transfer rate can be lowered by enabling the interpolation x2 or x4 in the D A devices 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 7 FMC110 User Manual 1 Sr r1 6 4 Design 4 1 Phycisal specifications 4 1 1 Board Dimensions The FMC110 card complies with the FMC standard known as ANSI VITA 57 1 The card is a single width conduction cooled mezzanine module with region 1 and front panel I O 4 1 2 Front panel coax inputs There are 6 coax connectors available from the front panel From top to bottom 1 analog input A 1 analog output 2 analog output 2 analog input D clock input CL trigger input TR Figure 2 Bezel drawing 4 1 1 Front panel HDMI I O The 19 pins HDMI connector on the front panel 1 holds 4 Multi gigabit transceivers 2 Tx pairs 2 Rx pairs and 4x LVTTL I O 5V tolerant Contact 4DSP for other conf
8. 0 User Manual January 2011 www 4dsp com 27 FMC110 User Manual JS 1 6 Appendix B CPLD Register map 00 External Trigger Reset resetting the clock tree is normally not required This bit is not self clearing D A device SPI reset Normal operation Reset resetting the D A device is normally not required This bit is not self clearing Table 11 Table 11 Register CPLD_REGO description Fano rane raw Fano Do omo Table 12 Register CPLD REG 1 definition 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual JS 1 6 Power control for FAN header x 0 to 3 Apply power to FAN header x 1 Cut power to FAN header x mo staTus iD Table 14 Register CPLD_REG2 definition read _ Desrpion Logic function NOT REFMON AND LD AND STATUS AND INT All status signals indicate OK 4 One or more status signals indicate ERROR Table 16 Register CPLD REG2 definition write 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 29 FMC110 User Manual esr r1 6 Writing to this register determines which status signal is reflected on the LED www m Table 17 Register CPLD REG2 description write 4DSP est distribu par TECHWAY www techwa
9. AY www techway fr info techway fr 33 0 1 64 53 37 90 January 2011 FMC110 User Manual www 4dsp com 20 FMC110 User Manual 1 Sr r1 6 N_CS SCLK snio spe ee ras ropa bo pe e Te Ts Te Te Te eT TT 8 bit pre selection 8 bit instruction 8 bit register data Figure 14 Read instruction to ADS5400 DAC5681Z registers A4 A0 N_CS SCLK soio e rer ofi io epe T e 8 e e T T T T T T gt 8 bit pre selection 16 bit instruction 8 bit register data Figure 15 Write instruction to AD9517 registers A12 A0 N_CS SCLK soio ee Ps eno eee oT T8 T TT T5 T T 8 bit pre selection 16 bit instruction 8 bit register data Figure 16 Read instruction to AD9517 registers A12 A0 6 Environment 6 1 Temperature Operating temperature e 40C to 85 Industrial Storage temperature 40C to 120C 6 2 Monitoring The onboard monitoring may be used to monitor the voltage on the different power rails as well as the temperature of the A D devices It is recommended that the carrier card and or host software uses the power down features in the case the temperature is too high Normal operations can resume once the temperature is within the operating conditions boundaries 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 21
10. C connection The user should NOT reprogram or erase the CPLD 4 21 FMC HPC The high pin count connector has 4 dedicated LVDS clock pairs and can host up to 80 LVDS data pairs Refer to appendix A for a detailed pin out 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 9 FMC110 User Manual a JS r1 6 Pais Clock pairs Data pairs wosto J o f oo ssm J 1 3 ooo mcnn o posom f e 1 ooo Amet wescek 9 posom f e oo posca 31 o posom f e 0 pg f e wescek o posse f 1 soa f 16 pog f 7 wescek e z5VVOmwedtoCeID f 24 ZSVOmwedtoFRONT f 2 9 Table 3 HPC signal usage Signal CLK3 BIDIR P N is not connected 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 10 FMC110 User Manual 1 Sr r1 6 4 3 Main characteristics Analog inputs Max 1 5Vp p to 2 0Vp p programmable Input voltage range Contact 4DSP for a 1Vp p option to match the A D input voltage range with the D A output voltage range In
11. FMC110 User Manual Sr r1 6 FMC110 User Manual E Yu ELLE 23 1 MES Re L p Ld pem ae LES a Contact www techway fr TECHWAY S A S 19 Avenue de B t Oslo Villebon sur Yvette 91953 Courtaboeuf Cedex France T 33 0 1 64 53 37 90 F 33 0 1 64 53 17 74 4DSP LLC 10713 Ranch Road 620 N Suite 522 Austin TX 78726 USA Email support 4dsp com This document is the property of 4DSP LLC and may not be copied nor communicated to a third party without the written permission of 4DSP LLC O 4DSP LLC 2010 FMC110 User Manual a IS r1 6 Revision History EL NEN KENN 2010 06 01 Initial release 1 1 2010 07 01 Update in Temperature and voltage parameters table 2010 09 01 Added details about programming the FMC110 1 2 including SPI timing waveforms Added FMC signal description in the Appendix Added CPLD register definition in the Appendix Z e 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 2 FMC110 User Manual Table of Contents 1 Acronyms and related documents 1e eere eee eene iom 1 2 Related DOCUMENMS ccccccccceeecceeeceeeecee
12. d FMC standard ANSI VITA 57 1 2010 Datasheet ADS5400 TI Datasheet DAC5681Z TI Datasheet AD9517 Analog Devices Datasheet ADT7411 Rev B Analog Devices 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com r1 6 FMC110 User Manual r1 6 2 General description The FMC110 is a dual channel A D and dual channel D A FMC daughter card The card provides two 12 bit A D channels and two 16 bit D A channels that enable simultaneous sampling at a maximum rate of 1 Gsps The sample clock can be supplied externally through a coax connection or supplied by an internal clock source optionally locked to an external reference Additionally a trigger input for customized sampling control is available The FMC110 daughter card is mechanically and electrically compliant to FMC standard ANSI VITA 57 1 The card has a high pin count connector front panel I O and can be used in a conduction cooled environment The FMC110 allows flexible control on clock source sampling frequency and calibration through a SPI communication bus Furthermore the card is equipped with power supply and temperature monitoring and offers several power down modes to switch off unused functions MGT 4 LVTTL 4
13. ecceeeceueeceeecsusessueeeeeeseesseessaeeens 2 3 1 Requirements and handling 4 1 1 Board SE 4 1 2 Front panel coax 4 1 1 Front Danel onpaper ET EEr SEE 4 1 1 Front VO LVTTL TIL 4 2 Electrical specifications cccccecceeccsecceeeceeeceeeceueceeeceeeceusseeesaeeseeeseeesaeees 421 EE IEEE cen A2 Avo AC De DTE EU Ris 4 4 Analog input channels cccccccseccseecseeeeeeeeeeeeeeeeeeeeeseeeeaeeseeseeeseeeseeeseeees 4 5 Analog output channels cccccccccseccseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeseeeeeeeeeeees 46 External 7 Extemal C UA ERREUR TT 49 Multi Gigabit TranSCelvelrS cccccccsecccsecceececeeecceeeceucecseeseueesueeseeessueensess 4 10 Power supply cee 4 11 Parallel A D operation 26 2 4 12 Synchronizing multiple cards
14. eference input of the AD9517 or the 2 RF switch e CLKSRC SEL1 connect either the onboard VCXO or the external clock to the clock input of the AD9510 This signal also controls the VCXO power supply e CLKSRC SEL2 enables disables the onboard reference oscillator 4 9 Multi Gigabit Transceivers The FMC connector hosts 10 MGT pairs 10 Tx and 10 Rx pairs These are connected to two 38 pins MICTOR headers The arrangement is such that different interconnect topologies are supported The VCXO should be powered down to avoid interference with the external clock when external clock is used 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 14 FMC110 User Manual eta ngs 180 88 B g E Gag Gaga GG dg dd gt 113133232 321727 0 1111111 111 m E 5 aH 2 5 Th o II Lia tT ty fT a EEHEHE 5 m 7 gt 5 sleet EHEE HIR a coe es 5 i W IINE j H m a m LET oe J E es oe ee as Ce en cere niri arri ri rri lef Y eae rer Cs ee Hj SSSR 1 SRS ES Figure 7 4DSP CPCI board stack slot to slot 4DSP est distribu TECHWAY www techway
15. fference The out of phase clocks are generated locally The analog signal needs to be split externally Fs 5096 UUU U CLOCK Fs 4 25 optional 1016 TRIGGER SYNC AIN 1 ADC 1 FMC110 SIGNAL AIN 2 ADC 2 Figure 8 Parallel A D operation Clock generation Analog Input SPLITTER 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 17 FMC110 User Manual a JS r1 6 Gain phase and offset errors may be compensated by the calibration features of the ADS5400 when not exceeding the programmability range refer to Table 4 The INL integral non linearity of the converters needs to be taken into account INL represents the number of LSBs the output of a converter is from the expected output for a given input voltage For example if a converter would ideally put out a code of N for an input voltage M but actually puts out a code N 2 then the INL at that point is two The ADS5400 has an INL of 2 LSB 4 LSB maximum When interleaving converters the output codes could differ by as much as 8 LSB for the same input voltage and may drastically reduce the number of effective bits A single device has a typical performance of 57dBFS Fin 1 2GHz The INL specification of the ADS5400 makes high performance interleaving difficult A very rough estimation is that
16. fr info techway fr 33 0 1 64 53 37 90 January 2011 FMC110 User Manual www 4dsp com 15 FMC110 User Manual Pin Signal Midplate Signal Pin _ GND 4 _5 0 N GND 6 7 9 TX1P GND 17 N GND RO N 18 GND GND GND_ ew map 2 GND 29 GND 4 GND 33 ND G 33 100 GND GND GND FLJ no Pin Signal Midplate Signal Pin HII E ES 5 GND GND 8 s 14 _15 RU P GND TX7_P 16 _17 RX7 N GND TX7_N 18 GND GND GND 20 eno msp zr 23 RX6 N GND__ TX6_N 24 25 GND GND GND 26 27 5 P TX5_P 28 29 RXS_N GND 5 N 30 GN CM 32 33 2 ES 37 38 O GND os enw GND GND GND_ Table 5 MGT connector pin out A low phase noise 125MHz XTAL is used as reference clock A 1 2 LVDS fan out buffer is used to fed to reference clock to both connections on the FMC connector The pairs marked with connects to either the MICTOR header or the HDMI connector The assembly is determined with 00 resistors A maximum of four pairs can connect to the HDMI connector Contact 4DSP for custom configurations 4 10 Power supply Power is supplied to the FMC110 card through the FMC connector The pin current rating is 2 but the overall maximum as specified by the FMC s
17. igurations 1 M2C P lt 0 gt 20 GND 2 sed 1 NC 3 J DPMX NO 18 4 J DPMCPd 1 NC 6 DPMCN lt I gt 15 FRONLIO2 8 Shield 13 FRONLIOZ2 9 2 22 12 Nc Table 2 HDMI connector pin out 4 1 1 Front I O LVTTL TTL A voltage translator is used for the LV TTL signals available on the front panel The FMC side is 2 5V The front side is either 3 3V for LVTTL or 5 0V for TTL build option These inputs are 5V tolerant when powered with 3 3V The direction is controlled by the CPLD 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 8 FMC110 User Manual a JS r1 6 4 2 Electrical specifications The FMC110 uses high speed LVDS outputs and require 2 5V on VADJ power supply supplied by the carrier card The voltage on VIO_B pins supplied by the FMC is also 2 5V VIO B is directly connected the VADJ on the FMC110 4 2 1 EEPROM The FMC110 card carries a 2Kbit EEPROM 24LC02B which is accessible from the carrier card through the bus The EEPROM is powered by 3P3VAUX The standby current is only 0 01 when SCL and SDA are kept 3PSVAUX level These signals may also be left floating since pull up resistors are present on the card 4 2 1 JTAG The CPLD device is included in the JTAG chain accessible from the FM
18. in case there is no external reference present A VC X O is used as internal clock source and can connect to the distribution section instead of the external clock input The distribution section drives the A D and D A devices with the LVPECL outputs One LVDS clock output is connected to the FMC connector as a reference for the digital data transferred to the D A devices One LVDS clock output connects to the synchronisation circuitry 4DSP est distribu TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 13 FMC110 User Manual m esr r1 6 VC X O L C P Q OKH XTA 1 CLKSRC_SEL2 400M mi T Y EE OVER AND MONITOR SWITCH CLKSRC_SELO 3 Y Switch FS CLKSRC_SEL1 outo ao a aes outs LAt D OUT4 RONE me ous gt To Sync gt outs LVDSICMOS M Lx ToFMC 8 AND lt a DIGITAL LOGIC Figure 5 Clock tree 4 8 4 Control The AD9517 supports polarity change on the LVPECL outputs This enables parallel operation of the A D converters see section 4 11 The clock tree contains two RF switches ADG918 and requires the following control signals driven from the CPLD e CLKSRC SELO connects the external clock input to the r
19. put impedance 500 AC coupled Analogue input bandwidth 2 GHz TBD Performance Fin 400 MHz ENOB 8 8 bit SFDR 64 dBc SNRFS 57 dB Gain 24 Calibration Offset 30mV Phase 0 72ps Analog outputs Output voltage range Max 1 0Vp p Load 500 TBD Max 500MHz Performance Fout 400 MHz Analogue Bandwidth External Clock Reference input Input level 250mVp p to 2 0Vp p Input impedance 500 AC coupled 10 100 MHz reference clock Input range 100 1000 MHz sample clock External Trigger Sync input Format 150 mVp p typical LVTTL level supported Input impedance 10kQ DC coupled 500 AC coupled option available Frequency range Up to 500 MHz ADC Output 1 bus mode 12 pairs DDR 1Gbps Output data width 2 bus mode 2x 12 pairs DDR 500Mbps Data Format Two s Complement Offset binary 100 1000 MHz Sampling Frequency Range Internal Clock Reference LVPECL 100 MHz reference clock Format Frequency Range 100 125 200 250 500 or 1000 MHz sample clock contact 4DSP for customized frequencies Table 4 FMC110 daughter card main characteristics 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 11 FMC110 User Manual a JS r1 6 4 4 Analog input channels The FMC110 has two single ended analog inputs AC coupled to the A D devices A wideband RF transformer TC1 1 13M
20. rder to correctly align the digital output samples when A D in 2 bus mode or two A D parallel a reset signal needs to be generated This can be a single pulse a repetitive pulse or a low to high step As a result of the reset input a pulse is generated on the sync output The carrier hardware must use these sync pulses to correctly align the digital output samples 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 12 FMC110 User Manual 1 Sr r1 6 TRIGGER Analog Out from FMC Analog Out Figure 4 D A Synchronization topology synchronization of multiple D A devices in parallel is done through the SYNC input The SYNC signal is driven by the FPGA can be derived from the trigger input Since the SYNC input has an internal 100R termination resistor a 1 2 fan out buffer is used to connect a single LVDS signal to both D A converters 4 8 Clock Tree The FMC110 offers a clock architecture that combines flexibility and high performance Components have been chosen in order to minimize jitter and phase noise to reduce degradation of the data conversion performance The user may choose to use an external sampling clock or an internal sampling clock The clock tree has a PLL and clock distribution section The PLL ensures locking of the internal clock to an external supplied reference There is an onboard reference which is used
21. rdware CLKSRC_SEL e Select sync source based on a SPI command from the carrier hardware SYNCSRC_SEL Generate SPI reset for AD9517 RESET and both DAC5681Z DAC N RESET Control the direction of the front I O transceivers FRONT DIR e Control the FAN header power FAN N EN e Collect local status signals and store them a register which be accessed from the carrier hardware Drive a LED according to the level of the status signals Local Side CPLD FMC Side ADCO N CS 4 ADC1 N CS i DACO N CS lag rai rai DAC1 N CS CLK N CS TO CPLD 0 SCLK TO CPLD 1 SCLK e SDIO NCS FMC_TO_CPLD 2 gt SDIO Shift register CLKSRC_SEL 0 2 SYNCSRC_SEL 0 1 CLK_N_RESET DAC_N_RESET FRONT IO DIR O 3 FAN EN O 3 Ctrl REFMON FMC TO CPLD 3 RN PN INT LD STATUS Y YYY VM INT LED q Figure 10 CPLD architecture Notes SDO on the AD9517 ADS5400 and DAC5681Z devices is not connected SDIO is used bidirectional 3 wire SPI e N SYNC and PD on the AD9517 are not connected e ENA1BUS and ENPWD on the ADS5400 are not connected 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 19
22. rt ADC1 OVRA P A of 2 ADC Can be used as sync signal SYNC FROM FPGA N A D 0 A D 1 Input LVDS Signal used to apply a sync pulse to both ADCs in order to SYNC FROM FPGA P align the digital outputs on sample basis CLK TO FPGA N D A 0 D A 1 Output LVDS Clock to be used as reference clock for generating DAC CLK_TO_FPGA_P clock and data signals Typically 1 2 times the sample clock frequency DACO DCLK N D A 0 Output LVDS Digital data clock to 1 DAC DACO DCLK P DACO DATA N 15 0 D A 0 Output LVDS Data bus to 1 DAC Data should be valid on both edges of DACO DATA lt 15 0 gt DACO DCLK P N DDR 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual r1 6 DAC1 DCLK N D A 1 Output LVDS Digital data clock to 2 DAC DAC1 DCLK P DAC1 DATA lt 15 0 gt D A 1 Output LVDS Data bus to 2 DAC Data should be valid on both edges of DAC1 DATA lt 15 0 gt DACO DCLK P N DDR DAC SYNC N D A 0 D A 1 Input LVDS Signal used as transmit enable for both DACs DAC SYNC P TRIGGER TO FPGA N TRIGGER Output LVDS Representation of the signal connected to the external TRIGGER TO FPGA P trigger input FRONT 1O 3 0 Bidir CMOS VIO Connected to the transceivers on the HDMI connector Table 2 The direction of the transceivers is controlled through a CPLD register 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC11
23. tact 4DSP for detailed mechanical information This conduction cooling mechanism should be applied in combination with proper chassis air flow 7 Safety This module presents no hazard to the user 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 22 FMC110 User Manual 1 Sr 1 6 8 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 9 Warranty Basic Warranty 1 Year from Date of Shipment 90 Days from Date of Shipment included me Warranty 2 Years from Date of Shipment 1 Year from Date of Shipment optional 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 23 FMC110 User Manual a JS r1 6 Appendix A HPC pin out FMC110 ese 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual ae ws meom
24. tandard is limited according to Table 6 Signals IO 0 3 connects to the CPLD and has no defined function yet 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 16 FMC110 User Manual a JS r1 6 Voltage pins Max Amps Max Watt 3A 12 W VADJ 2 5V VIO_B 2 5V 1 15A Table 6 FMC standard power specification The power provided by the carrier card can be very noisy Special care is taken with the power supply generation on the FMC110 card to minimize the effect of power supply noise on clock generation and data conversion Clean analog supply is derived from 12V in two steps for maximum efficiency The first step uses a high efficient switched regulator From this power rail the analog supply is derived with low dropout low noise high PSRR linear regulators At several stages in the power supply there is additional noise filtering The regulators have sufficient copper area to dissipate the heat in combination with proper airflow see section 6 3 Cooling Typical VADJ 3P3V 105mA 12POV 913mA 3P3VAUX Standby 0 01 WA 1 uA Table 7 Typical Maximum current drawn from FMC carrier card The total power consumption 12W 4 11 Parallel A D operation Fs up to 2GHz Both A D converters can operate in parallel capturing the same signal but clocked with 180 degree clock phase di
25. the SNR can decrease below 50dBFS even if phase offset and gain calibration has been performed INL problems can partly be corrected in the digital domain but may require lengthy calibration 4 12 Synchronizing multiple cards Multiple cards can be synchronized together The cards need to be supplied with synchronized clock signals In addition an external synchronization signal is required to be able to align the samples in the digital domain Refer to section 4 7 for details about synchronisation Fs 5096 eM U UUU CLOCK Clock generation Fs 4 2596 TRIGGER SYNC 110 eu gt CLOCK 9 Uu pe TRIGGER SYNC FMC110 gt CLOCK p gt TRIGGER SYNC FMC110 Figure 9 Synchronizing multiple cards 5 Controlling the FMC110 4DSP est distribu par TECHWAY www techway fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 18 FMC110 User Manual r1 6 5 1 Architecture The FMC needs to be controlled from the carrier hardware through a single SPI communication bus The SPI communication bus is connected to a CPLD which has the following tasks e Distribute SPI access from the carrier hardware along the local devices 2x ADS5400 A D converters 2x DAC5681Z D A converters 1x AD9517 Clock Tree e Select clock source based on a SPI command from the carrier ha
26. y fr info techway fr 33 0 1 64 53 37 90 FMC110 User Manual January 2011 www 4dsp com 90
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