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MN101C457 LSI User`s Manual

1. SCOMDS register T SCOSBOM flag ire Reset POPLUO Pull up resistor control DQ Write A Read Mrd PODIRO Lu direction control DQ 4 gt gt Write CK Read gt x P00 S Reset Y g R POOUTO M gt Port output data id DQ U 4 Write CK Read 1 777 X Schmitt input POINO Port input data Read Serial interface 0 reception data input UART reception data input Serial interface 0 transmission data output UART transmission data output SCOMDS register SCOSBOS flag Figure 4 2 2 Block diagram P00 nw Reset Pull up resistor control gt Write Ick Read Reset direction control ES PODIR1 e Write jCK Read cus Reset o Port output data bg POOUT Write Read 777 POIN1 Schmitt input Port input data 4 Read NU Serial interface 0 reception data input UART reception data input Figure 4 2 3 Block diagram P01 Port 0 IV 7 Chapter 4 Ports
2. SCOMDS register SCOSBTM flag BDE Reset POPLU2 Pull up resistor control DQ Write jCK Read pee R PODIR2 Ls direction control 0 gt gt Write Read Y Reset gm a R POOUT2 Port output data g an U Write Read 7 7 X E 4 POIN2 Se input ort input data N Read Serial interface 0 clock input Serial interface 0 clock output SCOMDS register SCOSBTS flag Figure 4 2 4 Block diagram P02 ae hese POPLU6 Pull up resistor control am Write Read nese PODIR6 direction control DQ Write A Read aet S Reset w R POOUT6 Port output data DQ 21 Write A Read 1 X 777 POING a input Port input data Read Buzzer output DLYCTR register BUZOE flag Figure 4 2 6 Block Diagram P06 8 Chapter 4 Ports 4 3 Port 1 4 3 1 Description Port Setup Each bit of the port 1 control I O direction register P1DIR can be set individually to set pins as input or output The control flag of the port 1 direction control register P1DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 1 direction control register P1DIR to 0 and read the
3. 1 ANBUF1 ANBUFO 5 ANBUF10 p E ANBUF11 z ANBUF12 0 13 AID ANBUF 14 51 ANST i contrat ANBUF15 52 ANBUF16 ANBUFOG ANLADE ANBUF17 7 7 7 ANCK1 ANSHO ANSH1 5 3 VDD zu 54 gt 2 2 A D conversion data AN2 M upper 8 bits ANS gt Sample and 10 bits A D comparator N 12 A D conversion data ANS i lower 2 bits AN6 AN7 Vss fs 2 fs 4 M 1442 1 6 0 x 1 48 Figure 11 1 1 A D Converter Block Diagram Overview XI 3 Chapter 11 A D Converter 11 2 Control Registers A D converter consists of the control register ANCTRn and the data storage buffer ANBUFn 11 2 1 Registers Table 11 2 1 shows the registers used to control A D converter Table 11 2 1 A D Converter Control Registers Register Address R W Function Page ANCTRO x 03F90 R W A D converter control register 0 XI 5 ANCTR1 03 91 R W A D converter control register 1 XI 6 X 03F 92 R A D buffer 0 XI 7 ANBUF1 X 03F93 R A D buffer 1 XI 7 ADICR R W A D converter interrupt control register Ill 27 PAIMD R W Port A input mode register 28 PAPLUD X 03F4A R W Port A pull up pull down resistance control register IV 28
4. VII 7 7 3 2 Setup Example owes edle E RR n VII 10 Time Bas Timer eterne tede ee pr RR ERE VII 12 7 4 1 Op ration VII 12 7 4 2 Set p Example omnee eere eem VII 14 Chapter 8 Watchdog Timer OVGEVIGW 1 4 se ertet ee ee et PRA Ert Rte 2 8 1 1 Block Diagrams VIII 2 Control Registers exe ite tics oA Cte esos erecti ato ead VIII 3 Operation pie i n REO Rr E ree 4 8 3 1 Operation s seed eet eite o ie iE 4 8 3 2 Setup Example e tee t een eet 7 OVerVIeW ecelesie ee ed adeo IX 2 9 1 1 BIGCK Dia eee RR RE URBE Ri 2 Control Register iot eco p ces IX 3 Operat On 225 PU OPER P e BI RU PUER IX 4 9 3 1 irte n e ete Sate ee e o IX 4 9 3 2 setup event iei oi oi qe pe 5 Chapter 10 Serial Interface 0 OVeEVIOW Gre ee E eg edet io e nid RR ter ee peer ation 2 10 1 Functions sere eher e He tpi Eins 2 10 I 2 _ 3 Control Registers nap ee ee ete X 4 10 2 1 Re gistetS de Rede Ren RR X 4 10 2 2 Data Buffer Registers X 5
5. 94841 o 5 080 jndino jeues 1ndino 041u09 Andino OIEIALL 1 ZADENL 1 G gt m 4 xn H 3 KC 19 8 16 8 1 OUIEIALL lt E SOEWL 31012118 eyeduio N3ENL eyeduio Y OMOEIAL v FREUE Y IK 00121004005 og OIZIA L lt vis lt 5 Timers 2 3 Block Diagram Figure 5 1 1 V 3 Overview Chapter 5 8 Timers Control Carrier Output Block Diagram Remote control ouput Synchronizing RMCTR Reserved RMDTYO Reserved RMOEN Reserved 2 2 o e Figure 5 1 2 Remote Conirol Carrier Output Block Diagram V 4 Overview Chapter 5 8 Bit Timers 5 2 Control Registers
6. 1 27 1 6 2 Option Check List Uno UU EN ir I 29 Package Dimension eet tette te eret I 30 Pr cautions 4 etie diee depen I 33 1 8 1 General Usage cte eie tege e e oe tire tren I 33 1 8 2 Unused Pins nite eg ERE REED RE REA I 34 1 8 3 Power Supply t RR EE re bos I 36 1 8 4 Power Supply Circuit pt e reete tis I 37 Chapter 2 CPU Basics contents 2 1 2 2 RPG DIDI ep D mb EIE 2 2 1 1 Block Di granm i hee ee 3 2 1 2 CPU Control Registers etre II 4 2 1 3 Instruction Execution Controller sese 5 2 1 4 Pipeline PLoCess reiten em ete pede ie eee s 6 2 1 5 Registers for 4 6 2 1 6 Registers for Dat eee 7 2 1 7 Processor Status Word epi eee t II 8 2 1 8 Addressing Modes eee eere II 10 Memory tee perte e pite ge e pte eb e etu II 12 2 2 1 Memory Mode Eran II 12 2 3 2 4 2 5 2 2 2 single chip Mode etr II 13 2 2 3 Special Function Registers II 14 Bus e II 15 2 3 1 Bus Controller eec p
7. Figure 2 4 2 Operating Mode and Clock Oscillation CPUM x 3F00 R W The procedure for transition from NORMAL to HALT or STOP mode is given below 1 If the return factor is a maskable interrupt set the MIE flag in the PSW to 1 and set the interrupt mask IM to a level permitting acceptance of the interrupt 2 Clear the interrupt request flag xxxIR in the maskable interrupt control register xxxICR set the interrupt enable flag xxxIE for the return factor and set the IE flag in the PSW 3 Set CPUM to HALT or STOP mode Set the IRWE flag of the memory control register MEMCTR to clear interrupt request flag by software The system clock fs is fosc 2 at NORMAL mode and fx 4 at SLOW mode Standby Functions II 19 Chapter 2 CPU Basics 2 4 3 Transition between SLOW and NORMAL This LSI has two CPU operating modes NORMAL and SLOW Transition from SLOW to NORMAL requires passing through IDLE mode A sample program for transition from NORMAL to SLOW mode is given below Program 1 MOV x 3 DO 00 CPUM Set SLOW mode Transition from NORMAL to SLOW mode when the low frequency clock has fully stabilized can be done by writing to the CPU mode control register In this case transition through IDLE is not needed For transition from SLOW to NORMAL mode the program must maintain the idle state until high fre quency clock oscillation is fully
8. 6 5 4 3 2 1 0 2 2 2 2 0 At reset 00 TM2CK2 TM2CK1 TM2CKO Clock source 0 0 fs 1 fs 4 0 fx 0 1 1 210 input 1 0 Synchronous fx 1 Synchronous 210 input TM2PWM Timer 2 operation mode selection 0 Normal timer operation 1 PWM operation TM2EN Timer 2 count control 0 Disable the count 1 Enable the count Figure 5 2 5 Timer 2 Mode Register TM2MD x 03F82 R W Control Registers V 7 Chapter 5 8 Timers 3 Mode Register TM3MD TM3MD V 8 3 2 1 0 TM3PWMITM3CK2 TM3CK1 3 Atreset 00XXX TM3CK2 TM3CK1 Clock source fosc fs 4 fs 16 el eel TMSIO input Timer 2 and Timer 3 cascade connection Synchronous TMSIO input TM3PWM P13 output selection at TM2PWM operation Timer 3 output Timer 2 PWM output Timer 3 count control Disable the count Enable the count Figure 5 2 6 Timer 3 Mode Register TM3MD 03 83 R W Control Registers Chapter 5 8 Bit Timers Control Carrier Output Control Register RMCTR 7 6 5 4 3 2 1 0 RMCTR Reserved RMOEN Atreset 00 0 Reserved Set alwa
9. 9 00 020 7 00 0 10 SEATING PLANE Sealing material EPOXY resin Lead material Alloy of Cu Lead surface processing Pd plate Figure 1 7 3 48 Pin TQFP The package dimension is subjected to change Before using this product please obtain product specifications from the sales office 1 32 Package Dimension Chapter 1 Overview 1 8 Precautions 1 8 1 General Usage iConnection of VDD pin and Vss pin All VDD pins should be connected directly to the power supply and all Vss pins should be connected to ground in the external Please consider the LSI chip orientation before mounting it on to the printed circuit board Incorrect connection may lead a fusion and break a micro controller iCautions for Operation 1 If you install the product close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 Each model has different operating condition Operation temperature should be well considered For example if temperature is over the operating condition its operation may be executed wrongly Operation voltage should be also well considered If the operation voltage is over the operation range it can be shortened the length of its life If the operation voltage is below the operating range it operation may be wrong Precautions I 33 Chapter 1 Overview 1 8 2 Unused Pins mUnused Pins only for outp
10. Figure 4 3 5 Block Diagram P12 P13 P14 Port 1 12 14 IV 13 Chapter 4 T O Ports 4 4 Port 2 4 4 1 Description General Port Setup Port 2 is input port except P27 To read input data of pin read out the value of the port 2 input register P2IN P27 is reset pin When the software is reset write the bp7 of the port 2 output register P2OUT to 0 Each bit can be set individually if pull up resistor is added or not by the port 2 pull up resistor control register P2PLU When the control flag of the port 2 pull up resistor control register P2PLU is set to 1 pull up resistor is added P27 is always added pull up resistor ilSpecial Function Pin Setup P20 to P23 are used as external interrupt pins as well P21 is used as an input pin for external interrupt and AC zero cross To read data of AC zero cross set the bp2 of the pin control register FLOAT1 to 1 and read the value of the port 2 input register P2IN a P23 is not allocated to package types of 42 pin SDIL and 44pin QFP 1 Do not add the pull up resistors to the P23 of 42 pin SDIL and 44pin QFP package types LI IV 14 2 Chapter 4 Ports 4 4 2 Registers 7 6 5 4 3 2 1 0 P20UT7 Atreset 1 2 Output data 0 Low 55 level 1 High level Port 2 output register P2OUT x 03F12 R W 7
11. maskable interrupts 9 disabled 1 xxxLVn xxxIE for each interrupt are enabled Reserved Set always 0 Figure 2 1 3 Processor Status Word PSW 8 Overview Chapter 2 CPU Basics Zero ZF Zero flag ZF is set to 1 when all bits are 0 in the operation result Otherwise zero flag is cleared to 0 Carry flag CF is set to 1 when a from or a borrow to the MSB occurs Carry flag is cleared to 0 when no carry or borrow occurs Flag NF Negative flag NF is set to 1 when MSB is 1 and reset to 0 when MSB is 0 Negative flag is used to handle a signed value WOverflow Flag VF Overflow flag VF is set to 1 when the arithmetic operation results overflow as a signed value Other wise overflow flag is cleared to O Overflow flag is used to handle a signed value interrupt Mask Level IM1 and IMO Interrupt mask level IM1 and IMO controls the maskable interrupt acceptance in accordance with the interrupt factor interrupt priority for the interrupt control circuit in the CPU The two bit control flag defines levels 0 3 Level 0 is the highest mask level The interrupt request will be accepted only when the level set in the interrupt level flag xxxLVn of the interrupt control register xxxICR is higher than the interrupt mask level When the interrupt is accepted the level is rese
12. Setup Procedure Description 1 Enable the binary counter 1 TM5LRS flag of the timer 5 mode initialization register TM5MD to 0 At that time the 5 3 88 initialization of the timer 5 binary counter bp7 TMBCLRS 0 TM5BC is enabled 2 Select the clock source 2 Clock source can be selected by the TM5CK3 1 5 x 3F88 flag of the TM5MD register Actually fs 4 is bp3 1 TM5CK3 1 001 selected 3 Set the interrupt generation cycle 3 Set the interrupt generation cycle to the timer TM50C 78 x F9 5 compare register TM5OC At that timer TM5BC is initialized to 00 4 Enable the interrupt request 4 Setthe TM5CLRS flag of the TM5MD register to generation 1 to enable the interrupt request generation TM5MD x 3F88 bp7 5 5 1 5 Set the interrupt level 5 Set the interrupt level by the TM5LV1 0 flag of TMBICR the timer 5 interrupt control register TM5ICR bp7 6 TM5LV1 0 01 If any interrupt request flag had already been set clear it 6 Chapter 3 3 1 4 Interrupt Setup 6 Enable the interrupt 6 Setthe TMBIE flag of the 51 register to 1 51 x 3FFO to enable the interrupt bp1 5 1 the above steps 1 2 set at once As 50 is set TM5BC is initialized to x 00 to count up When TM5BC matches 5 the timer 5 interrupt request flag is set at the nex
13. 10004 60 ul9A1 6 YLOGM YLOWAW 0 60 14 Chapter 2 CPU Basics 2 3 Bus Interface 2 3 1 Bus Controller The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads Therefore this series realizes faster operation There are three such buses ROM bus RAM bus and peripheral expansion bus I O bus They connect to the internal ROM internal RAM and internal peripheral circuits respectively The bus control block controls the parallel operation of instruction read and data access A functional block diagram of the bus controller is given below Instruction Interrupt queue Program address Operand address control Bus controller Interrupt bus Memory control register Memory mode setting Bus access wait control Address decode Bus arbitor Peripheral extension bus Internal Internal RAM peripheral functions Internal ROM Figure 2 3 1 Functional Block Diagram of the Bus Controller Bus Interface II 15 Chapter 2 CPU Basics 2 3 2 Control Registers Bus interface is controlled by the memory control register MEMC
14. Setup The clock source can be selected from the internal clock or the external clock Here is the internal clock source that can be set by the SCOCK1 to 0 register of the SCOMD1 register Also the internal clock can be divided by 8 by setting the SCOCKM flag of the SCOMD1 register to 1 Table 10 3 3 Synchronous Serial Interface Internal Clock Source Serial interface 0 fs 2 Clock source 5 4 internal clock fs 16 Timer 3 output Data Input Pin Setup 3 channels type clock pin SBTO pin data output pin SBOO pin data input pin SBIO pin or 2 chan nels type clock pin SBTO pin data I O pin SBOO pin can be selected as the communication 5810 pin can be used for only serial data input SBOO pin can be used for serial data input or output The SCOIOM flag of the SCOMDS register can select if the serial data is input from SBIO pin or SBOO pin When data input from 5800 pin is selected to set the 2 channels type the PODIRO flag of the PODIR register controls direction of SBOO pin to switch transmission reception At that time SBIO pin is free to be used as a general port At reception if SCOIOM of the SCOMDS register is set to 1 and serial data input from 5800 is selected 5810 pin is used as a general port Operation 17 Chapter 10 Serial Interface 0 EBUSY Flag When the activation factor is generated shown in table 10 3 1 and the serial interface communication
15. OI Pe OH suce II 15 2 3 2 Control Registers dn Seit ete e re Re tribe ep CU II 16 Standby E nction ier EEG PP 17 2 4 1 OVerVIew e eee dr tete e ei Pete ete ede gu II 17 2 4 2 CPU Mode Control Register esee II 19 2 4 3 Transition Between SLOW and NORMAL nee II 20 2 4 4 Transition to STANDBY Modes essen 22 II 24 2 5 1 Reset Operation ee e Poe nee Pete II 24 2 5 2 Oscillation Stabilization Wait II 26 Chapter3 Interrupts 3 1 3 2 3 3 OVeET VIEW Letto Sock aris Aad iate d 2 3 1 1 En III 3 3 1 2 Block Diagram teet terere III 4 3 1 3 Op eratiOD sro oe nee ce tet e eene Met 5 3 1 4 Interrupt Flag Setu p nose t bete III 14 Control Registers itte hehe te epe Anc et III 15 3 2 1 Auc Mb I III 15 3 2 2 Interrupt Control Registers eene III 16 External Interrupts cscs acere epe ie eire anaes III 28 3 3 1 OVELVICW III 28 3 3 2 Block Diagram be eee Deere emend III 29 3 3 3 Control Registers 3 oe ERG eie pe RERUM eet dur III 31 3 3 4 Programmable Active Edge Interrupt esee III 34 3 3 5 Noise Filter eiie ue e d E EE III 35 3 3 6 AC Zero Cross Detector i ria eite e 38
16. After P13 output selection is set to the timer 2 PWM output TM2PWM mov 08 TM3MD flag 1 the setting should be back bclr TM3MD 3 to the timer 3 output Timer 3 indefinite V 20 8 BitTimer Pulse Output Chapter 5 8 Bit Timers 5 6 8 Bit PWM Output The TMnIO pin outputs the PWM waveform which is determined by the match timing for the compare register and the overflow timing of the binary counter 5 6 1 Operation iOperation of 8 Bit PWM Output Timers 2 The PWM waveform with any duty cycle is generated by setting the duty cycle of PWM H period to the compare register TMnOC The cycle is the period from the full count to the overflow of the 8 bit timer Table 5 6 1 shows PWM output pins Table 5 6 1 Output Pins of PWM Output Timer 2 21 output pin P12 PWM output pin output pin P13 Count Timing of PWM Output at normal Timers 2 TMnEN flag Compare N register i H H H Binary 5 22 counter 00 01 N 1 NH E N 2 FE 00 01 4 N 1 N NH Compare ____ match signal TMnIO output PWM output A B C Set time in the compare register lt PWM basic components overflow time of binary counter Figure 5 6 1 Count Timing of PWM Output at Normal PWM source waveform is while counting up from 00 to the value stored in the co
17. VII 14 Time Base Timer Chapter8 Watchdog Timer re Chapter 8 Watchdog Timer 8 1 Overview This LSI has a watchdog timer This timer is used to detect software processing errors It is controlled by the watchdog timer control register WDCTR And once an overflow of watchdog timer is generated a watchdog interrupt WDIRQ is generated If the watchdog interrupt is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware Reset pin outputs low level 8 1 1 Block Diagram ia Watchdog Timer Block Diagram internal reset release overflow WDIRQ WDCTR WDEN reset input gt __ ____ Y Y R 7 S 15 25 A 5 MUX 15 2790 15 2 Y ROM option R tio overflow UN 1 4 DLYCTR 1 4 1 4 J LDLYSO 1 DLYS1 BUZCKO 1 21 BUZCK1 1 2 BUZOE 1 20 MUX 1 29 Figure 8 1 1 Block Diagram Watchdog Timer buzzer The watchdog timer is also used as a timer to count the oscillation stabilization wait time This is used as a watchdog timer except at recovering from STOP mode and at reset releasing The watchdog timer is initialized at reset or a
18. available fs 2 fs 2 fs 4 fs 4 Clock source 6 16 6 16 Timer 3 output Timer 3 output External clock Maximum transfer rate 5 0 MHz 625 kbps fosc Machine clock High speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 When the transmission and reception are operated at the same time at master communication of the clock synchronous select no start condition 4 Set fs 2 as maximum frequency for external clock X 2 Overview Chapter 10 Serial Interface 0 10 1 2 Block Diagram Serial Interface 0 Block Diagram zx ndyo 6 13w11 8 91 5 Fr 5 I 0 5 AS809S 3 5 QW9090S 110005 2 042005 0005 7 135095 115005 042025 005 29 1025 4 uH800S 5 3HO09S 5 3H300S 1 5 5 0 1005 12006 9 oawoos Lawoos Y N Tan 6 1 Y 101590 380 7 01005 Jejunoo ig fr A pappe Aued yoayo 04002 uoissiusueJ 0 02 5 1 uonipuoo URIS 0402 10109991 vy 1 x 10158118 6 00d QX L 008S 418160
19. fs 2 Y ROM option R overfl ts L 1 2 ow 2 overflow 0 gt 1 4 WDIRQ DLYCTR 1 4 1 4 0 J DLYSO LDLYS1 BUZCKO 1 27 BUZCK1 1 2 BUZOE 40 MUX buzzer Loe e 1 29 Figure 2 5 3 Block Diagram of Oscillation Stabilization Wait Time watchdog timer II 26 Reset Chapter 2 CPU Basics Oscillation Stabilization Wait Time Control Register 7 6 5 4 3 2 1 0 DLYCTR BUZOE BUZCK1 BUZCKO DLYS1 DLYSO Atreset 0xx 00 Oscillation stabilization wait period selection DLYS1 DLYSO 0 0 fg 214 1 fs 2 0 1 0 15 28 1 Do not set Note After reset is released the oscillation stabilization wait period is fixed at 5 214 Buzzer output BUZCK1 BUZCKO frequency selection o 15 2 2 0 1 16 211 1 o fs 21 1 fs 29 BUZOE P06 output selection 0 port data output 1 buzzer output Figure 2 5 4 Oscillation Stabilization Wait Time Control Register DLYCTR x O3F03 R W the Oscillation Stabilization Wait Time At recovering from STOP mode the bit 1 0 DLYS1 DLYSO of the oscillation stabilization wait time control register can be set to select the oscillation stabilization wait time from 2 27 26 x system clock The DLYCTR register is also used for controlling of buzzer functions Chapter 9 Buzzer At releasing
20. 777 777 ERROR NET MUNERE 55 1 gt gt 1000 pF 1 as R lt 500 1 That value is for reference Recommend Connection with A D Converter XI 14 Operation Chapter 12 Appendices Chapter 12 Appendices 12 1 EPROM Version 12 1 1 Overview EPROM version is microcomputer which was replaced the mask ROM of the 101 457 with an elec tronically programmable EPROM There are MN101CP427DP BF HP and PX AP101C42 SDC FBC for 101 457 MN101CP427DP the MN101CP427BF MN101C427HP are sealed plastic Once data is written to the internal EPROM it cannot be erased The PX AP101C42 SDC and PX AP101C42 FBC are sealed in a ceramic package with a window Written data can be erased by exposing the physical chip to intense ultraviolet radiation We offer the 42 pin shrink DIL package the 44 pin flat package and the 48 pin flat package of plastic packages and the 42 pin shrink DIL package and 44 pin flat package of ceramic packages Setting the EPROM version to EPROM mode functions as a microcomputer are halted and the internal EPROM can be programmed For EPROM mode pin connection refer to figure 12 1 2 12 1 3 and 12 1 4 Programming Adapter Connection The specification for writing to the internal EPROM are the same as for a general purpose 256 K bit EPROM 12 5 V tpw 1 ms Therefore by using a dedicated programming adapter supplied by Panasonic which can convert the 42 44
21. AN1 ANO gt V Od I P60 LOW speed HIGH speed CPU P61 oscillator oscillator MN101C P62 5 4 ROM RAM 16 512 bytes P66 A gt P67 8 bit timer 2 External Interrupt P70 U lt 71 8 bit timer 3 Serial Interface 0 9 16 bit timer 4 Time Base Timer 5 A D converter I 16 Block Diagram Figure 1 4 1 Watchdog Timer Block Diagram 48 TQFP package type 8 Jod P80 LEDO r P81 LED1 r P82 LED2 a P83 LEDS gt P84 LED4 lt gt P85 LED5 gt P86 LED6 r P87 LED7 Chapter 1 Overview 1 5 Electrical Characteristics This LSI user s manual describes the standard specification System clock fs is 1 2 of high speed oscillation at NOR MAL mode or 1 4 of low speed oscillation at SLOW mode Please ask our sales offices for its own product specifica tions Model Contents MN101C457 Structure CMOS integrated circuit Application General purpose Function 8 Bit single chip microcontroller 1 5 1 Absolute Maximum Ratings 23 voltages referenced to Vss Power supply voltage 0 310 7 0 Input clamp current ACZ 500 to 500 Input pin voltage 0 3 to 0 3 Output pin voltage 0 3 to VDD 0 3 V 5 VO voltage 0 3 to 0 3 ec ear P
22. 1 Port 2 output data 16 P6OUT7 5 P6OUT4 2 P6OUT1 0 0 0 0 0 0 0 0 Port 6 Output Data X 3F17 P7OUT1 P7OUTO 0 0 Port 7 Ou tput Data X 3F18 P8OUT7 P8OUT6 P8OUTS P8OUTA P80UT3 P8OUT2 P8OUT1 P8OUTO 0 0 0 0 0 0 0 0 Port 8 Output Data X 3F20 POING x x Port 0 Input Data Port 0 Input Data X 3F21 P1IN1 X x Port 1 Input Data X 3F22 P2IN2 X x Note x Initial value is unstable No data XII 16 Special Function Registers List Port 2 Input Data Chapter 12 Appendices Bit Symbol Initial Value Description Bit 7 Bit 7 Bit 7 P6IN4 P6IN3 Address Register X 3F26 Port 6 Output Data P7IN1 P7INO X 3F27 Port 7 Input Data P8IN4 P8IN3 P8IN1 P8INO x x x X 3F28 Port 8 Input Data PAINS x x X 3F2A Port A Input Data PODIR2 PODIR1 PODIRO 0 0 0 Port 0 I O Direction Control X 3F30 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO 0 0 0 0 0 Port 1 I O Direction Control X 3F31 P6DIR7 P6DIR6 P6DIRS P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIRO 0 0 0 0 0 0 0 0 Port 6 I O
23. 1 When the execution time at NORMAL is above that duration The following program should be inserted to make the waiting time for more than 4 cycles of low speed oscillation clock before the transition from NORMAL to SLOW 2 When the execution time at NORMAL is above that duration also its possibility will become clear at IDLE Set the program for switching to SLOW mode not to NORMAL mode from IDLE P High speed Setting value of rogram for waiting time oscillation WAIT CONST MOV WAIT CONST DO clock MHz decimal LOOP NOP 17 195 NCP 18 206 NOR 19 218 ADD 1 DO 20 229 BNE LOOP low speed oscillation clock 32 768 kHz Standby Functions 21 Chapter 2 CPU Basics 2 4 4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY HALT STOP modes by specifying the new mode in the CPU mode control register CPUM Interrupts initiate the return to the former CPU operating mode Before initiating a transition to a STANDBY mode however the program must 1 _ Set the maskable interrupt enable flag MIE in the processor status word PSW to 0 to disable all maskable interrupts temporarily 2 Set the interrupt enable flags in the interrupt control registers xxxICR to 1 or 0 to specify which interrupts do and do not initiate the return from the STANDBY mode Set MIE 1 to enable those maskabl
24. 68 0 7 0011 0001 Obp lt abs 8 gt lt 47 1 125 TBNZ abs8 bp label mem8 abs8 bp 1 PC 8 d1 1 label HPC mem8 abs8 bp 0 PC 82PC 0011 0001 1bp abs 82 did 72 125 2 108 mem8 io bpz1 PC 7 d7 label HPC 8 0 0 7 0011 0101 Obp lt io8 2 7 1 126 2 8 mem8 io bpz1 PC 8 d11 label H PC 8 0 0 8 0011 0101 1 lt io8 2 dii H 2 126 2 abs16 bp label mema abs16 bpz1 PC 9 d7 label H PC mem8 abs16 bp 0 PC 92PC 0011 1111 Obp abs 16 ane xd 4 127 BNZ abs16 bp label mem8 abs16 bp 1 PC 10 d1 1 label H PC mem8 abs16 bp 0 PC 105PC 0011 1111 1bp abs 16 mc ome 2 127 JMP JMP 0 17 16 15 0 0 0010 0001 00 0 JMP label 18 0011 1001 lt abs 18b 15 0 gt 5 128 JSR JSR An SP 35SP PC43 bp7 0 mem8 SP PC 3 bp15 8 mem8 SP 1 PC 3 H gt mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 3 bp17 16 mem8 SP 2 bp1 0 0 PC bp17 16 An PC bp15 0 0 PC H 0010 0001 00A1 JSR label SP 358P PC45 bp7 0 5mem8 SP PC45 bp15 82mem8 SP 1 PC 5 H gt mem8 SP 2 bp7 0 gt mem
25. BTimer 4 Compare Register 4 7 6 5 4 3 2 1 0 TM4OCL TM4OCL7 TM4OCL6 4 5 TM4OCL4 40013 TM4OCL2 TM40CL1 TM40CLO At reset X X X X X X X X Figure 6 2 1 Timer 4 Compare Register Lower 8 bits TM4OCL x 03F74 R W 7 6 5 4 3 2 1 0 4 TM4OCH7 TM4OCH6 TM4OCH5 TM4OCH4 TM40CH3 TM40CH2 TM4OCHIITM40CHO At reset X X X XX XXX Figure 6 2 2 Timer 4 Compare Register Upper 8 bits 4 75 R W Binary counter is a 16 bit up counter If any data is written to a compare register during counting is stopped the binary counter is cleared to x 0000 Timer 4 Binary Counter TM4BC 7 6 5 4 3 2 1 0 TM4BCL TM4BCL7 TM4BCL6 TM4BCL5 4 14 TM4BCL3 4 12 TM4BCL1 neo atreset 00000000 Figure 6 2 3 Timer 4 Binary Counter Lower 8 bits TM4BCL 03 64 7 6 5 4 3 2 1 0 TMABCH TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 eec eo atreset 00000000 Figure 6 2 4 Timer 4 Binary Counter Upper 8 bits 03 65 Control Registers VI 5 Chapter 6 16 Timer Input capture register is a register that holds the value loaded from a binary counter by capture trigger Capture trigger is generated by an input signal from an external interrupt pin Directly writing to the register by program is disable Timer 4 Inp
26. LSB first Reception data issi SCOCEO SCOCE1 edge 1 0 0 rising falling 1 falling rising 1 0 falling falling 1 rising rising Figure 10 2 3 Serial Interface 0 Mode Register 0 SCOMDO 03 50 R W Control Registers Serial Interface 0 Mode Register 1 SCOMD1 The SCOTRI SCOERE and SCOBRKF flags are only readable SCOMD1 7 6 5 4 3 2 1 0 E SCOCKM SCOCK1 SCOCKO SCOBRKF SCOERE SCOTRI Chapter 10 Serial Interface 0 at reset X00000 SCOTRI Transmission Reception interrupt request flag 0 Transmission interrupt request 1 Reception interrupt request SCOERE Error monitor 0 No error 1 Error SCOBRKF _ Break status receive monitor 0 Data Break 5 0 1 5 0 0 Clcok source 0 0 fs 2 1 fs 4 1 0 fs 16 1 Timer 3 output SCOCKM 1 8 dividing of transfer clock selection 0 Do not divide by 8 1 Divide by 8 Clock source can be selected as an external clock by setting the SBTO pin to input mode At UART mode SCOCMD 1 the SCOCKM is fixed to 1 Figure 10 2 4 Serial Interface 0 Mode Register 1 SCOMD1 x 03F51 R W Control Registers X 7 Chapter 10 Serial Interface 0 Serial Interface 0 Mode Register 2 SCOMD2 7 6 5 4 3 2 1 0 SCOMD2 SCOBRK
27. PAO PA7 Chapter 5 8 Bit Timers Chapter5 8 Bit Timers 5 1 Overview This LSI contains one general purpose 8 bit timers Timers 2 and one 8 bit timer Timers 3 that can be also used as baud rate timer Timers 2 and 3 can be used as 16 bit timers with cascade connection 5 1 1 Functions Table 5 1 1 shows functions of each timer Table 5 1 1 Timer Functions Timer 2 Timer 3 Timer 5 8 bit 8 bit 8 bit Interrupt source TM2IRQ TM3IRQ 4 4 4 Event count 5 Timer pulse output PWM output Serial transfer clock output SIFO Cascade connection Remote control carrier output 5 fs fosc fs 4 fs 4 2 Clock source fx fx fs 16 fosc 213 TM2IO input input 213 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation not contained in the package types of 42 SDIP 44 QFP fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 When timer 3 is used as a baud rate timer for serial interface function it is not used as a general timer Timer 5 is described in Chapter 7 V 2 Overview Chapter 5 8 Timers Block Diagram WTimers 2 Block Diagram 5 1 2 Andino OIZIALL 4 4 XNW 158 4 102204065
28. SCOTRB F E D C B Figure 10 3 1 1 Transfer Bit Count and First Transfer Bit starting with MSB Setting on program F E D C B A SCOTRB A B C D E F Figure 10 3 1 2 Transfer Bit Count and First Transfer Bit starting with LSB Received Data Buffer The received data buffer SCORXB is the sub buffer that pushed the received data in the internal shift register After the communication complete interrupt SCOIRQ is generated data stored in the transmis sion reception shift register is stored to the received data buffer SCORXB automatically SCORXB can store data up to 1 byte SCORXB is rewritten in every communication complete so read data of SCORXB till the next receive complete And before the next data reception is started the same data to the SCORXB can be read even if the SCOTRB is reading When the SCOSBIS flag of the SCOMD3 register is set to serial interface input the SCOTRI flag of the SCOMD register is set to 1 at the same time SCOIRQ is generated SCOTRI is cleared to 0 when the next reception has completed Bit Count and First Transfer Bit On reception when the transfer bit count is 1 bit to 7 bits the data reading method from the received data buffer SCORXB is different depending on the first transfer bit selection At MSB first data are read from the lower bits of SCORXB When there are 6 bits to be transferred as shown on figure 1
29. Set this switch to its USR position to drive the in circuit emulator with the oscillator built into the target board If there is no oscillator on the target board set this switch to the ICE position to use the oscillator built into the probe 2 S1 Power supply control Set this switch to its USR position to use the power supply from the target board If there is no oscillator on the target board set this switch to the ICE position to use the 5 V power supply from the in circuit emulator attention To use A D converter with power supply below 5 V set this switch to its USR position Reference voltage is 5 V 3 Function control DIP switches Each model has different setting of DIPSW as described below LCDSEL ON For models which use LCD function OFF For models which use LED function WDSEL1 WDSEL2 Switches for watchdog timer frequency Watchdog timer frequency WDSEL1 WDSEL2 mw NSSTRT Switch for oscillation control at reset released ON Start with the low speed oscillation Do not switch on at 101C45 OFF Start with the high speed OSC oscillation Probe Switches XII 13 Chapter 12 Appendices 12 2 2 PRB ADP101C11 42 45 44PIN Probe Switches Adapter boards differ depending upon the models This adapter board can be used for only 101C11 101642 and 101C45 44 Use this adapter board with EV board PRB EV101C15 Improper matching may cause any dama
30. fx 32 kHz 3 i Supply current DDR E Ta 25 C 8 during HALT mode 32 kHz VDD 3 V Ta 40 C to 85 C 5 V a Supply current ODE Ta 25 C during STOP mode 5 V 20 1 DD7 Ta 40 C to 85 C 0 Measured under conditions of load The supply current during operation IDD1 IDD2 is measured under the following conditions After all I O pins are set to input mode and the oscillation is set to NORMAL modes the MMOD pin is at VSs level the input pins are at VDD level and a 20 MHz 8 39 MHz square wave of and Vss amplitudes is input to the OSC1 pin The supply current during operation IDD3 is measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt SLOW mode the MMOD is at Vss level the input pins are at VDD level and a 32 kHz square wave of VDD and Vss amplitudes is input to the XI pin The supply current during HALT mode IDD4 is measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt HALT mode the MMOD pin is at Vss level the input pins are at VDD level and an 32 kHz square wave of and Vss amplitudes is input to the XI pin The supply current during STOP mode is measured under the following conditions After the oscillation is set to STOP mode MMOD pin is at Vss level the in
31. 8 d7 2111 if mem8 abs8 zimm8 PC 92PC CBEQ imm8 abs8 label li mem amp abs8 imm8 PC t0 dti abe H2PC e e 10 6 7 0010 1101 1101 abs 8 48 gt dii H 3 401 8 058 8 10 20516 if mem8 abs16 imm8 PC 11 d7 label HPC e e e 11 7 8 0011 1101 1100 lt abs 16 2 lt 8 gt lt 7 21 if mem8 abs16 4imm8 PC 11 PC CBEQ imm8 abs16 label _ if mem8 abs16 imm8 PC 12 d1 1 12 7 8 0011 1101 1101 abs 16 gt HB gt dii 13 11 if mem8 abs16 imm8 PC 12 PC CBNE CBNE imm8 Dm label if Dmzimm8 PC 6 d7 labe HOPC e 6 3 4 1101 10Dm lt 8 gt 47 H 2 11 8 6 imm8 Dm label if Dm4imm8 PC 8 d1 1 label H3PC e e e e 8 45 0010 1101 10Dm 48 gt lt 11 3 11 if Dm zimm8 PC 82PC CBNE imm8 abs8 label i mem8 abs8 Zimm8 PC 9 d7 labeHOPO e e e e 9 6 7 0010 1101 1110 abs 8 8 d7 H 2 12 if mem8 abs8 imm8 PC 95PC CBNE imm8 abs8 label _ if mems abs8 4imm8 PC 10 d11 label H PC e e 10 6 7 0010 1101 1111 abs 8 lt 8 gt 411 3 12 8 058 8 10 CBNE imm8 abs16 label 0516 04114 e 11 7 8 0011 1101 1110 lt abs 16 gt lt 8 gt 7 2 121 if mem8 abs16 imm8 PC 11 PC CBNE imm8 abs16 label
32. After reception has completed the TXD is H level If the frame mode is set by the SCOFM flag of the SCOMD2 register the SCOLNG2 0 flag of the SCOMDO register is automatically set After the transfer has completed the transfer bit count in the SCOLNG2 0 flag of the SCOMDO register is automatically set At UART reception set SCOSBIS flag of the SCOMDS register to 1 and set the SCOSBOS flag to 0 Setting both of flags to 1 is disabled Operation X 47 Chapter 11 A D Converter Chapter 11 A D Converter 11 1 Overview This LSI has an A D converter with 10 bits resolution That has a built in sample hold circuit and its analog input can be switched in channel 0 to 7 ANO to AN7 by software As A D converter is stopped the power consumption can be reduced by a built in ladder resistance 11 1 1 Functions Table 11 1 1 shows the A D converter functions Table 11 1 1 A D Converter Functions A D input pins 8 pins Pins AN7 to ANO Interrupt ADIRQ Resolution 10 bits Conversion time min 9 6 us as TAD 800 ns Input range to Vss Built in ladder resistance Power consumption ON OFF XI 2 Overview 11 1 2 Block Diagram ANCTR1 Chapter 11 A D Converter
33. Chapter 4 I O Ports 4 1 4 2 OVVIE W IV 2 4 1 1 VO Port Diagram IV 2 4 1 2 Port Status at IV 3 4 1 3 Control Registers oec eed pde REOR RES IV 4 Port O EDU EISE IV 5 4 2 1 e ere eer edt IV 5 4 2 2 Registers 5 eioenonoteotetbteoentetia e pre pete eei eren IV 6 4 2 3 Block Diagram cotto ite a ettet Bisbee deeds IV 7 jij contents iv 4 3 4 4 4 7 4 8 EEEE ERO rere TE IV 9 4 3 1 Description ounce EE IV 9 4 3 2 eun ae ies Rites Ha ea EAS 2 IV 10 4 3 3 Block Dia grant e eolit ee RO eee ae IV 12 2 5 opted er e re pra o re PEE Eee IV 14 4 4 1 D scriptlOn 14 4 4 2 R egistefs te tit P ee e c Poeni 15 4 4 3 Block Diagram 5 eet e tete IV 16 Port Oi ss siete RR ee es e i e ih e od IV 17 4 5 1 Description nacre pROD EORR EE m aise IV 17 4 5 2 Registers Gub uuo tei RU IV 18 4 5 3 Block i ih pe ne eee IV 19 Port 7 itti e m ee emere mette IV 20 4 6 1 Description eese Ie Rea eee As edi ae ete eters Rocke IV 20 4 6 2 Registers E IV 21 4 6 3 Block Di
34. TM4EN TM4PWM T4ICTS1 T4ICTSO TM4CK2 TM4CK1 0 0 0 0 x x x X 3F84 TM4MD VI 7 Timer 4 Timer 4 TM4 Clock source count control operation mode input capture trigger TM5CLRS 2 TMSIR1 TMSIRO 5 TM5CK2 TM5CK1 TM5CKO 0 x x x x x 0 X 3F88 TM5MD VII 6 5 binary Time base timer interrupt cycle Timer 5 clock source Time base timer counter clear clock source Note x Initial value is unstable No data Special Function Registers List XII 19 Chapter 12 Appendices Address Register 89 Bit Symbol Initial Value Description Bit 5 Bit 4 Reserved Bit 3 RMOEN Reserved RMDTYO Reserved 0 0 x x 0 Set always Enable remote control carrier output Set always 05 output duty Remote control carrier Set always X 3F8A NF1CKS1 NF1CKSO NF1EN NFOCKS1 NFOCKSO NFOEN 0 0 0 0 0 0 IRQ1 noise filter sampling period IRQ1 noise filter setup IRQO noise filter sampling period IRQO noise filter setup X 3F90 ANCTRO ANSH1 ANSHO ANCK1 ANCKO ANLADE ANCHS2 ANCHS1 ANCHSO x X x x 0 x x X A D sample and hold time A D conversion clock A D ladder resistance control Analog input select ion X 3F91 ANCTR1 ANST 0 A D conversion status 92 ANBUFO ANBUFO7 ANBUFO6 X X A D buffer 0 lower
35. TM5BC5 TM5BC4 TM5BC3 TM5BC2 5 1 5 0 Figure 7 2 1 atreset 00000000 Timer 5 Binary Counter TM5BC 03 68 5 Compare Register TM5OC 7 6 5 4 3 2 1 0 TM5OC TM50C7 50 6 TM50C5 TM50C4 TM50C3 TM50C2 TM50C1 50 0 Figure 7 2 2 Timer 5 Compare Register TM5OC x 03F78 R W Control Registers VII 5 Chapter 7 Time Base Timer 8 Bit Free running Timer 7 2 3 Timer Mode Registers This is a readable writable register that controls timer 5 and time base timer Timer 5 Mode Register TM5MD TM5MD 6 7 6 5 4 3 2 1 0 TM5CLRS TMSIR2 TMSIR1 TMSIRO TM5CK3 5 2 5 5 0 At reset 0XXXXXX0 TM5CKSO Time base timer clock source 0 fosc 1 fx TM5CK3 TM5CK2 TM5CK1 Timer 5 clock source fosc x 0 0 1 fs 4 0 fx 0 1 1 Output of base timer 1 0 Synchronous fx 1 Synchronous output of time base timer Time base timer TMSIR2 5 1 TMSIRO interrupt cycle selection 2 0 Time base selection clock x 1 2 0 1 Time base selection clock x 1 2 1 0 base selection clock x 1 2 1 Time base selection clock x 1 2
36. UART Half duplex Interrupt SCOIRQ transmission reception TXD output input Used pins RXD input First transfer bit MSB LSB Parity bit selection 0 1 Parity bit control odd parity even parity Frame selection Maximum transfer rate 7 bits 1 stop 7 bits 2 stops 8 bits 1 stop 8 bits 2 stops 625 kbps Operation X 29 Chapter 10 Serial Interface 0 Selection of Half duplex UART Serial Interface When the serial interface 0 is used as half duplex UART serial interface set the SCOCMD flag of the serial interface 0 control register SCOCTR to 1 Activation Factor for Communication At transmission if any data is written to the transmission reception shift register SCOTRB a start bit Data is changed from H to L is generated to start transfer At reception if a start bit Data is changed from to L is received communication is started At reception if the data length of L is longer than 0 5 bit that can be regarded as a start bit Transmission Data transfer is automatically started by writing data to the transmission reception shift register SCOTRB after setting the SCOSBOS flag of the SCOMD3 register to 1 During transmission reception and start bit input are disabled mReception When the SCOSBIS flag of the SCOMDO3 register is set to 1 and a start bit is received reception is started after the transfer bit counter is set as fra
37. mapped I O CPU control registers are also located in this memory space Table 2 1 2 CPU Control Registers Registers Address RW Function Pages CPUM x 03F00 R W 1 CPU mode control register ll 19 MEMCTR xO3F01 RAW Memory control register 1 16 Reserved For debugger NMICR 1 R W Non maskable interrupt control register Ill 16 X 03FE2 R W Maskable interrupt control register ll 17 to 27 Reserved xOSFFF 5 Reserved For reading interrupt vector data on interrupt process 5 1 Part of the register is only readable 4 Overview Chapter 2 CPU Basics 2 1 3 Instruction Execution Controller The instruction execution controller consists of four blocks memory instruction queue instruction regis ters and instruction decoder Instructions are fetched in 1 byte units and temporarily stored in the 2 byte instruction queue Transfer is made in 1 byte or half byte units from the instruction queue to the instruction register to be decoded by the instruction decoder 7 0 Memory 1 amp 5 0 1 byte or a half byte Instruction queue Instruction register cotta Instruction decoder Instruction decoding CPU control signals Figure 2 1 2 Instruction Execution Controller Configuration Overview 5 Chapter 2 CPU Basics 2 1 4 Pipeline Process Pipeline process
38. scribed on to the corresponded address Ill 6 Overview Wilnterrupt Level and Priority Chapter 3 Interrupts On this LSI vector numbers and interrupt control registers except reset interrupt are allocated to each interrupts The interrupt level except reset interrupt non maskable interrupt can be set by software per each interrupt group There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority For example if a vector 3 set to level 1 and a vector 4 set to level 2 request interrupts simultaneously vector 3 will be accepted Interrupt vector No Vector 1 Non maskable interrupt Priority 1 Level 0 Vectors 2 5 6 2 3 Interrupt level Level 1 TEE setting range Level 2 Vectors 4 8 6 7 Vector 1 Vector 2 Vector 5 Vector 6 Vector 3 Vector 4 Vector 8 Figure 3 1 3 Interrupt Priority Outline Overview II 7 Chapter 3 Interrupts Determination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance 1 The interrupt request flag xxxIR in the corresponding external interrupt control register IRQnICR or internal interrupt control register xxxICR is set to 1 2 interrupt request is input to the CPU If the interrupt enable flag in the same register is 1 The interrupt level IL is set for ea
39. status word PSW and thus the previous interrupt mask level 1 The maskable interrupt enable MIE in the processor status word PSW is not cleared to 0 when interrupt is accepted Non maskable interrupts have priority over maskable ones Overview 9 Chapter 3 Interrupts lilinterrupt Acceptance Operation When accepting an interrupt this hardware saves the handy address register the return address from the program counter and the processor status word PSW to the stack and branches to the interrupt handler using the starting address in the vector table The following is the hardware processing sequence after interrupt acceptance 1 The stack pointer SP is updated SP 6 gt SP 2 The contents of the handy address register HA are saved to the stack Upper half of HA SP 5 Lower half of HA SP 4 3 The contents of the program counter PC the return 22 D address are saved to the stack PC bits 18 17 and 0 SP 3 i Pea SP _ PSW Lower after interrupt PC bits 16 9 SP 2 1 PC bits 8 1 SP 1 4 contents of the PSW are saved to the stack Poo reserved 1817 Address PSW SP HATO 5 interrupt level xxxLVn for the interrupt is copied to FOR Old SP Higher the interrupt mask IMn in the PSW before interrupt Interrupt level xxxLVn IMn acceptance 6 The ha
40. 0 5 mA 4 5 42 low voltage VoLa8 5 0 V loL 1 0 mA 0 5 y VO pin7 P60 to P67 43 Input high voltage 1 ViH9 0 8 VDD 44 Input high voltage 2 ViH10 4 5 V to 5 5 V 0 7 VDD 45 Input low voltage 1 VIL9 0 0 2 VDD 46 Input low voltage 2 VIL10 4 5 V to 5 5 V 0 0 3 47 leakage current ILkg V 0 V to VDD 10 48 high current lig 0 5 30 100 300 e 49 Output high voltage VoH9 5 0 V 0 5 mA 4 5 50 Output low voltage VoL9 5 0 V loL 1 0 mA 0 5 1 24 Electrical Characteristics Chapter 1 Overview Ta 40 C to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions MIN Unit Input pin8 P70 to P71 3 51 high voltage 1 0 8 52 Input high voltage 2 ViH12 00 4 5 V to 5 5 V 0 7 VDD VDD 53 low voltage 1 0 0 2 VDD 54 low voltage 2 ViL12 4 5 V to 5 5 V 0 0 3 55 leakage current ILK11 Vi 0 V to VDD 10 56 Input high current 11 y 30 100 300 57 Input low current 80 180 400 58 Output high voltage 5 0 V 0 5 mA 45 59 Output low voltage 5 0 V loL 1 0 mA 0 5 d VO pin 9 P80 to P87 60 high voltage 1 ViH13 0 8 VDD VDD 61 high vol
41. 00 3 Select the AC zero cross detector signal FLOAT1 x 3F4B bp2 P211M 1 4 Set the interrupt level IRQ1ICR bp7 6 IRQ1ILV1 0 10 b Enable the interrupt IRQ1ICR x 3FE3 bp1 IRQ1IE 1 1 Set the REDG1 flag of the external interrupt 1 control register IRQ1ICR to 1 to specify the active edge of the external interrupt to rising Select the noise filter by the NF1EN NFCKS1 0 flag of the noise filter control register NFCTR And select fs 2 for its sampling cycle Set the P211M flag of the pin control register 1 FLOAT1 to 1 to select the AC zero cross detector signal as the external interrupt 1 generation factor Set the interrupt level by the IRQ1LV 1 0 flag of the IRQ1ICR register If any interrupt request flag had already been set clear it 14 Chapter 3 3 1 4 Interrupt flag setup Set the IRQ1IE flag of the IRQ1ICR register to 1 to enable the interrupt When the input signal level from P21 ACZ pin crosses 1 2 the external interrupt 1 is generated III 39 External Interrupts Chapter 4 I O Ports Chapter 4 Ports 4 1 Overview 4 1 1 Port Diagram A total of 40 pins on this LSI including those shared with special function pins are allocated for the 7 ports of ports 0 to 2 ports 6 to 8 and port A Each I O port is assigned to its corresponding special function register area in memory I O ports are operated in byte or bi
42. 5 3 0011 1010DmDm 8 gt 88 NOTE Pages for MN101C Series Instruction Manual D DWn d DWm 55 D DWm 9 m n 2 6 4 sign extension 3 d DWm 7 8 sign extension 4 D DWk 8 Dn zero extension Instruction Set XII 23 Chapter 12 Appendices MN101C SERIES INSTRUCTION SET Mnemonic Operation 0 Machine Code 6 7 8 NOT NOT Dn Dn5Dn 3 2 0010 0010 10Dn ASR ASR Dn Dn msb temp Dn Isb CF 01 6 2 0010 0011 10Dn Dn gt gt 1 Dn temp Dn msb LSR LSR Dn Dn lsbSCF Dn 1 Dn 0 00 06 3 2 0 0010 0011 t1Dn 0 Dn msb ROR ROR Dn Dn lsbtemp Dn 1 Dn 000 09 3 2 0010 0010 11Dn CFDn msb tempCF Bit manipulation instructions BSET io8 bp mem8 IOTOP i08 amp bpdata PSW 0 e 01 5 5 0011 1000 Obp lt 08 1 meme8 IOTOP io8 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 4 4 1011 Obp lt abs 8 gt 1 mem8 abs8 bp BSET abs16 bp mem8 abs16 amp bpdata PSW 01 016 7 6 0011 1100 abs 16 gt 1 mem8 abs16 bp BCLR BCLR io8 bp mem8 IOTOP io8 amp bpdata PSW 5 5 0011 1000 16 08 gt 0 mem8 IOTOP i08 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 0 0 0 2 4 1011 1bp abs 8 0 8 68 BCLR abs16 bp mem8 abs16 amp bpdata PSW 01 01676 0011 1100 1bp abs 16 gt 0 mem8 abs16 bp BTST BTST imm8 Dm Dm amp imms PSW 0le 0 0 5 3 0010 0000 11Dm
43. 5 6 7 Chapter 12 Appendices Contorl instructions REP imm3 5 5 meme8 SP 1 PC bp7 0 mem8 SP 42 PC bp15 8 mem8 SP 3 bp7 PC H mem8 SP 3 bp1 0 PC bp17 16 8 5 4 mem8 SP 5 HA h SP 6 SP imm3 1 RPC 0000 0011 0010 0001 1 NOTE Pages for 101 Series Instruction Manual 1 repeat whn imm3 0 rep imm3 1 0 Other than the instruction of MN101C Series the assembler of this Series has the following instructions as macro instructions The assembler will interpret the macro instructions below as the assembler instructions macro instructions replaced instructions remarks INC Dn ADD 1 Dn DEC Dn ADD 1 Dn INC An ADDW 1 An DEC An ADDW 1 An INC2 ADDW 2 DEC2 ADDW 2 An CLR SUB Dn Dm ASL ADD Dn Dm ROL ADDC Dn Dm NEG NOT Dn ADD 1 Dn NOPL MOVW__ DWn DWm MOV 0 SP Dn MOV __Dn 0 SP MOVW MOVW 0 SP DWn MOVW MOVW DWn 0 SP MOVW MOVW 0 SP An MOVW MOVW An 0 SP Instruction Set Ver3 1 2001 03 26 XII 27 Chapter 12 Appendices 12 5 Instruction Map MN101C SERIES INSTRUCTION MAP 1stnibble 2nd nibble 7 D E F MOV 8 i08 POP An CMP 8 abs8 abs12 ADD 8 Dm MOVW 8 DWm MOVW 8 Am JSR d12
44. 51 MOVW DWn HA DWn mem 16 HA 1 1 1 1213 1001 0100 52 MOVW 16 1 1 1 1213 1001 011A 52 MOVW imm8 DWm sign imm8 gt DWm 4 2 0000 1104 448 gt 5 53 MOVW imm8 Am zero imm8 Am 1 1 1 1412 0000 111a 4 8 gt 6 53 MOVW imm16 DWm imm16 5DWm 6 3 1100 1114 146 gt 54 NOTE Pages for the 101 Series Instruction Manual 98 4 A An a Am 2 d4zero extension 5 8 sign extension 3 d8zero extension 76 8 zero extension XII 22 Instruction Set MN101C SERIES INSTRUCTION SET Mnemonic Operation Machine Code 6 7 8 Chapter 12 Appendices MOVW imm16 Am imm16 gt Am 111a lt 16 MOVW SP Am SP Am 100a MOVW An SP An SP 101A MOVW DWn DWm DWn DWm MOVW DWn Am DWn Am 11Da MOVW An DWm An gt DWm 11Ad MOVW An Am An Am 00Aa PUSH Dn SP 15SP Dn mem8 SP 10Dn PUSH An 5 2 5 16 5 011A POP Dn mem8 SP gt Dn SP 1 SP 10Dn POP An mem16 SP An SP 25SP 011A EXT Dn DWm Arithmetic manupulation instructions sign Dn BDWm w A lav vajav vj ja 000d ADD ADD Dn Dm Dm Dn gt Dm 2 0011 0011 DnDm 61
45. 80616 412 411 80 12 7 8 0011 1101 1111 abs 16 gt H8 gt dii 8 121 if mem8 abs16 imm8 PC 12 PC TBZ TBZ abs8 bp label if mem8 abs8 bp 0 PC 7 d7 label H3PC 0 7 6 7 0011 0000 abs 8 lt d7 2 12 if mem8 abs8 bp 1 PC 73PC TBZ abs8 bp label if mem8 abs8 bp 0 PC 8 d1 1 labelsH PC 0 e O0 8 6 7 0011 0000 16 abs 8 dti 3 12 if mem8 abs8 bp 1 PC 8 PC Instruction Set 1 2 47 sign extension 8 411 sign extension 44 sign extension XII 25 Chapter 12 Appendices MN101C SERIES INSTRUCTION SET Mnemonic TBZ TBZ io8 bp label Operation if mem8 IOTOP io8 bp 0 PC 7 d7 label HPC if mem8 IOTOP io8 bp 1 PC 7PC 0100 Obp lt io8 6 7 wer 2075 Machine Code 1 123 BZ io8 bp label if mem8 IOTOP io8 op 0 8 211 6 if mem8 IOTOP i08 bp 1 PC 8 PC 0011 0100 1bp io8 ze wii us 2 123 BZ abs16 bp label memB abs16 bp 0 PC 9 d7 label HPC mem8 abs16 bp 1 PC 9 PC 0011 1110 Obp lt abs 16 gt dr 1 124 TBZ abs16 bp label mem8 abs16 bp 0 PC 10 d1 1 mem8 abs16 bp 1 PC 102PC 0011 1110 1 lt abs 16 xem 2 124 TBNZ TBNZ abs8 bp label 8 8068 0 1 7447 80 9 8
46. Data in internal EPROM with windowed packaging is erased by applying a light that the wavelength is shorter than 400 nm Fluorescent lamp and sunlight are not able to erase data as much as UV light of 253 7 nm is but those light sources are also able to erase data more or less To expose those light sources for a long while can damage its system To prevent this cover the window with an opaque label If the wavelength is longer than 400 nm to 500 nm data can not be erased However because of typical semiconductor characteristics the circuit may malfunction if the chip is exposed to an extremely high illumination intensity The chip will operate normally if this exposure is stopped However for areas where it is continuous take necessary precautions against the light that the wavelength is longer than 400 nm XII 4 EPROM Version Chapter 12 Appendices 12 1 4 Differences between Mask ROM version and EPROM version The differences between the 8 bit microcomputer 101 457 Mask ROM version MN101CP427 are as follows Table 12 1 1 Differences between Mask ROM version and internal EPROM version 101 457 101 427 Mask ROM version EPROM version TEES 2 0 V to 5 5 V 0 477 us at 4 19 MHz 2 7 V to 5 5 V 0 477 us at 4 19 MHz votag 2 0 V to 5 5 V 125 us at 32 kHz 27 V to 5 5 V 125 us at 32 kHz Pin DC Characteristics Output current input current and input judge level are the same Option
47. P1OUT x 03F11 R W 7 6 5 4 3 2 1 0 P1IN P1IN3 P1IN2 P1IN1 At reset XXXXX 0 1 Port 1 input register x OSF21 R 7 6 5 4 3 2 1 0 P1DIR P1DIR4 P1DIR3 P1DIR2 P1DIR1 PiDIRO Atreset 00000 P1DIR 0 1 Port 1 direction control register P1DIR x 03F31 7 6 5 4 3 2 1 0 P1PLU P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0 Atreset 00000 0 No pull up resistor 1 Pull up resistor Port 1 pull up resistor control register P1PLU x 03F41 R W Figure 4 3 1 Port 1 Registers 1 2 10 Port 1 Chapter 4 Ports 7 6 5 4 3 2 1 0 1 14 P12TCO 10 Atreset 000 0 port Remote control 10 output selection 0 port Remote control output port P12T co Timer 2 output selection 0 port 1 Timer 2 output 10 port PT3TCO Timer 3 output selection 0 10 port 1 Timer 3 output 10 port P14TCO Timer 4 output selection 0 I O port Timer 4 output Port 1 output mode register P1OMD 03 39 R W Figure 4 3 2 Port 1 Registers 2 2 Pot IV 11 Chapter 4 Ports 4 3 3 Pull up resistor control direction control Port output data Output mode control Port input data Timer input Remote control carrier output Pull
48. Set the compare register TM40C x 3F75 x 3F74 x FFFF Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Select fosc as clock source by the TM4CK2 0 flag of the TM4MD register Select the external interrupt 0 IRQO input as a generation source of capture trigger by the T4ICTS1 0 flag of the TM4MD register Set the REDGO flag of the external interrupt 0 control register IRQOICR to 1 to select the rising edge as the interrupt generation active edge Set the TM4PWM flag of the timer 4 mode register TM4MD to 0 to select the normal timer operation Set the timer 4 compare register 4 TM4OCL to x FFFF At that time the timer 4 binary counter TM4BC is initialized to x 0000 VI 26 16 Bit Timer Capture Chapter 6 16 Bit Timer Setup Procedure Description 7 Setthe interrupt level 7 Setthe interrupt level by the IRQOLV1 0 flag of IRQOICR x 3FE2 the IRQOICR register bp7 6 IRQOLV1 0 10 If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt Flag Setup 8 Enable the interrupt 8 Enable the interrupt by setting the IRQOIE flag IRQOICR x 3FE2 of the IRQOICR register to 1 bp1 IRQOIE 21 9 Start the timer operation 9 Set the TM4EN flag of the TMAMD register to TM4MD x 3F84 to start timer 4 bp6 TMAEN 1 TM4BC counts up from x 0000 At the timing of the rising edge o
49. Timers 2 and 3 consist of the binary counter TMnBC and the compare register TMnOC And they are controlled by the mode register TMnMD Remote control carrier output is controlled by the remote control carrier output control register RMCTR 5 2 1 Registers Table 5 2 1 shows registers that control timers 2 and 3 and remote control carrier output Table 5 2 1 8 bit Timer Control Registers Register Address R W Function Page X 03F62 eR Timer 2 binary counter V 6 72 Timer 2 compare register V 6 5 4 x 03F82 Timer 2 mode register V 7 imer x 03FE6 Timer 2 interrupt control register IIl 21 x 03F39 Port 1 output mode register 11 X 03F31 Port 1 direction control register IV 10 6 Timer 3 binary counter V 6 X 03F73 Timer 3 compare register V 6 3 x 03F83 Timer 3 mode register V 8 imer Timer 3 interrupt control register Ill 22 x O3F39 Port 1 output mode register 11 P1DIR X 03F31 R W Port 1 direction control register IV 10 Remote contol RMCTR x 03F89 R W Remote control carrier output control register V 9 carrier output R W Readable Writable R Readable only Control Registers V 5 Chapter 5 8 Timers 5 2 2 Programmable Timer Registers Each of timers 2 and 3 has 8 bit programmable timer registers Programmable timer register consists of compare register and binary counter Compare register is 8 bit register which stores the value to b
50. low for more than 4 clock cycles 200 nS at a 20 MHz NRST pin 4 clock cycles 200nS at a 20 MHz Figure 2 8 1 Minimum Reset Pulse Width 2 Setting the 2 7 flag of the P2OUT register to 0 outputs low level at P27 NRST pin And transfering to reset by program software reset can be executed If the internal LSI is reset and Key informatio n register is initiated the P2OUT7 flag becomes 1 and reset is released Summary Introduction to the section References gt Chapter 4 4 4 2 Registers On this LSI the starting mode is NORMAL mode that high oscillation is the base clock 6 When the power voltage low circuit is connected to NRST pin circuit that gives pulse for Important information from the main text Y enough low level time at sudeen unconnected And reset can be generated even if its pulse is low level as the oscillation clock is under 4 clocks take notice of noise 44 Reset References for the main text Precautions and warnings Precautions are listed in case of lost func tionality or damage Be sure to read About This Manual 2 Finding Desired Information This manual provides three methods for finding desired information quickly and easily 2 3 Consult the index at the front of the manual to locate the beginning of each section Consult the table of contents at the front of the manual to locat
51. low for more than OSC 4 clock cycles 200 ns at a 20 MHz NRST pin 4 clock cycles 200 ns at a 20 MHz Figure 2 5 1 Minimum Reset Pulse Width 2 Setting the P2OUT7 flag of the P2OUT register to 0 outputs low level at P27 NRST pin And transferring to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P2OUT7 flag becomes 1 and reset is released Chapter 4 4 4 2 Registers pulses with sufficient time during sudden disconnection And reset can be generated even if 1 When NRST pin is connected to low power voltage use the circuit that provides low level NRST pin is held low for less than OSC 4 clock cycles take notice of noise II 24 Reset Chapter 2 CPU Basics mSequence at Reset 1 When reset pin comes to high level from low level the internal 14 bit counter It can be used as watchdog timer too starts its operation by system clock The period that starts its count from its overflow is called oscillation stabilization wait time During reset internal register and special function register are initialized After oscillation stabilization wait time internal reset is released and program starts from the address written at address x 04000 at interrupt vector table 919 NRST OSC2 XO stabilization time internal RST Figure 2 5 2
52. resistor selection 0 Pull up resistor 1 Pull down resistor 21 P21 input mode selection Schmitt trigger input ACZ input Pin control register 1 FLOAT1 X 03F4B R W Figure 4 6 2 Port 7 Registers 2 2 Chapter 4 Ports 4 6 3 Block Diagram aid E P7PLUDO 1 Pull up Pull down resistor control DQ Write L Read Reset R FLOAT1 Pull up Pull down resistor selection 0 0 4 Write p Reset P7DIRO 1 ES direction control 2 S Write ck Z Read z A P70 P71 5 Reset R Port output data P7OUTO 1 Write CK Read 777 154 777 Port input data 1 P71NO 1 B Read Figure 4 6 3 Block Diagram P70 to P71 Pot7 IV 23 Chapter 4 Ports 4 7 Port 8 4 7 1 Description Port Setup Each bit of the port 8 control I O direction register P8DIR can be set individually to set pins as input or output The control flag of the port 8 direction control register P8DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 8 direction control register P8DIR to 0 and read the value of the port 8 input register P8IN To output data to pin se
53. set the frequency of buzzer output The BUZOE flag of the oscillation stabilization wait control register DLYCTR sets buzzer output ON OFF mBuzzer Output Frequency The frequency of buzzer output is decided by the frequency of the system clock fs and the bit 6 5 BUZCK1 BUZCKO of the oscillation stabilization wait control register DLYCTR Table 9 3 1 shows the buzzer output frequency Table 9 3 1 Buzzer Output Frequency fosc fs BUZCK1 BUZCKO Buzzer output frequency 0 0 2 44 kHz 20 MHz 10 MHz 0 1 4 88 kHz 0 1 2 05 kHz 8 39 MHz 4 19 MHz 1 0 4 10 kHz 2 MHz 1MHz 1 1 1 95 kHz IX 4 Operation Chapter9 Buzzer 9 3 2 Setup Example Buzzer outputs the square wave of 2 kHz from P06 pin It is used 8 39 MHz as the high oscillation clock fosc An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Setthe buzzer frequency 1 Set the BUZCK1 0 flag of the oscillation DLYCTR x 3F03 stabilization wait control register DLYCTR bp6 5 BUZCK1 0 01 to 01 to select fs 2 to the buzzer frequency When the high oscillation clock fosc is 8 39 MHz the buzzer output frequency is 2 kHz 2 Set PO6 2 output data POOUT6 of pin 0 POOUT x 3F10 and set the direction control PODIR6 of pin bp6 0 to 1 to select output mode PODIR x 3F30 pin outputs low leve
54. vi contents 10 3 10 2 3 Mode Registers Control registers 2 X 6 Operation E dep an iere or eO RO RR ERES 11 10 31 Clock Synchronous Serial 2 2200400101221 11 10 3 25 Setup Examples zt tette a hd ee e X 26 10 3 3 Half duplex UART Serial Interface see X 29 10 3 4 Setup ee cedes mete etr X 42 Chapter 11 Converter 11 1 11 2 11 3 OVERVIEW estu aotem eO eere reote ener XI 2 Functions 4 nnne trente t e ete t eite eg XI 2 1 1 2 Block Diagram aurei o Ree rH Reese XI 3 Control Registers uere ain aa pipe i e XI 4 1122210 er RE p ERE EEUU ex UE ee XI 4 11 2 2 Control Registers cite deterret heben XI 5 11 2 3 A D Buffers pet XI 7 8 11 351 Setup uiis ees 10 11 3 2 Setup Example eget eerte XI 12 11 323 CAUTIONS ie eet tt Re e e Pee eene tet XI 14 Chapter 12 Appendices 12 1 12 2 12 3 12 4 12 5 EPROM Versions onsena XII 2 ETS OVerVIeWotee tides itr eere qe i ree doeet ien XII 2 12 152 Cautions on Use esee err dene ea Eee eee PERSE XII 3 12 1 3 Erasing Data in Windowed Package PX APIOICA2 EBC S
55. 0 clear it to 0 1 Once the WDIR becomes 1 by generating of non maskable interrupt only the program can 16 Registers Chapter 3 Interrupts WExternal Interrupt 0 Control Register IRQOICR The external interrupt 0 control register IRQOICR controls interrupt level of the external interrupt 0 active edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level IRQOLV1 IRQOLVO 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 4 3 2 1 0 IRQO IRQO 9 IRQOICR LV1 LVO REDGO IRQOIE IRQOIR At reset 000 0 0 External interrupt IRQOIR request flag 0 No interrupt request 1 Interrupt request generated External interrupt IRQOIE enable flag 0 Disable interrupt 1 Enable interrupt External interrupt active REDGO edge flag 0 Falling edge 1 Rising edge IRQO IRQO Interrupt level flag LV1 LVO for external interrupt The CPU has interrupt levels from O to 3 These flags set the interrupt level for interrupt request Figure 3 2 2 External Interrupt 0 Control Register IRQOICR x OS3FE2 R W Control Registers 17 Chapter 3 Inte
56. 0 0 X 3F65 TM4BCH VI 5 Timer 4 binary counter upper 8 bits TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TMA4ICL3 TM4ICL2 TM4ICL1 TM4ICLO x x x x x x x x 66 TM4ICL VI 6 Timer 4 input capture register lower 8 bits TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICHO d TM4ICH 2 i B 2 2 x 3 VI 6 28586 Timer 4 input capture register upper 8 bits 4 TM5BC7 TM5BC6 TM5BC5 TM5BC4 5 TM5BC2 TM5BC1 TM5BCO 0 0 0 0 0 0 0 0 X 3F68 TM5BC VII 5 Timer 5 binary counter 20 7 20 6 20 5 20 4 20 3 TM20C2 TM2OC1 20 0 x x x 72 TM20C V 6 Timer 2 compare register TM30C7 TM30C6 5 4 2 TM30C1 TM30C0 x x X X 3F73 TMSOC 2 a X V 6 Timer 3 compare register TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCLO x x x x x x x x X 3F74 TM4OCL VI 5 Timer 4 compare register lower 8 bits 4 7 TM4OCH6 TM4OCH5 TM40CH4 TM40CH3 TM4OCH2 TM40CH1 TM4OCHO x x x x x x x x X 3F75 TM4OCH VI 5 Timer 4 compare register upper 8 bits TM50C7 TM50C6 TM50C5 TM50C4 TM50C3 TM50C2 TM50C1 TM5OCO x x x x x x x x X 3F78 TM50C VII 5 Timer 5 compare register TM2EN TM2PWM TM2CK2 TM2CK1 TM2CKO 0 0 x x x X 3F82 TM2MD 7 Timer 2 Timer 2 Clock source count control operation mode TM3PWM TMSCK2 TMS3CK1 TMSCKO 5 0 0 X 3F83 TM3MD V 8 Timer 3 P13 output at Clock source count control TM2PWM operation
57. 04 05 06 07 0 5 42 z 70 lt U pA NO N Package code SDIP042 P 0600 Figure 12 1 2 MN101CP427 DP DC EPROM Programming Adapter Connection Refer to the pin connection drawing of the 256 K bit EPROM 270256 EPROM Version XII 9 Chapter 12 Appendices do o wo o ANH CODA 03020320 lt lt lt 26 gt gt gt gt gt e T N e N A A A A A A4 A14 A5 Vss A6 NOE A7 Vss Vss MN101CP427 Vss Vss 44 Pin QFP Vss D7 Vss 06 Vss D5 VDD D4 Vss x A A N lt lt lt lt gt Package code QFP044 P 1010 Pin pitch 0 8mm Figure 12 1 3 101 427 EPROM Programming Adapter Connection Refer to the pin connection drawing of the 256 K bit EPROM 27C256 XII 10 EPROM Version Chapter 12 Appendices o Ul wo vo HAAAHGH DA lt lt lt 2 A4 37 P64 14 5 38 P65 Vss 39 P66 NOE 7 40 P67 be Vss 41 P70 SS 21 101 427 Vss Vss 43 NRST 48 Pin TQFP Vss 44 MMOD Vss D7 45 P87 Vss D6 46 P86 Vss D5 47 P85 VDD D4 48 P84 Vss 8 lt 22 A A A gt lt lt lt lt gt Package code TQFP048 P 0707B Pin pitch 0 5 mm Figure 12 1 4 101 427 EPROM Programming Adapter Connection Refer to the pin connection drawi
58. 18 X 34 Operation Chapter 10 Serial Interface 0 Transmission Timing Stop Stop bit bit TXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 12 Transmission Timing parity bit is enabled Stop bit TXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 13 Transmission Timing parity bit is disabled Operation 35 Chapter 10 Serial Interface 0 Timing Stop Stop bit bit RXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 14 Reception Timing parity bit is enabled Stop Stop bit bit RXD pin SCOBSY Interrupt SCOIRQ Figure 10 3 15 Reception Timing parity bit is disabled X 36 Operation Chapter 10 Serial Interface 0 ia Sequence Communication bit Y n 1 st reception 2 nd reception bit UART interrupt signal lt 2 nd reception is disabled On the above sequence communication this UART cannot regard start bit when the H period of the interrupt signal generated inside at reception complete and the falling edge of start bit input from the RXD pin are happened at the same time 1 machine cycle Therefore from the 2nd reception the operation cannot be properly executed To prevent this the reception interrupt signal and the falling edge of the start bit should not be happened at the same time There are 2 ways to solve it Method 1 by stop bit Set t
59. 2 as ROM option On detection of errors hardware reset is done by force in LSI Remote control output Based on the timer 3 output a remote control carrier with duty cycle of 1 2 or 1 3 can be output Buzzer output Output frequency can be selected from fs 2 15 27 fs 2 15 212 A D converter 10 bits X 8 channels input Serial interface 1 type Serial interface 0 Half duplex UART Synchronous serial interface OSynchronous serial interface Transfer clock source fs 2 fs 4 fs 16 UART baud rate timer timer 3 output External clock MSB LSB can be selected as the first bit to be transferred Any transfer size from 1 to 8 bits can be selected OHalf duplex UART Baud rate timer Timer 3 Parity check overrun error framing error detection Transfer size 7 to 8 bits can be selected When using timer 3 the transfer rate for a 12 MHz oscillation are 19200 9600 4800 2400 1200 300 bps Hardware Functions I 5 Chapter 1 Overview LED driver Port Package 1 6 Hardware Functions 8 pins ports 27 pins 5 LED large current driver pins 8 pins Input ports 12 pins 5 dual function for External interrupt 4 pins 7 One pin can also be used for zero cross input dual function for A D input 8 pins Special pins Operation mode input pin 1 pin Reset input pin 1 pin Power pin 2 pins Oscillation pin 4 pins 8 42 pin SDIP code name SDIP042 P 0600 44 pin QFP 10 mm square
60. 6 5 4 3 2 1 0 2 21 3 2 2 P2IN1 P2INO Atreset XXXX P2IN Input data 0 Pin is Low Vss level 1 Pin is High VDD level Port 2 input register P2IN x OSF22 R 7 6 5 4 3 2 1 0 P2PLU P2PLUS P2PLU2 P2PLU1 At reset 0000 P2PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 2 pull up resistor control register P2PLU 03 42 R W Figure 4 4 1 Port 2 Registers Pot2 IV 15 Chapter 4 Ports 4 4 3 Block Diagram eo Pull up resistor control 2 0 2 3 gt Write Read S z gt P20 P22 P23 Port input data 1 21 0 2 3 Read Schmitt input External interrupt Figure 4 4 2 Block Diagram P20 P22 to P23 P2PLU1 Pull up resistor control D gt Write 5 Rese R Special function input data o jl P24 Write Read M 1 AC zero cross detection circuit Port input dat pea Ulo ort input data n X Schmitt input AC zero cross input External intrerrupt Figure 4 4 3 Block Diagram P21 Rese tT 2 7 Port output d
61. ADD imm4 Dm Dm sign imm4 gt Dm 3 2 1000 00Dm lt 4 gt 6 61 ADD imm8 Dm 8 4 2 0000 10Dm lt 8 62 ADDC ADDC Dn Dm Dm Dn CF gt Dm 2 0011 1011 DnDm 63 ADDW ADDW DWn DWm DWm DWn gt DWm e 3 3 0010 0101 71 64 ADDW DWn Am Am DWn gt Am 3 3 0010 0101 10Da 64 ADDW imm4 Am Am sign imm4 gt Am e 3 2 1110 110a lt 4 gt 6 65 ADDW 8 Am sign imm8 Am 5 3 0010 1110 110a lt 8 7 65 ADDW imm16 Am Am imm16 gt Am 7 4 0010 0101 011a 4416 gt 66 ADDW imm4 SP SP sign imm4 SP 3 2 1111 1101 0 6 66 8 5 SP sign imm8 gt SP 412 1111 1100 48 77 67 ADDW imm16 SP SP imm16 SP 714 0010 1111 1100 lt 16 ed 67 ADDW imm16 DWm DWm imm16 5DWm 1 0010 0101 010d lt 16 gt 68 ADDUW ADDUW Dn Am Am zero Dn gt Am eee 3 0010 1000 8 69 ADDSW ADDSW Dn Am Am sign Dn gt Am 3 3 10010 1001 1aDn 70 SUB SUB Dn Dm when DnzDm Dm Dn Dm 2 0010 1010 DnDm 71 SUB Dn Dn 01010 1 211 1000 01Dn 71 SUB imm8 Dm Dm imm8 Dm 0010 1010 DmDm lt 8 72 SUBC SUBC Dn Dm Dm Dn CF gt Dm 2 0010 1011 DnDm 73 SUBW SUBW DWn DWm DWm DWn DWm 3 0010 0100 00Dd 71 74 SUBW DWn Am Am DWn Am 3 3 0010 0100 10Da 74 SUBW imm16 DWm DWm imm16 DWm 4 0010 0100 010d lt 16 gt 75 SUBW imm16 Am Am imm16 Am 1 0010 0100 011 lt 16 gt 75 MULU MULU
62. Chapter 10 10 2 Control registers is used as a buzzer output pin as well When the 6 7 of the oscillation control register DLYCTR is 1 buzzer output is enabled Port 0 IV 5 Chapter 4 Ports 4 2 2 POOUT POIN PODIR POPLU IV 6 Registers 1 6 2 1 0 6 POUT2 POUT1 At 0 000 Port 0 output register POOUT x 03F10 R W 1 0 POING POIN2 POINO Port 0 input register x OSF20 R 7 6 2 1 0 PODIR6 PODIR2 PODIR1 PODIRO POOUT Output data 0 L Vss level 1 level Atreset X XXX POIN Input data 0 Pin is low Vss level 1 Pin is high VDD level Atreset 0 000 Port 0 direction control register PODIR x 03F30 R W 7 6 2 1 0 POPLU6 POPLU2 POPLU1 POPLUO PODIR mode selection 0 Input mode 1 Output mode Atreset 0 000 POPLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 0 pull up resistor control register POPLU x 03F40 R W Port 0 Figure 4 2 1 Port 0 Registers Chapter 4 Ports 4 2 3 Block Diagram
63. Data Buffer Registers Serial Interface 0 has a 8 bit shift register to shift the transmission and reception data and a 8 bit data buffer register for reception Serial Interface 0 Transmission Reception Shift Register SCOTRB 7 6 5 4 3 2 1 0 SCOTRB SCOTRB7 SCOTRB6 SCOTRB5 SCOTRB4 SCOTRB3 SCOTRB2 SCOTRB1 SCOTRBO at reset XXX XX XXX Figure 10 2 1 Serial Interface 0 Transmission Reception Shift Register SCOTRB 03 55 R W Serial Interface 0 Received Data Buffer SCORXB 7 6 5 4 3 2 1 0 SCORXB sCoRXB7 SCORXB6 SCORXB5 SCORXB4 SCORXB3 SCORXB2 SCORXB1ISCORXB0 at reset X XXX XX XX Figure 10 2 2 Serial Interface 0 Reception Data Buffer SCORXB 03 56 Control Registers X 5 Chapter 10 Serial Interface 0 10 2 3 Mode Registers Control Registers Serial Interface 0 Mode Register 0 SCOMDO SCOMDO X 6 7 6 SCOCE1 sco SCOSTE 22 at reset 00XX000 SCOLNG2 SCOLNG1 SCOLNGO Synchronous serial transfer bit count 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Joj joj2jo j 2 o 1 bit SCOSTE Synchronous serial data transfer start condition selection 0 Disable start condition Enable start c ondition SCODIR First bit to be transferred 0 MSB first
64. Direction Control X 3F36 P7DIR1 P7DIRO 0 0 Port 7 Direction Control P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIRO 0 0 0 0 0 0 0 0 Port 8 I O Direction Control X 3F37 X 3F38 P14TCO P13TCO P12TCO P10TCO 0 0 0 0 9 Port Special function pin control VO Port Special function pin cntrol PAIMD7 PAIMD6 PAIMD5 PAIMD4 PAIMD2 PAIMD1 PAIMDO 0 0 0 0 0 0 0 0 Port Special function pin control 6 POPLU2 POPLU1 POPLUO 0 0 0 0 Port 0 pull up Port 0 pull up register ON OFF control register ON OFF control P1PLU4 P1PLU2 P1PLU1 0 0 0 0 0 Port 1 pull up register ON OFF control X 3F40 X 3F41 P2PLU3 P2PLU2 P2PLU1 P2PLUO 0 0 0 0 Port 2 pull up register ON OFF control X 3F42 Note Inicial value is unstable No data Special Function Registers List XII 17 Chapter 12 Appendices Bit Symbol Initial Value Description Address Register 5 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLUO 0 0 0 0 0 0 0 0 X 3F46 P6PLU IV 18 Port 6 pull
65. Dn Dm Dm Dn DWk 00 0 9538 0010 1111 111D 4 76 DIVU DIVU Dn DWm DWm Dn DWm l DWm h 9 0010 1110 111d 15 7 Dn Dm Dm Dn PSW 2 0011 0010 DnDm 78 imm8 Dm Dm imms PSW 9 4 2 1100 00Dm 48 78 CMP imm8 abs8 mem8 abs8 imms PSW eee 5 3 0000 0100 abs 8 8 gt 79 CMP imm8 abs12 mem8 abs12 imm8 PSW 0000 0101 abs 12 gt 448 gt 79 imm8 abs16 mem8 abs16 imm8 PSW 9 5 0011 1101 1000 abs 16 e HBL gt 80 CMPW CMPW DWn DWm DWm DWn PSW oeeo 3 0010 1000 01Dd 1 81 CMPW DWn Am Am DWn PSW 3 0010 0101 11Da 81 CMPW An Am Am An PSW 0010 0000 01Aa 2 82 CMPW imm16 DWm DWm imm16 PSW 3 1100 110d 4416 uum 82 CMPW imm16 Am Am imm16 PSW 3 1101 1104 lt 16 gt 83 Logical manipulation instructions AND AND Dn Dm Dm amp Dn Dm 0 910103 2 0011 0111 DnDm 84 AND imm8 Dm Dm amp imm8 Dm 016 066 4 2 0001 11Dm lt 8 gt 84 AND imm8 PSW PSW amp imm8 PSW eeee5 3 0010 1001 0010 48 gt 85 OR OR Dn Dm DmIDn gt Dm 3 2 0011 0110 DnDm 86 OR imm8 Dm Dmlimm8 Dm 01 4 2 0001 10Dm lt 8 gt 86 OR imm8 PSW PSWlimm8 PSW 5 0010 1001 0011 448 gt 87 XOR XOR Dn Dm Dm Dn2Dm 3 2 0011 1010 DnDm 9 88 XOR imm8 Dm Dm imm8 gt Dm
66. Dn mem8 d8 SP 5 3 0010 0111 01Dn d8 gt 3 34 MOV Dn d16 SP 16 5 7 4 0010 0111 00Dn 416 en ud 34 MOV Dn io8 8 408 4 2 0111 00 lt 08 gt 35 Dn abs8 Dn mem8 abs8 1 1 1 1412 0101 01Dn abs 8 35 MOV Dn abs12 Dn mem 8 abs12 1 1 1 1512 0101 00 abs 12 gt 36 MOV Dn abs16 8 516 1 1 1 1714 0010 1101 O0Dn abs 16 gt 36 MOV imme io8 imm8 mem8 IOTOP io8 6 3 0000 0010 408 gt lt 8 gt 37 MOV imm8s abs8 8 gt 8 058 6 3 0001 0100 abs 8 lt 8 gt 37 MOV imm8 abs12 8 gt 8 0512 1 1 1 17 3 0001 0101 abs 12 gt 48 gt 38 imm8 abs16 imm8 mem8 abs16 1 1 1 1915 0011 1101 1001 abs 16 gt 48 gt 38 MOV Dn HA 8 1 1 1 1212 1101 00Dn 39 MOVW MOVW An DWm mem16 An gt DWm 2 3 1110 00 40 MOVW 16 gt 1 1 1 1314 0010 1110 10Aa 4 40 MOVW d4 SP DWm mem16 d4 SP gt DWm 3 3 1110 0114 lt d4 gt 24 MOVW d4 SP Am mem16 d4 SP gt Am 3 3 1110 010a lt d4 gt 2141 MOVW d8 SP DWm mem16 d8 SP gt DWm 5 4 0010 1110 0114 d8 gt 3 42 MOVW d8 SP Am mem16 d8 SP gt Am 5 4 0010 1110 010a d8 gt 3 42 MOVW d16 SP DWm _ 16 016
67. F Read 777 P6INO 7 n Read NA IV 19 Chapter 4 Ports 4 6 Port7 4 6 1 Description Port Setup Each bit of the port 7 control I O direction register P7DIR can be set individually to set pins as input or output The control flag of the port 7 direction control register P7DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 7 direction control register P7DIR to 0 and read the value of the port 7 input register P7IN To output data to pin set the control flag of the port 7 direction control register P7DIR to 1 and write the value of the port 7 output register P7OUT Each pin can be set individually if pull up pull down resistor is added or not by the port 7 pull up pull down resistor control register P7PLUD But pull up pull down cannot be mixed Set the control flag of the port 7 pull up pull down resistor control register P7PLUD to 1 to add pull up or pull down resistor The pin control register 1 FLOAT1 select if pull up resistor or pull down resistor is added The bpO of the pin control register 1 FLOAT1 is set to 1 for pull down resistor set to 0 for pull up resistor At reset the P70 to P71 input mode is selected and pull up resistors are disabled high impedance output 1 P70 P71 not allocated to 42 pin SDIL package type P71 is not allocated to 44 QFP package typ
68. Hans Pinsel Strasse 2 85540 Haar Tel 89 46159 156 Fax 89 46159 195 B U K SALES OFFICE Panasonic Industrial Europe Ltd PIEL Electric component Group Willoughby Road Bracknell Berkshire RG12 8FP Tel 1344 85 3773 Fax 1344 85 3853 FRANCE SALES OFFICE Panasonic Industrial Europe G m b H PIEG Paris Office 270 Avenue de President Wilson 93218 La Plaine Saint Denis Cedex Tel 14946 4413 Fax 14946 0007 B ITALY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Milano Office Via Lucini N19 20125 Milano Tel 2678 8266 Fax 2668 8207 TAIWAN SALES OFFICE Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6th Floor Tai Ping amp First Building No 550 Sec 4 Chung Hsiao E Rd Taipei 10516 Tel 2 2757 1900 Fax 2 2757 1906 Kaohsiung Office 6th Floor Hsien 1st Road Kaohsiung Tel 7 223 5815 Fax 7 224 8362 Matsushita Electric Industrial Co Ltd 2001 HONG KONG SALES OFFICE Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11 F Great Eagle Centre 23 Harbour Road Wanchai Hong Kong Tel 2529 7322 Fax 2865 3697 SINGAPORE SALES OFFICE Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 Tel 390 3688 Fax 390 3689 MALAYSIA SALES OFFICE Panasonic Industrial Company Malaysia Sdn Bhd Head Office PICM Tingkat 16B Menara PKNS PJ No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul
69. Name 0 ait vO Function Description P20 29 Input IRQO Input port 2 4 Bit input port P21 30 IRQ1 ACZ A pull up resistor for each bit can be selected P22 31 IRQ2 individually by the P2PLU register At reset pull up P23 32 IRQS resistors are disabled P23 is not allocated to 42 SDIP 44 QFP package type P27 43 Input NRST Input port 2 P27 has an n channel open drain configuration When 0 is written and the reset is initiated by software a low level voltage will be output P60 33 VO VO port 6 8 Bit CMOS tri state VO port P61 34 Each bit can be set individually as either an input or P62 35 output by the P6DIR register A pull up resistor for each P63 36 bit can be selected individually by the P6PLU register P64 37 At reset when the input mode is selected pull up P65 38 resistors are disabled high impedance output P66 39 P67 40 P70 45 VO VO port 7 8 Bit CMOS tri state VO port P71 46 Each bit can be set individually as either an input or output by the P7DIR register A pull up or pull down resistor for each bit can be selected individually by the P7PLUD register However pull up and pull down resistors cannot be mixed At reset when the input mode is selected pull up resistors are disabled high impedance output P70 P71 are not allocated to 42 SDIP package type P71 is not allocated to 44 QFP package type P80 4 VO LEDO VO port 8 8 Bit CMOS tri state VO port P81 3 LED1 Each individual bit can be switch
70. Note The above 2 to 4 can be set at once Start the A D conversion after the current flowing through the ladder resistors stabilizes The wait time should be decided by the calculated time from the ladder resistance max 80 and the external bypass capacitor connected between Vrer and Vner Operation XI 13 Chapter 11 A D Converter 11 3 3 Cautions Since A D conversion can be damaged by noise easily antinoise measures should be taken BAntinoise transaction For A D input analog input pin add condenser near the 55 pins of micro controller VDD VDD Vss 10 AN7 T Vss Set near the Vss pin Figure 11 3 2 A D Converter Recommended Example 1 kept 1 input impedance R of A D input pin should be under 500 and the external capacitor more than 1000 pF under 1 uF 2 The A D conversion frequency should be set with consideration of R C time constant 3 Atthe A D conversion if the input level of micro controller is changed or the peripheral added circuit is switched to ON OFF the A D conversion may work wrongly because the analog input pins and power pins does not fix At the check of the setup confirm the wave form of analog input pins 1 For high precision of A D conversion the following cautions on A D converter should be Equivalent circuit block that outputs analog signal microcontroller
71. P10 RMOUT P06 BUZZER 02 5 0 PO1 SBIO RXD 5 VSS OSC1 OSC2 VDD PA7 AN7 Pin Configuration 44 QFP Top view C cO oa LED6 P86 lt gt 46 LED5 P85 LED4 P84 48 LED3 P83 1 LED2 P82 2 1 3 3 Chapter 1 Overview P21 IRQ1 ACZ P23 IRQ3 P22 IRQ2 P20 IRQO P14 TM4IO 12 2 11 61 60 P10 RMOUT POG BUZZER 02 5 0 PO1 SBIO RXD MN101C457 48 92222222 OTA st LO KO Qao 222222 lt lt lt lt lt lt 4 Pin Configuration 48 TQFP Top view Pin Description I 9 Chapter 1 1 3 2 Overview Pin Specification Table 1 3 1 Pin Specification Pins Special Functions 220 rol Functions Description SBOO in out PODIRO POPLUO SBO0 Serial Interface 0 transmission data output TXD UART transmission data output P01 SBIO in out PODIR1 POPLU1 SBIO Serial Interface 0 reception data input UART reception data input SBTO in out PODIR2 POPLU2 SBTO Serial Interface 0 clock I O BUZZER in out PODIR6 POPLU6 BUZZER Buzzer output P10 RMOUT in out P1DIRO P1PLUO RMOUT Remote control carrier output P11 in out P1DIR1 P1PLU1 P12 TM2IO in out P1DIR2 P1PLU2 Timer 2 I O
72. P13 in out P1DIR3 P1PLUS Timer 3 I O P14 TM4IO in out P1DIR4 Timer 4 I O P20 IRQO in P2PLUO IRQO External interrupt 0 P21 IRQ1 ACZ in P2PLU1 RQ1 External interrupt 1 ACZ Zero cross input p22 IRQ2 in P2PLU2 102 External interrupt 2 237 IRQ3 in PaPLUS RQ3 External interrupt P27 NRST in NRST Reset P60 in out PeDIRO PePLUO P61 in out PeDIR1 2 in out PeDIR2 P6PLU2 P63 in out P6DIR3 PePLUS P64 in out P6DIR4 04 P65 in out PeDIR5 95 P66 in out P6DIR6 P6PLU6 P67 in out PeDIR7 P6PLU7 P70 in out P7DIRO 7 P71 in out P7DIR1 P7PLUD1 P80 LEDO in out P8DIRO P8PLUO LEDO LED driver pin 0 P81 LED1 in out P8DIR1 P8PLU1 LED1 LED driver pin 1 P82 LED2 in out P8DIR2 P8PLU2 LED2 LED driver pin 2 P83 LED3 in out P8DIR3 P8PLU3 LED3 LED driver pin P84 LED4 in out P8DIR4 P8PLU4 LED4 LED driver pin 4 P85 LED5 in out P8DIR5 P8PLU5 LEDS LED driver pin 5 LED6 in out P8DIR6 P8PLU6 LED6 LED driver pin 6 P87 LED7 in out P8DIR7 P8PLU7 LED7 LED driver pin 7 PAO ANO in 7 PAPLUDO Analog 0 input PA1 AN1 in 7 __ 1 AN1 Analog 1 input PA2 AN2 in 7 PAPLUD2 AN2 Analog 2 input PA3 AN3 in 7 PAPLUDS AN3 Analog input PA4 AN4 in 7 PAPLUDA Analog 4 input 5 5 in 7 5 AN5 Analog 5 inp
73. PC BGT label if VE NF ZF 0 PC 5 d7 label H gt PC 0010 0010 if VFANF ZF 1 PC 5 PC NOTE Pages for MN101C Series Instruction Manual 1 d4sign extension 2 47 sign extension 8 d11 sign extension XII 24 Instruction Set MN101C SERIES INSTRUCTION SET Chapter 12 Appendices Group Mnemonic Operation Flag Re xten Machine Code Notes vF NFIcFIzF Size peat sion 1 2 3 4 5 6 P 8 9 10 11 Bcc BGT label if VF NFJZF 0 PC 6 dit labe eH5PO 6 3 4 0010 0011 0001 lt 011 3 107 if VFANF ZF 1 PC 63PC BHI label 12 0 5 47 5 3 4 0010 0010 0010 47 2 108 if CFIZF 1 PC 52PC BHI label if CFIZF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0010 lt 11 53 108 if CFIZF 1 PC 62PC BLS label 12 1 5 47 5 3 4 0010 0010 0011 47 2 109 if CFIZF 0 5 BLS label if CFIZF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0011 lt 11 53 109 if CFIZF 0 6 BNC label if NF 0 PC 5 d7 label H3PC 5 3 4 0010 0010 0100 d7 H 2 11 if NF 1 PC 5PC BNC
74. R W Readable Writable R Readable only XI 4 Control Registers Chapter 11 A D Converter 11 2 2 Control Registers A D Converter Control Register 0 ANCTRO 7 6 5 4 3 2 1 0 At reset XX XXOXXX ANCTRO ANSH1 ANSHO ANCK1 ANCKO ANLADE ANCHS2 ANCHSO ANCHS 1 ANCHSO Analog input selection 0 0 ANO 1 AN1 0 1 0 AN2 1 AN3 0 0 4 1 5 1 0 AN6 1 AN7 ANLADE A D ladder resistance control 0 A D ladder resistance OFF A D ladder resistance ON ANCK1 ANCKO A D conversion clock 1 9 1 0 fs 2 1 fs 4 1 0 fs 8 1 fxx2 as 800 ns lt TaD lt 15 26 us ANSH1 ANSHO Sample and hold time 0 x2 9 1 6 1 0 Tap x 18 1 Not to use Sampling and holding time is decided by the input impedance at analog input means the cycle for A D conversion clock Figure 11 2 1 A D Converter Control Register 0 ANCTRO x 03F90 R W Control Registers XI 5 Chapter 11 A D Converter A D Converter Control Register 1 ANCTR1 7 6 5 4 3 2 1 0 At reset 0 1 5 5 5 ANST A D conversion status 0 A D conversion is completed stopped 1 A D conversion is started in progress Figure 11 2 2 A D Converter Control Regist
75. Registers The external interrupt input signals which operated in each external interrupt 0 to 3 interface generate interrupt requests External interrupt 0 to 3 interface are controlled by the external interrupt control register IRQnICR And external interrupt interface 0 to 1 are controlled by the noise filter control register NFCTR When the external interrupt 1 is used for AC zero cross detection it is controlled by the pin control register 1 FLOAT1 Table 3 3 2 shows the list of registers control external interrupt 0 to 3 Table 3 3 2 External Interrupt Control Register External Interrupt Register Address R W Function Page IRQOICR x O3FE2 R W interrupt 0 control register lll 17 External interrupt O NFCTR R W Noise filter control register Ill 32 IRQ1ICR R W External interrupt 1 control register Ill 18 External interrupt 1 NFCTR R W Noise filter control register Ill 32 FLOAT1 4 R W Pin control register 1 Ill 33 External interrupt 2 IRQ2ICR R W interrupt 2 control register lll 19 External interrupt 3 5 IRQ3ICR XO3FEC R W External interrupt control register Ill 20 R W Readable Writable External interrupt 3 can be used only for 48 pin TQFP package type External Interrupts 31 Chapter 3 Interrupts BNoise Filter Control Register
76. Reset Released Sequence On this LSI the oscillation is stopped during the NRST pin p27 is low level Reset II 25 Chapter 2 CPU Basics 2 5 2 Oscillation Stabilization Wait time Oscillation stabilization wait time is the required time for oscillation to stabilize from halt condition Oscil lation stabilization wait time is automatically inserted at reset release and at recovering from STOP mode At recovering from STOP mode the oscillation stabilization wait time control register DLYCTR is set to select the oscillation stabilization wait time At releasing from reset oscillation stabilization wait time is fixed The timer that counts oscillation stabilization wait time is also used as a watchdog timer at anytime except at reset release and at recovering from STOP mode Watchdog timer is initiated at reset and at STOP mode and starts counting from the initialize value 0000 when system clock fs is as clock source After oscillation stabilization wait time it continues counting as a watchdog timer Chapter 8 Watchdog timer Block Diagram of Oscillation Stabilization Wait Time watchdog timer WDCTR WDEN reset input gt Mr ML Y R 7 internal reset release 5 5 _ 4 MUX fs 2
77. Setup Example Timer 4 Setup Example Chapter 6 16 Bit Timer Timer 4 generates an interrupt constantly for timer function Fosc fosc 20 MHz at operation is selected as a clock source to generate an interrupt every 1000 cycles 50 us An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 TM4EN 0 Select the normal timer operation x 3F84 bp5 1 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 000 Set the interrupt generation cycle TM40C x 3F75 x 3F74 x 03E7 Set the interrupt level TMAICR x 3FEF bp7 6 TM4LV1 0 10 Enable the interrupt TMAICR x 3FEF bp1 1 Start the timer operation TM4MD x 3F84 bp6 4 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the TMAPWM flag of the TM4MD register to 0 to select the normal timer operation Select fosc as a clock source by the TM4CK2 0 flag of the register Set the interrupt generation cycle to the timer 4 compare register 4 The cycle is 1000 The set value should be 1000 1 999 03 7 Set the interrupt level by the TM4LV1 0 flag of the timer 4 interrupt control register TM4ICR If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt Flag Setup Set
78. Time Base Timer 8 Bit Free running Timer 7 2 Control Registers Timer 5 consists of binary counter TM5BC compare register 5 and is controlled by mode register TM5MD Time base timer is controlled by mode register TM5MD too 7 2 1 Control Registers Table 7 2 1 shows the registers that control timer 5 time base timer Table 7 2 1 Control Registers Register Address Function Page TM5BC x 03F68 Timer 5 binary counter VII 5 TM5OC 78 Timer 5 compare register VII 5 Timer 5 TM5MD x 03F88 Timer 5 mode register VIL 6 Timer 5 interrupt control register Ill 24 TM5MD x 03F88 Timer 5 mode register VIL 6 Timer base timer TBICR 7 Time base interrupt control register Ill 25 R W Readable Writable R 4 Readable only Control Registers 7 2 2 Programmable Timer Registers Timer 5 is a 8 bit programmable counter Chapter 7 Time Base Timer 8 Bit Free running Timer Programmable counter consists of compare register and binary counter TM5BC Binary counter is a 8 bit up counter When the TM5CLRS flag of the timer 5 mode register TM5MD is 0 and the interrupt cycle data is written to the compare register TM5OC the timer 5 binary counter TM5BC is cleared to 00 Timer 5 Binary Counter TM5BC 7 6 5 4 3 2 1 0 TM5BC 5 7 TM5BC6
79. WDIRQ of the non maskable interrupt NMI is generated Table 8 3 1 Watchdog Timer Period WDSEL2 WDSEL1 Watchdog timer period 0 0 216 X system clock 0 1 218 X system clock 1 X 2 X system clock System clock is decided by the CPU mode control register CPUM The watchdog timer period is generally decided from the execution time for main routine of program That should be set the longer period than the value of the execution time for main routine divided by natural number 1 2 And insert the instruction of the watchdog timer clear to the main routine as that value makes the same cycle If the watchdog timer interrupt service routine does not respond to a watchdog timer interrupt for resetting the chip the hardware responds to the next one by pulling the RESET pin low to reset the chip Operation VIII 5 Chapter 8 Watchdog Timer mWatchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features are as follows 1 2 3 4 5 6 In NORMAL IDLE SLOW mode the system clock is counted The counting is continued regardless of switching at NORMAL IDLE SLOW mode In HALT mode the watchdog timer is not stopped In STOP mode the watchdog timer is cleared automatically by hardware In STOP mode the watchdog interrupt cannot be generated After releasing reset or recovering from STOP the counting is executed for the duration of the oscillation stabiliza
80. cross detector IRQ2 Edge selectable IRQ3 Edge selectable Timers 5 timers 4 can operate independently 8 Bit timer for general use 1 set 8 Bit timer for general use UART baud rate timer 1 set 8 Bit free running timer 1 set Time base timer 1 set 16 Bit timer for general use 1 set Timer 2 8 Bit timer for general use Square wave output Timer pulse output PWM output Event count Clock source fs fs 4 fx 4 2 pin input Timer 3 8 Bit timer for general use or UART baud rate timer Square wave output Timer pulse output Event counter Serial interface transfer clock output 16 Bit cascade connection function connect to timer 2 Remote control carrier output Clock source fosc fs 4 fs 16 pin input Timer 4 16 Bit timer for general use Square wave output Timer pulse output PWM output Event count Input capture function Clock source fosc fs 4 fs 16 TM4IO pin input I 4 Hardware Functions Chapter 1 Overview Timer 5 8 Bit free running timer Time base timer 8 Bit free running timer Clock source fosc fs 4 fx 4 fosc 2 8 fx 2 4 Time base timer Interrupt generation cycle fosc 2 fosc 2 fosc 2 fosc 2 fosc 21 fx 27 4 fx 28 4 fx 2 4 1 21054 213 4 at 32 768 kHz for low speed oscillation input can be set to measure one minute intervals Watchdog timer Watchdog timer frequency can be selected from 15 279 15 218 fs
81. device reliability may be damaged 6 At not change from to 12 5 V or from 12 5 V to Vit 7 After a program is written screening at a high temperature storage before mounting is recom mended Program Read 1 High temperature storage 125 C 48h 1 1 Mounting EPROM Version XII 3 Chapter 12 Appendices 12 1 3 Erasing Data in Windowed Package PX AP101C42 FBC SDC To erase data of an internal EPROM with windowed packaging 0 gt 1 UV light at 253 7 nm is used to irradiate the chip through a permeable cover The recommended exposure is 10 W s cm This coverage can be achieved by using a commercial UV lamp positioned 2 to 3 cm above the package for 14 20 minutes when the illumination intensity of the package surface is 12000 uW cm Remove any filters attached to the lamp With a mirrored reflector plate to the lamp illumination intensity will increase 1 4 to 1 8 times and decrease the erasure time If the window becomes dirty with oil adhesive etc UV light permeability will get worse causing the erasure time to increase If this happens clean with alcohol or another solvent that will not harm the package The above recommended exposure has enough leeway with several times as much as it takes to erase all the bits It is based on the reliable data over all temperature and voltage The lump and the level of illumination should be regularly checked and well controlled
82. each cycle of instruction execution by micro program control Instruction decoder uses pipeline process to decode instruction queue at one cycle before control signal is needed 2 1 5 Registers for Address Registers for address include program counter PC address registers AO A1 and stack pointer SP iProgram Counter This register gives the address of the currently executing instruction It is 19 bits wide to provide access to a 256 KB address space in half byte 4 bit increments The LSB of the program counter is used to indicate half byte instruction The program counter value after reset is stored from the value of vector table at the address of 04000 Program counter 6 Overview Chapter 2 CPU Basics Address Registers 0 A1 These registers are used as address pointers specifying data locations in memory They support the operations involved in address calculations i e addition subtraction and comparison Those pointers are 2 bytes data Transfers between these registers and memory are always in 16 bit units Either odd or even address can be transferred At reset the value of address register is undefined 15 0 EStack Pointer SP This register gives the address of the byte at the top of the stack It is decremented during push opera tions and incremented during pop operations At reset the value of SP is undefined 15 0 2 1 6 Registers for Data Registers for
83. for Synchronous Serial Interface Pin Data output pin Data input pin Clock VO pin Setup item SBTO SBOO pin 580 pin Internal clock External clock master communication slave communication Pin 00 P01 P02 580 5800 independent 580 SBOO 2 SCOMD3 SCOIOM End Serial data output Serial data input Serial clock VO Port unction SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Push pull Style Nch open drain Nch open drain Nch open drain SCOMD3 SCOSBOM SCOMD3 SCOSBTM Output mode Input mode Output mode Input mode PODIR PODIRO PODIR PODIR1 PODIR PODIR2 Added Not added Added Not added Added Not added Added Not added ull up POPLU POPLUO POPLU POPLU1 POPLU POPLU2 WPins Setup 2 channels at transmission Table 10 3 8 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at transmission SBIO pin can be used as a general port Table 10 3 8 Setup for Synchronous Serial Interface Pin 2 channels at transmission Data pin Serial unused pin Clock VO pin Setup item SBT1 pin 5800 580 pin Internal clock External clock master communication slave communication Pin P01 P02 580 5800 connected 580 SBOO pin SCOMD3 SCOIOM Serial data output 1 input Serial clock VO Port Functio
84. interrupt interrupt level fi Lvi LVO ilie The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 7 Timer Interrupt Control Register TM3ICR x O3FEE R W 22 Control Registers Chapter 3 Interrupts Timer 4 Interrupt Control Register TM4ICR The timer 4 interrupt control register TM4ICR controls interrupt level of timer 4 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter enable flag MIE of PSW is 0 When the interrupt level flag is set to level TM4LV1 TM4LVO the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 TM4 TM4 ET TM4ICR LV1 LVO At reset 00 00 TM4IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated TM4IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt 4 TM interrupt level fi LVO The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 8 Timer 4 Interrupt Control Register TM4ICR x OS3FEF R W Control Registers III 23 Chapter 3 Interrupts Timer 5 Interrupt Control Register TM5
85. is started the BUSY flag SCOBSY of the SCOCTR register is set to 1 That is cleared to 0 when the communication complete interrupt SCOIRQ is generated BOther Control Flag Setup Table 10 3 4 shows flags that are not used at clock synchronous communication So they need not to be set or monitored Table 10 3 4 Other Control Flag Register Flag Detail SCOBRKF Brake status reception monitor SCOMD1 SCOERE Error monitor SCONPE Parity is enabled SCOPM1 to 0 Added bit specification SCOMD2 SCOFM1 to 0 Frame mode specification SCOBRKE Brake status transmission control SCOORE Overrun error detection SCOCTR SCOPEK Parity error detection SCOFEF Frame error detection X 18 Operation Chapter 10 Serial Interface 0 Transmission Timing Tc 2 ts Tc ts Tc Clock SBTO pin Output data SBOO pin Start condition is enabled Output data SBOO pin Start condition is disabled Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ Write data SCOBSY is 1 on clock input at slave transmission to SCOTRB without start condition Figure 10 3 3 Transmission Timing falling edge 2 18 1 ts 54 2 3 Clock SBTO pin Output data SBOO pin Start condition is enabled Output data SBOO pin Start condition is disabled Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Write data SCOBSY is 1 o
86. low level at other level BAC Zero Cross Detector External interrupt 1 AC zero cross detector sets the IRQ1 pin to the high level when the input signal P21 ACZ pin is at intermediate range At the other level IRQ1 pin is set to the low level AC zero cross can be detected by setting the P211M flag of the pin control register FLOAT1 to 1 approx 10 ms at 50 Hz approx 8 3 ms at 60 Hz AC line waveform gt Ideal i gt IRQ1 Actual j IRQ1 Point A gt Figure 3 3 6 AC Line Waveform and IRQ1 Generation Timing Actual IRQ1 interrupt request is generated several times at crossing the 1 2 of AC line wave form So the filtering operation by the program is necessary If you select the noise filter the judgement of this program can be easier But it can not be used for the recover when OSC is stopped at the back up mode 38 External Interrupts Chapter 3 Interrupts WAC Zero Cross Detector Setup Example External interrupt 1 AC zero cross detector generates the external interrupt 1 IRQ1 by using P21 ACZ pin The sampling clock is set to fs 2 and the noise filter is used An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the interrupt edge IRQ1ICR x 3FE3 bp5 REDG1 1 2 Select the noise filter and its sampling clock x 3F8A bp3 NF1EN 1 bp5 4 NF1CKS1 0
87. only 101C11 101C42 and 101 45 48 PIN Use this adapter board with EV board PRB EV101C15 Improper matching may cause any damage to the ICE The switches that the adapter board provides for configuring the probe are described below Adapter Board Layout 4 1 SW1 OSC control Set this switch to its USR position to drive the in circuit emulator with the crystal oscillator 1 built into the target board If there is no oscillator on the target board set this switch to the ICE position to use the oscillator built into the probe 2 SW2 XI control Set this switch to its USR position to drive the in circuit emulator with the crystal oscillator 2 built into the target board If there is no oscillator on the target board set this switch to the ICE position to use the oscillator built into the probe 3 SW3 Power supply control Set this switch to its USR position to use the power supply from the target board If there is no oscillator on the target board set this switch to the ICE position to use the 5 V power supply from the in circuit emulator attention To use A D converter with power supply below 5 V set this switch to its USR position Reference voltage is 5 V 4 Function control DIP switches Each model has different setting of DIPSW as described below LCDSEL ON For models which use LCD function OFF For models which use LED function WDSEL1 WDSEL2 Switches for watchdog timer frequency Pin s setting Wa
88. open drain E Nch open drain Nch open drain SCOOMD3 SCOSBOM SCOMD3 SCOSBTM ie Output mode Output mode Input mode PODIR PODIRO PODIR PODIR2 Bl Added Not added Added Not added Added Not added ull up POPLU POPLUO POPLU POPLU2 WPins Setup 3 channels at reception Table 10 3 6 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO pin SBTO pin at reception Table 10 3 6 Setup for Synchronous Serial Interface Pin 3 channels at reception Data output pin Data input pin Clock VO pin Setup item SBTO pin SBOO pin 580 pin Internal clock External clock master communication slave communication Pin 00 P01 P02 5810 SBOO independent 580 SBOO pin 2 SCOMD3 SCOIOM Port Serial data input Serial clock Port Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Style Nch open drain Nch open drain SCOMD3 SCOSBTM Input mode Output mode Input mode PODIR PODIR1 PODIR PODIR2 Bd Added Not added Added Not added Added Not added ull up POPLU POPLU1 POPLU POPLU2 Operation Chapter 10 Serial Interface 0 WPins Setup 3 channels at transmission reception Table 10 3 7 shows the setup for synchronous serial interface pin with 3 lines SBOO pin SBIO pin SBTO pin at transmission reception 8 channels at transmission reception Table 10 3 7 Setup
89. reset is initiated by the hardware Reset pin outputs low level mUsage of Watchdog Timer When the watchdog timer is used constant clear in program is necessary to prevent an overflow of the watchdog timer As a result of the software failure the software cannot execute in the intended se quence thus the watchdog timer overflows and error is detected After error is detected the watchdog timer interrupt WDIRQ is generated as non maskable interrupt NMI Programming of the watchdog timer is generally done in the last step of its programming iHow to Clear Watchdog Timer The upper 2 bits of the watchdog timer can be cleared by setting the WDEN flag of the watchdog timer control register WDCTR to 0 The upper 2 bits of the watchdog timer are cleared when the WDEN flag of the watchdog timer control register WDCTR is set to 0 Therefore depending on the clear timing the watchdog timer may be reset at 1 4 x watchdog timer frequency If the WDEN flag is to be repeatedly cleared and set at regular intervals those operations should be performed within 1 4 of the watchdog timer frequency 4 Operation Chapter 8 Watchdog Timer mWatchdog Timer Period The watchdog timer period is decided by the system clock fs and ROM option amp Chapter1 1 6 1 Rom option If the watchdog timer is not cleared till the set period of watchdog timer that is regarded as an error and the watchdog interrupt
90. stable In IDLE mode the CPU operates on the low frequency clock For transition from SLOW to NORMAL oscillation stabilization waiting time is required same Y as that after reset Software must count that time a We recommend selecting the oscillation stabilization time after consulting with oscillator manufacturers Sample program for transition from SLOW to NORMAL mode is given below Program 2 MOV 01 DO Set IDLE mode MOV 00 CPUM Program 3 MOV x 0B DO A loop to keep approx 6 7 ms with low frequency clock 32 kHz LOOP ADD 1 D0 operation when changed to high frequency clock 20 MHz BNE LOOP SUB MOV DO CPUM Set NORMAL mode II 20 Standby Functions Chapter 2 CPU Basics Refer the following cautions to initiate the program on the transition to SLOW mode in case where the execution time at NORMAL mode is too short After the transition to NORMAL mode from SLOW mode if the mode is returned to SLOW again during 2 to 4 cycles of the low speed oscillation clock the short pulse can be generated in the system of the clock causing errors SLOW IDLE NORMAL SLOW CPU mode i control register CPUM time 61 0 us to 122 0 us Xl 32 768 kHz If the mode will be switched to SLOW again the execution time of NORMAL mode should be not in this duration The following 1 or 2 should be executed on the program by the software
91. the TM4IE flag of the TM4ICR register to 1 to enable the interrupt Set the flag of the register to 1 to start timer 4 counts up from x 0000 When TM4BC reaches the set value of the TM4OC register the timer 4 interrupt request flag is set to 1 at the next count clock and the TM4BC becomes x 0000 and counts up again VI 11 Operation Chapter 6 16 Bit Timer When the TM4EN flag of the TM4MD register is changed at same time to other bit binary counter may count up by the switching operation 4 If the value of the and TM4OCL register are rewritten when the timer 4 is stopped the timer 4 binary counter becomes x 0000 But even if the TM4EN flag of the operating timer is cleared to 0 it doesn t stop until the count edge of the next clock Therefore during max 1 count clock after the TM4EN is cleared the binary counter cannot be initialized VI 12 Operation Chapter 6 16 Bit Timer 6 4 16 Bit Event Count 6 4 1 Operation Event count operation has 2 types TM4IO input and synchronous TMAIO input can be selected as the count clock W16 Bit Event Count Operation Timer 4 Event count means that the binary counter TM4BC counts the input signal from external to the 4 pin If the value of the binary counter reaches the setting value of the compare register 4 inter rupts can be generated at the next count clo
92. up resister ON OFF control P7PLUD1 P7PLUDO 0 0 47 P7PLUD IV 21 Port 7 pull up pull down resister ON OFF control 7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLUO 0 0 0 0 0 0 0 0 X 3F48 P8PLU IV 25 Port 8 pull up resister ON OFF control PAPLUD7 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO 0 0 0 0 0 0 0 0 X 3FAA PAPLUD IV 28 Port A pull up pull down resister ON OFF control 21 PARDWN P7RDWN _ A 0 0 0 IIl 33 X 3FAB FLOAT1 P21 input PorApul up Port 7 pull up IV 22 29 pull down pull down mode selection selection selection SCOCEO SCOCE1 SCODIR SCOSTE SCOLNG2 SCOLNG1 SCOLNGO 0 0 0 0 0 X 3F50 SCOMDO Reception data input edge First bit to Serial Synchronous serial transfer bit count ata transfer Transmission data output edge be transferred start condition E SCOCKM SCOCK1 SCOCKO SCOBRKF SCOERE SCOTRI 0 0 0 0 0 X 3F51 SCOMD1 X 7 1 8 dividing of Clock source Brake status Error Transmission Reception interrupt transfer clock receive monitor monitor request flag SCOBRKE SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE B 0 0 0 x x x 52 SCOMD2 X 8 Brake status P Frame mode specification Added bit specification transmit control enable SCOIMO SCOSBOM SCOSBTM SCOSBOS SCOSBIS SCOSBTS 0 0 0 0 0 0 X 3F53 SCOMD3 X 9 SBIO SBOO 5800 pin SBTO pin 5800 pin SBIO input SBTO pin pin connection conf
93. up resistor control direction control Port output data Port input data IV 12 Block Diagram Figure 4 3 4 Block Diagram P11 DX 11 Rese Ui P1PLUO gt Write CK Read Rese DO P1 DIRO 2 2 Write Read V t 3 x P10 Rese P1OUTO M gt Z DQ U a Write Read X 7 7 RESE R P10TCO DQ Write Read P1INO d input J J Read Figure 4 3 3 Block Diagram P10 ae Rese A PAPLU1 Write Ick Read 8858 P1 DIRT y 23 2 Write Read Rese R P1OUT1 5 DQ 1 Write Read 777 Schmitt input n N Read Pull up resistor control direction control Port output data Output mode control Port input data Timer input Timer output Chapter 4 Ports RS Rese R P1PLU2 4 DQ m J Write 575 Haad ra P1 DIR2 4 1 Write XZ Read Reset s 1 a 1 OUT2 4 e Write Ick U P12 14TCO Write Z Read P1IN2 4 bn input RS Read
94. whole function of 8 bit timer is as follows Count clock uis TMnEN EE Row ci ou 4 flag AE Compare DONI i i y i M register i H 02 03 j O4 operation stop E 0 Binary 00 01 vy 01 counter B match signal Interrupt request flag Figure 5 3 1 Count Timing of Timer Operation Timers 2 and 3 A If the value is written to the compare register during the TMnEN flag is 0 the binary counter is cleared to 00 at the writing cycle B If the TMnEN flag is 1 the binary counter is started to count The counter starts to count up at the falling edge of the count clock But the binary counter doesn t count up at the first falling of the count edge C If the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock then the binary counter is cleared to x 00 and the counting is restarted D Even if the compare register is rewritten during the TMnEN flag is 1 the binary counter is not changed E If the TMnEN flag is 0 the binary counter is stopped after 1 count up When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the compare
95. x 3F8A NFOEN 1 Set the interrupt level IRQOICR x 3FE2 bp7 6 IRQOLV1 0 10 Enable the interrupt IRQOICR x 3FE2 bp1 IRQOIE 1 1 Set the 0 flag of the external interrupt 0 control register IRQOICR to 1 to specify the interrupt active edge to the rising edge 2 Select the sampling clock to fs 2 by the NFOCKS1 0 flag of the noise filter control register NFCTR 3 Set the NFOEN flag of the NFCTR register to 1 to add the noise filter operation 4 Setthe interrupt level by the IRQOLV 1 0 flag of the IRQOICR register If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt flag setup 5 Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt Note The above 2 and 3 are set at the same time The input signal from the P20 pin generates the external interrupt 0 at the rising edge of the signal after passing through the noise filter 1 The setup of the noise filter should be done before the interrupt is enabled The external interrupt pins are recommended to be pull up in advance III 37 External Interrupts Chapter 3 Interrupts 3 3 6 AC Zero Cross Detector This LSI has AC zero cross detector circuit The P21 ACZ pin is the input pin of AC zero cross detector circuit AC zero cross detector circuit output the high level when the input level is at the middle and outputs the
96. 0 3 2 1 if data to are stored to to bp5 of SCORXB Also data are read as the same way At LSB first data are read from the upper bits of SCORXB When there are 6 bits to be transferred as shown on figure 10 3 2 2 if data A to F are stored to bpO to bp5 of SCORXB But their order is changed in the SWAP circuit and reading is started from the upper bits Operation 15 Chapter 10 Serial Interface 0 SCORXB F E D C B Figure 10 3 2 1 Receive Bit Count and Transfer First Bit starting with MSB bit SCORXB A B C D E F Data is read F E D C B Figure 10 3 2 2 Receive Bit Count and Transfer First Bit starting with LSB bit Edge Output Edge Setup The SCOCE 1 to 0 flag of the SCOMDO register set an output edge of the transmission data an input edge of the reception data As the SCOCE1 flag 0 the transmission data is output at the falling edge and as 1 output at the rising edge As SCOCEO O the reception data is stored at the inversion edge to the output edge of transmission data and as 1 stored at the same edge Table 10 3 2 Input Edge and Output Edge of Transmission Reception Data SCOCEO SCOCE1 Reception data input edge Transmission data output edge 0 0 1 M 0 1 y 1 1 0 y 1 1 1 1 X 16 Operation Chapter 10 Serial Interface 0
97. 0 8 mm pitch code name QFP044 P 1010 48 pin TQFP 7 mm square 0 5 mm pitch code name TQFP048 P 0707B 5 42 pin SDIP package type 25 pins 44 pin QFP package type 26 pins 6 For the package types except 48 pin TQFP package type 11 pins 7 For the package types except 48 pin TQFP package type 3 pins 8 For the package types except 48 pin TQFP package type 2 pins 1 3 Pin Description 1 3 1 Pin Configuration TXD SBOO P00 RXD SBIO P01 SBTO P02 lt BUZZER P06 RMOUT P10 P11 lt TM2IO P12 1 14 lt IRQO P20 ACZ IRQ1 P21 0 031 A OON NRST P27 21 4185 uid zp LGVOLOLNW VSS OSC1 OSC2 VDD PA7 AN7 PA6 AN6 PA5 AN5 PA4 AN4 PA3 AN3 PA2 AN2 PA1 AN1 PAO ANO P80 LEDO P81 LED1 P82 LED2 P83 LED3 P84 LED4 P85 LED5 P86 LED6 P87 LED7 MMOD Figure 1 3 1 Pin Configuration 42 SDIP Top view Chapter 1 Overview Pin Description 1 7 Chapter 1 Overview P64 P65 P66 P67 P70 NRST P27 MMOD LED7 P87 LED6 P86 LED5 P85 LED4 P84 co A LED3 P83 lt gt 1 Figure 1 3 2 Pin Description P62 LED2 P82 lt gt 2 LED1 P81 P61 P60 P22 IRQ2 P21 IRQ1 ACZ P20 IRQO P14 TM4IO 101 457 44 pinQFP AN1 PA1 gt 6 gt 8 LEDO P80 lt gt 4 1 4 gt 9 P12 TM21IO P11 5 10 6 6 11
98. 1 X base selection clock x 1 2 TMS5CLRS Timer 5 binary counter clear selection 0 Enable the initialization of 5 as TM5OC is written 1 Disable the initialization of 5 as TM5OC is written TM5IRQ is disabled when TM5CLRS 0 is enabled when TM5CLRS 1 Figure 7 2 3 Timer 5 Mode Register TM5MD 03 88 R W Control Registers Chapter 7 Time Base Timer 8 Bit Free running Timer 7 3 8 Bit Free running Timer 7 3 1 Operation W8 Bit Free running Timer Timer 5 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register TM5OC in advance If the binary counter TM5BC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from 00 Table 7 3 1 shows clock source that can be selected Table 7 3 1 Clock Source at Timer Operation Timer 5 Clock source One count time fosc 50 ns fs 4 400 ns fx 30 5 us fosc X 1 2 19 409 6 us fx X 1 2 13 250 ms fosc 20 2 fx 32 768 kHz calculated as 15 fosc 2 10 MHz a Timer 5 cannot stop its timer counting except at standby mode STOP mode a 8 Bit Free running Timer VIL 7 Chapter 7 Time Base Timer 8 Bit Free running Timer B8 bit Free running Timer as a 1 minute timer a 1 second ti
99. 1 2 Interrupt Vector Address and Interrupt Group Vector Vector Interrupt group Control Register Number Address Interrupt source address 0 x04000 2 5 1 x04004 Non maskable interrupt NMI NMICR 1 2 X04008 External interrupt 0 IRQO IRQOICR 2 3 X0400C External interrupt 1 IRQ1 IRQ1ICR 4 x 04010 Reserved 5 4 5 x04014 Reserved 5 6 X04018 Timer 2 interrupt TM2IRQ TM2ICR 7 x 0401C Time base period TBIRQ TBICR 7 8 X04020 Serial interface 0 interrupt SCOIRQ SCOICR X 03FE8 9 x04024 Reserved gt 9 10 04028 converter interrupt ADIRQ ADICR 11 0402 External interrupt 2 IRQ2 IRQ2ICR 12 X04030 External interrupt 3 IRQ3 IRQ3ICR 13 x 04034 Reserved 14 x 04038 Timer 3 interrupt TMSIRQ TMSICR 15 X0403C Timer 4 interrupt TM4IRQ TM4ICR 16 x 04040 Timer 5 interrupt 17 x 04044 Reserved xO3FF1 18 X04048 Reserved 5 5 2 19 0404 Reserved 2 20 04050 Reserved 5 4 External interrupt 3 cannot be used for the other types except 48 pin TQFP package type For unused interrupts and reserved interrupts set the address the RTI instruction is de
100. 1 YUS 4 ec p 881095 g 1 2 8 eyng 9 0015 1 5 5 3788005 INOIOOS 11140985 0 6005 00154095 4 1195098 HAd0OoS IMS 5045005 OWd00S 5185005 8 5185005 0 AdNOOS 8 M 0 5 5 0 0195 LOd axu oias Serial Interface 0 Block Diagram Figure 10 1 1 X 3 Overview Chapter 10 Serial Interface 0 10 2 Control Registers 10 2 1 Registers Table 10 2 1 shows registers to control serial interface 0 Table 10 2 1 Serial Interface 0 Control Registers Register Address R W Function Page SCOMDO x 03F50 RAW Serial interface 0 mode register 0 X 6 SCOMD 1 XO3F51 R W Serial interface 0 mode register 1 X 7 SCOMD2 03 52 RWW Serial interface 0 mode register 2 X 8 SCOMD3 x O3F53 RW Serial interface 0 mode register X 9 interface 0 SCOCTR X O3F54 R W Serial interface 0 control register X 10 SCOTRB x 03F55 R W Serial interface 0 transmission reception shift register 5 5 X 03F56 R Serial interface 0 reception data buffer X 5 R W Readable Writable R Readable only X 4 Control Registers Chapter 10 Serial Interface 0 10 2 2
101. 11 Interrupt 1 generated z Accepted because xxxLV1 0 IM xxxLV1 0 10 1 0 10 77 Interrupt acceptance cycle 9 Interrupt service routine 1 2 Interrupt 2 generated z Accepted because 1 0 1 xxxLV1 0 00 Interrupt acceptance cycle 11 0 00 Interrupt service routine 2 2 Restart interrupt processing program 1 imt o 10 RTI imot Parentheses indicate hardware processing Figure 3 1 7 Processing Sequence with Multiple Interrupts Enabled Overview III 13 Chapter 3 Interrupts 3 1 4 Interrupt Flag Setup Interrupt request flag IR setup by the software The interrupt request flag is operated by the hardware That is set to 1 when any interrupt factor is generated and cleared to 0 when the interrupt is accepted If you want to operate it by the software the IRWE flag of MEMCTR should be set to 1 Bi interrupt flag setup procedure A setup procedure of the interrupt request flag set by the hardware and the software shows as follows Setup Procedure Description Disable all maskable interrupts PSW bp6 MIE 0 Select the interrupt factor Enable the interrupt request flag to be rewritten MEMCTR x 3F01 bp2 IRWE 1 Rewrite the interrupt request flag xxxICR bpO xxxIR Disable the interrupt request flag to be rewritten MEMCTR x
102. 11 BNS 011 BVC 411 011 ASR Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 Am SUBW DWn Am MOVW DWn Am ADDW DWn DWm ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am MOV d16 SP Dm MOV d8 SP Dm MOV d16 An D MOV Dn d16 SP MOV Dn d8 SP MOV Dn d16 Am MOVW DWn DWm NOPL n m CMPW DWn DWm ADDUW Dn Am EXT Dn DWm AND OR 8 PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm MOV abs16 Dm MOVW abs16 Am MOVW abs16 DWm CBEQ 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d12 CBEQ 8 abs8 d7 d11 CBNE 8 abs8 d7 d11 MOVW d16 SP Am MOVW d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 Am DIVU MOVW An d16 SP XII 28 MOVW DWn d16 SP Instruction Map MOVW An d8 SP MOVW DWn d8 SP MOVW An Am ADDW 16 SP MULU Extension code 6 0011 2nd nibble 3rd nibble 0 1 2 Chapter 12 Appendices TBZ abs8 bp d1 1 TBNZ abs8 bp d7 TBNZ abs8 bp d1 1 CMP Dn Dm ADD Dn Dm TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 TBNZ io8 bp d1 1 OR Dn Dm AND Dn Dm BSET io8 bp BCLR io8 bp JMP abs18 label JSR abs18 label Dn Dm 8 Dm ADDC Dn Dm BSET ab
103. 1CKSO 22 1 NFICKS1 12 5 M 9 U 7 5 2 x fs 2 I Y P2o Rao gt Noise filter M Polarity Inversion Y fs 2 fs 2 9 U 5 2 X fs 2 dore cun Y AC zero cross 2 detection circuit Noise filter input control M U Polarity Inversion FLOAT1 P7RDWN PARDWN Figure 3 3 1 AC zero cross detection circuit 21 Schmi t input Chapter 3 Interrupts RQOICR IRQOIR IRQOIE REDGO IRQOLVO IRQOLV1 7 IRQO interrupt request 16 bit timer RQ1ICR IRQ1IR IRQ1IE REDG1 IRQ1LV1 IRQ1 interrupt request 16 bit timer External Interrupt 0 Interface and External Interrupt 1 Interface Block Diagram External Interrupts 29 Chapter 3 Interrupts Interrupt 2 Interface and External Interrupt Interface Block Diagram IRQ2ICR 9 IRQ2IE 7 P22 IRQ2 EE ae M U IRQ2 interrupt request Polarity X 16 bit timer Inversion IRQSICR 9 IRQSIE P23 IRQ3 M U IRQS interrupt request Polarity X Inversion 1 External interrupt 3 interface can be used only for 48 pin TQFP package type Figure 3 3 2 External Interrupt 2 Interface External Interrupt 3 Interface 30 External Interrupts Chapter Interrupts 3 3 3 Control
104. 2 and 3 The TMnIO pin outputs 2 x cycle compared to the value in the compare register If the binary counter reaches the compare register and the binary counter is cleared to x 00 TMnIO output is inverted 18 8 Bit Timer Pulse Output Chapter 5 8 Timers 5 5 2 Setup Example Timer Pulse Output Setup Example Timers 2 and 3 TMSIO pin outputs 50 kHz pulse by using timer 3 For this select fosc as clock source and set a 1 2 cycle 100 kHz for the timer 3 compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter x 3F83 bp4 TMSEN 20 2 Setthe special function pin to the output mode 1 x 3F39 bp3 1 P1DIR x 3F31 bp3 P1DIR3 1 3 Select the normal timer operation TMSMD x 3F83 bp3 TM3PWM 0 4 Select the count clock source 3 83 bp2 0 2 0 000 5 Set the timer pulse output cycle x 3F73 7 6 Start the timer operation TM3MD x 3F83 bp4 1 1 Set the TM3EN flag of the timer 3 mode register TM3MD to 0 to stop timer 3 counting Set the P13TCO flag of the port 1 output mode register P1OMD to 1 to set P13 the special function pin Set the P1DIRG flag of the port 1 direction control register P1DIR to 1 to set output mode If needed add pull up resist
105. 2 bits X 3F93 ANBUF1 ANBUF 17 ANBUF16 ANBUF15 ANBUF 14 ANBUF13 ANBUF 12 ANBUF 11 ANBUF 10 x x X x x x x x upper A D buffer 1 8 bits not use X 3FE1 PIR WDIR Reserved 0 0 0 Program Watchdog Interrupt request interrupt request Set always 2 IRQOICR IRQOLV1 IRQOLVO REDGO IRQOIE IRQOIR 0 0 0 0 0 IRQO interrupt level IRQO interrupt active edge IRQO interrupt enable IRQO interrupt request IRQ1ICR IRQ1LV1 IRQ1LVO REDG1 IRQ1IE IRQ1IR 0 0 0 0 0 IRQ1 interrupt level interrupt active edge IRQ1 interrupt enable interrupt request X 3FE6 TM2ICR TM2LV1 TM2LVO 21 TM2IR 0 0 0 0 TMe interrupt level TM2 interrupt enable TM2 interrupt request 7 TBLV1 TBLVO TBIE TBR 0 0 0 0 TB interrupt level TB interrupt enable TB interrupt request X 3FE8 SCOICR SCOLV1 SCOLVO SCOIE SCOIR 0 0 0 0 SCO interrupt level SCO interrupt enable SCO interrupt request ADLV1 ADLVO ADIE ADIR 0 0 0 0 AD interrupt level Note x Initial value is unstable No data XII 20 Special Function Registers List AD interrupt enable AD i
106. 27 and contains an internal pull up resistor Typ 35 kQ Setting this pin low initializes the internal state of the device The reset will be released by setting this pin to high input level The hardware waits for the system clock to stabilize then processes the reset interrupt Also if 0 is written to P27 and the reset is initiated by software a low level voltage will be output The output has an n channel open drain configuration If a capacitor is to be inserted between NRST and VDD it is recommended that a discharge diode be placed between NRST and POO 20 VO 5 TXD VO port 0 4 Bit CMOS tri state port P01 21 580 RXD Each bit can be set individually as either an input or P02 22 SBTO output by the PODIR register A pull up resistor for each P06 23 BUZZER bit can be selected individually by the POPLU register At reset the input mode is selected and pull up resistors are disabled high impedance output P10 24 VO RMOUT VO port 1 5 Bit CMOS tri state VO port P11 25 Each bit can be set individually as either an input or P12 26 output by the P1DIR register pull up resistor for each P13 27 bit be selected individually by the P1PLU register P14 28 At reset the input mode is selected and pull up resistors are disabled high impedance output Pin Description I 11 Chapter 1 Overview Table 1 3 3 Pin Function Summary 2 5
107. 3 4 Programmable Active Edge Interrupt iProgrammable Active Edge Interrupts External interrupts 0 to 3 Through register settings external interrupts 0 to 3 can generate interrupt at the selected edge either rising or falling edge iProgrammable Active Edge Interrupt Setup Example External interrupts 0 to 3 External interrupt 1 IRQ1 is generated at the rising edge of the input signal from P21 The table below provides a setup example for IRQ1 Setup Procedure Description 1 Specify the interrupt active edge 1 Set the REDG1 flag of the external interrupt 1 IRQ1ICR control register IRQ1ICR to 1 to specify the bp5 REDG1 21 rising edge as the active edge for interrupts 2 Setthe interrupt level 2 Setthe interrupt priority level in the IRQ1LV1 0 IRQ1ICR flag of the IRQ1ICR register bp7 6 IRQ1LV1 0 10 If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt flag setup 3 Enable the interrupt 3 Setthe IRQ1IE flag of the IRQ1ICR register to IRQ1ICR 1 to enable the interrupt bp1 IRQ1IE 1 External interrupt 1 is generated at the rising edge of the input signal from P21 1 The Interrupt request be set to 1 at switching the interrupt edge so specify the interrupt active edge before the interrupt permission generated by setting the interrupt enable flag Therefore clear the interrupt reques
108. 300 16 00 osc 207 4808 103 9615 51 19230 5 4 5 103 1202 51 2404 5 16 103 300 16 76 osc 217 4805 108 9610 54 19045 5 4 E 108 1201 54 2381 s 16 108 300 20 00 050 2 5 129 9615 64 19231 5 4 129 1202 64 2404 32 4735 z ia 5 5 16 129 300 Operation X 39 Chapter 10 Serial Interface 0 Pin Setup 1 2 channels at transmission Table 10 3 19 shows the pins setup at UART serial interface transmission The pins setup is common to the TXD pin RXD pin regardless of those pins are independent connected The RXD pin can be used as general port P01 Table 10 3 19 UART Serial Interface Pin Setup 1 2 channels at transmission Data output pin Data input pin Setup item TXD pin RXD pin Pin P00 P01 TXD RXD pins are connected or independent TXD RXD pins SCOMD3 SCOIOM Serial data output 1 input Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS Push pull Style Nch open drain _ SCOMD3 SCOSBOM Output mode VO PODIR PODIRO Added Not added Pul up POPLU POPLUO BPin Setup 2 channels at reception Table 10 3 20 shows the pins setup at UART serial interface reception with 2 channels TXD pin RXD pin
109. 3F01 2 IRWE 0 Set the interrupt level xxxICR bp7 6 xxxLV1 0 PSW bp5 4 IM1 0 Enable the interrupt xxxICR xxxlE 1 Enable all maskable interrupts PSW bp6 MIE 1 Clear the MIE flag of PSW to disable all maskable interrupts This is necessary especially when the interrupt control register is changed Select the interrupt factor such as interrupt edge selection or timer interrupt cycle change Set the IRWE flag of MEMCTR to enable the interrupt request flag to be rewritten This is necessary only when the interrupt request flag is changed by the software Rewrite the interrupt request flag xxxIR of the interrupt control register xxxICR Clear the IRWE flag so that interrupt request flag can not be rewritten by the software Set the interrupt level by the xxxLV1 0 flag of the interrupt control register xxxICR Set the IM1 0 flag of PSW when the interrupt acceptance level of CPU should be changed Set the xxxIE flag of the interrupt control register xxxICR to enable the interrupt Set the MIE flag of PSW to enable maskable interrupts 14 Overview Control Registers Chapter 3 Interrupts 3 2 1 Registers List Table 3 2 1 Interrupt Control Registers Register Address R W Functions Page NMICR R W Non maskable interrupt control register Ill 16 IRQOICR XO3FE2 R W External interr
110. 3F52 bp5 SCOBRKE 0 8 Select the pin type SCOMDS x 3F53 bp4 SCOSBOM 1 POPLU x 3F40 POPLUO 0 9 Select the reception mode SCOMD3 x 3F53 bp5 SCOIOM 1 10 Control the pin direction PODIR x 3F30 bpO PODIRO 1 11 Select the interrupt level SCOICR x 03FE8 bp7 6 SCOLV1 0 10 12 Enable the interrupt SCOICR x 3FE8 SCOIE 1 13 Set the baud rate timer 14 Set the serial interface communication SCOMDS x 3F53 bp2 SCOSBOS 1 15 Start the serial interface communication SCOTRB x 3F55 6 Set the SCOFM1 0 flag of the SCOMD2 register to 11 to select 8 bits data 2 stop bits at the frame mode 7 Set the SCOBRKE flag of the SCOMD2 register to 0 to select serial data transmission 8 Set the SCOSBOM flag of the SCOMD3 register to 1 to select N ch open drain for the TXD pin Set the POPLUO flag of the POPLU register to 0 not to add pull up resistor 9 Setthe SCOIOM flag of the SCOMDS register to 1 to set the SBOO to transmission reception port Set the PODIRO flag of the PODIR register to 1 to set POO to output mode 10 11 Select the interrupt level by the SCOLV1 0 flag of the serial interface O interrupt control register SCOICR 12 Set the SCOIE flag of the SCOICR register to 1 to enable the interrupt request If any interrupt request flag had already been set clear it Chapte
111. 3F74 x 0740 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the P14TCO flag of the port 1 output mode register P1OMD to 1 to set the P14 pinasa special function pin Set the P1DIRA flag of the port 1 direction control register P1DIR to 1 to set output mode If needed pull up resister should be added 6 Chapter4 Ports Select fosc as a clock source by the TM4CK2 0 flag of the register Set the TMAPWM flag of the timer 4 mode register TM4MD to 1 to select the PWM operation Set the H period of the PWM output in the lower 8 bits of the timer 4 compare register TMAOCL To be 1 4 duty of the full count 256 of the lower 8 bits in the timer 4 binary counter TMABCL the setting value should be 256 4 64 40 Also set the location of the added pulse in the upper 8 bits of the compare register If it is set to 07 the added pulse is appended 7 times in 256 repetitions VI 22 Added Pulse Type 16 Bit Output Chapter 6 16 Bit Timer Setup Procedure Description 6 Start the timer operation 6 Set the TM4EN flag of the TM4MD register to TM4MD x 3F84 1 to start timer 4 bp6 4 1 TM4BCL counts up from x 00 The PWM source waveform outputs until TM4BCL reaches the set value of the TM4OCL register then after the match it outputs L After that TMABCL continues to count up o
112. 48 BTST abs16 bp mem8 abs16 amp bpdata PSW 016 7 5 0011 1101 abs 16 gt Branch instructions if ZF 1 PC 3 d4 label H gt PC 1001 if ZF 0 3 if ZF 1 PC 4 d7 label H PC 5 1000 if ZF 0 4 BEQ label if ZF 1 PC 5 d11 label H PC 5 1001 if ZF 0 5 BNE labe if ZF 0 PC 3 d4 label H PC 1001 if ZF 1 PC 3 PC BNE labe if ZF 0 PC 4 d7 label H PC 1000 if ZF 1 4 BNE labe 0 PC 5 d11 label H PC 1001 if ZF 1 5 BGE label if VF NF 0 PC 44d7 label H PC 1000 if VF NF 21 PC 4 PC BGE label if VF NF 0 PC 5 d11 label H PC 1001 if VF NF 21 PC45 PC if CF 0 PC 4 d7 label H PC 1000 if CF 1 4 BCC label 0 5 011 1 1001 if CF 1 5 BCS labe if CF 1 PC 4 d7 label H PC 1000 if CF 0 4 BCS labe if CF 1 PC 5 d11 label H PG 1001 if CF 0 5 BLT labe if VF NF 1 PC 4 d7 label H gt PC 1000 if VF NF 20 PC 4 PC BEQ label BCC label BLT labe if VF NF 1 PC 5 d11 label H PC 8 1001 0 5 BLE label if VE NF ZF 1 PC 44 d7 label H gt PC 1000 if VFANF ZF 0 PC 4 PC BLE label if VF8NF ZF 1 PC 5 d1 1 label H gt PC 1001 if VFANF ZF 0 PC 5
113. 48 pin of EPROM version to 28 pin having the same configu ration as a normal EPROM a general purpose ROM writer can be used to perform read and write operations The EPROM Version is described on the following items Cautions on use of the internal EPROM Erasing Data in Windowed Package PX AP101C42 SDC FBC Differences between mask ROM version and EPROM version Writing to the Microcomputer with internal EPROM Cautions on handling a ROM writer Programming Adapter Connection Option bit XII 2 EPROM Version Chapter 12 Appendices 12 1 2 Cautions on Use EPROM Version differs from the MN101C457 Mask ROM Version in some of its electrical characteris tics The user should be aware of the following cautions 1 To prevent data from being erased by ultraviolet light after a program is written affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU 101 42 PX AP101C42 SDC 2 Because of device characteristics of the MN101CP42xxx a writing test cannot be performed on all bits Therefore the reliability of data writing may not be 100 ensured 3 When a program 15 being written be sure that power supply 6 V is connected before applying the power supply 12 5 V Disconnect the Ver supply before disconnecting the supply 4 Vr should never exceed 13 5 V including overshoot 5 If a device is removed while a Ver of 12 5 V is applied
114. 5 7 5 0010 1110 0014 lt d16 ww gt 43 MOVW d16 SP Am mem16 d16 SP gt Am 1 1 1 17 5 0010 1110 000a 416 Zeb om 43 MOVW abs8 DWm mem16 abs8 gt DWm 1 1 1 1413 1100 0114 lt abs 8 44 MOVW abs8 Am mem16 abs8 Am 4 3 1100 010a lt abs 8 gt 44 MOVW absi6 DWm mem16 abs16 gt DWm 1 1 1 17 5 0010 1100 0114 abs 16 gt 45 MOVW abs16 Am mem16 abs16 gt Am 1 1 1 17 5 0010 1100 010a abs 16 gt 45 MOVW DWn Am DWn mem16 Am 2 3 1111 00aD 46 MOVW An Am 16 3 4 0010 1111 10aA 4 46 MOVW DWn d4 SP DWn mem16 d4 SP 313 1111 0110 lt d4 gt 2 47 MOVW An d4 SP Anmem16 d44SP 313 1111 010A lt d4 gt 2 47 MOVW DWn d8 SP DWn mem16 d8 SP 5 4 0010 1111 0110 d8 3 48 MOVW An d8 SP An mem16 d8 SP 5 4 0010 1111 010A lt 8 gt 3 48 MOVW DWn d16 SP DWn mem16 d16 SP 7 5 0010 1111 0010 416 AER 49 MOVW An d16 SP An mem16 d16 SP 1 1 1 17 5 0010 1111 000A 416 Se 49 MOVW DWn abs8 DWn mem 6 abs8 1 1 1 1413 1101 0110 lt abs 8 50 MOVW An abs8 16 058 1 1 1 1413 1101 010A lt abs 8 50 MOVW DWhn abs16 DWn mem16 abs16 1 1 1 17 15 0010 1101 0110 abs 16 gt 51 MOVW An abs16 An mem16 abs16 1 1 1 17 5 0010 1101 010A abs 16 gt
115. 54 bp6 SCOCMD 1 Select the first bit to be transferred SCOMDO x 3F50 bp4 SCODIR Select the start condition SCOMDO x 3F50 bp3 SCOSTE Select the clock source SCOMD1 x 3F51 bp4 3 SCOCK1 0 Select the parity bit SCOMD2 x 3F52 SCONPE bp2 1 SCOPM1 0 Specify the frame mode SCOMD2 x 3F52 bp4 3 SCOFM1 0 Select the reception mode SCOMDS 3 53 bp5 SCOIOM 0 0 11 0 00 11 1 1 Set the SCOCMD flag of the SCOCTR register to 1 to select the UART communication Select MSB as first transfer bit by the SCODIR flag of the SCOMDO register Set the SCOSTE flag of the SCOMDO register to disable start condition X 33 Selection of Start Condition Set the SCOCK1 0 flag of the SCOMD1 register to select timer 3 output as a clock source Set the SCONPE flag of the SCOMD2 register to select parity is enabled and set the SCOPM1 0 flag to select 0 checked Set the SCOFM1 0 flag of the SCOMD2 register to 11 to select 8 bits data 2 stop bits at the frame mode Set the SCOIOM flag of the SCOMDS register to 1 to set the SBOO to transmission reception port 45 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 8 Control the pin direction PODIR x 3F30 PODIRO 0 9 Add pull up resistor the TXD POPLU 40 POPLUO 1 10 Selec
116. 580 1 UART received data input pin In the serial interface in UART mode this pis is configured as the received data input pin Pull up resistors can be selected by the POPLU register Set this pin to the input mode by the PODIR register and to the serial mode by the serial 0 mode register 3 SCOMD3 This can be used as normal pin when the serial interface is not used TM2lIO 26 27 vO P12 P13 Timer VO pins Event counter clock input pins timer output and PWM signal output pins for 8 bit timers 2 to 3 To use these pins as event clock inputs configure these pins to input mode through the P1DIR register When the pins are used as input pins pull up resistors can be specified by the P1PLU register For timer output PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register When not used for timer I O these can be used as normal VO pins RMOUT 24 vO P10 Remote control transmission signal output pin Output pin for remote control transmission signal with a carrier signal For remote control carrier output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register This can be used as a normal pin when remote control is not used BUZZER 23 Output Buzzer output Piezoelectric buzzer driver p
117. 6 3 1 Operation Timer operation can constantly generate interrupt 16 Bit Timer Operation Timer 4 The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register TM4OC in advance When the binary counter TM4BC reaches the set value of the compare register the timer 4 interrupt request flag is set to 1 at the next count clock the binary counter TM4BC is cleared to x 0000 and the counting up is restarted from x 0000 unit data even if it is a 16 bit MOVW instruction As a result the CPU will read the data a When the CPU reads the 16 bit binary counter TM4BC the read data is treated as 8 bits incorrectly if a carry from the lower 8 bits to the upper 8 bits occurs during counting VI 8 Operation Chapter 6 16 Bit Timer Table 6 3 1 shows the clock source that can be selected Table 6 3 1 Clock Source at Timer Operation Timer 4 Clock source 1 count time fosc 50 ns 15 4 400 5 16 1 6 us as fosc 20 fs fosc 2 10 MHz iCount Timing of Timer Operation Timer 4 The binary counter counts up with the selected clock source as the count clock The basic operation of the whole function of 16 bit timer is as follows Count clock TM4EN flag Compare register Binary counter Compare match signal Interrupt request flag Figure 6 3 1 Count Timing of Timer Operation Timer 4 A Set the value t
118. 8 SP 2 bp6 2 PC 5 bp17 16 mem8 SP 2 bp1 0 5 412 0001 000H lt d12 53 129 JSR label 5 3 5 PC 6 bp7 0 gt mem8 SP PC 6 bp15 8 mem8 SP 1 PC 6 H gt mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 6 bp17 16 mem8 SP 2 bp1 0 PC 6 d16 label H gt PC 0001 001H lt d16 4 130 JSR label SP 3 SP PC 7 bp7 0 gt mem8 SP PC 7 bp15 8 mem8 SP 1 PC 7 H gt mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 7 bp17 16 mem8 SP 2 bp1 0 518 0011 1001 1aaH abs 18b 15 0 5 130 JSRV tbl4 5 3 68 3 7 0 8 PC 3 bp15 8 mem8 SP 1 PC 3 H gt mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 3 bp17 16 smem8 SP 2 bp1 0 mem8 x004080 tbl4 2 PC bp7 0 8 0040804104 2 1 9 0 15 8 mem6 x004080 tbl4 2 2 bp7 PC H mem8 x004080 tbl4 2 2 bp1 0 PC bpt7 16 1111 1110 lt 4 gt 131 2 NOTE Pages for MN101C Series Instruction Manual XII 26 Instruction Set 0000 0000 1 2 3 4 55 132 47 sign extension 411 sign extension 412 sign extension 416 sign extension aa abs18 17 16 MN101C SERIES INSTRUCTION SET Mnemonic Operation mem8 SP PC bp7 0 mem8 SP 1 PC bp15 8 mem8 SP 2 bp7 gt PC H mem8 SP 2 bp1 0 gt PC bp17 16 SP 3 SP 0000 0001 Machine Code
119. 91 kHz 256 us External Interrupts III 35 Chapter 3 Interrupts iNoise Remove Function Operation External interrupts 0 to 1 After sampling the input signal to the external interrupt pins IRQO IRQ1 by the set sampling time if the same level comes continuously three times that level is sent to the inside of LSI If the same level does not come continuously three times the previous level is sent It means that only the signal with the width of more than Sampling time X 3 sampling clocks can pass through the noise filter and other much narrower signals are removed because those are regarded as noise IRQn pin input signal Waveform after filtering noise Figure 3 3 5 Noise Remove Function Operation Noise filter can not be used at STOP mode and HALT mode 36 External Interrupts Chapter 3 Interrupts Noise Filter Setup Example External interrupt 0 and 1 Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 IRQO at the rising edge The sampling clock is set to fs 2 and the operation state is fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description Specify the interrupt active edge IRQOICR x 3FE2 bp5 REDGO 1 Select the sampling clock NFCTR x 3F8A bp2 1 NFOCKS1 0 00 Set the noise filter operation NFCTR
120. AC zero crossings When these are not used for interrupts these can be used as normal input pins IRQS pin is not allocated to 42 SDIP and 44 QFP package types ACZ 30 Input P21 IRQ1 AC zero cross An input pin for an AC zero cross detection circuit The detection input pin AC zero cross detection circuit outputs a high level when the input is at an intermediate level Otherwise It outputs a low level voltage ACZ input signal is connected to the P21 input circuit and to the IQR1 interrupt circuit When the AC zero cross detection circuit is not used this pin can be used as a normal P21 input The selection is set by the P211M flag of the FLOAT1 register MMOD 44 Input Test mode switch This pin sets the test mode and needs to be set always input pin to L Pin Description I 15 Chapter 1 Overview 1 4 1 4 1 TXD SBOO POO 5810 5 2 9 0 RMOUT 10 4 9 P11 TM2IO P12 gt TMSIO P13 gt P14 4 9 L uog Block Diagram Block Diagram Q Q e e 55 NRST MMOD IRQO P20 ACZ IRQ1 P21 IRQ2 P22 P23 NRST P27 AN7 7 AN6 PA6 AN5 PAS AN3 AN2 PA2
121. Atreset 00000000 Pull up or Pull down PAPLUD resistor selection 0 No pull up or pull down resistor 1 Pull up or Pull down resistor Port A pull up pull down resistor control register PAPLUD x 03F4A R W Figure 4 8 1 Port A Registers 1 2 IV 28 PortA Chapter 4 Ports 7 6 5 4 3 2 1 0 FLOAT1 211 PARDWN P7RDWN Atreset 000 p7RDwN Port7 pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor PARDWN Port A pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor P211M P21 input mode selection 0 Schmitt trigger input 1 ACZ input Pin control register 1 FLOAT1 X 03F4B R W Figure 4 8 2 Port A Registers 2 2 PotA 1 29 Chapter 4 Ports 4 8 3 Block Diagram Pull up Pull down resistor control Pull up Pull down resistor selection Port input data Input mode control Analog input IV 30 PortA ihe S PAPLUDO 7 DQ 1 LU Write Read Reset R FLOAT1 bp1 gt 9 M gt Write Read 5 d 7 7 Read PAINO 7 Reset R PAIMDO 7 DQ 7 Write Read Figure 4 8 3 Block Diagram PAO to 7
122. CO 1 P1DIR x 3F31 bp4 P4DIRA 21 3 Select the normal timer operation TM4MD x 3F84 bp5 0 4 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 000 5 Set the timer pulse output cycle X 3F75 X 3F74 x 00C7 6 Start the timer operation TM4MD x 3F84 bp6 4 1 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the P14TCO flag of the port 1 output mode register P1OMD to 1 to set P14 pin as the special function pin Set the P1DIR4 flag of the port 1 direction control register P1DIR to 1 to set output mode If needed pull up resister should be added 114 Chapter 4 I O Ports Set the TM4PWM flag of the timer 4 mode register TM4MD to 0 to select the normal timer operation Select fosc as a clock source by the TM4CK1 0 flag of the TM4MD register Set the 1 2 frequency of the timer pulse output cycle to the timer 4 compare register TM40C To be 100 kHz by a divided 20 MHz set as follows 200 1 199 xC7 Set the TM4EN flag of the TM4MD register to 1 to start timer 4 VI 18 16 Bit Timer Pulse Output Chapter 6 16 Bit Timer counts up from x 0000 If TM4BC reaches the set value of the register and TM4BC is cleared to x 0000 the signal of the TM4IO output is inverted and TM4BC counts up from x 0000 again Set the compare register value
123. COCTR to 0 Activation Factor for Communication Table 10 3 1 shows activation factors for communication At master the transfer clock is generated by setting data to the transmission reception shift register SCOTRB or by receiving a start condition At slave input an external clock or input an external clock after a start condition is input Table 10 3 1 Synchronous Serial Interface Activation Factor Sequence Operation mode Activation factor communication Enable start condition Writing data to serial buffer at master Disable start condition Writing data to serial buffer y Transmission Enable start condition Clock reception at slave Disable start condition Clock reception Enable start condition Start condition reception y at master Disable start condition Writing data to serial buffer Reception Enable start condition Start condition reception at slave Disable start condition Clock reception Start condition is output by writing the transmission data to the transmission reception shift register SCOTRB when the SCOSBOS flag of the serial interface 0 mode register SCOMD3 is set to 1 Then the transmission is started by the slave clock When synchronous serial interface is used for master clock reception it is necessary to write dummy data to the transmission reception shift register SCOTRB for starting master clock Automatic sequence reception wit
124. COMDO register to 00 or 01 Data is received at the opposite edge of the transmission clock so that the reception clock should be the opposite edge of the transmission clock from the other side SBTO pin Data is received at the rising edge of clock SBIO pin Data is output at the falling edge of clock Figure 10 3 9 Transmission Reception Timing Reception rising edge Transmission falling edge SCOCEO 0 SCOCE1 0 SBTO pin Data is received at the falling edge of clock SBIO pin Data is output at the rising edge of clock 5800 pin Figure 10 3 10 Transmission Reception Timing Reception falling edge Transmission rising edge SCOCEO 0 SCOCE1 1 X 22 Operation WPins Setup 3 channels transmission Table 10 3 5 shows the setup for synchronous serial interface pin with channels SBOO 5810 pin SBTO pin at transmission Chapter 10 Serial Interface 0 Table 10 3 5 Setup for Synchronous Serial Interface Pin 3 channels at transmission Data output pin Data input pin Clock VO pin SBTO pin Setup item 5800 pin 580 pin Internal clock External clock master communication slave communication Pin P01 P02 5810 SBOO independent 580 SBOO pin SCOMD3 SCOIOM Serial data output 1 input Serial clock VO Port Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Push pull Style Nch
125. Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Overview CPU Basics Interrupts I O Ports 8 Bit Timers 16 Bit Timer Time Base Timer 8 Bit Free running Timer Watchdog Timer Buzzer Serial Interface 0 A D Converter Appendices NO gt ii Contents Chapter 1 Overview 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 e casted RR E ERENER 1 2 1 1 1 ipee PREIS oda ee eR sun euer vu cu doe Pea gn I 2 1 1 2 Product Summary oboe eoe dee e D nee I 2 Hardware Functions ctt I 3 Pin B scriptioD eer ertet ret I 7 1 3 1 Pin Configuration i epp rero rt Rd e RU I 7 1 3 2 Pin Specification e De HE PER RURSUS I 10 1 3 3 Pin Function 3 iet entree erede aet entier I 11 Block Diagram eh RORIS eR am Matic DR eat sea I 16 1 4 1 Block Diagram eth ttem etu I 16 Electrical CharacteristiCs Rr e I 17 1 5 1 Absolute Maximum Ratings 2 eene I 17 1 5 2 Operating Conditions eder me e eee eet I 18 1 5 3 DC Characteristics ot eae ete Ure ee een I 21 1 5 4 A D Converter Characteristics essere I 26 Optom 1 27 1 6 1
126. DC eter ttt reme XII 4 12 1 4 Differences between Mask ROM version and EPROM version XII 5 12 1 5 Writing to Microcomputer with Internal EPROM XII 6 12 1 6 Cautions on Operation of ROM Writer seen XII 8 12 1 7 Programming Adapter Connection XII 9 12 1 8 Bit ie eee nere eee reus XII 12 Probe Switches eere tee ert e ne erret XII 13 12 2 1 Probe Switches 0 1 42 42 XII 13 12 2 2 Probe Switches 0 1 42 44 XII 14 12 2 3 Probe Switches 0 1 42 48 XII 15 Special Function Registers List esee XII 16 Instr ctiorni Set eem tet tete Re re te Hes XII 22 Instruction ee esit e Ar eR RE I XII 28 contents Chapter 1 Overview Chapter 1 Overview 1 1 Overview 1 1 1 Overview The MN101C series of 8 bit single chip microcontrollers incorporate multiple types of peripheral func tions This chip series is well suited for VCR MD TV CD LD printer telephone home automation pager air conditioner PPC remote control fax machine musical instrument and other applications This LSI brings to embedded microcomputer applications flexible optimized hardware configurations and a simple efficient inst
127. DIR flag of the SCOMDO register can set the first transfer bit MSB first or LSB first can be selected Transmission Data Set the transmission data to the transmission reception shift register SCOTRB Operation X 13 Chapter 10 Serial Interface 0 When switching from transmission to reception set the SCOSBOS flag of the SCOMDO reg ister to 0 and then set the SCOSBIS flag to 1 Do not change both of these flags at the same time When switching from reception to transmission set the SCOSBIS flag of the SCOMDO regis ter to 0 and then set the SCOSBOS flag to 1 Do not change both of these flags at the same time X 14 Operation Chapter 10 Serial Interface 0 iTranfer Bit Count and First Transfer Bit On transmission when the transfer bit is 1 bit to 7 bits the data storing method to the transmission reception shift register SCOTRB is different depending on the first transfer bit selection At MSB first use the upper bits of SCOTRB When there are 6 bits to be transferred as shown on figure 10 3 1 1 if data A to are stored to bp2 to bp7 of SCOTRB the transmission is started from to A At LSB first use the lower bits on the program When there are 6 bits to be transferred as shown on figure 10 3 1 2 if data A to are stored to to bp5 on the program the transmission is started from A to F because their order is changed in the SWAP circuit 7 6 5 4 3 2 1 0
128. Description Select the count clock source TMS3MD 3 83 bp2 0 TM3CK2 0 000 Set the base cycle of remote control carrier x 3F73 x 6C Start the timer operation TM3MD x 3F83 bp4 1 Enable the remote control carrier output RMCTR x 3F89 bp3 1 Select fosc to clock source by the 2 0 flag of the TM3MD register Set the base cycle of remote control carrier by writing x 6C to the timer compare register The set value should be 8 2 73 4 kHz 1 108 x 6C 8 MHz is divided to be 73 4 kHz 2 times 36 7 kHz Set the TMSEN flag of the TM3MD register to 1 to stop the timer 3 counting Set the RMOEN flag of the RMCTR register to 1 to enable the remote control carrier output TMSBC counts up from 00 Timer outputs the base cycle pulse set in TM3OC Then the 1 3 duty remote control carrier pulse signal is output If the RMOEN flag of the RMCTR register is set to O the remote control carrier pulse signal output is stopped Remote Control Carrier Output 33 Chapter 6 16 Bit Timer ra Chapter 6 16 Bit Timer 6 1 Overview This LSI contains a general purpose 16 bit timer Timer 4 6 1 1 Functions Table 6 1 1 shows the functions of timer 4 can use Table 6 1 1 16 Bit Timer Functions Timer 4 16 bit timer Interrupt source TM4IRQ Timer operation Event count
129. E SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE atreset 000 X XX SCONPE Parity enable 0 Enable parity bit 1 Disable parity bit Added bit specification SCOPM 1 SCOPMO Xm Transmission Reception 0 0 Add 0 Check for 0 Add i Check for 1 Add odd Gad parity Check f 1 Add even parity SCOFM1 SCOFMO Frame mode specification 7 data bits 1 stop bit 7 data bits 2 stop bits 8 data bits 1 stop bit 8 data bits 2 stop bits o 2 o SCOBRKE _ Break status transmit control 0 Data transmit Break transmit Figure 10 2 5 Serial Interface 0 Mode Register 2 SCOMD x 03F52 R W X 8 Control Registers Serial Interface 0 Mode Register 3 SCOMD3 SCOMD3 7 6 5 4 3 2 1 0 Sra bosson SCOSBTM 5005809 SCOSBIS 22 Chapter 10 Serial Interface 0 at reset 000000 SCOSBTS SBTO pin function selection 0 Port Serial interface clock pin SBIO input control SCOSBIS reception enable flag 0 1 input 1 Serial data input SCOSBOS SBOO pin function selection transmission enable flag 0 Port 1 Serial data communication SCOSBTM SBTO pin configuration 0 Push pull output 1 N ch open drain output SCOSBOM 5800 pin confi
130. EPROM Version Chapter 12 Appendices EROM Writer Setup The device types should be set up as listed below Table 12 1 2 Setup for Device Type Equip name Vendor Device type Remarks Hitachi 27 256 Mitsubishi 27C256 Hitachi 27 256 Pecker30 Aval Data 1890A Minato Electronics Mitsubishi 27C256 Hitachi 27 256 Do not run ID check 2900 Data VO Mitsubishi 27C256 T Hitachi 27 256 Do not run ID check and pin connection ipLa ata i i P Mitsubishi 27C256 inspection The above table is based on the standard samples Please contact the nearest semiconductor design center Refer to the sales office table attached at the end of the manual when you use the other equipment EPROM Version XII 7 Chapter 12 Appendices 12 1 6 Cautions on Operation of ROM Writer Cautions on Handling the ROM writer 1 The Ver programming voltage for the EPROM versions is 12 5 V Programming with a 21 V ROM writer can lead to damage The ROM writer specifications must match those for standard 256 K bit EPROM Ver 12 5 V 1 ms 2 Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter Faulty connections can damage the chip 3 After clearing all memory of the ROM writer load the program to the ROM writer 4 After confirming the device type write the loaded program in 3 to this LSI address from x 4000 to the final ad
131. Ehsan Malaysia Tel 03 7516606 Fax 03 7516666 Penang Office Suite 20 17 MWE PLAZA No 8 Lebuh Farquhar 10200 Penang Malaysia Tel 04 2625550 Fax 04 2619989 Johore Sales Office 39 01 Jaran Sri Perkasa 2 1 Taman Tampoi Utama Tampoi 81200 Johor Bahru Johor Malaysia Tel 07 241 3822 Fax 07 241 3996 CHINA SALES OFFICE Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ 74 107 International Business amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 Tel 755 359 8500 Fax 755 359 8516 Panasonic Industrial Shanghai Co Ltd PICS 1F Block A Development Mansion 51 Ri Jing Street Wai Gao Qiao Free Trade Zone Shanghai 200137 Tel 21 5866 6114 Fax 21 5866 8000 THAILAND SALES OFFICE Panasonic Industrial Thailand Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st Fl Rachadaphisek Rd Huaykwang Bangkok 10320 Tel 02 6933407 Fax 02 6933423 KOREA SALES OFFICE Panasonic Industrial Korea Co Ltd PIKL Group Bldg 11th 191 Hangangro 2ga Youngsans ku Seoul 140 702 Korea Tel 82 2 795 9600 Fax 82 2 795 1542 PHILIPPINES SALES OFFICE National Panasonic Sales Philippines NPP 102 Laguna Boulevard Laguna Technopark Sta Rosa Laguna 4026 Philippines Tel 02 520 3150 Fax 02 843 2778 130301 Printed in JAPAN
132. Figure 5 4 1 Count Timing of TMnIO Input Timers 2 and 3 When the TMnIO input is selected for count clock source and the value of the timer n binary counter is read during operation incorrect value at count up may be read To prevent this use the event count by synchronous TMnIO input as the following page 14 8 Bit Event Count Chapter 5 8 Timers iCount Timing of Synchronous TMnIO Input Timers 2 and 3 If the synchronous TMnIO input is selected the synchronizing circuit output signal is input to the timer n count clock The synchronizing circuit output signal is changed at the falling edge of the system clock after the TMnIO input signal is changed TMnIO input System clock fs Synchronizing circuit output Count clock TMnEN flag Compare register Binary counter Compare match signal Interrupt request flag Figure 5 4 2 Count Timing of Synchronous TMnlIO Input Timers 2 and 3 When the synchronous TMnIO input is selected as the count clock source the timer n counter counts up in synchronization with system clock therefore the correct value is always read But if the synchronous TMnIO is selected as the count clock source CPU mode cannot return from STOP HALT mode 8 Bit Event Count 15 Chapter 5 8 Timers 5 4 2 Setup Example mEvent Count Setup Example Timers 2 and 3 If the falling edge of the TM2IO input pin signal is detecte
133. H Era V 18 5 6 5 8 5 9 5 5 2 Setup Example ec Ep e ges V 19 8 Bit PWM Output keeno toreen Rer E V 21 5 6 1 Operation e Sah ih E V 21 5 6 2 Setup Example ue hats eek pen ile E SEREN E V 23 Serial Interface Transfer Clock Output sese 25 5 7 1 Operaatio iiie eerte er DUC UAR UNE ID e ON URS REPE ERU V 25 5 7 2 Setup Example een hess erat edd V 26 Cascade Connection eiiieaen ete eae E apa Trece pet e V 27 5 8 1 Operation et e ha Actes KER ente deed 27 5 8 2 Setup Example scac eaer ete ten erede V 29 Remote Control Carrier Output 2 2 2 2 31 5 9 1 Operation 4c oem ee ep eene ee ene t emos V 31 5 9 2 Setup Example o oot bes eee TEE TE E oE rE Eoee V 32 Chapter 6 X 16 Bit Timer 6 1 6 4 6 5 6 6 6 7 bedroom Rp eee pit e eher VI 2 6 1 1 Functions eto eee ur RASA ie e OR Ate VI 2 6 1 2 Block Dia Stam 2 eire teret ete VI 3 Control Registers odere egere det pter thee rere ova eee Den eel VI 4 6 2 1 DIGNI I reor AE EE E VI 4 6 2 2 Programmable Timer Registers eese VI 5 6 2 3 Timer Mode Registers VI 7 16 Bit Timer hec speed rete eco i rei e e e eine VI 8 6 3 1 Operation dte pP OP OE RE VI 8 6 3 2 Set
134. ICR The timer 5 interrupt control register TM5ICR controls interrupt level of timer 5 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter enable flag MIE of PSW is 0 When the interrupt level flag is set to level TM5LV1 TM5LVO z 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 5 5 2 Lvi LVO 5 At reset 0 0 0 0 Interrupt request flag 0 No interrupt request 1 Interrupt request generated TMBIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt TMS TMS interrupt level fi LVO SUB RU The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 9 Timer 5 Interrupt Control Register TM5ICR x O3FFO R W 24 Control Registers Chapter 3 Interrupts Time Base Interrupt Control Register TBICR The time base interrupt control register TBICR controls interrupt level of time base interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 TBLV1 TBLVO 1 the interrupt of its vector is dis
135. LUD Set the ANO PAO to the analog input pin by setting the ANCHS2 0 flag of the A D converter control register 0 ANCTRO to 000 Set the fs 4 to the A D converter clock by setting the ANCK1 flag of the A D converter control register 0 ANCTRO to 01 Set the TAD x 6 to the sample and hold time by setting the ANSH1 ANSHO flag of the A D converter control register 0 ANCTRO to 01 Set the interrupt level by the ADLV1 0 flag of the A D conversion complete interrupt control register ADICR If any interrupt request flag had already been set clear it 4 Chapter 3 3 1 4 Interrupt Flag Setting Enable the interrupt by setting the ADIE flag of the ADICR register to 1 Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 to send a current to the ladder resistance for the A D conversion XI 12 Operation Chapter 11 A D Converter Setup Procedure Description 8 Start the A D conversion 8 Set the ANST flag of the A D converter control 1 x 3F91 register 1 ANCTR1 to 1 to start the A D bp7 ANST 1 conversion 9 Complete the A D conversion 9 When the A D conversion has finished the A D ANBUFO x 3F92 conversion complete interrupt is generated ANBUF1 x 3F93 and the ANST flag of the A D converter control register 1 ANCTR1 is cleared to 0 The result of the conversion is stored to the A D converter buffer ANBUFO 1
136. M4BCL TM4BCH the compare register 4 1 4 and input capture register TM4ICL TM4ICH The timer 4 mode register TM4MD controls timer 4 6 2 1 Registers Table 6 2 1 shows the registers that control timer 4 Table 6 2 1 16 Bit Timer Control Registers Register Address RW Function Page TM4BCL 03 64 Timer 4 binary counter lower 8 bits VI 5 TM4BCH x 03F65 Timer 4 binary counter upper 8 bits VI 5 TM40CL 74 R W Timer 4 compare register lower 8 bits VI 5 75 R W Timer 4 compare register upper 8 bits VI 5 Timer 4 TM4ICL 03 66 Timer 4 input capture regsiter lower 8 bits VI 6 TM4ICH x 03F67 Timer 4 input capture register upper 8 bits VI 6 TM4MD 03 84 R W Timer 4 mode register VI 7 TM4ICR xO3FEF R W Timer 4 interrupt register timer 4 compare match Ill 23 9 R W Port 1 output mode register IV 11 P1DIR 1 RW 1 direction control register 10 R W Readable Writable R Readable only VI 4 Control Registers Chapter 6 16 Bit Timer 6 2 2 Programmable Timer Registers Timer 4 has a 16 bit programmable timer register It contains a compare register a binary counter and a capture register Each register has 2 sets of 8 bit register Operate by 16 bit access Compare register is a 16 bit register stores the value that compared to binary counter
137. MD 3 82 register TM2MD to 0 the flag of the bp4 2 0 timer 3 mode register TM3MD to 0 to stop x 3F83 timer 2 and timer 3 counting bp4 0 2 Select the normal operation of lower 2 Set both of the TM2PWM flag of the TM2MD timer 2 register to 0 to select the normal operation of TM2MD x 3F82 timer 2 bp3 3TM2PWM 0 3 Set the cascade connection 3 Connect timer 2 and timer 3 in cascade TMSMD x 3F83 connection by the TM3CK2 0 flag of the bp2 0 2 0 100 TM3MD register 4 Select the count clock source 4 Set the clock source to fs 4 by the TM2CK2 0 TM2MD 3 82 flag of the TM2MD register bp2 0 2 2 0 001 5 Set the interrupt generation cycle 5 Set the timer 2 compare register timer TMnOC x 3F71 x 8F72 x 09C3 compare register 2 to the interrupt generation cycle x 09C3 2500 cycles 1 At that time timer 3 binary counter timer 2 binary counter TM2BC are initialized to x 0000 6 Disable the lower timer interrupt 6 Setthe TM2IE flag of the timer 2 interrupt TM2ICR x 3FE6 control register TM2ICR to 0 to disable the bp1 TM2IE 0 interrupt Cascade Connection 29 Chapter 5 8 Timers Setup Procedure Description 10 Set the level of the upper timer interrupt TMSICR 7 bp7 6 1 0 10 Enable the upper tim
138. Pana Series The One toWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER 101 MN101C457 L SI User s Manual Pub No 21445 010E Panasonic PanaX Series is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 1 2 3 4 5 Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advance fo
139. R2 PSDIR1 P8DIRO Atreset 00000000 P8DIR 0 Input mode 1 Port 8 direction control register P8DIR x 03F38 R W 7 6 5 4 3 2 1 0 P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 PSPLUO At reset 00000000 P8PLU 0 No pull up resistor 1 Pull up resistor Port 8 pull up resistor control register P8PLU x 03F48 R W Figure 4 7 1 Port 8 Registers Port 8 IV 25 Chapter 4 Ports 4 7 3 Block Diagram Pull up resistor control Read direction control Port output data Port input data IV 26 Port8 P80 P87 Rese 2 a P8PLUO 7 D J Write CK NL Rese aa P8DIRO 7 p 2 Write Read mE M S P8OUTO 7 DQ 2 Write CK Read 777 0 7 N Read NJ Figure 4 7 2 Block Diagram P80 to P87 Chapter 4 Ports 4 8 Port A 4 8 1 Description ilGeneral Port Setup Port A is input port To read input data of pin read the value of the port A input register PAIN Each pin can be set individually if pull up pull down resistor is added or not by the port A pull up pull down resistor control register PAPLUD But pull up pull down cannot be mixed Set the control flag of the port A pull up pull down resistor control register PAPLUD to 1 to add pull up or pull down resis tor The pin contr
140. Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on If the input pin voltage is applied before power supply is on a latch up occurs and causes the destruction of micro controller by a large current flow The Relation between Power Supply and Reset Input Voltage After power supply is on reset pin voltage should be low for sufficient time ts before rising in order to be recognized as a reset signal Power voltage Voltage Reset pin low level Chapter 2 2 5 1 Reset Operation Figure 1 8 5 Power Supply and Reset Input Voltage 1 36 Precautions Chapter 1 Overview 1 8 4 Power Supply Circuit iCautions for Setting Circuits with VDD The CMOS logic microcontroller is high speed and high density So the power circuit should be de signed taking into consideration of AC line noise ripple caused by LED driver Figure 1 8 6 shows an example for emitter follower type power supply circuit Example for Emitter Follower Type Power Supply Circuit Set condensors for noise filter near microcontroller power pins Microcontroller Vss LED port For Noise filter Figure 1 8 6 An Example for Emitter Follower Type Power Supply Circuit Precautions 1 37 Chapter 2 CPU Basics Chapter 2 CPU Basics 2 1 Overview The MN101C series has a flexible optimized hardware configuration It is a high speed CPU with a simple and efficient ins
141. T5 P6O0UT4 P6OUT3 P60UT2 P60UT1 P60UTO At reset 00000000 P6OUT Output data 0 Low 55 level 1 High VDD level Port 6 output register P6OUT x 03F16 R W 7 6 5 4 3 2 1 0 P6IN P6IN7 P6IN6 5 PeIN4 P6IN3 P6IN2 PeIN1 P6INO At reset X X XXX XXX P6IN Input data 0 Pin is Low Vss level 1 Pin is High VDD level Port 6 intput register P6IN 03 26 R 7 6 5 4 3 2 1 0 P6DIR P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 PeDIR2 PeDIR1 P6EDIRO At reset 00000000 P6DIR mode selection 0 Input mode 1 Output mode Port 6 direction control register P6DIR x 03F36 R W 7 6 5 4 3 2 1 0 _ P6PLU7 P6PLU6 P6PLU5 P6PLU4 PePLU3 PePLU2 PePLU1 P6PLUO At reset 00000000 IV 18 P6PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 6 pull up resistor control register P6PLU x O3F46 R W Figure 4 5 1 Port 6 Registers 4 5 3 Block Diagram Pull up resistor control direction control Port output data Port input data Chapter 4 Ports Figure 4 5 2 Block Diagram P60 to P67 5959 E P6PLUO 7 Write F Read 1 Rese 5 P6DIRO 7 B i Write F Read ES SZ peo P 60 67 9 pese CN 251 PEOUTO 7 gt 5 Write
142. TR mMemory Control Register 7 6 5 4 3 2 1 0 MEMCTR IOW1 IVBA Reserved Reserved IRWE Reserved Reserved Atreset 11001011 Reserved Set always to 11 IRWE Software write enable flag for interrupt request Software write disable 0 Even if data is written to each interrupt control register the state of the interrupt request flag xxxIR will not change 1 Software write enable Reserved Set always to 1 Reserved Set always to 0 IVBA Base address setting for interrupt vector table 0 Interrupt vector base X 04000 1 Interrupt vector base X 00100 Wait cycles when Bus cycle at IOW1 to 0 accessing special register area 20 MHz oscillation 00 No wait cycles 100 ns 01 1 wait cycles 150 ns 10 2 wait cycles 200 ns 11 3 wait cycles 250 ns Figure 2 3 2 Memory Control Register MEMCTR x 3F01 R W The IOW1 IOWO wait settings affect accesses to the special registers located at the ad dresses x 3F00 x 3FFF After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles Wait setting of IOW is a function which CPU supports for special use for ex ample when special function register or I O is expanded to external For this LSI wait cycle setting is not always necessary Select no wait cycle for high performance system c
143. The TXD pin can be used as general port Table 10 3 20 UART Serial Interface Pin Setup 2 channels at reception Data output pin Data input pin Setup item TXD pin RXD pin Pin Poo P01 TXD RXD pins are independent TXD RXD pin SCOMD3 SCOIOM port serial data input Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS Style input mode VO PODIR PODIR1 added not added Pull up POPLU POPLU1 X 40 Operation Chapter 10 Serial Interface 0 Pin Setup 1 channel at reception Table 10 3 21 shows the pin setup at UART serial interface reception with 1 channel TXD pin The RXD can be used as general port Table 10 3 21 UART Serial Interface Pin Setup 1 channel at reception Data output pin Serial unused pin Setup item TXD pin RXD pin Pin POO P01 TXD RXD pins are connected TXD RXD pin SCOMD3 SCOIOM Port Serial data input Function SCOMD3 SCOSBOS SCOMD3 SCOSBIS Style Input mode VO PODIR PODIRO added not added Pull up POPLU POPLUO Operation X 41 Chapter 10 Serial Interface 0 10 3 4 Setup Example Transmission Setup The setup example at UART transmission with serial interface 0 is shown Table 10 3 22 shows the conditions at transmission Table 10 3 22 UART Interface Transmission Setup Setup item set to TXD RXD pin connected with 1 channe
144. The communication operation does not have any effect on those error flags Table 10 3 15 shows the list of reception error source Table 10 3 15 Reception Error Source of UART Serial Interface Flag Error Error source SCOORE Overrun error Next data is received before reading the receive buffer SCOPEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 when parity bit is 0 odd parity The total of 1 of parity bit and character bit is even The total of 1 of parity bit and character bit even parity is odd SCOFEF Framing error Stop bit is not detected 32 Operation Chapter 10 Serial Interface 0 mJudgement of Break Status Reception Reception at break status can be judged If all received data from start bit to stop bit is 0 the SCOBRKF flag of the SCOMD1 register is set and regard the break status The SCOBRKF flag is set at generation of the reception complete interrupt SCOIRQ Selection of Start Condition The SCOSTE flag of the SCOMDO register is originally to select start condition of the synchronous serial data communication When serial interface 0 is used as half duplex UART serial interface set the SCOSTE flag always to 0 to prevent the following errors Caution At UART communication set the SCOSTE flag of the SCOMD register to 0 Error At UART transmission when the SCOSTE flag is 1 start bit becomes at
145. The noise filter control register NFCTR sets the noise remove function to IRQO and IRQ1 and also selects the sampling cycle of noise remove function 7 6 5 4 2 1 NFCTR NFISCK1 NF1SCK0 NF1 NFOSCK1 NFOSCKO NFOEN atreset 000000 NF noise filter setup Noise filter OFF Noise filter ON NFOCKS1 NFOCKSO IRQO noise filter sampling period 0 fs 2 0 8 1 fs 2 1 0 16 2 1 fg 2 NF1EN IRQ1 noise filter sampling setu Noise filter OFF Noise filter ON NF1CKS1 NF1CKS0 IRQ1 noise sampling period 0 fs 2 0 8 1 fs 2 0 fs 2 1 15 2 Figure 3 3 3 Noise Filter Control Register R W 32 External Interrupts Chapter 3 Interrupts Pin Control Register 1 FLOAT 1 7 6 5 4 3 2 1 0 P211M PARDWN P7RDWN at reset 000 FLOAT1 Port 7 pull up pull down resistor selection P7RDWN 0 Pull up resistor Pull down resistor Port A pull up pull down PARDWN resistor selection 0 Pull up resistor 1 Pull down resistor 211 P21 input mode selection 0 Schmitt trigger input 1 ACZ input Figure 3 3 4 Pin Control Register 1 FLOAT1 4 R W External Interrupts 33 Chapter 3 Interrupts 3
146. Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions Unit MIN TYP MAX External clock input 1 OSC1 OSC2 is unconnected 18 Clock frequency fosc 1 0 200 MHz 19 High level pulse width 20 0 Fig 1 5 3 20 Low level pulse width twit 20 0 ns 21 Rising time twrt 5 0 Fig 1 5 3 22 Falling time twit 5 0 External clock input 2 XI XO is unconnected 1 23 Clock frequency fx 32 768 100 kHz 24 High level pulse width twh2 3 5 3 Fig 1 5 4 us 25 Low level pulse width twi2 3 5 26 Rising time twr2 20 Fig 1 5 4 ns 27 Falling time twi2 20 3 The clock duty rate should be 45 to 55 twh1 E twit e twh2 x twl2 gt gt lt gt lt gt lt gt twi I twr2 twi2 gt 1 x T gt Figure 1 5 3 OSC1 Timing Chart Figure 1 5 4 XI Timing Chart 1 20 Electrical Characteristics Chapter 1 Overview 1 5 3 DC Characteristics Ta 40 to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions MIN MAX Unit Power supply current no load at output pin 1 fosc 20 0 MHz 5 V 1 IDD1 fs fosc 2 15 40 fosc 8 39 MHz Vbb 5 V mA 2 Power supply current fs fosc 2 6 18 fx 32 kHz 3 V 3 2 8 504 100
147. X 1 29 7 fx X 1 279 72 fx X 1 23 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation not provided to the package types of 42 SDIP and 44 QFP fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 be used as a clock source of time base timer at fosc can be used as a clock source of time base timer at fx Time base timer and timer 5 cannot stop timer counting VII 2 Overview Chapter 7 Time Base Timer 8 Bit Free running Timer Block Diagram 7 1 2 5 Time Base Timer Block Diagram eseq 4 Dx eb peoy A OUISWIL lt A 18 8 Buiuuni 69JJ 18 8 G mm OOSIA L A gt X a snouoluou S n n IN x A X n visi A SH TOSWL LHISIALL 0416111 MOSIALL cMOSINL 4 oso OMOSWL gt SIX Block Diagram Timer 5 Time Base Timer Figure 7 1 1 3 Overview Chapter 7
148. X28 X38 x48 x58 8 8 04 0 14 10 24 20 XFA XFC X02 Xx 06 XOA XOE x12 x16 XFA XFE 01 03 05 07 09 0 XFD XFF The setting value in the TM4OCH register 00 01 repeated count 256 times 1 Ld 111111 1 Figure 6 6 2 The Setting Value The Register and The Position of The Added Pulse Position of added pulse Added Pulse Type 16 Bit PWM Output 21 Chapter 6 16 Timer 6 6 2 Setup Example Added Pulse Type 16 Bit PWM Output Setup Example Timer 4 The TM4IO output pin outputs the 1 4 duty 64 192 PWM output waveform at 78 125 kHz with timer 4 In the PWM output repetitions 256 times the added pulse is appended 7 times and the duty becomes 65 191 The high frequency oscillation fosc is set to be operated at 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 TM4EN 0 2 Set the special function pin to output mode P1OMD 9 bp4 P14TCO 1 P1DIR x 3F31 bp4 P4DIRA 21 3 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 000 4 Set the PWM operation TM4MD x 3F84 bp5 1 5 Set the PWM output period and the location of the added pulse TM40C x 3F75 x
149. __ 7 17 0H 11 17 0H PC d12 17 0H PC d16 L 15 0 15 0 SP d8 15 0 SP d16 7 0 11 0 15 0 IOTOP io8 Specifies the address using an address register Specifies the address using an address register with 8 bit displacement Specifies the address using an address register with 16 bit displacement Specifies the address using the program counter with 4 bit displacement and H bit Specifies the address using the program counter with 7 bit displacement and H bit Specifies the address using the program counter with 11 bit displacement and H bit Specifies the address using the program counter with 12 bit displacement and H bit 1 Specifies the address using the program counter with 16 bit displacement and H bit 1 Specifies the address using the stack pointer with 4 bit displacement Specifies the address using the stack pointer with 8 bit displacement Specifies the address using the stack pointer with 16 bit displacement Specifies the address using the operand value appended to the instruction code Optimum operand length can be used to specify the address Specifies an 8 bit offset from the address x 00000 Specifies an 8 bit offset from the top address x 03F00 of the special function register area Reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combined use with absolute addressing reduces code
150. abled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 TB TB TBICR Lvi LVO TBIE TBIR At reset 0 0 00 TBIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated TBIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt 18 Us Interrupt level fl Lvo RR teve Pag The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 10 Time Base Interrupt Control Register TBICR x O3FE7 R W Control Registers III 25 Chapter 3 Interrupts Serial interface 0 Interrupt Control Register SCOICR The serial interface 0 interrupt control register SCOICR controls interrupt level of serial interface 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 SCOLV1 SCOLVO 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 4 3 2 1 0 SCO SCO es SCOICR Lvi LVO SCOIE SCOIR at reset 00 00 SCOIR Interrupt request flag 0 No interrupt request flag 1 Interrupt request generated SCOIE Interru
151. ag of the TM2MD register to 0 to select the normal timer operation Select fs 4 to the clock source by the TM2CK2 0 flag of the TM2MD register Set the value of the interrupt generation cycle to the timer 2 compare register TM2OC The cycle is 250 so that the setting value is set to 249 9 At that time the timer 2 binary counter TM2BO is initialized to 00 Set the interrupt level by the TM2LV1 0 flag of the timer 2 interrupt control register TM2ICR If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt flag setting Set the TM2IE flag of the TM2ICR register to 1 to enable the interrupt V 12 Operation Chapter 5 8 Timers Setup Procedure Description 7 Start the timer operation 7 Set the TM2EN flag of the TM2MD register to TM2MD x 3F82 1 to start the timer 2 bp4 TM2EN 1 The TM2BC starts to count up from x00 When the TM2BC reaches the setting value of the 20 register the timer 2 interrupt request flag is set at the next count clock then the value of the TM2BC becomes 00 and restart to count up When the TMnEN flag of the TMnMD register is changed at the same time to other bit binary counter may count up by the switching operation The initial value of the TM3CK2 0 in the TM3MD register is indefinite When timer 2 timer 3 is used independently set any mode except cascade connection If fx i
152. agram eoe voee 23 S IV 24 4 7 1 eterno RR ER ROSE PERENNE 24 4 7 2 Registers Re hid p nte te hn es IV 25 4 7 3 Block 322 uim teet m S IV 26 POIUA eatin Resp C ERU dosent wen his DP a IV 27 4 8 1 Descrip phon het ade ete br de PR Rari IV 27 4 8 2 Jte n ie p fee re p n RO IV 28 4 8 3 Block Diagram eee tenet eere pedis IV 30 Chapter5 8 Timers contents 5 1 5 2 5 3 5 4 5 5 V 2 5 1 1 Functions a rre pet Hr be V 2 5 1 2 Block Diagram o eene PERPE RE E E V 3 Control oe tato eit a epit ose e pete V 5 5 2 1 temet V 5 5 2 2 Programmable Timer Registers esee V 6 5 2 3 Registers eine ep Pete deett be V 7 8 Bit Timer ERU bibe es 10 5 3 1 ne eee medi e dete d ett tenes V 10 5 3 2 Setup o doeet bees eee e ieget V 12 8 Bit Event Count tee ete diei en aree ARE 14 5 4 1 Operation eene pete req E ER V 14 5 4 2 Setup senso a e a E E Ue Sr E V 16 8 Bit Timer Pulse Output r E o eE EErEE nennen V 18 5 5 1 Op ration eene eene O
153. and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level 3 IRQ2LVO0 IRQ2LV1 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 1 0 IRQ2 IRQ2 IRQ2ICR LVO REDG2 IRQ2IEIRQ2IR Atreset 000 00 IRQ2IR External interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQ2IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDG2 External interrupt active edge flag 0 Falling edge 1 Rising edge IRQ2 IRQ2 LV1 LVO Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 4 External Interrupt 2 Control Register IRQ2ICR R W Control Registers III 19 Chapter 3 Interrupts External Interrupt Control Register The external interrupt 3 control register IRQ3ICR controls interrupt level of external interrupt 3 active edge interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is s
154. as follows The timer pulse output cycle The compare register value The count clock cycle X 2 1 16 Bit Timer Pulse Output VI 19 Chapter 6 16 Bit Timer 6 6 Added Pulse Type 16 Bit PWM Output 6 6 1 Operation In the added pulse method 16 bit PWM output a 1 bit output is appended to the basic component of the 8 bit PWM output and the output is from TM4IO Precise 16 bit control is possible based on the number of PWM repetitions 256 times to which this bit is appended iAdded Pulse Type 16 Bit PWM Output Timer 4 The lower 8 bits of the compare register TM4OCL set the duty H period of the basic PWM waveform and the upper 8 bits of the compare register 4 set the added pulse position The cycle of the basic PWM waveform is the period of the full count overflow in the lower 8 bits of the binary counter TM4BCL Table 6 6 1 shows the PWM output pin Table 6 6 1 PWM Output Pin Timer 4 output pin P14 PWM output pin Added Pulse PWM Output Timer 4 PWM basic components Added pulse gt Added pulse Tn x 00 01 02 03 Tn x 04 repeated count 256 times Figure 6 6 1 Added Pulse Type PWM Output Set the P1DIR register and the P1PLU register when the P14 pin is used as a PWM output pin For PWM operation x FF in TM4OCL produces the same result as x 00 constant low le
155. ata 5 oA m Write 3 777 27 Reset signal input lt Schmitt input Pull up resistor is always added Figure 4 4 4 Block Diagram P27 16 Port2 Chapter 4 Ports 4 5 Port 6 4 5 1 Description ilGeneral port Setup Each bit of the port 6 control I O direction register P6DIR can be set individually to set pins as input or output The control flag of the port 6 direction control register P6DIR should be set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 6 direction control register PeDIR to 0 and read the value of the port 6 input register P6IN To output data to pin set the control flag of the port 6 direction control register P6DIR to 1 and write the value of the port 6 output register Each pin can be set individually if pull up resistor is added or not by the port 6 pull up resistor control register Set the control flag of the port 6 pull up resistor control register P6PLU to 1 to add pull up resistor At reset the P60 to P67 input mode is selected and pull up resistors are disabled high impedance output In processor mode Pot6 IV 17 Chapter 4 Ports 4 5 2 Registers 7 6 5 4 3 2 1 0 P6OUT P60UT7 P6OUT6 P6OU
156. bits Settings for operating mode after reset ROM option EPROM option and watchdog timer frequency Chapter 1 1 6 Option Osailiiti n characteristics The combination of oscillator and each version should be estimated to match when EPROM version is changed to Mask ROM version for mass production Data for ROM option setting is used as Data for EPROM option setting is used option data as option data check should be done on each version when EPROM version is changed to Noise cnaracteristics Mask ROM version for mass production There are no other functional differences EPROM Version XII 5 Chapter 12 Appendices 12 1 5 Writing to Microcomputer with Internal EPROM The device type that set by each ROM writer should be selected the mode for writing 256 K bit EPROM Set the writing voltage to 12 5 V iMounting the device in the programming adapter and the position of the No 1 pin No 1 pin of the device must be matched to this position The shape of the adapter socket depends on the package type Package Product name 42 SDIP OTP42SD 101C117 44 QFP OTP44QF10 101C11 48 TQFP 7 101 42 No 1 Pin O No 1 Pin MN101CP427DP MN101CP427BF MN101CP427HT No 1 Pin No 1 Pin PX AP101C42 SDC PX AP101C42 FBC top view side view Figure 12 1 1 Mounting a Device in Programming Adapter and the Position of No 1 Pin XII 6
157. cade connection the binary counter and the compare register are operated as a 16 bit regis ter At operation set the TMnEN flag of the upper and lower 8 bit timers to 1 to be operated Also the clock source is the one which is selected in the lower 8 bit timer Other setup and count timing is the same to the 8 bit timer at independently operation When timer 2 and timer 3 are used in cascade connection timer 3 interrupt request flag is used Disable the timer 2 interrupt Timer pulse output of timer 2 is L fixed output At the cascade connection if the binary counter should be cleared by rewriting the compare register the TMnEN flags of the lower and upper 8 bits timers mode registers should be set to 0 to stop the counting then rewrite the compare register Also set the TM3OC 2 register by the 16 bit access instruction 28 Cascade Connection Chapter 5 8 Timers 5 8 2 Setup Example iCascade Connection Timer Setup Example Timer 2 Timer 3 Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 2 and timer 3 as a 16 bit timer is shown An interrupt is generated in every 2500 cycles 1 ms by selecting source clock to fs 4 fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter 1 Set the TM2EN flag of the timer 2 mode TM2
158. cation is used with the internal clock master communication Set the SCOSBOM SCOSBTM flag of the SCOMDS register to 11 to select the SBOO SBTO pin to N ch open drain Set the SCOIOM flag to 0 to set input serial data from the 5810 pin Set the POPLU2 0 flag of the POPLU register to 010 to select add pull up resistor only to the SBIO pin Set the PODIR2 0 flag of the port 0 pin direction control register PODIR to 101 to set and 2 to output mode and to set 1 to input mode Set the SCOSBOS SCOSBIS flag of the SCOMD3 register to 1 to set SBOO pin serial data output SBIO pin serial data input Set the interrupt level by the SCOLV1 0 flag of the serial interface 0 interrupt control register SCOICR Set the SCOIE flag of the SCOICR register to 1 to enable interrupts If the interrupt request flag SCOIR of the SCOICR register had already been set clear SCOIR before an interrupt is enabled t Chapter 3 3 1 4 Interrupt Flag Setup 27 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 10 Start serial interface transmission 10 Set the transmission data to the serial interface 0 Transmission data gt SCOTRB x 3F55 transmission reception shift register SCOTRB Reception data input to 5810 pin Then an internal clock is generated to start transmission reception After the transmission has finished serial interface 0 interrupt SCOIRQ is
159. ch interrupt The interrupt level IL is input to the CPU The interrupt request is accepted If IL has higher priority than IM and MIE is 1 After the interrupt is accepted the hardware resets the interrupt request flag xxxIR in the interrupt control register xxxICR to O a gt gt Current interrupt mask level IM PSW Mie imo ZF Level judgement Accepted if IL lt IM 7 xxxICR A Generated interrupt level IL Figure 3 1 4 Determination of Interrupt Acceptance accepted When the setting is xxxLV1 1 0 1 the interrupt is disabled regardless of the value of XXXIE 1 The corresponding interrupt enable xxxlE is not cleared to 0 even if the interrupt is 8 Overview Chapter 3 MIE 0 and interrupts are disabled when MIE in the PSW is reset to 0 by a program Reset is detected MIE 1 and interrupts are enabled when MIE in the PSW is set to 1 by a program The interrupt mask level IM IM1 IMO in the processor status word PSW changes when The program alters it directly A reset initializes it to 0 006 The hardware accepts and thus switches to the interrupt level IL for a maskable interrupt Interrupts Execution of the RTI instruction at the end of an interrupt service routine restores the processor
160. ck Table 6 4 1 Event Count Input Clock Source Timer 4 input P14 Synchronous TM4IO input Event input Count Timing of Input Timer 4 When TMAIO input is selected TM4IO input signal is directly input to the count clock of the timer 4 The binary counter counts up at the falling edge of the TM4IO input signal TM4IO input TM4EN flag Compare register Binary A counter 0000 0001 N 0000 000110002 Match signal BS Interrupt request flag Figure 6 4 1 Count Timing TM4IO Input Timer 4 If the binary counter is read at operation incorrect data at counting up may be read To prevent this use the event count by the synchronous input as the following page 16 Bit Event Count VI 13 Chapter 6 16 Timer Count Timing of Synchronous Input Timer 4 If the synchronous input is selected the synchronizing circuit output signal is input to the count clock The synchronizing circuit output signal is changed at the falling edge of the system clock after the TMAIO input signal is changed The binary counter counts up at the falling edge of the synchronizing circuit output signal or the synchronizing circuit output signal that passed through the divide by circuit TM4IO input System clock fs Synchronizing circuit output count clock TM4EN flag Compare register counter Compare match signal Int
161. consists of the interrupt level field LV1 0 interrupt enable flag IE and interrupt request flag IR Interrupt request flag IR is set to 1 by an interrupt request and cleared to 0 by the interrupt accep tance This flag is managed by hardware but can be rewritten by software Interrupt enable flag IE is the flag that enables interrupts in the group There is no interrupt enable flag in non maskable interrupt NMI Once this interrupt request flag is set it is accepted without any condi tions Interrupt enable flag is set in maskable interrupt Interrupt enable flag IE of each maskable interrupt is valid when the maskable interrupt enable flag MIE flag of PSW is 1 Maskable interrupts have had vector numbers by hardware but their priority can be changed by setting interrupts level field There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority Maskable interrupts are accepted when its level is higher than the interrupt mask level IM1 0 of PSW Non maskable interrupts are always ac cepted regardless of the interrupt mask level 3 external interrupts are provided to the other types except 48 TQFP package type II 2 Overview Interrupts Chapter 3 3 1 1 Functions Table 3 1 1 Interrupt Functions Non maskable Interrupt type Reset interrupt interrupt Maskable int
162. cs 1 6 1 6 1 Option ROM Option Chapter 1 Overview This LSI and the internal EPROM can specify the watchdog timer frequency select the packages and disenable the watchdog timer during operation by bit 2 to 0 of the ROM option address EROM Option Bits 7 6 5 4 3 2 1 0 WDMD PKGSEL2 PKGSEL1 WDSEL2 WDSEL1 Reserved Reserved Set always to 0 WDSEL2 WDSEL Watchdog timer frequency 0 fs 2 0 1 fs 2 1 X 15 22 PKGSEL2 PKGSEL1 Packages 0 X SDIP042 P 0600 0 44 1010 1 48 0707 WDMD Disenable the watchdog timer during operation 0 Disable 1 enable Figure 1 6 1 ROM Option Bits Table 1 6 1 ROM Option Address Model ROM option address 101 457 MN101CP427 Option I 27 Chapter 1 Overview Once started watchdog timer cannnot be stopped if WDMD bp5 is set to 0 In this setup when WDEN flag of watchdog timer control register WDCTR is set to 0 counter operation cannnot be stopped except upper 2 bits of the watchdog timer I 28 Option Chapter 1 Overview 1 6 2 Option Check List Date SE No Model Name MN101C 1 Watchdog timer frequency 16 216 16 219 16 220 Unused 2 SDIP042 P 0750 QFP044 P 1010 TQFP048 P 0707 2 Disenable
163. d 5 times with using timer 2 an interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter 1 Set the TM2EN flag of the timer 2 mode TM2MD 3 82 register TM2MD to 0 to stop timer 2 bp4 2 0 counting 2 Set the special function pin to input 2 Set the P1DIR2 flag of the port 1 direction P1DIR x 3F31 control register P1DIR to 0 to set P12 pin to bp2 P1DIR2 0 input mode If needed add the pull up resistor Chapter 4 I O Port Function 3 Select the normal timer operation 3 Set the TM2PWM flag of the TM2MD TM2MD 3 82 register to 0 to select the normal timer bp3 STM2PWM 0 operation 4 Select the count clock source 4 Select the clock source to 2 input by the TM2MD x 3F82 TM2CK2 0 flag of the TM2MD register bp2 0 2 2 0 011 5 Set the interrupt generation cycle 5 Set the timer 2 compare register 2 the 2 x 3F72 x 04 interrupt generation cycle Counting is 5 so the setting value should be 4 At that time the timer 2 binary counter TM2BC is initialized to 00 6 Set the interrupt level 6 Set the interrupt level by the TM2LV1 0 flag TM2ICR x 3FE6 of the timer 2 interrupt control register bp7 6 TM2LV1 0 10 2 If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt F
164. data include four data registers DO D1 D2 D3 Registers 00 D1 D2 D3 Data registers DO to D3 are 8 bit general purpose registers that support all arithmetic logical and shift operations All registers can be used for data transfers with memory The four data registers may be paired to form the 16 bit data registers DWO D0 D1 and DW1 D2 D3 At reset the value of Dn is undefined Data DO DWO registers D3 D2 Dwi Overview 7 Chapter 2 CPU Basics 2 1 7 Processor Status Word Processor status word PSW is an 8 bit register that stores flags for operation results interrupt mask level and maskable interrupt enable PSW is automatically pushed onto the stack when an interrupt occurs and is automatically popped when return from the interrupt service routine 7 6 5 4 3 2 1 0 PSW Reserved MIE IM1 IMO VF NF CF ZF Atreset 0000 0000 ZF Zero flag 0 Operation result is not 0 1 Operation result is 0 CF Carry flag A carry or a borrow from MSB did not occur A carry or a borrow from MSB occured NF Negative flag 0 MSB of operation results is 0 1 MSB of operation results is 1 VF Overflow flag 0 Overflow did not occur 1 Overflow occured IM1 to O Interrupt mask level Controls maskable interrupt acceptance MIE Maskable interrupt enable
165. ddress 18 bit max Data 8 bit Minimum bus cycle 1 system clock cycle Interrupt Vector interrupt 3 interrupt levels Low power STOP mode dissipation mode HALT mode 2 Overview 2 1 1 Chapter 2 CPU Basics Block Diagram Data registers Processor status word Clock Source oscillation Address registers 01 PSW T2 generator Stack pointer AO D2 SP A1 D3 ABUS BBUS 1 Instruction execution controller nstruction decoder Program counter 1 Incrementer 7 Instruction Interrupt queue controller 1 Program address Operand address Interrupt bus Y Y Bus controller ry 1 E ROM bus RAM bus gt Peripheral expansion bus Internal peripheral Internal ROM Internal RAM functions Clock generator Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals to CPU blocks Program counter Generates addresses for the instructions to be inserted into the instruction queue Normally incremented by sequencer indication but may be set to branch destination address or ALU operation result when branch instructions or interrupts occur Instruction queue Stores up to 2 bytes of pre fetched in
166. dress of the internal ROM 5 There is the same address for ROM option setting even on EPROM version t Chapter 12 1 8 Option Bit The internal ROM space of this LSI is from x 4000 t Chapter 2 2 2 Memory Space This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the a auto device selection command of ROM writer If the auto device selection command is to be executed for this writer the device is likely damaged Therefore never use this command ilWhen the writing is disabled When the writing is disabled check the following points 1 Check that the device is mounted correctly on the socket pin bending connection failure 2 Check that the erase check result is no problem 3 Check that the adapter type is identical to the device name 4 Check that the writing mode is set correctly 5 Check that the data is correctly transferred to the ROM writer 6 Recheck the check points 1 to 5 provided on the above paragraph of Cautions on Handling the ROM writer Please contact the nearest semiconductor design center See the attached sales office table when the writing is disabled even after the above check points are confirmed and the device is replaced with another one XII 8 EPROM Version Chapter 12 Appendices 12 1 7 Programming Adapter Connection Vss Vss Vss Vss Vss 13 12 A11 A10 A9 A8 DO D1 D2 D3
167. e IV 20 7 4 6 2 P7OUT P7IN P7DIR P7PLUD Registers 6 5 4 3 2 1 0 7 1 Chapter 4 Ports Port 7 output register P7OUT x 03F17 R W 1 0 P7IN1 P7INO Port 7 input register P7IN 03 27 R 1 0 P7DIR1 P7DIRO Atreset 00 P7OUT Output data 0 Low Vss level 1 High VDD level At reset XX P7IN Input data 0 Pin is Low Vss level Pin is High level Atreset 00 P7DIR mode selection 0 Input mode 1 Output mode Port 7 direction control register P7DIR 03 37 R W 1 0 P7PLUD1 P7PLUDO At reset P7PLUD Pull up or Pull down resistor selection 0 No pull up or pull down resistor 1 Pull up or Pull down resistor Port 7 pull up pull down resistor control register P7PLUD x 03F 47 R W Figure 4 6 1 Port 7 Registers 1 2 Pot7 IV 21 Chapter 4 Ports 6 5 4 3 2 1 0 FLOAT1 211 PARDWN P7RDWN At reset IV 22 7 P7RDWN Port 7 pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor PARDWN Port A pull up pull down
168. e compared to binary counter Timer 2 Compare Register TM2OC 7 6 5 4 3 2 1 0 TM20C 2067 TM20C6 TM20C5 2004 2063 TM20C2 TM20C1 TM20C0 reset XX XXXXXX Figure 5 2 1 Timer 2 Compare Register 2 x 03F72 R W 3 Compare Register 7 6 5 4 3 2 1 0 TM30C TM30C7 TM30C6 TM3OC5 30 4 TM30C3 TM3OC2 TM3OC1 TM30C0 At reset X XX XX XXX Figure 5 2 2 Timer Compare Register 03 73 R W Binary counter is 8 bit up counter If any data is written to compare register during counting is stopped binary counter is cleared to x 0O 2 Binary Counter TM2BC 7 6 5 4 3 2 1 0 TM2BC 2 7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BCO 00000000 Figure 5 2 3 Timer 2 Binary Counter TM2BC 03 62 Binary Counter TM3BC 7 6 5 4 3 2 1 0 TM3BC 3 7 TM3BC6 TM3BC5 TM3BCA TM3BC3 TM3BC2 TM3BC1 TM3BCO 00000000 Figure 5 2 4 Timer Binary Counter 03 63 V 6 Control Registers 5 2 3 Timer Mode Registers Timer mode register is readable writable register that controls timers 2 and 3 Timer 2 Mode Register TM2MD TM2MD Chapter 5 8 Bit Timers
169. e desired titles Chapter names are located at the top outer corner of each page and section titles are located at the bottom outer corner of each page iRelated Manuals Note that the following related documents are available MNIOIC Series LSI User s Manual lt Describes the device hardware gt MNIOIC Series Instruction Manual lt Describes the instruction set gt MNIOIC Series Cross assembler User s Manual lt Describes the assembler syntax and notation gt MNIOIC Series C Compiler User s Manual Usage Guide lt Describes the installation the commands and options of the C Compiler gt MNIOIC Series C Compiler User s Manual Language Description lt Describes the syntax of the C Compiler gt 101 Series Compiler User s Manual Library Reference lt Describes the standard library of the C Compiler gt MNIOIC Series C Source Code Debugger User s Manual lt Describes the use of C source code debugger gt 101 Series PanaX Series Installation Manual Describes the installation of C compiler cross assembler and C source code debugger and the procedure for bringing up the in circuit emulator iWhere to Send Inquires We welcome your questions comments and suggestions Please contact the semiconductor design center closest to you See the last page of this manual for a list of addresses and telephone numbers About This Manual 3 Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5
170. e interrupts NORMAL SLOW_ mode All interrupts disabled Enable interrupt which will trigger return Set HALT STOP mode Processing inside parentheses is handled by hardware When returning from STOP mode wait for oscillation to stabilize NORMAL SLOW mode Interrupt acceptance cycle Clear MIE flag in the PSW and all interrupt enable flags xxx IE in the maskable interrupt control register Set the xxx IE of the return factor and set MIE flag in the PSW HALT STOP Watchdog timer mode HALT stop counting STOP reset wax Return factor interrupt occured Watchdog timer HALT restarts counting STOP disable Figure 2 4 3 Transition to from STANDBY Mode or higher than the mask level in PSW before transition to HALT or STOP mode it is impos 1 If the interrupt is enabled but interrupt priority level of the interrupt to be used is not equal to sible to return to CPU operation mode by maskable interrupt II 22 Standby Functions Chapter 2 CPU Basics Transition to HALT modes The system transfers from NORMAL mode to HALTO mode and from SLOW mode to HALT1 mode The CPU stops operating but the oscillators remain operational There are two ways to leave a HALT mode a reset or an interrupt A reset produces a normal reset an interrupt an immediate return to the CPU state prior to the transition to the HALT mode The watchdog ti
171. eak output current Other than port 8 loL2 peak e eem E e Average output Other than port 8 1012 avg current 1 Power dissipation Operating ambient temperature Topr 40 to 85 Storage temperature Tstg 55 to 125 Applied to any 100 ms period 2 Connect at least one bypass capacitor of 0 1 or larger between the power supply pin and the ground for latch up prevention 3 The absolute maximum ratings are the limit values beyond which the LSI may be damaged and proper operation is not assured mA C Electrical Characteristics 1 17 Chapter 1 Overview 1 5 2 Operating Conditions NORMAL mode fs fosc 2 SLOW mode fs fx 4 Ta 40 C to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 1 1 foscx20 0 MHz 4 5 5 5 2 foscx8 39 MHz 2 7 5 5 Power supply voltage 20 3 foscx4 19 MHz 2 7 5 5 V 4 1 fx 32 kHz me 5 5 5 Voltage to maintain RAM data Vpps During STOP mode 1 8 5 5 Operation speed 2 6 tct 4 5 V to 5 5 V 0 100 2 7 V to 5 5 V 0 238 execution time 2 0 V 2 7 to5 5V 0 477 9 toa 1 20 V 2 7 V to 55 V 40 125 1 Applied only to 48 pin TQFP package type 2 122 123 1 2 of high speed oscil
172. ed to an input or output P82 2 LED2 by the P8DIR register A pull up resistor for each bit P83 1 LED3 can be selected individually by the P8PLU register P84 48 LED4 When configured as outputs these pins can drive P85 47 LED5 LEDs directly P86 46 LED6 At reset when the input mode is selected pull up P87 45 LED7 resistors are disabled high impedance output PAO 6 Input Input port A 8 Bit input port PA1 7 1 A pull up or pull down resistor for each bit can PA2 8 AN2 selected individually by the PAPLUD resister However PA3 9 AN3 pull up and pull down resistors cannot be mixed PA4 10 AN4 At reset when the PAO to PA7 input mode is selected PA5 11 5 and pull up resistors are disabled PA6 12 AN6 PA7 13 7 I 12 Pin Description Chapter 1 Table 1 3 4 Pin Function Summary 3 5 Name No 80 pin yo Other Function Function Description SBOO 20 Output TXD Serial interface transmission data output pins Transmission data output pins for serial interfaces 0 The output configuration either CMOS push pull or n channel open drain can be selected Pull up resistors can be selected by the POPLU register Select output mode by the PODIR register and serial data output mode by serial mode register SCOMD3 These can be used as normal pins when the serial interface is not used SBIO 21 Input P01 RXD Serial interface received data input
173. ed to the setting value in the compare register TM4OC Output pins are as follows Table 6 5 1 Timer Pulse Output Pin Timer 4 output P14 Pulse output pin i Count Timing of Timer Pulse Output Timer 4 TM4EN flag Compare 010 register H 6 counter Compare match signal Interrupt request flag 40 output Figure 6 5 1 Count Timing of Timer Pulse Output Timer 4 The TM4IO pin outputs 2 x cycle compared to the value in the compare register If the binary counter reaches the compare register and the binary counter is cleared to x 0000 TM4IO output timer output is inverted The inversion of the timer output is changed at the rising edge of the count clock This is happened to form the waveform inside to correct the output cycle In the initial state after releasing reset the timer pulse output is low output 16 Bit Timer Pulse Output VI 17 Chapter 6 16 Bit Timer 6 5 2 Setup Example Timer Pulse Output Setup Example Timer 4 TM4lO pin outputs 50 kHz pulse by using timer 4 For this select fosc as clock source and set a 1 2 cycle 100 kHz for the timer 4 compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 TM4EN 20 2 Setthe special function pin to output mode P1OMD x 3F39 bp4 P14T
174. en cleared to 0 as the A D conversion complete interrupt is generated Table 11 3 5 A D Conversion Starting ANST A D conversion status 1 A D conversion started or in progress 0 A Dconversion completedor stopped Operation XI 11 Chapter 11 A D Converter 11 3 2 Setup Example A D Converter Setup Example by Registers A D conversion is started by setting registers The analog input pins are set to ANO the converter clock is set to fs 4 and the sampling hold time is set to TAD x 6 Then A D conversion complete interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the analog input pin PAIMD PAIMDO 1 PAPLUD PAPLUDO 0 Select the analog input pin ANCTRO x 3F90 bp2 0 ANCHS2 0 000 Select the A D converter clock x 3F90 bp5 4 ANCK1 0 01 Set the sample and hold time ANCTRO x 3F90 bp7 6 ANSH1 0 01 Set the interrupt level ADICR bp7 6 ADLV1 0 00 Enable the interrupt ADICR ADIE 1 Set the A D ladder resistance ANCTRO x3F90 ANLADE 1 1 Set the analog input pin set in 2 to the special function pin by the port A input mode register PAIMD Also set no pull up pull down resistance by the port A pull up pull down resistance control register PAP
175. er Chapter 4 I O Ports Set the TM3PWM flag of the TM3MD register to 0 to select the normal timer operation Select fosc for the clock source by the 2 0 flag of the TM3MD register Set the timer 3 compare register to the 1 2 of the timer pulse output cycle The setting value should be 200 1 199 x C7 because 100 kHz is divided by 20 MHz At that time the timer 3 binary counter TM3BC is initialized to 00 Set the flag of the register to 1 to start timer 3 8 Bit Timer Pulse Output 19 Chapter5 8 Bit Timers counts up from x 00 If TM3BC reaches the setting value of the register then is cleared to x 00 output signal is inverted and TM3BC restarts to count up from x 00 When port 1 is used as pulse output pin the settings of the port 1 direction control register P1DIR and the port 1 pull up register P1PLU need to be set to 1 4 Set the compare register value as follows Th T The timer pulse output cycle FUISTI The count clock cycle 2 The initial value of timer output and the initialization low level Initial value To initialize after reset release Set to low level Program example After timers 2 and 3 are set to Timer 2 Low level cascade connection the setting should be the original mov x04 TM3MD bclr TM3MD 2
176. er 1 ANCTR1 x 03F91 R W XI 6 Control Registers Chapter 11 A D Converter 11 2 3 A D Buffers They are reading only registers that stores result of A D conversion A D Buffer 0 ANBUFO The lower 2 bits from the result of A D conversion are stored to this register 7 6 5 4 3 2 1 0 ANBUFO 2222 ai reset Figure 11 2 3 A D Buffer 0 ANBUFO x 03F92 R A D Buffer 1 ANBUF 1 The upper 8 bits from the result of A D conversion are stored to this register 7 6 5 4 3 2 1 0 ANBUF1 ANBUF17 ANBUF16 ANBUF15 ANBUF10 atreset X X X XXXXX Figure 11 2 4 A D Buffer 1 ANBUF1 x O3F93 R Control Registers XI 7 Chapter 11 A D Converter 11 3 Operation Here is a description of A D converter circuit setup procedure 1 XI 8 Set the analog pins Set the analog input pin set in 2 to special function pin by the port A input mode register PAIMD Setup for the port A input mode register should be done before analog voltage is put to pins Select the analog input pin Select the analog input pin from AN7 to ANO PA7 to PAO by the ANCHS2 to ANCHSO flag of the A D converter control register 0 ANCTRO Select the A D converter clock Select the A D converter clock by the ANCK1 ANCKO flag of the A D converter control register 0 ANCTRO The converter clock TAD should not be under 800 ns w
177. er interrupt TMSICR 7 bp1 1 Start the upper timer operation TM3MD x 3F83 bp4 1 Start the lower timer operation TM2MD x 3F82 bp4 2 1 10 Set the interrupt level by the TM3LV1 0 flag of the timer 3 interrupt control register If any interrupt request flag had already been set clear it Set the flag of the TM3ICR register to 1 to enable the interrupt 14 Chapter 3 3 1 4 Interrupt Setup Set the flag of the TM3MD register to 1 to start timer 3 Set the TM2EN flag of the TM2MD register to 1 to start timer 2 TM3BC TM2BC counts up from x 0000 as a 16 bit timer When TM3BC TM2BC reaches the set value of TM2CC register the timer 3 interrupt request flag is set to 1 at the next count clock and the value of TM2BC becomes x 0000 and counting up 15 restarted Use 16 bit access instruction to the 2 register Hd timer operation If the lower timer starts to operate before the upper timer does the first overflow signal of the lower timer may be invalid To prevent this start the upper timer operation before the lower 30 Cascade Connection Chapter 5 8 Timers 5 9 Remote Control Carrier Output 5 9 1 Operation Carrier pulse for remote control can be generated Operation of Remote Con
178. er pulse output is used as the clock source of the serial interface And its frequency is 1 2 of the set frequency in the timer compare register The count timing is same to the timing of timer operation For the baud rate calculation and the serial interface setup refer to chapter 10 Serial Interface O Serial Interface Transfer Clock Output 25 Chapter 5 8 Timers 5 7 2 Setup Example Serial Interface Transfer Clock Setup Example Timer 3 How to create a transfer clock for half duplex UART serial interface 0 using with timer 3 is shown below The baud rate is selected to be 300 bps the source clock of timer 3 is selected to be fs 4 at fosc 8 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter x 3F83 bp4 TMSEN 0 2 Select the normal timer operation TM3MD x 3F83 bp3 0 3 Select the count clock source TM3MD 3 83 bp2 0 4 2 0 001 4 Set the baud rate x 3F73 5 Start the timer operation TM3MD x 3F83 bp4 1 1 Set the TM3EN flag of the timer 3 mode register TM3MD to 0 to stop timer 3 counting Set the TM3PWM flag of the TM3MD register to 0 to select the normal timer operation Select the clock source to fs 4 by the 2 0 flag of the TM3MD register Set the timer 3 compare register TM3OC to
179. errupt Vector number 0 1 21016 Table address 04000 04004 04008 to 04040 Starting address Address specified by vector address Interrupt level 2 P Set by software External pin input Interrupt factor T pin Internal peripheral p p function Input interrupt request level set Generated operation Direct input to in interrupt level flag xxxLVn of p CPU core redister NMICR maskable interrupt control 9 register xxxICR to CPU core Acceptance only by the interrupt control of the register xxxICR Accept operation Always accepts Always accepts and the interrupt mask level in PSW Machine cycles 12 12 12 until acceptance Values of the interrupt level flag PSW status All flags are The interrupt mask level xxxLVn are set to the interrupt ftat acceptanc cleared flag in PSW is cleared mask level masking all interrupt 4 to 0 to 00 requests with the same or the lower priority Overview Il 3 Chapter 3 Interrupts 3 1 2 II 4 Block Diagram Overview IRQLVL 2 0 IRQNM1 Interrupt CPU core Vector 1 WDOG IRQOICR Figure 3 1 1 Periphe
180. errupt request flag Figure 6 4 2 Count Timing of Synchronous Input Timer 4 When the synchronous input is selected as the count clock source the timer 4 counter counts up in synchronization with system clock therefore the correct value is always read But if the synchronous is selected as the count clock source CPU mode cannot return from STOP HALT mode VI 14 16 Bit Event Count 6 4 2 Setup Example Event Count Setup Example Timer 4 If the falling edge of the TM4IO input pin signal is detected 5 times using timer 4 an interrupt is gener ated Chapter 6 16 Bit Timer An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM4MD x 3F84 bp6 4 0 Select the normal operation x 3F84 bp5 TMAPWM 0 Set the special function pin to input mode P1DIR x 3F31 bp4 P1DIRA 0 Select the count clock source TM4MD x 3F84 bp2 0 TM4CK2 0 011 Set the interrupt generation cycle TM40C x 3F75 x 3F74 x 0004 Set the interrupt level TMAICR x 3FEF bp7 6 TM4LV1 0 10 Set the TM4EN flag of the timer 4 mode register TM4MD to 0 to stop timer 4 counting Set the TM4PWM flag of the TM4MD register to 0 to select the normal timer operation Set the P1DIR4 flag of the port 1 direction control register P1DIR to 0 to set P14 pin
181. et to level IRQ3LV1 IRQ3LV0 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 4 3 2 1 0 IRQ3 LVI LVO REDG3 IRQSIEIRQSIR IRQaicR ROS Atreset 000 00 IRQSIR External interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQSIE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDG3 External interrupt active edge flag 0 Falling edge 1 Rising edge IRQ3 IRQ3 LVI LVO Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 5 External Interrupt Control Register IRQ3ICR x 03FEC R W 1 External interrupt 3 control register IRQ3ICR can be used only 48 TQFPpackage type 20 Control Registers Timer 2 Interrupt Control Register 2 Chapter 3 Interrupts The timer 2 interrupt control register TM2ICR controls interrupt level of timer 2 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 TM2LV1 2 the interrupt of its vector is disab
182. f the SCOMDO register SCOMDO x 3F50 0 to disable start condition bp3 SCOSTE 0 Select the first bit to be transferred Set the SCODIR flag of the SCOMDO register to SCOMDO x 3F50 0 to set MSB as a transfer first bit bp4 SCODIR 0 Select the transfer edge Set SCOCEO 1 flag of the SCOMDO SCOMDO x 3F50 register to 0 1 to set the transmission data bp6 SCOCEO 0 output edge rising and the received data bp5 SCOCE1 1 input edge falling X 26 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 3 Select the clock source SCOMD 1 x 3F51 bp4 3 SCOCK1 0 bp5 SCOCKM 4 Select the transfer clock SCOMD3 x 3F53 bpO SCOBTS b Control the pin type SCOMDS x 3F53 bp4 3 bp5 SCOIOM POPLU x 3F40 bp2 0 POPLU2 0 6 Control the pin direction PODIR x 3F30 bp2 0 PODIR2 0 7 Control the pin function SCOMDS x 3F53 bp2 SCOSBOS bp1 SCOSBIS 8 Set the interrupt level SCOICR x 3FF8 bp7 6 SCOLV1 0 9 Enable the interrupt SCOICR x 3FF8 SCOIE SCOSBOM SCOSBTM 11 0 010 101 10 3 Set the SCOCK1 0 flag of the SCOMD1 register to 00 to select the clock source fs 2 Set the SCOCKM flag to 0 to select not to divide the clock source by 1 8 Set the SCOSBTS flag of the SCOMDS register to 1 to set the SBTO pin to serial interface clock I O pin The communi
183. f the external interrupt 0 input signal the value of TM4BC is stored to the TMAIC register At the above 7 8 the IRQO interrupt is enabled but input capture is available even if an interrupt is disabled However if an interrupt is enabled the pulse width between rising edges of the external interrupt input signal can be measured by reading the value of TM4IC register by the interrupt service routine and by calculating the margin of the capture values the values of the TM4IC regis ter 16 Bit Timer Capture VI 27 Chapter 7 Time Base Timer 8 Bit Free running Timer Chapter 7 Time Base Timer 8 Bit Free running Timer 7 1 Overview This LSI has a time base timer and a 8 bit free running timer timer 5 Time base timer is a 13 bit timer counter These timers stop the timer counting only at standby mode STOP mode 7 1 1 Functions Table 7 1 1 shows the clock sources and the interrupt generation cycles that timer 5 and time base timer can select Table 7 1 1 Clock Source and Generation Cycle Timer 5 8 Bit free running timer Timer operation Interrupt source TBIRQ fosc 15 4 5 Se fx fosc X 1 25 fx X 1 213 72 fosc X 1 27 fosc X 1 28 fosc X 1 29 fosc X 1 29 Interrupt generation fosc X 1 25 The interrupt generation cycle is decided by the any cycle fk X 1 27 7 value written to 5 fx X 1 28 fx
184. from reset the oscillation stabilization wait time is fixed to 2 x system clock System clock is determined by the CPU mode control register CPUM Table 2 5 1 Oscillation Stabilization Wait Time Oscillation stabilization wait time eee at 20 MHz 2 x Systemclock 1 6384 ms o 2 Systemeock Reset II 27 Chapter 3 Interrupts Chapter 3 Interrupts 3 1 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corresponding interrupt service routine from an interrupt vector table reset non maskable interrupts NMI 8 maskable peripheral interrupts and 4 external interrupts For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing After the interrupt is accepted the program counter PC and processor status word PSW and handy addressing data HA are saved onto the stack And an inter rupts handler ends by restoring using the POP instruction and other means the contents of any regis ters used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was interrupted Max 12 machine cycles before execution and max 11 machine cycles after execution Each interrupt has an interrupt control register which controls the interrupts Interrupt control register
185. g a frequency 1 2 to 1 2 of the system clock fs POG BUZZER pin 9 1 1 Block Diagram iBuzzer Block Diagram 1 214 fs 2 2 Reset input CH E U gt BUZZER DLYCTR M _DLYSO_ 0 9 8 BUZCK1 BUZOE 7 Figure 9 1 1 Block Diagram Buzzer Ix 2 Overview Chapter9 Buzzer 9 2 Control Register Oscillation Stabilization Wait Time Control Register 7 6 5 4 3 2 1 0 DLYCTR BUZOE BUZCK1 BUZCKO DLYS1 DLYSO At reset 0xx 00 Oscillation stabilization wait period selection DLYS1 DLYSO 0 fs 2 4 1 fs 210 o _ 15 26 1 1 Do not set Note After reset is released the oscillation stabilization wait period is fixed at 5 214 Buzzer output BUZCK1 BUZCKO frequency selection 0 fs 212 0 1 16 211 i o fs 21 1 fs 29 BUZOE P06 output selection 0 port data output 1 buzzer output Figure 9 2 1 Oscillation Stabilization Wait Timer Control Register DLYCTR 03 03 R W Control Register IX 3 Chapter9 Buzzer 9 3 Operation 9 3 1 Operation mBuzzer Buzzer outputs the square wave having a frequency 1 2 to 1 2 2 of the system clock fs The BUZCK 1 0 flag of the oscillation stabilization wait control register DLYCTR
186. g of the SCOMDO register sets if a start condition is enabled or not If a start condition is enabled and input a bit counter is cleared to start the communication The start condition if the SCOCE1 flag of the SCOMDO register is set to 0 is regarded when a data line 5810 pin with 3 channels or SBOO pin with 2 channels is changed from H to L as a clock line SBTO pin is H Also the start condition if the SCOCE1 flag is set to 1 is regarded when a data line 5810 pin with 3 channels or 5800 pin with 2 channels is changed from to L as a clock line SBTO pin is L When the reception and the transmission should be operated at the same time disable start condition for proper operation Enabling the start condition drives the SBOO pin high level for a fixed time interval 1 2 the clock source cycle after the transmission has completed If the start condition is disabled the 5800 pin will remain at the level of the last data bit cleared when the start condition is received In this case the receive bit count is fixed at 8 bits Gd If the start condition is enabled the SCOLNG2 to 0 flags of the SCOMDO register will be reception and the transmission should not be operated at the same time The clock may be a On the master communication of the clock synchronous if start condition is enabled the 5 continued to output after the communication has completed First Transfer Bit The SCO
187. ge zF Size peat Ext 1 2 3 4 5 6 7 8 9 10 11 Data Move Instructions MOV MOV Dn Dm 211 1010 DnDm 25 MOV imm8 Dm imm8 Dm 1 1 1 1412 1010 DmDm lt 8 gt 25 Dn PSW 5 3 3 0010 1001 01Dn 26 MOV PSW Dm PSWDm 3 2 0010 0001 01Dm 26 MOV An Dm mem8 An Dm 2 2 0100 1ADm 27 MOV d8 An Dm mem8 d8 An Dm 1 1 1 1412 0110 1ADm 48 d16 An Dm mem8 d16 An Dm 7 4 0010 0110 1ADm lt d16 gt 28 d4 SP Dm mem8 d4 SP 5Dm 3 2 0110 01Dm lt d4 gt 2 28 MOV d8 SP Dm mem8 d8 SP gt Dm 1 1 1 1513 0010 0110 01Dm d8 gt 3 29 MOV d16 SP Dm mem8 d16 SP gt Dm 7 4 0010 0110 00Dm d 6 ahs 29 MOV i08 D mem8 IOTOP io8 5 Dm 4 2 0110 00Dm lt 08 gt 30 abs8 Dm mem8 abs8 Dm 4 2 0100 01Dm abs 8 30 MOV abs12 Dm mem8 abs12 gt Dm 5 2 0100 00Dm abs 12 gt 31 MOV abs16 Dm mem8 abs16 gt Dm 7 4 0010 1100 000 abs 16 gt 31 MOV Dn Am 2 2 0101 1aDn 32 Dn d8 Am 8 1 1 1 1412 0111 48 32 MOV Dn d16 Am 8 916 7 4 0010 0111 1aDn lt d16 33 Dn d4 SP Dn mem8 d4 SP 1 1 1 1312 0111 01Dn 04 2 33 Dn d8 SP
188. ge to the ICE The switches that the adapter board provides for configuring the probe are described below Adapter Board Layout 1 Q 8 1 S2 Oscillator control Set this switch to its USR position to drive the in circuit emulator with the oscillator built into the target board If there is no oscillator on the target board set this switch to the ICE position to use the oscillator built into the probe 2 S1 Power supply control Set this switch to its USR position to use the power supply from the target board If there is no oscillator on the target board set this switch to the ICE position to use the 5 V power supply from the in circuit emulator attention To use A D converter with power supply below 5 V set this switch to its USR position Reference voltage is 5 V 3 Function control DIP switches Each model has different setting of DIPSW as described below LCDSEL ON For models which use LCD function OFF For models which use LED function WDSEL1 WDSEL2 Switches for watchdog timer frequency Watchdog timer frequency WDSEL1 WDSEL2 NSSTRT Switch for oscillation control at reset released ON Start with the low speed XI oscillation Do not switch on at 101 45 OFF Start with the high speed OSC oscillation XII 14 EPROM Version Chapter 12 Appendices 12 2 3 PRB ADP101C11 42 45 48PIN Probe Switches Adapter boards differ depending upon the models This adapter board can be used for
189. generated Note In 2 each settings can be set at once When only reception with channels is operated set SCOSBOS of the SCOMD3 register to 0 and select a port The SBOO pin can be used as a general port When SBOO SBIO pin are connected for communication with 2 lines the SBOO pin inputs outputs serial data The port direction control register PODIR switches input output At re ception set SCOSBIS of the SCOMDS register to 1 always to select serial data input The SBIO pin can be used as a general port 2 If the SCOIOM flag of the SCOMD3 register is set 1 the 5810 pin can be used as port When the SBOO pin is input mode reception is operated and when it is output mode trans mission is operated When the register except the SCOTRB is written or rewritten set the SCOSBOS SCOSBIS flag to 0 4 4 When the internal clock is used as clock source write dummy data to the SCOTRB register after setting the SCOSBIS flag and the SCOSBOS flag of the SCOMDS register to 1 Even if the reception is operated again write dummy data to the SCOTRB register X 28 Operation 10 3 3 Half duplex UART Serial Interface Chapter 10 Serial Interface 0 Serial interface 0 can be used for half duplex UART communication Table 10 3 11 shows UART serial interface functions Table 10 3 11 UART Serial Interface Functions Communication style
190. guration 0 Push pull output 1 N ch open drain output SCOIOM Reception port SBIO Reception port SBOO Transmission port SBIO General port SBOO Transmission Reception port Figure 10 2 6 Serial Interface 0 Mode Register 3 SCOMDS 03 53 R W Control Registers X 9 Chapter 10 Serial Interface 0 Serial Interface 0 Control Register SCOCTR The SCOORE SCOPEK SCOFEF and SCOBSY flags are only readable 7 6 3 2 1 SCOCTR SCOBSY SCOCMD SCOFEF SCOPEK SCOORE At reset 00 000 SCOORE Overrun error detection 0 No error 1 Error SCOPEK Parity error detection 0 No error 1 Error SCOFEF Framing error detection 0 No error 1 Error Clock synchronous ee UART selection 0 Clock synchronous 1 UART SCOBSY Serial bus status 0 Other use 1 Serial transmission in progress Figure 10 2 7 Serial Interface 0 Control Register SCOCTR x 03F54 R W X 10 Control Registers Chapter 10 Serial Interface 0 10 3 Operation Serial Interface 0 can be used for both clock synchronous and half duplex UART 10 3 1 Clock Synchronous Serial Interface Selection of Clock Synchronous Serial Interface When the serial interface 0 is used as clock synchronous serial interface set the SCOCMD flag of the serial interface control register S
191. h automatic data transfer can not be used because it is necessary to write dummy data to serial interface buffer and to read reception data per a frame reception Operation X 11 Chapter 10 Serial Interface 0 Cautions for master clock reception by the synchronous serial interface 0 On the product with serial interface 1 or serial interface 2 master clock reception by synchro nous serial interface 1 2 is started by setting the SCxSBTS of the serial interface mode register SCxMDx to 1 then setting the SCxSBIS to 1 and writing dummy data to the transmission reception shift register 5 But by the above setting this serial interface 0 cannot output the master clock so that the reception is not started Therefore the following setup by the software is necessary lt By software gt When synchronous serial interface 0 is used for master clock reception it is necessary to set the SCOSBTS flag of the serial interface 0 mode register SCOMD3 to 1 then set the SCOSBIS flag to 1 and set the SCOSBOS flag to 1 At last the master clock is output by the writing dummy data to the transmission reception shift register SCOTRB then the reception is started Program example for master clock reception by the synchronous serial interface 0 SCOSBTS lt 1 SCOSBIS SCOSBOS lt 1 1 SCOTRB lt dummy data is written reception is started The SBOO pin cannot be used as general outp
192. hannel the TXD pin inputs outputs serial data The port direction control register PODIR should be set for switching input output At reception the SCOSBIS flag of the SCOMDS register should be set to 1 and select serial interface data input The RXD pin can be used as a general port X 46 Operation Chapter 10 Serial Interface 0 um Only timer 3 can be used as a baud rate timer For baud rate setup refer to Chapter 5 5 7 Serial Interface Transfer Clock Output Serial interface 0 is operated by setting the SCOSBOS flag or the SCOSBIS of the SCOMDS register to 1 The SCOSBOS flag or the SCOSBIS flag should be set after all conditions are set After that at reception the communication is started by receiving start bit When register except the SCOTRB is written rewritten set the SCOSBOS the SCOSBIS flag of the SCOMD3 register to 0 in advance When the TXD RXD pin are connected for communication with 1 channel the TXD pin inputs outputs serial data The port direction control register PODIR should be set for switching input output The RXD pin can be used as a general port When the serial interface port is enabled if the SCOCE1 0 flag of the SCOMDO register is switched the transfer bit count may be changed If it is used as half duplex UART serial interface setting the SCOCE1 0 flag fixed to 00 is recommended
193. he stop bit at the transmission side to 2 bits and set the stop bit at the reception side to 1 bit For parity bit set the same to both sides of the reception and transmission Method 2 by parity bit Set the transmission parity bit to always 1 and set the reception parity bit to none For stop bit set the same to both sides of the reception and transmission At the reception parity bit is regarded as one of stop bit This error can be prevented if one of the above methods can be enabled Both methods do not depend on the combination of the oscillation frequency and the baud rate timer setup Operation 37 Chapter 10 Serial Interface 0 Transfer Rate Baud rate timer timer 3 can set any transfer rate Table 10 3 17 shows the setup example of the transfer rate For detail of the baud rate timer setup refer to chapter 5 5 7 serial interface transfer clock output operation Table 10 3 17 UART Serial Interface Transfer Rate Setup Register Setup Register Page Serial 0 clock source timer 3 output SCOMD 1 X 7 Timer 3 clock source TM3MD V 8 Timer 3 compare register TM3OC V 6 Timer 3 compare register is set as follows overflow cycle set value of compare register 1 x timer clock cycle baud rate 1 overflow cycle x 2 x 8 8 means that clock source is divided by 8 Therefore set value of compare register timer clock frequency baud rate x 2 x 8 1 For exa
194. iguration configuration function control function SCOBSY SCOCMD SCOFEF SCOPEK SCOORE 0 0 0 0 0 54 SCOCTR 10 Serial bus synchronous Framing error Parity error Overrun error status UART detection detection detection SCOTRB7 SCOTRB6 SCOTRB5 SCOTRB4 SCOTRB3 SCOTRB2 SCOTRB1 SCOTRBO X x x x x x X 3F55 SCOTRB TTA T 5 Serial interface 0 transmission reception shift register SCORXB7 SCORXB6 SCORXB5 SCORXB4 SCORXB3 SCORXB2 SCORXB1 SCORXBO x x x x x x X x X 3F56 SCORXB 5 Serial interface 0 reception data buffer TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BCO 0 0 0 0 0 0 0 0 X 3F62 TM2BC V 6 Timer 2 binary counter TM3BC7 6 5 4 2 TM3BC1 TM3BCO E x 0 0 0 0 0 X 3F63 TM3BC V 6 Timer 3 binary counter Note x Initial value is unstable No data XII 18 Special Function Registers List Chapter 1 2 Appendices Bit Symbol Initial Value Description Address Register Bit 5 Bit 4 Bit 3 TM4BCL7 TM4BCL6 TM4BCL5 TM4BCL4 TM4BCL3 TM4BCL2 TM4BCL1 TM4BCLO 0 0 0 0 0 0 0 0 X 3F64 TM4BCL VI 5 Timer 4 binary counter lower 8 bits TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2 TM4BCH1 TM4BCHO 0 0 0 0 0 0
195. in The driving frequency can be selected by the DLYCTR register Select output mode by the PODIR register and select buzzer output by the DLYCTR register When not used for buzzer output this pin can be used as a normal pin TMAIO 28 VO P14 Timer VO pin Event counter clock input pin timer output and PWM signal output pin for 16 bit timer 4 To use this pin as event clock input configure this as input pins through the P1DIR register In the input mode pull up resistors can be selected by the P1PLU register For timer output PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register When not used for timer VO this can be used as normal VO pin I 14 Pin Description Chapter 1 Overview Table 1 3 6 Pin Function Summary 5 5 Name an pin y o Function Description ANO 62 Input PAO Analog input pins Analog input pins for an 8 channel 10 bit A D 1 63 PA1 converter AN2 64 PA2 When not used for analog input these pins can be used AN3 1 PA3 as normal input pins AN4 2 PA4 5 3 PA5 AN6 4 PA6 AN7 5 PA7 IRQO 29 Input P20 External interrupt External interrupt input pins IRQ1 30 P21 ACZ input pins The valid edge for IRQO to 3 can be selected through IRQ2 31 P22 the IRQnICR register IRQ3 32 P23 IRQ1 is an external interrupt pin that is able to deternine
196. is switched the transfer bit count may be changed If it is used as half duplex UART serial interface setting the SCOCE1 0 flag fixed to 00 is recommended After transmission has completed the TXD pin is H level If the frame mode is set by the SCOFM flag of the SCOMD2 register the SCOLNG2 0 flag of the SCOMDO register is automatically set After the transfer has completed the transfer bit count in the SCOLNG2 0 flag of the SCOMDO register is automatically set 25 At UART transmission set the SCOSBOS flag of the SCOMDS register to 1 and set the SCOSBIS flag to 0 Setting both of flags to 1 is disabled X 44 Operation Setup The setup example at UART reception with serial interface 0 is shown Table 10 3 23 shows the conditions at reception Chapter 10 Serial Interface 0 Table 10 3 23 UART Interface Transmission Reception Setup Setup item set to TXD RXD pi n connected with 1 channel Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source timer 3 TXD pin type Nch open drain Pull up resistor of TXD pin added Parity bit add check O add check Serial 0 interface interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the UART communication SCOCTR x 3F
197. ith any resonator Set the sample hold time Set the sample hold time by the ANSH1 ANSHO flag of the A D converter control register 0 ANCTRO The sample hold time should be based on analog input impedance Set the A D ladder resistance Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 and a current flow through the ladder resistance and A D converter goes into the waiting 2 to 5 are not in order 3 4 and 5 can be operated simultaneously Start the A D conversion Set the ANST flag of the A D converter control register 1 ANCTR1 to 1 to start A D converter A D conversion Each bit of the A D buffer 0 1 is generated after being sampled during sample and hold time set in 3 Each bit is generated in sequence from MSB to LSB Complete the A D conversion When A D conversion has finished the ANST flag is cleared to 0 and the result of the conversion is stored to the A D buffer ANBUFO 1 At the same time the A D complete interrupt request ADIRQ is generated Operation Chapter 11 A D Converter A D conversion clock ANST A D conversion start A D conversion complete Ts lt gt Sampling Hold A D conversion bit 8 comparison bit 9 comparison bit 0 comparison bit 9 bit 8 bit 1 bit 0 Determine Determine Determine Determine ______ This example is as sampling and hold time i
198. l Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source timer 3 output TXD pin type Nch open drain Pull up resistor of TXD pin not added Parity bit add check O add check Serial interface 0 interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the UART communication SCOCTR x 3F54 bp6 SCOCMD 1 Select the first bit to be transferred SCOMDO x 3F50 bp4 SCODIR 0 Select the start condition SCOMDO x 3F50 bp3 SCOSTE 0 Select the clock source SCOMD1 x 3F51 bp4 3 SCOCK1 0 11 Select the parity bit SCOMD2 x 3F52 SCONPE 0 bp2 1 SCOPM1 0 00 Set the SCOCMD flag of the SCOCTR register to 1 to select the UART communication Select MSB as first transfer bit by the SCODIR flag of the SCOMDO register Set the SCOSTE flag of the SCOMDO register to disable start condition t X 33 5 of Start Condition Set the SCOCK1 0 flag to select timer 3 output as a clock source Set the SCONPE flag of the SCOMD2 register to select parity is enabled and set the SCOPM1 0 flag to select 0 added X 42 Operation Chapter 10 Serial Interface 0 Setup Procedure Description 6 Specify the flame mode SCOMD2 x 3F52 bp4 3 SCOFM1 0 11 7 Control the output data SCOMD2 x
199. l bp6 PODIRG 1 3 Buzzer output ON 3 Set the BUZOE flag of the oscillation DLYCTR x 3F03 stabilization wait control register DLYCTR to bp7 BUZOE 1 1 to output the square wave of the buzzer output frequency set by 06 pin 4 Buzzer output OFF 4 Set the BUZOE flag of the oscillation DLYCTR x 3F03 stabilization wait control register DLYCTR to bp7 BUZOE 0 to clear and pin outputs low level IX 5 Operation Chapter 10 Serial Interface 0 Chapter 10 Serial Interface 0 10 1 Overview This LSI contains a serial interface 0 that can be used for both communication types of clock synchro nous and UART Half duplex 10 1 1 Functions Table 10 1 1 shows functions of serial interface 0 Table 10 1 1 Serial Interface 0 Functions Communication style clock synchronous UART half duplex Interrupt SCOIRQ SCOIRQ Used pins SBOO SBIO SBTO TXD RXD 3 channels type 2 channels type Y SBOO SBTO 1 channel type Y TXD 7 bits 1 stop Specification of transfer bit 1 to 8 bits 7 bits 2 stops count Frame selection 8 bits 1 stop 8 bits 2 stops Selection of parity bit Y 0 parity lm _ 1 Parity bit control odd parity even parity no selection Selection of start condition Start bit is always added Specification of the first 4 4 transfer bit Specification of input edge 4 _ output edge Internal clock 1 8 dividing
200. label JSR d16 label MOV 8 abs8 abs12 PUSH An OR 8 Dm AND 8 Dm When the exension code is b oo10 When the extension code is b 0011 MOV abs12 Dm MOV abs8 Dm MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV io8 Dm MOV d4 SP Dm MOV d8 An Dm MOV Dn io8 MOV Dn d4 SP Dn d8 Am ADD 4 Dm SUB Dn Dn BGE d7 BRA d7 BEQ d7 BNE d7 BCC d7 BCS d7 BLT d7 BLE d7 BEQ d4 BNE d4 MOVW DWn HA MOVW An HA d11 BRA 411 011 411 BCC d11 BCS 411 BLT 11 BLE 411 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp CMP 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVW DWn abs8 CBNE 8 Dm d7 CMPW 16 Am MOVW 16 Am MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am BRA d4 MOVW DWn Am Extension code 6 0010 2nd nible 3rd nibble 0 1 MOVW An Am MOVW 84 8 4 5 CMPW An Am MOVW DWn d4 SP PUSH Dn 8 9 A B MOVW SP Am MOVW An SP ADDW 8 SP ADDW 4 SP BTST 8 JSRV ibi JMP A0 JSR A0 JMP A1 JSR 1 MOV PSW Dm REP 3 BGT d7 BHI d7 BLS d7 BNC 47 BNS d7 BVC d7 BVS d7 NOT Dn ROR Dn BGT 411 BHI d11 BLS d11 BNC d
201. label if NF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0100 lt 11 3 11 1 6 BNS labe if NF 1 PC 5 d7 label H2PC 5 3 4 0010 0010 0101 47 2 111 if NF 0 PC 53PC BNS labe 1 6 11 6 3 4 0010 0011 0101 411 3 111 if NF 0 PC 63PC BVC labe if VF 0 PC 5 d7 label H PC 5 3 4 0010 0010 0110 d7 2 11 if VF 1 PC 5PC BVC labe if VF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0110 lt d11 H 3 101 1 6 BVS label if VF 1 PC 5 d7 label H PC 5 3 4 0010 0010 0111 d7 H 211 0 5 BVS label if VF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0111 dii 11 0 6 5 BRA labe PC 3 d4 label H PC 1 1 1 13 1110 111H lt d4 gt 1 1114 BRA labe PC 4 d7 label H PC 1 1 1 14 1000 1001 47 2 114 BRA labe PC 5 d11 1 1 1 15 1001 1001 411 3 115 CBEQ CBEQ imm8 Dm label if Dm imm8 PC 6 d7 label H3PC 6 3 4 1100 10Dm 48 gt lt d7 2 41 6 imm8 Dm label if Dmzimm8 PC 8 dit labe 4HOPC e e e e 8 45 0010 1100 10Dm 48 gt lt 11 3 11 if Dmzimm8 PC 82PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8 PC 9 d7 label HPC e e 9 6 7 0010 1101 1100 abs 8
202. lag Setup V 16 8 Bit Event Count Chapter 5 8 Timers Setup Procedure Description 7 Enable the interrupt 7 Setthe TM2IE flag of the TM2ICR register to TM2ICR 1 to enable the interrupt bp1 TM2IE 1 8 Start the event counting 8 Set the TM2EN flag of the TM2MD register to TM2MD x 3F82 start timer 2 bp4 TM2EN 1 Every time TM2BC detects the falling edge of 2 input TM2BC counts up from x00 When TM2BC reaches the setting value of the TM2OC register the timer 2 interrupt request flag is set at the next count clock then the value of TM2BC becomes x 00 and counting up is restarted 8 Bit Event Count V 17 Chapter 5 8 Timers 5 5 8 Bit Timer Pulse Output 5 5 1 Operation The TMnIO pin can output a pulse signal with any cycle B Operation of Timer Pulse Output Timers 2 and 3 The timers can output 2 x cycle signal compared to the setting value in the compare register TMnOC Output pins are as follows Table 5 5 1 Timer Pulse Output Pins Timer 2 Timer 3 20 output output Pulse output pin P12 P13 ilCount Timing of Timer Pulse Output Timers 2 and 3 flag Compare register Binary 00 ot 4N N X 00 4N 1 N 00 0t N 4X N counter Compare Match signal Interrupt request flag output Figure 5 5 1 Count Timing of Timer Pulse Output Timers
203. lation at NORMAL mode tc4 1 4 of low speed oscillation at SLOW mode 1 18 Electrical Characteristics Chapter 1 Overview Ta 40 C to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions Unit MIN TYP MAX Crystal oscillator 1 Fig 1 5 1 10 Crystal frequency depending in 1 0 20 0 MHz operating voltage 11 20 External capacitors pF 12 C12 20 13 Internal feedback resistor Rfto 700 Crystal oscillator 2 Fig 1 5 2 14 Crystal frequency fxtal2 32 768 100 kHz 15 20 External capasitors pF 16 C22 20 17 Internal feedback resistor Rf20 4 0 MQ OSC1 XI Rizo 700 2 4 0 vo Typ fxtal2 MN101C MN101CT e 0562 C12 C11 C22 __ 21 feedback resistor is built in The feedback resistor is built in Figure 1 5 1 Crystal Oscillator 1 Figure 1 5 2 Crystal Oscillator 2 Connect external capacitors that suit for used oscillator When crystal oscillator or ceramic 1 oscillator is used the oscillation frequency is changed depending on condenser Consult the 2 oscillator manufacturer to select the suitable external capacitor Electrical Characteristics I 19 Chapter 1 Overview Ta 40 to 85 2 0 V 2 7 V to 5 5 V
204. led regardless of the interrupt request flag and the interrupt enable flag TM2ICR 7 6 1 0 TM2 TM2 LV1 LVO TM2IE TM2IR Atreset 00 00 TM2IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated 21 Interrupt enable flag 0 Disable interrupt 1 Enable interrupt TM2 TM2 interrupt level f Lvi vo teve tag The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 6 Timer 2 Interrupt Control Register TM2ICR x 03FE6 R W Control Registers III 21 Chapter 3 Interrupts Timer Interrupt Control Register TM3ICR The timer 3 interrupt control register TM3ICR controls interrupt level of timer 3 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter enable flag MIE of PSW is 0 When the interrupt level flag is set to level TM3LV1 TM3LVO 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 TM3 TM3 1 E eum TM3ICR LVI LVO TM3IR At reset 0 0 0 0 TMSIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated TMSIE Interrupt enable flag 0 Disable interrupt 1 Enable
205. me mode is specified During reception transmission is disabled Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SCOFM1 to 0 flag of the SCOMD2 register If the SCOCMD flag of the SCOCTR register is set to 1 and UART communica tion is selected the synchronous serial data transfer bit count selection SCOLNG2 to 0 of the SCOMDO register is automatically set minput Edge Output Edge Setup The SCOCE 1 to 0 flag of the SCOMDO register set an output edge of the transmission data an input edge of the received data At UART communication not the transfer clock being needed but the SCOCE 1 0 flag should be set to decide the timing of the data transmission reception in this serial interface At UART communication generally set the SCOCE1 0 flag to 00 the transmission data output edge to falling and the reception data input edge to rising Refer to table 10 3 2 X 16 for Input Edge Output Edge Setup detail mData Input Pin Setup The communication mode can be selected from with 2 channels data output pin TXD pin data input pin RXD pin or with 1 channel data I O pin TXD pin The RXD pin can be used only for serial data input The TXD pin can be used for serial data input or output The SCOIOM flag of the SCOMDS register can specify which pin RXD or TXD to input the serial data Data input from TXD pin is selected to be with 1 channel communication At s
206. means that reading and decoding are executed at the same time on different instruc tions then instructions are executed without stopping Pipeline process makes instruction execution continual and speedy This process is executed with instruction queue and instruction decoder Instruction queue is buffer that fetches the second instruction in advance That is controlled to fetch the next instruction when instruction queue is empty at each cycle on execution At the last cycle of instruc tion execution the first word operation code of executed instruction is stored to instruction register At that time the next operand or operation code is fetched to instruction queue so that the next instruction can be executed immediately even if register direct da or immediate imm is required at the first cycle of the next instruction execution But on some other instruction such as branch instruction instruction queue becomes empty on the time that the next operation code to be executed is stored to instruction register at the last cycle Therefore only when instruction queue is empty and direct address da or immediate data imm are required instruction queue keeps waiting for a cycle Instruction queue is controlled automatically by hardware so that there is no need to be controlled by software But when instruction execution time is estimated operation of instruction queue should be into consideration Instruction decoder generates control signal at
207. mer 8 Bit Free running Timer WCount Timing of Timer Operation Time Base Timer The counter counts up with the selected clock source as a count clock 12 11 10 9 fosc fx 13 10 9 8 7 1 2 1 2 1 2 1 2 1 2 Figure 7 4 1 Count Timing of Timer Operation Time Base Timer When the selected interrupt cycle has passed the interrupt request flag of the time base interrupt control register TBICR is set to 1 An interrupt may be generated at switching of the clock source Enable interrupt after switch ing the clock source Time base timer cannot stop the operation 13 bit counter of time base timer can be initialized only at reset This LSI has built in time base timer for digital clock For example if fx 32 768 kHz is selected as clock source interrupt request flag is set by 13 bit counter par 250 ms However the 13 bit counter can be initialized only at reset Therefore the first interrupt request flag is not always set after 250 ms Depending on counting condition the first interrupt request flag is generated after 0 ms minimum to 250 ms maximum So digital clock may gain 250 ms maximum How to keep a error to a minimum on setting for digital clock When fx 32 768 kHz is set as clock source and the time base timer is used as digital clock Select fosc as clock source 1 Generate interrupt During interrupt service routine change clock source to fx and ini
208. mer Table 7 3 2 shows the clock source selection and the TM5OC register setup when a 8 bit free running timer is used as a 1 minute timer a 1 second timer Table 7 3 2 1 minute timer 1 second timer Setup Timer 5 Clock Source 50 Register 1 min fx x 1 213 fx x 1 210 15 fx x 1 2 fx 32 768 kHz When the 1 minute timer 1 min is set on Table 7 3 2 the bp1 waveform frequency cycle of the TM5BC register is 1 Hz 1 s So that can be used for adjusting the seconds 58 _ LI LILI LI 71 Hz 1 5 Figure 7 3 1 Waveform of TM5BC Register bp1 Timer 5 VII 8 8 Bit Free running Timer Chapter 7 Time Base Timer 8 Bit Free running Timer iCount Timing of Timer Operation Timer 5 Binary counter counts up with the selected clock source as a count clock Count clock TM5CLRS flag Compare register i 1 B ADIOOZLOGODOZODUOU counter A D Compare match signal Interrupt request i flag C Figure 7 3 2 Count Timing of Timer Operation Timer 5 A When any data is written to the compare register as the TM5CLRS flag is 0 the binary counter is cleared to 00 B Even if any data is written to the compare register as the TM5CLRS flag is 1 the binary counter is not changed C When the binary counter reaches the value of the compare register as the TM5CLRS flag is 1 aninte
209. mer if enabled resumes counting Program 4 MOV x 4 DO Set HALTO mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Program 5 MOV x 7 DO Set HALT1 mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Transition to STOP mode The system transfers from NORMAL mode to STOPO mode and from SLOW mode to STOP1 mode In both cases oscillation and the CPU are both halted There are two ways to leave a STOP mode a reset or an interrupt Program 6 MOV x 8 DO Set STOPO mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Program 7 MOV x B DO Set STOP1 mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Right after the instruction of the transition to HALT STOP mode NOP instruction should be inserted 3 times Do not set the system to enter the stop mode when instructions are executed the RAM area Standby Functions II 23 Chapter 2 CPU Basics 2 5 Reset 2 5 1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin P27 is pulled to low Binitiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low NRST pin should be held
210. mpare register B is L after the match to the value in the compare register then the binary counter continues counting up till the overflow C is again if the binary counter overflows 8 Bit PWM Output V 21 Chapter 5 8 Timers i Count Timing of PWM Output when the compare register is x 00 Timers 2 Here is the count timing when the compare register is set to x 00 TMnEN flag Compare register i 00 ovni eemper mim S An pen counter TMnIO output always L PWM output 4 Figure 5 6 2 Count Timing of PWM Output when compare register is x 00 iCount Timing of PWM Output when the compare register is x FF Timers 2 Here is the count timing when the compare register is set to x FF TMnEN flag Compare register Binary co par pesquero a TMnIO output PWM output Figure 5 6 3 Count Timing of PWM Output when compare register is FF V 22 8Bit PWM Output Chapter 5 8 Bit Timers 5 6 2 Setup Example BPWM Output Setup Example Timers 2 The 1 4 duty cycle PWM output waveform is output from the 2 output pin at 2 kHz by using timer 2 at fosc 4 19 MHz Cycle period of PWM output waveform is decided by the overflow of the binary counter H period of the PWM output waveform is decided by the setting value of the compare register An example setup procedure with a description of each step is shown below TM2IO outp
211. mple if baud rate should be 300 bps at timer 3 clock source fs 4 fosc 8 MHz fs fosc 2 set value should be as follows Set value of compare register 8 x 10 2 4 300 x 2 x 8 1 207 Timer 3 clock source and the set values of 3 compare register at the standard transfer rate are shown on the following page 1 At UART communication clock source is divided by 8 is selected regardless of the setup for the SCOCKM flag of the SCOMD1 register X 38 Operation Chapter 10 Serial Interface 0 Table 10 3 18 UART Serial Interface Transfer Rate and Timer 3 Compare Register decimal Transfer Rate bps fosc Clock source 300 1200 2400 4800 9600 19200 MHz timer3 Set value Calculated Value Set value Calculated Value Set value Calculated Value Set value Calculated Value Set value Calculated Value Set value Calculated Value 4 00 osc gt 207 1202 103 2403 51 4807 25 9615 12 19230 5 4 103 300 5 16 5 4 19 osc 217 1201 108 2402 54 4762 26 9699 5 5 4 108 300 5 16 E 8 00 osc E 207 2404 103 4807 51 9615 25 19230 5 4 207 300 51 1201 5 16 z S gt 5 3 8 38 osc E 217 2403 108 4805 54 9523 26 19398 5 4 217 300 54 1190 5 5 16 12 00 osc x 5 155 1808 77 9615 38 19230 5 4 E 77 1202 38 2403 5 s 16 77
212. n SCOMD3 SCOSBOS SCOMD3 SCOSBIS SCOMD3 SCOSBTS Push pull Push pull Push pull Style Nch open drain Nch open drain Nch open drain SCOMD3 SCOSBOM SCOMD3 SCOSBTM T Output mode Output mode Input mode PODIR PODIRO PODIR PODIR2 sui Added Not added Added Not added Added Not added ull up POPLU POPLUO POPLU POPLU2 X 24 Operation Chapter 10 Serial Interface 0 WPins Setup 2 channels at reception Table 10 3 9 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at reception SBIO pin can be used as a general port Table 10 3 9 Setup for Synchronous Serial Interface Pin 2 channels at reception Data VO pin Serial unused pin Clock pin Setup item SBTO 5 0 580 pin Internal clock External clock master communication slave communication Pin P01 P02 580 SBOO connected SBIO SBOO pin SCOMD3 SCOIOM Port Serial data input Serial clock VO Port Function SCOMD3 SCOMD3 SCOSBOS SCOSBIS SCOMDS SC0SBTS Push pull Push pull Stype Nch open drain Nch open drain SCOMD3 SCOSBTM Input mode Output mode Input mode PODIR PODIRO PODIR PODIR2 di Added Not added Added Not added Added Not added ull up POPLU POPLUO POPLU POPLU2 Operation X 25 Chapter 10 Serial Interface 0 10 3 2 Setup Example Transmission Reception Setup Example The setup e
213. n clock input at slave transmission to SCOTRB without start condition Figure 10 3 4 Transmission Timing rising edge Operation 19 Chapter 10 Serial Interface 0 Reception Timing Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Input start condition Figure 10 3 5 Reception Timing rising edge start condition is enabled Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Write dummy data to SCOTRB at master or clock input at slave Figure 10 3 6 Reception Timing rising edge start condition is disabled X 20 Operation Chapter 10 Serial Interface 0 Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Input start condition Figure 10 3 7 Reception Timing falling edge start condition is enabled Clock SBTO pin Input data SBIO pin Transfer bit counter SCOLNG2 to 0 SCOBSY Interrupt SCOIRQ A Write dummy data to SCOTRB at master or clock input at slave Figure 10 3 8 Reception Timing falling edge start condition is disabled Operation X 21 Chapter 10 Serial Interface 0 Transmission Reception Simultaneous Timing When transmission and reception are operated at the same time set the SCOCEO to 1 flag of the S
214. nce a overflow happens the PWM source waveform outputs H again and TM4BCL counts up from 00 again From the above setting the basic PWM waveform becomes 64 192 And the is set to x 07 in the PWM output repetitions 256 times the added pulse is appended 7 times and the duty becomes 65 191 For PWM operation x FF in TM4OCL produces the same result as x 00 constant low level output at the PWM4 pin not constant high Do not set x FF in TM4OCL Use 16 bit access instruction to TM4OCL register Added Pulse Type 16 Bit PWM Output VI 23 Chapter 6 16 Bit Timer 6 7 6 7 1 16 Bit Timer Capture Operation The value of a binary counter is stored to register at the timing of the external interrupt input signal iCapture Operation with External Interrupt Signal as a Trigger Timer 4 Capture trigger of input capture function is generated at the external interrupt signal that passed through the external interrupt interface block The capture trigger is selected by the timer 4 mode register TM4MD and the external interrupt control register IRQOICR IRQ1ICR IRQ2ICR Here are the capture trigger to be selected and the interrupt flag setup Capture trigger source Table 6 7 1 Capture Trigger Timer 4 mode External interrupt n control Interrupt starting edge register register IRQnICR of external interrupt n T4ICTS1 0 REDGn bp5 Disable i
215. ng of the 256 K bit EPROM 27C256 EPROM Version XII 11 Chapter 12 Appendices 12 1 8 Option Bit MN101CP427 has EPROM option address to specify the watchdog timer frequency to select the pack age and to disenable the watchdog timer during the operation BEPROM Option Bits 7 6 5 4 3 2 1 0 5 WDMD PKGSEL2 PKGSEL1 WDSEL2 WDSEL1 Reserved Reserved Set always to 1 WDSEL2 WDSEL1 Watchdog timer frequency 0 fs 2 0 1 27 1 15 2 PKGSEL2 PKGSEL1 Package 0 SDIP042 P 0600 1 0 QFP044 P 1010 1 TQFP048 P 0707 MDMD Watchdog timer disenable control during the operation 0 disable 1 enable Figure 12 1 5 EPROM Option Bits Model EPROM option address 101 427 When the WDMD bp5 is set to 0 and once the watchdog timer is started the operation cannot be stopped XII 12 EPROM Version Chapter 12 Appendices 12 2 Probe Switches 12 2 1 PRB ADP101C11 42 45 42PIN Probe Switches Adapter boards differ depending upon the models This adapter board can be used for only 101C1 1 101C42 and 101 45 42 PIN Use this adapter board with EV board PRB EV101C15 Improper matching may cause any damage to the ICE The switches that the adapter board provides for configuring the probe are described below Adapter Board Layout 0 1 52 Oscillator control
216. nput capture 00 IRQO falling edge IRQO rising edge o1 Rao ROO falling edge 01 IRQO IRQO rising edge IRQ1 falling edge IRQ1 rising edge IRQ2 falling edge IRQ2 rising edge Raz 1 IRQ2 rising edge IRQ2 falling edge 1 IRQ1 rising edge 0 1 An interrupt request and a capture trigger are generated at switching the active edge of an external interrupt by program when the setup is as follows at switching the active edge from the falling to the rising when the interrupt pin is H level at switching the active edge from the rising to the falling when the interrupt pin is L level 1 2 Operate the interrupt flag with regard to the noise influence on the program Chapter 3 3 3 4 Programmable Active Edge Interrupt 114 VI 24 16 Bit Timer Capture Chapter 6 16 Bit Timer iCapture Count Timing at Falling Edges of External Interrupt Signal is selected as a Trigger Timer 4 N register 5 ale External interrupt m a aia 1 2 20 Capture trigger dU db db db 2 Figure 6 7 1 Capture Count Timing at an External Interrupt Signal is selected as a Trigger Timer 4 A capture trigger is generated at the falling edges of the external interrupt m input signal At the same timing the value of a binary counter is stored to the input capture register A capture trigger is generated only at the edge that is specified as a capture
217. nput register 15 P2PLU x 03F42 R W Port 2 pull up resistor control register V 15 16 R W Port 6 output register 18 26 R 6 input register 18 Pona P6DIR 03 36 R W Port 6 direction control register 18 P6PLU 46 R W Port 6 pull up resistor control register 18 P7OUT 17 R W Port 7 output register IV 21 Bolt P7IN X 03F27 7 input register 21 P7DIR 7 R W Port 7 direction control register 21 47 R W 7 pull up pull down resistor control register 21 P8OUT 18 R W 8 output register 25 BH P8IN X 03F28 8 input register 25 P8DIR 03 38 R W Port 8 direction control register 25 48 R W 8 pull up resistor control register 25 PAIN 2 input register 28 Port R W Port A input mode register 28 PAPLUD X 03F4A R W Port A pull up pull down resistor control register 28 21 FLOAT1 4 R W Pin control register 1 22 29 IV 4 Overview Chapter 4 Ports 4 2 PortO 4 2 1 Description Port Setup Each bit of the port 0 control I O direction register PODIR can be set individually to set pins as input or output The control flag of the port 0 direction control register PODIR should be set to 1 for output mode and 0 for input mode To read input data of pin
218. nterrupt request Chapter 12 Appendices Bit Symbol Initial Value Description Bit 5 Bit 4 Bit 3 IRQ2LV1 IRQ2LVO REDG2 IRQ2IE IRQ2IR 0 0 0 0 0 IRQ2 interrupt level IRQ2 interrupt IRQ2 interrupt IRQ2 interrupt Address Register X 3FEB IRQ2ICR active edge enable request IRQ3LV1 IRQ3LVO REDG3 IRQSIE IRQ3IR 0 0 0 0 0 IRQ3 interrupt level IRQ3 interrupt IRQS interrupt IRQ3 interrupt active edge enable request TMS3LV1 TM3LVO 0 0 0 0 interrupt level interrupt interrupt enable request TM4LV1 TM4LVO 4 TM4IR 0 0 0 0 interrupt level TM4 interrupt TM4i nterrupt X 3FEC IRQ3ICR X 3FEE TMSICR X 3FEF TM4ICR enable request TM5LV1 TM5LVO TMSIE 5 0 0 0 0 5 interrupt level TMS interrupt 5 interrupt enable request X 3FFO TMSICR Note x Initial value is unstable No data Can be used only for 48 pin TQFP package type Special Function Registers List XII 21 Chapter 12 Appendices 12 4 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag Re Machine Code Notes Pa
219. nterrupt control register IRQnICR and the internal interrupt control register XxxICR liINon Maskable Interrupt Control Register NMICR address x 03FE1 The non maskable interrupt control register NMICR stores the non maskable interrupt request When the non maskable interrupt request is generated the interrupt is accepted regardless of the interrupt mask level IMn of PSW The hardware then branches to the address stored at location x 04004 in the interrupt vector table The watchdog timer overflow interrupt request flag WDIR is set to 1 when the watchdog timer overflows The program interrupt request flag PIR is set to 1 when the undefined instruction is executed 7 6 5 4 3 2 1 0 NMICR PIR WDIR Reserved At reset 000 Reserved Always set to 0 WDIR Watchdog interrupt request flag 0 No interrupt request 1 Interrupt request generated PIR Program interrupt request flag 0 No interrupt request 1 Interrupt request generated Figure 3 2 1 Non Maskable Interrupt Control Register NMICR x 03FE1 R W On this LSI when undefined instruction is decoded the program interrupt request flag PIR is set to 1 and the non maskable interrupt is generated If the PIR flag setup is confirmed by the non maskable interrupt service routine the reset via the software is recommended When software reset the reset pin P27 outputs
220. nterrupts There are 4 external interrupts in this LSI The circuit external interrupt interface for the external interrupt input signal is built in between the external interrupt input pin and the interrupt controller block This external interrupt interface can manage to do with any kind of external interrupts 3 3 1 Overview Table 3 3 1 shows the list for functions which external interrupts 0 to 3 can be used Table 3 3 1 External Interrupt Functions External External External External interrupt O interrupt 1 interrupt 2 interrupt 3 IRQO IRQ1 IRQ2 IRQ3 External interrupt P20 21 poo P23 input pin Programmable active edge interrupt Noise filter built in y zero cross 5 4 2 gt detection Capture trigger for timer 4 Y Y Y 1 3 external interrupts are provided to other package types except 48 TQFP package type 2 External interrupt 3 IRQ3 can be used only for 48 pin TQFP package type 28 External Interrupts 3 3 2 eExternal Interrupt 0 Interface External Interrupt 1 Interface Block Diagram Block Diagram 21 1 7 x amp IRQ1LVO amp NFOEN NFOCKSO 2 NFOCKS1 NF1EN 7 NF
221. o the timer 4 compare register 4 0 B If the TM4EN flag is 1 the binary counter starts counting from 0000 The counting is happened at the falling edge of the count clock But the binary counter doesn t count up at the first falling edge of the count clock C If the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock and the binary counter is cleared to x 0000 to restart counting up D If the TM4EN flag is 0 the binary counter is stopped after 1 counting up Operation VI 9 Chapter 6 16 Bit Timer When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the interrupt is enabled the timer interrupt request flag should be cleared before timer operation is started If the smaller value than that of the binary counter TM4BC is set to the compare register the binary counter counts up to the overflow at first Even if the TM4EN flag of the timer 4 is cleared during operation it does not stop until the next count clock Therefore during max 1 count clock after the TM4EN is cleared the binary counter cannot be initialized VI 10 Operation 6 3 2 Operation
222. of the TM2MD register to TM2MD x 3F82 1 to operate timer 2 bp4 2 1 TM2BC counts up from 00 PWM source waveform outputs H till TM2BC reaches the setting value of the TM2OC register and outputs L after that Then TM2BC continues counting up and PWM source waveform outputs H again once overflow happens and TM2BC restarts counting up from 00 If the timer 2 PWM output is selected by setting the TM3PWM flag of the TM3MD register to 1 the pin outputs the timer 2 PWM output too When port 1 is used as PWM output pin the settings of the P1DIR register and the P1PLU register need to be set to 1 V 24 8Bit PWM Output Chapter 5 8 Bit Timers 5 7 J Serial Interface Transfer Clock Output 5 7 1 Operation Serial interface transfer clock can be created by using the timer output signal Serial Interface Transfer Clock Operation by 8 Bit Timer Timer 3 Timer 3 output can be used as a transfer clock source for serial interface 0 Table 5 7 1 Timer for Serial Interface Transfer Clock Serial transfer clock Timer 3 Serial interface 0 Timing of Serial Interface Transfer Clock Timer 3 ar register x MCE Mee Xe counter Interrupt request flag Timer output Serial transfer o o op clock Figure 5 7 1 Timing of Serial Interface Transfer Clock Timer 3 The tim
223. ol register 1 FLOAT1 select if pull up resistor or pull down resistor is added The bp1 of the FLOAT is set to 1 for pull down resistor and set to 0 for pull up resistor At reset the PAO to PA7 input mode is selected and pull up resistors are disabled ilSpecial Function Pin Setup PAO to 7 are used as input pins for analog Each bit can be set individually as an input by the port A input mode register PAIMD When they are used as analog input pins set the port A input mode register PAIMD to 1 Then the value of the port A input register PAIN is 1 By setting the control flag of the PAIMD register to 1 the through current is not occurred when input voltage is at intermediate level PotA IV 27 Chapter 4 Ports 4 8 2 Registers 7 6 5 4 3 2 1 0 PAIN PAIN7 PAIN6 PAINS PAINS PAIN2 PAIN1 Atreset X XX XXXXX PAIN Input data 0 Pin is Low Vss level Pin is High VDD level Port A input register PAIN x O3F2A R 7 6 5 4 3 2 1 0 PAIMD _ PAIMD7 PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMD0 At 00000000 PAIMD port analog n input pin selection 0 port 1 Analog n input pin Port A input control register PAIMD x O3F3A R W 7 6 5 4 3 2 1 0 PAPLUD PAPLUD7 PAPLUD6 PAPLUDS PAPLUD4 PAPLUDIPAPLUDO0
224. on struction II 16 Bus Interface 2 4 2 4 1 Chapter 2 CPU Basics Standby Function Overview This LSI has two sets of system clock oscillator high speed oscillation low speed oscillation for two CPU operating modes NORMAL and SLOW each with two standby modes HALT and STOP Power consumption can be decreased with using those modes Reset CPU operation mode STANDBY mode Interrupt NORMAL mode B OSC Halt 5 T XI Halt NORMAL OSC Oscillation XI Oscillation Interrupt E 3 1 HALT 0 j E OSC Oscillation3 Oscillation gt Program 4 Program 3 STOP mode IDLE OSC Oscillation XI Oscillation Program1 HALT mode Program 2 Interrupt 22050 SLOW XI Halt OSC Halt Pr gram s XI Oscillation Interrupt 3 SLOW mode E Osc Halt 3 Oscillation 5 4 Wait period for oscillation stabilization is inserted OSC High frequency oscillation clock XI Low frequency oscillation clock 32 kHz Figure 2 4 1 Transition Between Operation Modes Only 48 TQFP package type is activated at low speed oscillation Xl 48 pin SDIP and 44 pin QFP package type are activated only at high speed
225. op bit 2 bits Operation X 31 Chapter 10 Serial Interface 0 Parity bit is to detect wrong bits with transmission reception data Table 10 3 14 shows kinds of parity bit The SCONPE SCOPM1 to 0 flag of the SCOMD2 register set parity bit Table 10 3 14 Parity Bit of UART Serial Interface SCOMD2 register Parity bit Setup SCOPM1 SCOPMO 0 0 0 fixed to 0 Set parity bit to 0 0 0 1 fixed to 1 Set parity bit to 1 Control total number of 1 of bit and 0 L 0 character bit should be 0 1 1 Control the total number of 1 of bit and panty character bit should be even 1 none Do not add parity bit Status Transmission Control Setup The SCOBRKE flag of the SCOMD2 register generates the break status If SCOBRKE is set to 1 to select the break transmission all bits from start bits to stop bits transfer 0 Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be determined by the SCOORE SCOPEK and SCOFEF flag of the SCOCTR register Even one of those errors is detected the SCOERE flag of the SCOMD1 register is set to 1 The reception error flag is renewed at generation of the reception complete interrupt SCOIRQ The judgement of the received error flag should be operated until the next communication has finished
226. oscillation OSC Standby Functions II 17 Chapter 2 CPU Basics BHALT Modes HALTO HALT1 The CPU stops operating But both of the oscillators remain operational in HALTO and only the high frequency oscillator stops operating in HALT1 An interrupt returns the CPU to the previous CPU operating mode that is to NORMAL from HALTO to SLOW from HALT1 ESTOP Modes STOPO STOP1 The CPU and both of the oscillators stop operating Aninterrupt restarts the oscillators and after allowing time for them to stabilize returns the CPU to the previous CPU operating mode that is to NORMAL from or to SLOW from STOP1 Mode This mode executes the software using the low frequency clock Since the high frequency oscillator is turned off the device consumes less power while executing the software Mode This mode allows time for the high frequency oscillator to stabilize when the software is changing from SLOW to NORMAL mode To reduce power dissipation in STOP and HALT modes it is necessary to check the stability of both the output current from pins and port level of input pins For output pins the output level should match the external level or direction control should be changed to input mode For input pins the external level should be fixed This LSI has two system clock oscillation circuits OSC is for high frequency operation NORMAL mode and XI is for low frequenc
227. ow Base period set by timer 3 36 7 kHz 4 Base period set by timer 3 RMOUT output 1 3 duty Figure 5 9 3 Output Wave Form of RMOUT Output Pin Setup Procedure Description 1 Disable the remote control carrier 1 Set the RMOEN flag of the remote control output carrier output control register RMCTR to 0 RMCTR x 3F89 to disable the remote control carrier output bp3 RMOEN 0 2 Select the carrier output duty 2 Setthe RMDTYO flag of the RMCTR register to RMCTR x 3F89 1 to select 1 3 duty bp1 RMDTYO 1 3 Stop the counter 3 Set the flag of the timer 3 mode x 3F83 register TM3MD to stop the timer 3 counting bp4 20 4 Setthe remote control carrier output of 4 Setthe P1OUTO flag of the port 1 output the special function pin register P1OUT to 0 to set the output data P1OUT x 3F11 of P10 pin to O bpO P1OUTO 0 Set the P1OTCO flag of the port 1 output mode 9 register P1OMD to 1 to set P10 pin as a bpO 1 special function pin P1DIR x 3F31 Set the P1DIRO flag of the port 1 direction bpO P4DIRO 21 control register P1DIR to 1 for output mode 5 Select the normal timer operation 5 Setthe TM3PWM flag of the TM3MD register TM3MD x 3F83 to 0 to select normal timer operation bp3 TM3PWM 0 32 Remote Control Carrier Output Chapter 5 8 Timers Setup Procedure
228. pins Receive data input pins for serial interfaces 0 Pull up resistors can be selected by the POPLU register Select input mode by the PODIR register and serial input mode by the serial mode register SCOMD3 These can be used as normal pins when the serial interface is not used SBTO 22 VO P02 P05 Serial interface clock VO pins Clock VO pins for serial interfaces 0 The output configuration either CMOS push pull or n channel open drain can be selected Pull up resistors can be selected by the POPLU register Select clock for each communication mode by the PODIR register and serial mode register SCOMD3 These can be used as normal pins when the serial interface is not used TXD 20 Output SBOO UART transmission data output pin In the serial interface in UART mode this pin is configured as the transmission data output pin The output configuration either CMOS push pull or n channel open drain can be selected Pull up resistors can be selected by the POPLU resister Select output mode by the PODIR register and serial data output by serial 0 mode register 3 SCOMDS3 This can be used as normal pin when the serial interface is not used I 13 Pin Description Overview Chapter 1 Overview Table 1 3 5 Pin Function Summary 4 5 Name No 80 pin VO Other Function Function Description RXD 21 Input
229. processing flow when a second interrupt with a lower priority level xxxLV1 xxxLVO 10 arrives during the processing of one with a higher priority level xxxLV1 xxxLV0 00 IMO 1 00 Main program Set MIE IM1 0 11 Interrupt 1 generated z Accepted because IL IM and MIE 1 xxxLV1 0 00 1 0 00 Interrupt acceptance cycle Interrupt service routine 1 1 Interrupt 2 generated xxxLV1 0 10 2 pe IM1 0 11 Interrupt acceptance cycle 1 0 10 Cinterrupt service routine 2 RTI 0 11 Interrupt generated z Not accepted because IM IL xxxLV1 0 11 Parentheses indicate hardware processing 1 If during the processing of the first interrupt an interrupt request with an interrupt level IL numerically lower than the interrupt mask IM arrives it is accepted as a nested interrupt If IL 2 IM however the interrupt is not accepted 2 second interrupt postponed because its interrupt level IL was numerically greater than the interrupt mask IM for the first interrupt service routine is accepted when the first interrupt handler returns Figure 3 1 6 Processing Sequence for Maskable Interrupts Overview 11 Chapter 3 Interrupts Multiplex Interrupt When an MN101C45 series device accepts an interrupt it automatically disables acceptance of sub
230. pt enable flag 0 Disable interrupt 1 Enable interrupt 200 Interrupt level fla Lv1 LVO 9 The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 11 Serial interface 0 Interrupt Control Register SCOICR x 03FE8 R W 26 Registers Chapter 3 Interrupts A D Conversion Interrupt Control Register ADICR The A D conversion interrupt control register ADICR controls interrupt level of A D conversion interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag is set to level 3 ADLV1 ADLVO 1 the interrupt of its vector is disabled regardless of the interrupt request flag and the interrupt enable flag 7 6 5 4 3 2 1 0 AD AD _ _ _ _ Gated ADICR ADIE ADIR At reset 0 0 0 0 ADIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated ADIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt AD a Interrupt level fl vo teve tag The CPU has interrupt levels from 0 to 3 These flags set the interrupt level for interrupt request Figure 3 2 12 A D Conversion Interrupt Control Register ADICR x O3FEA R W Control Registers III 27 Chapter 3 Interrupts 3 3 External I
231. pull up resistor VO port Port A Input mode No pull up pull down resistor VO port Overview IV 3 Chapter 4 T O Ports 4 1 3 Control Registers Ports 0 to 2 ports 6 to 8 and A are controlled by the data output register PnOUT the data input register PnIN the I O direction control register PnDIR the pull up resistor control register PnPLU and the pull up pull down resistor control resister PRPLUD and registers PT OMD PAIMD FLOAT1 that control special function pin This I O control is valid at selection of the special function as well Table 4 1 2 shows the registers to control ports 0 to 2 ports 6 to 8 and Table 4 1 2 1 Port Control Registers List Register Address R W Function Page POOUT x 03F 10 R W Port 0 output register 6 x O3F20 Port 0 input register 6 5809 PODIR x 03F 30 R W Port 0 direction control register 6 x O3F40 R W Port 0 pull up resistor control register 6 P1OUT 11 R W Port 1 output register 10 X 03F21 1 input register 10 Port1 P1DIR 1 R W Port 1 direction control register 10 P1PLU X 03F41 R W Port 1 pull up resistor control register 10 P10MD x 03F39 R W Port 1 output mode register IV 11 P2OUT X 03F 12 R W Port 2 output register 15 Port2 P2IN X 03F22 2 i
232. put pins are at VDD level and the OSC1 and XI pins are unconnected 2 Parameters of IDD3 and IDD4 IDD5 are applied only to 48 TQFP package type Electrical Characteristics 1 21 Chapter 1 Overview Ta 40 C to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions MIN Unit Input pin 1 MMOD 8 Input high voltage 1 0 9 VDD VDD 9 Input low voltage 1 0 0 2 VDD Y 10 leakage current Vi 0 V to VDD 10 Input pin2 P20 P22 to P23 Schmitt trigger input 11 Input high voltage 0 8 12 Input low voltage VIL2 0 0 2 VDD X 13 Input leakage current ILk2 Vi 0 V to VDD 10 14 Input high current 30 100 300 55 Input 3 1 P21 Schmitt trigger input 15 Input high voltage VIH3 0 8 VDD VDD 16 low voltage VIL3 0 0 2 y 17 leakage current ILk3 Vi 0 V to 10 18 Input high current Input pin 3 2 P21 at used as ACZ 19 Input high voltage 1 VDHH Vpp 5 0 V 4 5 20 low voltage 1 Fig 1 5 5 Vss 3 5 21 Input high voltage 2 15 V 22 low voltage 2 Vss 0 5 23 Input leakage current Vi 0 V to 10 24 Input clamp current Ica ele ries i 0 V t 400 ACZ pins 25 Ri
233. r 3 3 1 4 Interrupt Flag Setup Set the baud rate timer by the TM3MD register register And set the flag to 1 to operate timer 3 Chapter 5 5 7 Serial interface transfer clock output Set the SCOSBOS flag of the SCOMD3 register to 1 to set the serial interface communication 13 Set the transfer data to the SCOTRB register And the serial interface communication is started 15 Operation X 43 Chapter 10 Serial Interface 0 Only timer 3 be used as baud rate timer For baud rate setup refer to Chapter 5 5 7 Serial Interface Transfer Clock Output Serial interface 0 is operated by setting the SCOSBOS or the SCOSBIS of the SCOMDS3 register to 1 The SCOSBOS flag or the SCOSBIS flag should be set after all conditions are set After that at transmission the communication is started by writing data to the SCOTRB When a register except the SCOTRB is written rewritten set the SCOSBOS the SCOSBIS flag to 0 in advance When the RXD connected for communication with 1 channel the TXD inputs outputs serial data The port direction control register PODIR should be set for switching input output The RXD pin can be used as a general port When the serial interface port is enabled if the SCOCE1 0 flag of the SCOMDO register
234. r more detailsd infomation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual The MN101C457 offers a choice of masked ROM version or user programmable EPROM version MN101CP427 101 457 101 427 512 512 Unit byte In this LSI manual the LSI functions are presented in the folowing order overview CPU basic functions interrupt functions port functions timer functions serial interface functions and other peripheral hardware functions Each section contains overview of function block diagram control register operation and setting example About This Manual 1 mManual Configuration Each section of this manual consists of a title summary main text key information precautions and warnings and references The layout and definition of each section are shown below Subtitle Chapter 2 Basic CPU Sub subtitle The smallest block in this manual 2 8 Reset 2 8 1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin P 27 is pulled to low Main text W Initiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low for at least four clock cycles NRST pin should be holded
235. ral function xxxLV Interrupt Level xxxlE Interrupt Enable xxxlR Interrupt Request Peripheral function Interrupt Leve Interrupt Enab xxxlR Interrupt Request Interrupt Block Diagram Chapter 3 Interrupts 3 1 3 Operation Processing Sequence For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing The program counter PC and processor status word PSW and handy addressing data HA are saved onto the stack and execution branches to the address specified by the corresponding interrupt vector An interrupt handler ends by restoring the contents of any registers used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was inter rupted Interrupt service routine Main program Interrupt request xxxIR DS Hardware processing flag cleared Save up PC PSW etc at head Interrupt 12 machine cycles 11 machine cycles Restart Restore PSW PC up etc RTI Figure 3 1 2 Interrupt Processing Sequence maskable interrupts Non maskable interrupts have priority over maskable ones Overview 5 Chapter 3 Interrupts Sources and Vector Addresses Here is the list of interrupt vector address and interrupt group Table 3
236. rdware branches to the address in the vector 25 m table Figure 3 1 5 Stack Operation interrupt Return Operation during interrupt acceptance An interrupt handler ends by restoring using the POP instruction and other means the contents of any registers used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was interrupted The following is the processing sequence after the RTI instruction 1 The contents of the PSW are restored from the stack SP 2 The contents of the program counter PC the return address are restored from the stack SP 1 to SP 3 3 The contents of the handy address register HA are restored from the stack SP 4 SP 5 4 The stack pointer is updated SP 6 SP 5 Execution branches to the address in the program counter The handy address register is an internal register used by the handy addressing function The hardware saves its contents to the stack to prevent the interrupt from interfering with operation of the function Registers such as data register address register are not saved so that PUSH instruction should be used to save data register or address register onto the stack if necessary 1 The address bp6 to 2 when program counter are saved to the stack are reserved Do not change by program 10 Overview Chapter 3 Interrupts iMaskable Interrupt Figure 3 1 6 shows the
237. register is set the smaller than the binary counter during the count operation the binary counter counts up to the overflow at first If the interrupt is enabled the timer interrupt request flag should be cleared before timer operation is started Even if the TMnEN flag of the timer is cleared during operation it does not stop until the next count clock Therefore during max 1 count clock after the TMnEM is cleared the binary counter cannot be initialized Operation V 11 Chapter5 8 Bit Timers 5 3 2 Setup Example Timer Operation Setup Example Timers 2 and 3 Timer function can be set by using timer 2 that generates the constant interrupt By selecting fs 4 at fosc 20 MHz as a clock source interrupt is generated every 250 clock cycles 100 us An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD x 3F82 bp4 TM2EN 20 TM2MD x SF82 bp3 2 0 3 Select the count clock source TM2MD 3 82 bp2 0 TM2CK2 0 001 4 Set the cycle of the interrupt generation 20 x 3F72 9 5 Set the interrupt level TM2ICR x 3FE6 bp7 6 TM2LV1 0 10 6 Enable the interrupt TM2ICR x 3FE6 bp1 21 1 2 Select the normal timer operation Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the counting of timer 2 Set the TM2PWM fl
238. rrupt request flag is set at the next count clock D When an interrupt request flag is set the binary counter is cleared to x 00 and restarts the counting E Even if the binary counter reaches the value of the compare register as the TM5CLRS flag is 0 nointerrupt request flag is set When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If fx is selected as the count clock source in timer 5 when the binary counter is read at operation uncertain value on counting up may be read To prevent this select the synchro nous fx as the count clock source But if the synchronous fx is selected as the count clock source CPU mode cannot return from STOP HALT mode If the compare register is set the smaller value than the binary counter s during the count operation the binary counter counts up to the overflow at first 8 Bit Free running Timer VII 9 Chapter 7 Time Base Timer 8 Bit Free running Timer 7 3 2 Setup Example Timer Operation Setup Timer 5 Timer 5 generates an interrupt constantly for timer function fs 4 fosc 20 MHz is selected as a clock source to generate an interrupt every 250 dividing 100 us An example setup procedure with a description of each step is shown below
239. rrupts BExternal Interrupt 1 Control Register IRQ1ICR The external interrupt 1 control register IRQ1ICR controls interrupt level of external interrupt 1 active edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 When the interrupt level flag for external interrupt is set to level IRQ1LV1 IRQ1LVO0 1 the interrupt of its vector is disabled regardless of the external interrupt request flag and the external interrupt enable flag 7 6 5 1 0 IRQ1 LV1 LVO REDG1 IRQ1IE IRQ1IR 1 At reset 000 00 IRQ1IR External interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQ1IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDG1 External interrupt active edge flag 0 Falling edge 1 Rising edge IRQ1 IRQ1 Interrupt level flag LV1 LVO for external interrupt The CPU has interrupt levels from 010 3 These flags set the interrupt level for interrupt request Figure 3 2 3 External Interrupt 1 Control Register IRQ1ICR x O3FES R W 18 Control Registers WExternal Interrupt 2 Control Register IRQ21CR Chapter Interrupts The external interrupt 2 control register IRQ2ICR controls interrupt level of external interrupt 2 active edge interrupt enable
240. ruction set This LSI has internal ROM 16 KB and RAM 512 bytes Peripheral functions include 4 external interrupts 8 internal interrupts including NMI 5 timer counters 1 set of serial interface A D converter watchdog timer buzzer output and remote control output The configura tion of this microcontroller is well suited for application such as a system controller in a VCR selection timer CD player or MD 48 pin TQFP package type has two oscillation systems max 20 MHz 32 kHz contained on the chip the system clock can be switched to high speed oscillation NORMAL mode or to low speed oscillation SLOW mode The system clock is generated by dividing the oscillation clock For example in case of NORMAL mode when the oscillation source fosc is 8 MHz minimum instruc tions execution time is for 250 ns and when fosc is 20 MHz it is 100 ns 3 types of package are available 42 pin SDIP 44 pin QFP and 48 pin TOFP 1 3external interrupts for other types of package except 48 pin TQFP package type 1 1 2 Product Summary This manual describes the following models of the MN101C457 series These products have same peripheral functions Table 1 1 1 Product Summary Model ROM Size RAM Size Classification 1010457 16 512 bytes Mask ROM version MN101CP427 16 KB 512 bytes EPROM version 1 2 Overview Chapter 1 Overview 1 2 Hardware Functions CPU Core MN101C Core LOAD STORE architecture 3 s
241. s TAD 2 A D interrupt ADIRQ Figure 11 3 1 Operation of A D Conversion To read the value of the A D conversion A D conversion should be done several times to prevent noise error by confirming the match of level by program or by using the average value Operation XI 9 Chapter 11 A D Converter 11 3 1 Setup Pins of A D Converter Setup Input pins for A D converter is selected by the ANCH2 to 0 flag of the ANCTRO register Table 11 3 1 Input Pins of A D Converter Setup ANCHS2 51 ANCHSO A D pin 0 ANO pin 1 AN1 pin 0 AN2 1 AN3 0 j 1 AN5 pin 0 AN6 i 1 AN7 pin Clock of A D Converter Setup The A D converter clock is set by the ANCK1 to 0 flag of the ANCTRO register Set the A D converter clock TAD more than 800 ns and less than 15 26 us Table 11 3 2 shows the machine clock fosc fx fs and the A D converter clock TAD calculated as fs fosc 2 fx 4 Table 11 3 2 A D Conversion Clock and A D Conversion Cycle A D conversion cycle TAD ANCK1 ANCKO A D conversion clock at oscillation for high speed a low at fosc 20 MHz at fosc 8 38 MHz at fx 32 768 kHz 6 2 200 00 477 33 244 14 us unusable unusable unusable 400 00ns 488 28 us unusable 394 GNS unusable fs 8 800 00 ns 1 91 us 976 56 us 1 unusable fK x 2 15 26
242. s selected as the count clock source in timer 2 when the binary counter is read at operation uncertain value on counting up may be read To prevent this select the synchro nous fx as the count clock source In this case the timer 2 counter counts up in synchroniza tion with system clock therefore the correct value is always read But if the synchronous fx is selected as the count clock source CPU mode cannot return from STOP HALT mode 2 22 Operation 13 Chapter 5 8 Timers 5 4 8 Bit Event Count 5 4 1 Operation Event count operation has 2 types TMnIO input and synchronous TMnIO input can be selected as the count clock 8 Bit Event Count Operation Event count means that the binary counter TMnBC counts the input signal from external to the TMnlO pin If the value of the binary counter reaches the setting value of the compare register TMnOC inter rupts can be generated at the next count clock Table 5 4 1 Event Count Input Clock Timer 2 Timer 3 2 input input Event input P13 Synchronous Synchronous 210 input input iCount Timing of TMnIO Input Timers 2 and 3 When TMnlO input is selected TMnIO input signal is directly input to the count clock of the timer n The binary counter counts up at the falling edge of the TMnIO input signal Compare M register ae counter Cmpare match signal Interrupt request flag
243. s16 bp BCLR abs16 bp BTST abs16 bp 8 abs16 mov 8 20510 CBEQ 8 abs16 d7 11 8 abs16 d7 11 TBZ abs16 bp d7 TBZ abs16 bp d11 TBNZ abs16 bp d7 TBNZ abs16 bp d11 Ver2 1 2001 03 26 Instruction Map XII 29 101 457 LSI User s Manual April 2001 1st Edition Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES E U S A SALES OFFICE Panasonic Industrial Company PIC New Jersey Office 2 Panasonic Way Secaucus New Jersey 07094 Tel 201 392 6173 Fax 201 392 4652 Milpitas Office 1600 McCandless Drive Milpitas California 95035 Tel 408 945 5630 Fax 408 946 9063 Chicago Office 1707 N Randall Road Elgin Illinois 60123 7847 Tel 847 468 5829 Fax 847 468 5725 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee Georgia 30174 Tel 770 338 6940 Fax 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 Tel 619 503 2940 Fax 619 715 5545 CANADA SALES OFFICE Panasonic Canada Inc PCI 5700 Ambler Drive Mississauga Ontario LAW 2T3 Tel 905 624 5010 Fax 905 624 9880 GERMANY SALES OFFICE Panasonic Industrial Europe G m b H PIEG Munich Office
244. se quent interrupts with the same or lower priority level When the hardware accepts an interrupt it copies the interrupt level xxxLVn for the interrupt to the interrupt mask IM in the PSW As a result subse quent interrupts with the same or lower priority levels are automatically masked Only interrupts with higher priority levels are accepted The net result is that interrupts are normally processed in decreasing order of priority It is however possible to alter this arrangement 1 To disable interrupt nesting Reset the MIE bit in the PSW to 0 Raise the priority level of the interrupt mask IM in the PSW 2 To enable interrupts with lower priority than the currently accepted interrupt Lower the priority level of the interrupt mask IM in the PSW Multiplex interrupts are only enabled for interrupts with levels higher than the PSW interrupt mask level IM It is possible to forcibly rewrite IM to accept an interrupt with a priority lower than the interrupt being processed but be careful of stack overflow Do not operate the maskable interrupt control register xxxICR when multiple interrupts are enabled If operation is necessary first clear the PSW MIE flag to disable interrupts aan x 12 Overview Chapter 3 Interrupts Figure 3 1 7 shows the processing flow for multiple interrupts interrupt 1 xxxLV1 xxxLV0z 10 and interrupt 2 xxxLV1 xxxLV0 00 Main program 0
245. set the control flag of the port 0 direction control register PODIR to 0 and read the value of the port 0 input register To output data to pin set the control flag of the port 0 direction control register PODIR to 1 and write the value of the port 0 output register POOUT Each pin can be set individually if pull up resistor is added or not by the port 0 pull up resistor control register POPLU Set the control flag of the port 0 pull up resistor control register POPLU to 1 to add pull up resistor At reset the input mode is selected and pull up resistors are disabled high impedance output ilSpecial Function Pin Setup POO to P02 are used as I O pin for serial interface 0 as well POO is output pin of the serial interface 0 transmission data and UART transmission data When the SCOSBOS flag of the serial interface 0 mode register SCOMD3 is 1 POO is serial data output pin is the input pin of the serial interface 0 reception data and UART reception data When the SCOSBIS flag of the serial interface 0 mode register 3 SCOMD3 is 1 is serial data input pin PO2 is I O pin of the serial interface 0 clock When the SCOSBTS flag of serial interface 0 mode register 3 SCOMD3 is 1 2 is serial interface clock output pin POO can be selected as either an push pull output or Nch open drain output by the SCOSBOM and the SCOSBTM of the serial interface 0 mode register 3 SCOMD3 t
246. sing time trs 30 26 Falling time ffs icu 30 BS I 22 Electrical Characteristics Chapter 1 Overview trs gt lt tis Input voltage level 1 Input Input voltage level 2 Output Figure 1 5 5 AC Zero Cross Detector Electrical Characteristics 1 23 Chapter 1 Overview 40 to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions MIN Unit Input pin4 PA 0 to PA 7 27 hput high voltage 1 VIH5 0 8 VDD 28 Input high voltage 2 VIH6 4 5 V to 5 5 V 0 7 VDD VDD 29 low voltage 1 VIL5 0 0 2 30 low voltage 2 ViL6 4 5 V to 5 5 V 0 0 3 31 Input leakage current ILK5 V 0 V to VDD 2 32 Input high current 5 y 30 100 300 33 Input low current ILs 22 80 180 400 5 P27 NRST 34 Input high voltage VIH7 0 9 VDD 35 low voltage 7 0 0 2 36 Input high current 30 100 300 VO to P10 to P14 37 high voltage VIH8 0 8 38 low voltage VIL8 0 0 2 39 leakage current Vi 0 V to VDD 10 40 Input high current Y 30 100 300 41 Output high voltage 5 0 V lou
247. size half byte bit II 11 Overview Chapter 2 CPU Basics 2 2 Memory Space 2 2 1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable writable data In addition to these peripheral resources such as memory mapped special registers are allocated In single chip mode the system consists of only internal memory MMOD pin should be fixed to L level or H level Do not change the setup of MMOD pin after reset II 12 Memory Space Chapter 2 CPU Basics 2 2 2 Single chip Mode In single chip mode the system consists of only internal memory This is the optimized memory mode and allows construction of systems with the highest performance The single chip mode uses only internal ROM and internal RAM The MN101C series devices offer up to 12 KB of RAM and up to 224 KB of ROM x 00000 Abs 8 addressing 256 bytes access area Internal 512 bytes 00100 RAM space Data x 001FF A x 03F00 2 256 bytes Special function registers A x 04000 A Interrupt 128 D vector table x 04080 Subroutine 64 bytes vector table 16 KB Y Internal 040 0 ROM space Instruction code table data x 07FFF MMOD L Figure 2 2 1 Single chip Mode Differs depending upon the model 14 Table 2 2 1 Internal ROM Internal RAM Table 2 2 1 Internal ROM Internal RAM Internal RAM Internal ROM
248. stem clock WDEN 0 The watchdog timer clear should be inserted in BSET WDCTR WDEN the main routine with the same cycle and to WDEN 1 be the set cycle Operate the watchdog timer again after it is stopped Upper 2 bits of the counter are cleared The upper 2 bits of the watchdog timer are cleared when the WDEN flag of the watchdog timer control register is set to 0 Therefore depending on the clear timing the watchdog timer may be reset at 1 4 x watchdog timer frequency If the WDEN flag is to be repeatedly cleared and set at regular intervals those operations should be performed within 1 4 of the watchdog timer frequency Operation VIII 7 Chapter 8 Watchdog Timer Binterrupt Service Routine Setup Setup Procedure Description 1 Set the watchdog interrupt service routine NMICR x 03FE1 TBNZ NMICR WDPRO If the watchdog timer overflows the non maskable interrupt is generated Confirm that the WDIR flag of the non maskable interrupt control register NMICR is 1 on the interrupt service routine and manage the suitable execution Proper operation right before the WDOG interrupt is not guaranteed Therefore if the WDOG interrupt is generated initialize the system 8 Operation Chapter 9 Buzzer Chapter9 Buzzer 9 1 Overview This LSI has a buzzer It can output the square wave havin
249. structions Instruction decoder Decodes the instruction queue sequentially generates the control signals needed for instruction execution and executes the instruction by controlling the blocks within the chip Instruction execution controller Controls CPU block operations in response to the result decoded by the instruction decoder and interrupt requests ALU Executes arithmetic operations logic operations shift operations and calculates operand addresses for register relative indirect addressing mode Internal ROM RAM Assigned to the execution program data and stack region Address register Stores the addresses specifying memory for data transfer Stores the base address for register relative indirect addressing mode Data register Holds data for operations Two 8 bit registers can be connected to form a 16 bit register Interrupt controller Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing Bus controller Controls connection of CPU internal bus and CPU external bus Internal peripheral functions Includes peripheral functions timer serial interface A D converter etc Peripheral functions vary with model Figure 2 1 1 Block Diagram and Function Overview Chapter 2 CPU Basics 2 1 2 CPU Control Registers This LSI locates the peripheral circuit registers in memory space x 03F00 to x O3FFF with memory
250. t STOP mode and counts system clock fs as a clock source from the initial value x 0000 The oscillation stabilization wait time is set by the oscillation stabilization control register DLYCTR After the oscillation stabilization wait counting is continued as a watchdog timer VIII 2 Overview Chapter 2 2 5 Reset Chapter 8 Watchdog Timer 8 2 Control Registers The watchdog timer is controlled by the watchdog timer control register WDCTR And the cycle of the watchdog timer period is set in ROM option amp Chapter1 1 6 1 Rom option mWatchdog Timer Control Register WDCTR WDCTR WDEN at reset 0 Watchdog timer 0 Watchdog timer is cleared disabled 1 Watchdog timer is enabled Figure 8 2 1 Watchdog Timer Control Register WDCTR x 03F02 R W Control Registers VII 3 Chapter 8 Watchdog Timer 8 3 Operation 8 3 1 Operation The watchdog timer counts system clock fs as a clock source If the watchdog timer overflows the watchdog interrupt WDIRQ is generated as an non maskable interrupt NMI At reset the watchdog timer is stopped The watchdog timer control register WDCTR sets if the watchdog timer is enabled or disabled If the watchdog interrupt WDIRQ is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system
251. t count clock and TMBBC is cleared to x 00 to restart counting VII 10 8 Bit Free running Timer Chapter 7 Time Base Timer 8 Bit Free running Timer If the interrupt is enabled the timer 5 interrupt request flag should be cleared before timer 5 operation is started 2 If the TM5CLRS flag of the TM5MD register is set to 0 TM5BC can be initialized in every rewriting of 5 register but in that state the timer 5 interrupt is disabled If the timer 5 interrupt should be enabled set the TM5CLRS flag to 1 after rewriting the TM5OC register On the timer 5 clock source selection either the time base timer output or the time base timer synchronous output is selected the clock setup of time base timer is necessary 8 Bit Free running Timer VII 11 Chapter 7 Time Base Timer 8 Bit Free running Timer 7 4 Time Base Timer 7 4 1 Operation Base Timer Time Base Timer The Interrupt is constantly generated Table 7 4 1 shows the interrupt generation cycle in combination with the clock source Table 7 4 1 Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle fosc X 1 28 12 8 us fosc 20 MHz fosc X 1 2 25 6 us fosc X 1 279 51 2 us fosc X 1 23 409 6 us fosc X 1 27 15 2 us fosc X 1 2 30 5 us fosc 8 39 MHz fosc X 1 29 61 0 us fosc X 1 210 122 0 us fosc X 1 2 976 4 us VII 12 Time Base Timer Chapter 7 Time Base Ti
252. t flag after the switching the interrupt edge is highly recommended t Chapter 3 3 1 4 Interrupt flag setup Pull up the external interrupt pin in advance is also recommended a If the interrupt request flag is set to 1 at the switching the interrupt edge an interrupt is 34 External Interrupts Chapter Interrupts 3 3 5 Noise Filter WNoise Filter External interrupts 0 101 Noise filter reduces noise by sampling the input waveform from the external interrupt pins IRQO IRQ1 Its sampling cycle can be selected from 4 types 15 22 15 28 fs 2 15 219 iNoise Remove Selection External interrupts 0 to 1 Noise remove function can be used by setting the NFnEN flag of the noise filter control register NFCTR to 1 Table 3 3 3 Noise Remove Function NFnEN IRQO input P20 IRQ1 input P21 0 IRQO Noise filter OFF IRQ1 Noise filter OFF 1 IRQO Noise filter ON IRQ1 Noise filter ON BSampling Cycle Setup External interrupts 0 and 1 The sampling cycle of noise remove function can be set by the NFnSCK 1 0 flag of the register Table 3 3 4 Sampling Cycle Time of Noise Remove Function NEGRU Sampling High frequency oscillation cycle at fosc 20 MHz at fosc 8 MHz 0 fs 2 2 5 MHz 400 ns 1 MHz 1 us 1 16 28 39 06 kHz 25 60 us 15 62 kHz 64 us 0 fs 2 19 53 kHz 51 20 us 7 81 kHz 128 us 1 16 219 9 77 kHz 102 40 us 3
253. t the control flag of the port 8 direction control register P8DIR to 1 and write the value of the port 8 output register Each pin can be set individually if pull up resistor is added or not by the port 8 pull up resistor control register P8PLU Set the control flag of the port 8 pull up resistor control register PBPLU to 1 to add pull up resistor At reset the P80 to P87 input mode is selected and pull up resistors are disabled high impedance output iSpecial Function Pin Setup P80 to P87 are used as LED driving pins as well IV 24 8 Chapter 4 Ports Low Vss level High level Pin is Low Vss level Pin is High VDD level mode selection Output mode Pull up resistor selection 4 7 2 Registers 7 6 5 4 3 2 1 0 P8OUT7 6 P80UTS P8OUT2 PSOUT1 Atreset 00000000 P8OUT Output data 0 1 Port 8 output register PBOUT x 03F18 R W 7 6 5 4 3 2 1 0 P8IN P8IN7 P8IN6 5 P8IN4 2 P8IN1 P8INo Atreset P8IN Input data 0 1 Port 8 input register P8IN x O3F28 R 7 6 5 4 3 2 1 0 P8DIR 80 7 6 5 P8DIR4 P8DIR3 PSDI
254. t the interrupt level SCOICR x 03FE8 bp7 6 SCOLV1 0 10 11 Enable the interrupt SCOICR x 3FE8 bp1 SCOIE 21 12 Set the baud rate timer 13 Set the serial interface communication SCOMDS x 3F53 bp1 SCOSBIS 1 14 Start the serial interface reception Received data Input to TXD Set the PODIRO flag of the PODIR register to 0 to set the TXD pin to input mode Set the POPLUO flag of the POPLU register to add pull up resistor to the TXD pin Select the interrupt level by the SCOLV1 0 flag of the serial interface 0 interrupt control register SCOICR Set the SCOIE flag of the SCOICR register to 1 to enable the interrupt request If any interrupt request flag had already been set clear it t Chapter 3 3 1 4 Interrupt Flag Setup Set the baud rate timer by the TM3MD register TM3OC register And set the flag to 1 to operate timer 3 Set the SCOSBIS flag of the SCOMDS register to 1 to set the serial interface communication After start bit is received by inputting serial interface data from the TXD pin the received data is stored to the serial interface transmission reception shift register SCOTRB When the reception has completed the serial interface 0 interrupt SCOIRQ is generated then the received data is stored to the received buffer SCORXB When the TXD RXD pin are connected for communication with 1 c
255. t to IM1 IMO and interrupts whose mask levels are the same or lower are rejected during the accepted interrupt processing Table 2 1 3 Interrupt Mask Level and Interrupt Acceptance Interrupt mask level Priority Acceptable interrupt levels IM1 IMO Mask level 0 0 0 High Non maskable interrupt NMI only Mask level 1 0 1 NMI Level 0 Mask level 2 1 0 NMI Level 0 to 1 Mask level 3 1 1 Low NMI Level 0 to 2 Interrupt Enable MIE Maskable interrupt enable flag MIE enables disables acceptance of maskable interrupts by the CPU s internal interrupt acceptance circuit A 1 enables maskable interrupts a 0 disables all maskable inter rupts regardless of the interrupt mask level IM1 IMO setting in PSW This flag is not changed by interrupts Overview 9 Chapter 2 CPU Basics 2 1 8 Addressing Modes This LSI supports the nine addressing modes Each instruction uses a combination of the following addressing modes 1 Register direct 2 Immediate 3 Register indirect 4 Register relative indirect 5 Stack relative indirect 6 Absolute 7 RAM short 8 1 short 9 Handy These addressing modes are well suited for C language compilers All of the addressing modes can be used for data transfer instructions In modes that allow half byte addressing the relative value can be specified in half byte 4 bit increments so that instruction length can be shor
256. t units in the same way as RAM 5 0 P61 gt gt P01 RXD SBIO P62 Port 0 4 P02 SBTO Beale gt P06 BUZZER is Port 6 P65 gt 66 6 5 P67 gt 4 P10 RMOUT 1 4 9 12 210 P70 4 prii Port 7 lt gt P14 TM4IO LEDO P80 LED1 P81 gt 201 0 gt gt P21 IRQ1 ACZ fens cas Port 2 gt P22 RQ2 LED4 P84 gt Port 8 P23 IRQ3 LED5 P85 7 9 P27 NRST LED6 P86 LED7 P87 amp e AN1 PA1 AN2 PA2 AN3 PA3 AN4 PA4 8 Port A AN5 PA5 e AN6 PA6 AN7 PA7 1 P71 is not allocated to 42 SDIP and 44 QFP package types 2 P70 is not allocated to 42 SDIP package type Figure 4 1 1 1 Port Functions IV 2 Overview Chapter 4 Ports 4 1 2 Port Status at Reset Table 4 1 1 1 Port Status at Reset Single chip mode Port Name VO mode Pull up Pull down resistor VO port special functions Port 0 Input mode No pull up resistor VO port Port 1 Input mode No pull up resistor VO port Port 2 Input mode No pull up resistor VO port Port 6 Input mode No pull up resistor VO port Port 7 Input mode No pull up pull down resistor VO port Port 8 Input mode No
257. tage 2 ViH14 00 4 5 V to 5 5 V 0 7 VDD VDD 62 low voltage 1 ViL13 0 0 2 VDD 63 Input low voltage 2 VIL14 4 5 V to 5 5 V 0 0 3 64 leakage current ILK13 V 0 V to VDD 10 65 Input high current M 30 100 300 id 66 Output high voltage VOH13 5 0 V 0 5 mA 4 5 67 Output low voltage VoL13 5 0 V loL 15 mA 1 0 3 70 to P71 are not allocated to 42 501 package type P71 is not allocated to 44 pin QFP package type Electrical Characteristics 1 25 Chapter 1 Overview 1 5 4 A D Converter Characteristics Ta 40 C to 85 C 2 0 V 2 7 V to 5 5 V Vss 0 V EPROM vers is in Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Nondinearity error 1 t3 5 0 V Vss 0 V 3 Differential non linearity TAD 800 ns 5 error 1 E LSB 4 Non linearity error 2 5 VDD 5 0 V Vss 0 V 5 Differential non linearity fosc 32 kHz 1 error 2 6 Zero transition voltage 5 0 V Vss 0 V 30 100 TAD 800 ns i 7 Full scale transition voltage 30 100 8 TAD 800 ns 9 6 A D conversion time 9 32 kHz 71 183 Hs 10 fosc 8 MHz 1 0 36 Sampling time 11 fx 32 kHz 71 30 5 12 Analog input voltage Vss V 13 Analog input leakage VADIN 0 V to 5 0 V 2 current unselected channel 1 Applied only to 48 pin TQFP package type 1 26 Electrical Characteristi
258. tage pipeline Half byte instruction set Handy addressing Memory addressing space is 256 KB Minimum instruction execution time High speed mode 0 10us 20MHz 4 5 V to 5 5 V 0 238 us 8 39 MHz 2 7 V to 5 5 V 0 477 us 4 19 MHz 2 0 V to 5 5 V Low speed mode 12515 32kHz 2 0 V to 5 5 4 Operation modes NORMAL mode High speed oscillation SLOW mode Low speed oscillation HALT mode STOP mode Memory modes Single chip mode Internal ROM 2 16KB Internal RAM 2 512 bytes 1 EPROM vers is 2 7 V to 5 5 V 2 Differs depending upon the model t Chapter 1 1 1 2 Product Summary 3 1 byte of internal ROM is reserved for ROM option t Chapter 1 1 6 1 ROM Option 4 Provided only for 48 pin TQFP package type Hardware Functions I 3 Chapter 1 Overview Interrupts 8 Internal interrupts lt Non maskable interrupt NMI gt Incorrect code execution interrupt and Watchdog timer interrupt lt Timer interrupts gt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt Time base interrupt lt Serial interface interrupts gt Serial interface 0 interrupt Synchronous Half duplex UART lt A D interrupt gt A D converter interrupt 4 External interrupts 3 external interrupts for other package types except 48 pin TQFP package type IRQO Edge selectable With Without noise filter IRQ1 Edge selectable With Without noise filter AC zero
259. tchdog timer frequency WDSEL1 WDSEL2 Dem 8 0 NSSTRT Switch for oscillation control at reset released ON Start with the low speed oscillation Do not switch on at 101 45 OFF Start with the high speed OSC oscillation EPROM Version XII 15 Chapter 12 Appendices 12 3 Special Function Registers List Address X 3F00 Register Bit Symbol Initial Value Description Reserved Bit 5 Reserved Bit 4 Bit 3 Reserved STOP HALT 0 0 0 0 0 0 0 Set always 0 Set always 0 STOP Set always 0 transition request HALT transition request Oscillation Control X 3F01 MEMCTR IOW1 IOW0 IVBA Reserved Reserved IRWE Reserved Reserved 1 1 0 0 1 0 1 1 Wait Setup Interrupt Vector Address Set always 0 Set always 1 Interrupt request flag Set always 11 X 3F02 WDEN 0 WDT Activation X 3F03 DLYCTR BUZOE BUZCK1 BUZCKO DLYS1 DLYSO 0 X X 0 0 Enable Buzzer Output Buzzer Output Frequency Setup Oscillation Stabilization Wait Cycle Setup X 3F10 POOUT6 POOUT2 POOUT1 POOUTO 0 0 0 0 Port 0 output data Port 0 output X 3F11 1 0 4 P1OUTS3 P10UT2 P10UT1 P1OUTO 0 0 0 0 0 Port 1 Output Data X 3F12 2 7
260. ter Handy addressing reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combining handy addressing with absolute addressing will reduce the code size For transfer data be tween memory 7 addressing modes register indirect register relative indirect stack relative indirect absolute RAM short I O short handy can be used For operation instruction register direct and imme diate can be used Refer to instruction s manual for the MN101C series This LSI is designed for 8 bit data access It is possible to transfer data in 16 bit increments with odd or even addresses II 10 Overview Chapter 2 CPU Basics Table 2 1 4 Addressing Modes Effective address Explanation Directly specifies the register Only internal registers can be specified Directly specifies the operand or mask value appended to the instruction code 15 0 Addressing mode Dn DWn An SP PSW imm4 imm8 imm16 Register direct Immediate Register indirect 416 An Register relative indirect d4 PC branch instructions only d7 PC 1 branch instructions on d d11 PC branch instructions on d12 PC 1 branch instructions on d d16 PC l branch instructions only Stack relative indirect d8 SP d16 SP Absolute abs8 abs12 abs16 i abs18 1 branch instructions only RAM short short An d16 17 0H PC d4 7 ____
261. the 2nd trans mission and after At synchronous serial data transmission as the SCOSTE flag 1 High level after transmission Normal operation at synchronous mode Start condition 5 Shift register output POO H output control Source clock fs 2 fs 4 fs 16 Timer 3 output Transfer clock At UART transmission as the SCOSTE flag 1 Error operation at UART mode POO SBOO TXD X y Start bit Shift register output A 4 POO H output control UART clock Transfer clock Operation X 33 Chapter 10 Serial Interface 0 Other Control Flags The following flags need not to be set at UART communication Table 10 3 16 Other Control Flags Register Flag Detail SCOMDO SCOLNG2 to 0 Selection ot the transfer bit count automatically set SCOMD 1 SCOCKM Selection of the 1 8 division automatically set SCOSBTS Selection of the SBT pin s function SCOMD3 SCOSBTM Selection of the SBT pin s style The following items are the same to clock synchronous serial interface Reference as follows BFirst Transfer Bit Setup Refer to X 13 iTransfer Bit Count and First Transfer Bit Refer to X 15 Received Data Buffer Refer to X 15 Bit Count and First Transfer Bit Refer to X 15 EBUSY Flag Operation Refer to X
262. the value that baud rate comes to 300 bps 10 Table 10 3 18 At that time the timer 3 binary counter TM3BC is initialized to 00 Set the flag of the TM3MD register to 1 to start timer 3 TMSBC counts up from x 00 Timer output is the clock of the serial interface 0 at transmission and reception For the compare register setup value and the serial interface operation setup refer to chapter 10 Serial Interface 0 26 Serial Interface Transfer Clock Output 5 8 Cascade Connection 5 8 1 Operation Cascading timer 2 and 3 form a 16 bit timer 8 Bit Timer Cascade Connection Operation Timer 2 Timer 3 Chapter 5 8 Bit Timers Timer 2 and timer 3 are combined to be a 16 bit timer Cascading timer is operated at clock source of timer 2 which are lower 8 bits Table 5 8 1 Timer Functions at Cascade Connection Timer 2 Timer 3 16 Bit Interrupt source TM3IRQ Timer operation Event count 20 input Timer pulse output output PWM output 5 Serial interface transfer clock output output Remote control carrier output fs Clock source Be fx TM2IO input fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 Cascade Connection 27 Chapter 5 8 Timers At cas
263. tialize a digital clock Time Base Timer VII 13 Chapter 7 Time Base Timer 8 Bit Free running Timer 7 4 2 Setup Example Timer Operation Setup Time Base Timer Time base timer generates an interrupt constantly in the selected interrupt cycle The interrupt genera tion cycle is as fosc 1 213 as 0 976 ms fosc 8 39 MHz for generation interrupts An example setup procedure with a description of each step is shown below Setup Procedure Description Select the clock source TM5MD x 3F88 bpO TM5CKO 1 0 Select the interrupt generation cycle TM5MD x 3F88 bp6 4 TMBIR2 0 100 Set the interrupt level TBICR 7 bp7 6 TBLV1 0 01 Enable the interrupt TBICR x 3FE7 bp1 TBIE 1 Select fosc a clock source by TM5CKO flag of the timer 5 mode register TM5MD Select the selected clock 1 2 as an interrupt generation cycle by the TM5IR2 0 flag of the TM5MD register Set the interrupt level by the TBLV1 0 flag of the time base interrupt control register TBICR If any interrupt request flag had already been set clear it Set the TBIE flag of the TBICR register to 1 to enable the interrupt e Chapter 3 3 1 4 Interrupt Flag Setup the above steps 1 2 can be set at once When the selected interrupt generation cycle has passed the interrupt request flag of the time base interrupt control register TBICR is set to 1
264. tion wait time 201211 DHS DY flag of the watchdog timer control register WDCTR to 0 to stop the watchdog timer opera tion before transition to HALT mode HALT mode the watchdog timer count won t stop If it should be stopped set the tion does not stop after it operates as a counter for oscillation stabilization waiting at recover If the watchdog timer need not to detect errors set the WDEN flag of the watchdog timer control register WDCTR to 0 to stop the watchdog timer before CPU mode is switched to STOP mode When CPU mode is switched to STOP mode during the watchdog timer operation the opera 6 Operation Chapter 8 Watchdog Timer 8 3 2 Setup Example The watchdog timer detects errors On the following example the watchdog timer period is set to 2 x system clock in ROM option An example setup procedure with a description of each step is shown below Binitial Setup Program Watchdog Timer Initial Setup Example Setup Procedure Description 1 Start the watchdog timer operation 1 Setthe WDEN flag of the WDCTR register to WDCTR x 03F02 start the watchdog timer operation 1 Routine Program Watchdog Timer Constant Clear Setup Example Setup Procedure Description 1 Set the constant watchdog timer clear 1 Clear the watchdog timer under the 1 4 cycle BCLR WDCTR WDEN of 2 8 x sy
265. to input mode If needed pull up resistor should be added t Chapter 4 Ports Select the TM4IO input as a clock source by the 2 0 flag of the register Set the interrupt generation cycle to the timer 4 compare register 4 The set value should be 4 because the counting is 5 times Set the interrupt level by the TM4LV1 0 flag of the timer 4 interrupt control register TM4ICR If any interrupt request flag had already been set clear it Chapter 3 3 1 4 Interrupt Flag Setup 16 Bit Event Count VI 15 Chapter 6 16 Bit Timer Setup Procedure Description 7 Enable the interrupt 7 Set the 4 flag of the TM4ICR register to TMAICR x 3FEF 1 to enable interrupt bp1 1 8 Start the event count 8 Set the TM4EN flag of the TM4MD register to TM4MD x 3F84 1 to start timer 4 1 Every time TM4BC detects the falling edge of TM4IO input TM4BC counts up x0000 When 4 reaches the setting value of the TM4OC register the timer 4 interrupt request flag is set at the next count clock then the value of TM4BC becomes x 0000 and counting up is restarted VI 16 16 Bit Event Count Chapter6 16 Timer 6 5 16 Bit Timer Pulse Output 6 5 1 Operation TMAIO pin can output a pulse signal with any frequency WOperation of 16 Bit Timer Pulse Output Timer 4 The timers can output 2 x cycle signal compar
266. trigger source The other count timing is same to the count timing of the timer operation When the binary counter is used as a free counter that counts x 0000 to x FFFF set the compare register to x FFFF If a capture trigger is generated before the value of the input capture register is read the value of the input capture register can be rewritten 16 Bit Timer Capture VI 25 Chapter 6 16 Bit Timer 6 7 2 Setup Example Capture Function Setup Example Timer 4 Pulse width measurement is enabled by storing the value of the binary counter to the capture register at the interrupt generation edge of the external interrupt 0 input signal with timer 4 The interrupt generation edge is specified to be the rising edge An example setup procedure with a description of each step is shown below interrupt interrupt External interrupt IRQO input lt _ gt Pulse width to be measured Figure 6 7 2 Pulse Width Measurement of External Interrupt 0 Setup Procedure Description 1 Stop the counter TMAMD x 3F84 bp6 TM4EN 20 2 Select the count clock source x 3F84 bp2 0 TM4CK2 0 000 3 Select the capture trigger generation interrupt source TM4MD x 3F84 bp4 3 51 0 01 4 Select the interrupt generation active edge IRQOICR x 3FE2 bp5 REDGO 1 5 Select the normal timer operation TM4MD x 3F84 bp5 TM4PWM 0 6
267. trol Carrier Output Timer 3 Remote control carrier pulse is based on output signal of timer 3 Duty cycle is selected from 1 2 1 3 RMOUT P10 outputs remote control carrier output signal Base period set by timer die Base timer output RMOUT 1 2 duty RMOUT 1 3 duty Figure 5 9 1 Duty Cycle of Remote Control Carrier Output Signal iCount Timing of Remote Control Carrier Output Timer 3 Base timer output Output ON RMOEN Output OFF 1 P1OMDO 0 RMOUT 1 3 duty A Figure 5 9 2 Count Timing of Remote Control Carrier Output Function Timer 3 A Even if the RMOEN flag is off when the carrier output is high the carrier waveform is held by the synchronizing circuit When the RMOEN flag is switched to on set the P10TCO flag of the P1OMD register to 1 When it is switched to off set it to 0 When the RMOEN flag is changed do not change the base cycle and its duty at the same time If they are changed at the same time the carrier wave form is not output properly Remote Control Carrier Output 31 Chapter 5 8 Timers 5 9 2 Setup Example mRemote Control Carrier Output Setup Example Timer 3 Here is the setting example that the RMOUT pin outputs the 1 3 duty carrier pulse signal with H period of 36 7 kHz by using timer 0 The source clock of timer 0 is set to fosc at 8 MHz An example setup procedure with a description of each step is shown bel
268. truction set Specific features are as follows 1 Minimized code sizes with instruction lengths based on 4 bit increments The series keeps code sizes down by adopting a minimum instruction length of one byte and variable instruction lengths based on 4 bit increments 2 Minimum instruction execution time is one system clock cycle 3 Minimized register set that simplifies the architecture and supports C language The instruction set has been determined depending on the size and capacity of hardware after an analysis of embedded application programing code and creation code by C language compiler Therefore the set is simple instruction using the minimal register set required for C language compiler 6 101 LSI User s Manual Architecture Instructions Table 2 1 1 Basic Specifications Structure Load store architecture Six registers Data 8 bit x 4 Address 16 bit x 2 Other PC 19 bit PSW 8 bit SP 16 bit Instructions Number of instructions 37 Addressing modes 9 Instruction length Basic portion 1 byte min Extended portion 0 5 byte x n O lt ns9 Basic Internal operationg frequency max 10 MHz performance Instruction execution Min 1 cycle Inter register operation Min 2 cycles Load store Min 2 cycles Conditional branch 2 to 3 cycles Pipeline 3 stage instruction fetch decode execution Address space 256 KB max 64 KB for data External bus A
269. up Example Ree o VI 11 I6 Bit Event Count 4 noh mn nce eoe nene rode eres VI 13 6 4 1 Operation eh SS Hea ish ees VI 13 6 4 2 Setup Example Arsen as Gee ode dete VI 15 16 Bit Timer Pulse Output neret ee etre ipte ren VI 17 6 5 1 Operations ista oath de aes e Se einai VI 17 6 5 2 Set p Exaimple eta eser et tn iet e enn VI 18 Added Pulse Type 16 Bit PWM Output seen VI 20 6 6 1 Operation ccs oe ei i een ahi a ente ied VI 20 6 6 2 Setup Example eee teer it pe eee et eme pH VI 22 16 Timer C pture onec lite a Eee tet VI 24 6 7 1 Operation eae DE den au sed ee RUDI VI 24 6 7 2 Setup Example one ee fete eerie uet VI 26 y contents Chapter 7 Time Base Timer 8 Bit Free running Timer 7 1 7 2 7 3 8 1 8 2 8 3 Chapter9 Buzzer 9 1 9 2 9 3 10 1 10 2 OVERVIEW i b Laert e Hs VII 2 7 1 1 E nctiobs ee dnte Rt tbe eere tbe me edm VII 2 7 1 2 Block Diagrams eee nes ante edente VII 3 Control Registets a ccs eese ter e I ert en ERU tod Reseed eet de VII 4 7 2 1 Control REGISTERS cti coge VII 4 7 2 2 Programmable Timer Registers 5 7 2 3 Timer Mode Registers 6 8 Bit Free running Timer epe tree ete paas S VII 7 7 3 1 Operations 52
270. upt 0 control register lll 17 IRQ1ICR XOS3FES3 R W External interrupt 1 control register Ill 18 IRQ2ICR XOSFEB R W External interrupt 2 control register Ill 19 IRQSICR xOSFEC R W External interrupt 3 control register Ill 20 TM2ICR XO3FE6 R W Timer 2 interrupt control register Timer 2 interrupt Ill 21 TMSICR xOSFEE R W Timer 3 interrupt control register Timer interrupt Ill 22 TM4ICR xOSFEF Timer 4 interrupt control register Timer 4 interrupt Ill 23 XOSFFO R W Timer 5 interrupt control register Timer 5 interrupt Ill 24 TBICR 7 R W Time base interrupt control register Time base period Ill 25 SCOICR 8 R W Serial interface 0 interrupt control register Serial interface 0 interrupt Ill 26 ADICR RW A D converter interrupt control register A D converter interrupt Ill 27 1 IRQSICR be used only for 48 TQFP package type 1 Writing to the interrupt control register should be done after that all maskable interrupts are set to be disabled by the MIE flag of the PSW register If the interrupt level xxxLVn is set to level 3 its vector is disabled regardless of interrupt enable flag and interrupt request flag Control Registers III 15 Chapter 3 Interrupts 3 2 2 Interrupt Control Registers The interrupt control registers include the non maskable interrupt control register NMICR the external i
271. us 15 26 us 15 26 us 5 Time Ts of A D Converter Setup The sampling time of A D converter is set by the 5 to 0 flag of the ANCTRO register The sampling time of A D converter depends on external circuit so set the right value by analog input impedance Table 11 3 3 Sampling Time of A D Conversion and A D Conversion Time ANSH1 ANSHO Sampling time A D conversion time Ts at TAD 800 ns at TAD 954 65 ns at TAD 1 91 us at TAD 15 26 us 0 2 9 60 11 46 us 22 92 us 183 12 us Y 1 TAD x 6 12 80 us 15 27 us 30 56 us 244 16 us 0 TAD x 18 22 40 us 26 73 us 53 48 us 427 28 us 1 Reserved XI 10 Operation Chapter 11 A D Converter Built in Ladder Resistor Control The ANLADE flag of the ANCTRO register is set to 1 to send a current to the ladder resistance for A D conversion As A D converter is stopped the ANLADE flag of the ANCTRO register is set to 0 to save the power consumption Table 11 3 4 A D Ladder Resistor Control ANLADE A D ladder resistance control 0 A D ladder resistance OFF A D conversion stopped 1 A D ladder resistance ON A D conversion stopped A D Conversion Starting Setup A D conversion starting is set by the ANST flag of the ANCTR1 register The flag of the ANCTR1 register is set to 1 to start A D conversion Also the ANST flag of the ANCTR1 register is set to 1 during A D conversion th
272. ut 2 kHz Figure 5 6 4 Output Waveform of 210 Output Pin Setup Procedure Description 1 Stop the counter TM2MD x 3F82 bp4 TM2EN 20 2 Setthe special function pin to the output mode 1 x 3F39 bp2 P12TCO 1 P1DIR x 3F31 PIDIR2 1 3 Select the PWM operation TM2MD x 3F82 bp3 2 1 4 Select the count clock source TM2MD x 3F82 bp2 0 TM2CK2 0 001 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the timer 2 counting Set the P12TCO flag of the port 1 output mode register P10MD to 1 to set P12 pin to the special function pin Set the P1DIR2 flag of the port 1 direction control register P1DIR to 1 for the output mode If needed add pull up resistor t Chapter 4 I O Ports Set the TM2PWM flag of the TM2MD register to 1 to select the PWM operation Select fs 4 for the clock source by the 2 2 0 flag of the TM2MD register 8 Bit PWM Output 23 Chapter5 8 Bit Timers Setup Procedure Description 5 Set the period of PWM H output 5 Set the period of PWM output to the timer 2 72 40 2 compare register TM2OC The setting value is set to 256 4 64 40 because it should be the 1 4 duty of the full count 256 At that time the timer 2 binary counter TM2BO is initialized to 00 6 Start the timer operation 6 Setthe TM2EN flag
273. ut PA6 AN6 in 7 PAPLUD6 AN6 Analog 6 input PA7 AN7 in 7 PAPLUD7 AN7 Analog 7 input 1 Allocated only to 48 pin TQFP package type 2 Not allocated to 42 pin SDIP package type I 10 Pin Description 1 3 3 Pin Functions Table 1 3 2 Pin Function Summary 1 5 Chapter 1 Overview Note that Pin NO described on this table are only for 48 pin TQFP package type t Fig 1 3 3 Pin Configuration Name n pir y o 2 Function Description Vss 17 Power supply pin Supply 2 0 V to 5 5 V to and 0 V to Vss VDD 14 OSC1 16 Input Clock input pin Connect these oscillation pins to ceramic or crystal OSC2 15 Output Clock output pin oscillators for high frequency clock operation If the clock is an external input connect it to OSC1 and leave OSC2 open The chip will not operate with an external clock when using either the STOP or SLOW modes XI 18 Input Clock input pin Connect these oscillation pins to crystal oscillators for 19 Output Clock output pin low frequency clock operation If the clock is an external input connect it to Xl and leave XO open The chip will not operate with an external clock when using the STOP mode If these pins are not used connect XI to Vss and leave XO open These pins are not allocated to 42 SDIP 44 QFP package type NRST 43 Input P27 Reset pin This pin resets the chip when power is turned on is Active low allocated to P
274. ut Set unused pins only for output open Output Figure 1 8 1 Unused Pins only for output iUnused Pins only for input Insert 10 to 100 resistor to unused pins only for input for pull up or pull down If the input is unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and causes power supply noise Input pin Input 10 to 100 q 10 KQ to 100 kQ Input Input pin Figure 1 8 2 Unused Pins only for input Through current Current Pch Input pin Input Nch 0 5 Input voltage at 5 V Input inverter characteristics Input inverter organization Figure 1 8 3 Input Inverter Organization and Characteristics 1 34 Precautions Chapter 1 Overview mUnused pins for I O Unused I O pins should be set according to pins condition at reset If the output is high impedance Pch Nch transistor output off at reset to stabilize input set 10 to 100 resistor to be pull up or pull down If the output is on at reset set them open Output control Output control 10 to 100 Output OFF Output OFF Data Data 10 to 100 Output OFF Output OFF pli 10 kQ to 100 kQ Data 10 to 100 Figure 1 8 4 Unused I O pins high impedance output at reset Precautions 1 35 Chapter 1 Overview 1 8 3 Power Supply The
275. ut Capture Register TM4IC 7 6 5 4 3 2 1 0 TM4ICL TM4ICL7 TM4ICL6 4015 TMAICL4 TM4ICL3 TM4ICL2 TMAICL1 TM4ICLO At reset X XXX XXXX Figure 6 2 5 Timer 4 Input Capture Register Lower 8 bits TM4ICL 03 66 7 6 5 4 3 2 1 0 TM4ICH TMAICH7 TM4ICHG TM4ICHS TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICHO At reset X XX XX XXX Figure 6 2 6 Timer 4 Input Capture Register Upper 8 bits TM4ICH x 03F67 VI 6 Control Registers Chapter 6 16 Timer 6 2 3 Timer Mode Registers This is a readable writable register that controls timer 4 Timer 4 Mode Register TMAMD 7 6 5 4 3 2 1 0 TM4MD TM4EN TM4PWM TM4ICTS1 TM4ICTS0 TM4CK2 TM4CK1 atreset 0000 XX X TM4CK2 TM4CK1 TM4CKO Clock source 0 0 fosc 15 4 0 o fs 16 1 40 input 1 Synchronous 410 input TMAICTS1 TM4ICTS0 Timer 4 input capture trigger 0 0 Disable input capture 1 IRQO 1 0 IRQ1 1 IRQ2 Timer 4 operation mode 0 16 bit timer normal operation 1 PWM operation TM4EN Timer 4 count control 0 Disable the count 1 Enable the count Figure 6 2 7 Timer 4 Mode Register TM4MD x OSF84 R W Control Registers VI 7 Chapter 6 16 Timer 6 3 16 Bit Timer Count
276. ut port by setting the SCOSBOS flag to 1 But it can be used as general input port by setting the bpO of the port 0 direction control register PODIR to 0 Serial data communication of serial interface 0 can be available by setting the SCOSBIS flag or the SCOSBOS flag of the SCOMDS register to 1 The SCOSBIS flag or the SCOSBOS flag should be set to 1 after all conditions are set On the master communication of the clock synchronous set the SCOSBTS flag to 1 before the SCOSBOS flag or the SCOSBIS flag of the SCOMDS register is set to 1 But at the slave communication the SCOSBTS flag needs not to be set to 1 X 12 Operation Chapter 10 Serial Interface 0 mTransfer Bit Count The transfer bit count is selected from 1 bit to 8 bits Set it by the SCOLNG2 to 0 flag of the SCOMDO register at reset 000 4 The SCOLNG2 to 0 flags change at the opposite edge of the transmission data output edge SCOMDO register is changed Except in an 8 bit transfer reset the transfer bit count at the After the transfer has completed the transfer bit count in the SCOLNG2 to 0 flags of the time of the next transmission SCOCE 1 to 0 flags of the SCOMDO register are changed the transfer bit count in the a When the SCOSBOS flag or the SCOSBIS flag of the SCOMDS register to 1 and the 2 SCOLNG2 to 0 flags of the SCOMDO register may be incremented Start Condition The SCOSTE fla
277. value of the port 1 input register P1IN To output data to pin set the control flag of the port 1 direction control register P1DIR to 1 and write the value of the port 1 output register P1OUT Each pin can be set individually if pull up resistor is added or not by the port 1 pull up resistor control register P1PLU Set the control flag of the port 1 pull up resistor control register P1PLU to 1 to add pull up resistor At reset the input mode is selected and pull up resistors are disabled high impedance output 5 Function Pin Setup P12 to P14 are used as timer I O pin as well P10 is used as remote control carrier output pin as well The port 1 output mode register P1OMD can select P12 to P14 output mode by each bit When the port 1 output mode register P1 OMD is 1 special function data is output and when it is 0 they are used as general port Port 1 IV 9 Chapter 4 Ports Output data Low Vss level High level Input data Pin is low Vss level Pin is high VDD level mode selection Input mode Output mode Pull up resistor selection 4 3 2 Registers 7 6 5 4 3 2 1 0 P1OUT P1OUTA4 PTOUT3 P1OUT2 PTOUT1 iom Atreset 00000 P1OUT 0 1 Port 1 output register
278. vel output at the PWM4 pin not constant high Do not set x FF in TM4OCL VI 20 Added Pulse Type 16 Bit PWM Output 5 the Added Pulse Position Chapter 6 16 Bit Timer The upper 8 bits of timer 4 compare register 4 set the position of the added pulse If the register is set to x 00 an additional bit is not appended to the basic PWM component If the register is set to x FF an additional bit is repeatedly appended to the 255 basic PWM compo nents during the cycle The relation between the value set in the register and the position of the added pulse is shown in the table below In the TMAOCH register the position of the added pulse the value of Tn depends which bit has 1 And the number of the setting value in is the number of bits to be added For example if x 03 is set in the TMAOCH register set 1 in bp1 bits are appended to pulse positions for x 01 Tn x 80 and x 02 Tnzx 40 x C0 shown in the below table The setting value of Position of the added pulse the value of Tn x 02 00000100 x04 00001000 08 00010000 x10 00100000 x20 01000000 x40 10000000 x80 0 7 bpO 00000000 x00 00000001 x01 80 00000010 x 40 x C0 X20 X 60 X AO X EO X10 x 30x 50 Xx 70 x 90 X08 x18
279. watchdog timer during operation Disable Enable Li Signature This check list is subjected to change Please request the most recent check list from the sales office when doing ROM release Option of this product is used a part of the built in ROM Please set data on the address of the option when doing ROM release Option 1 29 Chapter 1 Overview 1 7 Package Dimension Package Code SDIP042 P 0600 SEATING PLANE Units mm Sealing material Lead material Lead surface processing EPOXY resin Fe Ni Solder plate Figure 1 7 1 42 SDIP 0 The package dimension is subjected to change Before using this product please obtain product specifications from the sales office 1 30 Package Dimension Chapter 1 Overview Package Code QFP044 P 1010 Units mm 12 30 0 40 10 00 40 20 10 00 0 20 2 00 0 20 2 10 030 0 10 0 10 1 15 2020 SEATING PLANE Sealing material EPOXY resin Lead material Fe Ni Lead surface processing Solder plate 0 60 2020 Figure 1 7 2 44 Pin QFP The package dimension is subjected to change Before using this product please obtain product specifications from the sales office Package Dimension I 31 Chapter 1 Overview Package Code TQFP048 P 0707B Units mm 9 00 020 7 00 20 10 LJ
280. witching transmission reception TXD pin s direction should be controlled by the PODIRO flag of the PODIR register At that time the RXD pin is not used so that it can be used as a general port X 30 Operation Chapter 10 Serial Interface 0 Mode and Parity Check Setup Figure 10 3 11 shows the data format at UART communication lt lt 1 data frame parity bit character bits Figure 10 3 11 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 10 3 12 shows its kinds to be set Table 10 3 12 UART Serial Interface Transmission Reception Data Start bit 1 bit must be L Character bit 7 8 bits Parity bit fixed to 0 fixed to 1 even odd none Stop bit 1 2 bits noramally H The SCOFM1 to 0 flag of the SCOMD2 register sets the frame mode Table 10 3 13 is shown the UART serial interface frame mode setting If the SCOCMD flag of the SCOCTR register is set to 1 and UART communication is selected the SCOLNG2 to 0 flag of the SCOMDO register is automatically set Table 10 3 13 UART Serial Interface Frame Mode SCOMD2 register Frame mode 5 SCOFMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits St
281. x00000 X04000 XUFFF MN101CP427 X 00000 to X 001FF 512 X 04000 to X 07FFF x 07FFF should be reserved for ROM option Memory Space II 13 Chapter 2 CPU Basics ion Registers Special Funct 3 2 2 The MN101C series locates the special function registers I O spaces at the addresses x 03F00 to x OSFFF in memory space The special function registers of this LSI are located as shown below Table 2 2 2 Register Map 460 9120 991098 Y91104 801008 X33 0 XQ3 0 X93 0 X83 0 160 LY LONY OULONY X6360 JOU QNTIN L 9O8IAL 20201 TOWWL HOP 1287 1 GENL IgZNL 4 1 12195 8XH09S 1098 19038 EdW00S 4008 1011025 001025 6460 spod 101515 11494 111494 M1d0d 460 01 0 1094 6460 yod NI9d 2460 jndino 104 10044 111094 100084 10044 1 01
282. xample for clock synchronous serial interface communication with serial interface 0 is shown Table 10 3 10 shows the conditions at transmission reception Table 10 3 10 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item set to Setup item set to SBIO SBOO pin Independent with 3 channels Clock source fs 2 Transfer bit count 8 bits Clock source 1 8 dividing not divided by 8 Start condition none 5870 5800 pin style Nch open drain First transfer bit MSB SBTO pin pull up resistor Not added 5800 pin pull up resistor Not added Input clock edge falling edge 580 pin pull up resistor Added Serial 0 communication Output clock edge rising edge complete interrupt Enable Internal clock Clock master communication An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the clock synchronous serial 1 Set the SCOCMD flag of the serial interface 0 interface control register SCOCTR to 0 to select the SCOCTR x 3F54 clock synchronous serial interface bp6 SCOCMD 0 2 SCOMDO register 2 Set the SCOLNG2 0 flag of the serial interface Select the transfer bit count SCOMDO x 3F50 0 mode register 0 SCOMDO to 000 to set the transfer bit to 8 bits bp2 0 SCOLNG2 0 000 Select the start condition Set the SCOSTE flag o
283. y Timer pulse output PWM output Added Pulse Capture function fosc Clock source E input fosc Machine clock High speed oscillation fs System clock at NORMAL mode fs fosc 2 at SLOW mode fs fx 4 VI 2 Overview 16 Bit Timer Chapter 6 Block Diagram 6 1 2 Timer 4 Block Diagram indino 4 ZXOVIAL OXOVIAL peau peau 0 A A H ZOul ZAN LLL TOIL 2 eunjdeo 18 9 i 004 A A OILSY uoneziu 288 1 lonoufs gt _ 2 5 emo HogpI c 28 S 6 uonippe asing P Jejunoo 419 9 UN 91 8 lt vis 80 ae asing d 1 lt eui HOOPNL TOOPWL Jejsi68 18 91 1 Y Y Timer 4 Block Diagram Figure 6 1 1 VI 3 Overview Chapter 6 16 Bit Timer 6 2 Control Registers Timer 4 contains the binary counter T
284. y operation SLOW mode Transition between NORMAL and SLOW modes to standby mode is controlled by the CPU mode control register CPUM Reset and interrupts are the return factors from standby mode A wait period is inserted for oscillation stabilization at reset and when returning from STOP mode but not when returning from HALT mode High low frequency oscillation mode is automatically returned to the same state as existed before entering standby mode oscillation fosc and low speed oscillation fx fosc should be set to 2 5 times or higher a To stabilize the synchronization at the moment of switching clock speed between high speed 2 frequency than fx II 18 Standby Functions Chapter 2 CPU Basics 2 4 2 Mode Control Register Transition from one mode to another mode is controlled by the CPU mode control register CPUM 7 6 5 4 3 2 1 0 CPUM _ RESERVED RESERVED RESERVED STOP HALT 05 1 05 0 At reset 0 0 0 0 0 0 0 NEN 0 oe STOP HALT OSC1 OSCO ee XI XO 21 CPU NORMAL 0 0 0 0 Oscillation Oscillation fosc 2 Operating IDLE 0 0 0 1 Oscillation Oscillation fx 4 Operating SLOW 0 0 1 1 Halt Oscillation fx 4 Operating HALTO 0 1 0 0 QOscillation Oscillation 2 Halt HALT1 0 1 1 1 Halt Oscillation fx 4 Halt STOPO 1 0 0 0 Halt Halt Halt Halt STOP1 1 0 1 1 Halt Halt Halt Halt
285. ys to 0 RMDTYO Remote control carrier output duty 0 1 2 duty 1 1 3 duty Reserved Set always 0 RMOEN Enable remote control carrier output 0 Output low level 1 Output remote control carrier Reserved Set always to 0 Figure 5 2 7 Remote Control Carrier Output Control Register RMCTR 03 89 R W Control Registers V 9 Chapter5 8 Timers 5 3 8 Bit Timer Count 5 3 1 Operation The timer operation can constantly generate interrupts 8 Bit Timer Operation Timers 2 3 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register TMnOC in advance If the binary counter TMnBC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from 00 Table 5 3 1 shows clock source that can be selected 10 Operation Table 5 3 1 Clock Source Timers 2 and 3 at Timer Operation Clock source 1 count time p m fosc 50 ns fs 100 ns fs 4 400 ns Y y fs 16 1 6 us fx 30 5 us Y 1 as fosc 20 MHz fx 32 768 kHz fs fosc 2 10 2 Chapter 5 8 Timers Timing of Timer Operation Timers 2 and 3 Binary counter counts up with selected clock source as a count clock The basic operation of the

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