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Data Sheet: DiskOnChip-Based MCP 1 (MS01-D7N7P6-B1)

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1. emere wes p e manner Lee pe n en e gt Poms pe n pepe pe Leer s prp ep Lees pe n e Lees pe prp n p gt pe np e e fe a Pa eT np n e gt mens u j 3E 53 2002 08 07 46 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ADDRESS RANGE C epe e onmes p epe mes pe epe n e pepe n p p epe epe serene p epe ep pe epe pen e snore Pome pepe pepe n p p ep e e C p eee n e E s e Fee a Pete Leer pp epp ep pe epe pn e gt pee pep n e momen meo p ne e sme wen perpe n
2. 50 10 34 AG Operating CornditlOns tp tetto et e ce REO E d E 52 10 4 Timing Specifications iuda uae bead ade be etcetera ede aee 53 10 4 1 Read Cycle Timing Standard 53 10 4 2 Write Cycle Timing Standard 56 10 4 3 Read Cycle Timing Multiplexed 58 10 4 4 Write Cycle Timing Multiplexed 2 60 10 4 5 Power Up iine ats a A nee 62 10 4 6 Interrupt Timing u LL ninii Leite 63 10 5 Mechanical Dimensions eade 64 11 Ordering Informatlon eren enne aes 65 5 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Revision History Revision Date Description Reference 1 7 February 2003 ID 0 1 AVD and VCCQ description detailed Section 2 2 3 Ordering info table updated to reflect Pb free ordering info Section 11 6 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 1 Introduction This data sheet includes the following sections Section 1 Section 2 Section 3 Sec
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4. ks x no he AC TEST CONDITIONS PARAMETER CONDITION Output load 30 pF 1 TTL Gate Input pulse level Vpp 0 2 V 0 2 V 2002 05 22 2 7 TOSHIBA TC51WHM616A TIMING DIAGRAMS READ CYCLE 2002 05 22 3 7 TOSHIBA TC51WHM616A See Note 8 WRITE CYCLE 1 WE CONTROLLED See Note 8 WRITE CYCLE 2 CE CONTROLLED 2002 05 22 4 7 TOSHIBA TC51WHM616A See Note 8 WRITE CYCLE 3 UB LB CONTROLLED twR 2002 05 22 5 7 TOSHIBA TC51WHM616A Deep Power down Timing CE1 CE2 tcs tcH Power on Timing V Vom 2 Provisions of Address Skew Read In case multiple invalid address cycles shorter tacmin sustain over 1045 in a active status as least one valid address cycle over tacmin must be needed during 10us over 10us CE1 Address Write In case multiple invalid address cycles shorter than twcmin sustain over 10us in a active status as least one valid address cycle over twcmin with twpPmin must be needed during 10 5 over 10us CE1 Address 2002 05 22
5. 9 1 9 Auto Chip Erase Time and Auto Block Erase Time include internal pre program time 2002 08 07 F 17 57 TOSHIBA TC58FVM7T2A 7B2A type COMMAND WRITE PROGRAM ERASE CYCLE SYMBOL PARAMETER Command Write Cycle Time g o Address Set up Time BYTE Set up Time Address Hold Time BYTE Hold Time Address Hold Time from High level Data Set up Time 5 gt T lt Data Time gt x Low Level Hold Time WE Control E High Level Time WE Control E1 CE2 Set up Timeto WE Active WE Control 2 Time from WE High Level WE Control 1 2 Low Level Time Control rn 3 High Level Hold Time CE1 CE2 Control E Set up time to CE1 CE2 Active CE1 CE2 Control Time from 1 2 High Level 1 2 Control toES OE Set up Time Hold Time Toggle Data Polling lOEHT OE High Level Hold Time Toggle tAHT Address Hold Time Toggle Address Set up Time Toggle Erase Hold Time Vpp Set up Time Program Erase Valid to RY BY Delay m O Oo 30 20 2 2 2 o o o 2 o o 2 o 5 2 2 2 2 2 2 2 2 2 2 2 2 o o o o o o o o o o o o o o 2 o Program Erase
6. pe e epp prn o E premens momen sa e pepe e C soga omen e e fe fe perpe fem Fr e pene pe er ep ep e er Pens fe Palm oP aoe Poms e pepe fe fe Pepa pepe ep o e pe pepe 8 e Le e pe pep e perpe e e pepe Le jt e pepe x e ppp n Dn 2002 08 07 F 54 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ADDRESS RANGE one u re r e e lt 77738772773 s s epe n a epe n p s fe Pe pee p epe s epe pen e mes pe e fe Pa Pe peo E oer Pee fe Pe Pe eT s epp n e gt Lee fe ep n p p epp ep
7. Fee pe epe Co pes p e Pome n pe wer pe npe n e Fees pe npe n pe npe pe e s Pee Le Pa Pe e n pepe p mme mes p erp mes a e fe a e e eosar Fen pne prp n p pe np e e gt mes n s rp Po Pe e 2002 08 07 F 55 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ADDRESS RANGE p e pe saoo sore pe pe epe po pe epe pe wer pep epe D pep pe n e pee pe n epe e wen pe n ep 7 sme wee afu se
8. 37 8 3 Boot Replacements n eoe edis ape e te eoe de dut ene 38 831 de dac t ea x de eai ed oe eee ce nue aee evade 38 8 3 2 Non PG Architectures cadena e eue a dee ie Pe ee eiue apud deua d 38 8 3 3 Using Mobile DiskOnChip Plus Asynchronous Boot 39 9 Design Considerations seen 40 9 1 DESIGN ur u uy Gr SAS 40 92 u tee t Lebe Le certe Lo tie 41 9 2 Standard INS race uu 41 9 2 2 uuu l sssi aqa naraq qa ao Aq Ta 42 9 3 Connecting Slgrials Lm 42 9 3 1 Standard Merate n uu uu eei ea 42 932 Multiplexed Interface uuu tees cederet ae tots RP nta aae e REY deters 43 9 4 Implementing the Interrupt Mechanism ee eren 43 941 Hardware GonflguFatlon l teg ci irt nta eub otc kat ec be 43 942 Software ConfiQuration n Eee Reduce 43 9 5 Platform Specific Issues 1 0000 a 44 9 51 Walt States uu
9. WEF BHE RSTIN 8 bit BUSY im 1002 im ID 0 1 IF CFG Figure 5 Standard Interface Simplified Block Diagram 17 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 3 2 System Interface The system interface block provides an easy to integrate SRAM like also EEPROM like interface to Mobile DiskOnChip Plus enabling it to interface with various CPU interfaces such as a local bus ISA bus SRAM interface EEPROM interface or any other compatible interface In addition the EEPROM like interface enables direct access to the Programmable Boot Block to permit XIP functionality during system initialization A 13 bit wide address bus enables access to the DiskOnChip 8KB memory window as shown in Section 6 2 The 16 bit data bus permits 16 bit wide access to the host The internal access to the flash 1s 8 bit The Chip Enable CE Write Enable WE and Output Enable OE signals trigger read and write cycles write cycle occurs while both the and the WE inputs are asserted Similarly a read cycle occurs while both the and OE inputs are asserted Note that Mobile DiskOnChip Plus does not require a clock signal Mobile DiskOnChip Plus features a unique analog static design optimized for minimal power consumption WE and OE s
10. DC S 10 2 14 2Environtriebtal sd A eee TREE IB REDDE ORE RIEN E D EE ERR RS 10 2 2 Mechanical tn eerte tec obe di dO cde am ed a E e DR 10 3 Ordering Information uu torna e ero ea XY Xa napa dE RES VL AX RS daa 11 4 MARKINGS ee 11 Appendix 128Mbit Mobile DiskOnChip Plus Data Sheet Appendix B 128Mbit CMOS NOR Flash Memory Data Sheet Appendix C 64Mbit CMOS Pseudo Static RAM PSRAM Data Sheet 2 Data Sheet Rev 0 4 91 SR 001 53 8L 10 DiskOnChip Based MS01 D7N7P6 B1 The ball assignment information in this section replaces and supersedes the PRODUCT OVERVIEW Ballout MS I I PAN NCC OJE Z 197522522 Me ee Gree ay sy S p Fey SY SY sy Sy ey sy 8 gy e UN NUN CAEABAEASATASASABAS Yz m s sya say vom DD ODED ED EAE EV Rm mmm 3 9 3 2 a e s 740 2 2 assignment information in individual data sheets from M Systems and Toshiba provided as part M Systems DiskOnChip based MCP is packaged in a 107 ball FBGA 9x12 mm package See of this data sheet Figure 1 for the preliminary ball assignments M Systems mm Flash Disk Pioneers Important 1 1 1 qu emm Ve ANS EE e us 91 SR 001 53 8L Figure 1 DiskOnChip Based MCP Ball Diagram Top View Dat
11. esmes orones see e 2002 08 07 F 57 57 M Systems mamam Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 APPENDIX C 64MBIT CMOS PSEUDO STATIC RAM PSRAM DATA SHEET Note Information regarding packaging ball assignment and package level specifications does not apply to DiskOnChip based MCP For DiskOnChip based MCP specifications refer to Sections 1 and 2 of this data sheet Data Sheet Rev 0 4 91 SR 001 53 8L TOSHIBA TC51WHM616A 64 Mbits PSEUDO STATIC RAM TC51WHM616A Organization 4M x t6bits 2002 05 22 1 7 TOSHIBA TC51WHM616A AC CHARACTERISTICS AND OPERATING CONDITIONS Ta 30 to 85 C Vpp 2 7 to 3 3 V See Note 5 to 11 pasem ole Chip Enable CE1 Access Time 7 n ke x ko massa Umm ate 9 sa be asx ke m feo m 9 ls ine a Page ine Adres un e E hor Pag oe he eem o ag tay wa Fs ke ks
12. s Lee pen p fa Pee fe Pe Pave pe e fe n e eosar Lee perpe e pe ep pepe po n e Panes Po De De seer re are 2002 08 07 42 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK E ADDRESS RANGE E ws pee e pep pe pepe sommer Lo pe pepe sommer pe p p e epe seoor serre ene pep epe pe epe pe pr 7 pe n epe pe n epe e pee n epp 7 sms emer pep n epo semen pen pep e pep en pepe memes semen Como pep n pep e mma ee pep n pop sm pep prp pe Le pep pepe fe De pep pre pep pepe pep De semen Ls pep pepe pepe pep pepe pop De Come
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15. Besplo 0 2 4 7 Reserved for future use 3 SLOCK Sticky Lock Setting this bit to a 1 has the same effect as asserting the LOCK input up until the next power up or reset Once set this bit can only be cleared by asserting the RSTIN input Like the input the assertion of this bit prevents the protection key from disabling the protection for a given partition if the value of the LOCK bit in its respective Data Protect Structure is set When read this bit always returns the value 0 Setting this bit affects the state of the bit in the Protection Status register Note For further information on the Output Control and Protection Status registers refer to the addendum to this data sheet Mobile DiskOnChip Plus DIMM Plus Register Description 7 10 Interrupt Control Description Interrupts may be generated when the flash transitions from the busy state to the ready state or by a data protection violation Address hex 100E Type Read Write Reset Value 00H FRDY T 2 0 Flash Ready Trigger This field determines if an interrupt will be generated when the flash array of Mobile DiskOnChip Plus is ready as follows 000 Interrupts are disabled Holds the IRQ output in the negated state 001 Interrupt when flash array is ready EDGE Edge sensitive interrupt 0 Specifies level sensitive interrupts in which the IRQ output remains asserted until the interrupt is cleared 1 Specifies edge se
16. A i M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V signal Ball No an Description ype Reserved RSRVD K6 Reserved signal that is not connected internally Note Future DiskOnChip devices will use this pin as a clock input To be forward compatible this pin can already be connected to the system CLK or to VCC when the clock input feature is not required Other See Reserved signal that is not connected internally and must be left Figure 3 floating to guarantee forward compatibility with future products It should not be connected to arbitrary signals M Mechanical These balls are for mechanical placement and are not connected internally A Alignment This ball is for device alignment and is not connected internally The following abbreviations are used IN Standard non Schmidt input ST Schmidt Trigger input OD Open drain R8 Nominal 22 pull up resistor enabled only for 8 interface mode input is 0 R 3 7 nominal pull up resistor Note For forward compatibility with future DiskOnChip 7x10 FBGA products additional pads are required Please refer to Application Note AP DOC 067 Preparing your PCB Footprint for the DiskOnChip BGA Migration Path for detailed information 16 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems ms Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 3 Theory of Operation 3 4 Overview
17. Bad Block Table and Factory Programmed UID Pages 0 5 Block 0 OTP Pages 7 12 Data Protect Structure 0 Block 1 Data Protect Structure 1 and IPL Code Block 2 Figure 8 Low Level Structure of Mobile DiskOnChip Plus Blocks 0 1 and 2 in Mobile DiskOnChip Plus contain the following information Block 0 Bad Block Table page 2 Contains the mapping information to unusable Erase units on the flash media e UID 16 bytes This number is written during the manufacturing stage and cannot be altered at a later time e Customer OTP occupies pages 26 31 The OTP area is written once and then locked Block 1 e Data Protect Structure 0 This structure contains configuration information one of the two user defined protected partitions Block 2 e Data Protect Structure 1 This structure contains configuration information on one of the two user defined protected partitions e IPL Code IKB This is the boot code that is downloaded by the DE to the internal boot block 23 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 5 Modes of Operation Mobile DiskOnChip Plus has three modes of operation e Reset e Normal Deep Power Down Mode changes can occur due to any of the following events as shown in Figure 9 e Assertion of the RSTIN signal sets the device in Reset mode During power up boot detector circuitry sets the device
18. Pins Deep Power Down mode 32MB VCCQ Pins All inputs OV or VCCQ 32MB 1 The input includes a pull up resistor which sources 0 3 1 4 uA at Vin 0V 2 The D 15 8 and BHE inputs each include a pull up resistor which sources 58 234 at Vin when IF_CFG is a logic 0 3 3 3V VCCQ 1 8V Outputs open 4 If DiskOnChip is not set to Deep Power Down mode and is not accessed for read write operation standby supply current 15 400 typ to 600 max 5 Deep Power Down mode is achieved by asserting RSTIN when in Normal mode or writing the proper write sequence to the DiskOnChip registers and asserting the CE input VCCQ See Section 5 3 for further details 50 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Table 12 DC Characteristics 2 5V 3 6 I O e Low level Output Voltage llo omx 04 lt lt a High level Output Current Active Supply Current loc m Deep Power Down mode 10 40 Standby Supply Current 16MB A 4 Deep Power Down mode 32 1 CE input includes a pull up resistor which sources 0 3 1 4 uA at Vin 0V 2 The D 15 8 and BHE inputs each include pull up resistor which sources 58 234 at Vin when IF_CFG is a logic 0 3 VCC VCC
19. 10 5 Mechanical Dimensions See Figure 26 for the mechanical dimensions of the FBGA package FBGA Dimensions 16 9 0 0 20 mm x 12 0 0 20 mm x 1 2 0 1 mm FBGA Dimensions 32 9 0 0 20 mm x 12 0 0 20 mm x 1 4 0 1 mm Ball Pitch 0 8mm 90 gt lt 0 90 720 gt i 14 0 80 gt 45 080 040 gt I 2 B r N D 120 oce N 2 2 E NL Y Figure 26 Mechanical Dimensions of the FBGA Package 64 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 11 Ordering Information MD3x31 Dxx V3Q18 T C MD M Systems DiskOnChip 03831 Mobile DiskOnChip Plus FBGA MD3331 Mobile DiskOnChip Plus dual die FBGA D Capacity 16 32 Capacity 32MB 256Mb 16MB 128Mb V Voltage V3Q18 Core Voltage 3 3V I O Voltage 1 8 or 3 3V T Temperature Range Blank Commercial 0 C to 70 C x Extended 40 C to 85 C C Composition Blank Regular P Lead free Summary of available configurations Table 24 Available Mobile DiskOnChip Plus Configurations 16 MByte Extended MD3831 D16 V3Q18 X 9x12 mm FBGA 128 Mbit 32 MByte 256 Mbit 65 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems mamam Flash Disk Pioneers DiskOnCh
20. Programming in Erase Suspend Toggle Notes DQ outputs cell data and RY BY goes High Impedence when the operation has been completed DQO DQ1 pins are reserved for future use 0 is output on DQ0 DQ1 and DQ4 1 Data output from an address to which Write is being performed is undefined 2 Output when the block address selected for Auto Block Erase is specified and data is read from there During Auto Chip Erase all blocks are selected 3 Output when block address selected for Auto Block bank selected block is specified data is read there 4 In case of Page program operation is program data of A0 A1 A2 1 1 1 in eleventh bus write cycle in word mode Program data of 1 0 1 2 1 1 1 1 nineteenth bus write cycle byte mode DQ7 DATA polling During an Auto Program or auto erase operation the device status can be determined using the data polling function DATA polling begins on the rising edge of WE in the last bus In an Auto Program operation DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished In an auto erase operation DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished If an Auto Program or auto erase operation fails DQ7 simply outputs the data When the operation has finished the address latch is reset Dat
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22. A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 7 4 Operation Register Description Address hex Type Reset Value A call to this register results in no operation To aid in code readability and documentation software should access this register when performing cycles intended to create a time delay 1002 Write None 7 5 Test Register Description Address hex Type Reset Value This register enables software to identify multiple Mobile DiskOnChip Plus devices or multiple aliases in the CPUs memory space Data written 1s stored but does not affect the behavior of Mobile DiskOnChip Plus 1004 Read Write 00H Bits Bito D 7 0 mue BeHpios 0 7 D 7 0 Data bits Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 7 6 DiskOnChip Control Register Control Confirmation Register Description These two registers are identical and contain information on the operation mode of Mobile DiskOnChip Plus After writing the required value to the DiskOnChip Control register the complement of that data byte must also be written to the Control Confirmation register The two writes cycles must not be separated by any other read or write cycles to the Mobile DiskOnChip Plus memory space except for reads from the Programm
23. Mobile DiskOnChip Plus consists of the following major functional blocks as shown in Figure 5 e System Interface for host interface e Configuration Interface for configuring Mobile DiskOnChip Plus to operate in 8 16 bit mode cascaded configuration and hardware write protection Protection and Security Enabling containing write read protection and One Time Programming OTP for advanced data code security and protection e Programmable Boot Block with XIP capability enhanced with a Download Engine DE for system initialization capability Reed Solomon based Error Detection and Error Correction Code EDC ECC for on the fly error handling e Data Pipeline through which the data flows from the system to the NAND flash arrays e Control amp Status block that contains registers responsible for transferring the address data and control information between the TrueFFS driver and the flash media e Flash Interface consists of a single 16MB NAND flash array Figure 5 Mobile DiskOnChip Plus achieves a 32MB capacity using two stacked 16MB devices in a dual die package Bus Control for translating the host bus address data and control signals into valid NAND flash signals Address Decoder to enable the relevant unit inside the DiskOnChip controller according to the address range received from the system interface Controller DATA 0 15 ADDR 0 17 71 Dota pipeline 1 8 8 I
24. J lt Twcvc gt Figure 23 Multiplexed Interface Write Cycle Timing Table 20 Multiplexed Interface Write Cycle Parameters VCC 2 5V 3 6V VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 5 3 6V VCC 2 5 3 6V Units Min Max Min Max tsu AVD Address to AVD Y setup time 5 5 ns tho AVD Address to AVD hold time 7 7 ns Tw AVD AVD low pulse width 12 12 ns tsu AVD WE AVD V to WE v setup time Trec WE AVD to AVD in next cycle 29 30 ns WE asserted width 51 50 tw WE ns WE asserted width all other addresses 50 49 Twcyc Write Cycle Time 83 83 ns tsu CEO v to Y setup time ns tho CEO WE to CE hold time ns tho CE1 OE WE to hold time 6 6 ns tsu CE1 to WE or OE V setup time 6 6 ns trec WE WEZ to start of next cycle 20 20 ns Tsu D D to WE 7 setup time RAM 29 29 ns Tho D to D hold time 0 0 ns Note When designing your board to support also DiskOnChip Plus 32MB or 64MB devices it is not possible to use 2 5 3 6 as these devices only support VCC 2 7 3 6V 60 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems mam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O Table 21 Multiplexed Interface Write Cycle Parameters VCC 2 7 3 6V
25. M M Systems Flash Disk Pioneers 5 MobileDiskOnChip DiskOnChip Based MCP with Mobile DiskOnChip Plus CMOS NOR Flash and PSRAM Highlights DiskOnChip based MCP Multi Chip Package is complete memory solution Efficiently packed in a small Fine Pitch Ball Grid Array FBGA package it is ideal for data and code storage inside 2 5G and 3G mobile handsets and Personal Digital Assistants PDAs DiskOnChip based MCP consists of M Systems Mobile DiskOnChip m Toshiba s CMOS NOR flash Toshiba s PSRAM Pseudo Static RAM General Features m Small 9x12x1 4 mm 107 ball FBGA package 128Mbit 16MByte Mobile DiskOnChip Plus m 128Mbit 16MByte Toshiba NOR flash m 64Mbit Toshiba PSRAM m High performance 16 bit interface to all devices m Deep Power Down mode for low power consumption m Operating voltage 2 7V to 3 3V m Operating temperature 30 C to 85 Data Sheet Nov 2003 LN 248 DiskOnChip Mobile DiskOnChip Plus Mobile DiskOnChip Plus 128Mbit 16MByte is the industry s most efficient code and storage solution with the fastest write performance the smallest die size and the highest level of reliability and flash endurance Additionally Mobile DiskOnChip Plus offers advanced data protection and security enabling options Mobile DiskOnChip Plus features Exceptional write read and erase performance Advanced protection and security enabling
26. Mobile DiskOnChip Plus 16 32MByte 1 8V I O Table 14 Standard Interface Read Cycle Timing Parameters VCC 2 5 3 6V VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 5 3 6V VCC 2 5 3 6V Units Min Max Min Max Tsu A Address to OE v setup time 2 2 ns Tho A OE v to Address hold time 28 28 ns Tsu CEO CE V to OE V setup time ns Tho CEO to hold time ns Tho CE1 OE WE to CE v hold time ns Tsu CE1 to WE or OE v setup time ns Trec OE OE negated to start of next cycle 20 20 ns id Read access time 107 116 ns Read access time all other addresses 87 96 ns Tloz D OE Y to D driven 15 15 ns Thiz D OE to D Hi Z delay 23 27 ns Asynchronous Boot Mode tacc A RAM Read access time from A 9 1 93 101 ns tho A D Data hold time from A 9 1 RAM 0 0 ns Note When designing your board to support DiskOnChip Plus 32MB or 64MB devices it is not possible to use 2 5 3 6 as these devices only support VCC 2 7 3 6V Table 15 Standard Interface Read Cycle Timing Parameters VCC 2 7 3 6V VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 7 3 6V VCC 2 7 3 6V Units Min Max Min Max Tsu A Address to OE setup time 2 2 ns Tho A OE Y to Address hold time 28 28 ns Tsu CEO to OE v setup time ns Tho
27. Mobile DiskOnChip Plus has an additional hardware safety measurement If the Lock option is enabled by means of software and the LOCK ball is asserted the protected partition has an additional hardware lock that prevents read write access to the partition even with the use of the correct protection key The LOCK ball must be asserted during DFORMAT and later when the partition is defined as changeable to enable the additional hard wired safety lock It is possible to set the Lock option for one session only that is until the next power up or reset This Sticky Lock feature can be useful when the boot code in the boot partition must be read write protected Upon power up the boot code must be unprotected so the CPU can run it directly from Mobile DiskOnChip Plus At the end of the boot process protection can be set until the next power up or reset Setting the Sticky Lock SLOCK bit in the Output Control register to 1 has the same effect as asserting the LOCK 2 ball Once set SLOCK can only be cleared by asserting the RSTIN input Like the LOCK input the assertion of this bit prevents the protection key from disabling the protection for a given partition For more information see Section 7 9 The target partition does not have to be mounted before calling a hardware protection routine Only one partition can be defined as changeable i e its password and attributes are fully configurable at any time from read to write both or n
28. Mode Entry AAAh ETS Hidden ROM Wor Program Uu lt gt 555h 2AAh B AAAh Hidden ROM Wor 555h 2AAh SEX Erase AAAh 555h Uu lt gt iss a jo ja Uu lt gt Hidden ROM Wor 555 2 Mode Exit 555h Quer 55h uery C att 12 BK AAh Notes system should generate the following address patterns Word Mode 555 or 2AAH on address pins A10 AO DQ8 DQ15 are ignored in Word Mode Byte Mode AAAH or 555H on address pins A10 A 1 RA Read Address 7 PD Program Data RD Read Data 8 BA Block Address A21 A12 ID Read 6 1 0 55 21 20 9 Slok Do 212 d IA Bank Address and ID Read Address 6 0 ID Read Address 0 1 0 Bank Address 21 20 10 BPD Verify Data Manufacturer Code 0 0 0 11 CFI Address Device Code 0 0 1 12 CD CFI Data Ip Data 13 FOH is valid too 55 Input continuous 8 address 0 1 2 0 0 0 to 0 1 2 1 1 1 program 2002 08 07 F 2 57 TOSHIBA TC58FVM7T2A 7B2A type CE1 CE2 OPERATION MODE TC58FVM7T2A B2A havetwo CE pins 1 CE2 Two CE pins enable the device to use like 64Mbits x 2pcs Therefore this device is useful for the system 128Mbit address is no supported
29. When using a standard interface Mobile DiskOnChip Plus be configured for 8 bit 16 bit or 32 bit bus operations 8 Bit Byte Data Access Mode When configured for 8 bit operation should be negated Data should then be driven only on the low data bus signals D 7 0 D 15 8 and BHE are internally pulled up and may be left floating 16 Bit Word Data Access Mode When configured for 16 bit operation should be asserted The following definition is compatible with 16 bit platforms using the BHE BLE protocol e When the host BLE signal asserts Mobile DiskOnChip Plus 0 data is valid on D 7 0 e When the host BHE signal asserts Mobile DiskOnChip Plus BHE data is valid on D 15 8 When both A 0 and BHE are at logic 0 data is valid on D 15 0 44 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V e data is transferred when both BHE and 0 are logic 1 e 16 bit hosts that do not support byte transfers may hardwire the AO and BHE inputs to logic 0 Table 4 shows the active data bus lanes in 16 bit configuration Table 4 Active Data Bus Lanes in 16 bit Configuration inputs Data Bus Activity Transfer Type mu ao Loo Jo v lt w lt Ew o Note Although Mobile DiskOnChip Plus 16 32MB uses 8 bit access to
30. eo fe Pee fe e E menm Les pen pep n pep Pane pp npe npo Pave Pepe ee Pe Pave epp omen ws een pen ep Pane epee fe fae mT reer ono ws pen epo Les pen rp n e Cwe e efe re 7307757773 pe 2002 08 07 40 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ES ADDRESS RANGE ES ws Les pepe epe pe n o wes e epe ws Le Cwe e CC awe pepe Le fem p o aoe ws pepe epe pepe sme pepe n e Lee pepe peo n o pep e e pepe peo Come pepe n e Pane e serra ms perpe Le perp
31. flash defragmentation and other options This unique functionality is available in all TrueFFS based drivers through the standard I O control command of the native file system For further information please refer to the Extended Functions of the TrueFFS Driver for DiskOnChip developer guide 6 1 9 Compatibility The TrueFFS driver supports all released DiskOnChip products Upgrading from one product to another requires no additional software integration When using different drivers e g TrueFFS SDK BDK BIOS extension firmware etc to access Mobile DiskOnChip Plus the user must verify that all software is based on the same code base version It is also important to use only tools e g DFORMAT DINFO GETIMAGE etc derived from the same version as the firmware version and the TrueFFS drivers used in the application Failure to do so may lead to unexpected results such as lost or corrupted data The driver and firmware version can be verified by the sign on messages displayed or by the version information stored in the driver or tool Note When a new M Systems DiskOnChip product with new features is released a new TrueFFS version is required 28 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems mm Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 6 2 8KB Memory Window in Mobile DiskOnChip Plus 16MB TrueFFS utilizes an SKB memory window in the CPU address space consisting of four 2KB sections
32. 0000h 0 none exists 19h 0000h 0000h Address for alternate OEM extended table Vpp min Write Erase 0023h DQ7 DQ4 1 V DQ3 DQO 100 mV Vpp max Write Erase 1Ch 0036h DQ7 DQ4 1 V DQ3 DQO 100 mV 28h 0002h Flash device interface description 29h 0000h 2 x8 x16 0004h WQ 0000h 9 bytes i multi byte write 2 2002 08 07 F 11 57 TOSHIBA TC58FVM7T2A 7B2A type ADDRESS A6 A0 DATA DQ15 DQ0 DESCRIPTION NET GENI 0002h Number of erase block regions within device Erase Block Region 1 information Bits 0 15 y block number Bits 16 31 z block size z x 256 bytes Erase Block Region 2 information ASCII string PRI 0031h Major version number ASCII 0031h Minor version number ASCII Address Sensitive Unlock 0000h 0 Required 1 Not required Erase Suspend 0 Not supported eh 1 For Read only 2 For Read amp Write Block Protect 47h 0001h 0 Not supported X Number of blocks per group Block Temporary Unprotect 48h 0001h 0 Not supported 1 Supported 0004h Block Protect Unprotect scheme Simultaneous operation 4Ah 0001h 0 Not supported 1 Supported Burst Mode bid S Nor supported Page Mode EX M Nor supported Vacc min voltage 0085h DQ7 DQ4 1 V DQ3 DQ0 100 mV max voltage 4Eh 0095h DQ7 DQ4 1 V DQ3 DQ0 100 mV Top Bottom Boot Block Flag 4Fh 000Xh 2 Bottom Boot 3 Top Boot Program Suspend 50h 0001h 0 Not supported 1 Supported 2002 08
33. 07 F 12 57 TOSHIBA TC58FVM7T2A 7B2A type Bank Organization 57h 0004h 00h Data at 4Ah is zero X Number of Banks Bank1 Region information DUM X Number of blocs Bank1 TOP 20h BOTTOM 27h Bank2 Region information OOK X Number of blocks in Bank 60 BOTTOM 60h Bank3 Region information ORA X Number of blocks in TOP 60h BOTTOM 60h Bank4 Region information X Number of blocks in TOP 27h 20 2002 08 07 13 57 TOSHIBA HARDWARE SEQUENCE FLAGS The TC58FVM7T2A B2A has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation The output data is read out using the same timing as that used when 1 2 RY BY output can be either High or Low The device re enters Read Mode automatically after an auto mode operation has been completed successfully The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read out data with the original data Auto Programming Auto Page Programming DQ7 4 Toggle mT Not selected Auto Erase In Progress TC58FVM7T2A 7B2A CE 2pin type OE in Read Mode The In Erase Read Programming Not selected Toggle Auto Programming Auto Page Programming Toggle ETTEREN EET Exceeded Auto Erase Toggle 1 1 NA 507
34. 1 8V 9 9 1 Design Considerations Design Environment Mobile DiskOnChip Plus provides a complete design environment consisting of Evaluation Boards EVB for enabling software integration and development with Mobile DiskOnChip Plus even before the target platform is available An EVB with Mobile DiskOnChip Plus soldered on it 15 available with an ISA standard connector and a PCI standard connector for immediate plug and play usage Programming solutions GANG programmer o Programming house o On board programming TrueFFS Software Development Kit SDK and DOS utilities DFORMAT GETIMG PUTIMG DINFO Documentation o Data sheet Application notes Technical notes Articles White papers oo o Please visit the M Systems website www m sys com for the most updated documentation utilities and drivers 40 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 9 2 System Interface 9 2 1 Standard Interface Mobile DiskOnChip Plus uses an SRAM like interface that can easily be connected to any microprocessor bus With a standard interface it requires 13 address lines 8 data lines and basic memory control signals OE WEZ as shown in Figure 14 below Typically Mobile DiskOnChip Plus can be mapped to any free 8 memory space In a PC compatible platform it is usually mapped into the BIOS expa
35. 1 8V Table 22 Power Up Timing Parameters Unis mes RSTN asserted pulse with n mus s mSmweesuswes ms WwegusecEy m Dae vao Busen m RSTN mio Avot owad 1 Specified from the final positive crossing of Vcc above 2 5V and VCCQ above 1 65 or 2 5V 2 If the assertion of RSTIN occurs during a flash erase cycle this time could be extended by up to 500 uS 3 Normal read write cycle timing applies This parameter applies only when the cycle is extended until the negation of the BUSY signal 4 Applies to multiplexed interface only 5 When operating DiskOnChip with separate power supplies for VCC and VCCQ it is recommended to turn both power supplies on and off simultaneously Providing power separately either at power on or power off can cause excessive power dissipation Damage to the device may result if this condition persists for more than 1 second 10 4 6 Interrupt Timing The interrupt timing is illustrated in Figure 25 and described in Table 23 Tw IRQ Figure 25 Pulse Width in Edge Mode Table 23 Interrupt Timing Tw IRQ IRQ asserted pulse width edge mode 63 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems mam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V
36. 38 57 TOSHIBA TC58FVM7T2A 7B2A type Block Protect RESET for 4 us PLSCNT 1 Block Protect 2 Command First Bus Write Cycle XXXH 60H Set up Address Addr BPA Block Protect 2 Command Second Bus Write Cycle BPA 60H Wait for 100 us Block Protect 2 LSCNT PLSCNT 1 Command Third Bus Write Cycle SONTE XXXH 40H Verify Block Protect Data 01 Yes Yes Yes Protect Another Block Remove from RESET No Remove from RESET Reset Command Reset Command Block Protect Complete Device Failed BPA Block Address and ID Read Address A6 A1 A0 ID Read Address 0 1 0 2002 08 07 F 39 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS TABLES Top boot block BLOCK ADDRESS BANK BLOCK IE ADDRESS RANGE IE Tome ee someone pp pepe pepe E ppp npe E pp pepe Les pp pepe ne fe Pa Pe TF pp pepper ne pep pepe fe ee pepe coment r epp npe i Pane epee a Pe pep oomen e r e eeaeee e oroare
37. AVD Tsu AVD THO AVD AD 15 0 XXX X ADDR gt 1 Si WEZ DATA U CE1 4 Figure 22 Multiplexed Interface Read Cycle Timing Table 18 Multiplexed Interface Read Cycle Parameters VCC 2 5 3 6V THIZ D VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 5 3 6V VCC 2 5 3 6V Units Min Max Min Max tsu AVD Address to AVD V setup time 5 5 ns tho AVD Address to AVD hold time 7 7 ns Tw AVD AVD low pulse width 12 12 ns tsu CEO V to OE v setup time tho CEO OE to hold time t ns tho CE1 OE or WE to CE hold time 6 ns tsu CE1 to WEZ Y or OE v setup 6 ns time trec OE OE negated to start of next cycle 20 20 ns Read access time RAM 107 116 ns Tacc Read access time all other 96 addresses d tloz D I OE v to D driven 15 15 ns Thiz D OE to D Hi Z delay 23 27 ns Note When designing your board to support also DiskOnChip Plus 32MB or 64MB devices it is not possible to use VCC 2 5 3 6V as these devices only support VCC 2 7 3 6V 58 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Table 19 Multiplexed Interface Read Cycle Parameters VCC 2 7V 3 6V VCCQ VCC VCCQ 1
38. D13 015 RSRVD J RSRVD D10 vec vcca D12 D7 vss K 08 02 011 RSRVD D5 D14 M M L M M M Figure 1 Standard Interface FBGA Ball Diagram Top View 9 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 2 2 2 System Interface See Figure 2 for a simplified I O diagram for a standard interface Host SystemBus 12110 LOOK System Interface Configuration Control Figure 2 Standard Interface Simplified I O Diagram 10 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 2 2 3 Signal Description The ball designations are listed in the signal descriptions presented in logic groups in Table 1 Table 1 Standard Interface Signal Descriptions Description System Interface ST Address bus F7 E7 C7 C3 D3 E3 F3 D2 E2 F2 G2 BHE ST R8 Byte High Enable active low When low data transaction on D 15 8 is enabled Not used and may be left floating when IF is set to 0 8 bit mode Chip Enable active low Input 98 67 7 6 Data bus low byte Input H5 K4 G4 J3 Output D 15 8 H8 K8 H7 J7 IN R8 Data bus high byte Not used and may be left floating when Input K5 J4 H4 K3 IF_CFG is set to 0 8 bit mode Output Confiquration ID 1 0 G9 F8 ST
39. DSP Page read operation 8 words page NeoMagic MiMagic Deep Power Down AMD Alchemy ARM based CPUs NOR Flash m Organization 8M x 16 bits m Power dissipation Read 50 mA max Address increment read 11 mA max Pageread 5 mA max Program Erase 15 mA max Standby 10 uA max m Access time O Random 65 ns CL 30 pF 70 ns CL 100 pF Page 30 ns CL 30 pF 35 ns CL 100 pF m Functions Simultaneous read write Automatic operations program page program chip erase block erase Block erase architecture 8x8KB 255x64KB Modes Fast program Acceleration Data Sheet Rev 0 4 91 SR 001 53 8L M Systems ms Flash Disk Pioneers REVISION HISTORY DiskOnChip Based MCP MS01 D7N7P6 B1 Revision Date Change Description Reference 0 4 November 2003 Added ID Code table Section 1 5 Data Sheet Rev 0 4 91 SR 001 53 8L M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 TABLE OF CONTENTS T Prod ct OVerVieW u u a a Sium ua aus u Su usus sss 3 3 12 Signal Deseriptloris o ree t sd 4 1 3 Internal 5 1 4 MB a T 8 15 128Mbit CMOS NOR Flash Memory ID Code 9 2 5
40. Erase Mode Erase Suspend Mode Program during Erase Suspend Program Suspend during Erase Suspend CFI Mode 1 Only Command Mode is valid 2 Including times when Acceleration Mode is in use 3 If the selected blocks are spread across all nine banks simultaneous operation cannot be carried out 2002 08 07 F 3 57 TOSHIBA TC58FVM7T2A 7B2A type OPERATION MODES In addition to the Read Write Erase Modes the TC58FVM7T2A B2A CE 2 type features many functions including block protection and data polling When incorporating the device into a deign please refer to the timing charts and flowcharts in combination with the description below READ MODE PAGE READ To read data from the memory cell array set the device to Read Mode Read Mode the device can perform high speed random access and Page Read as asynchronous ROM The device is automatically set to Read Mode immediately after power on or on completion of automatic operation A software reset releases ID Read Mode and the lock state which the device enters if automatic operation ends abnormally and sets the device to Read Mode A hardware reset terminates operation of the device and resets it to Read Mode When reading data without changing the address immediately after power on either input a hardware Reset or change CEl or CE2 from H toL ID Read Mode ID Read Mode is used to read the device maker code and device code The mode is useful in that
41. Erase Suspend Read Mode can be verified by checking the Hardware Sequence flag If data is read consecutively from the block selected for Auto Block Erase the DQ2 output will toggle and the DQ6 output will stop toggling and RY BY will be set to High I mpedance Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase Data is written in the usual manner To resume the Auto Block Erase input an Erase Resume command On input of the command the address of the bank on which the Write was being performed must be specified On receiving an Erase Resume command the device returns to the state it was in when the Erase Suspend command was input If an Erase Suspend command is input during the Erase Hold Time the device will return to the state it was in at the start of the Erase Hold Time At this time more blocks can be specified for erasing If an Erase Resume command is input during an Auto Block Erase Erase resumes At this time toggle output of DQ6 resumes 0 is output RY BY 2002 08 07 8 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK PROTECTION Block Protection is a function for disabling writing and erasing specific blocks Applying Vip to RESET and inputting the Block Protect 2 command also performs block protection The first cycle of the command sequence is the Set up command the second cycle the Block Protect command is inp
42. The table below shows CE1 CE2 operation mode BAN Pu 2 ected Notes L H 1 Pulse input SIMULTANEOUS READ WRITE OPERATION The TC58FVM7T2A B2A 2pin type features a Simultaneous Read Write operation Simultaneous Read Write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank TC58FVM7T2A B2A 2 type has a total of four banks 16Mbits 48Mbits 48Mbits 16Mbits Banks can be switched between using the bank addresses A21 A20 CE1 and CE2 For a description of bank blocks and addresses please refer to the Block Address Table and Block Size Table The Simultaneous Read Write operation cannot perform multiple operations within a single bank The table below shows the operation modes in which simultaneous operation can be performed Note that during Auto Program execution or Auto Block Erase operation the Simultaneous Read Write operation cannot read data from addresses in the same bank which have not been selected for operation Data from these addresses can be read using the Program Suspend or Erase Suspend function however SIMULTANEOUS READ WRITE OPERATION STATUS OF BANK ON WHICH OPERATION IS BEING STATUS OTHER BANKS Read Mode ID Read Mode Auto Program Mode Auto Page Program Mode Fast Program Mode Program Suspend Mode Read Mode Auto Block Erase Mode Auto Multiple Block
43. VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 7 3 6V VCC 2 7 3 6V Units Min Max Min Max tsu AVD Address to AVD V setup time ns tho AVD Address to AVD hold time ns Tw AVD AVD low pulse width 12 12 ns tsu AVD WE AVD V to WE setup time 4 4 Trec WE AVD to AVD in next cycle 28 30 ns WE asserted width RAM 48 47 tw WE ns WE asserted width all other addresses 49 48 Twcyc Write Cycle Time 79 79 ns tsu CE0 v to v setup time ns tho CEO WE to CE hold time ns tho CE1 OE WE to CE hold time ns tsu CE1 to WE or OE V setup time ns trec WE WEZ to start of next cycle 20 20 ns Tsu D D to WE setup time RAM 27 28 ns Tho D to D hold time 0 0 ns 1 may be asserted any time before or after WEZ is asserted If is asserted after WEZ all timing relative to WE asserted will be referenced instead to the time of asserted 2 may be negated any time before or after WE is negated If CE is negated before WEZ all timing relative to WE negated will be referenced instead to the time of negated 3 WE may be asserted before or after the rising edge of AVD The beginning of the WEZ asserted pulse width spec is measured from later of the falling edge of WE or the rising edge of AVD 61 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pio
44. Word Mode address shown BA Block address for Auto Block Erase operation Auto Program Operation Control tcMD SS w gt gt DB Note Word Mode address shown PA Program address PD Program data 2002 08 07 F 26 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Page Program Operation 1 2 Control Address A3 21 Address A0 2 CE1 toEH DIN Dour 105 Note Word Mode address shown PA Program address PD Program data 2002 08 07 F 27 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Chip Auto Block Erase Operation 1 Control Address Note Word Mode address shown BA Block address for Auto Block Erase operation 2002 08 07 F 28 57 TOSHIBA TC58FVM7T2A 7B2A type Program Erase Suspend Operation toE DouT Hi Z tsusP tSUSE RY BY Program Erase Mode Suspend Mode RA Read address Program Erase Resume Operation Dour RY BY Suspend Mode Program Erase Mode lt gt lt Program address BK Bank address BA Block address RA Read address Flag Hardware Sequence flag 2002 08 07 F 29 57 TOSHIBA TC58FVM7T2A 7B2A type RY BY during Auto Program Erase Operation Command input sequence WE RY BY tgusv During
45. afu Ls pep pepe pep p e pep e epe e pep n epe e pep pen pepe E pep pen pep pe pep pep pep emere mensem pep pen pepe pep pep pep e 23 2002 08 07 43 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ADDRESS RANGE one pepe Pome pepe n p ie Pee pe epp eT Pe fe fe fae e fe ie Lee pp epp ep pp n e e e e fete a Paw e pee e nsnm npe epp fe fee fe fe n e Pome fe fete fe fe n p perpe Come
46. as depicted in Figure 11 When in Reset mode the Programmable Boot Block in sections 0 and 3 will show the IPL 1KB aliased twice to support systems that search for a checksum at the boot stage from the top and bottom of memory Read cycles from sections 1 and 2 always return the value 00H to create a fixed and known checksum When in Normal mode sections 1 and 2 are used for the internal registers The addresses described here are relative to the absolute starting address of SKB memory window Reset Mode 000H Programmable Boot Block 000H 3FFH 2 aliases 800H 00H 1000H 00H 1800H Programmable Boot Block 000H 3FFH 2 aliases Figure 11 Mobile DiskOnChip Plus 16 Memory Map Section 0 Section 1 Section 2 Section 3 Normal Mode Programmable Boot Block 000H 3FFH 2 aliases Flash area window aliases Control Registers aliases Programmable Boot Block 000H 3FFH 2 aliases 29 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 6 3 8KB Memory Window for Mobile DiskOnChip Plus 32MB TrueFFS utilizes an SKB memory window in the CPU address space consisting of four 2KB sections as depicted in Figure 11 When in Reset mode the Programmable Boot Block in sections 0 and 3 will show the IPL 1KB of the first 16MB of the dual die aliased twice Read c
47. enables Mobile DiskOnChip Plus to provide unmatched physical and performance related benefits It has the highest flash density in the smallest die size available on the market for the best cost structure and the smallest real estate Mobile DiskOnChip Plus devices use 8 bit internal flash access featuring unrivaled write and read performance Mobile DiskOnChip Plus is a cost effective solution for code storage as well as data storage A Programmable Boot Block with eXecute In Place XIP functionality can store boot code replacing the boot ROM to function as the only non volatile memory on board The Programmable Boot Block is for 16MB devices and 2 for 32MB devices This reduces hardware expenditures and board real estate M Systems Download Engine DE 15 automatic bootstrap mechanism that expands the functionality of the Programmable Boot Block to enable CPU and platform initialization directly from Mobile DiskOnChip Plus M Systems patented TrueFFS software technology fully emulates a hard disk to manage the files stored on Mobile DiskOnChip Plus This transparent file system management enables read write operations that are identical to a standard sector based hard disk In addition TrueFFS employs various patented methods such as dynamic virtual mapping dynamic and static wear leveling and automatic bad block management to ensure high data reliability and to maximize flash lifetime TrueFFS binary drivers are available for a
48. ep e e perpe n e ome e e e e e fe ep e 8 e Cer 8 o e e s Do DL 2002 08 07 F 45 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK E ADDRESS RANGE E ICCHERESESESESESESERERERE 7773872773 p Pete fe Pee fe fee fe fe n fee fe fe n p s pee a fe Pa Pe LT pe epe pen peo epe imeem s pe epp n e pe epp n p pe epp ep comer s Emm p pepe pr rmn pes a n e Ee ICRERESERESESESERERERERET E7738 wen fo fee fe fe n
49. features for data and code m NAND based flash technology that enables high density and small die size Proprietary TrueFFS technology for full hard disk emulation high data integrity and maximum flash lifetime m Programmable Boot Block with eXecute In Place XIP functionality using 16 bit access with download support for more code to enable CPU initialization o Platform initialization OS boot m Data integrity with Reed Solomon based Error Detection Code Error Correction Code EDC ECC 1 Data Sheet Rev 0 4 91 SR 001 53 8L M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 m Deep Power Down mode for reduced power Mode control compatible with consumption standard commands m Support for all major mobile operating Boot block architecture systems OSs including THPV067Z02BABD top boot block Symbian OS THPV067Z03BABD bottom boot Smartphone 2002 3 block Pocket PC 2002 3 PSRAM Windows CE CE NET ee G Linux m Organization 4M x 16 bits Nucleus Power dissipation Palm O Operating 50 mA max m Fasy to integrate configurable interface D Standby 100 max Simple SRAM like interface Deep Power Down 5 HA max Compatible with all major CPUs including Access time Texas Instruments OMAP Random 70 ns CL 30 pF Intel StrongARM XScale Page 30 ns CL 30 pF Motorola MX1 m Modes Texas Instruments TMS320VC55x
50. for data and boot code m Hardware data and code protection O Protection key and LOCK signal O Sticky Lock option for lock of boot partition O Protected Bad Block Table Boot Capability Programmable Boot Block with XIP functionality to replace boot ROM O 1KB for 16MB devices O for 32MB devices m Download Engine DE for automatic download of boot code from Programmable Boot Block Boot capabilities O CPU initialization O Platform initialization O OS boot Asynchronous Boot mode to boot CPUs that wake up in burst mode The following abbreviations are used in this document MB for MByte Mb for Mbit 1 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems wam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O Reliability Reed Solomon Error Detection Code Error Correction Code EDC ECC W Guaranteed data integrity even after power failure Transparent bad block management Dynamic and static wear leveling Hardware Compatibility m Configurable interface simple SRAM like or multiplexed A D interface m Compatible with all major CPUs including O ARM based CPUs O Texas Instruments OMAP O Intel StrongARM XScale O AMD Alchemy O Motorola PowerPC MPC8xx O Motorola DragonBall MX1 O Philips PR31700 O Hitachi SuperH SH x NEC VR Series 8 bit 16 bit and 32 bit bus architecture support TrueFFS Software m Full hard disk read write emulati
51. in Reset mode A valid write sequence to Mobile DiskOnChip Plus sets the device in Normal mode This is done automatically by the TrueFFS driver on power up reset sequence end e Switching back from Normal mode to Reset mode can be done by a valid write sequence to Mobile DiskOnChip Plus or by triggering the boot detector circuitry by soft reset e Power down e A valid write sequence initiated by software sets the device from Normal mode to Deep Power Down mode Four read cycles from offset 0 1 set the device back to Normal mode Alternately the device can be set back to Normal mode with an extended access time during a read from the Programmable Boot Block see Section 10 4 1 for read cycle timing e Asserting the RSTIN signal and holding it in this state while in Normal mode puts the device in Deep Power Down mode When the RSTINZ signal is released the device is set in Reset mode Power Up Reset Power Down Power Down Assert RSTIN Reset equence Power Down Assert RSTIN Boot Detect or Software Control 27 Release RSTIN 4 Read from offset 0x1FFF Power Down extended read cycle Normal Mode Mode PARI NK e Software Control Figure 9 Operation Modes and Related Events 24 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile Disk
52. initialization due to a faulty VCC or invalid assertion of the RSTIN input Another failsafe mechanism is designed to overcome possible NAND flash data errors It prevents internal registers from powering up in a state that bypasses the intended data protection In addition in any attempt to sabotage the data structures causes the entire Mobile DiskOnChip Plus to become both read and write protected and completely inaccessible 19 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 3 7 Error Detection Code Error Correction Code EDC ECC NAND flash being an imperfect memory requires error handling Mobile DiskOnChip Plus implements Reed Solomon Error Detection Code EDC A hardware generated 6 byte error detection signature is computed each time a page 512 bytes is written to or read from Mobile DiskOnChip Plus The TrueFFS driver implements complementary Error Correction Code ECC Unlike error detection which 15 required on every cycle error correction is relatively seldom required hence implemented in software The combination of Mobile DiskOnChip Plus s built in EDC mechanism and the TrueFFS driver ensures highly reliable error detection and correction while providing maximum performance The following detection and correction capability is provided for each 512 bytes e Corrects up to two 10 bit symbols including two random bit errors e Corre
53. it allows EPROM programmers to identify the device type automatically Input command sequence With this method simultaneous operation be performed an ID Read command sets the specified bank to ID Read Mode Banks are specified by inputting the bank address BK in thethird Bus Write cycle of the Command To read an ID code the bank address as well as the ID read address must be specified The maker code is output from address 00 the device code is output from address BK 01 From other banks data are output from the memory cells Inputting a Reset command releases ID Read Mode and returns the device to Read Mode Access time in ID Read Mode is the same as that in Read Mode For a list of the codes please refer to the ID Code Table Standby Mode There are two ways to put the device into Standby M ode 1 Control using 1 2 and RESET With the device in Read Mode input 0 3 V to CE1 CE2 and The device will enter Standby Mode and the current will be reduced to the standby current Ipps1 However if the device is in the process of performing simultaneous operation the device will not enter Standby Mode but will instead cause the operating current to flow 2 Control using RESET only With the device in Read Mode input Vss 0 3 V to RESET The device will enter Standby Mode and the current will be reduced to the standby current Ipps1 Even if the device is in the process of perfo
54. note AP DOC 047 Designing DiskOnChip as a Flash Disk and Boot Device Replacement 8 3 2 Non PC Architectures In non PC architectures the boot code is executed from a boot ROM and the drivers are usually loaded from the storage device When using Mobile DiskOnChip Plus as the system boot device the CPU fetches the first instructions from the Mobile DiskOnChip Plus Programmable Boot Block which contains the IPL Since in most cases this block cannot hold the entire boot loader the IPL runs minimum initialization after which the Secondary Program Loader SPL is copied to RAM from flash The remainder of the boot loader code then runs from RAM The IPL and SPL are located in a separate binary partition on Mobile DiskOnChip Plus and can be hardware protected if required For further information on software boot code implementation refer to application note AP DOC 044 Writing an IPL for DiskOnChip Plus 16MByte Devices 38 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 8 3 3 Using Mobile DiskOnChip Plus in Asynchronous Boot Mode Platforms that host CPUs that wake up in burst mode should use Asynchronous Boot mode when using Mobile DiskOnChip Plus as the system boot device During platform initialization certain CPUs wake up in 32 bit mode and issue instruction fetch cycles continuously An XScale CPU for example initiates a 16 bit read cycle
55. only support VCC 2 7 3 6V 56 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Table 17 Standard Interface Write Cycle Parameters VCC 2 7V 3 6V VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 7 3 6V VCC 2 7 3 6V Units Min Max Min Max Tsu A Address to WE v setup time 2 2 ns Tho A WE V to Address hold time 28 28 ns Tw WE WE asserted width 49 48 ns Twcvc Write Cycle Time 79 79 ns Tsu CEO CE Y to WE v setup time ns Tho WE to M hold time ns Tho CE1 OE or WE to CE v hold time 6 6 ns Tsu CE1 to WE OE V setup time 6 6 ns Trec WE WE n to start of next cycle 20 20 ns Tsu D D to WE setup time 27 28 ns Tho D WE to D hold time 0 0 1 may be asserted any time before or after WE is asserted If CE is asserted after WEZ all timing relative to WE asserted should be referenced to the time CE was asserted 2 may be negated any time before or after WE is negated If CE is negated before WEZ all timing relative to WE negated will be referenced to the time CE was negated 57 Data Sheet 1 7 95 SR 000 10 8L A lp M Systems wam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 4 3 Read Cycle Timing Multiplexed Interface Tw AVD
56. operation Hardware Reset Operation WE tRB RESET RY BY Read after RESET tac lt gt 55 tRH lt gt toH Dour Output data valid 2002 08 07 F 30 57 TOSHIBA TC58FVM7T2A 7B2A type BYTE during Read Operation BYTE during Write Operation WE tA 2002 08 07 F 31 57 TOSHIBA TC58FVM7T2A 7B2A type Hardware Sequence Flag DATA Polling _ KZ gt gt toE OE gt N gt lt gt _ lt Last DIN Command Data DQ0 DQ6 tBUSY RY BY Z PA Program address BA Block address Hardware Sequence Flag Toggle bit gt tAST tAST Last Command Data Stop DQ2 6 Toggle Toggle Toggle Toggle tBUSY DQ2 DQ6 stops toggling when auto operation has been completed 2002 08 07 F 32 57 TOSHIBA TC58FVM7T2A 7B2A type Block Protect Operation 2002 08 07 33 57 TOSHIBA TC58FVM7T2A 7B2A type FLOWCHARTS Auto Program Start Auto Program Command Sequence see below DATA Polling or Toggle Bit No Address Address 1 Last Address Yes Auto Program Completed Auto Program Command Sequence address data 555h AAh 2A
57. should be connected to VCC Note When used in a multiplexed interface it 1s not possible to cascade Mobile DiskOnChip Plus 32MB This mode is automatically entered when a falling edge is detected AVD input This edge must occur after RSTIN is negated and before OE CE are both asserted the first read cycle made to Mobile DiskOnChip Plus must observe the multiplex mode protocol Please refer to Section 2 3 for pinout and signal descriptions and to Section 10 4 3 for timing specifications for a multiplexed interface 9 4 Implementing the Interrupt Mechanism 9 4 1 Hardware Configuration To configure the hardware connect the IRQ pin to the host interrupt input Note A nominal 10 pull up resistor must be connected to this pin 9 4 2 Software Configuration Configuring the software to support the IRQ interrupt is performed in two stages Stage 1 Configure the software so that upon system initialization the following steps occur 1 The correct value is written to the Interrupt Control register to configure Mobile DiskOnChip Plus for e Interrupt source Flash ready and or data protection Output sensitivity Either edge or level triggered Note Refer to Section 7 10 for further information on the value to be written to this register 2 The host interrupt 1s configured to the selected input sensitivity either edge or level 3 The handshake mechanism between the interrupt handler and the OS is initiali
58. when an operation has failed RY BY outputs a 0 after the rising edge of WE the last command cycle During an Auto Block Erase operation commands other than Erase Suspend ignored RY BY outputs 1 during an Erase Suspend operation The output buffer for the RY BY is an open drain type drcuit allowing a wired OR connection A pull up resistor must be inserted between Vpp and the RY BY pin 2002 08 07 F 15 57 TOSHIBA TC58FVM7T2A 7B2A type DATA PROTECTION The TC58FVM7T2A B2A includes a function which guards against malfunction or data corruption Protection against Program Erase Caused by Low Supply Voltage To prevent malfunction at power on or power down the device will not accept commands while VDD is below VL Ko In this state command input is ignored If drops below Vi during an Auto Operation the device will terminate Auto Program execution In this case Auto operation is not executed again when Vpp return to recommended Vpp voltage Therefore command need to input to execute Auto operation again When VDD gt make up countermeasure to be input accurately command in system side please Protection against Malfunction Caused by Glitches To prevent malfunction during operation caused by noise from the system the device will not accept pulses shorter than 3 ns Typ inputon 1 2 However if a glitch exceeding 3 ns Typ occurs and the glitch
59. wide range of popular OSs including Symbian OS Pocket PC Smartphone Windows CE NET OSE Nucleus and Linux Customers developing for target platforms not supported by TrueFFS binary drivers can use the TrueFFS Software Development Kit SDK developer guide For customized boot solutions M Systems provides the DiskOnChip Boot Software Development Kit BDK developer guide Mobile DiskOnChip Plus is designed for compatibility and easy scalability All capacities of Mobile DiskOnChip Plus have the same ballout and are interchangeable Greater capacities may easily be obtained by cascading up to four 16MB devices or two 32MB devices with no additional glue logic This upgrade path provides a flash disk of up to 64MB 512Mb while remaining totally transparent to the file system and user 8 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 2 2 Standard Interface 2 2 1 Ball Diagram See Figure 1 for the Mobile DiskOnChip Plus standard interface FBGA ball diagram To ensure proper device functionality balls marked RSRVD are reserved for future use and should not be connected 1 2 3 4 5 6 7 8 9 10 M M B RSRVD RSRVD WE A8 11 u N AN A3 A6 RSRVD RSTIN RSRVD RSRVD A12 RSRVD A2 A5 BUSY RSRVD A9 LOCK RSRVD F M IF 10 IDO M AO vss D1 D6 RSRVD ID1 M H CE OE D9 D3 D4
60. 1 5 Wear Leveling Flash memory can be erased a limited number of times This number is called the erase cycle limit or write endurance limit and 15 defined by the flash array vendor The erase cycle limit applies to each individual erase block in the flash device In Mobile DiskOnChip Plus the erase cycle limit of the flash 15 300 000 erase cycles This means that after approximately 300 000 erase cycles the erase block begins to make storage errors at a rate significantly higher than the error rate that 1s typical to the flash In a typical application and especially if a file system is used a specific page or pages are constantly updated e g the page s that contain the FAT registry etc Without any special handling these pages would wear out more rapidly than other pages reducing the lifetime of the entire flash To overcome this inherent deficiency TrueFFS uses M Systems patented wear leveling algorithm The wear leveling algorithm ensures that consecutive writes of a specific sector are not written physically to the same page in the flash This spreads flash media usage evenly across all pages thereby maximizing flash lifetime TrueFFS wear leveling extends the flash lifetime 10 to 15 years beyond the lifetime of a typical application Dynamic Wear Leveling TrueFFS uses statistical allocation to perform dynamic wear leveling on newly written data This not only minimizes the number of erase cycles per block it also minimizes the tot
61. 6 7 TOSHIBA TC51WHM616A Notes 1 N O UI N Stresses greater than listed under Absolute Maximum Ratings may cause permanent damage to the device All voltages are reference to GND IDDO depends on the cycle time IDDO depends on output loading Specified values are defined with the output open condition AC measurements are assumed tF 5 ns Parameters top topo and topw define the time at which the output goes the open condition and are not output voltage reference levels Data cannot be retained at deep power down stand by mode If OE ishigh during the write cycle the outputs will remain at high impedance During the output state of 1 signals input signals of reverse polarity must not be applied If CE1 or LB UB goes LOW coincident with or after WE goes LOW the outputs will remain at high impedance If CE1 or LB UB goes HIGH coincident with or before WE goes HIGH the outputs will remain at high impedance 2002 05 22 7 7 yy M Systems ms Flash Disk Pioneers HoW TO Us USA M Systems Inc 8371 Central Ave Suite Newark CA 94560 Phone 1 510 494 2090 Fax 1 510 494 5545 Japan M Systems Japan Inc Asahi Seimei Gotanda Bldg 5 25 16 Higashi Gotanda Shinagawa ku Tokyo 141 0022 Phone 8 1 3 5423 8101 Fax 81 3 5423 8102 Taiwan M Systems Asia Ltd Room B 13 F No 133 Sec 3 Min Sheng East Road Taipei
62. 65 1 9V Symbol Description VCC 2 7 3 6V VCC 2 7 3 6V Units Min Max Min Max tsu AVD Address to AVD V setup time 5 5 ns tho AVD Address to AVD hold time 7 7 ns Tw AVD AVD low pulse width 12 12 ns tsu CEO V to OE setup tho CEO OE to hold time ns tho CE1 OE or WE to CE v hold time 6 6 ns tsu CE1 to WEZ v or OE v setup 6 6 ns time trec OE OE negated to start of next cycle 20 20 ns Read access time RAM 101 111 ns Tacc Read access time all other 92 addresses tloz D 3 OE Y to D driven 15 15 ns Thiz D OE to D Hi Z delay 23 27 ns 1 may be asserted any time before or after OE is asserted If CE is asserted after OE all timing relative to OE asserted will be referenced instead to the time of asserted 2 may be negated any time before or after is negated If is negated before OE all timing relative to OE negated will be referenced instead to the time of CEZ negated 3 No load C 0 pF 59 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 4 4 Write Cycle Timing Multiplexed Interface Tw AVD AVD TREC WE AVD AD 15 0 DATA NEXT ADDR THO CE1 eI Tsu AVD WE Tw WE TREC WE W
63. 8V 3 3V l 1 0 1 uF 10 nF 0 1 uF 10 nF I I 1 20 Z Address Data AD 15 0 BUSY gt Busy Mobile DiskOnChip Write Enable Plus AVD AVD Output Enable OE Chip Enable CE Reset t RSTIN LOCKE Chip ID lt 00 VSS NY Figure 15 Multiplexed System Interface 9 3 Connecting Signals 9 3 1 Standard Interface Mobile DiskOnChip Plus uses standard SRAM like control signals which should be connected as follows Address A 12 0 Connect these signals to the host address bus e Data D 15 0 Connect these signals to the host data bus Write WE and Output Enable OE Connect these signals to the host WR RD signals respectively Chip Enable CE Connect this signal to the memory address decoder e Chip Identification ID 0 1 Both signals must be connected to GND if only one Mobile DiskOnChip Plus 15 being used If more than one refer to Section 9 6 for more information on cascaded configuration Power On Reset In RSTIN Connect this signal to the host Power On Reset signal e Busy BUSY Connect this signal to an input port It indicates when the device is ready for first access after hardware reset e Interrupt IRQ Connect this signal to the host interrupt to release the host of this task and improve performance Byte High Ena
64. 9 DQ9 D9 D9 94 010 0010 010 010 5 011 0011 011 011 J7 D12 DQ12 D12 D12 H7 013 0013 013 013 014 0014 014 014 H8 D15 DQ15 D15 D15 J5 VCCf VDD J6 VCCps G5 NC 6 Data Sheet Rev 0 4 91 SR 001 53 8L M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 Internal Connections 128Mb 64Mb 128Mb Mobile Location Signal NOR PSRAM _ DiskOnChip Plus 15 LOCK LOCK K6 NC AO of the DiskOnChip Me 0 must connected externally to VSS G10 RSTIN RSTIN G3 vss vss vss VSS J9 VSS vss vss VSS E1 G1 VSS VSS VSS VSS IDO ID1 BHE to BYTE to Data Sheet Rev 0 4 91 SR 001 53 8L M M Systems ms Flash Disk Pioneers 1 4 Block Diagram DiskOnChip Based MCP MS01 D7N7P6 B1 Figure 2 shows a block diagram of all components that comprise the DiskOnChip based MCP including their special and interconnected signals 0 22 0 22 WP ACC RESET CEf1 VCCf VSS RY BY lt A0 A21 VCCps vss 64Mbit Pseudo SRAM CE1ps CE2ps UB LB A0 A11 WE VCCm VCCqm VSS 128Mbit CEm Mobile DiskOnChip Plus LOCK RSTIN BUSY eee Figure 2 DiskOnC
65. Ah 55h 555h A0h Program Address Program Data Note The above command sequence takes place in Word Mode 2002 08 07 34 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Page Program START Auto page program command sequence see below DATA Polling or Toggle Bit No Address Address 1 Last address Yes Auto Program Completed 555h AAh 2AAh 55h 555h E6h Program address A2 1 A1 0 A0 0 Program data Program address A2 0 A1 0 A0 0 Program data v Program address 2 1 1 0 0 1 Program data Program address 2 0 1 0 0 1 Program data v Program address 2 1 1 1 0 0 Program data v Program address 2 0 1 1 0 0 Program data Program address 2 0 1 1 0 1 Program data Program address 2 1 1 1 0 1 Program data 2002 08 07 F 35 57 TOSHIBA TC58FVM7T2A 7B2A type Fast Program Fast Program Set Command Sequence see below Fast see below DATA Polling or Toggle Bit No Address Address 1 Last Address see below Fast Program Completed Fast Program Set Command Sequence Fast Program Command Sequence Fast Program Reset Command Sequence address data address data address data 555h AAh XXXh A0h XXXh 90h 2AAh 55h Program Address Program Data XXXh F0h 555h 20h 2002 08 07 F 36 57 TOSHIBA
66. Auto Program operation is terminated in this manner the data written so far is invalid Any attempt to program a protected block is ignored In this case the device enters Read Mode 3 us after the rising edge of the WE signal in the fourth Bus Write cycle If an Auto Program operation fails the device remains in the programming state and does not automatically return to Read Mode The device status is indicated by the Hardware Sequence flag Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure If a programming operation fails the block which contains the address to which data could not be programmed should not be used The device allows Os to be programmed into memory cells which contain a 1 1s cannot be programmed into cells which contain Os If this is attempted execution of Auto Program will fail This is a user error not a device error A cell containing O must be erased in order to set it to 1 Auto Page Program Mode Auto Page Program is a function which enables to simultaneously program 8words or 16bytes data In this mode Program time for 128M bit is less than 60 compare with Auto program mode In word mode input page program command during first bus write cycle to third bus write cycle Input program data and address 0 1 2 0 0 0 in forth bus write cycle Input increment address and program data during fifth bus write cycleto eleventh bus write cyde After input eleventh
67. Byte 1 8V 61 9 tn tt ota ie mda teet 28 6 2 8KB Memory Window in Mobile DiskOnChip Plus 16 29 6 3 8KB Memory Window for Mobile DiskOnChip Plus 32 0 30 7 Register Descriptions DEO alacer a ba a tues qanqa saa REL Cox 31 7 1 Definitlon of Terms cer e n diee de Sa tut te piv eue 31 1 2 ResetValues s net ph aim hia tp pad 31 7 3 Chip Identification ID 31 7 4 No Operation 32 Test Register zx suni Aa Sa Aes le en See 32 7 6 DiskOnChip Control Register Control Confirmation 33 7 7 Device ID Select Register reae t e et toe e det ee eu ee stt eur odd ee ee 34 7 8 Configuration eee ete bottle ace aed etis 34 79 Output Control REQ teet ie Lose che eats Lectt be ues ab Sa 35 7 10 Interrupt Control eae ee 35 7 11 Toggle Beglster 36 8 Booting from Mobile DiskOnChip Plus nennen 37 ST M 37 8 2 Boot Procedure in PC Compatible Platforms
68. CEO OE to hold time ns Tho CE1 OE WE to CE v hold time ns Tsu CE1 to WE v v setup time ns Trec OE OE negated to start of next cycle 20 20 ns DM Read access time 101 111 ns Read access time all other addresses 82 92 ns Tloz D OE to D driven 15 15 ns Thiz D OE to D Hi Z delay 23 27 ns Asynchronous Boot Mode tacc A RAM Read access time from A 9 1 89 98 ns tho A D Data hold time from A 9 1 RAM 0 0 ns 1 CE may be asserted any time before or after OE is asserted If is asserted after OE all timing relative to when OE was asserted will be referenced to the time was asserted 2 may be negated any time before or after OE is negated If CE is negated before OEZ all timing relative to when OE was negated will be referenced to the time CE was negated 54 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 3 The boot block is located at addresses 0000 07 and 1800H 1FFFH Registers located at addresses 0800H 17FFH have a faster access time than the boot block Access to the boot block is not required after the boot process has completed 4 Systems that do not access the boot block may implement only the read access timing for all other registers This will increase the systems performance however it will prevent acce
69. Environmental Specifications 10 1 1 Operating Temperature Ranges Commercial Temperature Range 0 C to 70 C Extended Temperature Range 40 C to 85 C 10 1 2 Thermal Characteristics Table 5 Thermal Characteristics Thermal Resistance C W Junction to Case 0JC 30 Junction to Ambient 0JA 85 10 1 3 Humidity 10 to 90 relative non condensing 10 1 4 Endurance Mobile DiskOnChip Plus is based on NAND flash technology which guarantees a minimum of 300 000 erase cycles Due to the TrueFFS wear leveling algorithm the life span of all DiskOnChip products is significantly prolonged M Systems website www m sys com provides an online life span calculator to facilitate application specific endurance calculations 10 2 Disk Capacity Table 6 Disk Capacity 16MB in bytes Formatted Capacity Sectors Formatted Capacity Sectors 16 302 080 31 840 16 367 616 31 968 Table 7 Disk Capacity 32MB in bytes Formatted Capacity Sectors Formatted Capacity Sectors 32 800 768 64 064 32 724 992 63 916 48 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 3 Electrical Specifications 10 3 1 Absolute Maximum Ratings Table 8 Absolute Maximum Ratings DC I O Supply Voltage vcco 0 6 to 4 6 v J Maximum duration of applying VCCQ without VCC or VCC without TsuppLy 500 mS See Note 3 VCCQ 1 Permanent device da
70. OnChip Plus 16 32MByte 1 8V 5 1 Normal Mode This is the mode in which standard operations involving the flash memory are performed Normal mode 18 automatically entered when a valid write sequence is sent to the DiskOnChip Control register and Control Confirmation register The boot detector circuit triggers the software to set the device to Normal mode A write cycle occurs when both the CE and WE inputs are asserted Similarly a read cycle occurs when both the CE and OE inputs are asserted Because the flash controller generates its internal clock from these CPU cycles and some read operations return volatile data it is essential that the specified timing requirements contained in Section 10 4 1 be met It is also essential that read and write cycles are not interrupted by glitches or ringing on the WE OE address inputs All inputs to Mobile DiskOnChip Plus are Schmidt Trigger types to improve noise immunity In Normal mode Mobile DiskOnChip Plus responds to every valid hardware cycle When there is no activity it is possible to reduce the power consumption to a typical deep power down current of 10 pA 16MB or 20 32MB by setting the device in Deep Power Down mode 5 2 Reset Mode In Reset mode Mobile DiskOnChip Plus ignores all write cycles except for those to the DiskOnChip Control register and Control Confirmation register All register read cycles return a value of 00H Before attempting to perform a re
71. Q 3 3V Outputs open 4 If DiskOnChip is not set to Deep Power Down mode and 15 not accessed for read write operation standby supply current is 400 typ to 600 max 5 Deep Power Down mode is achieved by asserting RSTIN when in Normal mode or writing the proper write sequence to the DiskOnChip registers and asserting the CE input VCCQ See Section 5 3 for further details 51 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 3 4 AC Operating Conditions Environmental and timing specifications are based on the following conditions Table 13 AC Test Conditions 52 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems mam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 4 Timing Specifications 10 4 1 Read Cycle Timing Standard Interface ete A 12 0 BHE CER WE Tioz D THIZ D D 15 0 Figure 19 Standard Interface Read Cycle Timing Tsu A azo Ox a leac Trio Tsu CE0 Tsu CE1 THO CEO WE THIZ D TLoz D D 15 0 Dx Figure 20 Standard Interface Read Cycle Timing Asynchronous Boot Mode 53 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems ms Flash Disk Pioneers
72. S boot device when configured as drive C it must be formatted as a bootable device by copying the OS files onto it This 15 done by using the SYS command when running DOS 8 3 Boot Replacement 8 3 1 PC Architectures In current PC architectures the first CPU fetch after reset is negated is mapped to the boot device area also known as the reset vector The reset vector in PC architectures is located at address FFFFO by using a Jump command to the beginning of the BIOS chip usually F0000 or E0000 The CPU executes the BIOS code initializes the hardware and loads Mobile DiskOnChip Plus software using the BIOS expansion search routine e g D0000 Refer to Section 8 2 for a detailed explanation on the boot sequence in PC compatible platforms Mobile DiskOnChip Plus implements both disk and boot functions when it replaces the BIOS chip To enable this Mobile DiskOnChip Plus requires a location at two different addresses e After power up Mobile DiskOnChip Plus must be mapped in segment so that the CPU fetches the reset vector from address FFFF0 where Mobile DiskOnChip Plus 15 located e After the BIOS code is loaded into RAM and starts execution Mobile DiskOnChip Plus must be reconfigured to be located in the BIOS expansion search area e g D0000 so it can load the TrueFFS software This means that the signal must be remapped between two different addresses For further information on how to achieve this refer to application
73. Supply G3 J9 Ground All VSS balls must be connected Supply Reserved RSRVD K6 Reserved signal that is not connected internally Note Future DiskOnChip devices will use this pin as a clock input To be forward compatible this pin can already be connected to the system CLK or to VCC when the clock input feature is not required Other See All reserved signals are not connected internally and must be left Figure 1 floating to guarantee forward compatibility with future products They should not be connected to arbitrary signals M Mechanical These balls are for mechanical placement and are not connected internally A Alignment This ball is for device alignment and is not connected internally The following abbreviations are used IN Standard non Schmidt input ST Schmidt Trigger input OD Open drain R8 Nominal 22 KQ pull up resistor enabled only for 8 bit interface mode IF_CFG input is 0 R 3 7 MQ nominal pull up resistor Note For forward compatibility with future DiskOnChip 7x10 FBGA products additional pads are required Please refer to application note AP DOC 067 Preparing Your PCB Footprint for the DiskOnChip BGA Migration Path for detailed information 12 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 2 3 Multiplexed Interface 2 3 4 Ball Diagram See Figure 3 for the Mobile DiskOnChip Plus multiplexed interfa
74. TC58FVM7T2A 7B2A type Auto Erase Auto Erase Command Sequence see below DATA Polling or Toggle Bit Completed Auto Chip Erase Command Sequence Auto Block Auto Multi Block Erase Command Sequence address data address data 555h AAh 555h AAh 2AAh 55h 2AAh 55h 555h 80h 555h 80h 555h AAh 555h AAh 2AAh 55h 2AAh 55h 555h 10h Block Address 30h Block Address 30h Additional address inputs during Auto Multi Block Erase Block Address 30h Note The above command sequence takes place in Word Mode 2002 08 07 F 37 57 TOSHIBA DQ7 DATA Polling Read Byte 200 007 Addr gt Yes DQ7 Data No Yes 1 2 D 9 2 Yes DQ6 Toggle Bit 2 D 5 9 2 2 D 9 2 Byte address for programming TC58FVM7T2A 7B2A type 1 DQ7 must be rechecked even if DQ5 1 because DQ7 may change at the same time as DQ5 Pass 1 006 must be rechecked even if 005 1 because DQ6 may stop toggling at the same time that DQ5 changes to 1 Pass Any of the addresses within the block being erased during a Block Erase operation Don t care during a Chip Erase operation Any address not within the current block during an Erase Suspend operation 2002 08 07
75. Taiwan R O C Tel 886 2 8770 6226 Fax 886 2 8770 6295 DiskOnChip Based MCP MS01 D7N7P6 B1 China M Systems China Ltd Room 121 122 Bldg 2 International Commerce amp Exhibition Ctr Hong Hua Rd Futian Free Trade Zone Shenzhen China Phone 86 755 8348 5218 Fax 86 755 8348 5418 Europe M Systems Ltd 7 Atir Yeda St Kfar Saba 44425 Israel Tel 972 9 764 5000 Fax 972 3 548 8666 Internet http www m sys com General Information info m sys com Sales and Technical Information techsupport m sys com This document is for information use only and is subject to change without prior notice M Systems Flash Disk Pioneers Ltd assumes no responsibility for any errors that may appear in this document No part of this document may be reproduced transmitted transcribed stored in a retrievable manner or translated into any language or computer language in any form or by any means electronic mechanical magnetic optical chemical manual or otherwise without prior written consent of M Systems M Systems products are not warranted to operate without failure Accordingly in any use of the Product in life support systems or other applications where failure could cause injury or loss of life the Product should only be incorporated in systems designed with appropriate and sufficient redundancy or backup features Contact your local M Systems sales office or distributor or visit our website at www m
76. Valid to RY BY Delay during Suspend Mode RESET Low Level Hold Time gt RESET Low Level to Read Mode m gt lt Recovery Time RESET Recovery Time gt 2 1 2 Set uptime BYTE Transition BYTE to Output High Z Program Suspend Command to Suspend Mode Page Program Suspend Command to Suspend Mode Program Resume Command to Program Mode Erase Suspend Command to Suspend Mode Erase Resume Command to Erase Mode f al gt gt gt o gt gt gt UJ m c m n n n n n 00 70 79 gt o 2 2 o o t 7 2 2 o o o 7 5 5 2002 08 07 18 57 TOSHIBA TC58FVM7T2A 7B2A type TIMING DIAGRAMS Thetiming which is described in the following pages is the same as thetiming CE2 is used Read ID Read Operation Address toH tpF1 tAHW gt WE 2002 08 07 19 57 TOSHIBA TC58FVM7T2A 7B2A type Page Read Operation gt X tacc toE lt gt 2 277 Read after command input Only Hidden Read 2002 08 07 20 57 TOSHIBA TC58FVM7T2A 7B2A type Command Write Operation This is the timing of the Command Write Operation The timing which is described
77. _ Identification For Mobile DiskOnChip 16MB up to four chips can be cascaded in the same memory window according to the following assignment Chip 1 1 IDO VSS VSS 0 0 required for single chip Chip 2 01 IDO VSS VCC 0 1 Chip 3 ID1 100 VCC VSS 1 0 Chip 4 1 IDO VCC VCC 1 1 For Mobile DiskOnChip 32MB up to two chips can be cascaded in the same memory window according to the following assignment Chip 1 ID12VSS IDO VSS required for single chip Chip 2 ID12VSS IDO VCC 4 ST Interface Configuration 1 for 16 bit interface mode 0 for 8 bit interface mode LOCK E8 ST Lock active low When active provides full hardware data protection of selected partitions Control BUSY E5 Busy active low open drain Indicates that DiskOnChip is initializing and should not be accessed 10 pull up resistor is required even if the ball is not used IRQ Ia Interrupt Request Requires a 10 pull up resistor Output RSTIN Reset active low Input power supply Sets the logic 1 voltage level range of I O balls pins VCCQ may be either 2 5V to 3 6V or 1 65V to 2 0V Requires 10 nF and 0 1 uF capacitor 11 Data Sheet Rev 1 7 95 SR 000 10 8L l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Input ae Signal Eg Ball No Description Type vcc J5 Device supply Requires 10 nF 0 1 pF capacitor
78. a Sheet Rev 0 4 M M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 1 2 Signal Descriptions Table 1 contains signal descriptions based on the ball diagram in Figure 1 Table 1 DiskOnChip Based MCP Signal Descriptions Address bus Input A1 A11 used by Mobile DiskOnChip Plus 0 21 used by NOR flash A22 reserved for future NOR expansion 0 20 used by PSRAM CEm Chip Enable active low Mobile DiskOnChip Plus Input CEf2 Enable 1 2 active low NOR flash CE1ps CE2ps Enable 1 active low Chip Enable 2 active high PSRAM Output Enable active low Ready active high Busy active low NOR flash multiplexed with IRQ interrupt request Mobile DiskOnChip Plus Lock active low Mobile DiskOnChip Plus When active provides full hardware data protection of selected partitions co ss C 4 Data Sheet Rev 0 4 91 SR 001 53 8L M M Systems ms Flash Disk Pioneers 1 3 Internal Interconnections DiskOnChip Based MCP MS01 D7N7P6 B1 Every component in the DiskOnChip based MCP behaves as if it were a separate device Each component has a separate ball for its Chip Enable CE signal as well as a separate ball for power supply Table 2 shows the internal connections Note Some signals described in the individual data sheets have been internally connected to VSS or VCC Other signals are shared and therefore have been renam
79. a polling is asynchronous with the OE signal 2002 08 07 14 57 TOSHIBA TC58FVM7T2A 7B2A type 006 Toggle bit 1 The device status can be determined by the Toggle Bit function during an Auto Program or auto erase operation The Toggle bit begins toggling on the rising edge of WE the last bus cycle DQ6 alternately outputs 0 or a 1 for each OE access while CE1 or while the device is busy When the internal operation has been completed toggling stops and valid memory cell data can be read by subsequent reading If the operation fails the DQ6 output toggles If an attempt is made to execute an Auto Program operation on a protected block DQ6 will toggle for around 3 us It will then stop toggling If an attempt is made to execute an auto erase operation on a protected block DQ6 will toggle for around 400 us It will then stop toggling After toggling has stopped the device will return to Read Mode DQ5 internal time out If the internal timer times out during a Program or Erase operation DQ5 outputs a 1 This indicates that the operation has not been completed within the allotted time Any attempt to program a 1 into a cell containing a 0 will fail see Auto Program Mode In this case DQ5 outputs 1 Either a hardware reset or a software Reset command is required to return the device to Read Mode DQ3 Block Erase timer The Block Erase operation starts 50 us the Erase Hold Time after the rising edg
80. able Boot Block space Address hex 1006 1076 Type Read Write Reset Value 10H Bir Bite Bis RFU 0 RST LAT BDET MDWREN Mode 1 0 Mode These bits select the mode of operation as follows 00 Reset 01 Normal 10 Deep Power Down MDWREN Mode Write Enable This bit must be set to 1 before changing the mode of operation BDET Boot Detect This bit is set whenever the device has entered Reset mode as a result of the Boot Detector triggering It is cleared by writing a 1 to this bit result of the RSTINZ input signal being asserted or the internal voltage detector triggering It is cleared by writing a 1 to this bit 5 7 Reserved for future use RST LAT Reset Latch This bit is set whenever the device has entered the Reset mode as a 33 Data Sheet Rev 1 7 95 SR 000 10 8L 77 M Systems Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 7 7 Device ID Select Register Description In a cascaded configuration this register controls which device provides the register space The value of bits ID 0 1 is compared to the value of the ID configuration input balls as defined in Section 9 6 The device whose ID input balls matches the value of bits ID 0 1 responds to read and write cycles to register space Address hex 1008 Type Read Write Reset Value 00H Bits Bito RFU 0 ID 1 0 to Be
81. al number of erase cycles Because a block erase 15 the most time consuming operation dynamic wear leveling has a major impact on overall performance This impact cannot be noticed during the first write to flash since there is no need to erase blocks beforehand but it 15 more and more noticeable as the flash media becomes full 27 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Static Wear Leveling Areas on the flash media may contain static files characterized by blocks of data that remain unchanged for very long periods of time or even for the whole device lifetime If wear leveling were only applied on newly written pages static areas would never be cycled This limited application of wear leveling would lower life expectancy significantly in cases where flash memory contains large static areas To overcome this problem TrueFFS forces data transfer in static areas as well as in dynamic areas thereby applying wear leveling to the entire media 6 1 6 Power Failure Management TrueFFS uses algorithms based on erase after write instead of erase before write to ensure data integrity during normal operation and in the event of a power failure Used areas are reclaimed for erasing and writing the flash management information into them only afier an operation is complete This procedure serves as a check on data integrity The erase after write algo
82. ble This signal definition is compatible with 16 bit platforms that use the BHE BLE protocol This signal is only relevant during the boot phase e Hardware Lock LOCK This signal prevents the use of the write protect key to disable the protection e 8 16 Bit Configuration IF This signal is required for configuring the device for 8 or 16 bit access mode When negated the device is configured for 8 bit access mode When asserted 16 bit access mode is operative 42 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Mobile DiskOnChip Plus derives its internal clock signal from the OE and WE inputs Since access to Mobile DiskOnChip Plus registers is volatile much like a FIFO or UART ensure that these signals have clean rising and falling edges and are free from ringing that can be interpreted as multiple edges PC board traces for these three signals must either be kept short or properly terminated to guarantee proper operation 9 3 2 Multiplexed Interface Mobile DiskOnChip Plus can also be configured to work with a multiplexed interface where data and address line are multiplexed In this configuration AVD input is driven by the host s AVD signal and the D 15 0 pins used for both address and data are connected to the host AD 15 0 bus DiskOnChip address lines A 12 0 and BHE should be connected to VSS IF CFG
83. boot device is required on the motherboard Mobile DiskOnChip Plus 16MB contains a 1KB Programmable Boot Block whereas Mobile DiskOnChip Plus 32MB contains a 2KB Programmable Boot Block The Download Engine DE described in the next section expands the functionality of this block by copying the boot code from the flash into the boot block When the maximum number of Mobile DiskOnChip Plus devices are cascaded the Programmable Boot Block provides 4KB of boot block area The Programmable Boot Block of each device is mapped to a unique address space 3 6 Download Engine DE Upon power up or when the RSTIN signal is asserted high the DE automatically downloads the Initial Program Loader IPL from the flash to the Programmable Boot Block The IPL is responsible for starting the boot process The download process is quick 1 3 ms max and is designed so that when the CPU accesses Mobile DiskOnChip Plus for code execution the IPL code is already located in the Programmable Boot Block In addition the DE downloads the Data Protection Structures DPS from the flash to the Protection State Machines PSMs so that Mobile DiskOnChip Plus is secure and protected from the first moment it is active During the download process Mobile DiskOnChip Plus asserts the BUSY signal to indicate to the system that it is not yet ready to be accessed After BUSY is negated the system can access Mobile DiskOnChip Plus A failsafe mechanism prevents improper
84. bus write page program operation start byte mode input increment address and program data of A 1 A0 A1 A2 0 0 0 0 1 0 1 2 1 1 1 1 during fifth bus write cycle to nineteenth bus write cycle Fast Program Mode Fast Program is a function which enables execution of the command sequence for the Auto Program to be completed in two cycles In this mode the first two cycles of the command sequence which normally requires four cycles are omitted Writing is performed in the remaining two cycles To execute Fast Program input the Fast Program command Write in this mode uses the Fast Program command but operation is the same at that for ordinary Auto Program The status of the device is indicated by the Hardware Sequence flag and read operations can be performed as usual To exit this mode the Fast Program Reset command must be input When the command is input the device will return to Read Mode Acceleration Mode The TC58FVM 7T2A B2A CE 2pin type features Acceleration Mode which allows write time to be reduced Applying VACC to WP or ACC automatically sets the device to Acceleration Mode In Acceleration Mode Block Protect Mode changes to Temporary Block Unprotect Mode Write Mode changes to Fast Program Mode Modes are switched by the WP ACC signal thus there is no need for a Temporary Block Unprotect operation or to set or reset Fast Program Mode Operation of Write is the same as in Auto Program Mode Removing VAcc
85. but after the first word is read it continues to hold and OE asserted while it increments the address and reads additional data as a burst A StrongARM CPU wakes up in 32 bit mode and issues double word instruction fetch cycles Since Mobile DiskOnChip Plus derives its internal clock signal from OE and WE inputs it cannot distinguish between these burst cycles To support this type of access Mobile DiskOnChip Plus needs to be set in Asynchronous Boot mode To set Mobile DiskOnChip Plus in Asynchronous Boot mode set the byte RAM MODE SELECT to 8FH This can be done through the Mobile DiskOnChip Plus format utility or by customizing the IPL code For more information on the format utility refer to the DiskOnChip Software Utilities user manual or the TrueFF S Software Development Kit SDK developer guide For further details on customizing the IPL code refer to application note AP DOC 044 Writing an IPL for DiskOnChip Plus 16MByte Once in Asynchronous Boot mode the CPU can fetch its instruction cycles from the Mobile DiskOnChip Plus Programmable Boot Block After reading from this block and completing boot Mobile DiskOnChip Plus returns to derive its internal clock signal from the and WEZ inputs Please refer to Section 10 4 for read timing specifications for Asynchronous Boot mode 39 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte
86. ce FBGA ball diagram To ensure proper device functionality balls marked RSRVD are reserved for future use and should not be connected 1 2 3 4 5 6 7 8 9 10 uw n oy ad ub P ME See dm f m QU 6 an e NS RSRVD p RC ay m Eon dem a E WEGE LX ELO oie as eae Au H a Pa s S noa E Imm A PE PLU RWV IL K More L 4 6 m w Figure 3 Multiplexed Interface Mobile DiskOnChip Plus 16MB FBGA Ball Diagram Top View 13 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 2 3 2 System Interface See Figure 4 for a simplified I O diagram RSTIN CE OE WE Host System Bus Mobile DiskOnChip Plus AD 15 0 ID0 AVD LOCK J System Interface Configuration Control Figure 4 Multiplexed Interface Simplified I O Diagram 14 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 2 3 3 Signal Description The ball designations are listed in the signal descriptions pres
87. ced data and code security and protection Located on the main route of traffic between the host and the flash this block monitors and controls all data and code transactions to and from Mobile DiskOnChip Plus 3 4 1 Read Write Protection Data and code protection 15 implemented through a Protection State Machine PSM The user can configure one or two independently programmable areas of the flash memory as read protected write protected or read write protected A protection area may be protected by either both of these hardware mechanisms e 64 bit protection key Hard wired LOCK signal The size and location of each area 1s user defined to provide maximum flexibility for the target platform and application requirements The configuration parameters of the protected areas are stored on the flash media and are automatically downloaded from the flash to the PSM upon power up to enable robust protection throughout the flash lifetime In the event of an attempt to bypass the protection mechanism illegally modify the protection key or in any way sabotage the configuration parameters the entire DiskOnChip becomes both read and write protected and 18 completely inaccessible For further information on the hardware protection mechanism refer to Section 4 18 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 3 4 2 Unique Identification UID Number Eac
88. cts single bursts up to 11 bits Detects single bursts up to 31 bits and double bursts up to 11 bits e Detects up to 4 random bit errors 3 8 Data Pipeline Mobile DiskOnChip Plus uses a two stage pipeline mechanism designed for maximum performance while enabling on the fly data manipulation such as read write protection and Error Detection Error Correction 3 9 Control amp Status The Control amp Status block contains registers responsible for transferring the address data and control information between the DiskOnChip TrueFFS driver and the flash media Additional registers are used to monitor the status of the flash media ready busy and of the DiskOnChip controller For further information on the Mobile DiskOnChip Plus registers refer to Section 6 3 3 10 Flash Architecture A 16MB flash bank consists of 1024 blocks organized in 32 pages as follows e Each page contains 512 bytes of user data and 16 byte extra area that is used to store flash management and EDC ECC signature data as shown in Figure 6 A page is the minimal unit for read write operations e Block Each block contains 32 pages total of 16KB as shown in Figure 7 A block is the minimal unit that can be erased and 15 sometimes referred to as an erase block Flash Management amp ECC EDC Signature User Data 0 5 KB Figure 6 Page Structure 20 Data Sheet Rev 1 7 95 SR 000 10 8L 77 M Systems Mobile DiskOnC
89. ds the TrueFFS driver into system memory installs Mobile DiskOnChip Plus as a disk in the system and then returns control to the BIOS code The operating system subsequently identifies Mobile DiskOnChip Plus as an available disk TrueFFS responds by emulating a hard disk From this point onward Mobile DiskOnChip Plus appears as a standard disk drive It is assigned a drive letter and can be used by any application without any modifications to either the BIOS set up or the autoexec bat config sys files Mobile DiskOnChip Plus can be used as the only disk in the system with or without a floppy drive and with or without hard disks 37 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V The drive letter assigned depends on how Mobile DiskOnChip Plus is used in the system as follows If Mobile DiskOnChip Plus is used as the only disk in the system the system boots directly from it and assigns it drive C If Mobile DiskOnChip Plus is used with other disks in the system o Mobile DiskOnChip Plus can be configured as the last drive the default configuration The system assigns drive C to the hard disk and drive D to Mobile DiskOnChip Plus o Alternatively Mobile DiskOnChip Plus can be configured as the system s first drive The system assigns drive D to the hard disk and drive C to Mobile DiskOnChip Plus If Mobile DiskOnChip Plus is used as the O
90. e 44 9 52 Bigand Little Endan Systems si 44 9 5 3 44 9 5 4 Working with 8 16 32 Bit Systems with a Standard 44 9 6 Device Cascadltig uuu a ea eere pu eee eade 46 9 6 1 Standard Interface 2 eue eene eed de xia ee 46 9 6 2 Multiplexed 46 9 6 3 Memory in a Cascaded 47 10 Product Specifications RENE cen cereus nn 48 4 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 1 Environmental Specifications nennen 48 10 1 1 Operating Temperature eene 48 10 1 2 Thermal Characteristics u o e P eR D e P eei eredi 48 10 1 3 eee tod He DN a RE 48 10 top Endurance doa hath cR HERR t nen edd 48 10 2 Disk Capacity e uuu AREA Raha ARE a er D ed 48 10 3 Electrical Specifications Eee eonun e ee 49 10 3 1 Absolute Maximum 49 10 3 2 Capacitance e edd te o b ee ie edet etus 49 10 3 3 DC Electrical Characteristics Over Operating
91. e 46 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 9 6 3 Memory Map in Cascaded Configuration When cascading Mobile DiskOnChip Plus devices the Programmable Boot Block size is enlarged by for each additional 16MB device in the configuration When four 16MB devices or two 32MB devices are connected in a cascaded configuration a boot block size of 4KB is available The field of the Configuration register can be programmed with the maximum ID value used to enable access to the boot block of each device in a separate address space Initially at power up only device 0 responds to reads from the boot block address space with its 1KB of data aliased at addresses OK 6K and 7K Figure 18 shows the memory map when the maximum number of devices are connected in a cascaded configuration and the location of each IPL Normal Mode after setting Reset Mode ID 0000H IPLO Section 0 IPLO Programmable Boot IPLO Block 1 0800 Section 1 Flash Area 00H Window 1000H 00H Secon 2 Control Registers IPL2 1004 IPL0 Section 3 Programmable Boot IPL 0 Block IPL3 Figure 18 Memory Map in a Cascaded Configuration 47 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 Product Specifications 10 1
92. e 8 pepe p n o pepe p e ep pepe epo ws epe e n ep e e e e epp epe Pepa e Pe n e Less opere Pepe ee Pe Lee perpe ep emere perpe n e me e fe e e e a a ER ERE 2773877727773 e e eoor Pepa ep Lees e 8 e pepe 8 o Par Pepa e e epe Lees perpe ep Lees epe e e 8 e gt emo 23 2002 08 07 F 50 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK E ADDRESS RANGE E pp epp epp pp pepe s s Pe pp epe Cow e s e we a epp epo pepper pe snm a s
93. e n e Les perpe e we oper pep Les perpe ep perpe n e perpe n p o perpe epe Pepa ef epo ef Pe 8 e Le e e CC Pepa ef e e Lee ep e omnee Lee ppp s Dno 2002 08 07 41 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK E ADDRESS RANGE E rr pepe s s Pee ef Pe me epe pepe mme u re e Le p Pam e e u epp Depp pepe pp npe Paws s epp n po u e pp epp s pepper pe Dm pen p E Emme fe Pee pep epp u Pee pe n e nee a e Je s pepe Panes perpe s
94. e Mode is set using the Chip Erase command An Auto Chip Erase operation starts on the rising edge of WE in the sixth bus cycle All memory cells are automatically preprogrammed to 0 erased and verified as erased by the chip The device status is indicated by the Hardware Sequence flag Command input is ignored during an Auto Chip Erase A hardware reset can interrupt an Auto Chip Erase operation If an Auto Chip Erase operation is interrupted it cannot be completed correctly Hence an additional Erase operation must be performed Any attempt to erase a protected block is ignored If all blocks are protected the Auto Erase operation will not be executed and the device will enter Read mode 400 us after the rising edge of the WE signal in the sixth bus cycle If an Auto Chip Erase operation fails the device will remain in the erasing state and will not return to Read Mode The device status is indicated by the Hardware Sequence flag Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure In this case it cannot be ascertained which block the failure occurred in Either abandon use of the device altogether or perform a Block Erase on each block identify the failed block and stop using it The host processor must take measures to prevent subsequent use of the failed block 2002 08 07 7 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Block Erase Auto Multi Block Erase Modes The Auto Bloc
95. e aont d 13 2 9 1 Diagram rro die ie ea oe RR 13 2 32 Lm 14 AB rogna Descriptor e e etes ee I e Er yaa HR Eras ERR Re sawasqa 15 3 Theory OF mec 17 31 uu gu l 17 3 2 System Interface oie etie ea e ud eee ae es 18 3 3 Configuration 18 3 4 Protection and Security Enabling 18 3 4 1 18 3 4 2 Unique Identification UID 19 3 4 3 One Time Programmable 0 nemen nnne nns 19 3 5 Programmable Boot Block with eXecute In Place XIP Functionality 19 3 6 Download Engine DE ui ict teet ite eee bo ie 19 3 7 Error Detection Code Error Correction Code 20 3 8 Data Pipeline s ee ee one etis ct Su eu be dae oed el UTER dede ed 20 3 9 Control amp aS su uka ly a ise ABUS 20 3 10 ElashArchitectUre ride d RU Oe n PA un rie nitebatur TCR 20 4 Hardware Protection 1 leere Rhe E Rua Eri e ren RE P ERR RR ERR Rea 22 4 1 Method of Op
96. e e fe fee fe Pa n ep omnee fe fee Pee fe Pe fe fee fe fee fe n r fee fe Pele re Pee fe Pa e gt T 2002 08 07 44 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ES ADDRESS RANGE ES Ce pepe n n epe pe epe as e elt Pose epe n n e po e e e epe o c pepe pep n e peo 8 p ome e epee ep p pee peo 8 e ERE 77375773 pes Te epe semen ppp ep fe fe n e Powe n p o npe ph e e pepe pep
97. e of WE the last command 003 outputs 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase operation starts Additional Block Erase commands can only be accepted during the Block Erase Hold Time Each Block Erase command input within the hold time resets the timer allowing additional blocks to be marked for erasing DQ3 outputs a 1 if the Program or Erase operation fails DQ2 Toggle bit 2 002 is used to indicate which blocks have been selected for Auto Block Erase to indicate whether the device is in Erase Suspend Mode If data is read continuously from the selected block during an Auto Block Erase the DQ2 output will toggle Now 1 will be output from non selected blocks thus the selected block can be ascertained If data is read continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode the DQ2 output will toggle Because the DQ6 output is not toggling it can be determined that the device is in Erase Suspend Mode If data is read from the address to which data is being written during Erase Suspend in Programming Mode DQ2 will output a 1 RY BY READY BUSY TC58FVM7T2A B2A has a RY BY signal to indicate the device status to the host processor A 0 Busy state indicates that an Auto Program or auto erase operation is in progress A 1 Ready state indicates that the operation has finished and that the device can now accept a new command RY BY outputs 0
98. ed Table 2 Internal Connections Internal Connections 128Mb 64Mb 128Mb Mobile UR FBGA Location Signal NOR PSRAM DiskOnChip Plus F10 H2 CE fi CE1 F6 BUSY BUSY J2 1 1 5 CEf2 CE2 C4 LB LB F1 VCCm VCC H3 OE OE OE OE D5 RESET RESET D4 UB UB C6 WE WE WE WE C5 WP ACC WP ACC D6 CE2ps CE2 G6 NC G8 NC E5 RY BY RY BY IRQ A1 of Mobile 2 A0 i Concedo AD or 16 bit word support F2 A1 A1 A1 A2 E2 A2 A2 A2 A3 D2 A3 A3 A3 A4 F3 4 4 4 5 5 5 5 6 03 A6 6 6 8 C7 A8 A8 8 9 Data Sheet Rev 0 4 91 SR 001 53 8L M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 Internal Connections 128Mb 64Mb 128Mb Mobile Comment FBGA Location Signal NOR PSRAM _ DiskOnChip Plus E7 AQ AQ AQ A10 F7 A10 A10 A10 11 C8 11 11 11 12 08 12 12 12 E8 A13 A13 A13 F8 A14 A14 A14 9 15 15 15 9 16 16 16 17 17 17 4 18 18 18 07 19 19 19 E6 A20 A20 A20 9 21 21 21 Currently not expansion J3 D0 DQ0 D0 D0 G4 D1 DQ1 D1 D1 K4 D2 DQ2 D2 D2 H5 D3 DQ3 D3 D3 H6 D4 DQ4 D4 D4 K7 D5 DQ5 D5 D5 G7 D6 DQ6 D6 D6 J8 D7 DQ7 D7 D7 K3 D8 DQ8 D8 D8 H4 D
99. ented logic groups in Table 2 Table 2 Multiplexed Interface Signal Descriptions Description System Interface H8 K8 H7 J7 Multiplexed bus Address and data signals K5 48 G7 K7 H6 H5 K4 G4 J3 Output Enable active low Input Write Enable active low Input Configuration G9 ST Sets multiplexed interface Multiplexed mode is automatically For Mobile DiskOnChip 16MB only F8 ST ldentification For Mobile DiskOnChip 16MB up to two chips For Mobile be cascaded in the same memory window according to the entered when a rising edge is detected on this ball DiskOnChip 16MB only following assignment Chip 1 IDO VSS required for single chip Chip 2 ID0 E8 ST Lock active low When active provides full hardware data protection of selected partitions Control Busy active low open drain Indicates that DiskOnChip is initializing and should not be accessed A 10 pull up resistor is required even if the ball is not used power supply Sets the logic 1 voltage level range of I O balls pins VCCQ may be either 2 5V to 3 6V or 1 65V to 2 0V Requires 10 nF and 0 1 uF capacitor Device supply All VCC balls must be connected each VCC ball requires a 10 nF and a 0 1 UF capacitor C3 C7 C8 D2 Ground All VSS balls must be connected D3 D8 E2 E3 E4 E7 F2 F7 G2 G3 J9 15 Data Sheet Rev 1 7 95 SR 000 10 8L
100. er support for all major OSs e TrueFFS Software Development SDK developer guide DiskOnChip Boot Software Development Kit BDK developer guide e Support for all major CPUs including 8 16 and 32 bit bus architectures TrueFFS technology features e Block device API e Flash file system management Bad block management e Dynamic virtual mapping e Dynamic and static wear leveling Power failure management e Implementation of Reed Solomon EDC ECC e Performance optimization Compatibility with all DiskOnChip products 6 1 1 Built In Operating System Support The TrueFFS driver is integrated into all major OSs including Symbian OS Windows CE Pocket PC Smartphone OSE Nucleus and others For a complete listing of all available drivers please refer to M Systems website http www m sys com It is advised to use the latest driver versions that can be downloaded from the Mobile DiskOnChip Plus web page on the M Systems site 26 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 6 1 2 TrueFFS Software Development Kit SDK The basic TrueFFS Software Development SDK provides the source code of the TrueFFS driver It can be used in an OS less environment or when special customization of the driver is required for proprietary OSs When using Mobile DiskOnChip Plus as the boot replacement device the TrueFFS SDK also incor
101. eratlon e tet i tee Pt 22 4 2 Low Level Structure of the Protected Area 0 23 5 Modes of Operation u uuu irri re s Loire Dr re Eia 24 5 1 Normal Mode ute died etre ua ans hum ro sas gan 25 5 2 lt E A halun 25 5 3 Power Dowr u uu auqa ec 25 6 TrueFFS Technology 26 6 1 General Description 26 6 1 1 Built In Operating System 26 6 1 2 TrueFFS Software Development Kit 5 27 62 3 Management aes 27 6 1 4 Bad Block Management anaku NIRE ARAM 27 6 5 WearsLevellng SESERRA ROME M RUN RS 27 6 1 6 Power Failure 28 61 7 Error Detection GOITGCtlon 28 6 1 8 Special Features through I O Control IOCTL 28 3 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32M
102. ess Hex Register Name 1000 Chip Identification ID 1002 No Operation NOP 1004 Test 1006 DiskOnChip Control 1008 Device ID Select 100A Configuration 100C Output Control 100E Interrupt Control 1046 Toggle Bit 1076 DiskOnChip Control Confirmation 7 1 Definition of Terms The following abbreviations and terms are used within this section RFU Reserved for future use This bit is undefined during a read cycle and don t care during a write cycle RFU_0 Reserved for future use when read this bit always returns the value 0 when written software should ensure that this bit is always set to 0 RFU_1 Reserved for future use when read this bit always returns the value 1 when written software should ensure that this bit is always set to 1 Reset Value Refers to the value immediately present after exiting from Reset mode to Normal mode 7 2 Reset Values registers return 00H while in Reset mode The Reset value written in the register description 15 the register value after exiting Reset mode and entering Normal mode Some register contents are undefined at that time N A 7 3 Identification ID Register Description This register 1s used to identify the device residing on the host platform It always returns 41H when read Address hex 1000 Type Read only Reset Value 41H 5 Bii Bito 31 Data Sheet 1 7 95 SR 000 10 8L
103. from WP ACC terminates Acceleration Mode 2002 08 07 6 57 TOSHIBA TC58FVM7T2A 7B2A type Program Suspend Resume Mode Program Suspend is used to enable Data Read by suspending the Write operation The device accepts a Program Suspend command in Write Mode including Write operations performed during Erase Suspend but ignores the command in other modes When the command is input the address of the bank on which Write is being performed must be specified After input of the command the device will enter Program Suspend Read Mode after tsusp During Program Suspend Cell Data Read ID Read and Data Read can be performed When Data Write is suspended the address to which Write was being performed becomes undefined ID Read and CFI Data Read are the same as usual After completion of Program Suspend input a Program Resume command to return to Write Mode When inputting the command specify the address of the bank on which Write is being performed If the ID Read or Data Read functions is being used abort the function before inputting the Resume command On receiving the Resume command the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written Program Suspend can be run in Fast Program Mode or Acceleration Mode However note that when running Program Suspend in Acceleration Mode must not be released Auto Chip Erase Mode The Auto Chip Eras
104. g Hidden ROM Mode To protect the hidden ROM area use the block protection function The operation of Block Protect here is the same as a normal Block Protect except that VIH rather than Vip is input to RESET Once the block has been protected protection cannot be released even using the temporary block unprotection function Use Block Protect carefully N ote that in Hidden ROM Mode simultaneous operation cannot be performed for in top boot type and for BANKO in bottom boot type To exit Hidden ROM Mode usethe Hidden ROM Mode Exit command This will return the device to Read Mode HIDDEN ROM AREA rT TABLE BOOT BLOCK WORD MODE ARCHITECTURE GE ADDRESS RANGE SIZE ADDRESS RANGE SIZE TOP BOOT BLOCK SEM 7F0000h 7FFFFFh 64 Kbytes 3F8000h 3FFFFFh 32 Kwords 000000H 00FFFFh 64 Kbytes 000000H 007FFFh 32 Kwords Notes L H 2002 08 07 10 57 TOSHIBA TC58FVM7T2A 7B2A type FLASH MEMORY INTERFACE The TC58FVM7T2A B2A conforms to the specifications To read information from the device input the Query command followed by the address In Word Mode DQ8 DQ15 all output 0s To exit this mode input the Reset command CFI CODE TABLE ADDRESS A6 A0 DATA DQ15 DQO DESCRIPTION ASCII string QRY 13h 0002h Primary OEM command set 14h 0000h 2 AMD FJ standard type i Reid Address for primary extended table 17h 0000h Alternate OEM command set 18h
105. gister read operation the device is set to Normal mode by the TrueFFS software 5 3 Deep Power Down Mode In Deep Power Down mode Mobile DiskOnChip Plus internal high current voltage regulators are disabled to reduce quiescent power consumption to 10 16MB or 20 32MB The following signals are also disabled in this mode e Standard interface input buffers A 12 0 BHE WEZ D 15 0 and OE when is negated e Multiplexed interface input buffers AD 15 0 AVD WE and OE when is negated To enter Deep Power Down mode a proper sequence must be written to the DiskOnChip Control registers and DiskOnChip Control Confirmation register and the CE input must negated VCC other inputs should be VSS or VCC An additional option for setting the device into Deep Power Down mode when in Normal mode is by asserting the RSTIN signal and holding it in the low state see the dotted line in Figure 9 When the RSTIN signal is released the device 15 set in Reset mode In Deep Power Down mode write cycles have no effect and read cycles return indeterminate data Mobile DiskOnChip Plus does not drive the data bus Entering Deep Power Down mode and then returning to the previous mode does not affect the value of any register To exit Deep Power Down mode perform the following sequence e Read four times from address The data returned is undefined This option is valid for both s
106. h Mobile DiskOnChip Plus is assigned a 16 byte UID number Burned onto the flash during production the UID cannot be altered and is unique worldwide The UID is essential in security related applications and can be used to identify end user products in order to fight fraudulent duplication by imitators The UID on Mobile DiskOnChip Plus eliminates the need for an additional on board ID device such as a dedicated EEPROM 3 4 3 One Time Programmable OTP Area The 6KB OTP area is user programmable for complete customization The user can write to this area once after which it is automatically locked permanently After it is locked the OTP area becomes read only just like a ROM device Typically the OTP area is used to store customer and product information such as product ID software version production data customer ID and tracking information 3 5 Programmable Boot Block with eXecute In Place XIP Functionality During boot code must be executed directly from the flash media rather than first copied to the host RAM and then executed from there This direct XIP code execution functionality is essential for booting The Programmable Boot Block with XIP functionality enables Mobile DiskOnChip Plus to act as a boot ROM device in addition to being a flash disk This unique design enables the user to benefit from the advantages of NOR flash typically used for boot and code storage and NAND flash typically used for data storage No other
107. has ended abnormally Stops any automatic operation which is in progress tue Stops any operation other than the above and returns the device to False True Read Mode BYTE Word Mode BYTE is used select Word M ode 16 bits or Byte M ode 8 bits for the TC58F VM 7T2A B2A type If is input to BYTE the device will operate in Word Mode Read data write commands using 000 0015 When isinput to BYTE read data or write commands using 000 007 DQ15 A 1 is used as the lowest address DQ8 DQ14 will become High I mpedance 2002 08 07 F 5 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Program Mode The TC58FVM 7T2A B2A 2pin type be programmed in either byte or word units Auto Program Mode is set using the Program command The program address is latched on the falling edge of the WE signal and data is latched on the rising edge of the fourth Bus Write cycle with WE control Auto programming starts on the rising edge of the WE signal in thefourth Bus Write cycle The Program and Program Verify commands are automatically executed by the chip The device status during programming is indicated by the Hardware Sequence flag To read the Hardware Sequence flag specify the address to which the Write is being performed During Auto Program execution a command sequence for the bank on which execution is being performed cannot be accepted To terminate execution use a hardware reset N ote that if the
108. hese changes can be implemented through the Registry Entries In all other cases some minor customization is required in the driver Please refer to the readme of each specific driver for further information 45 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 9 6 Device Cascading 9 6 1 Standard Interface When using a standard interface up to four Mobile DiskOnChip Plus 16MB or up to two Mobile DiskOnChip Plus 32MB devices can be cascaded for up to 64MB capacity No external decoding circuitry or system redesign is required ID 1 0 ball values determine the identity of each device Systems with only one device must configure it as device 0 by setting ID 1 0 to 00H Additional devices should be configured as device 1 device 2 and device 3 by setting ID 1 0 to 01H 10H and 11H respectively Note As Mobile DiskOnChip Plus 32MB 15 a dual die comprised of two internally stacked Mobile DiskOnChip Plus 16MB devices only two Mobile DiskOnChip Plus 32MB devices may be cascaded Only IDO is used When devices are cascaded all I O balls must be wired in common including the BUSY output The ID input balls should be strapped to VCC or VSS according to the location of each device To communicate with a particular device its ID must be written into the Device ID Select register see Section 7 7 Only the device whose ID corresponds with this value responds
109. hip Based MCP Block Diagram 128Mbit NOR Flash Memory 000 0015 Data Sheet Rev 0 4 91 SR 001 53 8L M M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 1 5 128Mbit CMOS NOR Flash Memory ID Code Table Table 3 ID Code Table Type A21 A12 AG 0 Manufacturer Code L L L 0098H Device THPV067Y02BABD L L H 0074H Code THPV067Y03BABD L L H 0084H Verify Block Protect L H L Data Vi or Vi L Vi H Vig 1 Block Address 2 0001H Protected block 0000H Unprotected block 9 Data Sheet Rev 0 4 91 SR 001 53 8L M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 2 SPECIFICATIONS 2 1 Environmental Temperature Range 30 C to 85 C 2 2 Mechanical Dimensions 9 0 0 20 x 12 0 0 20 mm Height 1 4 0 1 mm Ball Count 107 balls Ball Pitch 0 8 mm Top Side Bottom 10 Data Sheet Rev 0 4 91 SR 001 53 8L M M Systems ms Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 3 ORDERING INFORMATION 501 D7N7P6 B1 MS01 M Systems DiskOnChip based MCP D7 Mobile DiskOnChip Plus 128Mbit 277 Mbit N7 NOR flash 128Mbit 2 7 Mbit P6 PSRAM 64Mbit 2 6 Mbit B1 107 ball FBGA 9x12x1 4 mm 4 MARKINGS First row Product name DiskOnChip MCP Secondrow Ordering information Third row Production information yyww Year and week 222 Product s
110. hip Plus 16 32MByte 1 8V I O wam Flash Disk Pioneers 512 Bytes 16 Bytes 4 Page 0 7 4 1 16 4 Page 30 4 31 Figure 7 Block Structure Mobile DiskOnChip Plus 32MB consists of two stacked 16MB devices each designed with a single bank 16 flash array consisting of 1024 blocks organized in 32 pages 21 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 4 Hardware Protection 4 1 Method of Operation Mobile DiskOnChip Plus enables the user to define two partitions that are protected hardware against any combination of read or write operations The two protected areas can be configured as read protected or write protected and are protected by a protection key i e password defined by the user Each of the protected areas can be configured separately and can function separately providing maximal flexibility for the user The size and protection attributes protection key read write changeable lock of the protected partition are defined in the media formatting stage DFORMAT utility or the format function in the TrueFFS SDK In order to set or remove a read write protection the protection key 1 e password must be used as follows Insert the protection key to remove read write protection e Remove the protection key to set read write protection
111. ignals trigger the controller e g system interface block bus control and data pipeline and flash access The Reset In RSTIN and Busy BUSY control signals are used in the reset phase See Section 5 2 for further details The Interrupt Request IRQ signal can be used when long I O operations such as Block Erase delay the CPU resources The signal is also asserted when a Data Protection violation has occurred When this signal 1s implemented the CPU can run other tasks and only returns to continue read write operations with Mobile DiskOnChip Plus after the IRQ signal has been asserted and an Interrupt Handling Routine implemented in the OS has been called to return control to the TrueFFS driver 3 3 Configuration Interface The Configuration Interface block enables the designer to configure Mobile DiskOnChip Plus to operate in different modes The identification signals ID 1 0 are used for identifying the relevant DiskOnChip device in a cascaded configuration see Section 9 6 on cascading for further details The Lock LOCK signal enables hard wire hardware controlled protection of code and data as described below For a standard interface the Interface Configuration signal configures Mobile DiskOnChip Plus for 16 bit or 8 bit data access see Section 9 5 4 3 4 Protection and Security Enabling Features The protection and security enabling block consisting of read write protection UID and OTP area enables advan
112. in the following pages is essentially the same as the timing shown on this page WE Control CE2 Control CE1 lt _ lt 19 105 tpH 2002 08 07 F 21 57 TOSHIBA TC58FVM7T2A 7B2A type e Control First Bus Write Cycle tcMD Control Last Bus Write Cycle 2002 08 07 F 22 57 TOSHIBA TC58FVM7T2A 7B2A type ID Read Operation input command sequence Manufacturer code Device code 2 Read Mode input of ID Read command sequence ID Read Mode Continued Dour 2 ID Read Mode input of Reset command sequence Read Mode Note Word Mode address shown BK Bank address 2002 08 07 F 23 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Program Operation WE Control Address Note Word Mode address shown PA Program address PD Program data 2002 08 07 F 24 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Program Operation WEControl Address A3 21 Address A0 2 CE1 toEHP toEs tPPAW cadacadacmuacscacaEGAS Hi Z tvps Vpp Note Word Mode address shown PA Program address PD Program Data 2002 08 07 F 25 57 TOSHIBA TC58FVM7T2A 7B2A type Auto Chip Erase Auto Block Erase Operation wE Control tvps Vpp Note
113. ip Based MCP MS01 D7N7P6 B1 APPENDIX B 128MBIT CMOS NOR FLASH MEMORY DATA SHEET Note Information regarding packaging ball assignment and package level specifications does not apply to DiskOnChip based MCP For DiskOnChip based MCP specifications refer to Sections 1 and 2 of this data sheet Data Sheet Rev 0 4 91 SR 001 53 8L TOSHIBA TC58FVM7T2A 7B2A type 128 Mbits NOR FLASH MEMORY TC58FVM7TA 7BA CE 2pin type Organization 8M x t6bits 16M x 8bits 2002 08 07 F 1 57 TOSHIBA TC58FVM7T2A 7B2A type COMMAND SEQUENCES anana YS a 5 6 BUS FIRST BUS SECOND BUS THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS COMMAND WRITE WRITE CYCLE WRITE CYCLE WRITECYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE SEQUENCE CYCLES REQ D Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data ee E m m An 555h Word 555h 2AAh ID Read AAAh PR Wor 555h 2 555h Auto Program AAA Auto Word 555h 2 Read Reset E r 6 H Program Suspend ae E Suspend 1 RM Block Erase Resume E Block Protect 2 xn Word 555h 2 Verify Block Protect Byte E Fast Progra Word 555 2 ce mt Aoh Saas es S on XXR s Hidden ROM Word 555h 2AAh
114. is input to the device malfunction may occur The device uses standard J EDE C commands It is conceivable that in extreme cases system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it Then even if a proper command is input the device may not operate To avoid this possibility clear the Command Register before command input In an environment prone to system noise Toshiba recommend input of a software or hardware reset before command input Protection against Malfunction at Power on To prevent damage to data caused by sudden noise at power on when power is turned on with WE 1 CE2 VIL the device does not latch the command on the first rising edge of WE or CE1 or CE2 Instead the device automatically Resets the Command Register and enters Read Mode 2002 08 07 F 16 57 TOSHIBA TC58FVM7T2A 7B2A type AC CHARACTERISTICS AND OPERATING CONDITIONS Ta 30 to 85 C Vpp 2 7 to 3 3 V Output load capacitance CL 30 pF 100 pF Symbol Unit De gt ee enzo 9 e aa som s BLOCK PROTECT emme Fr gt PROGRAM CHARACTERISTICS tPPW Auto Program Time Word Mode
115. k Erase Mode and Auto Multi Block Erase Mode are set using the Block Erase command The block address is latched on the falling edge of the WE signal in the sixth bus cycle The block erase starts as soon as the Erase Hold Time tBEH has elapsed after the rising edge of the WE signal When multiple blocks are erased the sixth Bus Write cycle is repeated with each block address and Auto Block E rase command being input within the Erase Hold Time this constitutes an Auto Multi Block Erase operation If a command other than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time the device will reset the Command Register and enter Read Mode The Erase Hold Time restarts on each successive rising edge of WE Once operation starts all memory cells in the selected block are automatically preprogrammed to 0 erased and verified as erased by the chip The device status is indicated by the setting of the Hardware Sequence flag When the Hardware Sequence flag is read the addresses of the blocks on which auto erase operation is being performed must be specified If the selected blocks are spread across all nine banks simultaneous operation cannot be carried out All commands except Erase Suspend are ignored during an Auto Block Erase or Auto Multi Block Erase operation Either operation can be aborted using a Hardware Reset If an auto erase operation is interrupted it cannot be completed correctly therefore a further erase o
116. mage may occur if absolute maximum ratings are exceeded Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 The voltage on any pin may undershoot to 2 0 V or overshoot to 6 6V for less than 20 ns 3 When operating DiskOnChip with separate power supplies for VCC and it is desirable to turn both supplies on and off simultaneously Providing power separately either at power on or power off can cause excessive power dissipation Damage to the device may result if this condition persists for more than 1 second 10 3 2 Capacitance Table 9 Capacitance 16 s ee is not 100 tested Table 10 Capacitance 32MB Parameter Symbol Conditions Min Typ Unit Capacitance is not 100 tested 49 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 10 3 3 DC Electrical Characteristics Over Operating Range Table 11 DC Characteristics 1 65V to 1 95V I O LL eee Voltage 165 65 1 95 95 VCCQ Low level Low level Input Voltage Voltage LIIS Lic EY Bs zr D 15 0 lol 100 Low level Output Voltage VoL IRQ BUSY _ Input Leakage Current 10 Time 100 ns 16MB r mr Cycle Time 100 ns 32MB Deep Power Down mode Standby Supply Current 16
117. men wen pe p e n pep memes wes pep n pep e p pep p pee prp epe pep pep epe fe De pe pepe pp sme a e De De De oeoo saree Fue pep pepe pep pe pr pe pep De memes pep pepe pep e pep p pe pep De mes prp pen epe prp pe n Fm pep pen pepe E pep pen pep pe pep pen pepe e seoor serrer pep pen pepe pep pep pep e pup o pes De LL aa 2002 08 07 56 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK SIZE TABLE Top boot BLOCK BocszE SIZE B AN BANK BANKSZE WORD BYTE MODE COUNT ae eS sa mere mem x eme wee x block BLOCK 2 BocszE SIZE BANK BANK Neer BYTE MODE WORD CE2 BYTE worp COUNT sa mere
118. n pho Les pep epe Pens epp epo pp epp npe Pane pepe pp n po Les epp pepe c Cwe e e e Pane e ane i Pee fe e pepe me npe epp we Pane Pepe e ener Pane Pe conor Pane pep Pane fe fee fe Pa n e oro wm pen pepe n p pen pp ws pen prp epp pepe npe n ep epe npe n p es Te fe Pe pepe epee es peperere omoes ICCRESESERCREICICRER toe Fs oer 2002 08 07 49 57 TOSHIBA TC58FVM7T2A 7B2A type BLOCK ADDRESS BANK BLOCK ES ADDRESS RANGE ES pepe pep pepe n e ane pepe pep n o pepe eorr Le pepe pepe e Les epe pepe peo epe o ws pepe
119. nChip Plus 16 32MByte features W Exceptional read write and erase performance Advanced protection and security enabling features for data and code m Low voltage 3 I O 1 8V 3V auto detect m Small form factor 69 ball 9x12 mm Fine Pitch Ball Grid Array FBGA NAND based flash technology that enables high density and small die size m Proprietary TrueFFS technology for full hard disk emulation high data reliability and maximum flash lifetime m Single die chip 16MByte Dual die chip 32MByte with device cascade options for up to 64MByte 512MBit capacity m Programmable Boot Block with eXecute In Place XIP functionality using 16 bit access with download support for more code m Configurable for 8 16 32 bit bus interface m Data integrity with Reed Solomon based Error Detection Code Error Correction Code EDC ECC m Deep Power Down mode for reduced power consumption Support for all major mobile OSs including Symbian OS Windows CE Smartphone 2002 3 Pocket PC Nucleus OSE and Linux M Systems mums Flash Disk Pioneers lt lt ye Performance Burst read write 13 3 MB sec Sustained read 1 7 MB sec Sustained write 0 86 MB sec Protection and Security Enabling Features m 16 byte Unique Identification UID number 6KByte user configurable One Time Programmable OTP area W Two configurable write protected and read protected partitions
120. neers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 4 5 Power Up Timing Mobile DiskOnChip Plus is reset by assertion of the RSTIN input When this signal is negated DiskOnChip initiates a download procedure from the flash memory into the internal Programmable Boot Block During this procedure Mobile DiskOnChip Plus does not respond to read or write accesses Host systems must therefore observe the requirements described below for first access to Mobile DiskOnChip Plus Any of the following methods may be employed to guarantee first access timing requirements a Use a software loop to wait at least Tp BUSY 1 before accessing the device after the reset signal is negated b Pollthe state of the BUSY output c Use BUSY output to hold the host CPU in wait state before completing the first access Host systems that boot from Mobile DiskOnChip Plus must employ option c or use another method to guarantee the required timing for first time access VCC 2 5V 1 65 2 5V E TREC VCC RSTIN lt Tw RSTIN RSTIN 05 0 ets BUSY THO BUSY A TP BUSYO 12 0 BHE VALID THO BUSY CS lt CE OE WE Tsu D BUSY1 D Read cycle THO RSTIN AVD AVD Muxed Mode Only Figure 24 Reset Timing 62 Data Sheet Rev 1 7 95 SR 000 10 8L l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte
121. nsion area If the allocated memory window 1s larger than 8KB an automatic anti aliasing mechanism prevents the firmware from being loaded more than once during the ROM expansion search 3 3V 1 8V 3 3V l 1 0 1 uF 0 1 uF 10 lt iL gt 1 20KOhm lt Address 12 0 BUSY Busy Data D 15 0 Output Enable OE Mobile DiskOnChip Write Enable WE Plus gt LOCK lt Chip Enable Reset RSTINZ Chip ID ID 1 0 a VSS Figure 14 Standard System Interface Notes 1 The 0 1 uF and the 10 nF low inductance high frequency capacitors must be attached to each of the device s VCC and VSS balls These capacitors must be placed as close as possible to the package leads 2 Mobile DiskOnChip Plus is an edge sensitive device OE WE should be properly terminated according to board layout serial parallel or both terminations to avoid signal ringing 3 All capacities support the standard interface 41 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 9 2 2 Multiplexed Interface With a multiplexed interface Mobile DiskOnChip Plus requires the signals shown in Figure 15 below 3 3 V 1
122. nsitive interrupts in which the IRQ output pulses low Interrupt Request when flash array is ready Indicates that the IRQ output has been asserted due to an indication that the flash array is ready Writing 1 to this bit clears its value 35 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V negates the IRQ output and permits subsequent interrupts to occur P Interrupt Request on Protection Violation Indicates that the IRQ output has been asserted due to a data protection violation Writing a 1 to this bit clears its value negates the IRQ output and permits subsequent interrupts to occur Reserved for future use 7 11 Toggle Bit Register Description This register identifies the presence of the device Address hex 1046 Type Read Only Reset Value 82H 0 1 3 7 Reserved for future use TOGGLE This read only bit toggles on consecutive reads and identifies the presence of the device 36 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 8 Booting from Mobile DiskOnChip Plus 8 1 Introduction Mobile DiskOnChip Plus can function both as a flash disk and the system boot device If DiskOnChip is configured as a flash disk it can operate as the OS boot device DiskOnChip default firmware contains drivers t
123. o enable it to perform as the OS boot device under DOS see Section 8 2 For other OSs please refer to the readme file of the TrueFFS driver If Mobile DiskOnChip Plus is configured as a flash disk and as the system boot device it contains the boot loader an OS image and a file system In such a configuration Mobile DiskOnChip Plus can serve as the only non volatile device on board Refer to Section 8 3 2 for further information on boot replacement 8 2 Boot Procedure in PC Compatible Platforms When used in PC compatible platforms Mobile DiskOnChip Plus is connected to an 8 memory window in the BIOS expansion memory range typically located between 0C8000H to OEFFFFH During the boot process the BIOS loads the TrueFFS firmware into the PC memory and installs Mobile DiskOnChip Plus as a disk drive in the system When the operating system is loaded Mobile DiskOnChip Plus is recognized as a standard disk No external software is required to boot from Mobile DiskOnChip Plus Figure 13 illustrates the location of the Mobile DiskOnChip Plus memory window in the PC memory map Extended Memory 0 Figure 13 Mobile DiskOnChip Plus Memory Window in PC Memory Map After reset the BIOS code first executes the Power On Self Test POST and then searches for all expansion ROM devices When Mobile DiskOnChip Plus is located the BIOS code executes from it the IPL code located the XIP portion of the Programmable Boot Block This code loa
124. on for transparent file system management Identical software for all DiskOnChip capacities Patented methods to extend flash lifetime including O Dynamic virtual mapping O Dynamic and static wear leveling Support for all major OS environments including Symbian OS Windows CE Pocket PC Smartphone OSE ATI Nucleus Linux Support for OS less environments 8KByte memory window Power Requirements m Operating voltage O Core 2 5 to 3 6V auto detect 1 65 1 95V or 2 5V 3 6V m Current O Active 25 mA Typ O Deep Power Down Typ 10 pA 16 20 32MB Capacities m 16MB 128 with device cascading option for up to 64MB 512Mb m 32MB 256MD with device cascading option for up to 64MB 512Mb Packaging m 69 ball FBGA 9 x 12 x 1 4 mm max Data Sheet Rev 1 7 95 SR 000 10 8L M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V Table of Contents Und 7 22 lt 9 a 8 2 1 Product Descriptlons e ee RE 8 2 2 Standard AVERAGE esna eh dete te eoa te eade 9 2 21 Diagram DUE 9 2 2 2 Systerm Interface ose ete tree be OAS UR y 10 2 2 3 Sigrial Descrlptioni u u u kau tete fea es AUR REESE qasan 11 2 3 Multiplexed Interface ete ito reto te as ERR RU
125. one and visa versa Note that un changeable partition attributes cannot be changed unless the media 15 reformatted A change of any of the protection attributes causes a reset of the protection mechanism and consequently the removal of all device protection keys That is if the protection attributes of one partition are changed the other partition will lose its key protected read write protection The only way to read or write from a read or write protected partition is to use the insert key call even DFORMAT does not remove the protection This is also true for modifying its attributes key read write and lock enable state Read write protection 15 disabled in each one of the following events Power down Change of any protection attribute not necessarily in the same partition Write operation to the IPL area e Removal of the protection key For further information on hardware protection please refer to TrueFF S Software Development Kit SDK developer guide or application note AP DOC 057 Protection and Security Enabling Features in DiskOnChip Plus 22 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 4 2 Low Level Structure of the Protected Area The first three blocks on Mobile DiskOnChip Plus contain foundry information the Data Protect structures IPL code and bad block mapping information See Figure 8
126. peration is necessary to complete the erasing Any attempt to erase a protected block is ignored If all the selected blocks are protected the auto erase operation is not executed and the device returns to Read Mode 400 us after the rising edge of the WE signal in the last bus cycle If an auto erase operation fails the device remains in Erasing state and does not return to Read Mode The device status is indicated by the Hardware Sequence flag After a failure either a Reset command or a Hardware Reset is required to return the device to Read Mode If multiple blocks are selected it will not be possible to ascertain the block in which the failure occurred In this case either abandon use of the device altogether or perform a Block Erase on each block identify the failed block and stop using it The host processor must take measures to prevent subsequent use of the failed block Erase Suspend Erase Resume Modes Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes When the command is input the address of the bank on which Erase is being performed must be specified In Erase Suspend Mode only a Read Program or Resume command can be accepted If an Erase Suspend command is input during an Auto Block Erase the device will enter Erase Suspend Read Mode after tsusE The device status
127. porates in its source code the BDK software that 1s required for this configuration this package is also available separately Please refer to the DiskOnChip Boot Software Development Kit BDK developer guide for further information on using this software package 6 1 3 File Management TrueFFS accesses the flash memory within Mobile DiskOnChip Plus through an 8KB window in the CPU memory space It provides block device API by using standard file system calls identical to those used by a mechanical hard disk to enable reading from and writing to any sector on Mobile DiskOnChip Plus This makes it compatible with any file system and file system utilities such as diagnostic tools and applications When using the File Allocation Table FAT file system the data stored on Mobile DiskOnChip Plus uses FAT 16 Note Mobile DiskOnChip Plus is shipped unformatted and contains virgin media 6 1 4 Bad Block Management As NAND flash is an imperfect storage media it contains some bad blocks that cannot be used for storage because of their high error rates TrueFFS automatically detects and maps bad blocks upon system initialization ensuring that they are not used for storage This management process is completely transparent to the user who remains unaware of the existence and location of bad blocks while remaining confident of the integrity of data stored The Bad Block Table on Mobile DiskOnChip Plus 15 hardware protected for ensured reliability 6
128. r WE 1 CE2 The data is latched the rising edge of either WE 1 CE2 090 0907 are valid for data input DQ8 DQ15 are ignored To abort input of the command sequence use the Reset command The device will reset the Command Register and enter Read Mode If an undefined command is input the Command Register will be reset and the device will enter Read Mode Software Reset Apply a software reset by inputting Read Reset command A software reset returns the device from ID Read Mode Mode to Read Mode releases the lock state if automatic operation has ended abnormally and clears the Command Register Hardware Reset A hardware reset initializes the device and sets it to Read Mode When a pulse is input to RESET for trp the device abandons the operation which is in progress and enters Read Mode after tREADY Note that if a hardware reset is applied during data overwriting such as a Write or Erase operation data at the address or block being written to at the time of the reset will become undefined After a hardware reset the device enters Read RESET or Standby RESET VIL The DQ pins are High I mpedance when RESET After the device has entered Read Mode Read operations and input of any command are allowed Comparison between Software Reset and Hardware Reset ACTION SOFTWARE RESET HARDWARE RESET Releases the lock state if automatic operation
129. res for both data and code storage With superior read and write performance small size and low power consumption it is optimized for the high end handset multimedia handset and PDA markets These markets require fast read and write rates minimum weight and space and low power consumption to support the large and growing pool of data rich applications Mobile DiskOnChip Plus protection and security features offer unique benefits Two write and read protected partitions with both software and hardware based protection can be configured independently for maximum design flexibility The 16 byte Unique ID UID identifies each flash device used with security and authentication applications eliminating the need for a separate ID device i e EEPROM on the motherboard The user configurable One Time Programmable OTP area written to once and then locked to prevent data and code from being altered is ideal for storing customer and product specific information In addition the Bad Block Table 18 hardware protected ensuring that it will not be damaged or accidentally changed to ensure maximum reliability Mobile DiskOnChip Plus devices have a simple SRAM like interface for easy integration It can also be configured to work with a multiplexed interface Multiplexing data and address lines can save board space reduce RF noise effects and more Mobile DiskOnChip Plus 15 based on Toshiba s cutting edge 0 16 NAND flash technology This technology
130. rithm is also used to update and store mapping information on the flash memory This keeps the mapping information coherent even during power failures The only mapping information held in RAM 15 a table pointing to the location of the actual mapping information This table 15 reconstructed during power up or after reset from the information stored in the flash memory To prevent data from being lost or corrupted TrueFFS uses the following mechanisms e When writing copying or erasing the flash device the data format remains valid at all intermediate stages Previous data is never erased until the operation has been completed and the new data has been verified e data sector cannot exist in a partially written state Either the operation is successfully completed in which case the new sector contents are valid or the operation has not yet been completed or has failed in which case the old sector contents remain valid 6 1 7 Error Detection Correction TrueFFS implements a Reed Solomon Error Correction Code ECC algorithm to ensure data reliability Refer to Section 3 7 for further information on the EDC ECC mechanism 6 1 8 Special Features through I O Control IOCTL Mechanism In addition to standard storage device functionality the TrueFFS driver provides extended functionality This functionality goes beyond simple data storage capabilities to include features such as format the media read write protect binary partition s access
131. rming simultaneous operation this method will terminate the current operation and set the device to Standby Mode This is a hardware reset and is described later In Standby Mode DQ is put in High I mpedance state Auto Sleep Mode This function suppresses power dissipation during reading If the address input does not change for 150 ns the device will automatically enter Sleep Mode and the current will be reduced to the standby current I pps2 However if the device is in the process of performing simultaneous operation the device will not enter Standby Mode but will instead cause the operating current to flow Because the output data is latched data is output in Sleep Mode When the address is changed Sleep Mode is automatically released and data from the new address is output Output Disable Mode Inputting to OE disables output from the device and sets DQ to High I mpedance 2002 08 07 4 57 TOSHIBA TC58FVM7T2A 7B2A type Command Write The TC58FVM7T2A B2A 2pin type uses the standard J EDEC control commands for single power supply 2 Command Write is executed by inputting the address and data into the Command Register The command is written by inputting a pulse to WE with and OE WE control The command can also be written by inputting a pulse to CE1 or CE2 with WE CE1 or CE2 control The address is latched on the falling edge of eithe
132. ro aM ID 1 0 Identification The device whose ID input balls matches the value of bits ID 0 1 responds to read and write cycles to register space Reserved for future use 7 8 Configuration Register Description This register indicates the current configuration of the device Unless otherwise noted the bits are reset only by a hardware reset and not upon boot detection or any other entry to Reset mode Address hex 100A Type Read Write except bit 7 which is Read Only Reset Value X0000X10 Bit Bits Bito IF CFG RFU 0 MAX ID RFU RFU 0 Beslon Reserved for future use 4 5 MAX Maximum Device ID This field controls the RAM address mapping when multiple devices are used in a cascaded configuration using the ID 1 0 inputs It should be programmed to the highest ID value that is found by software in order to map all available boot blocks into usable address space IF Interface Configuration Reflects the state of the IF input pin 34 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 7 9 Output Control Register Description This register controls the behavior of certain output balls Address hex 100C Type Read Write Reset Value 01H Bir Bits RFU 0 SLOCK RFU 1 RFU 0 RFU 1 Bio
133. rotected 01H is output If the block is unprotected is output Boot Block Protection Boot block protection temporarily protects certain boot blocks using a method different from ordinary block protection Neither Vip nor a command sequence is required Protection is performed simply by inputting WP ACC The target blocks are the two pairs of boot blocks The top boot blocks BA261 BA262 the bottom boot blocks are BAO and Inputting WP ACC releases the mode From now on if it is necessary to protect these blocks the ordinary Block Protection Mode must be used 2002 08 07 F 9 57 TOSHIBA TC58FVM7T2A 7B2A type Hidden ROM Area The TC58FVM7T2A B2A type features a 64 K byte hidden ROM area which is separate from the memory cells area consists of one block Data Read Write and Protect can be performed on this block Because Protect cannot be released once the block is protected data in the block cannot be overwritten The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE To access the Hidden ROM area input a Hidden ROM Mode Entry command The device now enters Hidden ROM Mode allowing Read Write Erase and Block Protect to be executed Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode However regarding write operation Accelaration mode can not be performed durin
134. ss to the boot block 5 Add 260 ns on the first read cycle when exiting Power Down mode See Section 5 3 for more information 6 No load C 0 pF 55 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 10 4 2 Write Cycle Timing Standard Interface tTwcyc azae WCO 00009000000000000000 THO CE1 CE Tsu CE0 Tsu CE1 THO CEO TREC WE tsu D Figure 21 Standard Interface Write Cycle Timing WE D 15 0 Table 16 Standard Interface Write Cycle Parameters VCC 2 5 3 6V VCCQ VCC VCCQ 1 65 1 9V Symbol Description VCC 2 5 3 6V VCC 2 5 3 6V Units Min Max Min Max Tsu A Address to WE v setup time 2 2 ns Tho A WE V to Address hold time 28 28 ns Tw WE asserted width 50 49 ns Tweyc Write Cycle Time 83 83 ns Tsu Y to WE v setup time ns Tho WE to CE hold time ns Tho CE1 OE or WE to CE v hold time 6 6 ns Tsu CE1 to WE or OE V setup time 6 6 ns Trec WE n to start of next cycle 20 20 ns Tsu D D to WE 7 setup time 29 29 ns Tho D WE to D hold time 0 0 Note When designing your board to support also DiskOnChip Plus 32 64 devices it is not possible to 2 5 3 6 these devices
135. sys com to obtain the latest specifications before placing your order 2003 M Systems Flash Disk Pioneers Ltd All rights reserved M Systems DiskOnChip DiskOnChip Millennium DiskOnKey DiskOnKey MyKey FFD Fly By iDiskOnChip iDOC mDiskOnChip mDOC Mobile DiskOnChip Smart DiskOnKey SuperMAP TrueFFS uDiskOnChip and uDOC are trademarks or registered trademarks of M Systems Flash Disk Pioneers Ltd Other product names or service marks mentioned herein may be trademarks or registered trademarks of their respective owners and are hereby acknowledged All specifications are subject to change without prior notice Data Sheet Rev 0 4 91 SR 001 53 8L
136. tandard and multiplexed interfaces e Perform a single read cycle from the Programmable Boot Block with an extended access time and address hold time as specified in Section 10 4 1 The data returned will be correct Applications that require both Deep Power Down mode and boot detection require BIOS support to ensure that Mobile DiskOnChip Plus exits from Power Down mode prior to the expansion ROM scan Similarly applications that use Mobile DiskOnChip Plus as a boot ROM must ensure that the device is not in Deep Power Down mode before reading the boot vector instructions either by pulsing RSTIN to the asserted state and waiting for the BUS Y output to be negated or by entering Reset mode via software 25 Data Sheet Rev 1 7 95 SR 000 10 8L A l M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 6 TrueFFS Technology 6 1 General Description M Systems patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance reliability and lifetime TrueFFS emulates a hard disk making it completely transparent to the OS In addition since it operates under the OS file system layer see Figure 10 it is completely transparent to the application Application OS File System TrueFFS DiskOnChip Figure 10 TrueFFS Location in System Hierarchy TrueFFS technology support includes e Binary driv
137. tatus Engineering samples ES customer samples CS or FAB marking Internal marking 7 M Systems ms Flash Disk Pioneers DiskOnChip MS01 D7N7P6 B1 JAPAN yywwzzz 11 Data Sheet Rev 0 4 91 SR 001 53 8L M Systems mamam Flash Disk Pioneers DiskOnChip Based MCP MS01 D7N7P6 B1 APPENDIX 128MBIT MoBILE DISKONCHIP PLUS DATA SHEET Note Information regarding packaging ball assignment and package level specifications does not apply to DiskOnChip based MCP For DiskOnChip based MCP specifications refer to Sections 1 and 2 of this data sheet Data Sheet Rev 0 4 91 SR 001 53 8L Data Sheet Mobile DiskOnChip Plus 16 32MByte 1 8V Flash Disk Protection and Security Enabling Features Highlights Mobile DiskOnChip Plus 16 32MByte 128 256 is one of the industry s most efficient storage solutions with the fastest write rates the smallest size and lowest power consumption Additionally it offers advanced data protection and security enabling features Based on a monolithic dual die chip that utilizes Toshiba s 0 16 1 NAND technology Mobile DiskOnChip Plus attains levels of reliability that surpass competing products These characteristics make Mobile DiskOnChip Plus ideal for meeting the growing demand for secure and reliable data storage in mobile multimedia devices such as mobile phones and Personal Digital Assistants PDAs Mobile DiskO
138. the internal flash it can be connected to a 16 bit bus The TrueFFS driver handles all the issues regarding routing data to and from Mobile DiskOnChip Plus The Programmable Boot Block is accessed as a true 16 bit device It responds with the appropriate data when the CPU issues either an 8 bit or 16 bit read cycle 32 Bit Word Data Access Mode In a 32 bit bus system that cannot execute byte or word aligned accesses the system address lines SA0 and SA1 are always zero Consecutive long words 32 bit are differentiated by SA2 toggling Therefore in 32 bit systems that support only 32 bit data access cycles DiskOnChip 1 is connected to the first system address bit that toggles i e SA2 DiskOnChip 0 is connected to VSS to configure it for 16 bit operation see Table 4 System Host SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA SA1 SAO VOY Y YY Y Y A12 11 10 9 8 AT A6 A5 A4 A3 A2 A1 0 DiskOnChip Figure 16 32 Bit Word Data Access Mode Note The prefix S indicates system host address lines TrueFFS Driver Modifications TrueFFS supports a wide range of OSs see Section 6 1 1 The TrueFFS driver is set to work in 8 bit data access mode as the default To support 16 bit 32 bit data access modes and their related memory window allocations TrueFFS must be modified In Windows CE and Windows NT Embedded t
139. tion 4 Section 5 Section 6 Section 7 Section 8 Section 9 Section 10 Section 11 Appendix A Overview of data sheet contents Product overview including a brief product description pin and ball diagrams and signal descriptions Theory of operation for the major building blocks Hardware Protection mechanism Modes of operation TrueFFS technology including power failure management and 8Kbyte memory window Register description Using Mobile DiskOnChip Plus as a boot device Hardware and software design considerations Environmental electrical timing and product specifications Information on ordering Mobile DiskOnChip Plus Sample code for verifying Mobile DiskOnChip Plus operation To contact M Systems worldwide offices for general information and technical support please see the listing on the back cover or visit M Systems website www m sys com Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 2 Product Overview 2 4 Product Description Mobile DiskOnChip Plus 16 32MB is a member of M Systems DiskOnChip product series It is a based on a single die 16MB or dual die 32MB with an embedded flash controller and flash memory providing a complete easily integrated flash disk for highly reliable data storage Mobile DiskOnChip Plus also offers advanced features for hardware protected data and code and security enabling featu
140. to read or write cycles to registers Figure 17 illustrates the configuration required to cascade four devices on the host bus Only the relevant cascading signals are included in this figure although all other signals must also be connected vss VCC VSS vce VSS vss VCC VCC 13 2nd 3rd 4th ID1 L 1 Y ID1 CE 1 OE m OE m OE m OE WE WE WE __ WE WE e Figure 17 Cascading Configuration for Four Devices 9 6 2 Multiplexed Interface When using a multiplexed interface up to two Mobile DiskOnChip Plus 16MB devices can be cascaded for up to 32MB capacity No external decoding circuitry or system redesign is required The IDO ball value determines the identity of each device Systems with only device must configure it as device 0 by connecting IDO to VSS The second device should be configured as device 1 by connecting IDO to VCC When two devices are cascaded all I O balls must be wired in common including the BUSY output To communicate with a particular device its ID must be written into the Device ID Select register see Section 7 7 Only the device whose ID corresponds with this value responds to read or write cycles to registers Note Mobile DiskOnChip Plus 32MB devices cannot be cascaded in a multiplexed interfac
141. uses the Little Endian system Therefore bytes D 7 0 are its Least Significant Byte LSB and bytes D 15 8 are its Most Significant Byte MSB Within the bytes bit DO and bit D8 are the least significant bits of their respective byte When connecting Mobile DiskOnChip Plus to a device that supports the Big Endian system make sure to that the bytes of the CPU and Mobile DiskOnChip Plus match Note Processors like the Power PC also change the bit ordering within the bytes Failing to follow these rules results in improper connection of Mobile DiskOnChip Plus and prevents the TrueFFS driver from identifying Mobile DiskOnChip Plus For further information on how to connect Mobile DiskOnChip Plus to support CPUs that use the Big Endian system refer to the application note for the relevant CPU 9 5 3 Busy Signal The Busy signal BUS Y indicates that Mobile DiskOnChip Plus has not yet completed internal initialization After reset BUSY is asserted while the IPL is downloaded into the internal boot block and the Data Protection Structures DPS are downloaded to the Protection State Machines After the download process is completed BUSY is negated It can be used to delay the first access to Mobile DiskOnChip Plus until it is ready to accept valid cycles Note The TrueFFS driver does NOT use this signal to indicate that the flash 15 in busy state e g program read or erase 9 5 4 Working with 8 16 32 Bit Systems with a Standard Interface
142. ut in which a block address and A1 and areinput Now the device writes to the block protection circuit There is a wait of until this write is completed however no intervention is necessary during this time In the third cycle the Verify Block Protect command is input This command verifies the write to the block protection circuit Read is performed in the fourth cycle If the protection operation is complete 01H is output If a value other than 01H is output block protection is not complete the Block Protect command must input again Removing the Vip input from RESET exits this mode Temporary Block Unprotection The TC58FVM 7T2A B2A CE 2pin type has a temporary block unprotection feature which disables block protection for all protected blocks Unprotection is enabled by applying Vip to the RESET pin Now Write and Erase operations can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect operation The device returns to its previous state when Vip is removed from the RESET That is previously protected blocks will be protected again Verify Block Protect The Verify Block Protect command is used to ascertain whether a block is protected or unprotected Verification is performed either by inputting the Verify Block Protect command as for ID Read Mode and setting the block address AO and A1 If the block is p
143. ycles from sections 1 and 2 always return the value 00H to create a fixed and known checksum After setting the MAX ID field in the Configuration register done by IPLO the second copy of IPLO is replaced with the IPL of the second 16MB device of the dual die thereby creating a 2KB Programmable Boot Block When in Normal mode sections 1 and 2 are used for the internal registers The Programmable Boot Block in section 0 contains IPLO and IPL1 Section 3 contains IPLO aliased twice The addresses described here are relative to the absolute starting address of SKB memory window Reset Mode Normal Mode 000H cb le Programmable 7 BU boot block IPL Section 0 IPL0 IPL1 2 aliases 800H Flash area 00H Section 1 WIQOW aliases 1000H Control 00H Section 2 Registers aliases 1800H Programmable Programmable boot block boot block 000H 3FFH Section 3 IPLO IPL1 2 aliases 2 aliases Figure 12 Mobile DiskOnChip Plus 32MB Memory Map 30 Data Sheet Rev 1 7 95 SR 000 10 8L M Systems m Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V I O 7 Register Descriptions This section describes various Mobile DiskOnChip Plus registers and their functions as listed in Table 3 This section can be used to enable the designer to better evaluate DiskOnChip technology Table 3 Mobile DiskOnChip Plus Registers Addr
144. zed 4 interrupt service routine to the host interrupt is connected and enabled Stage 2 Configure the software so that for every long flash I O operation the following steps occur 1 The correct value is written to the Interrupt Control register to enable IRQ interrupt Note Refer to Section 7 10 for further information on the value to be written to this register 2 flash I O operation starts 3 Control is returned to the OS to continue other tasks When the IRQ interrupt is received other interrupts are disabled and the OS 15 flagged 43 Data Sheet Rev 1 7 95 SR 000 10 8L A lp M Systems mamam Flash Disk Pioneers Mobile DiskOnChip Plus 16 32MByte 1 8V 4 5 either returns control immediately to the TrueFFS driver or waits for the appropriate condition to return control to the TrueFFS driver For further information on implementing the interrupt mechanism please refer to application note AP DOC 063 Improving the Performance of DiskOnChip Plus Devices Using the IRQ Pin 9 5 Platform Specific Issues The following section describes hardware design issues 9 5 1 Wait State Wait states be implemented only when Mobile DiskOnChip Plus 15 designed in a bus that supports a Wait state insertion and supplies a WAIT signal 9 5 2 Big and Little Endian Systems Power PC ARM and other RISC processors can use either Big or Little Endian systems Mobile DiskOnChip Plus

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