Quick Start Guide for GR712 Development Board
Contents
1. Quick Start Guide for GR712RC BOARD 21 GAISLER 6 Support For support contact the Aeroflex Gaisler support team at support gaisler com2. verify hello prom For further information about connecting to the board with GRMON see Chapter 3 4 5 VxWorks 4 5 1 Overview VxWorks is an embedded real time operating system developed by WindRiver Aeroflex Gaisler provides a LEON architectural port HAL and a Board Support Package BSP in full source code for VxWorks The VxWorks package includes a quick start guide and technical support Contact support gaisler com for more information Quick Start Guide for GR712RC BOARD 19 EROFLEX 5 Frequently Asked Questions Common Mistakes Know Issues 5 1 Clock gating Several of the design s peripherals may be clock gated off GRMON will enable all clocks if started with the flag cginit Within GRMON the command greg enable all will have the same effect Alternatively if a boot loader is used instead of GRMON to load an executable then clock gating must be setup via the General Purpose register Clock source divider selection must also be setup for the MIL 1553 SpaceWire and TM cores See Chapter 13 of RD 2 5 2 GRMON issues When connected to the board the message stack pointer not set will be shown by the command info sys in case GRMON doesn t find any memory 5 3 Clock problems Ensure that the jumper JP84 selecting the clock source is always present combination of its absence and the presence of jumper JP88 can lead to unexpected processor behavior When jumper JP88 is present the oscillator in
3. EROFLEX GAISLER Quick Start Guide for GR712 Development Board GR712 BOARD Quick Start Guide QSG GR712 Version 0 1 0 November 2013 Kungsgatan 12 tel 46 31 7758650 411 19 Gothenburg fax 46 31 421407 Sweden www aeroflex com gaisler Quick Start Guide for GR712RC BOARD 2 EROFLEX Quick Start Guide for GR712RC BOARD Copyright 2013 Aeroflex Gaisler AB JEROFLEX Quick Start Guide for GR712RC BOARD lil GAISLER Table of Contents 1 rini ae lern 1 1 1 OVERVICW E ee ea 1 DZ RE em 1 pairaaevouacuo m 2 2 1 OVEIVIEW q EE 2 2 2 Clock SOULCES x ee eh KEENER EAEE KAE EE 2 223 VO o WItCh Matrik Em 3 p LU WW 4 2 5 PROMESSE en Deere ee ee tenes D te TM A DISP el 4 3 GRMON hardware debugger u entente kb Dx retra gu eines it AE EERE 5 3 1 FOVETVIEW RM 5 3 2 Deb g link alternatives i ies nein nen ne 5 3 2 1 Connecting via the FTDI USB JTAG interface u4224ns4Bnsn nen nennnen nennen 5 3 2 2 Connecting via SpaceWire RMAP interface W W u u ssseseeeeeeeeeer renere renere rn rnnnee 9 3 3 uj ice E ser bre 5 3 4 Connecting to the board oi stets neh 6 LM DEI PT m 13 2 du RC wise 13 4 2 Bare C Cxoss Compiler System u a sea 13 CAN OVERVIEW d 13 4 22 Installing BCC nee ea 13 4 2 3 Comp
4. 80000800 RO 13 Aeroflex Gaisl AHB 00000000 AHB 20000000 AHB 40000000 APB 80000000 er AMBA Wrapper for Core1553BRM FFF01000 er CCSDS Telecommand Decoder FFF10100 er CCSDS Telemetry Encoder 80000C00 er SLINK Master 80000900 er Memory controller with EDAC 20000000 40000000 80000000 80000100 8 bit prom 0x00000000 32 bit static 32 bit sdram col 10 cas 2 ram 1 8192 kbyte 0x40000000 2 128 Mbyte 0x60000000 ref 7 8 us Aeroflex Gaisler AHB APB Bridge AHB 80000000 80100000 Aeroflex Gaisler LEON3 Debug Support Unit AHB 90000000 A0000000 AHB trace 256 lines 32 bit bus CPUO win 8 hwbp 2 itrace 256 V8 mul div srmmu lddel 1 GRFPU stack pointer 0x407ffff0 icache dcache CPUl win 8 4 4 kB 32 B line lru 4 4 kB 16 B line lru hwbp 2 itrace 256 V8 mul div srmmu lddel 1 GRFPU stack pointer 0x407ffff0 icache dcache 4 A kB 32 B line lru 4 4 kB 16 B line lru Aeroflex Gaisler AHB APB Bridge AHB 80100000 80200000 Aeroflex Gaisler OC CAN AHB interface AHB FFF30000 IRQ 5 cores 2 FFF31000 Aeroflex Gaisler Generic FT AHB SRAM module AHB A0000000 APB 80100000 A0100000 80100100 JEROFLEX GAISLER Quick Start Guide for GR712RC BOARD uart0 irqmpO gptimer0 spi0 adev25 grgpregO adev27 gpio0 gpiol i2cmstO grcgO ahbstat0 uartl uart2 uart3
5. Board Configuration 2 1 Overview The primary source of information for board configuration is the GR712RC Development Board User Man ual The board requires some hardware configuration to fit with the customer requirements In particular the number of the GR712RC BOARD s processor I O pins limits the simultaneously available connections to external interfaces To overcome this limitation the SoC features an internal switch matrix and a set of jumpers must be configured accordingly to route the signals to the appropriate headers on the board The internal switch matrix is configured by enabling the respective interfaces via software Additionally clock selection might need to be configured by a set of jumpers and possibly the insertion of custom oscillators 9 p Lj s 98m8 JP85 X5 JP3 JP26 ERR Sd P pc Fra 2 E 4 gt JP88 JP1 JP2 EN a Ha dae pnm E JP27 JP66 gt e mm XE e JP84 i E Figure 2 1 GR712RC BOARD default configuration as delivired 2 2 Clock Sources The minimum requirement in order for the board to work and to be able to connect to it is that the clock sources are properly configured The 80 MHz oscillator in socket X2 provided by default with the board is JEROFLEX Quick Start Guide for GR712RC BOARD 3 GAISLER 2 3 connected to the system clock input through the JP84 jumper in the default configuration 2 3 The on board soldered 48 MHz oscillator can be used instead by positi
6. RO 7 0000 Interrupt Ctrl at divisor 48 nes 0 xer Register 1 0 port 1 0 port OC I2C master t initialization ter Latches 8 bit scalar 2 32 bit timers divisor 48 grmon2 info reg GR Ethernet MAC 0x80000e00 Control register 0x80000e04 Status register 0x80000e08 MAC address MSB 0x80000e0c MAC address LSB 0x80000e10 MDIO register 0x80000e14 Tx descriptor register 0x80000e18 Rx descriptor register 0x80000elc EDCL IP register GRSPW2 SpaceWire Serial Link 0x80100800 Control register 0x80100804 Status Interrupt source 0x80100808 Node address 0x8010080c Clock divisor 0x80100810 Destination key 0x80100814 Time 0x80100818 Timer and Disconnect 0x80100820 DMA Channel 0 control status 0x80100824 DMA Channel 0 rx maximum len 0x04000080 0x0000000a 0x00000412 0x10884440 0x7849084a 0x10004000 0xc8000000 0x00000000 0xa0010002 0x00600000 0x000000fe 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 gth 0x00431000 JEROFLEX GAISLER Quick Start Guide for GR712RC BOARD 9 0x80100828 0x8010082c DMA Channel 0 tx desc table address DMA Channel 0 rx desc table address GRSPW2 SpaceWire Serial Link 0x80100900 0x80100904 0x80100908 0x8010090c 0x80100910 0x80100914 0x80100918 0x80100920 0x80100924 0x80100928 0x8010092c Control register Status Interrupt source Node address Clock divisor Destination key Time Timer and Disconnect DMA Cha
7. FTDI USB JTAG interface Please see GRMON User s Manual for how to set up the required FTDI driver software Then connect the PC and the board using a standard USB cable into the USB mini J12 USB JTAG connector and issue the following command grmon ftdi 3 2 2 Connecting via SpaceWire RMAP interface 3 3 GRMON has support for connecting to boards with SpaceWire interfaces as long as the SpaceWire has RMAP and automatic link start An Ethernet to SpaceWire bridge GRESB is required to tunnel SpaceWire packets from the Ethernet network over to SpaceWire Please see the RD 4 for information about connecting through a GRESB and optional parameters Connect the GRESB SpWO connector and the GR712RC BOARDS s J3 SPW 0 or J4 SPW 1 connector then issue the following command grmon gresb First steps The previous sections have described which debug links are available and how to start using them with GRMON The subsections below assume that GRMON the host computer and the GR712RC BOARD board have been set up so that GRMON can connect to the board When connecting to the board for the first time it is recommended to get to know the system by inspecting the current configuration and hardware present using GRMON With the info sys command more details about the system is printed and with info reg the register contents of the I O registers can be inspected Below is a list of items of particular interest AMBA system frequency is prin
8. configuration is correctly set as to enable SDRAM If in doubt you can use a default configuration that supports SDRAM See Section 2 3 for more details Only half of the installed SDRAM will be available in the system as reported by GRMON s info sys com mand This limitation is due to the fact that the SODIMM provides 64 bit data paths but in the standard LEON model only 32 bits of the SDRAM are used plus 16 additional data bits for the RS EDAC memory bits EROFLEX Quick Start Guide for GR712RC BOARD 20 GAISLER 5 7 5 8 5 9 Multiprocessor amp legacy support Code compiled for the single core LEON3 will generally be able to run unmodified on the GR712RC The second core is inactivated after reset and unless it s activated by writing a specific bit in the IRQ controller it will remain inactivated and the chip will behave as a single CPU system Interrupts When using a multiprocessor OS like RTEMS AMP Linux or VxWorks the default IRQ for interprocessor cross calls IRQ 14 clashes with the MIL 1553 Ethernet and Telecommand IP cores The OS may need to be reconfigured by changing the IRQ value which is usually a define in the source code of your operating system and rebuilding it This should not be an issue with single core RTEMS GRMON Debug Link Limitations The GR712RC does not support debugging over Ethernet EDCL is not included in the Ethernet core design Refer to Chapter 3 for an introduction to the supp
9. modelling of the on chip IP cores and AMBA buses It is time based rather that instruction based as TSIM and can be attached to other simulation frameworks such as System C Developer tools are generally provided for both Linux and Windows operating systems Aeroflex Gaisler also provides an integrated easy to use solution to help programmers with the task of developing for the LEON The LEON Integrated Development Environment for Eclipse LIDE is an Eclipse plug in integrat ing compilers software and hardware debuggers in a graphical user interface The plugin makes it possible to cross compile C and C application for LEON and ERC32 and to debug them on either simulator and target hardware TSIM or GRMON The recommended method to load software onto a LEON board is by connecting to a debug interface of the board through the GRMON hardware debugger Execution of programs by a PROM loaded bootloader like u boot is also possible Aeroflex Gaisler provides the free MKPROM tool to encapsulate BCC or RTEMS applications in a simple boot loader Currently u boot for the GR712RC Development Board is not provided by Aeroflex Gaisler 4 2 Bare C Cross Compiler System 4 2 1 Overview The Bare C Cross Compiler BCC for short is a GNU based cross compilation system for LEON proces sors It allows cross compilation of C and C applications for LEON3 4 This section gives the reader a brief introduction on how to use BCC together with the GR712R
10. the board please refer to the GR712RC Development Board User Manual the GR712RC system on chip is described in the GR712RC User Manual This quick start guide does not contain as many technical details and is instead how to oriented However to make the most of the guide the user should have glanced through the aforementioned documents and should ideally also be familiar with the GRMON debug monitor 1 2 References Table 1 1 References RD 1 GR712RC Development Board User Manual RD 2 GR712RC User Manual http gaisler com doc gr712rc usermanual pdf RD 3 GR712RC Data Sheet http www gaisler com doc er712rc datasheet pdf RD 4 GRMON User s Manual http www gaisler com doc grmon2 pdf RD 5 RTEMS homepage http www rtems org RD 6 RTEMS Cross Compilation System RCC http www gaisler com index php prod ucts operating systems rtems RD 7 RCC User s manual http gaisler com anonftp rcc doc RD 8 Aeroflex Gaisler RTEMS driver documentation http gaisler com anonftp rec doc RD 9 GRTOOLS homepage http www gaisler com index php downloads grtools RD 10 Bare C Cross Compilation System http www gaisler com index php products operat ing systems bcc RD 11 BCC User Manual http www gaisler com doc bec pdf RD 12 MKPROM2 User Manual http gaisler com doc mkprom pdf The referenced documents can be downloaded from http www gaisler com Quick Start Guide for GR712RC BOARD 2 EROFLEX 2
11. 09b 0x0000002 0x0000002 0x0000003a 0x00000000 Oxffffffff Oxffffffff 0x00000043 0x00000000 0xa0080048 0xa0080048 0x00000040 0x00000000 EROFLEX GAISLER One can limit the output to certain cores by specifying the core s name s to the info sys and info reg commands As seen below the memory parameters first UART and first Timer core information is listed grmon2 gt info sys mctr10 mctrl0 Aeroflex Gaisler Memory controller with EDAC AHB 00000000 20000000 AHB 20000000 40000000 AHB 40000000 80000000 APB 80000000 80000100 8 bit prom 0x00000000 32 bit static ram 1 8192 kbyte 8 0x40000000 32 bit sdram 2 128 Mbyte 0x60000000 col 10 cas 2 ref 7 8 us grmon2 info sys uart0 gptimer0 uart0 Aeroflex Gaisler Generic UART APB 80000100 80000200 IRO 2 Baudrate 38461 gptimer0 Aeroflex Gaisler Modular Timer Unit APB 80000300 80000400 IRQ 8 16 bit scalar 4 32 bit timers divisor 80 The GR712RC has a clock gating unit which can disable and enable clock gating and generate reset signals of certain cores in the SOC With the GRMON greg command the current setting of the clock gating unit can be inspected and changed the command line switch cginit also affects the clock gating unit See RD 4 for more information Below is an example where the GRETH Ethernet core s clocks are turned on not gated grmon2 grcg GRCLKGATE GR712RC info Unlock register 0x00000000 Clock ena
12. 0x80100d0c 0x80100d10 0x80100d14 0x80100d18 0x80100d20 0x80100d24 0x80100d28 0x80100d2c Control register Status Interrupt source Node address Clock divisor Destination key Time Timer and Disconnect DMA Channel 0 control status DMA Channel 0 rx maximum length DMA Channel 0 tx desc table address DMA Channel 0 rx desc table address AMBA Wrapper for Core1553BRM Oxfff00100 Oxfff00104 Oxfff00108 B1553BRM status control register B1553BRM interrupt settings AHB page address register CCSDS Telecommand Decoder Oxfff10000 Oxfff10004 Oxfffl1000c Oxfff10010 Oxfff10014 Oxfff10018 Oxfff1001c Oxfff10020 Oxfff10024 Oxfff10028 Oxfff1002c Oxfff10030 CCSDS Telemetry 0x80000b00 0x80000b04 0x80000b08 lobal reset register lobal control register pacecraft Identifier Register rame acceptance report register LCW register 1 LCW register 2 Physical Interface Register Control Register Status Register Address Space Register Receive Read Pointer Register Receive Write Pointer Register Encoder DMA control register DMA status register DMA length register Q Q 4H Q Q 0x40004000 0x00000000 0xa0010002 0x00200000 0x000000fe 0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00820000 0x00000000 0x02000000 0x20000100 0x00800000 0x000000fe 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00100040 0x15000000 0x80000000 0x20000000 0x00a00000 0x000000fe 0
13. 53BRM MIL STD 1553 BRM 0 0 1 4 4 R JEROFLEX GAISLER Quick Start Guide for GR712RC BOARD 13 IEROFLEX 4 Software 4 1 Overview Aeroflex Gaisler provides a comprehensive set of software tools to run several different operating systems The LEON platform supports the following workflows Table 4 1 BCC the Bare C Cross Compiler System is a toolchain to compile bare C or C applications directly on top of the processor without the burden and the servises provided by an op erating system RTEMS a hard Real Time Operating System Aeroflex Gaisler provides RCC a toolchain to de velop and compile RTEMS applications specifically for the LEON Linux the open source operating system Board Support Packages and tools to ease the compi lation and deployment of the kernel are provided VxWorks an embedded real time operating system developed by WindRiver Aeroflex Gaisler pro vides a LEON architectural port HAL and a Board Support Package BSP in full source code Hardware simulators for the LEON platform are available in the form of TSIM and GRSIM The TSIM simulator emulates a mono processor computer system based on either the ERC32 or LEON processors It can be extended to emulate custom I O functions through loadable modules The GRSIM simulator emulates a multi processor LEON2 or LEON3 system and has a more accurate
14. C Development Board It will be demon strated how to install BCC build an existing sample project and run it on the board using GRMON 4 2 2 Installing BCC The BCC toolchain includes the GNU C C cross compiler 4 4 2 and 3 4 4 GNU Binutils Newlib em bedded C library the Bare C run time system with interrupt support and the GNU debugger GDB The toolchain can be downloaded from RD 10 and is available for both Linux and Windows Further informa tion about BCC can be found in RD 11 The installation process of BCC is straight forward by first extracting the toolchain into C opt or opt on Linux and in order for the compiler to be found by adding the binary directory opt sparc elf pininto the PATH variable Quick Start Guide for GR712RC BOARD 14 EROFLEX BCC for Windows is provided for native Windows MinGW and for the Cygwin environment 4 2 3 Compiling with BCC The following command shows an example of how to compile a simple Hello World program with BCC sparc elf gcc 02 g hello c o hello exe All gcc options are described in the gcc manual but some useful options are reported below Table 4 2 BCC s GCC compiler relevant options g generate debugging information must be used for debugging with gdb msoft float emulate floating point must be used if no FPU exists in the system mcpu v8 generate SPARC V8 mul div instructions needs hardware multiply and divide 02 or 03 optimize code maximum perf
15. GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler GRSPW2 SpaceWire Serial Link Aeroflex Gaisler AMBA Wrapper for Core1553BRM Aeroflex Gaisler CCSDS Telecommand Decoder Aeroflex Gaisler CCSDS Telemetry Encoder Aeroflex Gaisler SLINK Master Aeroflex Gaisler Memory controller with EDAC Aeroflex Gaisler AHB APB Bridge Aeroflex Gaisler LEON3 Debug Support Unit Aeroflex Gaisler AHB APB Bridge Aeroflex Gaisler OC CAN AHB interface Aeroflex Gaisler Generic FT AHB SRAM module Aeroflex Gaisler Generic UART Aeroflex Gaisler Multi processor Interrupt Ctrl Aeroflex Gaisler Modular Timer Unit Aeroflex Gaisler SPI Controller Aeroflex Gaisler CAN Bus multiplexer Aeroflex Gaisler General Purpose Register Aeroflex Gaisler ASCS Master Aeroflex Gaisler General Purpose I O port Aeroflex Gaisler General Purpose I O port Aeroflex Gaisler AMBA Wrapper for OC I2C master Aeroflex Gaisler Clock gating unit Aeroflex Gaisler AHB Status Register Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Generic UART Aeroflex Gaisler Timer Unit with Latches Aeroflex Gaisler Use command info sys to print a detailed report of attached cores grmon2 info sys cpul Aeroflex Gaisler LEON3 FT SPARC V8 Process
16. Wire 3 SDRAM with optional Reed Solomon Ethernet SPI IC Once the board s jumpers are properly connected the internal switch matrix must be driven by a set of enabling conditions It is important to note that to obtain a proper functioning system the I O interfaces of the required configurations have to be enabled or clock ungated by software See Chapter 2 and Table 9 of RD 2 for further details on the switch matrix The I O matrix is not limited to these pre defined configurations Jumpers can be custom configured accord ing to the user requirements See Section 2 4 of RD 1 for further details UART Jumpers JP1 and JP2 are used to select the output standard of the UARTO and UARTI interfaces between RS232 and RS422 and to route the signals to the J1 and J16 connectors respectively In the default config uration the interfaces are connected to the J1 connectors UART 0 and UART 1 using the RS232 standard While UARTO is not affected by the internal switch matrix UART1 Rx is multiplexed and JP3 must be set to 3 4 in order to use it Refer to the GR712RC Development Board Schematic for more information on how to configure UARTO and UARTI to use the RS422 standard PROM The PROM width and PROM EDAC conditions are set by the state of the GPIO 3 and GPIO 1 pins at power up of the Processor These pins are provided with pull down resistors to set the default mode to 8 bit with no EDAC If EDAC operation of the Flash PROM
17. am exited normally CPU 1 Power down mode To debug the compiled program you can insert break points step and continue directly from the GRMON console Compilation symbols are loaded automatically by GRMON once you load the executable An ex ample is provided below grmon2 gt load rtems hello 40000000 text 136 4kB 136 4kB gt 100 400221A0 data 4 4kB 4 4kB 40023350 jer 4B Total size 140 83kB 781 11kbit s Entry point 0x40000000 Image home andrea Desktop samples rtems hello loaded grmon2 gt bp Init Software breakpoint 1 at lt Init gt grmon2 gt run CPU 0 breakpoint 1 hit 0x400011f8 1110007 sethi hi 0x4001FC00 00 lt Init 4 gt CPU 1 Power down mode grmon2 gt step 0x400011f8 1110007f sethi hi 0x4001FC00 00 lt Init 4 gt grmon2 gt step 0x400011fc 4000003b call 0x400012E8 lt Init 8 gt grmon2 gt cont Hello World CPU 0 Program exited normally CPU 1 Power down mode EROFLEX Quick Start Guide for GR712RC BOARD 17 GAISLER grmon2 gt Exiting GRMON Alternatively you can run GRMON with the gdb command line option and then attach a gdb session to it For further information see Chapter 3 of RD 7 4 4 MKPROM2 4 4 1 Overview To run application from the on board PROM it s necessary to create a bootable PROM image file MKPROM2 is a utility program to create boot images for programs compiled with the BCC or RTEMS cross compiler It encapsulates the applicati
18. ble register 0x00000006 Reset register 0x00000ff9 GR712RC decode of values 4 4 Gate Core s Description 4 Unlocked Enabled Reset Quick Start Guide for GR712RC BOARD 12 0 GRETH 10 100 Ethernet MAC 0 0 1 GRSPW Spacewire link 0 0 1 0 2 GRSPW Spacewire link 1 0 i 0 3 GRSPW Spacewire link 2 0 0 4 GRSPW Spacewire link 3 0 0 5 GRSPW Spacewire link 4 0 0 6 GRSPW Spacewire link 5 0 0 7 CAN CAN core 1 amp 2 0 0 8 SatCAN SatCAN controller 0 0 9 GRTM Telemetry Encoder 0 0 10 GRTC Telecommand Decoder 0 0 11 B1553BRM MIL STD 1553 BRM 0 0 T m 4 eee qp grmon2 gt grcg enable 0 grmon2 gt grcg GRCLKGATE GR712RC info Unlock register 0x00000000 Clock enable register 0x00000007 Reset register 0x00000ff8 GR712RC decode of values 4 quee aS e recu Ecc 4 4 Gate Core s Description Unlocked Enabled Reset t 4R 4 444 0 GRETH 10 100 Ethernet MAC 0 1 0 1 GRSPW Spacewire link 0 0 1 0 2 GRSPW Spacewire link 1 0 1 0 3 GRSPW Spacewire link 2 0 0 1 4 GRSPW Spacewire link 3 0 0 aE 5 GRSPW Spacewire link 4 0 0 1 6 GRSPW Spacewire link 5 0 0 1 3 CAN CAN core 1 amp 2 0 0 1 8 SatCAN SatCAN controller 0 0 1 9 GRTM Telemetry Encoder 0 0 1 10 GRTC Telecommand Decoder 0 0 1 11 B15
19. e unnecessary at lower frequencies To generate a boot PROM for a GR712RC Development Board and running your program from SDRAM mkprom2 leon3 freq 80 rmw nosram sdram 128 romsize 65536 baud 38400 o hello prom hello exe This example command will again work for a board in the default configuration at delivery The nosram option will disable the SRAM and the sdram option sets the size of the available SDRAM This value is 128 MB which is the value for the SODIMM provided by default with the board When SRAM is disabled the SDRAM address range is moved from 0x60000000 to 0x40000000 therefore not requiring recompilation of executables To run your program in SDRAM without disabling SRAM you need to link your program to the 0x60000000 address at compilation time See the manual of your toolchain for more information It s required that the MKPROM2 command line parameters match your system configuration For more information about command line options please refer to RD 12 If EDAC is enabled on the board s PROM then the bch8 flag must be included in the command line The generated PROM image that needs to be flashed on the device in this case would be hello prom bch8 Once the PROM file is generated it can be loaded onto the board with GRMON Once GRMON is attached to the board run the following commands to program the PROM flash flash erase all flash load hello prom Quick Start Guide for GR712RC BOARD 18 IEROFLEX
20. eported below Quick Start Guide for GR712RC BOARD 16 EROFLEX Table 4 3 RCC s GCC compiler relevant options g generate debugging information must be used for debugging with gdb msoft float emulate floating point must be used if no FPU exists in the system mcpu v8 generate SPARC V8 mul div instructions needs hardware multiply and divide 02 or 03 optimize code maximum performance and minimal code size qleon3std generate LEON3 4 executable without driver manager startup initialization qleon3mp generate LEON3 4 Multiprocessor executable AMP 4 3 4 Running and debugging with GRMON Once your executable is compiled connect to your GR712RC BOARD with GRMON The following log shows how to load and run an executable Note that the console output is redirected to GRMON by the use of the u command line switch so that printf output is shown directly in the GRMON console andrea localhost samples grmon ftdi u GRMON2 LEON debug monitor v2 0 42 internal version Copyright C 2013 Aeroflex Gaisler All rights reserved For latest updates go to http www gaisler com Comments or bug reports to support gaisler com Parsing ftdi Parsing u grmon2 gt load rtems hello 40000000 text 136 4kB 136 4kB 400221A0 data 4 4kB 4 4kB 40023350 jcr 4B Total size 140 83kB 780 05kbit s Entry point 0x40000000 Image home andrea Desktop samples rtems hello loaded grmon2 gt run Hello World CPU 0 Progr
21. iling with BCC is iiie tae ette a egere Dia 14 4 2 4 Running and debugging with GRMON rn nenn 14 4 3 RTEMS Real Time Operating System sess HH 15 4 3 1 OVELVIEW ice ite ett ht te Re theol pakteub tas debt E EEE S EOE EEE e DAP EE 15 4 3 2 Installing ROC a ne a aging 15 4 3 3 Building an RTEMS sample application see 15 4 3 4 Running and debugging with GRMON sean nenn 16 LE MKPROM M RT 17 AA T OVERVIEW M ice inch 17 442 Usage Of MK PROM 1220508 manne her rennen Pau Dee deals 17 AD AQ I C p dba mean ehe dass 18 4 5 1 OV EVI W EEUU 18 5 Frequently Asked Questions Common Mistakes Know Issues eeeA 19 REG gcn 19 5 2 GRMON TSSUES c c use en 19 3 3 Clock problems 19 5 4 Switch Matrix Configuration Problems u 4444Bneennennnen eme 19 oP E 9 essen 19 5 6 SDRAM configuration ea aan 19 5 7 Multiprocessor amp legacy support ss 20 3 8 rwn o une une ni 20 5 9 GRMON Debug Link Limitations ss 20 9 10 MIL ISSS 2 enable 20 ENDO NM 21 Quick Start Guide for GR712RC BOARD 1 IEROFLEX 1 Introduction 1 1 Overview This document is a quick start guide for the GR712RC Development Board The purpose of this document is to get users quickly started using the board For a complete description of
22. is desired then jumper JP85 should be installed to pull up GPIO 1 JEROFLEX Quick Start Guide for GR712RC BOARD 5 GAISLER 3 GRMON hardware debugger 3 1 3 2 Overview GRMON is a debug monitor used to develop and debug GRLIB LEON systems The CPU and its peripherals are accessed on the AMBA bus through a debug link connected to the PC GRMON has GDB support which makes C C level debugging possible by connecting GDB to the GRMON s GDB socket With GRMON one can for example Inspect LEON and peripheral registers Upload applications and or program the FLASH Control execution flow by starting applications run continue execution cont single stepping step inserting breakpoints watchpoints bp etc e Inspect the current CPU state listing the back trace instruction trace and disassemble machine code The first step is to set up a debug link in order to connect to the board The following section outlines which debug interfaces are available and how to use them on the GR712RC Development Board after that a basic first inspection of the board is exemplified Several of the SoC s peripherals may be clock gated off GRMON will enable all clocks if started with the flag cginit Within GRMON the command greg enable all will have the same effect GRMON is described on the homepage http www gaisler com index php products debug tools and in detail in RD 4 Debug link alternatives 3 2 1 Connecting via the
23. mpers JP3 through JP66 all multiplexed switch matrix signals are connected to the board s GPIO pins Six basic example configurations are provided to respond to typical use cases as seen in Table 2 1 To use one of these configurations the user has to insert jumpers JP3 through JP66 in the position described in the table Refer to RD 1 and GR712RC Development Board Schematic for more information on signal and GPIO configuration Table 2 1 Typical configurations Cfg description I O enabled ursi position UARTO UARTI UART2 UART3 UART4 UARTS B SpaceWire 0 SpaceWire 1 SpaceWire 2 SpaceWire 3 SpaceWire 4 SpaceWire 5 CPU for GEO applications ea 1553 A Mil Std 1983 8 SPI PC CPU for TMTC applications UARTO UARTI UART2 UART3 C SpaceWire 0 SpaceWire 1 SpaceWire 2 SpaceWire 3 SDRAM with optional Reed Solomon CCSDS ECSS TC amp TM CPU for LEO applications UARTO UART1 UART2 UART3 UART4 UARTS D Space Wire 0 SpaceWire 1 SDRAM with optional Reed Solomon ASCS16 CAN A CAN B SLINK Dc Instrument Controller type A UARTO UARTI UART2 UART3 UART4 UARTS E SpaceWire 0 SpaceWire 1 SDRAM with optional Reed Solomon CAN A CAN B SLINK JEROFLEX Quick Start Guide for GR712RC BOARD 4 GAISLER Cfg description I O enabled eee position PC Instrument Controller type B UARTO UARTI UART2 UART3 UART4 UARTS F 2 4 2 5 SpaceWire 0 SpaceWire 1 SpaceWire 2 Space
24. nd for multi core development see RD 7 for more information The LEON BSP specific drivers are documented in RD 8 Samples RTEMS projects are available within the toolchain package installed into rtems x y src samples 4 3 2 Installing RCC The RCC toolchain is downloadable from the RCC homepage at RD 6 The full installation procedure is found in the RCC manual RD 7 Windows users are recommended to install the UNIX like environment MSYS before proceeding The installation process of RCC is straight forward by first extracting the toolchain into C opt or opt on Linux then extracting the source distribution into the opt rtems x y src directory In order for the compiler to be found one has to add the binary directory opt rtems x y bin into the PATH variable as below cd opt tar xf sparc rtems 4 10 linux tar bz2 cd rtems 4 10 src tar xf rtems 4 10 src tar bz2 export PATH SPATH opt rtems 4 10 bin dn 40 40 YH The GRTOOLS package RD 9 includes a set of UNIX tools together with a MSYS environment suitable for RCC 4 3 3 Building an RTEMS sample application Once the toolchain is set up you can compile and link a sample RTEMS application by doing Sparc rtems gcc g 02 rtems hello c o rtems hello RCC s gcc creates executables for LEON3 4 by default The default load address is at the start of the RAM i e 0x40000000 All compilation options are described in RD 7 but some useful options are r
25. ng unit 0x80000d00 Unlock register 0x80000d04 Clock enable register 0x80000d08 Reset register AHB Status Register 0x80000f00 Status register 0x80000f04 Failing address register Generic UART 0x80100104 UART Status register 0x80100108 UART Control register 0x8010010c UART Scaler register Generic UART 0x80100204 UART Status register 0x80100208 UART Control register 0x8010020c UART Scaler register Generic UART 0x80100304 UART Status register 0x80100308 UART Control register 0x8010030c UART Scaler register Generic UART 0x80100404 UART Status register 0x80100408 UART Control register 0x8010040c UART Scaler register Generic UART 0x80100504 UART Status register 0x80100508 UART Control register 0x8010050c UART Scaler register Timer Unit with Latches 0x80100600 Scalar value register 0x80100604 Scalar reload value register 0x80100608 Configuration register 0x8010060c Latch configuration register 0x80100610 Timer Value register 0x80100614 Timer Reload value register 0x80100618 Timer Control register 0x8010061c Timer Latch register 0x80100620 Timer Value register 0x80100624 Timer Reload value register 0x80100628 Timer Control register 0x8010062c Timer Latch register PRPRPROOOO 11 0x00000000 0x00000007 0x00000ff8 0x00000012 0x80000f04 0x00000086 0x80000003 0x0000009b 0x00000086 0x80000003 0x0000009b 0x00000086 0x80000003 0x0000009b 0x00000086 0x80000003 0x0000009b 0x00000086 0x80000003 0x00000
26. nnel 0 control status DMA Channel 0 rx maximum length DMA Channel 0 tx desc table address DMA Channel 0 rx desc table address GRSPW2 SpaceWire Serial Link 0x80100a00 0x80100a04 0x80100a08 0x80100a0c 0x80100a10 0x80100a14 0x80100a18 0x80100a20 0x80100a24 0x80100a28 0x80100a2c Control register Status Interrupt source Node address Clock divisor Destination key Time Timer and Disconnect DMA Channel 0 control status DMA Channel 0 rx maximum length DMA Channel 0 tx desc table address DMA Channel 0 rx desc table address GRSPW2 SpaceWire Serial Link 0x80100b00 0x80100b04 0x80100b08 0x80100b0c 0x80100b10 0x80100b14 0x80100b18 0x80100b20 0x80100b24 0x80100b28 0x80100b2c Control register Status Interrupt source Node address Clock divisor Destination key Time Timer and Disconnect DMA Channel 0 control status DMA Channel 0 rx maximum length DMA Channel 0 tx desc table address DMA Channel 0 rx desc table address GRSPW2 SpaceWire Serial Link 0x80100c00 0x80100c04 0x80100c08 0x80100c0c 0x80100c10 0x80100c14 0x80100c18 0x80100c20 0x80100c24 0x80100c28 0x80100c2c Control register Status Interrupt source Node address Clock divisor Destination key Time Timer and Disconnect DMA Channel 0 control status DMA Channel 0 rx maximum length DMA Channel 0 tx desc table address DMA Channel 0 rx desc table address GRSPW2 SpaceWire Serial Link 0x80100d00 0x80100d04 0x80100d08
27. on in a loader suitable to be placed in a boot PROM The appli cation is compressed with a modified LZSS algorithm typically achieving a compression factor of 2 The boot loader operates in the following steps The register files of IU and FPU if present are initialized The memory controller UARTs and timer unit are initialized according to the specified options The application is decompressed and copied into RAM Finally the application is started setting the stack pointer to the top of RAM 4 4 2 Usage of MKPROM2 The MKPROM2 tool can be downloaded from the Aeroflex Gaisler website http gaisler com index php downloads compilers No installation is required but the directory containing the executable must be in cluded in the system s PATH together with a valid SPARC toolchain sparc elf sparc rtems or sparc linux To generate a boot PROM for a GR712RC Development Board and running your program from SRAM mkprom2 leon3 freq 80 rmw ramsize 8192 romsize 65536 baud 38400 ramws 1 o hello prom hello exe This example command will work for a board in the default configuration at delivery with a system clock frequency of 80 MHz The ramsize and romsize options are expressed in KB The former value is 8MB the size of the SRAM The latter value is 64 MB the size of the on board flash Finally the ramws option sets the number of wait states during SRAM access to 1 needed when running the system at 80 MHz but might b
28. oning the JP84 jumper on pins 1 2 Alternatively a custom oscillator can be installed in X2 The SpaceWire clock is by default driven by an on board additional 100 MHz oscillator If the user wants to use the system clock configured in the paragraph above as the source of the SpaceWire clock then jumper JP88 must be inserted and the oscillator in socket X5 must be removed Refer to Section 2 14 of RD 1 for further information about oscillators and clock inputs and more infor mation about the system and SpaceWire clock Once the external clock sources are selected further clock configuration can be done in software The SpaceWire external clock source can be used as 1X 2X or 4X or the external system clock can be used in its place This selection is done by configuring the SoC s General Purpose Register GPREG At reset the 1X SpaceWire clock received from the board is used internally For in depth information about configuring the SpaceWire and MIL STD 1553 clocks through the GPREG please refer to Chapter 3 and Chapter 13 of RD 2 I O Switch Matrix To overcome the limitation on the number of SoC pins an internal switch matrix selects the input output signals to connect to the pad Additionally the chip I O pins are connected to the board s I O ports through an array of jumpers One UART and two SpaceWire interfaces are routed independently of the internal switch matrix and the jumpers JP3 through JP66 In the default position A of ju
29. or AHB Master 0 cpul Aeroflex Gaisler LEON3 FT SPARC V8 Processor AHB Master 1 ahbjtag0 Aeroflex Gaisler JTAG Debug Link AHB Master 2 greth0 Aeroflex Gaisler GR Ethernet MAC AHB Master 3 Quick Start Guide for GR712RC BOARD 7 satcan0 grspw0 grspwl grspw2 grspw3 grspw4 grspw5 b1553brm0 grtc0 grtm0 adev14 mctr10 apbmst 0 dsu0 apbmst1 occanO ahbram0 APB 80000E00 IRQ 14 80000F00 Aeroflex Gaisler SatCAN controller AHB Master 4 AHB FFF20000 IRO 14 FFF20100 Aeroflex Gaisler GRSPW2 SpaceWire Serial Link AHB Master 5 APB 80100800 IRO 22 80100900 Number of ports 1 Aeroflex Gaisler GRSPW2 SpaceWire Serial Link AHB Master 6 APB 80100900 IRO 23 80100A00 Number of ports 1 Aeroflex Gaisler GRSPW2 SpaceWire Serial Link AHB Master 7 APB 80100A00 IRO 24 80100B00 Number of ports 1 Aeroflex Gaisler GRSPW2 SpaceWire Serial Link AHB Master 8 APB 80100B00 IRO 25 80100C00 Number of ports 1 Aeroflex Gaisler GRSPW2 SpaceWire Serial Link AHB Master 9 APB 80100C00 IRO 26 80100D00 Number of ports 1 Aeroflex Gaisler GRSPW2 SpaceWire Serial Link AHB Master 10 APB 80100D00 IRQt 27 80100E00 Number of ports 1 Aeroflex Gaisl AHB Master 11 AHB FFF00000 RO 14 Aeroflex Gaisl AHB Master 12 AHB FFF10000 RO 14 Aeroflex Gaisl AHB Master 13 APB 80000B00 RO 29 Aeroflex Gaisl AHB Master 14 APB
30. ormance and minimal code size qsvt use the single vector trap model qnoambapp disable AMBA Plug amp Play recursive scanning across AHB2AHB bridges cre ates a leaner software image 4 2 4 Running and debugging with GRMON Once your executable is compiled connect to your GR712RC BOARD with GRMON The following log shows how to load and run an executable Note that the console output is redirected to GRMON by the use of the u command line switch so that printf output is shown directly in the GRMON console andrea localhost Desktop grmon ftdi u GRMON2 LEON debug monitor v2 0 42 professional version Copyright C 2013 Aeroflex Gaisler All rights reserved For latest updates go to http www gaisler com Comments or bug reports to support gaisler com Parsing ftdi Parsing u grmon2 gt load hello exe 40000000 text 23 6kB 23 6kB 40005E70 data 2 7kB 2 7kB Total size 26 29kB 803 58kbit s Entry point 0x40000000 Image home andrea Desktop hello exe loaded gt 100 gt 100 grmon2 gt run Hello world CPU 0 Program exited normally CPU 1 Power down mode To debug the compiled program you can insert break points step and continue directly from the GRMON console Compilation symbols are loaded automatically by GRMON once you load the executable An ex ample is provided below grmon2 gt load hello exe 40000000 text 23 6kB 23 6kB 40005E70 data 2 7kB 2 7kB Total
31. orted debug links 5 10 MIL 1553 The 1553 IP core in the GR712RC is an Actel Core1553BRM with an AMBA adapter devel oped by Aeroflex Gaisler Actel s core is documented on Actel s website http www actel com ip docs Core1553BRM_HB pdf while the wrapper is documented in RD 2 The correct RTEMS driver to use for the MIL 1553 core is B1553BRM This should not be confused with GR1553B which is the driver for Aeroflex Gaisler s in house developed core To use the core users need to set up clock gating and clock selection with the general purpose register There are some restrictions on what clock frequencies can be used see Section 3 3 of RD 2 Users also need to set a register inside the Core1553BRM to match the BRM frequency used This is usually done by the driver in the RTEMS VxW case default is 24 MHz Below is provided an example routine for setting up GR712RC clocking to external 24 MHz clock This routine can be used for instance as mkprom2 bdinit In this case it needs to be compiled with O2 to avoid using stack static void gr712 init void volatile unsigned long p Select external 1553 clk through GPREG p volatile unsigned long 0x80000600 xp 0x20 Ungate 1553 clock and reset volatile unsigned long 0x80000D00 1 lt lt 11 3 1 lt lt 11 3 1 lt lt 11 et Core1553BRM to 24 MHz operation volatile unsigned long OxFFF00000 D fp fp to oto fd tg mme JEROFLEX
32. ration Register Generic UART 0x80000104 UART Status register 0x80000108 UART Control register 0x8000010c UART Scaler register Multi processor Interrupt Ctrl 0x80000200 Interrupt level register 0x80000204 Interrupt pending register 0x80000210 Interrupt status register 0x80000240 Interrupt mask register 0 0x80000244 Interrupt mask register 1 0x80000280 Interrupt force register 0 0x80000284 Interrupt force register 1 Modular Timer Unit 0x80000300 Scalar value register 0x80000304 Scalar reload value register 0x80000308 Configuration register 0x80000310 Timer 0 Value register 0x80000314 Timer 0 Reload value register 0x80000318 Timer 0 Control register 0x80000320 Timer 1 Value register 0x80000324 Timer 1 Reload value register 0x80000328 Timer 1 Control register 0x80000330 Timer 2 Value register 0x80000334 Timer 2 Reload value register 0x80000338 Timer 2 Control register 0x80000340 Timer 3 Value register 0x80000344 Timer 3 Reload value register 0x80000348 Timer 3 Control register SPI Controller 0x80000400 Capability register 0x80000420 Mode register 0x80000424 Event register 0x80000428 Mask register 0x8000042c Command register 0x80000430 Transmit register 0x80000434 Receive register General Purpose Register 0x80000600 GR712RC general purpose register General Purpose I O port 0x80000900 O port data register 0x80000904 O port output register 0x80000908 O port direction register 0x8000090c O interrupt mask register 0x80000910 O interrup
33. size 26 29kB 806 59kbit s Entry point 0x40000000 Image home andrea Desktop hello exe loaded gt 100 gt 100 grmon2 gt bp main Software breakpoint 1 at lt main gt grmon2 gt run CPU 0 breakpoint 1 hit 0x40001928 b0102000 mov 0 i0 lt main 4 gt CPU 1 Power down mode Quick Start Guide for GR712RC BOARD 15 EROFLEX grmon2 gt step 0x40001928 b0102000 mov 0 i0 lt main 4 gt grmon2 gt step 0x4000192c 11100017 sethi hi 0x40005C00 00 lt main 8 gt grmon2 gt cont Hello world CPU 0 Program exited normally CPU 1 Power down mode grmon2 gt Exiting GRMON Alternatively you can run GRMON with the gdb command line option and then attach a gdb session to it For further information see Chapter 3 of RD 11 4 3 RTEMS Real Time Operating System 4 3 1 Overview RTEMS is a real time operating system maintained at RD 5 that supports the LEON CPU family Aeroflex Gaisler distributes a precompiled RTEMS toolchain for LEON called RCC RD 6 This section gives the reader a brief introduction on how to use RTEMS together with the GR712RC Development Board It will be demonstrated how to install RCC and build an existing sample RTEMS project from RCC and run it on the board using GRMON The RCC toolchain includes a prebuilt toolchain with GNU BINUTILS GCC NewlibC and GDB for Linux and Windows mingw It also contains prebuilt RTEMS kernels for the LEON2 LEON3 4 BSPs single core a
34. socket X5 which is provided by default must be disconnected or it will short with the main clock source leading to possible damage to the oscillators and unexpected behavior 5 4 Switch Matrix Configuration Problems Ensure that the jumper array is properly configured and that any I O peripheral required is clock ungated or enabled The internal switch matrix routing is explained more in depth in Chapter 2 of GR712RC User Manual If an IP core behaves correctly as seen from software but does not receive transmit any data from the out side first check that the jumper array is properly configured The problem might also arise when conflicting cores are enabled Check Table 8 from RD 2 for further information on conflicting cores 5 5 GPIO Some of the GPIOs have special meaning on power up GPIO 1 and GPIO 3 configure the PROM area of the memory controller and GPIO 42 GPIO 40 GPIO 37 and GPIO 34 are used for the SPW clock divider reset value These pins are provided with pull down resistors by default If measuring the state of these GPIO pins please take into account the effect of these pull down resistors Conversely if an external signal is connected to the GPIO 3 and GPIO 1 pins this may override the expected state of the pin at power up See Section 2 3 2 and Section 2 6 2 of RD 1 for more information 5 6 SDRAM configuration SDRAM is by default not configured on the board Ensure that the switch matrix jumper
35. t polarity register 0x80000914 O interrupt edge register 0x80000918 O bypass register General Purpose I O port 0x80000a00 O port data register 0x80000a04 O port output register 0x80000a08 O port direction register 0x80000a0c O interrupt mask register 0x80000a10 O interrupt polarity register 0x80000a14 O interrupt edge register 0x80000a18 O bypass register AMBA Wrapper for OC I2C master 0x80000c00 Clock prescale register 0x80000c04 Control register 0x80000c08 Receive register 0x80000c0c Status register 0x00000000 0x00010001 0x00000000 0x00000000 Ox001affdf 0x00000000 0x00000000 0x352ef853 0x00000000 0x00000000 0x00000000 0x00000000 0x0003c0ff 0x8ac05460 0x08174000 0x00000003 0x000000ef 0x000000b0 0x6911d034 0x6911d034 0x00200000 0x00000086 0x80000003 0x0000009b 0x00000000 0x00000000 0x180c0002 0x00000000 0x00000000 0x00000000 0x00000000 0x0000002 0x0000002f 0x00000144 Oxffffffff Oxffffffff 0x00000043 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x00000040 Oxfal6f3e8 Oxfffffffe 0x00000040 0x01001002 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x20880021 0x00000000 0x419ff955 0x00000000 0x00000000 0x00000000 0x00000058 0x00001100 0x00000000 Oxfffl9ad9 0x00000000 0x00000000 0x00000000 0x00000001 0x0000e00c 0x00000000 0x0000005f 0x00000000 0x00000000 0x00000000 JEROFLEX GAISLER Quick Start Guide for GR712RC BOARD Clock gati
36. ted out at connect if the frequency is wrong then it might be due to noise in auto detection small error See freq flag in RD 4 Memory location and size configuration is found from the info sys output If the board has both SRAM and SDRAM interfaces SDRAM can be mapped at the SRAM base address using the nosram option of GRMON See RD 4 for further details Quick Start Guide for GR712RC BOARD 6 EROFLEX The GR712RC has a clock gating unit which is able to disable enable clocking and control reset signals Clocks must be enabled for all cores that LEON software or GRMON will be using The greg command is described in RD 4 3 4 Connecting to the board In the following example the FTDI debug link is used to connect to the board The auto detected frequency memory parameters and stack pointer are verified by looking at the GRMON terminal output below daniel daniel grmon ftdi GRMON2 LEON debug monitor v2 0 35 professional version Copyright C 2012 Aeroflex Gaisler All rights reserved For latest updates go to http www gaisler com Comments or bug reports to support gaisler com Parsing ftdi Commands missing help debug datacache JTAG chain 1 GR712RC Detected system GR712RC Detected frequency 80 MHz Component Vendor LEON3 FT SPARC V8 Processor Aeroflex Gaisler LEON3 FT SPARC V8 Processor Aeroflex Gaisler JTAG Debug Link Aeroflex Gaisler GR Ethernet MAC Aeroflex Gaisler SatCAN controller Aeroflex Gaisler
37. uart4 uart5 grtimer0 32 bit static ram 256 kB 0xa000 Aeroflex Gaisler Generic UART APB 80000100 80000200 IRQ 2 Baudrate 3846 Aeroflex Gaisler Multi processor APB 80000200 80000300 EIRO 12 Aeroflex Gaisler Modular Timer Un APB 80000300 80000400 IRQ 8 16 bit scalar 4 32 bit timers Aeroflex Gaisler SPI Controller APB 80000400 80000500 IRQ 3 FIFO depth 16 no slave select li Maximum word length 32 bits Controller index for use in GRMON Aeroflex Gaisler CAN Bus multiple APB 80000500 80000600 Aeroflex Gaisler General Purpose APB 80000600 80000700 Aeroflex Gaisler ASCS Master APB 80000700 80000800 IRQ 6 Aeroflex Gaisler General Purpose APB 80000900 80000A00 Aeroflex Gaisler General Purpose APB 80000A00 80000800 Aeroflex Gaisler AMBA Wrapper for APB 80000C00 80000D00 IRO 28 Aeroflex Gaisler Clock gating uni APB 80000D00 80000E00 GRMON did NOT enable clocks during Aeroflex Gaisler AHB Status Regis APB 80000F00 80001000 RO Aeroflex Gaisler Generic UART APB 80100100 80100200 RO 7 Baudrate 3846 Aeroflex Gaisler Generic UART APB 80100200 80100300 RO 8 Baudrate 3846 Aeroflex Gaisler Generic UART APB 80100300 80100400 RO 9 Baudrate 3846 Aeroflex Gaisler Generic UAR APB 80100400 80100500 RO 20 Baudrate 3846 Aeroflex Gaisler Generic UARI APB 80100500 80100600 ROT 21 Baudrate 3846 Aeroflex Gaisler Timer Unit with APB 80100600 80100700
38. x00000000 0x00000000 0x00000000 0x00000000 0x00000014 0x00323084 0x5c406400 0xa701b800 0x20000000 0x00a00000 0x000000fe 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01410104 0x488b0800 0x20aaf800 0x20000200 0x00a00000 0x000000fe 0x00000000 0x00000000 0x00000000 0x00000000 0x00000004 0x0040032c 0x01800000 0x06002000 0xc5040001 0xc5040001 0xc5040001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000004 0x00000000 0x00400002 JEROFLEX GAISLER Quick Start Guide for GR712RC BOARD 10 0x80000b0c DMA descriptor pointer register 0x80000b14 DMA revision register 0x80000b80 Control register 0x80000b84 Status register 0x80000b88 Configuration register 0x80000b90 Physical layer register 0x80000b94 Coding sub layer register 0x80000b98 Attached Synchronization Marker 0x80000ba0 All frames generation register 0x80000ba4 Master frame generation register 0x80000ba8 Idle frame generation register 0x80000bd0 OCF register Memory controller with EDAC 0x80000000 Memory config register 1 0x80000004 Memory config register 2 0x80000008 Memory config register 3 LEON3 Debug Support Unit 0x90000024 Debug mode mask register 0x90000000 CPU 0 Control register 0x90400020 CPU 0 Trap register 0x90100000 CPU 1 Control register 0x90500020 CPU 1 Trap register Generic FT AHB SRAM module 0x80100000 Configu
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