COM-1826 Receiver for TDRSS Demand Access Service
Contents
1. REG36 LSB IP1 static address 4 byte IPv4 address used for SDDS left LAN input stream connector on Example 0x AC 10 01 80 designates packpanel address 172 16 1 128 The new address becomes effective immediately no need to reset the ComBlock REG37 MSB REG40 LSB IP2 address right 4 byte IPv4 address used for receiver LAN connector on output monitoring and control backpanel Example 0x AC 10 01 80 designates address 172 16 1 128 The new address becomes effective immediately no need to reset the ComBlock REG41 MSB REG44 LSB 4 byte IPv4 address Status Registers Parameters Monitoring Hardware self check External 10 MHz presence Input sampling rate Time tag Input frame counter Missing input frame counter SREG28 LSB SREG29 MSB CRC counter MAC address Demodulator carrier lock status Code lock status Viterbi decoder1 synchronized Viterbi decoder2 synchronized Signal presence Decoder1 built The Viterbi decoder computes the BER in BER on the received encoded data stream At power up the hardware platform performs a quick self check The result is stored in status registers SREGO 9 Properly operating hardware will result in the following sequence being displayed SREG0 SREG9 01 F1 1D xx 1F 93 10 22 22 03 1 detected 0 missing SREG9 0 The sampling rate as read from the SDDS input stream Format sampling rate fclk 2 32 SREG102. bit 7 0 LSB SREGI1 bit 15 8 SREG12 bit 23 16 Last valid timetag read from the SDDS input header Expressed in 250ps units Cumulative SDDS frame counter Each frame contains 1024 bytes 256 complex samples SREG22 LSB SREG25 MSB Cumulative number of missing SDDS frames Should be zero SREG26 LSB SREG27 MSB Unique 48 bit hardware address 802 3 In the form SREG30 SREG31 SREG32 ISREG35 SREG36 0 0 unlocked or no input 1 locked SREG36 1 0 unlocked or no input 1 locked 1 s hysteresis SREG36 2 0 not synchronized or no input 1 synchronized SREG36 3 0 not synchronized or no input 1 synchronized SREG36 4 0 no carrier detected in FFT 1 carrier detected in FFT Decoder built in BER Nominal center frequency Carrier frequency offset Carrier frequency offset2 Despread signal power S Noise power N irrespective of the transmitted bit stream Encoded stream bit errors detected over a 1000 bit measurement window SREG37 LSB SREG38 MSB The Viterbi decoder computes the BER on the received encoded data stream irrespective of the transmitted bit stream Encoded stream bit errors detected over a 1000 bit measurement window SREG39 LSB SREG40 MSB Expected center frequency sum of the fixed center frequency and the dynamic frequency profile table SREG41 LSB SREG44 MSB Residual frequency offset with respect to the nominal
3. 16 1 Multicast IP address 225 0 MAC address 00 00 00 00 00 00 input sampling rate Input frame counter I code 275 Q code 1337 Octal Chiprate 3077800 298 Chips s I channel symbol rate 9999 989 Symbols s Q channel symbol rate Symbals s Input center frequency 0 Hz Spectrum inversion FEC decoding Modulation BPSK Encoding NRZ FJ COM1826 TDRSS DAS receiver Basic Settings Static IP address 172 16 1l 2 Subnet mask 255 255 255 0 Gateway address 172 16 1 3 Destination IP address 172 16 1 45 1026 E u Configuration Advanced Alternatively users can access the full set of configuration features by specifying 8 bit control registers as listed below These control registers can be set manually through the ComBlock Control Center or by software using the ComBlock API see www comblock com download M amp C_reference pdf All control registers are read write Definitions for the Control registers and Status registers are provided below Control Registers Q channel Approximate i e rounded ratio of chip spreading factor rate symbol rate The module configuration parameters are stored in volati
4. 283 291 299 f l i Hh i i l i 67 75 83 91 99 107 115 123 131 139 147 155 163 171 179 187 195 203 211 219 227 235 243 251 259 267 275 283 291 299 Plot Settings Trigger Settings Autoscale X Min XMax Y Min Y Max Rescale Signal Representation Threshold Edge Position _ A 67 302 80 78 2 SbitSigned 0 w Rising v 10 v Close Apply Changes Re arm Trigger Force Trigger Plot ComScope example showing demodulated l channel tl Te Points Test Definition Peint UDP TCP input data activity SDDS receive data valid flag from UDP or when the sender is not fast enough A3 Recovered carrier center frequency coarse A4 Carrierlock o PAS Codelock S All I channel before despreading compare with code replica Demodulated bit 1 Demodulated bit Q BER tester synchronized 1 when no FEC FEC 1K bits Viterbi decoder Q synchronized pulse every 1K bits Operation Monitoring amp Control M amp C is possible over USB and LAN TCP A pre requisite for using USB is the prior installation of the ComBlock USB driver Remote monitoring and control is only through the right LAN connector on the backpanel the left LAN connector is reserved for the SDDS input stream At manufacturing the default M amp C LAN address is 172 16 1 1 It can be subsequently changed via USB or LAN TCP SDDS input stream The left LAN connector on the back panel is reserved
5. carrier frequency i e after frequency profile correction Part 1 2 32 bit signed integer expressed as fcerror 2 fox p SREG45 LSB SREG48 MSB Residual frequency offset with respect to the nominal carrier frequency i e after frequency profile correction Part 22 32 bit signed integer expressed as fcerror 2 fenip rate SREG49 LSB SREGS2 MSB Average signal power after despreading Compute the signal to noise ratio after despreading as S N The absolute value is meaningless because of multiple agcs SREGS53 LSB SREG54 MSB Average noise power Used to compute the SNR after despreading The absolute value is meaningless because of multiple agcs SREGS55 LSB SREG56 2 S N N ratio valid only during code lock Linear not in dBs Fixed point format 14 2 SREG57 LSB SREG58 MSB Bit error rate Monitors the BER number of bit errors on the I channel at the demodulator output counted over 10 000 received bits when the modulator is sending a PRBS 11 test sequence Assume no FEC encoding SREGS9 LSB SREG60 MSB SREG36 5 1 when the BER tester is synchronized with the received PRBS 11 test sequence BER tester synchronized Built in modulator SNR calibration SREG61 LSB SREG62 SREG63 MSB SREG64 LSB SREG65 SREG66 MSB Measured modulated signal Measured AWGN power Noise bandwidth is 6 25 MHz Multi byte status variables are latched upon re rea
6. com MSS 2014 Issued 8 6 2015 Block Diagram Skip 1 2 chips Code replica generation baseband complex samples Digital frequency translation Despreading Coherent I amp D Re sampling Non coherent I amp D Code Carrier NCO Despreading with on time code replica Carrier tracking loop PLL AFC Demodulated PSK symbol 22 bits decoding Code lock Carrier lock Noise power State machine acquisition Frequency error vy Yvy False Code code lock tracking detection loop Monitoring Monitoring Inf Configuration This ComBlock assembly comprising several ComBlock modules can be monitored and controlled centrally over a single connection with a host computer Connection types include built in types e USB e TCP IP LAN The module configuration is stored in non volatile memory Configuration Basic The easiest way to configure the COM 1826 is to use the ComBlock Control Center software supplied with the module on CD In the ComBlock Control Center window detect the ComBlock module s by clicking the VA Detect button next click to highlight the COM 1826 module to be configured next click the ey Settings button to display the Settings window shown below F j COM1826 TDRSS DAS receiver Basic Settings UDP port 1280 TCP port 1028 Static IP address 172
7. for SDDS formatted input stream POWER amp I O The input stream can be received on UDP port 1280 or TCP IP port 1028 Control register REGO 0 selects UDP versus TCP The static IP address is defined in control registers REG37 40 Note It 1s important to ensure that the data source 1s fast enough to send 200 Mbits s of UDP or TCP data with latency less than 2 5ms the receiver input elastic buffer depth When in doubt please check the test point A2 with an oscilloscope The input sampling rate is read from the SDDS preamble The receiver design was verified at an input sampling rate of 6 25 MSamples s but the design should work similarly at other sampling rates The 64 bit receiver time is read from each SDDS frame preamble It is used to time tag the output frames containing the demodulated bits External frequency reference A 10 MHz external frequency reference is required for proper operation The electrical characteristics are as follows Sinewave clipped sinewave or squarewave AC coupled Minimum level 2Vpp Maximum level 5Vpp When the SDDS input stream is transmitted as UDP it is essential that the same 10 MHz be used at both ends of the UDP link otherwise buffer underflow or overflow conditions may occur When the SDDS input stream is transmitted as TCP the 10 MHz frequency stability requirements are not as stringent as the TCP protocol informs the data source of flow control cond
8. reference is selected by default Demodulator can t achieve lock even at high signal to noise ratios e Make sure the modulator baseband I Q signals do not saturate as such saturation would strongly distort the modulation phase information this is a phase demodulator Demodulator can demodulate BPSK but not QPSK e A spectrum inversion may have occurred in the RF transmission chain If so invert the spectrum inversion flag at the demodulator Configuration Management This specification is to be used in conjunction with VHDL software revision 0 and ComBlock control center revision 3 09a and above It is possible to read back the option and version of the FPGA configuration currently active Using the ComBlock Control Center highlight the COM 1826 module then go to the advanced settings The option and version are listed at the bottom of the configuration panel Reference Documents 1 Space Network Interoperable PN Code Libraries 451 PN CODE SNIP ComBlock Ordering Information COM 1826 Access Service Receiver for TDRSS Demand MSS e 18221 A Flower Hill Ways Gaithersburg Maryland 20879 U S A Telephone 240 631 1111 Facsimile 240 631 1676 E mail sales comblock com 14
9. 4DA741 prior to coherent sum The maximum allowed error between REG26 2 transmitted and received chip rate is Encoding 0 NRZ L 100ppm 1 NRZ M 2 NRZ S REG5 LSB REG8 MSB 4 Biphase L The I channel symbol rate can be set REG26 5 3 AGC response Users can to optimize AGC response time time while avoiding instabilities depends 232 fy on external factors such as gain signal filtering at the RF front end and chip Example 00346DC6 represents 100 rate The AGC_DAC gain control signal Ksymbols s is updated as follows 0 every chip REG9 LSB REG12 MSB every 2 input chips Q channel symbol The Q channel symbol rate can be set 2 every 4 input chips rate independently of the spreading code 3 every 8 input chips etc Sac j E period as 10 every 1000 input chips symbol_rate 932 fiks Valid range 0 to 14 REG28 4 0 REG13 LSB REG16 MSB Diale Oy Enable G I channel Approximate i e rounded ratio of chip REG27 1 spreading factor rate symbol rate Viterbi decoder No 0 Yes 1 Processing REG17 LSB G2 parity bit REG27 2 I channel symbol rate independently of the spreading code fsymbol_rate period as ae ee x Ls rutek rst Parameters Configuration Digital Signal 16 bit amplitude scaling factor for the gain modulated signal The maximum level should be adjusted to prevent saturation The settings may vary slightly with the selected symbol rate Therefore we r
10. Com Block COM 1826 RECEIVER FOR TDRSS DEMAND ACCESS SERVICE o Receiver lock Carrier frequency error Key Features SNR ComScope enabled key internal signals 8 can be captured in real time and displayed on host computer e 90VAC 264VAC power supply e TDRSS DAS receiver including o SDDS formatted input stream parsing o BPSK and SQPN spread spectrum demodulation o Viterbi error correction e Programmable 2047 chip periodic I and Q Gold codes e Programmable bit rates from 1 to 150 Kbits s on each channel Two independent bit synchronizers to acquire and track each channel bit stream e 30 bin parallel code search for fast code acquisition False code lock prevention e K 7 Rate 4 Viterbi decoding e Built in Bit Error Rate measurement for PRBS 11 test sequences e Demodulation performances within 1 5 dB from theory at threshold Eb No of 2 dB For the latest data sheet please refer to the ComBlock web site http www comblock com download com1826 pdf e Demodulated bits encapsulated in UDP frames These specifications are subject to change without notice and sent out to the LAN Support for IGMPv2 multicast addressing For an up to date list of ComBlock modules please DO refer to http www comblock com product list html e Monitoring MSS e 845 N Quince Orchard Boulevard Gaithersburg Maryland 20878 U S A Telephone 240 631 1111 Facsimile 240 631 1676 Wwww ComBlock
11. ding SREG7 ComScope Monitoring Key internal signals can be captured in real time and displayed on a host computer using the ComScope feature of the ComBlock Control Center Click on the button to start then select the signal traces and trigger are defined as follows Trace 1 signals Buffer Format Nominal sampling length 8 bit Input signed sampling 2 Demodulated 8 bit 1 sample 512 Q channel signed symbol 3 Parallel correlator 8 bit l output unsigned 4 2 S N N after 8 bit f unsigned despreading Valid only if code is locked Linear i e not in dBs Trace 2 signals Format Nominal sampling 8 bit signed sampling 8 bit 2 signed samples chip spread input signals channel signed symbol 4 Averaged signal fox 5 power valid only signed during code Format Nominal sampling 8 bit 2 samples 512 signed symbol 1 Input signal I channel Buffer length 1 Input signal Q channel 2 Code replica Compare with 12 12 tracking Trace 3 signals 1 Code tracking phase correction accumulated 2 Carrier fine 8 bit fox tracking phase signed 3 I Symbol tracking phase accumulated 4 Averaged noise power valid only 8 bit 1 sample 512 signed symbol 8 bit fak 512 signed during code tracking Trigger Signal 1 Start of code replica 2 Code Lock Signals sampling rates can be changed under software control by adjusting the deci
12. ecommend checking for saturation when changing either the symbol rate or the signal gain REG29 LSB REG30 MSB Additive White 16 bit amplitude scaling factor for Gaussian Noise additive white Gaussian noise gain The new address becomes effective immediately no need to reset the ComBlock inversion o adress Destination IP address for UDP frames with decoded data Example 0x AC 10 01 80 designates address 172 16 1 128 Destination ports I channel data is routed to this user defined port number REG49 LSB REG50 MSB Q channel data is routed to the incremented port number REGS1 MSB REGS4 LSB Gateway IP REGS5 MSB REG58 LSB address Re Writing to the last control register REGS58 is recommended after a configuration change to enact the change Because of the potential for saturation please check for saturation when changing this parameter REG31 LSB REG32 MSB Network Interface MAC addresses In order to ensure the uniqueness of LSB MAC addresses users can define bits 7 1 through REGO 7 1 The MAC addresses upper bits 47 42 and 39 8 are automatically tied to the nearly unique FPGA DNA_ID MAC address bit 0 is either 0 LANI or 1 LAN2 REGO 7 1 IP1 multicast 4 byte IPv4 address used for SDDS address input stream left LAN Example 0x E1 00 00 01 designates somali oe address 225 0 0 1 a ae Use 0 0 0 0 to signify that multicasting is not supported REG33 MSB
13. itions at the data sink In this case the data source is responsible for timing adjustments in the data throughput Spreading codes The demodulator is designed to acquire all Return Mode 2 link codes The Gold code selection is performed by entering two 11 bit initialization vectors for the linear feedback shift registers Appendix A of document 451 PN CODE SNIP lists these initialization vectors as I code and Q code For example NASA code 40 is selected by entering 22250 octal and 13370 in the appropriate control registers 10 Symbol Rate The demodulation symbol rates on the I and Q channels are independent of the chip rate and code period The demodulator includes two autonomous symbol tracking loops separate from the code tracking loop However the full spread spectrum processing gain can only be achieved if the symbol period is less than the 2047 chip code period Frequency Tracking The DSSS demodulator is capable of acquiring signals with a maximum center frequency error of 5 KHz remaining after fixed and dynamic frequency profile table compensation Two features assist the demodulator in extending this natural frequency acquisition range 1 a fixed user defined frequency offset entered through the GUI is applied to the received signal 2 a frequency profile table can be sent to the receiver It consists of a start time followed by 32 bit frequency offset samples read at 1 sec
14. le SRT command or non volatile memory Processing REG19 LSB SRG command All control registers are gain REG20 4 0 MSb read write Nominal input The nominal center frequency is a fixed center frequency frequency offset applied to the SDDS Several key parameters are computed on the basis f input samples It is used for fine of the 125 MHz internal processing clock fax p frequency corrections for example to frequency translation chip rate etc correct clock drifts 32 bit signed integer 2 s complement Parameters Configuration representation expressed as f i a fax SDDS formatted 1 UDP port 0x0500 1280 P stream input 0 TCP port 0x0400 1024 i selection REGO 0 In addition to this fixed value an Linear feedback shift register optional time dependent frequency re ae profile can be entered See frequency As per 1 profile table REG1 LSB REG21 LSB REG24 MSB REG2 2 0 MSb Q Code REG3 LSB Spectrum Invert Q bit OOS Recent meson Oo Chip rate The nominal chip rate is 3 077799479166 on fchip rate Mchips s However the design is somewhat more flexible Alternative chip SON rates can be entered here Q 0 BPSK 1 SQPN 32 bit integer expressed as fchip rate 2 fer p REG26 1 The maximum practical chip rate is fax p QIN 0 dual source independent symbol 2 single double rates on I and Q channels source 1 identical data on I and Q channels Nominal chip rate 0x06
15. mation factor and or selecting the fax processing clock as real time sampling clock In particular selecting the fax processing clock as real time sampling clock allows one to have the same time scale for all signals The ComScope user manual is available at www comblock com download comscope pdf i EJ ComScope COM1518A Direct Sequence Spread Spectrum Demodulator 60 Mchip s So Trace Settings Trace Signal Representation Sampling Clock Decimation Visible Plot style Color Export 2 y 2 w 8 bit Signed Nominal see specs w 1 1 OFF Lines gt 28 36 44 52 60 68 76 84 100 108 116 124 132 140 148 156 164 172 180 188 6196 20 28 36 44 52 60 68 92 100 108 116 124 132 140 148 156 164 172 180 188 196 Plot Settings Trigger Settings Autoscale X Min X Max Y Min Signal Representation Threshold Edge Position T 20 202 137 2 w 8 amp bit Signed 0 w Rising 10 w ComScope example showing code lock with aligned received spread signal green vs code replica red r EJ ComScope COM1518A Direct Sequence Spread Spectrum Demodulator 60 Mchip s x Trace Settings Trace Signal Representation Sampling Clock Decimation Visible Plot style Color Export 2a 3 8 bit Signed Nominal see specs w 1 1 OFF W BigDots amp Lines J m 67 75 83 91 99 107 115 123 131 139 147 155 163 171 179 187 195 203 211 219 227 235 243 251 259 267 275
16. mestamp last timestamp read from the SDDS input frames latched at the first demodulated byte in the transmit frame The output frames are sent when one of two trigger conditions is met at least 1024 demodulated data bytes are waiting in the transmit queue or at least 0 5second has elapsed since the last output frame and at least one demodulated data byte is waiting in the transmit queue The payload data size is thus variable in the range 1 through 1024 bytes Bytes are packed MSb first Only full bytes are transmitted no partially filled bytes Load Software Updates From time to time ComBlock software updates are released To manually update the software highlight the ComBlock and click on the Swiss army knife button ComBlock Control Center File Operations Functions Help The receiver can store multiple personalities The list of personalities stored within the ComBlock Flash memory will be shown upon clicking on the Swiss army knife button ComBlock Control Center efx Fie Operations Functions Help SUF Geese us COM5003 TCP IP USB GATEWA 2 COMB00 Ree wiutkn res Aa Personalities Index Personality Option Default Authorized Boot Protection Address 1 1400 B Yes 2 5003 262144 3 5003 D 524288 4 o000 0 5 o000 6 0 o000 0 0 iy o000 B Add Remove Modify Personality Index Personality Option Password v 5003 B Add ModiFy 172161128 The defaul
17. ond intervals To prevent sudden frequency jumps the table entries are interpolated linearly Once the demodulator has confirmed carrier and code lock the above frequency offsets are frozen Once locked the carrier tracking loops tracks the carrier phase over a very wide frequency range Frequency profile table The table is entered in one TCP session whereby the user TCP client opens a TCP connection to port 1024 and writes the entire frequency table The table consists of a 64 bit start time same reference as the SDDS time tag 1 e 250ps units followed by up to 4096 32 bit frequency samples Each sample represents a nominal center frequency expressed in units of 125 MHz 2 about 29 mHz steps sampled at 1s intervals The byte order is MSB first The frequency table 1s read played back every second starting at the specified SDDS start time The receiver interpolates linearly 64x between successive ls samples so as to minimize discontinuities This ensures phase and frequency continuity This frequency bias is removed from the SDDS input samples for the playback duration irrespective of the demodulator lock status Table playback is mutually exclusive with table upload Opening a new TCP session to upload a new table will immediately stop any playback in progress Because the table is quite small 131 Kbits max the TCP upload time 2 Sms is insignificant relative to the playback duration A utili
18. ration file into flash memory using the ComBlock Control Center UDP Reset Port 1029 is open as a UDP receive only port This port serves a single purpose being able to reset the modem and therefore the TCP IP connection gracefully This feature is intended to remedy a common practical problem it is a common occurrence for one side of a TCP IP connection to end abnormally without the other side knowing that the connection is broken for example when a client crashes In this case new connections cannot be established without first closing the previous ones The problem is particularly acute when the COM 1826 is at a remote location The command 001RST lt CR gt lt LF gt sent as a UDP packet to this port will reset all TCP IP connections within the COM 1826 TCP IP connections can also be cleared remotely from the ComBlock Control Center as illustrated below ComBlock Control Center File Operations Functions Help SR Communication Setup Ctrl S x Detect ComBlocks Ctrl D TCP Reset TCP IP Connection Reset TCP IP Connection Enter the IP address of the ComBlock that you would like to reset i 72 16 1 i 30 Cancel 13 Troubleshooting Checklist Receiver does not communicate with the ComBlock Control Center e Make sure an external 10 MHz frequency reference is present prior to powering up the receiver This applies only when the B firmware option external 10 MHz frequency
19. t personality loaded at power up or after a reboot is identified by a D in the Default column Any unprotected personality can be updated while the Default personality is running Select the personality index and click on the Add Modify button 12 ComBlock Control Center Fil Operations Functions Help COM5S003 TCP IP f USB GATEWA a select FPGA Configuration File Source for x Select Source Download From local File YY The software configuration files are named with the bit extension The bit file can be downloaded via the Internet from the ComBlock CD or any other local file The option and revision for the software currently running within the FPGA are listed at the bottom of the advanced settings window Two firmware options are available for this receiver A firmware uses an internal VCTCXO frequency reference B firmware option requires an external 10 MHz frequency reference Recovery This module is protected against corruption by an invalid FPGA configuration file during firmware upgrade for example or an invalid user configuration To recover from such occurrence connect a jumper in J3 and during power up This prevents the FPGA configuration and restore USB communication LAN communication is restored only if the IP address is known defined for the personality index selected as default Once this is done the user can safely re load a valid FPGA configu
20. ty is included in the ComBlock Control Center to upload a binary frequency profile table a ComBlock Control Cent File Operations Help E send File Recerve File Pattern Generator Ctrl P Data Acquisition Logic Analyzer Ctrl L z COM6001 Front Panel Display Send File Function File to be sent ko ComBlock Alain Desktop doppler_profile bin s Code Tracking Loop The code tracking loop is a coherent delay lock loop DLL of the 1 order Code Acquisition 30 parallel detectors search for code aligment during the code acquisition phase During the subsequent code tracking phase 3 detectors track 11 the early center late code while the other 27 detectors scan for false lock The detectors are staggered 2 chip apart Detection is performed in two steps first a coherent detector averages the despread signal over 2 a symbol period The result is squared and further averaged over 100 symbols The received chip rate must be within 4ppm of the nominal 3 077799479166 Mchips s value Demodulated data output Demodulated data is encapsulated within variable length UDP frames and send to the specified destination P Port The output format is as follows fixed length preamble consisting of in the order of transmission 2 byte length of payload data excluding preamble In the range 1 to 1024 bytes 2 byte frame counter modulo 2 4 byte currently undefined 8 byte ti
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