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ModelSim SE User`s Manual

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1. 12 326 Instance specification bbe hei a B45 2H AG 4k 12 320 SDF specification with the GUI i Oh ve e A gt a e A ae es Se a we 2327 Errorsand WETUIMES sos s g e aw Oe Se ee Bete ee ee tot 12 327 VHDL VITAL SDF we oe hh ee we a i ai 12328 SDF to VHDL generic arching a bee oN ba a eh Go we Se Gace y 12328 Resolving crore e e ac doe Ea ere w k Roe s ow ee a 125329 Verilog SDF ws a a E as a L230 The sdf_annotate yates task koe To Gok a a A e 12330 SDF to Verilog construct matching 12 331 Optional edge specifications gt s lt s so so s eso eroe s soro eav eu e lt 12 333 Optional conditions lt e s s s eoo on e peono oee a a o 12 334 Rounded timing values o a a a aa 12 338 SDF for Mixed VHDL and Verilog Designs a a a a a 12 336 Interconnect delays o soros osor omaa Re a e eee oe e a a ee we eos 12330 Troubleshooting bow a A oaos at e L337 Mistaking a component or t moduler name tone an instance abel io oh ee aoa amp os a a 12 398 Forgetting to specify the instance 2 2 ee ee ee ee 12 338 Obtaming the SDF specification s poa s e wos w moe ee pe we 12 339 ModelSim SE User s Manual Table of Contents 9 13 Value Change Dump VCD Files 13 341 ModelSim VCD commands and VCD tasks Resimulating a VHDL design from a VCD file Specifying a filename and state mappings Creating the VCD fil
2. 2 36 System initialization Oo bs Wie oe BS ae e ee F287 Files accessed during shag a fog oe os a 2637 Environment variables accessed da staty goa ee mk BB Initialization sequence aaa BD This chapter discusses ModelSim projects Projects greatly simplify the process of compiling and simulating a design and are a great tool for getting started with ModelSim This chapter also includes a section on ModelSim initialization ModelSim SE User s Manual Projects and system initialization 2 25 Introduction Introduction What are projects Projects are collection entities for HDL designs under specification or test At a minimum projects have a root directory a work library and metadata which are stored in a mpf file located in a project s root directory The metadata include compiler switch settings compile order and file mappings Projects may also consist of HDL source files or references to source files e other files such as READMEs or other project documentation e local libraries e references to global libraries What are the benefits of projects Projects offer benefits to both new and advanced users Projects e simplify interaction with ModelSim you don t need to understand the intricacies of compiler switches and library mappings eliminate the need to remember a conceptual model of the design the compile order is maintained for you in the project remove the necessity to re esta
3. 2 o o eee 8150 Common window features 8 151 Main window eee 8157 Dataflow window o o 8 171 List window e BTS Process window o o ee 8 190 Signals window o o o 8 193 Source window eee 8201 Structure window eee 8210 Variables window eee 8213 Wave window eee 8216 Compiling with the graphic interface 8 250 Simulating with the graphicinterface 8 256 ModelSimtools 2 eee 8269 Graphic interface commands 8 277 Customizing the interface 2 2 2 wee 8279 The example graphics in this chapter illustrate ModelSim s graphic interface within a Windows environment however ModelSim s interface is designed to provide consistency across all supported platforms Your operating system provides the basic window management frames while ModelSim controls all internal window features such as menus buttons and scroll bars Because ModelSim s graphic interface is based on Tcl Tk you are able to customize your simulation environment Easily accessible preference variables and configuration commands give you control over the use and placement of windows menus menu options and buttons ModelSim SE User s Manual ModelSim Graphic Interface 8 149 Window overview Window overview The ModelSim simulation and debugg
4. ModelSim counter tcounter Compile All Top level modules test counter vlog work work E modelsim55_011801 exam M counter ples counter Model Technology ModelSim SEEE vlog 5 i test_counter 5 Beta 4 Compiler 2001 01 Jan 18 2001 Compiling module counter Top level modules counter vsim work counter vsim work counter Loading work counter 2 32 Projects and system initialization ModelSim SE User s Manual Getting started with projects Step 4 Simulate a design 1 To simulate one of the designs either double click the name or right click the name and select Load A new page appears showing the structure of the current active simulation l ModelSim File Edit acili view Project Run ee Macro Options Window Help Pile Es Model Technology ModelSim SE EE vlog 5 5 Beta 4 Compiler 2001 01 Jan 18 2001 Compiling module counter Top level modules counter vsim work counter vsim work counter Loading work counter quit sim vsim work counter vsim work counter Loading work counter counter counter Function increment VSIM 8 gt Project test Now Ons Delta O sim counter A At this point you are ready to run the simulation and analyze your results You often do this by adding signals to the Wave window and running the simulation for a given period of time See the ModelSim Tutorial for examples O
5. ModelSim SE User s Manual Waveform Comparison 11 313 Graphical Interface to Waveform Comparison Setting Compare Options Selecting Compare gt Options in either the Main or Wave windows provides access to the Add Signal Options dialog box This dialog is divided into two tabs the General Options tab and the Comparison Method tab e General Options EA Add Signal Options Genel Onions AEE Comparison Limit Count Total Limit fi 000 Per Signal Limit fi DO VHDL Matching x Verilog Matching Y Ignore Strength x Z ro mo 71 E x IV Automatically add comparisons to the wave window Reset to Defaut OK Cancel Comparison Limit Count Allows you to limit the waveform comparison to a specific number of total differences and or a specific number of differences per signal VHDL Matching Allows you to designate which VHDL signal values will match the VHDL X and Z values Verilog Matching Allows you to designate which Verilog signal values will match the Verilog X and Z values It also allows you to ignore the strength of the Verilog signal and consider only logic values Save as Default Allows you to save all changes as the new default settings for subsequent waveform comparisons Reset to Default Resets all settings to original default values Automatically add comparisons to the wave window Specifies whether new signal comparison objects are a
6. inserts vall val2 etc just before the index th element of list_name list vall val2 returns a Tcl list consisting of vall val2 etc llength list_name returns the number of elements in list_name Irange list_name first last returns a sublist of list_name from index first to index last first or last may be end which refers to the last element in the list Ireplace list_name first last vall val2 replaces elements first through last with val1 val2 etc Two other commands Isearch and Isort are also available for list manipulation See the Tcl man pages Help gt Tcl Man Pages for more information on these commands See also the ModelSim Tcl command lecho CR 128 ModelSim Tcl commands These additional commands enhance the interface between Tcl and ModelSim Only brief descriptions are provided here for more information and command syntax see the ModelSim Commands CR 9 Command Description alias CR 41 creates anew Tcl procedure that evaluates the specified commands used to create a user defined alias find CR 119 locates incrTcl classes and objects lecho CR 128 takes one or more Tcl lists as arguments and pretty prints them to the Main window Ishift CR 133 takes a Tcl list as argument and shifts it in place one place to the left eliminating the Oth element Isublist CR 134 returns a sublist of the specified Tcl list that
7. saed ee Ob pe Se AS ee a we a lA Customizing menus and pattone ae Pe hb a Rone Be eck ce A Combining signals into a user defined aw bb eee RR eS aR BR eK Ge BEDS Tree window hierarchical view 2 ee eee 8 155 Maim UMW ceo as kk ws ee a we BT WOTKSPACE o es se c e b ee eb ke eee ee ee S Transcript Boba bee oh ee Se ok ee dae Bw Eee we a BADD The Main window menu bar oO 2 org BA ol A ee oe ee ae ee wt ew 8100 The Main window toolbar 2 2 eee 8 166 The Main window status bar o 88 168 Mouse and keyboard shortcuts in the Transcript and Source windows Loe ee ee es 8 168 Dataflow window oe Bie eee eae 6 ate te amp 4S ee BIT Link to active cursor in Wives window G ika Jas A Dataflow window menu bar eR omea e ea a Sm a BETZ Tracing HDL items with the Dataflow podik EE ee Se ee we lT Saving the Dataflow window as a Postscript file 2 2 2 2 8 174 isi wane e e he Bk we OR A ee IE ee Ee ee we 2 3 OD HDL items you Can view o c c soosoo oe so a e a OS The List window menu bar 0 a a a a sem we we ee 8 176 Setting List window display properties oa a a a a a 8178 6 Table of Contents ModelSim SE User s Manual Adding HDL items to the List window Editing and formatting HDL items in the List widow Examining simulation results with the List window Finding items by name in the List window Searching for item va
8. B Note Stand alone tools will pick up project settings in command line mode if they are invoked in the project s root directory Ifinvoked outside the project directory stand alone tools will pick up project settings only if you set the MODELSIM environment variable to the path to the project file lt Project_Root_Dir gt lt Project_Name gt mpf Batch mode In batch mode ModelSim behaves much as in command line mode except that there are no prompts and commands from re directed stdin are not echoed to stdout Do not use the e argument with vsim for batch mode simulations because c invokes the command line mode which supplies the prompts and echoes the commands Tcl user_hook_variables may also be used for Tcl customization during batch mode simulation see http www model com resources pref_variables frameset htm ModelSim SE User s Manual Tips and Techniques E 429 Using macros DO files Using macros DO files ModelSim macros also called DO files are scripts that contain ModelSim and optionally Tcl commands You invoke DO files with the Macro gt Execute Macro Main window menu selection or the do command CR 104 Creating DO files You can create DO files by typing the required commands in any editor and saving the file Alternatively you can save the Main window transcript to a DO file see Saving the Main window transcript file 8 159 The following is a simple DO file that was saved from the
9. The pwd button was added to the Main window with the add button command CR 26 Buttons can be added to the status bar as well e The Mine menu was added to the Signals window with the add_menu command CR 31 The Do My Own Thing menu item was added with the add_menuitem command CR 34 The menu separator was added with the add_separator command CR 35 The ChangeCase and Vars submenus were added with the add_submenu command CR 36 You can also add a menu checkbox like those in this menu tearoff with the add_menucb command CR 33 ModelSim SE User s Manual ModelSim Graphic Interface 8 279 8 280 ModelSim Graphic Interface ModelSim SE User s Manual 9 Performance Analyzer Chapter contents Introducing Performance Analysis 9282 A Statistical Sampling Profiler 2 9 282 Getting Started 9 283 Interpreting the data a 9 283 Viewing Performance Analyzer Results eo oe ao a 95284 Interpreting the Name Field o 9 286 Interpreting the Under and In Fields 2o w o o ea 9 286 Differences in the Ranked and Hierarchical Views 9 287 Ranked Hierarchical Profile Window Features 9 288 Thereportoption gt a eee 9 289 Setting preferences with Tcl variables 9 290 Performance Analyzer commands 9 290 You can use the Performance Analyzer to easily identify
10. tf_longtime_tostr tf_message ModelSim SE User s Manual Verilog Simulation 5 123 Using the Verilog PLI VPI tf_mipname tf_imipname tf_movepvc_flag tf_imovepvc_flag tf_multiply_long tf_nodeinfo tf_inodeinfo tf_nump tf_inump tf_propagatep tf_ipropagatep tf_putlongp tf_iputlongp tf_putp tf_iputp tf_putrealp tf_iputrealp tf_read_restart tf_real_to_long tf_rosynchronize tf_irosynchronize tf_scale_longdelay tf_scale_realdelay tf_setdelay tf_isetdelay tf_setlongdelay tf_isetlongdelay tf_setrealdelay tf_isetrealdelay tf_setworkarea tf_isetworkarea tf_sizep tf_isizep tf_spname tf_ispname tf_strdelputp tf_istrdelputp tf_strgetp tf_istrgetp tf_strgettime tf_strlongdelputp tf_istrlongdelputp tf_strrealdelputp tf_istrrealdelputp tf_subtract_long tf_synchronize tf_isynchronize tf_testpve_flag tf_itestpvc_flag tf_text tf_typep tf_itypep tf_unscale_longdelay tf_unscale_realdelay tf_warning tf_write_save 5 124 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI Verilog XL compatible routines The following PLI routines are not defined in IEEE Std 1364 but ModelSim Verilog provides them for compatibility with Verilog XL char acc_decompile_exp handle condition This routine provides similar functionality to the Veri
11. 1200 1 Sdumpall 1 qa 1 o 0 08 Qr 0 0 0 0 0 13 348 Value Change Dump VCD Files ModelSim SE User s Manual Capturing port driver data Capturing port driver data Some ASIC vendor s toolkits read a VCD file format that provides details on port drivers This information can be used for example to drive a tester See the ASIC vendor s documentation for toolkit specific information In ModelSim use the ved dumpports command CR 201 to create a VCD file that captures port driver data Port driver direction information is captured as TSSI states in the VCD file Each time an external or internal port driver changes values a new value change is recorded in the VCD file with the following format p lt TSSI state gt lt 0 strength gt lt 1 strength gt lt identifier_code gt Supported TSSI states The supported lt TSSI states gt are Input testfixture Output dut D low L low U high H high N unknown X unknown Z tri state T tri state Unknown direction low both input and output are driving low high both input and output are driving high unknown both input and output are driving unknown tri state unknown input driving low and output driving high unknown input driving low and output driving unknown unknown input driving unknown and output driving low unknown input driving high
12. M Simulation Options The WLF Files page includes these options e WLF File Size Limit Limits the WLF file by size as closely as possible to the specified number of megabytes If both size and time limits are specified the most restrictive is used Setting it to 0 results in no limit Edit the WLFSizeLimit B 401 variable in the modelsim ini file to set a permanent default WLF File Time Limit Limits the WLF file by size as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used Setting it to O results in no limit Edit the WLFTimeLimit B 401 variable in the modelsim ini file to set a permanent default ModelSim SE User s Manual ModelSim Graphic Interface 8 267 Simulating with the graphic interface e Compress WLF data Compresses WLF files to reduce their size You would typically only disable compression for troubleshooting purposes Edit the WLFCompress B 401 variable in the modelsim ini file to set a permanent default Delete WLF file on exit Specifies whether the WLF file should be deleted when the simulation ends Edit the WLFDeleteOnQuit B 401 variable in the modelsim ini file to set a permanent default e Design Hierarchy Specifies whether to save all design hierarchy in the WLF file or only regions containing logged signals Edit the WLESaveAllRegions B 401 variable in the modelsim ini file to set a permanent default 8 268 Mo
13. e Orientation Select the output page orientation Portrait or Landscape ModelSim SE User s Manual ModelSim Graphic Interface 8 249 Compiling with the graphic interface Compiling with the graphic interface You can use a project or the Compile HDL Source Files dialog box to compile VHDL or Verilog designs For information on compiling in a project see Getting started with projects 2 28 To open the Compile HDL Source Files dialog select the Compile button Main window or Design gt Compile ModelSim Reading E modelsim55_se win32 tcl vsim pi ModelSim gt wm title ModelSim SE EE The Compile HDL Source Files dialog box opens as shown below Compile HDL Source Files pr EC e E 71x a set vhd top vhd HDL Files whdl whd w v __Defauit Options Edt Source 8 250 ModelSim Graphic Interface ModelSim SE User s Manual Compiling with the graphic interface From the Compile HDL Source Files dialog box you can e select source files to compile in any language combination e specify the target library for the compiled design units e select among the compiler options for either VHDL or Verilog Select the Default Options button to change the compiler options see Setting default compile options 8 252 for details The same Compiler Options dialog box can also be accessed by selecting Options gt Compile Main window or by selecting Compil
14. ke mese ss e a e a 166377 System commands s e s sc s soc s ee ee e a 160377 List DIOCESE s s e es a a A 10 378 ModelSim Tcl commands 16 378 ModelSim Tcl time commands o 16 379 Conversions lt a e E A ee RA a 10 319 Relations o 16 379 ACUIMEHS s s esbirros Ge 2 10 380 TELELAIP ES o o os o Oe ee ee ee e ee ee 16 381 EMPR 6 be a ede ee ir A A A e 10 382 A Technical Support Updates and Licensing A 385 Technical support electronic ee o e A 386 Mentor Graphics customers 2 o A 386 Technical support telephone O o Mentor Graphics customers in North America ck a do e AO Mentor Graphics customers outside North America 2 A 387 Technical support other channels 2 2 2 ee ee A 387 Updates o 2 ecc mos a a ee a eee a AB Online References s c A ee acabla k or a a A 388 FLEX Im Licenses cols e moa we ee we E AE A 390 B ModelSim Variables B 391 Variable settings report e t soe de a aa al e aa al a al 4 eo B 392 Personal preferentes o lt s e s soe s w osoro a a e a B392 Returning to the original ModelSim defaults u a a aaa a B 392 Environment variables Bae a ee a e B 399 Setting environment millas in Val ee see OO ee aren te we B 394 Referencing environment variables within ModelSim Ly A a A y BOS Removing temp files YSQUT ooo o oea sx ee B 395 Preference variables located
15. moves the active marker in the List window up to the next transition on the selected signal that matches the specifications write preferences CR 280 saves the current GUI preference settings to a Tcl preference file ModelSim SE User s Manual ModelSim Graphic Interface 8 277 Graphic interface commands Window menu and button commands Description add button CR 26 adds a user defined button to the Main window button bar add_menu CR 31 adds a menu to the menu bar of the specified window add_menucb CR 33 creates a checkbox within the specified menu of the specified window add_menuitem CR 34 creates a menu item within the specified menu of the specified window add_separator CR 35 adds a separator as the next item in the specified menu path in the specified window add_submenu CR 36 creates a cascading submenu within the specified menu_path of the specified window change_menu_cmd CR 53 changes the command to be executed for a specified menu item label in the specified menu in the specified window disable_menu CR 102 disables the specified menu within the specified window useful if you want to restrict access to a group of ModelSim features disable_menuitem CR 103 disables a specified menu item within the specified menu_path of the specified window useful if you want to restrict access to a specific ModelSim feature enable_
16. Loading project Modifying E modelsim55_se win32 workspace E lt No Design Loaded gt lt No Context gt 4 The name of the current project is shown at the bottom left corner of the Main window 2 30 Projects and system initialization ModelSim SE User s Manual Getting started with projects Step 2 Add files to the project Y our right mouse button 2nd button in Windows 3rd button in UNIX gives quick access to project commands When you right click in the workspace a context menu appears The menu that appears depends on where you click in the workspace 1 ModelSim file to Project Right click in a blank area on the Project page and select Add file to Project This opens the Add file to Project dialog You can also select Project gt Add file to Project from the menu bar Add file to Project Specify one or more files you want to add to the project The files used in this example are available in the examples directory that is installed along with ModelSim For the files you re adding choose whether to reference them from their current location or copy them into the project directory ModelSim SE User s Manual Projects and system initialization 2 31 Getting started with projects Step 3 Compile the files 1 To compile the files right click in the Project page and select Compile All You can also select Project gt Compile All from the menu bar
17. S severity level T R report message Iteration T time of assertion D In D delta l instance or region pathname if available print character BreakOnAssertion 0 4 defines severity of assertion that causes a 3 simulation break 0 note 1 warning 2 error 3 failure 4 fatal CheckpointCompressMode 0 1 1f 1 checkpoint files are written in on 1 compressed format CommandHistory any valid sets the name of a file in which to store the commented filename Main window command history out B 398 ModelSim Variables ModelSim SE User s Manual Preference variables located in INI files Variable name Value range Purpose Default ConcurrentFileLimit any positive controls the number of VHDL files open 40 integer concurrently this number should be less than the current limit setting for max file descriptors 0 unlimited DatasetSeparator any single the dataset separator for fully rooted character contexts for example sim top must not be the same character as PathSeparator DefaultForceKind freeze drive or defines the kind of force used when not drive for deposit otherwise specified resolved signals freeze for unresolved signals DefaultRadix symbolic binary any radix may be specified as a number or symbolic octal decimal name i e binary can be specified as binary unsigned or 2 hexadecimal ascii DefaultRestartOptions one or more of s
18. These zoom buttons are available on the toolbar Zoom in 2x Zoom area zoom in by a factor of two use the cursor to outline a from the current view zoom area Zoom out 2x Zoom Full zoom out by a factor of zoom out to view the full two from current view range of the simulation from time 0 to the current time Zooming with the mouse To zoom with the mouse position the mouse cursor to the left side of the desired zoom interval press the middle mouse button three button mouse or lt Ctrl gt left mouse button two button mouse and while continuing to press drag to the right and then release at the right side of the desired zoom interval Zooming keyboard shortcuts See Wave window mouse and keyboard shortcuts 8 244 for a complete list of Wave window keyboard shortcuts Saving zoom range and scroll position with bookmarks Bookmarks allow you to save a particular zoom range and scroll position This lets you return easily to a specific view later You save the bookmark with a name and then access the named bookmark from the Bookmark menu Bookmarks are saved in the Wave format file see Adding items with a Wave window format file 8 219 and are restored when the format file is read There is no limit to the number of bookmarks you can save Bookmarks can also be created and managed from the command line See bookmark add wave command CR 44 for details ModelSim SE User s Manual ModelSim Graphic Interf
19. You can combine signals in the Wave window into busses A bus is a collection of signals concatenated in a specific order to create a new virtual signal with a specific value To create a bus select one or more signals in the Wave window and then choose Edit gt Combine ER Combine Selected Signals Name Bus Combine Into Order of Indexes Bus C Ascending C Group Descending J Remove selected signals after combining OK Cancel The Combine Selected Signals dialog box includes these options Combine Into Only the Bus option is valid at this time Groups are not currently implemented Order of Indexes Specifies in which order the selected signals are indexed in the bus If set to Ascending the first signal selected in the Wave window will be assigned an index of 0 If set to Descending the first signal selected will be assigned the highest index number Remove selected signals after combining Specifies whether you want to remove the selected signals from the Wave window once the bus is created In the illustration below three signals have been combined to form a new bus called BUS1 Note that the component signals are listed in the order in which they were selected in the Wave window Also note that the bus value is made up of the values of its component signals arranged in a specific order Virtual objects are indicated by an orange diamond ModelSim SE User s Manual ModelSim Graphic Interf
20. at 4913000 ns Primary Channel H AXDA Mark at 4913800 ns Primary Channel AXDA Mark at 4914400 ns Primary Channel AXDA Mark at 4914800 ns Primary Channel H AXDA Mark at 4915400 ns Primary Channel Now 6 088 600 ns Delta 1 Profile Samples 1247 ingbuffring Getting Started Performance analysis occurs during the ModelSim run command and is displayed graphically as a profile of simulator performance To enable the Performance Analyzer use the profile on command at the VSIM prompt After this command is executed all subsequent run commands will have profiling statistics gathered for them With the Performance Analyzer enabled and a run command initiated the simulator will provide a message indicating that profiling has started The Performance Analyzer is turned off by issuing the profile off command at the VSIM prompt Any ModelSim run commands that follow will not be profiled Profiling results are cumulative Therefore each run command performed with profiling ON will add new information to the data being gathered To clear this data issue the profile clear command at the VSIM prompt Interpreting the data The Performance Analyzer is most helpful in those situations where a high percentage of simulation time is being spent in a particular module For example say the Performance Analyzer shows that the simulation is spending 60 of its time in module X This information can be used to find where module X wa
21. lt control x gt lt control s gt lt control s gt save lt control y gt F18 lt control v gt paste the selection none lt control a gt select the entire contents of the widget lt control 1 gt clear any selection in the widget lt control _ gt lt control gt lt control Z gt undoes previous edits in the Source window lt meta lt gt none move cursor to the beginning of the file lt meta gt gt none move cursor to the end of the file lt meta v gt PageUp move cursor up one screen lt Meta w gt lt control c gt copy selection lt F8 gt search for the most recent command that matches the characters typed Main window only The Main window allows insertions or pastes only after the prompt therefore you don t need to set the cursor when copying strings to the command line 8 170 ModelSim Graphic Interface ModelSim SE User s Manual Dataflow window Dataflow window The Dataflow window allows you to trace VHDL signals or Verilog nets and registers through your design Double click an item with the left mouse button to move it to the center of the Dataflow display VHDL signals or processes in the Dataflow window e A signal is displayed in the center of the window with all the processes that drive the signal on the left and all the processes that read the signal on the right e A process is displayed with all the signals read by the p
22. vlib work vlog hello v ole Simulate the design vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 gt run all Hello world VSIM 2 gt quit gt Note A general VPI example can be found in lt install_dir gt modeltech examples vpi The PLI callback reason argument The second argument to a PLI callback function is the reason argument The values of the various reason constants are defined in the veriuser h include file See IEEE Std 1364 for a description of the reason constants The following details relate to ModelSim Verilog and may not be obvious in the IEEE Std 1364 Specifically the simulator passes the reason values to the misctf callback functions under the following circumstances reason_endofcompile For the completion of loading the design reason_finish For the execution of the finish system task or the quit command reason_startofsave For the start of execution of the checkpoint command but before any of the simulation state has been saved This allows the PLI application to prepare for the save but it shouldn t save its data with calls to tf_write_save until it is called with reason_save reason_save For the execution of the checkpoint command This is when the PLI application must save its state with calls to tf_write_save ModelSim SE User s Manual Verilog Simulation 5 117 reason_startofrestart For the start of execution of the restore command but before
23. work in all entry boxes Cut Copy Paste Delete into any entry box by clicking the right mouse button in the entry box Standard cut copy paste shortcut keystrokes X C V will Structure Signals Variables and Wave windows Cut Copy Paste Delete When the focus changes to an entry box the contents of that box are selected highlighted This allows you to replace the current Select All contents of the entry box with new contents with a simple paste command without having to delete the old value of the screen Dialog boxes will appear on top of their parent window instead of the upper left corner ModelSim SE User s Manual ModelSim Graphic Interface 8 151 Common window features e The Main window includes context menus that are accessed by ae Lopy clicking the right mouse button qee e The middle mouse button will allow you to paste the following into the transcript window Select All Unselect All text currently selected in the transcript window Find a current primary X Windows selection can be from another A application or Breakpoint s Transcript window contents of the clipboard context menu Note Selecting text in the transcript window makes it the current primary X Windows selection This way you can copy transcript window selections to other X Windows windows xterm emacs etc e The Edit gt Paste operation in the transcript wi
24. 4 59 Using the TextlO package 2 we 4 60 Syntax for file declaration o 4 60 Using STD_INPUT and STD OUTPUT within ModelSim o 461 TextlO implementationissues 4 62 Writing strings and aggregates kogo a w wog A02 Reading and writing hexadecimal n mibers aaa 463 Dangling pointers a aaa 463 The ENDLINE function 2 2 eee 463 The ENDFILE function Be a GA ee oe Sn et 463 Using alternative input output files bow be ow wb A Providing stimulus 4 64 Obtaining the VITAL specification and source code 4 65 VITAL packages 2 ee 465 ModelSim VITAL compliance 4 66 VITAL compliance checking 4 66 VITAL compliance warnings 4 66 Compiling and Simulating with accelerated VITAL packages 4 67 Unlpackase mo ao w m ooo e ee o SO we 4568 get_resolutionD eee 468 init_signal spy 469 toreal 2 2 ee 470 to_time o 4 TI This chapter provides an overview of compilation and simulation for VHDL designs within the ModelSim environment using the TextlO package with ModelSim ModelSim s implementation of the VITAL VHDL Initiative Towards ASIC Libraries specification for ASIC modeling and documentation on ModelSim s special built in utilities package The TextlO package is defined within the VHDL Language Reference Manuals IEEE S
25. ModelSim SE User s Manual Projects and system initialization 2 35 Accessing projects from the command line Accessing projects from the command line Generally projects are used only within the ModelSim graphical user interface However standalone tools will use the project file if they are invoked in the project s root directory If invoked outside the project directory the MODELSIM environment variable can be set with the path to the project file lt Project_Root_Dir gt lt Project_Name gt mpf You can also use the project command CR 159 from the command line to perform common operations on new projects The command is to be used outside of a simulation session 2 36 Projects and system initialization ModelSim SE User s Manual System initialization System initialization ModelSim goes through numerous steps as it initializes the system during startup It accesses various files and environment variables to determine library mappings configure the GUI check licensing and so forth Files accessed during startup The table below describes the files that are read during startup They are listed in the order in which they are accessed File Purpose modelsim ini contains initial tool settings see Preference variables located in INI files B 396 for specific details on the modelsim ini file location map file used by ModelSim tools to find source files based on easily reallocated soft paths defau
26. Using the FLEXIm License Manager D 417 Starting the license server daemon D 418 Controlling the license file search on n a a a eee D 418 Manual start a D 4118 Automatic start at boot time E DALO What to do if another application uses FLEXIm oh a a Se God Soe amp DA O Format of the license file s s s sw dw ao m doe ne e dor et s e DA20 Format of the daemon options file a aa ee D 420 License administration tools ee eee ee ew D 422 LION lt lt ds a AE ee E A a DEAD Imremove o D 423 Imreread a wd oe e ad EY ewe ck howe 446 4 DA Administration tools fist Windows Bote ch oh he atte dh chores i ho se e DAS E Tips and Techniques E 425 How to use checkpoint restore a a as E420 The difference between chuches me plas so dem A a amp BRAT Using macros with restart and checkpoint restore 2 2 2 E427 Running command line and batch mode simulations 2 2 2 2 2 2 E 428 Commandslint mode lt gt lt s sor a s oa m eee Ree o E428 Batch mode oe eo asa ALO Using macros DO files 0 a ee ee ee E 430 Using Parameters with DO files 2 2 e moe a E 430 Source code security and nodebug E 433 Saving and viewing waveforms 2 ee ee eee E 434 Setting p libraries for group s gt s s so e oee moma epo s 5 4 o 0 0 16 434
27. dest_object Required A full hierarchical path or relative path with reference to the calling block to a Verilog register or VHDL signal Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose integer Optional Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the spy_object s value is mirrored onto the dest_object Default is 0 no message Limitations e When mirroring the value of a VHDL signal onto a Verilog register the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Mirroring slices or single bits of a vector is not supported If you do reference a slice or bit of a vector the function will assume that you are referencing the entire vector 5 104 Verilog Simulation ModelSim SE User s Manual System Tasks Example module reg top_sigl initial begin Sinit_signal_spy top uut instl sigl top_sigl 1 end endmodule In this example the value of top uut inst1 sig1 will be mirrored onto top_sigl ModelSim SE User s Manual Verilog Simulation 5 105 Compiler Directives Compiler Directives ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364 and some additional Verilog XL compiler directives for compatibility Many of the compiler d
28. dist_erlang itor q_exam nochange dist_exponential realtobits q_full period dist_normal rtoi q_initialize recovery dist_poisson signed q_remove setup dist_t unsigned setuphold dist_uniform skew random width removal recrem ModelSim SE User s Manual Verilog Simulation 5 99 System Tasks Display tasks display displayb displayh displayo monitor monitorb monitorh monitoro monitoroff monitoron strobe strobeb strobeh strobeo write writeb writeh writeo PLA modeling tasks async and array async nand array async or array async nor array async and plane async nand plane async or plane async nor plane sync and array sync nand array sync or array sync nor array sync and plane sync nand plane sync or plane sync nor plane Value change dump VCD file tasks dumpall dumpfile dumpflush dumplimit dumpoff dumpon dumpvars dumpportson dumpportsoff dumpportsall dumpportsflush dumpports dumpportslimit 5 100 Verilog Simulation ModelSim SE User s Manual System Tasks File 1 O tasks fclose fdisplay fdisplayb fdisplayh fdisplayo ferror fflush fgetc fgets fmonitor fmonitorb fmonitorh fmonitoro fopen fread fscanf fseek fstrobe fstrobeb fstrobeh fstrobeo ftell fwrite fwriteb fwriteh fwriteo readmemb readmemh rewind sdf_annotate sformat sscanf swrite
29. s Manual VHDL Simulation 4 57 Simulating VHDL designs Simulating VHDL designs After compiling the design units you can simulate your designs with vsim CR 258 This section discusses simulation from the UNIX or Windows DOS command line You can also use a project to simulate see Getting started with projects 2 28 or the Load Design dialog box see Simulating with the graphic interface 8 256 B Note Simulation normally stops if a failure occurs however if a bounds check on a signal fails the simulator will continue running Invoking the simulator from the Main window For VHDL invoke vsim CR 258 with the name of the configuration or entity architecture pair Note that if you specify a configuration you may not specify an architecture This example invokes vsim CR 258 on the entity my_asic and the architecture structure vsim my_asic structure If a design unit name is not specified vsim CR 258 will present the Load Design dialog box from which you can choose a configuration or entity architecture pair See Simulating with the graphic interface 8 256 for more information Selecting the time resolution The simulation time resolution is 1 ns by default You can select a specific time resolution with the vsim CR 258 t option or from the Load Design dialog box Available resolutions are 1x 10x or 100x of fs ps ns us ms or sec For example to run in picosecond resolution or 10ps resolution r
30. use mgc_location_map if it exists else use HOME mgc mgc_location_map else use HOME mgc_location_map else use MGC_HOME etc mgc_location_map else use MGC_HOMEJ shared etc mgc_location_map else use MODEL_TECH mgc_location_map else use MODEL_TECH mgc_location_map else use no map Reads various variables from the vsim section of the modelsim ini file See vsim simulator control variables B 398 for more details ModelSim SE User s Manual Projects and system initialization 2 39 System initialization 5 Parses any command line arguments that were included when you started ModelSim and reports any problems 6 Defines the following environment variables e use MODEL_TECH_TCL if it exists else set MODEL_TECH_TCL MODEL_TECH tcl set TCL_LIBRARY MODEL_TECH_TCL Atcl8 0 set TK_LIBRARY MODEL_TECH_TCL k8 0 set TIX_LIBRARY MODEL_TECH_TCL tix4 1 set ITCL_LIBRARY MODEL_TECH_TCLYitcl3 0 set ITK_LIBRARY MODEL_TECH_TCL itk3 0 set VSIM_LIBRARY MODEL_TECH_TCL Asim 7 Initializes the simulator s Tcl interpreter 8 Checks for a valid license a license is not checked out unless specified by a modelsim ini setting or command line option The next four steps relate to initializing the graphical user interface 9 Sets Tcl variable MTI_LIB_DIR MODEL_TECH_TCL 10 Loads MTI_LIB_DIR pref tcl 11 Loads last working directory project init project history and printer defaults fro
31. variable substitution 16 377 VSIM Tcl commands 16 378 Technical support A 385 test region 11 311 test signals 11 302 Text and command syntax 1 20 Text editing see Editing TextlO package 4 55 alternative I O files 4 64 containing hexadecimal numbers 4 63 dangling pointers 4 63 ENDFILE function 4 63 ENDLINE function 4 63 file declaration 4 60 implementation issues 4 62 providing stimulus 4 64 standard input 4 61 standard output 4 61 WRITE procedure 4 62 WRITE_STRING procedure 4 62 Time handling negative timing constraints 5 102 setting the resolution 4 58 5 84 8 258 time resolution as a simulator state variable B 408 time type converting to real 4 70 timing differences 11 302 11 317 TMPDIR environment variable B 394 to_real VHDL function 4 70 to_time VHDL function 4 71 tolerance leading edge 11 310 11 313 trailing edge 11 310 11 313 tolerances 11 303 Toolbar Main window 8 166 Wave window 8 224 Tracing HDL items with the Dataflow window 8 173 Transcript file saving 8 159 TranscriptFile variable in ini file B 400 Tree windows VHDL and Verilog items in 8 155 viewing the design hierarchy 8 155 Triggers setting in the List window 8 179 E 444 TSSI in VCD files 13 349 type converting real to time 4 71 converting time to real 4 70 ModelSim SE User s Manual Index 476 U nbound Component 8 253 nbufferedOutput ini file variable B 401 pCase ini file variable B 398 pdates A 385 se 1076 1993 language stan
32. CR 148 command Actions recorded by the Macro Helper can only take place within the ModelSim GUI window sizing and repositioning are not recorded because they are handled by your operating system s window manager In addition the run CR 176 commands cannot be recorded with the Macro Helper but can be invoked as part of a complex macro Select Macro gt Macro Helper Main window to access the Macro Helper Record a macro by typing a new macro file name into the field provided then press Record Use the Pause and Stop buttons as shown in the table below Play a macro by entering the file name of a Macro Helper file into the field and pressing Play Files created by the Macro Helper can be viewed with the notepad CR 141 Button Description Record Stop Record begins recording and toggles to Stop once a recording begins Insert Pause inserts a 5 second pause into the macro file press the button more than once to add more pause time the pause time can subsequently be edited in the macro file plays the Macro Helper file specified in the file name field See the macro_option command CR 135 for playback speed delay and debugging options for completed macro files 8 270 ModelSim Graphic Interface ModelSim SE User s Manual ModelSim tools The Tcl Debugger We would like to thank Gregor Schmid for making TDebug available for use in the public domain This program is distribute
33. CR 249 See Design libraries 3 41 for additional information on working with libraries Invoking the VHDL compiler ModelSim compiles one or more VHDL design units with a single invocation of vcom CR 217 the VHDL compiler The design units are compiled in the order that they appear on the command line For VHDL the order of compilation is important you must compile any entities or configurations before an architecture that references them You can simulate a design containing units written with both the 1076 1987 and 1076 1993 versions of VHDL To do so you will need to compile units from each VHDL version separately The vcom CR 217 command compiles units written with version 1076 1987 by default use the 93 option with vcom CR 217 to compile units written with version 1076 1993 You can also change the default by modifying the modelsim ini file see Preference variables located in INI files B 396 for more information Dependency checking Dependent design units must be reanalyzed when the design units they depend on are changed in the library vcom CR 217 determines whether or not the compilation results have changed For example if you keep an entity and its architectures in the same source file and you modify only an architecture and recompile the source file the entity compilation results will remain unchanged and you will not have to recompile design units that depend on the entity ModelSim SE User
34. Displays VHDL constants generics variables and Verilog register variables in the current process and their current values Wave window 8 216 Displays waveforms and current values for the VHDL signals and variables and Verilog nets and register variables you have selected Current and past simulations can be compared side by side in one Wave window 8 150 ModelSim Graphic Interface ModelSim SE User s Manual Common window features Common window features ModelSim s graphic interface provides many features that add to its usability features common to many of the windows are described below Feature Feature applies to these windows Quick access toolbars 8 152 Main Source and Wave windows Drag and Drop 8 152 Dataflow List Signals Source Structure Variables and Wave windows Command history 8 152 Main window command line Automatic window updating 8 153 Dataflow Process Signals and Structure windows Finding names searching for values and locating cursors 8 153 various windows Sorting HDL items 8 154 Process Signals Source Structure Variables and Wave windows Multiple window copies 8 154 all windows except the Main window Menu tear off 8 154 all windows Customizing menus and buttons 8 154 all windows Combining signals into a user defined bus 8 154 List and Wave windows Tree window hierarchical view 8 155
35. If vsim CR 258 is invoked with the do lt command_string gt option a DO file macro is called A DO file executed in this manner will override any startup command in the modelsim ini file E 428 Tips and Techniques ModelSim SE User s Manual Running command line and batch mode simulations During simulation a transcript file is created containing any messages to stdout A transcript file created in command line mode may be used as a DO file if you invoke the transcript on command CR 194 after the design loads see the example below The transcript on command will write all of the commands you invoke to the transcript file For example the following series of commands will result in a transcript file that can be used for command input if top is resimulated remove the quit f command from the transcript file if you want to remain in the simulator vsim c top library and design loading messages then execute transcript on force clk 1 50 0 100 repeat 100 run 500 run 5000 quit f gt Note Rename transcript files that you intend to use as DO files They will be overwritten the next time you run vsim if you don t rename them Also simulator messages are already commented out but any messages generated from your design and subsequently written to the transcript file will cause the simulator to pause A transcript file that contains only valid simulator commands will work fine comment out anything else with a
36. L2 new string Ll all Copy contents WRITELINE outfile L1 Deallocate buffer The ENDLINE function The ENDLINE function described in the JEEE Standard VHDL Language Reference Manual IEEE Std 1076 1987 contains invalid VHDL syntax and cannot be implemented in VHDL This is because access types must be passed as variables but functions only allow constant parameters Based on an ISAC VASG recommendation the ENDLINE function has been removed from the TextIO package The following test may be substituted for this function L NULL OR L LENGTH 0 The ENDFILE function In the VHDL Language Reference Manuals IEEE Std 1076 1987 and IEEE Std 1076 1993 the ENDFILE function is listed as function ENDFILE L in TEXT return BOOLEAN As you can see this function is commented out of the standard TextIO package This is because the ENDFILE function is implicitly declared so it can be used with files of any type not just files of type TEXT ModelSim SE User s Manual VHDL Simulation 4 63 TextlO implementation issues Using alternative input output files You can use the TextIO package to read and write to your own files To do this just declare an input or output file of type TEXT The VHDL 87 declaration is file myinput TEXT is in pathname dat The VHDL 93 declaration is file myinput TEXT open read_mode iS pathname dat Then include the identifier for this file myinput in
37. ModelSim SE User s Manual ModelSim Shortcuts C 413 Keystrokes UNIX Keystrokes Windows Result lt alt gt lt F4 gt close active window lt control a gt lt home gt lt home gt move cursor to the beginning of the line lt control b gt move cursor left lt control d gt delete character to the right lt control e gt lt end gt lt end gt move cursor to the end of the line lt control f gt move cursor right one character lt control k gt delete to the end of line lt control n gt move cursor one line down Source window only under Windows lt control o gt none insert a newline character in front of the cursor lt control p gt move cursor one line up Source window only under Windows lt control s gt lt control f gt find lt F3 gt find next lt control t gt reverse the order of the two characters to the right of the cursor lt control u gt delete line lt control v gt PageDn move cursor down one screen lt control w gt lt control x gt cut the selection lt control x gt lt control s gt lt control s gt save lt control y gt F18 lt control v gt paste the selection none lt control a gt select the entire contents of the widget lt control gt
38. Once you have generated a component declaration for a Verilog module you can instantiate the component just like any other VHDL component In addition you can reference a Verilog module in the entity aspect of a component configuration all you need to do is specify a module name instead of an entity name You can also specify an optional architecture name but it will be ignored because Verilog modules do not have architectures Verilog instantiation criteria A Verilog design unit may be instantiated from VHDL if it meets the following criteria e The design unit is a module UDPs are not allowed e The ports are named ports Verilog allows unnamed ports e The ports are not connected to bidirectional pass switches it is not possible to handle pass switches in VHDL Component declaration A Verilog module that is compiled into a library can be referenced from a VHDL design as though the module is a VHDL entity The interface to the module can be extracted from the library in the form of a component declaration by running vgencomp CR 224 Given a library and module name vgencomp CR 224 writes a component declaration to standard output The default component port types are e std_logic e std_logic_vector Optionally you can choose bit and bit_vector e yl logic and vl_logic_vector VHDL and Verilog identifiers The identifiers for the component name port names and generic names are the same as the Verilog identifie
39. Setting List window display properties 8 178 Once display properties have been set you can add items to the windows or logfile in several ways Adding items with the Signals window View menu Use the View menu with either the Wave List or Log selection to add HDL l View Pel Ed items to the Wave window 8 216 List Wave gt window 8 175 or a logfile respectively List ll ee EE The logfile is written as an archive file in Log gt Selected Signals binary format and is used to drive the List and Wave windows at a later time Once signals are added to the logfile they cannot be removed If you begin a simulation by invoking vsim CR 258 with the view lt logfile_name gt option ModelSim reads the logfile to drive the Wave and List windows Signals in Region Signals in Design Filter Choose one of the following options ModelSim opens the target window for you e Selected Signal Lists only the item s selected in the Signals window e Signals in Region Lists all items in the region that is selected in the Structure window e Signals in Design Lists all items in the design Adding items from the Main window command line Another way to add items to the Wave or List window or the logfile is to enter the one of the following commands at the VSIM prompt choose either the add list CR 28 add wave CR 37 or log CR 131 command add list add wave log lt item_name gt lt item_name gt
40. The Imewin disable command disables continuous monitoring of a window The window signal is not deleted but it no longer is updated when the model s window register changes value For example to disable continuous monitoring of window wa lmcwin disable top ul wa Imcwin release Some windows are actually nets and the Imcwin write command behaves more like a continuous force on the net The Imcwin release command disables the effect of a previous Imcwin write command on a window net A memory model usually makes the entire register array available as a window In this case the window commands operate only on a single element at a time The element is selected as an array reference in the window instance specification For example to read element 5 from the window memory mem lmcwin read top u2 mem 5 Omitting the element specification defaults to element 0 Also continuous monitoring is limited to a single array element The associated window signal is updated with the most recently enabled element for continuous monitoring 14 360 Logic Modeling SmartModels ModelSim SE User s Manual Verilog SmartModel interface Verilog SmartModel interface The SWIFT SmartModel library beginning with release r40b provides an optional library of Verilog modules and a PLI application that communicates between a simulator s PLI and the SWIFT simulator interface The Logic Modeling documentation refers to this as the Logic Models to
41. Using Tcl with ModelSim gives you these features e command history like that in C shells full expression evaluation and support for all C language operators a full range of math and trig functions support of lists and arrays regular expression pattern matching procedures the ability to define your own commands e command substitution that is commands may be nested Note ModelSim PE does not support Tk You must be using ModelSim SE to customize the interface Tcl References Tcl printed references Two sources of information about Tcl are Tcl and the Tk Toolkit by John K Ousterhout published by Addison Wesley Publishing Company Inc and Practical Programming in Tcl and Tk by Brent Welch published by Prentice Hall Tcl online references Tcl tutorial The following are a few of the many Tcl references available Select Help gt Tcl Man Pages Main window Tcl man pages are also available at http dev scriptics com man tcl8 1 Tcl Tk general information is available from the Tcl Tk Consortium www tclconsortium org The Scriptics Corporation John Ousterhout s company the original Tcl developer www scriptics com For some hands on experience using Tcl with ModelSim see the Tcl Tk and ModelSim lesson in the ModelSim SE Tutorial 16 370 Tcl and ModelSim ModelSim SE User s Manual Tcl commands Tcl commands The Tcl commands are listed below For complete information on Tcl c
42. X will work okay 16 376 Tel and ModelSim ModelSim SE User s Manual Tcl commands e For the equal operator you must use the C operator For not equal you must use the C operator Variable substitution When a lt var_name gt is encountered the Tcl parser will look for variables that have been defined either by ModelSim or by you and substitute the value of the variable B Note Tcl is case sensitive for variable names To access environment variables use the construct Senv lt var_name gt echo My user name is env USER Environment variables can also be set using the env array set env SHELL bin csh See Simulator state variables B 408 for more information about ModelSim defined variables System commands To pass commands to the UNIX shell or DOS window use the Tcl exec command echo The date is exec date ModelSim SE User s Manual Tcl and ModelSim 16 377 List processing List processing In Tcl a list is a set of strings in curly braces separated by spaces Several Tcl commands are available for creating lists indexing into lists appending to lists getting the length of lists and shifting lists These commands are Command syntax Description lappend var_name vall val appends vall val2 etc to list var_name lindex list_name index returns the index th element of list_name the first element is 0 linsert list_name index vall val2
43. a ee A888 PLEAlmLacens s 2 ke we ew A389 ModelSim SE User s Manual Technical Support Updates and Licensing A 385 Technical support electronic Technical support electronic Model Technology customers Support questions may be submitted through the Model Technology online support form at www model com Model Technology customers may also email test cases to support model com please provide the following information in this format in the body of your email message Y our name Company Email address if different from message address Telephone FAX optional ModelSim product SE EE or PE and VHDL VLOG or PLUS ModelSim Version Use the Help About dialog box with Windows type vecom for UNIX workstations Host operating system version PC hardware security key authorization number Ethernet card address if used for authorization Host ID of license server for workstations e Description of the problem please include the exact wording of any error messages Note Model Technology customers in Europe should contact their distributor for support See www model com contact_us asp for distributor contact information Mentor Graphics customers Mentor Graphics Customer Support offers a SupportNet Email server for North American and European companies that lets customers find product information or submit service requests call logs to the SupportCenter 24 hours a day 365 d
44. delay in GUI_expression_format assign delay to signals in a GUI_expression Signal attributes CR 303 acc_fetch_paramval_str function in PLI allows fetching of a string on 64 bit platforms 64 bit support in the PLI 5 125 WLF file control variables new vsim control variables configure WLF file creation Setting default simulation options 8 265 F 448 What s new in ModelSim ModelSim SE User s Manual Documentation changes What Description Where select a link Model Sim release New Foreign Language Interface Reference manual new manual provides detailed documentation of FLI including code examples FLI Reference Manual 5 5 FLI chapter has been eliminated replaced by FLI reference manual new chapter on waveform comparison describes new waveform comparison feature Chapter 11 Waveform Comparison new tutorial on waveform comparison practice using the new waveform comparison feature ModelSim Tutorial ModelSim SE User s Manual What s new in ModelSim F 449 GUI changes in version 5 5 GUI changes in version 5 5 This section identifies differences between the version 5 3 5 4 GUI and the 5 5 GUI Main window changes we a FASI Menubarandtoolbar a F 451 File Men o 2 4 w 2 amp amp PASA Edt menie s e w 4 oe 8 a mw ew amp a F453 Desi
45. lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 ModelSim SE User s Manual ModelSim Graphic Interface 8 223 Wave window The Wave window toolbar The Wave window toolbar gives you quick access to these ModelSim commands and functions wave default OF gt File Edit Cursor Zoom Compare Bookmark Format Window A x S A c x oS SL SL F amp F FF ESLCE SS ESSE EF amp S iS S S gt o O d Lo lt Pe vw amp SSE Fo Le e e ES ve os ESN SSNS SES Y N iS So S A FL y s S S S e g vo o 2 V o SS S xS E AS Wave window toolbar buttons Button Menu equivalent Other options Load Wave Format File gt Load Format do wave do run a Wave window format DO see do command CR 104 file previously saved with Save Format Save Wave Format File gt Save Format none saves the current Wave window display and signal preferences to a do macro file Print Waveform File gt Print none prints a user selected range of the File gt PrintPostscript current Wave window display to a printer or a file o Cut Edit gt Cut right mouse in pathname pane gt Cut cut the selected signal from the Wave window
46. min tst_pseudo clock min tst_pseudo teset min tst_pseudo storage min tst_pseudo expected min tst_pseudo data Typical SDF Timing c e o c typ tst_pseudo clock typ tst_pseudo reset typ tst_pseudo storage typ tst_pseudo expected typ tst_pseudo data Compare Data tst_pseudo clock tst_pseudo reset tst_pseudo storage tst_pseudo expected tst_pseudo data tst_pseudo clocked_data tst_pseudo clocked_delay4_data tst_pseudo tol_typ_exp_data tst_pseudo tol_min_exp_data tst_pseudo clocked_typ_exp_data tst_pseudo clocked_min_exp_data 00007 O ns 100071 0 es Bal Galen ta match match match match diff match match compare tst_pseudo data 991647 ps match Sn Diff number 47 From time 980939 ps delta 1 to time 994078 ps delta 1 diff min tst_pseudo data Std maeh typ Ast_pseudo data Stl match 10000 ps 100940 ps cs 964670 ps to 1239284 ps 11 316 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison Compare Data The Wave window provides a graphic display of waveform comparison results Pathnames of all test signals included in the waveform comparison are denoted by yellow triangles Test signals that contain timing differences when compared with the reference signals are denoted by a red X over the yellow triangle tst_pseudo clock tst_pseudo reset tst_pseudo sto
47. modify or delete signals 11 308 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison The Add button opens the Add Clock Add Clock dialog where you can define a clock signal name a delay signal offset the signal upon which the clock will be based and whether the compare strobe edge will be the rising or falling edge or both You can also use The GUI Expression Builder 8 275 to specify a when expression that must evaluate to true or 1 at the Modify Clock signal edge for the clock to become effective ae oe Modify Clock A El Comparison Clocks isi aa dialog opens the Men A Tre dialog This dialog provides the same functionality as the rpms Add Clock dialog ModelSim SE User s Manual Waveform Comparison 11 309 Graphical Interface to Waveform Comparison Continuous Comparison With the Continuous Comparison method you can set leading and trailing edge tolerances The leading edge tolerance specifies how much earlier the test signal edge may occur before the reference signal edge The trailing edge tolerance specifies how much later the test signal edge may occur after the reference signal edge The default value for both tolerances is zero In addition these tolerances may be specified differently for each signal compared Continuous Comparison Leading Tolerance Trailing Tolerance is o Ts im With Co
48. s Manual Datasets saved simulations and virtuals 7 139 Datasets Viewing dataset structure In versions 5 5 and later each dataset you open creates a Structure page in the Main window workspace This page contains the same data as the Structure window 8 210 but you get one for each dataset The graphic below shows three Structure pages one for the active simulation Sim and one each for two open datasets Test and Gold ModelSim File Edit Design View Project Run Compare Macro Options Window Help ae SB ERT oye EAEN El D m memory M Package std_logic_util W Package vi_types M Package std_logic_1164 W Package standard E Project test gold top i If you have too many tabs to display in the available space you can scroll the tabs left or right by clicking and dragging them Each Structure page has a context menu that you access by clicking the right mouse button Windows 2nd button UNIX 3rd button anywhere within the Structure page 7 140 Datasets saved simulations and virtuals ModelSim SE User s Manual Datasets ModelSim 101 x File Edit Design View Project Run Compare Macro Options Window Help Se SB ERT w0t ElEkEk at oP al top topfonly VSIM 13 gt p proc Save As c cache PR D m memory FE Ascending M Package std_logic_util Expand Selected Descending MM Package vl_types Collapse Selected Declaration Order M Package st
49. std standard Loading E modelsim55_102500 win32 ieee std_logic_ 1164 body Loading work gates Loading work adder structural Loading work xorg only Loading work anda only Loading work orgfonly WSIM 55 gt wm title ModelSimn adder adder structural M sor xorgfonly E xor2 xora only MM and1 anda only M or orgfonly M and2 anda only M or2 oro only W Package gates Library ane e Project page Shows all files that are included in the open project See Chapter 2 Projects and system initialization for details Library page Shows compiled design units in the specified library See Managing library contents 3 44 for details Structure pages Shows a hierarchical view of the active simulation and any open datasets This is the same data that is displayed in the Structure window 8 210 There is one page for the current simulation and one page for each open dataset See Viewing dataset structure 7 140 for details Compare page Shows comparison objects that were created by doing a waveform comparison See Chapter 11 Waveform Comparison for details 8 158 ModelSim Graphic Interface ModelSim SE User s Manual Main window Transcript The transcript portion of the Main window maintains a running history of commands that are invoked and messages that occur as you work with ModelSim When a simulation is running the transcript display
50. swriteb swriteh swriteo ungetc gt Note readmemb and readmemh match the behavior of Verilog XL rather than IEEE Std 1364 Specifically it loads data into memory starting with the lowest address For example whether you make the declaration memory 127 0 Or memory 0 127 ModelSim will load data starting at address 0 and work upwards to address 127 ModelSim SE User s Manual Verilog Simulation 5 101 System Tasks Verilog XL compatible system tasks The following system tasks are provided for compatibility with Verilog XL Although they are not part of the IEEE standard they are described in an annex of the IEEE Std 1364 Scountdrivers Sgetpattern Ssreadmemb Ssreadmemh The following system tasks are also provided for compatibility with Verilog XL but they are not described in the IEEE Std 1364 Ssystem operating system shell command This system task executes the specified operating system shell command and displays the result For example to list the contents of the working directory on Unix Ssystem 1s The following system tasks are extended to provide additional functionality for negative timing constraints and an alternate method of conditioning as does Verilog XL Ssetuphold clk_event data_event setup_limit hold_limit notifier tstamp_cond tcheck_cond delayed_clk delayed_data The tstamp_cond argument conditions the data_event for the setup check and the clk_event for
51. test dataset names e Comparison Wizard Gives step by step assistance while you create a waveform comparison 11 318 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison e Run Comparison Computes the number of differences from time zero to the end of the simulation run from time zero until the maximum total number of differences per signal limit is reached or from time zero until the maximum total number of differences for all signals compared 1s reached This information is posted to the Main window transcript and saved to the compare_info txt file It is equivalent to the compare run command CR 80 H H write results to compare_info txt compare start H Computing waveform differences from time O ps to 10 us H XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Max total difference per signal limit of 100 reached on signal compare tst_pseudo tol_min_exp_data x H Comparison reached signal difference lirit at time 8080 ns H Found 438 differences Tvsim 3 gt E ltyp tst_pseudo A End Comparison Stops difference computation and closes the currently open comparison e Add Compare by Signal Opens the structure_browser dialog box page 11 307 and allows you to designate signals for comparison Compare by Region Opens the Add Comparison by Region dialog box page 11 311 and allows you to designate a reference region for comparison Also allows you to designate a
52. 1 00000010 0000000000000010 0 1 1 00000010 00000 560 0 001 1 00000010 0000000000000010 0 1 1 00000010 00000 580 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 O0000 585 0 1 0 1 1 00000010 0000000000000010 0 1 0 00000010 O0000 590 0 1 0 1 0 00000010 0000000000000010 0 1 0 00000010 00000t 600 0 0 O 1 0 00000010 0000000000000010 0 1 0 00000010 00000 620 0 1 0 1 0 00000010 0000000000000010 0 1 0 00000010 00000 625 0 100 1 00000011 2222222222222Z4P1 1 00000010 22222 al Default dataset sim gt i HDL items you can view One entry is created for each of the following VHDL and Verilog HDL items within the design e VHDL items signals and process variables e Verilog items nets and register variables e Comparison items comparison regions and comparison signals see Chapter 11 Waveform Comparison for more information e Virtual items Virtual signals and functions P Note Constants generics and parameters are not viewable in the List or Wave windows ModelSim SE User s Manual ModelSim Graphic Interface 8 175 List window The List window menu bar The following menu commands are available from the List window menu bar File menu Write List format save the listing as a text file in one of three formats tabular events or TSSI Load Format run a List window format DO file previously saved with Save Format Save Format save the current List window display and signal pre
53. 190 To examine a particular process in the Dataflow window click on the process name in the Process window To examine a particular HDL item in the Dataflow window click on the item name in the Signals window With a signal in the center of the Dataflow window you can e click once on a process name in the Dataflow window to make the Source Process Signals and Variable windows update to show that process e click twice on a process name in the Dataflow window to move the process to the center of the Dataflow window With a process in the center of the Dataflow window you can e click twice on an item name to move that item to the center of the Dataflow window The backward and forward buttons on the toolbar are analogous to Back and Forward buttons in a web browser They move backward or forward through previous views of the dataflow move backward through dataflow views move forward through dataflow views The Dataflow window will display the current process when you single step or when ModelSim hits a breakpoint ModelSim SE User s Manual ModelSim Graphic Interface 8 173 Dataflow window Saving the Dataflow window as a Postscript file Select File gt Save Postscript Dataflow window to save the current Dataflow view as a Postscript file Configure the Postscript output with the following dialog box or use the Options gt Edit Preferences Main window command The dialog box has the following
54. 2 5 84 Event order issues a a A A DEN Verilog XL compatible alain peo wo 986 Compiling for faster performance 5 90 Compiling with fast roa ee ee 5 90 Compiling gate level designs with det ok o ook e e pep ANg Referencing the optimized design Lp 5 92 Enabling design object visibility with the acc coptios bom a w 5 94 Using pre compiled libraries 000a aaa 5 96 Cell Libraries Bo bo oe do o s o e o we OT SDF timing annotation a a aa 5 97 Delaymodes a aaa 5 97 System Tasks be we ee ee we oe poa 999 TEEE Std 1364 gti wk Joam Som a ea 999 Verilog XL compatible system tasks 5 102 init_signal spy ee eee 5104 Compiler Directives E L IEEE Std 1364 compiler directives aaa 5 106 Verilog XL compatible compiler directives 5 106 Using the Verilog PLI VPI 2 1 5 108 Registering PLI applications 5 108 Registering VPI applications o 5 110 Compiling and linking PLI VPI elicabons sop s o e el The PLI callback reason argument 5 117 The sizetf callback function 2 5 119 PLI object handles 2 2 ee 5 119 Third party PLI applications 5 120 Support for VHDL objects ee 5121 IEEE Std 1364 ACC routines 2 2 2 5 122 IEEE Std 1364 TF routines 5 123 Verilog XL com
55. 201 Structure open and or view the Structure window 8 210 Variables open and or view the Variables window 8 213 Signals open and or view the Signals window 8 193 List open and or view the List window 8 175 Process open and or view the Process window 8 190 Wave open and or view the Wave window 8 216 Dataflow open and or view the Dataflow window 8 171 Datasets open the Dataset Browser for selecting the current Dataset New create a new window of the specified type Other 1f the Performance Analyzer and or Code Coverage is turned on this selection will allow viewing of Hierarchical Profile Ranked Profile and Source Coverage a You can specify a Layout Style to become the default for ModelSim After choosing the Layout Style you want select Options gt Save Preferences and the layout style will be saved to the PrefMain layoutStyle preference variable Project menu Compile Order set the compile order of the files in the open Project see Changing compile order 2 34 for details Compile All compile all files in the open Project see Step 3 Compile the files 2 32 for details Add File to Project add file s to the open Project see Step 2 Add files to the project 2 31 for details 8 162 ModelSim Graphic Interface ModelSim SE User s Manual Main window Run menu Run lt default gt run simulation for one default run length change the run length with Opti
56. 304 graphical interface 11 305 hierarchical designs 11 304 icons 11 318 introduction 11 302 leading edge tolerance 11 310 11 313 limit count 11 314 List window display 11 322 logfile 11 302 modify clock 11 309 pathnames 11 317 preference variables 11 323 printing differences 11 321 reference dataset 11 305 reference region 11 311 reference signals 11 302 reload 11 321 rules 11 321 run run comparison 11 319 save differences 11 320 show differences 11 320 signal options 11 308 specify when expression 11 310 11 312 11 313 specifying a dataset 11 305 start 11 318 test dataset 11 305 test region 11 311 ModelSim SE User s Manual Index 478 test signals 11 302 timing differences 11 302 11 317 tolerances 11 303 trailing edge tolerance 11 310 11 313 values column 11 317 Verilog matching 11 314 VHDL matching 11 314 Wave window display 11 316 write report 11 320 waveform comparison 7 137 8 228 Waveforms 7 137 saving 8 220 saving and viewing E 434 saving as a eps file 8 220 viewing 8 216 WaveSignalNameWidth ini file variable B 401 Web site Model Technology s home page URL 1 23 Welcome dialog turning on off B 392 Windows finding HDL item names 8 153 opening multiple copies 8 154 opening with the GUI 8 162 searching for HDL item values 8 153 adding buttons 8 269 coverage_source 10 296 coverage_summary 10 292 Dataflow window 8 171 tracing signals and nets 8 173 List window 8 175 adding HDL items 8 180 ad
57. 8 174 Selection Selection gt Follow Selection updates the Dataflow window when the Process window 8 190 or Signals window 8 193 changes Selection gt Fix Selection freezes the view selected from within the Dataflow window Close Window menu close this copy of the Dataflow window you can create a new window with View gt New from the The Main window menu bar 8 160 Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 8 172 ModelSim Graphic Interface ModelSim SE User s Manual Dataflow window Tracing HDL items with the Dataflow window The Dataflow window is linked with the Signals window 8 193 and the Process window 8
58. 8 217 Wave window Cursor panes There are two cursor panes as shown below The left pane shows the time value for each cursor The selected cursor s value is highlighted The right pane shows the absolute time value for each cursor and relative time between cursors Up to 20 cursors can be displayed 200 ns two cursor panes HDL items you can view VHDL items indicated by a dark blue square ftop clk signals and process variables top pry top pstrb Verilog items top prdy indicated by a light blue circle top paddr nets register variables and named top pdata events Hopesrw top sstrb Virtual items top srdy indicated by an orange diamond top saddr virtual signals buses and functions top sdata see Virtual Objects User defined buses and more 7 144 for more information Comparison items indicated by a yellow triangle comparison region and comparison signals see Chapter 11 Waveform Comparison for more information Note Constants generics and parameters are not viewable in the List or Wave windows The data in the item values pane is very similar to the Signals window except that the values change dynamically whenever a cursor in the waveform pane is moved At the bottom of the waveform pane you can see a time line tick marks and a readout of each cursor s position As you click and drag to move a cursor the time value at the cursor location is updated at the
59. A4 in std_logic A5 in std_logic A6 in std_logic A7 in std logici A8 in std_logic A9 in std_logic A10 in std_logic All in std_logic A12 in std_logic A13 in std_logic A14 in std_logic A15 in std_logic CS in std_logic 00 out std_logic O out std_logic 02 out std_logic 03 out std_logic 04 out std_logic O05 out std_logic 06 out std_logic 07 out std_logic W inout std_logic end architecture Hardware of cy7c285 is attribute FOREIGN STRING attribute FOREIGN of Hardware architecture is hm_init SMODEL_TECH libhm sl CY7C285 MDL begin end Hardware Entity details e The entity name is the hardware model name you can manually change this name if you like e The port names are the same as the hardware model port names these names must not be changed If the hardware model port name is not a valid VHDL identifier then hm_entity issues an error message If hm_entity is invoked with the 93 option then the identifier is converted to an extended identifier and the resulting entity must also be compiled with the 93 option Another option is to create a pin name mapping file Consult the Logic Modeling documentation for details The port types are std_logic This data type supports the full range of hardware model logic states e The DelayRange generic selects minimum typical or maximum delay values Valid n values are min typ or max th
60. Developer s Guide http docs sun com 80 ab2 coll 45 10 SOL64TRANS HP HP UX 64 bit Porting and Transition Guide http docs hp com 80 dynaweb hpux 1 1 hpuxen 1a 0462 Generic__BookView HP UX 11 x Software Transition Kit http software hp com STK IBM AIX 64 bit Migration Guide http www developer ibm com library aix4 3 Sun 5 114 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI Specifying the PLI VPI file to load The PLI applications are specified as follows e As a list in the Veriuser entry in the modelsim ini file Veriuser pliappl so pliapp2 so pliappn so e As a list in the PLIOBJS environment variable setenv PLIOBJS pliappl so pliapp2 so pliappn so e As a pli option to the simulator multiple options are allowed pli pliappl so pli pliapp2 so pli pliappn so gt Note On Windows platforms the file names shown above should end with dll rather than so The various methods of specifying PLI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases See also Appendix B ModelSim Variables for more information on the modelsim ini file ModelSim SE User s Manual Verilog Simulation 5 115 Using the Verilog PLI VPI PLI example The following example is a trivial but complete PLI application hello c include veriuser h static h
61. If the SDF cell instance is a primitive instance then that primitive s delay is annotated If 1t is a module instance then all specify path delays are annotated that drive the output port specified in the DEVICE construct all path delays are annotated if the output port is omitted If the module contains no path delays then all primitives that drive the specified output port are annotated or all primitives that drive any output port if the output port is omitted SETUP is matched to setup and setuphold SDF Verilog SETUP d posedge clk 5 setup d posedge clk 0 SETUP d posedge clk 5 setuphold posedge clk d 0 0 HOLD is matched to hold and setuphold SDF Verilog HOLD d posedge clk 5 hold posedge clk d 0 HOLD d posedge clk 5 setuphold posedge clk d 0 0 SETUPHOLD is matched to setup hold and setuphold SDF Verilog SETUPHOLD d posedge clk 5 5 setup d posedge clk 0 SETUPHOLD d posedge clk 5 5 hold posedge clk d 0 SETUPHOLD d posedge clk 5 5 setuphold posedge clk d 0 0 RECOVERY is matched to recovery SDF Verilog RECOVERY negedge reset posedge clk 5 recovery negedge reset posedge clk 0 REMOVAL is matched to removal SDF Verilog REMOVAL negedge reset posedge clk 5 removal negedge reset posedge clk 0 12 332 Standard Delay Format SDF
62. LO Compiling and linking PLI VPI llas be AR ee See ee Se we ee we ge DIT The PLI callback reason argument lt s so senc 2 r 2 5 117 The sizeti callback TUBCUOR s por cor os p a aos e o e reses 3119 PLI object handles A BSH EA eS a lg Third party PLI applications god Sec oe ue e e SSR Bhs SOS we aa we oe ZO Support tor VHDL objects 6 e e ee ee ee ee Ree Be ede ew 121 IBRE Std 1364 ACC routines es e os ew we we em eRe 22 IEEE Std 1364 TF routines lt os coss e s eog oa ee a eb 5 123 Verilog XL compatible routines lt lt aaa 9 12 64 bit support in th PEL lt s w sas mope oe as Re aa a ey LS PLENPLENE ooe e dais aa a AS 6 Mixed VHDL and Verilog Designs 6 127 Separate compilers common libraries 2 ee 6 128 Mapping data ypes lt sc a e soe MR ses poe ea oh ee a a OZ VHDL emernces ss abe woe e A a e a E8 Verilog parameters 0 e poe OR eos e e E e rs ee we e 29 VHDL and Verilog poris s s soe ewa edoa a ekoe aa a a a a 6129 Verlos sates o s eo e A Ar o O10 VHDL instantiation of Verilog design units 0 u a a eee eee 6 132 Component declaration E E vgencomp component declaration be bd Re he a he Be a A e e a ee ew OS VOD Opt cio eco r obp eow ee he eee ee ne O 13 Verilog instantiation of VHDL design units 2 2 ee 6 136 ModelSim SE User s Manual Table of Contents 5 7 Datasets saved simulations
63. Main window transcript It is used in the dataset exercise in the ModelSim Tutorial This DO file adds several signals to the Wave window provides stimulus to those signals and then advances the simulation add wave ld add wave rst add wave clk add wave d add wave q force freeze clk 0 0 1 50 ns r 100 force rst 1 force rst 0 10 force ld 0 force d 1010 run 1700 force ld 1 run 100 force ld 0 run 400 force rst 1 run 200 force rst 0 10 run 1500 You can write more complex macros using the Tcl scripting language See Chapter 16 Tcl and ModelSim for more information Using Parameters with DO files You can increase the flexibility of DO files using parameters Parameters specify values that are passed to the corresponding parameters 1 through 9 in the macro file For example do testfile design vhd 127 If the macro file testfile contains the line bp 1 2 this command would place a breakpoint in the source file named design vhd at line 127 There is no limit on the number of parameters that can be passed to macros but only nine values are visible at one time You can use the shift command CR 183 to see the other parameters E 430 Tips and Techniques ModelSim SE User s Manual Using macros DO files Useful commands for handling breakpoints and errors If you are executing a macro when your simulation hits a breakpoint or causes a run time error ModelSim interrupts the macro and returns control to t
64. Maintaining 32 bit and 64 bit modules in the same library 2 2 2 E 434 Buscontention checking s s e s p e s s eres os oe e 435 Bus iloatehe Kne cesa isa a AR a a a as a a BAI 12 Table of Contents ModelSim SE User s Manual Desipn stability Checking coc 4 Re Gee ee ee kw a E486 Talle checking os esca bb Se RS he ee RE a Sw be amp E436 Detecting infinite zero delay loops ee so E486 Referencing source files with location maps 4 E437 Using location mapping 2 ee eee ee E 437 Pathname syntaX gt o s s s soado we as E A38 How location mapping works 2 a ee eee ee E438 Mapping with Tcl variables gt s c soos c aooe eee ew E438 Accelerate simulation by locking memory under HP UX 10 2 2 2 2 2 E439 Modeling memory in VHDL o o s e os s e Vos wee Ree ee eee eS ey gt E440 Setting up a List trigger with Expression Builder 2 1 E444 F What s new in ModelSim F 447 New TEADIES y opa Oe es Be OR se Ow Sm Ww RAAT Command and variable changes 2 2 ee ee F448 Documentation changes s so pos eos sop eos ee F449 GUI changes in version 5 5 lt s o 2 62 Re 4 4 5 4 44 lt F450 Main window changes a 451 Signals window changes s c p s p s eo tow 0 ee paea a a a a FAST Source window changes s ss seoa mac osc ma sosro woo ee o oa a a F458 Wave window chan
65. ModelSim SE User s Manual ModelSim Graphic Interface 8 197 Signals window You can add all the items in the current region with this command add list add wave log Or add all the items in the design with add list add wave log r If the target window Wave or List is closed ModelSim opens it when you when you invoke the command Finding HDL items in the Signals window To find the specified text string within the Signals window choose the Name or Value field to search and the search direction Down or Up Find Find Next Field Name Direction C Value You can also do a quick find from the keyboard When the Signals window is active each time you type a letter the signal selector highlight will move to the next signal whose name begins with that letter Setting signal breakpoints You can set signal breakpoints a k a when breakpoints see the when command CR 273 for more details via a context menu in the Signal window When statements instruct ModelSim to perform actions when the specified conditions are met For example you can break on a signal value or at a specific simulator time see Time based breakpoints CR 275 When a breakpoint is hit a message appears in the transcript window about which signal caused the breakpoint To access the breakpoint commands select a signal and then click your right mouse button 2nd button in Windows 3rd button in UNIX To set a b
66. ModelSim fal File Edit Design View Ms Run Compare Macro Options Window Help a xi Loading project Library wor Loading project Modifying E modelsim55_se win32 test mpf ae adder run over hl Mi lod dl Five pages Design VHDL Verilog Libraries and SDF allow you to select various simulation options You can switch between pages to modify settings then begin simulation by selecting the Load button If you select Cancel all selections remain unchanged and you are returned to the Main window the Exit button only active before simulation closes ModelSim The Save Settings button allows you to save the preferences on all pages to a DO macro file Compile before you simulate To begin simulation you must have compiled design units located in a design library see Creating a design library 4 57 B Note Many of the dialog box options discussed in this section include parenthetical elements that correspond to vsim CR 258 command options For example Simulator Resolution time lt multiplier gt lt time_unit gt 8 256 ModelSim Graphic Interface ModelSim SE User s Manual Simulating with the graphic interface Design selection page Load Design M counter i test_counter gt Note The Exit button closes the Load Design dialog box and quits ModelSim The Design page includes these options e Library Specifies a library to view Make certain your selection is a valid ModelSim li
67. Modeling SmartModels ModelSim SE User s Manual VHDL SmartModel interface Entity details e The entity name is the SmartModel name you can manually change this name if you like e The port names are the same as the SmartModel port names these names must not be changed If the SmartModel port name is not a valid VHDL identifier then sm_entity automatically converts it to a valid name If sm_entity is invoked with the 93 option then the identifier is converted to an extended identifier and the resulting entity must also be compiled with the 93 option If the 93 option had been specified in the example above then WAIT would have been converted to WAI7 Note that in this example the port WAIT was converted to WAIT_PORT because wait is a VHDL reserved word e The port types are std_logic This data type supports the full range of SmartModel logic states e The DelayRange TimingVersion and MemoryFile generics represent the SmartModel attributes of the same name Consult your SmartModel library documentation for a description of these attributes and others Sm_entity creates a generic for each attribute of the particular SmartModel The default generic value is the default attribute value that the SmartModel has supplied to sm_entity Architecture details e The first part of the foreign attribute string sm_init is the same for all SmartModels The second part MODEL_TECH libsm sl is taken from the libsm entry in the
68. Ranked and Hierarchical Profile windows have a number of features that can manipulate the data displayed Most of these features are contained in a toolbar in the header of the window which displays an icon for each feature Placing the mouse over an icon causes its function to be displayed l Hierarchical Profile Samples 5121 oh Under fi 5 o a The Find Entry icon provides access to a search function that can be used to search for a given string in the window Type text in the entry box and then press Return or click the binocular icon The Under filter allows you to specify a cutoff percentage for displaying the data By default every entry in the profiling data that has spent at least 1 of the simulation time under that entry will be displayed The hierCutoff and rankCutoff variables provide asimilar function See Setting preferences with Tcl variables 9 290 The Update Data icon causes the data to be reloaded from the simulator If you change the cutoff percentage or do an additional simulation run the Ranked and Hierarchical Profile windows are not automatically updated You should click on this button to update the data being displayed in these windows The Save to File icon allows the data to be saved to disk You will be prompted for the output file name The profile report command CR 158 provides another way to save profile data 9 288 Perfo
69. Task update_mru icon module instantiations named forks named begins tasks and functions Function pick_set Task systead Task syswrite Virtual items Function get_hit indicated by an orange diamond E s0 cache_set only icon E sl cache_set only virtual regions see Virtual Objects I s2 cache_set only User defined buses and more 7 f E s3 cache_set only 144 for more information You can expand and contract the display to view the hierarchical structure by clicking on the boxes that contain or Clicking expands the hierarchy so the sub elements of that item can be seen Clicking contracts the hierarchy sim ftop The first line of the Structure window indicates the top level design unit being simulated By default this is the only level of the hierarchy that is expanded upon opening the Structure window 8 210 ModelSim Graphic Interface ModelSim SE User s Manual Structure window Instance name components in the Structure window An instance name displayed in the Structure window consists of the following parts e instantiation label Indicates the label assigned to E sD cache_set orily the component or module instance in the instantiation ve oe statement i instantiation label architecture a entity or module e entity or module y Indicates the name of the entity or module that has been instantiated e architecture Indicates the name of the archit
70. Techniques E 425 How to use checkpoint restore How to use checkpoint restore The checkpoint CR 62 and restore CR 172 commands will save and restore the simulator state within the same invocation of vsim or between vsim sessions If you want to restore while running vsim use the restore command CR 172 we call this a warm restore If you want to start up vsim and restore a previously saved checkpoint use the restore switch with the vsim command CR 258 we call this a cold restore gt Note Checkpoint restore allows a cold restore followed by simulation activity followed by a warm restore back to the original cold restore checkpoint file Warm restores to checkpoint files that were not created in the current run are not allowed except for this special case of an original cold restore file The things that are saved with checkpoint and restored with the restore command are e simulation kernel state e vsim wlf file e signals listed in the list and wave windows e file pointer positions for files opened under VHDL e file pointer positions for files opened by the Verilog fopen system task e state of foreign architectures Things that are NOT restored are e state of macros e changes made with the command line interface such as user defined Tcl commands e state of graphical user interface windows toggle statistics In order to save the simulator state use the command checkpoint lt filename gt To resto
71. The GUI Expression Builder 8 275 e Expression Enter the expression for trigger gating into this field or use the Expression Builder select the Use Expression Builder button The expression is evaluated when the List window would normally have displayed a row of data given the trigger on signals and strobe settings above e On Duration The duration for gating to remain open after the last list row in which the expression evaluates to true expressed in x number of default timescale units Gating is level sensitive rather than edge triggered List window gating information is saved as configuration statements when the list format 1s saved The gating portion of a configuration statement might look like this configure list config usegating 1 configure list config gateduration 100 configure list config gateexpr lt expression gt Adding HDL items to the List window Before adding items to the List window you may want to set the window display properties see Setting List window display properties 8 178 You can add items to the List window in several ways Adding items with drag and drop You can drag and drop items into the List window from the Signals Source Process Variables Wave Dataflow or Structure window Select the items in the first window then drop them into the List window Depending on what you select all items or any portion of the design may be added Adding items from the Main window command li
72. Timing Annotation ModelSim SE User s Manual Verilog SDF RECREM is matched to recovery removal and recrem SDF Verilog RECREM negedge reset posedge clk 5 5 recovery negedge reset posedge clk 0 RECREM negedge reset posedge clk 5 5 removal negedge reset posedge clk 0 RECREM negedge reset posedge clk 5 5 SKEW is matched to skew SDF recrem negedge reset posedge clk 0 Verilog SKEW posedge clk1 posedge clk2 5 WIDTH is matched to width SDF skew posedge clk1 posedge clk2 0 Verilog WIDTH posedge clk 5 PERIOD is matched to period SDF width posedge clk 0 Verilog PERIOD posedge clk 5 NOCHANGE is matched to nochange SDF period posedge clk 0 Verilog NOCHANGE negedge write addr 5 5 Optional edge specifications nochange negedge write addr 0 0 Timing check ports and path delay input ports can have optional edge specifications The annotator uses the following rules to match edges e A match occurs if the SDF port does not have an edge e A match occurs if the specify port does not have an edge e A match occurs if the SDF port edge is identical to the specify port edge e A match occurs if explicit edge transitions in the specify port edge overlap with the SDF port edge These rules allow SDF annotation to take place
73. Transition locate the next signal locate the previous signal value change for the value change for the selected signal selected signal Zooming changing the waveform display range Zooming lets you change the simulation range in the waveform pane You can zoom with either the context menu toolbar buttons mouse keyboard or commands Using the Zoom menu You can use the Wave window menu bar or call up the context menu by clicking the right mouse button in the waveform pane The Zoom menu options include e Zoom Area with Mouse Button 1 Use mouse button 1 to create a zoom area Position the mouse cursor to the left side of the desired zoom interval press mouse button 1 and drag to the right Release when the box has expanded to the right side of the desired zoom interval Zoom In Zooms in by a factor of two increasing the resolution and decreasing the visible range horizontally e Zoom Out Zooms out by a factor of two decreasing the resolution and increasing the visible range horizontally 8 240 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Zoom Full Redraws the display to show the entire simulation from time 0 to the current simulation time Zoom Last Restores the display to where 1t was before the last zoom operation Zoom Range Brings up a dialog box that allows you to enter the beginning and ending times for a range of time units to be displayed Zooming with toolbar buttons
74. a project select the file s in the Project page right click on the file names and select Compile Properties The pages that appear in the resulting dialog depend on the type of files you have selected If you select a VHDL file you ll see only the General and VHDL pages If you select a Verilog file you ll see only the General and Verilog pages If you select both a VHDL file and a Verilog file you lI see all three pages as shown in the dialog below When setting options on a group of files keep in mind the following e If two or more files have different settings for the same option the checkbox in the dialog will be grayed out like this Vv If you change the option you cannot change it back to a multi state setting without cancelling out of the dialog Once you click OK ModelSim will set the option the same for all selected files e If you select a combination of VHDL and Verilog files the options you set on the VHDL and Verilog tabs apply only to those file types Project Compiler Settings T Exclude File from Build Compile to library work El Ok Cancel Exclude File from Build Determines whether the file is excluded from the compile e Compile to library Specifies to which library you want to compile the file defaults to the working library The definitions of the options on the VHDL and Verilog pages can be found in the section Setting default compile options 8 252
75. an extension of the IEEE Std 1364 specification The tasks behave the same as the IEEE equivalent tasks such as dumpfile dumpvar etc The difference is that fdumpfile can be called multiple times to create more than one VCD file and the remaining tasks require a filename argument to associate their actions with a specific file VCD commands VCD system tasks ved add CR 198 file lt filename gt fdumpvars ved checkpoint CR 199 lt filename gt fdumpall ved files CR 210 lt filename gt fdumpfile ved flush CR 212 lt filename gt fdumpflush ved limit CR 213 lt filename gt fdumplimit ved off CR 214 lt filename gt fdumpoff ved on CR 215 lt filename gt fdumpon 13 342 Value Change Dump VCD Files ModelSim SE User s Manual ModelSim VCD commands and VCD tasks ModelSim versions 5 5 and later also support dumpports system tasks The table below maps the VCD dumpports commands to their associated tasks VCD dumpports commands VCD system tasks ved dumpports CR 201 dumpports ved dumpportsall CR 203 dumpportsall ved dumpportsflush CR 204 dumpportsflush ved dumpportslimit CR 205 dumpportslimit ved dumpportsoff CR 206 dumpportsoff ved dumpportson CR 207 dumpportson ModelSim SE User s Manual Value Change Dump VCD Files 13 343 Resimulating a VHDL design from a VCD file Resimula
76. and output driving unknown unknown input driving high and output driving low unknown input driving unknown and output driving high ModelSim SE User s Manual Value Change Dump VCD Files 13 349 Capturing port driver data Strength values The lt strength gt values are based on Verilog strengths Strength VHDL std_logic mappings O highz A small medium weak large pull W HL strong TT OW oo 2 47 2 US XO T 7 supply Port identifier code The lt identifier_code gt is an integer preceded by lt that starts at zero and is incremented for each port in the order the ports are specified Also the variable type recorded in the VCD header is port 13 350 Value Change Dump VCD Files ModelSim SE User s Manual Capturing port driver data Example VCD output from vcd dumpports The following is an example VCD file created with the ved dumpports command Scomment File created using the following command vcd dumpports results dumpl Send date Tue Aug 20 13 33 02 2000 Send Sversion ModelSim Version 5 4c Send Stimescale ins Send Sscope module topl end Sscope module ul Send Svar port 1 lt 0 a Send Svar port 1 lt 1 b Send Svar port 1 lt 2 c Send Supscope end Supscope end Senddefinitions Send 0 Sdumpports PN 6 6 lt 0 px 6 6 lt 1 p 6 lt 2 end 10 px 6 pN 6 pG Model
77. and toolbar option details new menus wave default new icons Edit menu See The Wave window menu bar 8 220 for complete menu option details 5 5 new selection ModelSim SE User s Manual What s new in ModelSim F 459 Compare menu The Compare menu is new in version 5 5 See Chapter 11 Waveform Comparison for details on waveform comparisons See also The Wave window menu bar 8 220 for complete menu option details 5 5 Compare Iof x new menu Bookmark menu The Bookmark menu is new in version 5 5 See Saving zoom range and scroll position with bookmarks 8 241 for details on bookmarks See also The Wave window menu bar 8 220 for complete menu option details 5 5 Bookmark OF Xx Edit Bookm new menu F 460 What s new in ModelSim ModelSim SE User s Manual Coverage_summary window changes Coverage_summary window changes new half of window shows line misses and exclusions The coverage_summary window has been enhanced to show line misses and exclusions below the summary information li covyerage_summary File Coverage Report Lines Hits Coverage E modelsim55_011801 4win322 2whdl 240 0 E modelsim55_011801 4win322 4whdl 507 0 E modelsim55_011801 win32 vhdl 515 0 E modelsim55_011801 win322 4whdl 50 0 rol 37 retrieve vhd 5 5 ringrtl hd 1 1 store vhd 9 9 testring hd 83 60 4
78. any of the simulation state has been restored This allows the PLI application to prepare for the restore but it shouldn t restore its state with calls to tf_read_restart until it is called with reason_restart The reason_startofrestart value is passed only for a restore command and not in the case that the simulator is invoked with restore reason_restart For the execution of the restore command This is when the PLI application must restore its state with calls to tf_read_restart reason_reset For the execution of the restart command This is when the PLI application should free its memory and reset its state We recommend that all PLI applications reset their internal state during a restart as the shared library containing the PLI code might not be reloaded See the keeploaded CR 260 and keeploadedrestart CR 260 vsim arguments for related information reason_endofreset For the completion of the restart command after the simulation state has been reset but before the design has been reloaded reason_interactive For the execution of the stop system task or any other time the simulation is interrupted and waiting for user input reason_scope For the execution of the environment command or selecting a scope in the structure window Also for the call to acc_set_interactive_scope if the callback_flag argument is non zero reason_paramvc For the change of value on the system task or function argument reason_synch For th
79. areas in your simulation where performance can be improved The Performance Analyzer can be used at all levels of design simulation Functional RTL and Gate Level and has the potential to save hours of regression test time In addition ASIC and FPGA design flows benefit from the use of this tool gt Note The Performance Analyzer does not work on Windows 95 ModelSim SE User s Manual Performance Analyzer 9 281 Introducing Performance Analysis Introducing Performance Analysis The Performance Analyzer provides an interactive graphical representation of where ModelSim is spending its time while running your design This feature enables you to quickly determine what is impacting the design environment s simulation performance Those familiar with the design and validation environment will be able to find first level improvements in a matter of minutes For example the Performance Analyzer might show some or all of the following e A non accelerated VITAL library cell is impacting simulation run time e A process is consuming more time than necessary because of non required items in its sensitivity list e A testbench process is active even though it is not needed e A random number process is consuming simulation resources when in a test bench that is running in non random mode With this information you can make changes to the VHDL or Verilog source code that will speed up the simulation A Statistical Sampling Profi
80. as ordinary characters and included in the word Command substitution variable substitution and backslash substitution are performed on the characters between the quotes as described below The double quotes are not retained as part of the word 5 Ifthe first character of a word is an open brace then the word is terminated by the matching close brace Braces nest within the word for each additional open brace there must be an additional close brace however if an open brace or close brace within the word is quoted with a backslash then it is not counted in locating the matching close brace No substitutions are performed on the characters between the braces except for backslash newline substitutions described below nor do semi colons newlines close brackets or white space receive any special interpretation The word will consist of exactly the characters between the outer braces not including the braces themselves 6 Ifa word contains an open bracket then Tcl performs command substitution To do this it invokes the Tcl interpreter recursively to process the characters following the open bracket as a Tcl script The script may contain any number of commands and must be terminated by a close bracket The result of the script i e the result of its last command is substituted into the word in place of the brackets and all of the characters between them There may be any number of command substitutions in a single word
81. as set forth in subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 Boeckman Road 466 License Agreement ModelSim SE User s Manual Wilsonville Oregon 97070 7777 USA 12 THIRD PARTY BENEFICIARY For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth in this Agreement 13 CONTROLLING LAW This Agreement shall be governed by and construed under the laws of Ireland if the Software is licensed for use in Israel Egypt Switzerland Norway South Africa or the European Union the laws of Japan if the Software is licensed for use in Japan the laws of Singapore if the Software is licensed for use in Singapore People s Republic of China Republic of China India or Korea and the laws of the state of Oregon if the Software is licensed for use in the United States of America Canada Mexico South America or anywhere else worldwide not provided for in this section 14 SEVERABILITY If any provision of this Agreement is held by a court of competent jurisdiction to be void invalid unenforceable or illegal such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect 1
82. assistance to settle or defend the claim and c grant Mentor Graphics sole authority and control of the defense or settlement of the claim 8 2 If an infringement claim is made Mentor Graphics may at its option and expense either a replace or modify Software so that it becomes noninfringing or b procure for you the right to continue using Software If Mentor Graphics determines that neither of those alternatives is financially practical or otherwise reasonably available Mentor Graphics may require the return of Software and refund to you any license fee paid less a reasonable allowance for use 8 3 Mentor Graphics has no liability to you if the alleged infringement is based upon a the combination of Software with any product not furnished by Mentor Graphics b the modification of Software other than by Mentor Graphics c the use of other than a current unaltered release of Software d the use of Software as part of an infringing process e a product that you design or market f any Beta Code contained in Software or g any Software provided by Mentor Graphics licensors which do not provide such indemnification to Mentor Graphics customers 8 4 THIS SECTION 8 STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT 9 TERM This Agreement remains effective until expi
83. bottom of the cursor You can resize the window panes by clicking on the bar between them and dragging the bar to a new location 8 218 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Waveform and signal name formatting are easily changed via the Format menu 8 223 You can reuse any formatting changes you make by saving a Wave window format file see Adding items with a Wave window format file 8 219 Adding HDL items in the Wave window Before adding items to the Wave window you may want to set the window display properties see Setting Wave window display properties 8 235 You can add items to the Wave window in several ways Adding items from the Signals window with drag and drop You can drag and drop items into the Wave window from the List Process Signals Source Structure or Variables window Select the items in the first window then drop them into the Wave window Depending on what you select all items or any portion of the design can be added Adding items from the Main window command line To add specific HDL items to the window enter separate the item names with a space add wave lt item_name gt lt item_name gt You can add all the items in the current region with this command add wave Or add all the items in the design with add wave r Adding items with a Wave window format file To use a Wave window format file you must first save a format file for the design y
84. by Compile Order commands on the context menu Keep in mind that the order you see in the Project tab is not necessarily the order in which the files will be compiled To open the Compile Order dialog right click in an empty area of the Project tab and select Compile Order The dialog shown below opens Compile Order gt Current Order Sa EG Verilog Group 1 3 tcounter 3 counter v amp counter vhd gates vhd adder vhd move up in order move down in order group Verilog files ungroup Verilog files The group and ungroup buttons are used on Verilog files only They allow you to group two or more Verilog files so they are sent to the compiler at the same time One case where you might use this is when you have one file with a bunch of define statements and a second file that is a Verilog module You would want to compile these two files at the same time 2 34 Projects and system initialization ModelSim SE User s Manual Customizing project settings Setting compiler options The VHDL and Verilog compilers vcom and vlog respectively have numerous options that affect how a design is compiled and subsequently simulated Outside of a project you can set the defaults for all future simulations using the Options gt Compile Main window command Inside of a project you can set these options on individual files or a group of files To set the compiler options in
85. by the simulator Because the uselib directive is intended to reference source libraries ModelSim Verilog must infer the object libraries from the library references The rule is to assume an object library named work in the directory defined in the library reference dir lt library_directory gt or the directory containing the file in the library reference file lt library_file gt The library reference libext lt file_extension gt is ignored in the pre 5 5 release implementation For example the following uselib directives infer the same object library uselib dir h vendorA uselib file h vendorA libcells v In both cases ModelSim Verilog assumes that the library source is compiled into the object library h vendorA work ModelSim Verilog also extends the uselib directive to explicitly specify the object library with the library reference lib lt library_name gt For example uselib lib h vendorA work 5 82 Verilog Simulation ModelSim SE User s Manual Compilation The library name can be a complete path to a library or it can be a logical library name defined with the vmap command Since this usage of uselib is an extension it may be desirable to qualify it with an ifdef to make it portable to other Verilog systems For example ifdef MODEL_TECH uselib lib vendorA e156 uselib dir h vendorA libext v endif The MODEL_TECH macro is automatically defined by the ModelSim compi
86. can be set only on executable lines The breakpoints are toggles click once to create the colored dot click again to disable or enable the breakpoint To delete the breakpoint completely click the colored dot with your right mouse button and select Remove Breakpoint ModelSim SE User s Manual ModelSim Graphic Interface 8 205 Source window Setting breakpoints with the Edit gt Breakpoints command Selecting Edit gt Breakpoints Source window opens the dialog box shown below Breakpoint s wm bp E modelsim55_s examples mixedHDL proc The Breakpoints dialog box allows you to create and manage both file line and signal breakpoints a k a when breakpoints For details on signal breakpoints see Setting signal breakpoints 8 198 and the when command CR 273 8 206 ModelSim Graphic Interface ModelSim SE User s Manual Source window You can enable and disable existing breakpoints by checking or unchecking the box next to the breakpoint s name To add a new file line breakpoint select Add BP or Edit Selected for an existing file line breakpoint Add Edit Breakpoint File Name ve Line Condition Instance Command s OK Cancel The Add Edit Breakpoint dialog box includes the following options File Name The file name in which you want to set the breakpoint Required The button next to this field allows you to browse to select a file Line The line
87. clear any selection in the widget lt control _ gt lt control gt lt control Z gt undoes previous edits in the Source window lt meta lt gt none move cursor to the beginning of the file lt meta gt gt none move cursor to the end of the file lt meta v gt PageUp move cursor up one screen lt Meta w gt lt control c gt copy selection lt F8 gt search for the most recent command that matches the characters typed Main window only C 414 ModelSim Shortcuts ModelSim SE User s Manual The Main window allows insertions or pastes only after the prompt therefore you don t need to set the cursor when copying strings to the command line Right mouse button The right mouse button provides shortcut menus in the Main and Wave windows In the Source window the button gives you feedback on any HDL item under the cursor See Chapter 8 ModelSim Graphic Interface for menu descriptions ModelSim SE User s Manual ModelSim Shortcuts C 415 C 416 ModelSim Shortcuts ModelSim SE User s Manual D Using the FLEXIm License Manager Appendix contents Starting the license server daemon D 418 Locating the license file D 418 Controlling the license file search D 418 Manual start a D 418 Automatic start at boot time D 419 What to do
88. clock from the drop down history of past clock selections Or you can click the Clocks button to add a new clock Comparison Clocks Clicking the Clocks button opens the Comparison Clocks dialog box To add a signal click the Add button to open the Add Clock dialog box where you can define a clock signal name a delay signal offset the signal upon which the clock will be based and whether the compare strobe edge will be the rising or falling edge or both You can also use the Expression Builder to Specify 11 312 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison a When Expression that must evaluate to true or 1 at the signal edge for the clock to become effective Add Clock E a e Continuous Comparison With the Continuous Comparison method you can set leading and trailing edge tolerances The leading edge tolerance specifies how much earlier the test signal edge may occur before the reference signal edge The trailing edge tolerance specifies how much later the test signal edge may occur after the reference signal edge The default value for both tolerances is zero In addition these tolerances may be specified differently for each signal compared e Specify When Expression Allows you to use The GUI Expression Builder 8 275 to specify a when expression that must evaluate to true or at the signal edge for the clock to become effective
89. contain several instances of a utility function that compute the maximum of 3 delay values A ranked view might reveal that the simulation spent 60 of its time in this utility function but would not tell you which routine or routines were making the most use of it The hierarchical view will reveal which line is calling the function most frequently Using this information you might decide that instead of calling the function every time to compute the maximum of the 3 delays this spot in your VHDL code can be used to compute it just once You can then store the maximum delay value in a local variable The Parent column provides the percent of simulation time a given entry used of its parent s total simulation time From this column you can calculate the percentage of total simulation time taken up by any function For example if a particular parent entry used ModelSim SE User s Manual Performance Analyzer 9 287 Ranked Hierarchical Profile Window Features 10 of the total simulation time and it called a routine that used 80 of its simulation time then the percentage of total simulation time spent in that routine would be 80 of 10 or 8 In addition to these differences the ranked view displays any particular function only once regardless of where it was used In the hierarchical view the function can appear multiple times each time in the context of where it was used Ranked Hierarchical Profile Window Features The
90. defined bus 8 154 displaying in Dataflow window 8 171 displaying values in Signals window 8 193 referencing in the hierarchy 4 69 saving values as binary log file 8 197 selecting signal types to view 8 195 viewing waveforms 8 216 Signals window see also Windows 8 193 Simulating applying stimulus to signals and nets 8 196 batch mode E 428 command line mode E 428 comparing simulations 7 137 11 301 mixed Verilog and VHDL Designs compilers 6 128 libraries 6 128 Verilog parameters 6 129 Verilog state mapping 6 130 VHDL and Verilog ports 6 129 VHDL generics 6 128 saving simulations 7 137 E 434 saving waveform as a Postscript file 8 245 setting default run length 8 266 setting iteration limit 8 266 setting time resolution 8 258 speeding up with Performance Analyzer 9 28 1 Verilog delay modes 5 97 event order issues 5 85 hazard detection 5 86 optimizing performance 5 90 resolution limit 5 84 XL compatible simulator options 5 86 VHDL 4 58 invoking code coverage 4 59 viewing results in List window 8 175 with the graphic interface 8 256 with VITAL packages 4 67 Simulation and Compilation Verilog 5 73 5 126 VHDL 4 55 4 67 simulator resolution returning as a real 4 68 sizetf callback function 5 119 sm_entity 14 355 SmartModels creating foreign architectures with sm_entity 14 355 invoking SmartModel specific commands 14 358 Imcwin commands 14 359 memory arrays 14 360 Verilog interface 14 361 VHDL interface 14 354 Software upd
91. disables this default The celldefine directive only affects the PLI Access routines acc_next_cell and acc_next_cell_load R lt simargs gt This option instructs the compiler to invoke the simulator after compiling the design The compiler automatically determines which top level modules are to be simulated The command line arguments following R are passed to the simulator not the compiler Place the R option at the end of the command line or terminate the simulator command line arguments with a single character to differentiate them from compiler command line arguments The R option is not a Verilog XL option but it is used by ModelSim Verilog to combine the compile and simulate phases together as you may be used to doing with Verilog XL It is not recommended that you regularly use this option because you will incur the unnecessary overhead of compiling your design for each simulation run Mainly it is provided to ease the transition to ModelSim Verilog Verilog XL uselib compiler directive The uselib compiler directive is an alternative source library management scheme to the v y and libext compiler options It has the advantage that a design may reference different modules having the same name You compile designs that contain uselib directive statements using the compile_uselibs vlog switch described below The syntax for the uselib directive is uselib lt library_reference gt where lt libra
92. ee De Ba A a a e a ETD Verilog XL uselib compiler directive 2 2 2 5 81 A 2s Yee ae G OR eo eRe ae ee oe ee 2 ae ESE ow eS 25 84 4 Table of Contents ModelSim SE User s Manual Simulation resolution limit 2 2 ee ee 84 Event order issues E Verilog XL compatible slam options bet he hh de Soe ce e e elk i80 Compiling for faster performance s lt s e s s s s eow w ge e os a ee a 9 90 Compiling with fast we Po whe a we ae Pe eek ae 4 89290 Compiling gate level designs wiih DA YE Bie a e amp doe o e e Referencing the optimized design E A eo DOD Enabling design object visibility with the acc copio A Using pre compiled branes s e s sos p ee Re sos ee ee ee a e 4 396 Cell Lianie ceg boheme beh Ee MEE HE Re aed DA Delay modes s sns oe e ee We A a e Boe eG E oe ww O97 System Tasks gee Ge ate The Bootes Ge es cae ee ay a se ow ete Sa i SOD TEEE Std 1364 system tasks bok he A e Ake we a a 09 Verilog XL compatible system tasks a a a a ee ee ee 5 102 init signal spy o a A A a ee 25104 Compiler Directives LR A 06 IEEE Std 1364 compiler sodas Se e a as a A 06 Verilog XL compatible compiler directives 2 2 5 106 Using the Vertos PLESPI gt cossis css wor ras Bie dos amp 4 o s 5 108 Registering PLI applications s s s s poe son w no poa aoo pou a e 39 108 Registering VPI applications an ani amp doe OR 4 e e
93. enable signal to work like a One Shot that would display all values for the next say 10 ns after the rising edge of enable then set the On Duration value to 10 ns Otherwise leave it at zero and select Apply again When everything is correct click OK to close the Modify Display Properties dialog box When you save the List window configuration the list gating parameters will be saved as well and can be set up again by reading in that macro You can take a look at the macro to see how the gating can be set up using macro commands ModelSim SE User s Manual Tips and Techniques E 445 E 446 Tips and Techniques ModelSim SE User s Manual F What s new in Model Sim Appendix contents New features F 447 Command and variable changes F 448 Documentation changes F 449 GUI changes in version 5 5 F 450 ModelSim 5 5 includes many new features and enhancements that are described in the tables below Links within the groups will connect you to more detail GUI changes are described toward the end of the appendix New features What Description Where select a link Model Sim release waveform comparison compare simulations and datasets Chapter 11 Waveform Comparison 5 5 ModelSim projects projects have been completely revamped to ease getting started with ModelSim Projects and system initialization 2 25 5 5 gate level optimizations gate level Verilog designs can now be optim
94. file B 404 for additional information Invoke the Button Adder from any ModelSim window menu Window gt Customize You have the following options for adding a button button_adder Al x E Right Window Name Window Name is the name of Tool Bar the window to which you wish to add the button C Left Function Button Name is the button s eo label C Top C Bottom Function can be any command or macro you might execute from the ModelSim command line For example you might want to add a Run or Step button to the Wave window Locate the button within the window with these selections e Toolbar places the button on a new toolbar Footer adds the button to the Main window s status bar ModelSim SE User s Manual ModelSim Graphic Interface 8 269 ModelSim tools Justify the button within the menu bar toolbar with these selections e Right places the button on the right side of the menu toolbar e Left adds the button on the left side of the menu toolbar Top places the button at the top center of the menu bar or toolbar e Bottom places the button at the bottom center of the menu bar or toolbar The Macro Helper This tool is available for UNIX only excluding Linux The purpose of the Macro Helper is to aid macro creation by recording a simple series of mouse movements and key strokes The resulting file can be called from a more complex macro by using the play
95. file when a tool is invoked If the environment variables corresponding to logical pathnames have not been set in your shell ModelSim sets the variables to the first physical pathname following the logical pathname in the location map For example if you dont set the SRC environment variable ModelSim will automatically set it to home vhdl sre Mapping with Tcl variables Two Tcl variables may also be used to specify alternative source file paths SourceDir and SourceMap See http www model com resources pref_variables frameset htm E 438 Tips and Techniques ModelSim SE User s Manual Accelerate simulation by locking memory under HP UX 10 2 Accelerate simulation by locking memory under HP UX 10 2 ModelSim 5 3 and later versions contain a feature to allow HP UX 10 2 to use locked memory This feature provides significant acceleration of simulation time for large designs i e with a memory footprint gt 500Mb Test cases showed 2x acceleration of large simulations The following steps show how to set up the HP UX 10 2 so memory can be locked 1 Allow the average user to lock memory By default this privilege is not allowed so it has to be enabled To allow everyone MLOCK privileges the administrator needs to execute this command on the machine that will be running ModelSim usr sbin setprivgrp g MLOCK To only allow a particular group MLOCK privileges use the command usr sbin setprivgrp lt group name gt MLOC
96. gt c lt license_file gt f lt feature_name gt s lt server_name gt t lt value gt Arguments a Displays everything A Lists all active licenses S lt daemon gt Lists all users of the specified daemon s features c lt license_file gt Specifies that the specified license file is to be used f lt feature_name gt Lists users of the specified feature s s lt server_name gt Displays the status of the specified server node s t lt value gt Sets the Imstat time out to the specified value The Imdown utility allows for the graceful shutdown of all license daemons both Imgrd and all vendor daemons on all nodes Syntax 1mdown c lt license_file path gt D 422 Using the FLEXIm License Manager ModelSim SE User s Manual License administration tools If not supplied here the license file used is in either user local flexlm licenses license dat or the license file pathname in the environment variable LM_LICENSE_FILE B 393 The system administrator should protect the execution of Imdown since shutting down the servers will cause loss of licenses Imremove The Imremove utility allows the system administrator to remove a single user s license for a specified feature This could be required in the case where the licensed user was running the software on a node that subsequently crashed This situation will sometimes cause the license to remain unusable Imremove will allow t
97. gt 1458 112 7 6 51 IF csb 0 THEN 52 control_reg lt switch 62 when 10 buffer_txd lt txd l 63 when Ol buffer _txd lt txd 2 64 when OO buffer _txd lt txd 3 70 when 10 rxd lt l amp buffer _rxd 11 rvd antirra ols ML Y Y 4 4 04 Y Y A ModelSim SE User s Manual What s new in ModelSim F 461 F 462 What s new in ModelSim ModelSim SE User s Manual License Agreement IMPORTANT USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal Agreement concerning the use of Software between you the end user either individually or as an authorized representative of the company purchasing the license and Mentor Graphics Corporation Mentor Graphics Ireland Limited Mentor Graphics Singapore Private Limited and their majority owned subsidiaries Mentor Graphics USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within 10 days after receipt of Software and receive a full refund of any license fee paid END USER LICENSE AGREEMENT 1 GRANT OF LICENSE The software programs you are installing downloading or
98. gt Copy see Mouse and keyboard uy copy the selected text within the Source window shortcuts in the Transcript and Source windows 8 168 8 204 ModelSim Graphic Interface ModelSim SE User s Manual Source window Source window toolbar buttons Button Menu equivalent Other equivalents Paste paste the copied text to the cursor location Edit gt Paste see Mouse and keyboard shortcuts in the Transcript and Source windows 8 168 a Find find the specified text string within the source file match case option Edit gt Find lt control f gt Windows lt control s gt UNIX Step Main window use step command at the VSIM H steps the current simulation to Run gt Step prompt the next HDL statement see step CR 187 command Step Over Main window use the step over command at the pp HDL statements are executed but Run gt Step Over VSIM prompt treated as simple statements instead of entered and traced line by line see step CR 187 command Setting file line breakpoints You can set breakpoints three different ways e Using the command line see the bp CR 48 breakpoint command for details e Using your mouse in the Source window e Using the Edit gt Breakpoints menu selection Setting breakpoints with your mouse To set a breakpoint with your mouse click on a green line number at the left side of the window breakpoints
99. have acquired with this Agreement including any updates modifications revisions copies and documentation Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement Mentor Graphics or its authorized distributor grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your internal business purposes and c on the computer hardware or at the site for which an applicable license fee is paid or as authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics then current standard policies which vary depending on Software license fees paid or service plan purchased apply to the following and are subject to change a relocation of Software b use of Software which may be limited for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be communicated and technically implemented through the use of authorization codes or similar devices c eligibility to receive updates modifications and revisions and d support services provided Current standard policies are available upon request 2 ESD SOFTWARE If you purchased a license
100. if another application uses FLEXIm D 419 Format of the license file D 420 Format of the daemon options file D 420 License administration tools D 422 Imstat 2 ee ee D422 Imdown a D422 Imremove o mo meee a des D 423 Imreread o D423 Administration tools for Windows a D 423 This appendix covers Model Technology s application of FLEXIm for ModelSim licensing Globetrotter Software s Flexible License Manager FLEXIm is a network floating licensing package that allows the application to be licensed on a concurrent usage basis as well as on a per computer basis FLEXIm user s manual The content of this appendix is limited to the use of FLEXIm with Model Technology s software For more information see the FLEXIm user s manual that is available from Globetrotter Software s web site http www globetrotter com manual htm ModelSim SE User s Manual Using the FLEXIm License Manager D 417 Starting the license server daemon Starting the license server daemon Locating the license file When the license manager daemon is started 1t must be able to find the license file The default location is usr local flexlm licenses license dat for Unix or c flexlm icense dat for Windows You can change where the daemon looks for the license file using one of two methods e By starting the license manager using the c lt
101. in INI files 2 2 B 396 Library library path variables 2 a a a B 396 vcom VHDL compiler control variables 2 2 B 39 vlog Verilog compiler control variables 2 2 ee B 398 vsim simulator control variables 2 ee ee ee eee B 398 Imc Logic Modeling variables 2 a ee B 402 Setting variables in INI files pea a sa 4 B402 Reading variable values from the INI file DA a a B 402 Vanable TUOCHORS s s eo o a a a a 403 Preference variables located in TCL files B 406 User defined variables os sooo co sa soso moo aomas ac aa s o a B 406 ModelSim SE User s Manual Table of Contents 11 More preferences o s c s c ma s mota we a aaa B 406 Preference variable loading order 2 a a a a eee ee ee B 407 Simulator state variables aeus ees MS a Ge G Aeus es BE ea ke oe e a B408 Referencing simulator state variables e aba BE aS Ede e ed ods A a B408 C ModelSim Shortcuts C 409 Wave window mouse and keyboard shortcuts o a u a a a aa C410 List window keyboard shortcuts a a a a aa C 411 Command SHOUTS s o es oa a a ee ee ee a COA Command history shortcuts toe ee ew C 412 Mouse and keyboard shortcuts in the Transcript and Source windows ee ee oe ee CATB Richt mouse button lt lt o s coso r e woe ee ae e 4 CATS D
102. ini file to set a permanent default Iteration Limit Sets a limit on the number of deltas within the same simulation time unit to prevent infinite looping Edit the IterationLimit B 399 variable in the modelsim ini file to set a permanent iteration limit default Default Force Type Selects the default force type for the current simulation Edit the DefaultForceKind B 399 variable in the modelsim ini file to set a permanent default Assertion settings page M Simulation Options L L L LI The Assertions page includes these options e Break on Assertion Selects the assertion severity that will stop simulation Edit the BreakOnAssertion B 398 variable in the modelsim ini file to set a permanent default 8 266 ModelSim Graphic Interface ModelSim SE User s Manual Simulating with the graphic interface Ignore Assertions For Selects the assertion type to ignore for the current simulation Multiple selections are possible Edit the IgnoreFailure IgnoreError Ignore Warning and IgnoreNote B 399 variables in the modelsim ini file to set permanent defaults When an assertion type is ignored no message will be printed nor will the simulation halt even if break on assertion is set for that type gt Note Assertions that appear within an instantiation or configuration port map clause conversion function will not stop the simulation regardless of the severity level of the assertion WLF settings page
103. listed above for Unix ModelSim SE User s Manual Using the FLEXIm License Manager D 423 D 424 Using the FLEXIm License Manager ModelSim SE User s Manual E Tips and Techniques Appendix contents How to use checkpoint restore E 426 Running command line and batch mode simulations E 428 Using macros DO files ee a E 430 Command line mode E 430 Source code security and nodebug E433 Saving and viewing waveforms E434 Setting up libraries for group use E434 Maintaining 32 bit and 64 bit modules inthe same library E 434 Bus contention checking 1 E435 Bus float checking 2 2 2 E435 Design stability checking E436 Toggle checking s o e p pl p a 436 Detecting infinite zero delay loops E436 Referencing source files with location maps E437 Accelerate simulation by locking memory under HP UX 102 E 439 Modeling memory in VHDL E440 Setting up a List trigger with Expression Builder E 444 This appendix contains various tips and techniques collected from several parts of the manual and from answers to questions received by tech support Your suggestions tips and techniques for this section would be appreciated ModelSim SE User s Manual Tips and
104. manual only describes details of using the PLI VPI with ModelSim Verilog Registering PLI applications Each PLI application must register its system tasks and functions with the simulator providing the name of each system task and function and the associated callback routines Since many PLI applications already interface to Verilog XL ModelSim Verilog PLI applications make use of the same mechanism to register information about each system task and function in an array of s_tfcell structures This structure is declared in the veriuser h include file as follows typedef int p_tffn typedef struct t_tfcell short type USERTASK USERFUNCTION or USERREALFUNCTION short data passed as data argument of callback function p_tffn checktf argument checking callback function p_tffn sizetf function return size callback function p_tffn calltf task or function call callback function p_tffn misctf miscellaneous reason callback function char tfname name of system task or function The following fields are ignored by ModelSim Verilog int forwref char tfveritool char tferrmessage int hash struct t_tfcell left_p struct t_tfcell right_p char namecell_p int warning_printed s_tfcell p_tfcell The various callback functions checktf sizetf calltf and misctf are described in detail in the IEEE Std 1364 The simulator calls these functions for various reasons All callba
105. nets and registers declared in the region in which the process is located 8 190 ModelSim Graphic Interface ModelSim SE User s Manual Process window The Process window menu bar The following menu commands are available from the Process window menu bar File menu Save As save the process tree to a text file viewable with the ModelSim notepad CR 141 Environment Follow Context Selection update the window based on the selection in the Structure window 8 210 Fix to Current Context maintain the current view do not update Close close this copy of the Process window you can create a new window with View gt New from the The Main window menu bar 8 160 Edit menu Copy copy the selected process full name Sort sort the process list in either ascending descending or declaration order Select All select all processes in the Process window Unselect All deselect all processes in the Process window Find find the specified text string within the process list choose the Status ready wait or done the Process label or the path to search and the search direction down or up View menu Active display all the processes that are scheduled to run during the current simulation cycle In Region display any processes that exist in the region that is selected in the Structure window ModelSim SE User s Manual ModelSim Graphic Interface 8 191 Process window Wind
106. none none e find the previous difference in a waveform comparison Find Next Difference none none find the next difference in a waveform comparison Find Last Difference none none 8 226 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Using Dividers Dividing lines can be placed in the pathname and values window panes by selecting File gt New Divider Wave window Dividers serve as a visual aid to signal debugging allowing you to separate signals and waveforms for easier viewing Dividing lines can be assigned any name or no name at all The default name is New Divider In the illustration below VHDL signals have been separated from Verilog signals with a Divider called Verilog Notice that the waveforms in the waveform window pane have been separated by the divider as well wave default Al Xx File Edit Cursor Zoom Compare Bookmark Format Window SUS SBR RA eX RIA E LEG ELS Jae of wy top clk 1 Hopeprw 0 7 Aoprpsub aos e cache cik Hz feache prdy Stl cache saddr 00000000 cacheshit 1111 cache i 32 cache setsel SKK D ns to 938 ns After you have added a divider you can move it change its properties name and size or delete it To move a divider Click and drag the divider to the location you want To change a divider s name and size Click the divider with the right Windows or third UNIX mouse button and select Di
107. number on which you want to set the breakpoint Required Condition The condition s that determine whether the breakpoint is hit See the bp command CR 48 for more information on creating the condition statement Instance Specify a region in which the breakpoint should be set If left blank the breakpoint affects every instance in the design Command s One or more commands that you want executed at the breakpoint ModelSim SE User s Manual ModelSim Graphic Interface 8 207 Source window Editing the source file in the Source window Several toolbar buttons shown above mouse actions and special keystrokes can be used to edit the source file in the Source window See Mouse and keyboard shortcuts in the Transcript and Source windows 8 168 for a list of mouse and keyboard editing options Checking HDL item values and descriptions There are two quick methods to determine the value and description of an HDL item displayed in the Source window e select an item then chose Object gt Examine or Object gt Description from the Source window menu e select an item with the right mouse button to see an examine pop up select now to examine the current simulation time in VHDL code You can also invoke the examine CR 115 and or describe CR 100 command on the command line or in a macro Finding and replacing in the Source window The Find dialog box allows you to find and replace text strings or regular express
108. of the modules referenced in a design then you must instruct the compiler to search libraries for the precompiled modules The compiler optimizes pre compiled modules the same as if the source code is available The optimized code for a pre compiled module is written to the same library in which the module is found The compiler automatically searches libraries specified in the uselib directive see Verilog XL uselib compiler directive 5 81 If your design exclusively uses uselib directives to reference modules in other libraries then you don t need to specify library search options to the compiler The library search options supported by the compiler are identical to those supported by the simulator e g L and Lf see Library usage 5 78 The compiler also searches the libraries in the same order as the simulator Lf libraries first followed by uselib libraries and finally L libraries However unlike the simulator the compiler does not search the work library by default gt Note The library search options you specify to the compiler must also be specified to the simulator when you simulate the design 5 96 Verilog Simulation ModelSim SE User s Manual Cell Libraries Cell Libraries Model Technology is the first Verilog simulation vendor to pass the ASIC Council s Verilog test suite and achieve the Library Tested and Approved designation from Si2 Labs This test suite is designed to ensure Verilo
109. pathname gt option e By setting the LM_LICENSE_FILE B 393 environment variable to the path of the file More information about installing ModelSim and using a license file is available in Model Technology s Start Here for ModelSim guide see Where to find our documentation 1 21 or email us at license model com Controlling the license file search Manual start By default ModelSim checks for the existence of both Model Technology and Mentor Graphics generated licenses When vsim is invoked it will first locate and use any available MTI licenses then search for MGC licenses as needed The following vsim command CR 258 switches narrow the search to exclude or include specific licenses license option Description lic_nomge excludes any MGC licenses from the search lic_nomti excludes any MTI licenses from the search lic_noqueue do not wait in license queue if no licenses are available lic_plus searches only for PLUS licenses lic_vlog searches only for VLOG licenses lic_vhdl searches only for VHDL licenses lic_viewsim accepts a simulator license rather than being queued for a viewer license The options may also be specified with the License B 400 variable in the modelsim ini file see the vsim simulator control variables B 398 Note that settings made from the command line are additive to options set in the License variable For example if you set the License variable
110. ram storage can be shared between multiple processes For example a second process is shown that initializes the memory you could add other processes to create a multi ported memory To implement this model you will need functions that convert vectors to integers To use 1t you will probably need to convert integers to vectors Example functions are provided below in package conversions use std standard all library ieee use ieee std_logic_1164 all use work conversions all entity memory is generic add_bits integer 12 data_bits integer 32 port add_in in std_ulogic_vector add_bits 1 downto 0 data_in in std_ulogic_vector data_bits 1 downto 0 data_out out std_ulogic_vector data_bits 1 downto 0 cs mwrite in std_ulogic do_init in std_ulogic subtype word is std_ulogic_vector data_bits 1 downto 0 constant nwords integer 2 add_bits type ram_type is array 0 to nwords 1 of word end architecture style_93 of memory is E 440 Tips and Techniques ModelSim SE User s Manual Modeling memory in VHDL begin memory process cs variable address natural begin if rising_edge cs then address sulv_to_natural add_in if mwrite 1 then ram address data_in data_out lt ram address else data_out lt ram address end if end if end process memory illustrates a second process using the shared variable initialize process do_init variable
111. region 11 311 reload 11 321 rules 11 321 run 11 319 save differences 11 320 show differences 11 320 signal options 11 308 specify dataset 11 305 specify when expression 11 310 start 11 318 startup wizard 11 318 tab 11 306 test dataset 11 305 test region 11 311 timing differences 11 317 tolerance 11 310 11 313 tolerances 11 303 values 11 317 verilog matching 11 314 ModelSim SE User s Manual Index 469 VHDL matching 11 314 wave window display 11 316 waveforms 11 301 write report 11 320 compare by region 11 311 compare commands 11 323 compare simulations 7 137 compare waveforms 7 137 8 228 comparison modes 11 303 comparison wizard 11 318 Compilation and Simulation Verilog 5 73 5 126 VHDL 4 55 4 67 Compiler directives 5 106 IEEE Std 1364 2000 5 106 XL compatible compiler directives 5 106 Compiling invoking the VHDL compiler 4 57 locating source errors 8 251 setting default options 8 252 setting options in projects 2 35 setting order in projects 2 34 Verilog incremental compilation 5 76 optimizing performance 5 90 XL uselib compiler directive 5 81 XL compatible options 5 79 Verilog compile options 8 254 VHDL 4 57 VHDL compile options 8 252 with the graphic interface 8 250 with VITAL packages 4 67 Component declaration generating VHDL from Verilog 6 134 with vgencomp 6 134 Concatenation of signals 7 147 ConcurrentFileLimit ini file variable B 399 configuration simulator state variable
112. sequences that are handled specially along with the value that replaces each sequence a Audible alert bell 0x7 b Backspace 0x8 f Form feed Oxc n Newline Oxa Vr Carriage return 0xd t Tab 0x9 v Vertical tab Oxb lt newline gt whiteSpace A single space character replaces the backslash newline and all spaces and tabs after the newline This backslash sequence is unique in that it is replaced in a separate pre pass before the command is actually parsed This means that it will be replaced even when it occurs between braces and the resulting space will be treated as a word separator if it isn t in braces or quotes Backslash ModelSim SE User s Manual Tcl and ModelSim 16 373 Tcl commands Vooo The digits ooo one two or three of them give the octal value of the character xhh The hexadecimal digits hh give the hexadecimal value of the character Any number of digits may be present Backslash substitution is not performed on words enclosed in braces except for backslash newline as described above 9 Ifa hash character appears at a point where Tcl is expecting the first character of the first word of a command then the hash character and the characters that follow it up through the next newline are treated as a comment and ignored The comment character only has significance when it appears at the beginning of a c
113. shell around the WRITE procedure that solves the overloading problem For further details refer to the WRITE_STRING procedure in the 10_utils package which is located in the file modeltech examples io_utils vhd 4 62 VHDL Simulation ModelSim SE User s Manual TextlO implementation issues Reading and writing hexadecimal numbers The reading and writing of hexadecimal numbers is not specified in standard VHDL The Issues Screening and Analysis Committee of the VHDL Analysis and Standardization Group ISAC VASG has specified that the TextIO package reads and writes only decimal numbers To expand this functionality ModelSim supplies hexadecimal routines in the package 10_utils which is located in the file modeltech examples io_utils vhd To use these routines compile the io_utils package and then include the following use clauses in your VHDL source code use std textio all use work io_utils all Dangling pointers Dangling pointers are easily created when using the TextIO package because WRITELINE de allocates the access type pointer that is passed to it Following are examples of good and bad VHDL coding styles Bad VHDL because L1 and L2 both point to the same buffer READLINE infile L1 Read and allocate buffer L2 Ll Copy pointers WRITELINE outfile L1 Deallocate buffer Good VHDL because L1 and L2 point to different buffers READLINE infile L1 Read and allocate buffer
114. should understand Tcl command syntax before using these commands The syntax especially for the if command may be unfamiliar The following rules define the syntax and semantics of the Tcl language Details on if command syntax 16 374 and set command syntax 16 375 follow the general discussion of Tcl command syntax 1 A Tcl script is a string containing one or more commands Semi colons and newlines are command separators unless quoted as described below Close brackets are command terminators during command substitution see below unless quoted 2 A command is evaluated in two steps First the Tcl interpreter breaks the command into words and performs substitutions as described below These substitutions are performed in the same way for all commands The first word is used to locate a command procedure to carry out the command then all of the words of the command are passed to the command procedure The command procedure is free to interpret each of its words in any way it likes such as an integer variable name list or Tcl script Different commands interpret their words differently 3 Words of a command are separated by white space except for newlines which are command separators 4 Ifthe first character of a word is double quote then the word is terminated by the next double quote character If semi colons close brackets or white space characters including newlines appear between the quotes then they are treated
115. software based on entries in the modelsim ini initialization file The simulator and the hm_entity tool for creating foreign architectures both depend on these entries being set correctly These entries are found under the Imc section of the default modelsim ini file located in the ModelSim installation directory The default settings are as follows 1mc ModelSim s interface to Logic Modeling s hardware modeler SFI software libhm MODEL_TECH libhm sl ModelSim s interface to Logic Modeling s hardware modeler SFI software Windows NT libhm SMODEL_TECH libhm dl1 Logic Modeling s hardware modeler SFI software HP 9000 Series 700 libsfi lt sfi_dir gt lib hp700 libsfi sl Logic Modeling s hardware modeler SFI software IBM RISC System 6000 libsfi lt sfi_dir gt lib rs6000 libsfi a Logic Modeling s hardware modeler SFI software Sun4 Solaris libsfi lt sfi_dir gt lib sun4 solaris libsfi so Logic Modeling s hardware modeler SFI software Window NT libsfi lt sfi_dir gt lib pcent lm_sfi dll The libhm entry points to the ModelSim dynamic link library that interfaces the foreign architecture to the hardware modeler software The libsfi entry points to the Logic Modeling dynamic link library software that accesses the hardware modeler The simulator automatically loads both the libhm and libsfi libraries when it elaborates a hardware model foreign architecture By default the libhm
116. spec gt Meaning Enable access to registers including memories integer time and real types Enable access to nets Enable access to individual bits of vector nets This is necessary for PLI applications that require handles to individual bits of vector nets Also some user interface commands require this access if you need to operate on net bits Enable access to ports This disables the module inlining optimization and should be used for PLI applications that require access to port handles or for debugging see below Enable access to library cells By default any Verilog module bracketed with a celldefine endcelldefine may be optimized and debug and PLI access may be limited This option keeps module cell visibility If lt spec gt is omitted then access is enabled for all objects lt module gt is a module name optionally followed by to indicate all children of the module Multiple modules are allowed each separated by a If no modules are specified then all modules are affected If your design uses PLI applications that look for object handles in the design hierarchy then it is likely that you will need to use the acc option For example the built in dumpvars system task is an internal PLI application that requires handles to nets and registers so that it can call the PLI routine acc_vcl_add to monitor changes and dump the values to a VCD file This requires that access is
117. system initialization file allows you to specify a command or a do file that is to be executed after the design is loaded For example VSIM Startup command Startup do mystartup do The line shown above instructs ModelSim to execute the commands in the macro file named mystartup do VSIM Startup command Startup run all The line shown above instructs VSIM to run until there are no events scheduled See the do command CR 104 for additional information on creating do files Turning off assertion messages You can turn off assertion messages from your VHDL code by setting a switch in the modelsim ini file This option was added because some utility packages print a huge number of warnings vsim IgnoreNote 1 IgnoreWarning IgnoreError IPod IgnoreFailure Messages may also be turned off with Tcl variables see Preference variables located in TCL files B 406 Turning off warnings from arithmetic packages You can disable warnings from the synopsys and numeric standard packages by adding the following lines to the vsim section of the modelsim ini file vsim NumericStdNoWarnings I StdArithNoWarnings 1 Warnings may also be turned off with Tcl variables see Preference variables located in TCL files B 406 Force command defaults The force command has freeze drive and deposit options When none of these is specified then freeze is assumed for unresolved signals and drive is assumed f
118. test region of a different name Clocks Opens the Comparison Clocks dialog box page 11 308 and allows you to define clocks to be used in the comparison Options Opens the Add Signal Options dialog box page 11 314 which allows you to define a number of waveform comparison options ModelSim SE User s Manual Waveform Comparison 11 319 Graphical Interface to Waveform Comparison e Differences wave default File Edit Cursor Zoom MO ES Bookmark Format Window i a 5 S i Es f Start Comparison El i Ja Comparison Wizard Run Comparison RS End Comparison compare test_co A Add Differences Rules Reload Write Report Clear Clears all differences from the Wave window and resets the waveform comparison function It is equivalent to the compare reset command CR 79 Show Displays the difference in text format in the transcript area of the Main window It is equivalent to the compare info command CR 73 Save Opens the Specify Differences File dialog box where you can save the differences to a file that can be reloaded later in ModelSim The default file name is compare dif Write Report Saves a report of the differences to a text file that you can view 11 320 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison e Rules Za Start Comparison ell El El EN Ja i Comparison Wizard Run Comparison ES Eng Comp
119. that has only an interactive command line no interactive windows are opened To run vsim in this manner invoke it with the e option as the first argument from either the UNIX prompt or the DOS prompt in Windows 95 98 2000 NT Batch mode Batch mode is an operational mode that provides neither an interactive command line nor interactive windows In a UNIX environment vsim can be invoked in batch mode by redirecting standard input using the here document technique Batch mode does not require the c option In a Windows environment vsim is run from a Windows 95 98 2000 NT DOS prompt and standard input and output are re directed to and from files An example is vsim ent arch lt lt log r run 100 do test do quit f 1 Here is another example of batch mode this time using a file as input vsim counter lt yourfile From a user s point of view command line mode can look like batch mode if you use the vsim command CR 258 with the do option to execute a macro that does a quit f CR 165 before returning or if the startup do macro does a quit f before returning But technically that mode of operation is still command line mode because stdin is still operating from the terminal The following paragraphs describe the behavior defined for the batch and command line modes Command line mode In command line mode ModelSim executes any startup command specified by the Startup B 400 variable in the modelsim ini file
120. the coverage statistics You can create the filter file in any text editor or save the current filter in the coverage_source window by selecting File gt Save gt Current Filter To load the filter during a future analysis select File gt Open gt Load a New Filter Syntax lt filename gt lt range gt lt line gt all Arguments lt filename gt The name of the file you want to exclude Required The filter file may include an unlimited number of filename entries each on its own line lt range gt A range of line numbers you want to exclude Optional Enter the range in format For example 32 35 You can specify multiple ranges separated by spaces lt line gt z A line number that you want to exclude Optional You can specify multiple line numbers separated by spaces all Specifies that all lines in the file should be excluded Required if a range or line number is not specified Example control vhd 72 76 84 93 testring vhd all Default filter file The Tcl preference variable PrefCoverage pref_InitFilterFrom specifies a default filter file and path to read when a design is loaded with the coverage switch By default this variable is set to Exclude cov See Code Coverage preference variables 10 300 for details on changing this variable ModelSim SE User s Manual Code Coverage 10 299 Code Coverage preference variables Code Coverage preference variables Various Tel variables cont
121. the Find Find in structure field Specify whether you are looking for an Find Find Next Direction Close Instance Entity Module or Field Architecture Also Instance specify which direction ee Down to search Check Auto Entity Module C Up Wrap to have vie Architecture search continue at the Y Auto Wrap top of the window 8 212 ModelSim Graphic Interface ModelSim SE User s Manual Variables window Variables window The Variables window is divided into two window panes The left pane lists the names of HDL items within the current process The right pane lists the current value s associated with each name The pathname of the current process is displayed at the bottom of the window The internal variables of your design can remain hidden if you wish see Source code security and nodebug E 433 HDL items you can view FX variables The following HDL items for pem VHDL and Verilog are viewable within the Variables window cache verbose 1 VHDL items sdata_r 0000000000000100 constants generics and variables pdata_r 2222222222222222 saddr_r 00000100 Verilog items SII sstrb_r prdy_r oen register variables The names of any VHDL composite types arrays and record types are shown in a hierarchical fashion Hierarchy also applies to Verilog vector memories Verilog vector registers do not have hierarchy because they are not internally represented as
122. the Main window transcript file 8 159 Save Transcript As save the current contents of the transcript window to a file Clear Transcript clear the Main window transcript display Options all options are set for the current session only Transcript File set a transcript file to save for this session only Command History file for saving command history only no comments Save File set filename for Save Transcript and Save Transcript As Saved Lines limit the number of lines saved in the transcript default is 5000 Line Prefix specify the comment prefix for the transcript Update Rate specify the update frequency for the Main status bar ModelSim Prompt change the title of the ModelSim prompt VSIM Prompt change the title of the VSIM prompt Paused Prompt change the title of the Paused prompt lt path list gt a list of the most recent working directory changes Quit quit ModelSim 8 160 ModelSim Graphic Interface ModelSim SE User s Manual Main window Edit menu Copy copy the selected text Paste paste the previously cut or copied text to the left of the currently selected text Select All select all text in the Main window transcript Unselect All deselect all text in the Main window transcript Find search the transcript forward or backward for the specified text string Breakpoints open the Breakpoints dialog box see Setting file line breakpoin
123. the currently selected region are displayed Each HDL item in the scrollbox is preceded by one of the following EE process indicators File Edit View Window e lt Ready gt lt Wwaib HASSIGNH113 Indicates that the process is wait HASSIGNH112 scheduled to be executed within Wai HALWAYSH144 the current delta time lt Done gt HIMPLICITWIRE wen 3 e lt Wait gt lt Done gt IMPLICIT WIRE oen 3 Indicates that the process is lt Done gt IMPLICIT WIRE wen 2 waiting for a VHDL signal or lt Done gt HIMPLICITAWIRE oen 2 Verilog net or variable to change lt Done gt HIMPLICITWIRE wen 1 or for a specified time out period lt Done gt Indicates that the process has executed a VHDL wait statement without a time out or a sensitivity list The process will not restart during the current simulation run If you select a Ready process it will be executed next by the simulator When you click on a process in the Process window the following windows are updated Window updated Result Structure window 8 210 shows the region in which the process is located Variables window 8 213 shows the VHDL variables and Verilog register variables in the process Source window 8 201 shows the associated source code Dataflow window 8 171 shows the process the signals nets and registers the process reads and the signals nets and registers driven by the process Source window 8 201 shows the signals
124. two steps to map your files 1 Set the environment variable MGC_LOCATION_MAP to the path to your location map file 2 Specify the mappings from physical pathnames to logical pathnames SRC home vhdl src usr vhdl sre SIEEE usr modeltech ieee ModelSim SE User s Manual Tips and Techniques E 437 Referencing source files with location maps Pathname syntax The logical pathnames must begin with and the physical pathnames must begin with The logical pathname is followed by one or more equivalent physical pathnames Physical pathnames are equivalent if they refer to the same physical directory they just have different pathnames on different systems How location mapping works When a pathname is stored an attempt is made to map the physical pathname to a path relative to a logical pathname This is done by searching the location map file for the first physical pathname that is a prefix to the pathname in question The logical pathname is then substituted for the prefix For example usr vhdl src test vhd is mapped to SRC test vhd If a mapping can be made to a logical pathname then this is the pathname that is saved The path to a source file entry for a design unit in a library is a good example of a typical mapping For mapping from a logical pathname back to the physical pathname ModelSim expects an environment variable to be set for each logical pathname with the same name ModelSim reads the location map
125. util all entity top is end architecture signal top_sigl std_logic begin spy_process process begin init signal_spy topfuut instl sigl top sigl 1 wait end process spy_process end In this example the value of top uut inst1 sigi will be mirrored onto top_sigl to_real to_real converts the physical type time value into a real value with respect to the current simulator resolution The precision of the converted value is determined by the simulator resolution For example if you were converting 1900 fs to a real and the simulator resolution was ps then the real value would be 2 0 i e 2 ps Syntax realval to_real timeval Returns Name Description realval The time value represented as a real with respect to the simulator resolution Arguments Name Description timeval The value of the physical type time Related functions get_resolution 4 68 to_time 4 71 Example 4 70 VHDL Simulation ModelSim SE User s Manual Util package to_time If the simulator resolution is set to ps and you enter the following function realval to_real 12 99 ns then the value returned to realval would be 12990 0 If you wanted the returned value to be in units of nanoseconds ns instead you would use the get_resolution 4 68 function to recalculate the value realval le 9 to_real 12 99 ns get_resolution If you wanted the retu
126. vpi mixedHDL a max wif profiler Ef min wif projects a typ wif tcl_tutorial File name min wif Files of type Log Files w1f y Cancel Once the Reference and Test Datasets have been specified clicking OK in the Compare Dataset dialog box will place a Compare tab in the project pane of the Main window After adding the signals regions and or clocks you want to use in the comparison see Adding Signals Regions and or Clocks 11 307 you ll be able to drag compare objects from this project tab into the Wave and List windows l ModelSim File Edit Design View Project Aun Compare Macro Options Window Help ee Ba E OTHE AP xi WSIM 3 gt add list D ModelT ech_5 5_110600 examples max wif opened as dataset max j WSIM 4 gt add wave WSIM 5 gt add list compare open min max VSIM 7 gt max Atst_pseudo 4 11 306 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison Adding Signals Regions and or Clocks To designate the signals regions and or clocks to be used in the comparison click Compare gt Add in the Main or Wave window then make a selection Compare by Signal 11 307 Compare by Region 11 311 Clocks from the popup menu wave default E e Bookmark Format Window Compare by Signal Clicking Compare gt Add gt Compare by Signal in the Wave window opens the structure_browser window where you can s
127. whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LOANED TO YOU FOR A LIMITED TERM OR AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS OR IMPLIED WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 6 LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE STATUTE OR REGULATION IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR AN
128. with a process selected in the center of the window Source window 8 201 Structure window 8 210 Variables window 8 213 Process window 8 190 Dataflow window 8 171 Signals window 8 193 Structure window 8 210 Variables window 8 213 Signals window 8 193 Dataflow window 8 171 Structure window 8 210 Process window 8 190 Signals window 8 193 Source window 8 201 Finding names searching for values and locating cursors Find HDL item names with the Edit gt Find menu selection in these windows List Process Signals Source Structure Variables and Wave windows Search for HDL item values with the Edit gt Search menu selection in these windows List and Wave windows You can also Locate time markers in the List window with the Markers gt Goto menu selection e Locate time cursors in the Wave window with the Cursor gt Goto menu selection In addition to the menu selections above the virtual event lt lt Find gt gt is defined for all windows The default binding is to lt Key F19 gt in most windows the Find key on a Sun keyboard You can bind lt lt Find gt gt to other events with the Tcl Tk command event add For example event add lt lt Find gt gt lt control Key F gt ModelSim SE User s Manual ModelSim Graphic Interface 8 153 Common window features Sorting HDL items Use t
129. with bookmarks 8 241 with the mouse 8 241 ModelSim SE User s Manual Index 479 ModelSim SE User s Manual Index 480
130. you to specify which s HDL items are shown in the Signals window Multiple options Filter Ol x can be selected Input Ports Dutput Ports InQut Ports Internal Signals ModelSim SE User s Manual ModelSim Graphic Interface 8 195 Signals window Forcing signal and net values The Edit gt Force command displays a dialog box that allows you to apply stimulus to the selected signal or net Multiple signals can be selected and forced the force dialog box remains open until all of the signals are either forced skipped or you close the dialog box To cancel a force command use the Edit gt NoForce command See also the force command CR 121 Force Selected Signal Signal Name HTA Vauel 0 Kind Freeze Drive Deposit Delay For 0 Cancel After OK Cancel The Force dialog box includes these options e Signal Name Specifies the signal or net for the applied stimulus Value Initially displays the current value which can be changed by entering a new value into the field A value can be specified in radixes other than decimal by using the form for VHDL and Verilog respectively base value or blol d h value 16 EE or h EE for example specifies the hexadecimal value EE Kind Freeze Freezes the signal or net at the specified value until it is forced again or until it is unforced with a noforce command CR 138 Freeze is the default for Verilog nets and unresolved VHDL signa
131. 0000000000010 0 1 0 00000010 OL PS list E File Edit Markers Prop Window ns top clkk top pdata y top sdata top pry y top stw Signal values are ftop pstb Hop sstib y listed in decimal top prdy y top stdy y format top paddr ftop saddr y 500 0 III 2 mn E Z 505 0 MOI ama 2 520 0 OUR ele zudi E 2 540 0 E 20i E 2 560 0 Dial E 7A q a e 2 580 0 Wa E Mi E 2 585 0 VI E ai q Ww 2 2 Aon 0 AAN ee 2 In the first List window the HDL items are formatted as symbolic and use an item change to trigger a line the field width was changed to accommodate the default label width The window divider maintains the time and delta in the left pane signals in the right pane can be viewed by scrolling For the second listing the item radix for paddr pdata saddr and sdata is now decimal 8 184 ModelSim Graphic Interface ModelSim SE User s Manual List window Finding items by name in the List window The Find dialog box allows you to search for text strings in the List window Select Edit gt Find List window to bring up the Find dialog box Enter a text string and ENT F Find it by searching Find in list Right or Left through the List window display Find Find Next Specify Name to search r de the real pathnames of the Field Direction Close C Name Right items or Label to search their assigned names see Setting List window display properties 8 178 Checking Auto Wr
132. 12 gt A 12 A13 gt A 13 A14 gt A 14 A15 gt A 15 CS gt CS 00 gt O 0 Ol gt O 1 02 gt O 2 03 gt 0 3 04 gt O 4 05 gt 0 5 06 gt 0 6 07 gt O 7 WAIT_PORT gt WAIT_PORT j Command channel The command channel is a SmartModel feature that lets you invoke SmartModel specific commands These commands are documented in the SmartModel library documentation ModelSim provides access to the Command Channel from the command line The form of a SmartModel command is imc lt instance_name gt all lt SmartModel command gt The instance_name argument is either a full hierarchical name or a relative name of a SmartModel instance A relative name is relative to the current environment setting see environment command CR 114 For example to turn timing checks off for SmartModel top ul imc top ul SetConstraints Off Use all to apply the command to all SmartModel instances For example to turn timing checks off for all SmartModel instances imc all SetConstraints Off There are also some SmartModel commands that apply globally to the current simulation session rather than to models The form of a SmartModel session command is imcsession lt SmartModel session command gt Once again consult your SmartModel library documentation for details on these commands 14 358 Logic Modeling SmartModels ModelSim SE User s Manual VHDL SmartModel interface SmartMode
133. 5 MISCELLANEOUS This Agreement contains the entire understanding between the parties relating to its subject matter and supersedes all prior or contemporaneous agreements including but not limited to any purchase order terms and conditions except valid license agreements related to the subject matter of this Agreement which are physically signed by you and an authorized agent of Mentor Graphics This Agreement may only be modified by a physically signed writing between you and an authorized agent of Mentor Graphics Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent waiver or excuse The prevailing party in any legal action regarding the subject matter of this Agreement shall be entitled to recover in addition to other relief reasonable attorneys fees and expenses Rev 03 00 ModelSim SE User s Manual License Agreement 467 468 License Agreement ModelSim SE User s Manual Index Numerics 64 bit ModelSim using with 32 bit FLI apps 5 114 A Accelerated packages 3 51 architecture simulator state variable B 408 argc simulator state variable B 408 AssertFile ini file variable B 398 AssertionFormat ini file variable B 398 Assertions selecting severity that stops simulation 8 266 B Base radix specifying in List window 8 182 Batch mode simulations E 428 E 429 bookmarks 8 241 Break on assertion 8 266 BreakOnAssertion ini file variable B 398 breakpoints d
134. 59 Using the TestlO package ss s sms Ea es ER De eR Se oe oe amp 4400 Syntax for file declaration eae oe eB ee oe ce 2 400 Using STD_INPUT and STD OUTPUT tia ModelSim S AO TextlO implementation issues E 402 Reading and writing hexadecimal situa bo GO ae he Gee i oO o Dangling pointers s e s sos ee 4263 The ENDLUNE function 2 s s sos coa wos boa aoea op a ao mas a03 The ENDFILE function E Rae e AO Using alternative input output files popia e al e a a a a 504 Providing stimulus e 64 Obtaining the VITAL specification and sourcecode 2 2 2 4 65 VITAL packages E A Gp de BL e A A AOS ModelSim VITAL compliance 2 ee ee ee 66 VITAL compliance checking 2 ee 4 66 VITAL compliance warnings La AR AA a 0 Compiling and Simulating with accelerated VITAL packages 467 UTIDACRABS o cr os Bab eee be Be A EA He amp 4668 Bel wesolubiom lt lt s amp a eos kOe A Be Se Be a AS Tit BUA BBY Pee es ee we LY BLE Oy EI ood Ba 14 amp ae 4 28469 BG FOAM ce Ge ee a RRA a ee a ee eee PAO tO TBO acar we RR eRe ee eee eee ee El 5 Verilog Simulation 5 73 Compilation hb ose dic pe es Eun pi es ee ce ee E ee ee ee OO Incremental compilation Be e ee oe Ob a od ck od doe ae 2 a 4 O Library usage Bo ae bok A Se bok Gos aoa amp es amp a DRS Verilog XL compatible compilar options PR OE
135. 70 Tcl commands 16 371 Tel command syntax ee 16 372 if command syntax 2 16 374 set command syntax 1 16 375 Command substitution 16 376 Command separator we 16 376 Multiple line commands 16 376 Evaluation order 2 1 we ee 16 376 Tcl relational expression evaluation 16 376 Variable substitution ee 6 377 System commands 2 2 16 377 List processing 2 a ee ee 16 378 ModelSim Tclcommands 2 16 378 ModelSim Tel time commands 16 379 Telexamples oo s s e so oo e so a s e 16 381 This chapter provides an overview of Tel tool command language as used with ModelSim Additional Tcl and Tk Tcl s toolkit can be found through several Tcl online references 16 370 Tcl is a scripting language for controlling and extending ModelSim Within ModelSim you can develop implementations from Tcl scripts without the use of C code Because Tcl is interpreted development is rapid you can generate and execute Tcl scripts on the fly without stopping to recompile or restart ModelSim In addition if ModelSim does not provide the command you need you can use Tcl to create your own commands ModelSim SE User s Manual Tcl and ModelSim 16 369 Tcl features within ModelSim Tcl features within ModelSim gt
136. 80 de al Under 1 q o W ESP PAS EPA B retrieve vhd 35 Lines ec mi_stel logic unsigned vhd 429 Bl store vhd 43 ieee_src mti_std_logic_unsigned hd 429 Bl control vhd 87 leee_src mti_std_logic_unsigned vhd 276 retrieve vhd 38 testring vhd 99 Bl control vhd 98 leee_src mti_std_logic_unsigned vhd 424 store hd 46 testring vhd 97 a a 2 1 1 1 1 1 1 1 l i i ODO gt GO ModelSim SE User s Manual Performance Analyzer 9 285 Interpreting the data The Ranked view can be invoked by entering view_profile_ranked The modules and code lines are ranked in order of the amount of simulation time used The two lines that are taking up most of the simulation time retrieve vhd 35 and store vhd 43 appear at the top of the list under the VHDL module that contains them Samples 6180 fz o D o e ieee_src mti_std_logic_unsigned vhd 429 67 retrieve vhd 35 44 store vhd 43 43 ieee_stc mti_std_logic_unsigned vhd 276 o 1 ieee_stc mti_std_logic_unsigned vhd 424 1 retrieve vhd 38 1 testring vhd 99 1 store vhd 46 1 testring vhd 97 1 i 2 y Interpreting the Name Field The Name Under and In fields appear in both the ranked and hierarchical views These fields are interpreted identically in both views Typically a Name consists of an HDL file and line number pair Most useful names consist of a line of VHDL or Verilog source code If you use a PLI
137. 90 8 191 8 193 8 194 8 195 8 196 8 197 8 198 8 198 8 200 8 201 8 202 8 204 8 205 8 208 8 208 8 208 8 209 8 210 8 211 8 212 8 213 8 214 8 216 8 216 8 217 8 217 8 218 8 218 8 219 8 220 8 224 8 227 8 228 8 229 8 230 8 235 8 236 8 237 8 237 8 239 ModelSim SE User s Manual Table of Contents 7 A Making cursor measurements poroko ee ee we ew 9240 Zooming changing the waveform display range o ooo o a soro ooo 0 8 240 Saving zoom range and scroll position with bookmarks 2 2 8 241 Wave window mouse and keyboard shortcuts 8244 Printing and Saving waveforms a ee eee ee 89 245 Compiling with the graphic interface 2 a a ee 8 250 Locating source errors during compilation 2 8 251 setting default compile options s s s s s see ee aop e poa popri s 09 292 Simulating with the graphic interface oa ao a eee 8 256 Design selection page o lt s ecr oaee ls ee e 027 VHDL settings Page lt oe a W we Oe Be Goby aed e 8299 Verilog settings page lt s c pos pa c ma Rew as oP eek we eg 8261 Libraries settings page lt lt be so esoe boema ok eea A e 8 262 SDF sengs page gt e s cros eop A AR as e e 8263 SDF options e A A A ee e 00204 Setting default elias ella pe Oh ke ke om a oe oe ee oe aoe er 82265 ModelSimtools gt 2 ss ee ee e
138. A5 gt A 5 A6 gt A 6 A7 gt A 7 A8 gt A 8 A9 gt A 9 A10 gt A 10 All gt A 11 A12 gt A 12 A13 gt A 13 A14 gt A 14 A15 gt A 15 CS gt CS 00 gt O 0 Ol gt O 1 02 gt O 2 03 gt 0 3 04 gt O 4 05 gt 0 5 06 gt O 6 07 gt O 7 WAIT_PORT gt W ModelSim SE User s Manual Logic Modeling Hardware Models 15 367 VHDL Hardware Model interface Hardware model commands The following simulator commands are available for hardware models Refer to the Logic Modeling documentation for details on these operations Im_vectors onloff lt instance_name gt lt filename gt Enable disable test vector logging for the specified hardware model Im_measure_timing onJoff lt instance_name gt lt filename gt Enable disable timing measurement for the specified hardware model Im_timing_checks onloff lt instance_name gt Enable disable timing checks for the specified hardware model Im_loop_patterns on off lt instance_name gt Enable disable pattern looping for the specified hardware model Im_unknowns onloff lt instance_name gt Enable disable unknown propagation for the specified hardware model 15 368 Logic Modeling Hardware Models ModelSim SE User s Manual 16 Tcl and Model Sim Chapter contents Tel features within ModelSim 16 370 Tel References lt o ce a so so o we 0 we s 16 3
139. B 408 context menus coverage_source window 10 296 described 8 154 Library page 3 45 Signal window 8 198 Structure pages 7 140 continuous comparison 11 303 11 310 convert real to time 4 71 convert time to real 4 70 coverage report command 10 300 coverage_summary window 10 292 cursors link to Dataflow window 8 171 Wave window 8 239 D Dataflow window see also Windows 8 171 Dataset Browser 7 142 datasets 7 137 11 302 managing 7 142 reference 11 305 restrict dataset prefix display 7 143 simulator time resolution 7 138 specifying for compare 11 305 test 11 305 DatasetSeparator ini file variable B 399 Default compile options 8 252 DefaultForceKind ini file variable B 399 DefaultRadix ini file variable B 399 DefaultRestartOptions ini file variable B 399 B 405 Defaults restoring B 392 Delay detecting infinite zero delay loops E 436 interconnect 5 86 modes for Verilog models 5 97 SDF files 12 325 specifying stimulus delay 8 197 DelayFileOpen ini file variable B 399 deleting library contents 3 44 Delta collapse deltas in the List window 8 179 referencing simulator iteration as a simulator state variable B 408 Delta cycles E 436 delta simulator state variable B 408 Dependent design units 4 57 Descriptions of HDL items 8 208 Design hierarchy viewing in Structure window 8 210 Design library assigning a logical name 3 47 creating 3 43 for VHDL design units 4 57 mapping search rules 3 48 resource ty
140. Command substitution is not performed on words enclosed in braces 16 372 Tcl and ModelSim ModelSim SE User s Manual Tcl commands If a word contains a dollar sign then Tcl performs variable substitution the dollar sign and the following characters are replaced in the word by the value of a variable Variable substitution may take any of the following forms name Name is the name of a scalar variable the name is terminated by any character that isnt a letter digit or underscore Sname index Name gives the name of an array variable and index gives the name of an element within that array Name must contain only letters digits and underscores Command substitutions variable substitutions and backslash substitutions are performed on the characters of index name Name is the name of a scalar variable It may contain any characters whatsoever except for close braces There may be any number of variable substitutions in a single word Variable substitution is not performed on words enclosed in braces If a backslash appears within a word then backslash substitution occurs In all cases but those described below the backslash is dropped and the following character is treated as an ordinary character and included in the word This allows characters such as double quotes close brackets and dollar signs to be included in words without triggering special processing The following table lists the backslash
141. E Copy Edit gt Copy right mouse in pathname pane gt copy the selected signal in the Copy El signal name pane 8 224 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Wave window toolbar buttons Button Menu equivalent Other options Paste paste the copied signal above another selected signal Edit gt Paste right mouse in pathname pane gt Paste a a a Add Cursor Cursor gt Add Cursor none add a cursor to the center of the waveform pane Delete Cursor Cursor gt Delete Cursor none delete the selected cursor from the window ES Find Previous Transition locate the previous signal value change for the selected signal Edit gt Search Search Reverse keyboard Shift Tab left lt arguments gt see left command CR 129 Find Next Transition locate the next signal value change for the selected signal Edit gt Search Search Forward keyboard Tab right lt arguments gt see right command CR 174 Zoom in 2x zoom in by a factor of two from the current view Zoom gt Zoom In keyboard i I or right mouse in wave pane gt Zoom In Zoom out 2x zoom out by a factor of two from current view Zoom gt Zoom Out keyboard o O or right mouse in wave pane gt Zoom Out Zoom area with mouse button 1 use the cursor to outline a zoom area Zoom gt Zoom Range keyboard r or R right mouse in wave pan
142. E User s Manual Compiling and Simulating with accelerated VITAL packages Compiling and Simulating with accelerated VITAL packages vcom CR 217 automatically recognizes that a VITAL function is being referenced from the ieee library and generates code to call the optimized built in routines Optimization occurs on two levels VITAL Level 0 optimization This is a function by function optimization It applies to all level 0 architectures and any level 1 architectures that failed level 1 optimization e VITAL Level 1 optimization Performs global optimization on a VITAL 3 0 level 1 architecture that passes the VITAL compliance checker This is the default behavior Compiler options for VITAL optimization Several vcom CR 217 options control and provide feedback on VITAL optimization 00 04 Lower the optimization to a minimum with O0 capital oh zero Optional Use this to work around bugs increase your debugging visibility on a specific cell or when you want to place breakpoints on source lines that have been optimized out Enable optimizations with O4 default debugVA Prints a confirmation if a VITAL cell was optimized or an explanation of why it was not during VITAL level 1 acceleration vital2000 Turns on acceleration for the VITAL 2000 vital_memory package ModelSim VITAL built ins will be updated in step with new releases of the VITAL packages ModelSim SE User s Manual VHDL Simulation 4 67 U
143. HDL resource libraries 2 3 50 Predefined libraries La ss IAN Alternate IEEE libraries smiplicd eR bee E VITAL 2000 library 2 2 we ee 3 51 Rebuilding supplied libraries 3 51 Regenerating your design libraries 3 51 Verilog resource libraries po ae 292 Maintaining 32 bit and 64 bit versions in th same a libeary oo 3 52 Importing FPGA libraries 2 2 7 7 we ee 8 53 VHDL contains libraries which are objects that contain compiled design units libraries are given names so they may be referenced Verilog designs simulated within ModelSim are compiled into libraries as well ModelSim SE User s Manual Design libraries 3 41 Design library contents Design library contents A design library is a directory that serves as a repository for compiled design units The design units contained in a design library consist of VHDL entities packages architectures and configurations and Verilog modules and UDPs user defined primitives The design units are classified as follows Primary design units Consist of entities package declarations configuration declarations modules and UDPs Primary design units within a given library must have unique names Secondary design units Consist of architecture bodies and package bodies Secondary design units are associated with a primary design unit Architectures by the same name can exist if they are associated with dif
144. K This allows you to lock memory No other privileges are enabled 2 Once the MLOCK privilege is enabled you merely have to modify the modelsim ini file and add the following entry to the vsim section LockedMemory lt some value gt Where lt some value gt is an integer representing the number of megabytes of memory to be locked Once this is done the memory will be locked when vsim invokes using this ini file ModelSim will not lock more memory than is available in the system The maximum memory that can be locked is system physical memory RAM 100 Mb locked memory When ModelSim locks memory other processes will not have access to it Therefore you should consider how much memory is locked on a per design basis to avoid locking more than is needed System parameters used for shared locked memory may not be set by default high enough to take full advantage of this feature in later generations of HP UX Using the sam program go to the Configurable Parameters window under Kernel Configuration There are several values that may need to be increased First enable shared memory The value for shmem should be equal to 1 Set the value for shmmax as large as possible The defaults for the values of shmmin and shmseg should be ok To change these parameters you have to rebuild the kernel and reboot ModelSim SE User s Manual Tips and Techniques E 439 Modeling memory in VHDL Modeling memory
145. MTUCKUTE ark at 23480800 ns Primary Channel al a aik Wariables ark at 29481400 ns Primary Channel laa ringrtl vhd Signals ark at 29482200 ns Primary Channel m S ark at 29483000 ns Primary Channel laa store vhd L List ark at 29484000 ns Primary Channel a testring vhd Process ark at 29484600 ns Primary Channel Wave ark at 29485000 ns Primary Channel ark at 29486600 ns Primary Channel Dataflow ark at 29487000 ns Primary Channel ark at 29487600 ns Primary Channel Datasets ark at 29488400 ns Primary Channel ee gt ark at 29489200 ns Primary Channel sele 3 DOAONINN wo DB imary Channel Hierarchical Profile Ranked Profile Source Coverage n 94 in user code Project H Tatal Run Time N Minutes Ad Seconds pS Project performance Now 30 ms Delta 4 sim test_ringbuf 4 9 284 Performance Analyzer ModelSim SE User s Manual Interpreting the data The Hierarchical view can also be invoked by entering view_profile at the VSIM prompt In the Hierarchical Profile window you can expand and collapse various levels to hide data gt that is not useful and or is cluttering the data display Click on a the box to collapse all levels beneath the entry Click on the box to expand an entry By default all levels are fully expanded In the hierarchical view below two lines retrieve vhd 35 and store vhd 43 are taking the majority of the simulation time Samples 61
146. ModelSim SE User s Manual Compiler Directives This directive specifies the default decay time to be used in trireg net declarations that do not explicitly declare a decay time The decay time can be expressed as a real or integer number or as infinite to specify that the charge never decays delay_mode_distributed This directive disables path delays in favor of distributed delays See Delay modes 5 97 for details delay_mode_path This directive sets distributed delays to zero in favor of path delays See Delay modes 5 97 for details delay_mode_unit This directive sets path delays to zero and non zero distributed delays to one time unit See Delay modes 5 97 for details delay_mode_zero This directive sets path delays and distributed delays to zero See Delay modes 5 97 for details uselib This directive is an alternative to the v y and libext source library compiler options See Verilog XL uselib compiler directive 5 81 for details The following Verilog XL compiler directives are silently ignored by ModelSim Verilog Many of these directives are irrelevant to ModelSim Verilog but may appear in code being ported from Verilog XL accelerate autoexpand_vectornets disable _portfaults enable_portfaults endprotect expand_vectornets noaccelerate noexpand_vectornets noremove_gatenames noremove_netnames nosuppress_faults protect remove_gatena
147. ModelSin SE User s Manual Version 5 5 Published 22 Feb 01 The world s most popular HDL simulator ModelSim VHDL Model Sim VLOG Model Sim LNL and Model Sim PLUS are produced by Model Technology Incorporated Unauthorized copying duplication or other reproduction is prohibited without the written consent of Model Technology The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology The program described in this manual is furnished under a license agreement and may not be used or copied except in accordance with the terms of the agreement The online documentation provided with this product may be printed by the end user The number of copies that may be printed is limited to the number of licenses purchased ModelSimis a registered trademark of Model Technology Incorporated PostScript is a registered trademark of Adobe Systems Incorporated UNIX is a registered trademark of AT amp T in the USA and other countries FLEXIm is a trademark of Globetrotter Software Inc IBM AT and PC are registered trademarks AIX and RISC System 6000 are trademarks of International Business Machines Corporation Windows Microsoft and MS DOS are registered trademarks of Microsoft Corporation OSF Motif is a trademark of the Open Software Foundation Inc in the USA and other countries SPARC is a registered trademark and SPARCstation is a trademark of SPARC Inter
148. RM errors are printed as warnings if they were considered errors they would prevent VITAL level 1 acceleration they do not affect how the architecture behaves e Starting index constraint to Dataln and PreviousDataln parameters to VITALStateTable do not match 1076 4 section 6 4 3 2 2 e Size of PreviousDataln parameter is larger than the size of the Dataln parameter to VITALStateTable 1076 4 section 6 4 3 2 2 e Signal q_w is read by the VITAL process but is NOT in the sensitivity list 1076 4 section 6 4 3 The first two warnings are minor cases where the body of the VITAL 3 0 LRM is slightly stricter than the package portion of the LRM Since either interpretation will provide the same simulation results we chose to make these two cases just warnings The last warning is a relaxation of the restriction on reading an internal signal that is not in the sensitivity list This is relaxed only for the CheckEnabled parameters of the timing checks and only if it is not read elsewhere You can control the visibility of VITAL compliance check warnings in your vcom CR 217 transcript They can be suppressed by using the vcom nowarn switch as in vcom nowarn 6 The 6 comes from the warning level printed as part of the warning i e WARNING 6 You can also add the following line to your modelsim ini file in the vcom VHDL compiler control variables B 396 section vcom Show_VitalChecksWarnings 0 4 66 VHDL Simulation ModelSim S
149. Sim Graphic Interface ModelSim SE User s Manual Wave window Refresh Display clearthe Wave window empty the file cache and rebuild the window from scratch Close close this copy of the Wave window you can create a new window with View gt New from The Main window menu bar 8 160 Edit menu Cut cut the selected item and waveform from the Wave window see Editing and formatting HDL items in the Wave window 8 230 Copy copy the selected item and waveform Paste paste the previously cut or copied item above the currently selected item Delete delete the selected item and its waveform Select All select or unselect all item names in the name pane Unselect All Combine combine the selected fields into a user defined bus Signal Breakpoints add edit and delete signal breakpoints see Setting signal breakpoints 8 198 Sort sort the top level items in the name pane sort with full path name or viewed name use ascending or descending order Find find the specified item label within the pathname pane or the specified value within the value pane Search search the waveform display for a specified value or the next transition for the selected signal see Searching for item values in the Wave window 8 237 Justify Values justify values to the left or right margins of the window pane Display Properties set display properties for signal path length cursor snap distance row mar
150. Sim SE User s Manual Value Change Dump VCD Files 13 351 13 352 Value Change Dump VCD Files ModelSim SE User s Manual 14 Logic Modeling SmartModels Chapter contents VHDL SmartModel interface o 14 354 Creating foreign architectures with sm gt ent Le e a 14 395 Vector ports 2 we ee 14 357 Command channel ee 14 358 SmartModel Windows 7 we 14 359 Memory arrays 2 1 1 14 360 Verilog SmartModelinterface a 14361 LMTV usage documentation o 14 361 Linking the LMTV interface to the latas o 14 361 Compiling Verilog shells 14 361 The Logic Modeling SWIFT based SmartModel library can be used with ModelSim VHDL and Verilog The SmartModel library is a collection of behavioral models supplied in binary form with a procedural interface that is accessed by the simulator This chapter describes how to use the SmartModel library with ModelSim gt Note The SmartModel library must be obtained from Logic Modeling along with the SmartModel library documentation that describes how to use it This chapter only describes the specifics of using the library with ModelSim SE ModelSim SE User s Manual Logic Modeling SmartModels 14 353 VHDL SmartModel interface VHDL SmartModel interface ModelSim VHDL interfaces to a SmartModel through a foreign architecture The foreign architecture contains a foreign attribute string that
151. SmartModelName gt Arguments Read SmartModel names from standard input xe Do not generate entity declarations xa Do not generate architecture bodies E Generate component declarations al1 Select all models installed in the SmartModel library y Display progress messages 93 Use extended identifiers where needed lt SmartModelName gt Name of a SmartModel see the SmartModel library documentation for details on SmartModel names By default the sm_entity tool writes an entity and foreign architecture to stdout for each SmartModel name listed on the command line Optionally you can include the component declaration c exclude the entity xe and exclude the architecture xa The simplest way to prepare SmartModels for use with ModelSim VHDL is to generate the entities and foreign architectures for all installed SmartModels and compile them into a library named Imc This is easily accomplished with the following commands sm_entity all gt sml vhd vlib lmc vcom work lmc sml vhd To instantiate the SmartModels in your VHDL design you also need to generate component declarations for the SmartModels Add these component declarations to a package named sml for example and compile the package into the Imc library sm_entity all c xe xa gt smlcomp vhd Edit the resulting smlcomp vhd file to turn it into a package of SmartModel component declarations as follows library ieee u
152. T SET THIS VARIABLE MODEL_TECH_TCL used by ModelSim to find Tcl libraries for Tcl Tk 8 0 Tix and vsim defaults to modeltech tcl may be set to an alternate path MGC_LOCATION_MAP used by ModelSim tools to find source files based on easily reallocated soft paths optional see Using location mapping E 437 also see the Tcl variables SourceDir and SourceMap MODELSIM used by all ModelSim tools to find the modelsim ini file consists of a path including the file name optional An alternative use of this variable is to set it to the path of a project file lt Project_Root_Dir gt lt Project_Name gt mpf This allows you to use project settings with command line tools However if you do this the mpf file will replace modelsim ini as the initialization file for all ModelSim tools MODELSIM_TCL used by ModelSim to look for an optional graphical preference file can be a colon separated UNIX or semi colon Windows separated list of file paths MTL TF_LIMIT limits the size of the VSOUT temp file generated by the ModelSim kernel the value of the variable is the size of k bytes TMPDIR below controls the location of this file STDOUT controls the name default 10 0 no limit MTI_USELIB_DIR specifies the directory into which object libraries are compiled when using the compile_uselibs argument to the vlog command CR 250 ModelSim SE User s Manual ModelSim Variables B 393 Env
153. VPI or FLI routine then the name of the C function that implements that routine can also appear in the name field vsim is a stripped executable file so that any functions inside of it will be credited to the line of code that uses the function The hierarchical view opens with all levels displayed You can collapse the hierarchical view by clicking the boxes next to the high level names At this time the hierarchical view will not remember which levels are opened or closed when data is reloaded By default hierarchical levels are opened every time data is reloaded Interpreting the Under and In Fields The In and Under columns describe the percentage of the total simulation time spent in and under a function listed in the Name field The distinction between In and Under is subtle but important For the retrieve vhd 35 entry in the hierarchical and ranked views above Under is 44 and In is 10 Under means that this particular line and all support routines it needed took 44 of total simulation time In means that 10 of the total simulation time was actually spent executing this line of VHDL code 9 286 Performance Analyzer ModelSim SE User s Manual Interpreting the data In the body of the Hierarchical Profile or Ranked Profile windows you can double click on any VHDL Verilog file and line number pair to bring up that file in the Source Window with the selected line highlighted In the diagram b
154. Verilog LMTV interface To install this option you must select the simulator type Verilog when you run Logic Modeling s SmartInstall program LMTV usage documentation The SmartModel Library Simulator Interface Manual is installed with Logic Modeling s software Look for the file lt LMC_install_dir gt doc smartmodel manuals slim pdf This document is written with Cadence Verilog in mind but mostly applies to ModelSim Verilog Make sure you follow the instructions below for linking the LMTV interface to the simulator Linking the LMTV interface to the simulator Model Technology ships a dynamically loadable library that links ModelSim to the LMTV interface To link to the LMTV all you need to do is add libswiftpli sl to the Veriuser line in modelsim ini as in the example below Veriuser MODEL_TECH libswiftpli sl gt Note On Windows platforms the above file should be named libswiftpli dll Compiling Verilog shells Once libswiftpli sl is in the modelsim ini file you can compile the Verilog shells provided by Logic Modeling You compile them just like any other Verilog modules in ModelSim Verilog Details on the Verilog shells are in the SmartModel Library Simulator Interface Manual as well The command line plus options and LMTV system tasks described in that document also apply to ModelSim ModelSim SE User s Manual Logic Modeling SmartModels 14 361 14 362 Logic Modeling SmartModels ModelSim SE User s Manua
155. Y OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER 7 LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS LOSS COST DAMAGE EXPENSE OR LIABILITY INCLUDING ATTORNEYS FEES ARISING OUT OF OR IN CONNECTION WITH SUCH USE 8 INFRINGEMENT 8 1 Mentor Graphics will defend or settle at its option and expense any action brought against you alleging that Software infringes a patent or copyright in the United States Canada Japan Switzerland Norway Israel Egypt or the European Union Mentor Graphics will pay any costs and damages finally awarded against you that are attributable to the claim provided that you a notify Mentor ModelSim SE User s Manual License Agreement 465 Graphics promptly in writing of the action b provide Mentor Graphics all reasonable information and
156. _TECH is a special variable set by Model Technology software Its value is the name of the directory from which the VCOM compiler or VSIM simulator was invoked MODEL_TECH is used by the other Model Technology tools to find the libraries Hierarchical library mapping By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the ModelSim tools don t find a mapping in the modelsim ini file then they will search the library section of the initialization file specified by the others clause Examples Library asic_lib cae asic_lib work my_work others install_dir modeltech modelsim ini Tip Since the file referred to by the others clause may itself contain an others clause you can use this feature to chain a set of hierarchical INI files Creating a transcript file A feature in the system initialization file allows you to keep a record of everything that occurs in the transcript error messages assertions commands command outputs etc To do this set the value for the TranscriptFile line in the modelsim ini file to the name of the file in which you would like to record the ModelSim history The size of this file can be controlled with the MTI_TF_LIMIT B 393 variable Save the command window contents to this file TranscriptFile trnscrpt ModelSim SE User s Manual ModelSim Variables B 403 Preference variables located in INI files Using a startup file The
157. _Warning5 0 1 if 0 turns off multiple drivers on unresolved signal on 1 warnings VHDL93 0 1 if 1 turns on VHDL 1993 off 0 ModelSim SE User s Manual ModelSim Variables B 397 Preference variables located in INI files vlog Verilog compiler control variables Variable name Value Purpose Default range Hazard 0 1 if 1 turns on Verilog hazard checking order off 0 dependent accessing of global vars Incremental 0 1 if 1 turns on incremental compilation of modules off 0 NoDebug 0 1 if 1 turns off inclusion of debugging info within off 0 design units Quiet 0 1 if 1 turns off loading messages off 0 Show_Lint 0 1 if 1 turns on lint style checking off 0 ScalarOpts 0 1 1f 1 activates optimizations on expressions that don t off 0 involve signals waits or function procedure task invocations Show_source 0 1 1f 1 shows source line containing error off 0 UpCase 0 1 1f 1 turns on converting regular Verilog identifiersto off 0 uppercase Allows case insensitivity for module names see also Verilog XL compatible compiler options 5 79 vsim simulator control variables Variable name Value range Purpose Default AssertFile any valid alternative file for storing assertion transcript filename messages AssertionFormat see purpose sets the message to display after a break on S assertion message formats include R n Time
158. _src directory a macro file is also provided for Windows platforms rebldlibs do To rebuild the libraries invoke the DO file from within ModelSim with this command do rebldlibs do Make sure your current directory is the modeltech install directory before you run this file Shell scripts are provided for UNIX rebuild_libs csh and rebuild_libs sh To rebuild the libraries execute one of the rebuild_libs scripts while in the modeltech directory B Note Because accelerated subprograms require attributes that are available only under the 1993 standard many of the libraries are built using vcom CR 217 with the 93 option Regenerating your design libraries Depending on your current ModelSim version you may need to regenerate your design libraries before running a simulation Check the installation README file to see if your libraries require an update You can regenerate your design libraries using the Refresh command from the Library page context menu see Managing library contents 3 44 or by using the refresh argument to vcom CR 217 and vlog CR 250 From the command line you would use vcom with the refresh option to update VHDL design units in a library and vlog with the refresh option to update Verilog design units By default the work library is updated use work lt library gt to update a different library For example if you have a library named mylib that contains both VHDL and Verilog design units Mod
159. a soeone easa eaa a 10293 8 Table of Contents ModelSim SE User s Manual Exclusions tab o 10 293 The coverage_summary window menu sbar e oe e o e a i e 108294 The coverage_source window aoa ee ee a a ee ee ee 10 206 Excluding limesandfiles 2 6 moe sta eye eee 4 ee w ww 10 296 Merging coverage report files 2 p s s so spoe rore soe pooo ee ee es 10 298 Exclusion filterfiles gt 2 s o o sacr sob b ate poki omoa ee a a 10 299 Code Coverage preference variables 0 u u a a a a a a a eee ee 10 300 Code Coverage commands 2 10 300 11 Waveform Comparison 11 301 Introducing Waveform Comparison a e aa 11 302 Two Modes of Comparison Book ae Gos de gh a a ES 03 Comparing Hierarchical and Flattened Designs bok A eben Ebb we e T1304 Graphical Interface to Waveform nll oy SO eR ok oe eo ee oe Oe ee LIED Opening Dataset Comparison Oe Bes o A Ee Ge te EOS Adding Signals Regions and or Clocks gee Roe ie na OR e aa we e AE OT Setting Compare Options lt lt s ea so esa cor semas ee es 2 1314 Wave window display lt s s s e e os mie oe ee rs o D386 Printing compare differences 2 s po coa ee ee a 11 321 List window display lt lt s s pe sms pasea ra rr a a a 11322 Command line interface to Waveform Comparison 11 323 12 Standard Delay Format SDF Timing Annotation 12 325 Specifying SDF files for simulation
160. ables path pulse error warning messages e Rejection Limit pulse_r lt percent gt Sets the module path pulse rejection limit as a percentage of the path delay Error Limit pulse_e lt percent gt Sets the module path pulse error limit as a percentage of the path delay ModelSim SE User s Manual ModelSim Graphic Interface 8 261 Other Options Enable Hazard Checking hazards Enables hazard checking in Verilog modules Disable Timing Checks in Specify Blocks notimingchecks Disables the timing check system tasks setup hold in specify blocks User Defined Arguments lt plusarg gt Arguments are preceded with making them accessible through the Verilog PLI routine mc_scan_plusargs The values specified in this field must have a preceding them or ModelSim may incorrectly parse them Libraries settings page Load Design The Libraries page includes these options Search Libraries L Specifies the library to search for design units instantiated from Verilog e Search Libraries First Lf Same as Search Libraries but these libraries are searched before uselib 8 262 ModelSim Graphic Interface ModelSim SE User s Manual Simulating with the graphic interface SDF settings page Load Design Ie rey leat Dae Ea iea ea Ls tna The SDF Standard Delay Format page includes these options SDF Files The Add button opens a dialog box th
161. ace 8 229 Wave window wave default A E File Edit Cursor Zoom Compare Bookmark Format Window oS BB RA eX QQQQ EF ELEVELM Male dm top clk 0 top prw 0 top pstrb 0 ftop prdy 1 top paddr 00000010 A 0 A 00000011 top pdata LLLLLTLL LLL LZ Z HA gt HI E 7 BUSI 011 Oona aa on tor ort 4 2 top stw 0 1 top sstrb 1 O top srdy 1 top stw 0 50 ns to 928 ns Other virtual items in the Wave window See Virtual Objects User defined buses and more 7 144 for information about other virtual items viewable in the Wave window Editing and formatting HDL items in the Wave window Once you have the HDL items you want in the Wave window you can edit and format the list in the pathname and values panes to create the view you find most useful See also Setting Wave window display properties 8 235 To edit an item Select the item s label in the pathname pane or its waveform in the waveform pane Move copy or remove the item by selecting commands from the Wave window Edit menu 8 221 You can also click drag to move items within the pathnames and values panes to select several items control click to add or subtract from the selected group e to move the selected items re click and hold on one of the selected items then drag to the new location 8 230 ModelSim Graphic Interface ModelSim SE User s Manual Wave window To format an item Select
162. ace 8 241 Wave window To add a bookmark select Bookmark gt Add Bookmark Wave window Bookmark Properties wave Al x Bookmark Label example Zoom fo ns to 625 us Top Index id JV save zoom range with bookmark JV save scroll location with bookmark OK Cancel The Bookmark Properties dialog includes the following options Bookmark Label A text label to assign to the bookmark The label will identify the bookmark on the Bookmark menu Zoom A starting value and ending value that define the zoom range Top Index The item that will display at the top of the wave window For instance if you specify 15 the Wave window will be scrolled down to show the 15th item in the window Save zoom range with bookmark When checked the zoom range will be saved in the bookmark Save scroll location with bookmark When checked the scroll location will be saved in the bookmark Once the bookmark is saved select it by name from the Bookmark menu and the Wave window will be zoomed and scrolled accordingly 8 242 ModelSim Graphic Interface ModelSim SE User s Manual Wave window To edit or delete a bookmark select Bookmark gt Edit Bookmarks Wave window Bookmark Selection wave Al E example The Bookmark Selection dialog includes the following options Add bookmark add wave Add a new bookmark Modify Edit the selected bookmark Delete bookmark delete wave Delete the selected
163. address natural begin if rising_edge do_init then for address in 0 to nwords 1 loop ram address data_in end loop end if end process initialize end architecture style_93 architecture style_87 of memory is begin memory process cs variable ram ram_type variable address natural begin if rising_edge cs then address sulv_to_natural add_in if mwrite 1 then ram address data_in data_out lt ram address else data_out lt ram address end if end if end process end style_87 architecture bad_style_87 of memory is begin memory process cs variable address natural 0 begin ModelSim SE User s Manual Tips and Techniques E 441 Modeling memory in VHDL if rising_edge cs then address sulv_to_natural add_in if mwrite 1 then ram address lt data_in data_out lt data_in else data_out lt ram address end if end if end process end bad_style_87 use std standard all library ieee use ieee std_logic_1164 all package conversions is function sulv_to_natural x std_ulogic_vector return natural function natural_to_sulv n bits natural return std_ulogic_vector end conversions package body conversions is function sulv_to_natural x std_ulogic_vector return natural is variable n natural 0 variable failure boolean false begin assert x high x low 1 lt 31 report Range of sulv_to_natural argume
164. als window menu bar File menu Save As save the signals tree to a text file viewable with the ModelSim notepad CR 141 Environment allow the window contents to change based on the current environment or fix to a specific context or dataset Close close this copy of the Signals window you can create a new window with View gt New from the The Main window menu bar 8 160 Edit menu Copy copy the current selection in the Signals window Sort sort the signals tree in either ascending descending or declaration order Select All select all items in the Signals window Unselect All unselect all items in the Signals window Expand Selected expand the hierarchy of the selected items Collapse Selected collapse the hierarchy of the selected items Expand All expand the hierarchy of all items that can be expanded Collapse All collapse the hierarchy of all expanded items Force apply stimulus to the specified Signal Name specify Value Kind Freeze Drive Deposit Delay and Cancel see also the force command CR 121 Noforce remove the effect of any active force command CR 121 on the selected HDL item see also the noforce command CR 138 Clock define clock signals by Signal Name Period Duty Cycle Offset and whether the first edge is rising or falling see Defining clock signals 8 200 Justify Values justify values to the left or right margins of the window pane Find find the s
165. ample vlog top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top The most efficient method of incremental compilation is to manually compile only the modules that have changed This is not always convenient especially if your source files have compiler directive interdependencies such as macros In this case you may prefer to always compile your entire design in one invocation of the compiler If you specify the incr option the compiler will automatically determine which modules have changed and generate code only for those modules This is not as efficient as manual incremental compilation because the compiler must scan all of the source code to determine which modules must be compiled The following is an example of how to compile a design with automatic incremental compilation vlog incr top v and2 v or2 v Compiling module top Compiling module and2 Compiling module or2 Top level modules top Now suppose that you modify the functionality of the or2 module vlog incr top v and2 v or2 v Skipping module top Skipping module and2 Compiling module or2 Top level modules top The compiler informs you that it skipped the modules top and and2 and compiled or2 Automatic incremental compilation is intelligent about when to compile a module For example changing a comment in your source code does not result in a recompile how
166. and virtuals 7 137 Datasets pael a a a e Ge rs al ALAS Saving a siranlation toa adataset nh a Oe A ew A ea ee we eal et a IBS Opening datasets r A RO ee g ee we a ee Talg Viewing dataset structure ee ee eee ee ee 7 140 Managing datasets Be hehe So bok Goo bak amp ye ed IAD Using datasets with ModelSim souumande OR Gh hg RO ea BA a e SAD Restricting the dataset prefix display 2 7 143 Virtual Objects User defined buses and more 4 7 144 VUtUA SIMS o kk e ER AR a 5144 Virtual MACHONG 2 ee si ee POE Ae wee Bw a a e o EAS WUtUEITEBIONS es lt p Be Ok Re ewe ee eee ee ee FAO Vimal types 25 6265 3 84 26 Soe De a ee aE Se IEA Dataset logfile and virtualcommands 2 7 147 8 ModelSim Graphic Interface 8 149 Window overview gt s c o soe be e ee ee osaa ana ew ew ey 8150 Common window features 2 2 2 ee ee ee ee eee ee 8 151 Quick accesstoolbars a sos sos 2 eaa eee 8 2 0 89 152 Dragand Drop o sa sa Gok pop aop eH woe ee ee ee Se 8 192 Command history Uwe Se Ae E Re Be ee S O Automatic window er Hes oo hk de Uk Bee we es me 4 a 8193 Finding names searching for values aid loiig CURSOS o eie w oa ea w 8193 Sorne HDL tems s sop s soa aa a e a g a lA Multiple window copies a a a a ee ee 8 154 Contest Men s s e ecc s por a RA Ee we ew SIDA Menu tear off
167. annotator does not match the second condition above because the order of rl and r2 are reversed Rounded timing values The SDF TIMESCALE construct specifies time units of values in the SDF file The annotator rounds timing values from the SDF file to the time precision of the module that is annotated For example if the SDF TIMESCALE is Ins and a value of 016 is annotated to a path delay in a module having a time precision of 10ps from the timescale directive then the path delay receives a value of 20ps The SDF value of 16ps is rounded to 20ps Interconnect delays are rounded to the time precision of the module that contains the annotated MIPD ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 335 SDF for Mixed VHDL and Verilog Designs SDF for Mixed VHDL and Verilog Designs Annotation of a mixed VHDL and Verilog design is very flexible VHDL VITAL cells and Verilog cells can be annotated from the same SDF file This flexibility is available only by using the simulator s SDF command line options The Verilog sdf_annotate system task can annotate Verilog cells only See the vsim command CR 258 for more information on SDF command line options Interconnect delays An interconnect delay represents the delay from the output of one device to the input of another With Verilog designs ModelSim can model single interconnect delays or multisource interconnect delays See Arguments Verilog CR 265 unde
168. ap makes the search continue at the beginning of the window Note that you can change an item s label Label C Left V Auto Wrap Searching for item values in the List window Select an item in the List window Select Edit gt Search List window to bring up the List Signal Search dialog box z List Signal Search window list Signal Name s No Signals Selected Search Type C Any Transition Rising Edge C Falling Edge Search for Signal Value Value Search for Expression Expression Builder Search Options Search Forward fi Match Count Ignore Glitches Search Reverse Search Results Status Time Done ime ModelSim SE User s Manual ModelSim Graphic Interface 8 185 List window Signal Name s shows a list of the items currently selected in the List window These items are the subject of the search The search is based on these options Search Type Any Transition Searches for any transition in the selected signal s Search Type Rising Edge Searches for rising edges in the selected signal s Search Type Falling Edge Searches for falling edges in the selected signal s Search Type Search for Signal Value Searches for the value specified in the Value field the value should be formatted using VHDL or Verilog numbering conventions see Numbering conventions CR 291 B Note If your signal values are displayed in binary radix s
169. ar of the specified window ModelSim SE User s Manual ModelSim Graphic Interface 8 203 Source window lt window_name gt The Source window toolbar list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 Buttons on the Source window toolbar give you quick access to these ModelSim commands and functions i source proc File Edit O N NA go S SS SI K Kg g P Q amp S SO O 9 Ea Source window toolbar buttons Object Options Window Ssi EBA OO A eS E e Button Menu equivalent Other equivalents Compile Source File File gt Compile use vcom or vlog command at the 2 open the Compile HDL Source VSIM prompt File dialog see vcom CR 217 or vlog CR 250 command Open Source File File gt Open select an HDL item in the zy open the Open File dialog box Structure window the associated you can open any text file for source file is loaded into the editing in the Source window Source window Save Source File File gt Save none save the file in the Source window Cut Edit gt Cut see Mouse and keyboard y cut the selected text within the shortcuts in the Transcript and oe Source window Source windows 8 168 Copy Edit
170. aration of in the same package LRM Section 10 3 However if another version of the operator is declared in a different package than that containing the enumeration declaration and both operators become visible through use clauses neither can be used without explicit naming for example ARITHMETIC left right This option allows the explicit operator to hide the implicit one Disable loading messages Disables loading messages in the Main window Same as the quiet switch for the vcom command CR 217 Edit the Quiet B 397 variable in the modelsim ini file to set a permanent default Show source lines with errors Causes the compiler to display the relevant lines of code in the transcript Same as the source switch for the veom command CR 217 Edit the Show_source B 397 variable in the modelsim ini file to set a permanent default Flag Warnings on Unbound Component Flags any component instantiation in the VHDL source code that has no matching entity in a library that is referenced in the source code either directly or indirectly Edit the Show_Warningl B 397 variable in the modelsim ini file to set a permanent default Process without a WAIT statement Flags any process that does not contain a wait statement or a sensitivity list Edit the Show_Warning2 B 397 variable in the modelsim ini file to set a permanent default Null Range Flags any null range such as 0 down to 4 Edit the Show_Warning3 B 397 v
171. arg_int acc_fetch_itfarg_int acc_fetch_tfarg_str acc_fetch_itfarg_str acc_fetch_timescale_info acc_fetch_type acc_fetch_type_str acc_fetch_value acc_free acc_handle_by_name acc_handle_calling_mod_m acc_handle_ condition acc_handle_conn acc_handle_hiconn acc_handle_interactive_scope acc_handle_loconn acc_handle_modpath acc_handle_ notifier acc_handle_object acc_handle_parent acc_handle_path acc_handle_pathin acc_handle_pathout acc_handle_port acc_handle_scope acc_handle_simulated_net acc_handle_tchk acc_handle_tchkargl acc_handle_tchkarg2 acc_handle_ terminal acc_handle_tfarg acc_handle_itfarg acc_handle_tfinst acc_initialize acc_next acc_next_bit acc_next_cell acc_next_cell_load acc_next_child acc_next_driver acc_next_hiconn acc_next_input acc_next_load acc_next_loconn acc_next_modpath acc_next_net acc_next_output acc_next_parameter acc_next_port acc_next_portout 5 122 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI acc_next_primitive acc_next_scope acc_next_specparam acc_next_tchk acc_next_terminal acc_next_topmod acc_object_in_typelist acc_object_of_type acc_product_type acc_product_version acc_release_object acc_replace_delays acc_replace_pulsere acc_reset_buffer acc_set_intera
172. ariable in the modelsim ini file to set a permanent default No space in time literal e g 5ns Flags any time literal that is missing a space between the number and the time unit Edit the Show_Warning4 B 397 variable in the modelsim ini file to set a permanent default Multiple drivers on unresolved signals Flags any unresolved signals that have multiple drivers Edit the Show_Warning5 B 397 variable in the modelsim ini file to set a permanent default Check for Synthesis Turns on limited synthesis rule compliance checking Edit the CheckSynthesis B 396 variable in the modelsim ini file to set a permanent default ModelSim SE User s Manual ModelSim Graphic Interface 8 253 e Vital Compliance Toggle Vital compliance checking Edit the NoVitalCheck B 397 variable in the modelsim ini file to set a permanent default Optimize for StdLogic1164 Causes the compiler to perform special optimizations for speeding up simulation when the multi value logic package std_logic_1164 is used Unless you have modified the std_logic_1164 package this option should always be checked Edit the Optimize_1164 B 397 variable in the modelsim ini file to set a permanent default Vital Toggle acceleration of the Vital packages Edit the NoVital B 397 variable in the modelsim ini file to set a permanent default Verilog compiler options page Compiler Options Enable run time hazard checks Enables the run
173. arison E compare test_co A Add Options ales Show Displays the rules or instructions used to set up the waveform compare It is equivalent to the compare list command CR 74 Save Opens the Specify Rule File dialog box and allows you to assign a name to the file that will contain all rules for making the comparison The default file name is compare rul Reload Opens the Reload and Redisplay Compare Differences dialog box and allows you to enter or browse for waveform rules and difference file names Reload and Redisplay Compare Differences Waveform Rules file name compare rul Browse Waveform Difference file name compare di Browse Printing compare differences You can print the compare differences shown in the Wave window either to a printer or to a Postscript file See Printing and saving waveforms 8 245 for details ModelSim SE User s Manual Waveform Comparison 11 321 Graphical Interface to Waveform Comparison List window display Compare objects can be displayed in the List window too Differences are highlighted with a yellow background Tabbing on selected columns moves the selection to the next difference actually difference edge Shift tabbing moves the selection backwards PS list Iof ES File Edit Markers Prop Window ns zy ftst_pseudo storage delta ftst pseudo data ftst_pseudo cl icky ftst_pseudo expected wy
174. arrays Hierarchy is indicated in typical ModelSim fashion with plus expandable and minus expanded See Tree window hierarchical view 8 155 for more information To change the value of a VHDL variable constant or generic or a Verilog register variable move the pointer to the desired name and click to highlight the selection Select Edit gt Change Variables window to bring up a dialog box that lets you specify a new value Note that Variable Name is a term that is used loosely in this case to signify VHDL constants and generics as well as VHDL and Verilog register variables You can enter any value that is valid for the variable An array value must be specified as a string without surrounding quotation marks To modify the values in a record you need to change each field separately Click on a process in the Process window to change the Variables window ModelSim SE User s Manual ModelSim Graphic Interface 8 213 Variables window The Variables window menu bar The following menu commands are available from the Variables window menu bar File menu Save As save the variables tree to a text file viewable with the ModelSim notepad CR 141 Environment Follow Process Selection update the window based on the selection in the Process window 8 190 Fix to Current Process maintain the current view do not update Close Edit menu close this copy of the Variables window you
175. ary library path variables Variable name Value range Purpose ieee any valid path may include environment variables sets the path to the library containing IEEE and Synopsys arithmetic packages the default is modeltech ieee std any valid path may include environment variables sets the path to the VHDL STD library the default is modeltech std std_developerskit any valid path may include environment variables sets the path to the libraries for MGC standard developer s kit the default is modeltech std_developerskit synopsys any valid path may include environment variables sets the path to the accelerated arithmetic packages the default is modeltech synopsys verilog any valid path may include environment variables vcom VHDL compiler control variables sets the path to the library containing VHDL Verilog type mappings the default is modeltech verilog Variable name Value Purpose Default range CheckSynthesis 0 1 if 1 turns on limited synthesis rule compliance off 0 process checking checks only signals used read by a B 396 ModelSim Variables ModelSim SE User s Manual Preference variables located in INI files Variable name Value Purpose Default range Explicit 0 1 if 1 turns on resolving of ambiguous function on 1 overloading in fav
176. associates a specific SmartModel with the architecture On elaboration of the foreign architecture the simulator automatically loads the SmartModel library software and establishes communication with the specific SmartModel The ModelSim software locates the SmartModel interface software based on entries in the modelsim ini initialization file The simulator and the sm_entity tool for creating foreign architectures both depend on these entries being set correctly These entries are found under the Imc section of the default modelsim ini file located in the ModelSim installation directory The default settings are as follows 1mc ModelSim s interface to Logic Modeling s SmartModel SWIFT software libsm MODEL_TECH libsm sl ModelSim s interface to Logic Modeling s SmartModel SWIFT software Windows NT libsm S MODEL_TECH libsm dll Logic Modeling s SmartModel SWIFT software HP 9000 Series 700 libswift LMC_HOME 1lib hp700 lib libswift sl Logic Modeling s SmartModel SWIFT software IBM RISC System 6000 libswift LMC_HOME 1ib ibmrs lib swift o Logic Modeling s SmartModel SWIFT software Sun4 Solaris libswift LMC_HOME 1ib sun4Solaris lib libswift so Logic Modeling s SmartModel SWIFT software Windows NT libswift LMC_HOME 1lib pcnt lib libswift dll Logic Modeling s SmartModel SWIFT software Linux libswift LMC_HOME 1ib x86_linux lib libswift so Th
177. at allows you to specify the SDF files to load for the current simulation files are then added to the Region File list You may also select a file on the listing to Delete or Edit opens the dialog box below ModelSim SE User s Manual ModelSim Graphic Interface 8 263 Simulating with the graphic interface SDF options Specify an SDF File Ox SDF File my sdf Browse Apply to region counter Delay Selection typ e tal From the Specify an SDF File dialog box you can set the following options SDF file lt region gt lt sdf_filename gt Specifies the SDF file to use for annotation Use the Browse button to locate a file within your directories Apply to region lt region gt lt sdf_filename gt Specifies the design region to use with the selected SDF options Delay Selection sdfmin sdftyp sdfmax The drop down menu selects delay timing min typ or max to be used from the specified SDF file See also Specifying SDF files for simulation 12 326 The OK button places the specified SDF file and delay on the Region File list Cancel dismisses the dialog box without changes Disable SDF warnings sdfnowarn Select to disable warnings from the SDF reader Reduce SDF errors to warnings sdfnoerror Change SDF errors to warnings so the simulation can continue Multi Source Delay multisource_delay lt sdf_option gt Select max min or latest delay Controls how multiple PORT
178. ates A 385 software version 8 165 Sorting sorting HDL items in VSIM windows 8 154 Source code source code security E 433 ModelSim SE User s Manual Index 475 Source directory setting from source window 8 202 Source files referencing with location maps E 437 Source window see also Windows 8 201 specify when expression 11 312 Speeding up the simulation 9 281 Standards supported 1 17 Startup environment variables access during 2 38 files accessed during 2 37 macro in the modelsim ini file B 400 startup macro in command line mode E 428 using a startup file B 404 Startup ini file variable B 400 Startup macros B 404 Status bar Main window 8 168 std ini file variable B 396 std_developerskit ini file variable B 396 std_logic_arith package 3 51 std_logic_signed package 3 51 std_logic_unsigned package 3 51 StdArithNoWarnings ini file variable B 400 STDOUT environment variable B 394 Stimulus applying to signals and nets 8 196 Structure window see also Windows 8 210 Support A 385 Symbolic link to design libraries UNIX 3 48 synopsys ini file variable B 396 system calls VCD 13 342 Verilog 5 99 System initialization 2 37 system tasks VCD 13 342 Verilog 5 99 T tab stops in the Source window 8 209 Tcl 16 369 16 380 command separator 16 376 command substitution 16 375 command syntax 16 372 evaluation order 16 376 history shortcuts C 412 Man Pages in Help menu 8 165 relational expression evaluation 16 376
179. aves the comparison setup information or rules to a file that can be re executed later as a command file saves compare options and all clock definitions and region and signal selections ModelSim SE User s Manual Waveform Comparison 11 323 Command line interface to Waveform Comparison Command Description compare see command CR 83 causes the specified compare difference to be made visible in the specified wave window using whatever horizontal and vertical scrolling is necessary compare start command CR 84 initializes internal data structures for waveform compare compare stop command CR 86 used internally by the compare stop button to suspend comparison computations in progress compare update command CR 87 used internally to update the comparison differences when comparing a live simulation against a wlf file 11 324 Waveform Comparison ModelSim SE User s Manual 12 Standard Delay Format SDF Timing Annotation Chapter contents Specifying SDF files for simulation 12 326 Instance specification sog ee ae ge e om o p 128826 SDF specification with the GUI Soe ds oo 12827 Errors and warnings o 12 327 VHDL VITAL SDF oa Ho oe oe e op amp of i2328 SDF to VHDL generic tal n e go ro so oop a a po 12 328 Resolvingerrors 2 eee 12 329 Verilog SDF o 12 330 The sdf_annotate systemi task oa a 2330 SDF to Veri
180. ay Properties Wave window and Prop gt Display Props List window ModelSim designates one of the datasets to be the active dataset and refers all names without dataset prefixes to that dataset The active dataset is displayed in the context path at the bottom of the Main window When you select a design unit in a dataset s Structure page that dataset becomes active automatically Alternatively you can use the Dataset Browser or the environment command CR 114 to change the active dataset ModelSim remembers a current context within each open dataset You can toggle between the current context of each dataset using the environment command CR 114 specifying the dataset without a path For example env foo sets the active dataset to foo and the current context to the context last specified for foo The context is then applied to any unlocked windows The current context of the current dataset usually referred to as just current context is used for finding objects specified without a path The Signals window can be locked to a specific context of a dataset Being locked to a dataset means that the window will update only when the content of that dataset changes If locked to both a dataset and a context e g test top foo the window will update only when that specific context changes You specify the dataset to which the window is locked by selecting File gt Environment Signals window Restricting the dataset prefi
181. ay differences in a text format in the Main window Transcript Save save computation differences to a file that can be reloaded later Write Report save computation differences to a text file ModelSim SE User s Manual ModelSim Graphic Interface 8 163 Main window Rules provides two options Show display the rules used to set up the waveform comparison Save save rules for waveform comparison to a file Reload load saved differences and rules files Macro menu Execute Macro browse for and execute a DO file macro Execute Old PE call and execute an old PE 4 7 macro without changing the macro Macro to SE 5 5 backslashes can be selected as pathname delimiters Convert Old PE convert old PE 4 7 macro to SE 5 5 macro without changing the Macro file backslashes can be selected as pathname delimiters Macro Helper UNIX only invoke the Macro Helper tool see also The Macro Helper 8 270 Tel Debugger invoke the Tcl debugger TDebug see also The Tcl Debugger 8 271 TclPro Debugger Options menu invoke the TclPro Debugger by Scriptics if installed TclPro Debugger can be acquired from Scriptics at www scriptics com Compile set both VHDL and Verilog compile options see Setting default compile options 8 252 Simulation set various simulation options see Setting default simulation options 8 265 Edit Preferences set various preference variabl
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183. being analyzed Save Line Coverage Saves a textual report of the source file summary data and details for each executable line in the file Save Excluded Lines Saves a textual report of the lines and files that are currently being excluded from the coverage statistics Save Zeroed Lines Saves a textual report like the Line Coverage report but only includes those lines that have zero coverage Save Totals Saves a one line text report of the total files lines hits and overall percentage for the current analysis Save As Lets you choose from the above reports in one dialog ModelSim SE User s Manual Code Coverage 10 295 The coverage_source window You can open the coverage_source window by selecting a file in the pathname column of The coverage_summary window 10 292 The coverage_source window is an enhanced version of the standard Source window 8 201 When code coverage is enabled an additional column appears on the left side of the window This column identifies how many times each executable line of code has been executed during simulation lines that are not executed are highlighted with a red zero and it marks with a green X lines that have been excluded from the code coverage statistics fi coverage_source control vhd IE E File Edit Object Options Window Seb BEBA 00 when others gt buffer txd lt X end case case control reg 5 downto is when ll gt r
184. bench2 t2 All of the modules within design v compiled for testbench1 are identified by t1 within the library whereas for testbench2 they are identified by t2 When the simulator loads testbenchl the instantiations from testbench1 reference the tl versions of the code Likewise the instantiations from testbench2 reference the t2 versions Therefore you only need to invoke the simulator on the desired top level module and the correct versions of code for the lower level instances are automatically loaded The only time that you need to specify a secondary name to the simulator is when you have multiple secondary names associated with a top level module If you omit the secondary name then by default the simulator loads the most recently generated code optimized or unoptimized for the top level module You may explicitly specify a secondary name to load specific optimized code specify verilog to load the unoptimized code For example suppose you have a top level testbench that works in conjunction with each of several other top level modules that only contain defparams that configure the design In this case you need to compile the entire design for each combination using a different secondary name for each For example vlog fast cl testbench v design v configl v Compiling module testbench Compiling module design Compiling module configl Top level modules testbench configl Analyzing design Optimizing 3
185. bled mb of memory to locking to speed up large designs gt 500mb lock memory footprint see Accelerate simulation by locking memory under HP UX 10 2 E 439 NumericStdNoWarnings 0 1 if 1 warnings generated within the off 0 accelerated numeric_std and numeric_bit packages are suppressed PathSeparator any single used for hierarchical path names must not character be the same character as DatasetSeparator Resolution fs ps ns us ms simulator resolution this value must be less ns or sec with than or equal to the UserTimeUnit specified optional prefix of below NOTE if your delays are truncated 1 10 or 100 set the resolution smaller no space between value and units i e 10ps not 10 ps RunLength positive integer default simulation length in units specified 100 by the UserTimeUnit variable Startup do lt DO specifies the ModelSim startup macro see commented filename gt any the do command CR 104 out valid macro do file StdArithNoWarnings 0 1 if 1 warnings generated within the off 0 accelerated Synopsys std_arith packages are suppressed TranscriptFile any valid file for saving command transcript transcript filename environment variables may be included in the path name B 400 ModelSim Variables ModelSim SE User s Manual Preference variables located in INI files Variable name Value range Purpose Default UnbufferedOutput 0 1 controls VHDL and Verilo
186. blish compiler switches and settings at each session these are stored in the project metadata as are mappings to HDL source files e allow users to share libraries without copying files to a local directory you can establish references to source files that are stored remotely or locally e allow you to change individual parameters across multiple files in previous versions you could only set parameters one file at a time e enable what if analysis you can copy a project manipulate the settings and rerun it to observe the new results e reload ini variable settings every time the project is opened in previous versions you had to quit ModelSim and restart the program to read in a new ini file 2 26 Projects and system initialization ModelSim SE User s Manual Introduction How do projects differ in version 5 5 Projects have improved a great deal from earlier versions Some of the key differences include e A new interface eliminates the need to write custom scripts e You don t have to copy files into a specific directory you can establish references to files in any location e You don t have to specify compiler switches the automatic defaults will work for many designs However if you do want to customize the settings you do it through a dialog box rather than by writing a script e All metadata compiler settings compile order file mappings are stored in the project mpf file A Important Due to the sig
187. bookmark Delete All bookmark delete wave Delete all bookmarks Goto bookmark goto wave Zoom and scroll the Wave window using the selected bookmark ModelSim SE User s Manual ModelSim Graphic Interface 8 243 Wave window Wave window mouse and keyboard shortcuts The following mouse actions and keystrokes can be used in the Wave window Mouse action Result lt control left button click on a scroll arrow gt scrolls window to very top or bottom vertical scroll or far left or right horizontal scroll lt middle mouse button click in scroll bar trough gt UNIX only Keystroke scrolls window to position of click Action il or zoom in oOo zoom out for F zoom full mouse pointer must be over the the cursor or waveform panes lor L zoom last ror R zoom range lt arrow up gt scroll waveform display up by selecting the item above the currently selected item lt arrow down gt scroll waveform display down by selecting the item below the currently selected item lt arrow left gt scroll waveform display left lt arrow right gt scroll waveform display right lt page up gt scroll waveform display up by a page lt page down gt scroll waveform display down by a page lt tab gt search forward right to the next transition on the selected signal finds the next edge lt shift tab gt searc
188. brary the library must be created by ModelSim and it s directory must include a _info file e Design Unit This hierarchical list allows you to select one top level entity or configuration to be simulated All entities configurations and modules that exist in the specified library are displayed in the list box Architectures can be viewed by selecting the box before any name ModelSim SE User s Manual ModelSim Graphic Interface 8 257 Simulating with the graphic interface e Simulate lt configuration gt lt module gt lt entity gt lt architecture gt Specifies the design unit s to simulate You can simulate several Verilog top level modules or a VHDL top level design unit in one of three ways 1 Type a design unit name configuration module or entity into the field separate additional names with a space Specify library design units with the following syntax lt library_name gt lt design_unit gt 2 Click on a name in the Design Unit list below and click the Add button 3 Leave this field blank and click on a name in the Design Unit list single unit only e Simulator Resolution time lt multiplier gt lt time_unit gt The drop down menu sets the simulator time units original default is ns Simulator time units can be expressed as any of the following Simulation time units 1fs 10fs or 100fs femtoseconds 1ps 10ps or 100ps picoseconds Ins 10ns or 100ns nanosec
189. can create a new window with View gt New from the The Main window menu bar 8 160 Copy copy the selected items in the Variables window Sort sort the variables tree in either ascending descending or declaration order Select All select all items in the Variables window Unselect All deselect all items in the Variables window Expand Selected expand the hierarchy of the selected item Collapse Selected collapse the hierarchy of the selected item Expand All expand the hierarchy of all items that can be expanded Collapse All collapse the hierarchy of all expanded items Change change the value of the selected HDL item Justify Values justify values to the left or right margins of the window pane Find find the specified text string within the variables tree choose the Name or Value field to search and the search direction Down or Up View menu Wave List Log place the Selected Variables or Variables in Region in the Wave window 8 216 List window 8 175 or logfile 8 214 ModelSim Graphic Interface ModelSim SE User s Manual Variables window Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon C
190. cate ModelSim sales contacts anywhere in the world model com contact_us asp Support Model Technology email support and software downloads model com support default asp 1 22 Introduction ModelSim SE User s Manual Comments Comments Comments and questions about this manual and ModelSim software are welcome Call write fax or email Model Technology Incorporated 10450 SW Nimbus Avenue Bldg R B Portland OR 97223 4347 USA phone 503 641 1340 fax 503 526 5410 email manuals model com home page http www model com ModelSim SE User s Manual Introduction 1 23 1 24 Introduction ModelSim SE User s Manual 2 Projects and system initialization Chapter contents Introduction Boe ee ee wo ge wh le Se oe 2G What are projects o sop ooe a e oo eoe EO What are the benefits of projects rob e wo e e woo 220 How do projects differ in version 5 57 woe to op s s amp amp 227 Getting started with projects 000a a wee 2 28 Step 1 Create a new project aaa aaa 2 29 Step 2 Add files to the project aaa 2 31 Step 3 Compile the files 2 31 Step 4 Simulate a design a 231 Other project operations 2 ee 2 83 Customizing project settings 2 1 2 34 Changing compile order 2 2 2 34 Setting compiler options 2 1 we 2 85 Accessing projects from the commandline
191. cating source errors during compilation 8 251 Location maps referencing source files E 437 LockedMemory ini file variable B 400 logfile 11 302 logfiles 7 137 E 434 Logic Modeling SmartModel command channel 14 358 compiling Verilog shells 14 361 SmartModel Windows Imcwin commands 14 359 memory arrays 14 360 M MacroNestingLevel simulator state variable B 408 Macros DO files creating from a saved transcript 8 159 depth of nesting simulator state variable B 408 DO files macros E 430 error handling E 431 parameter as a simulator state variable n B 408 parameter total as a simulator state variable B 408 passing parameters to E 430 startup macros B 404 Main window see also Windows 8 157 Mapping Verilog states in mixed designs 6 130 math_complex package 3 51 math_real package 3 51 ModelSim SE User s Manual Index 472 Memory locked memory under HP UX 10 2 E 439 modeling in VHDL E 440 Menus customizing menus and buttons 8 154 Dataflow window 8 172 List window 8 176 Main window 8 160 Process window 8 191 see also context menus Signals window 8 194 Source window 8 202 Structure window 8 211 tearing off or pinning menus 8 154 Variables window 8 214 Wave window 8 220 Messages turning off assertion messages B 404 turning off warnings from arithmetic packages B 404 MGC_LOCATION_MAP environment variable B 393 Miss and Exclusion details 10 293 Mixed language simulation 6 127 MODEL_TECH environ
192. cc_close is called The following object types are created on demand in ModelSim Verilog accOperator acc_handle_condition accWirePath acc_handle_path accTerminal acc_handle_terminal acc_next_cell_load acc_next_driver and acc_next_load accPathTerminal acc_next_input and acc_next_output accTchkTerminal acc_handle_tchkargl and acc_handle_tchkarg2 accPartSelect acc_handle_conn acc_handle _pathin and acc_handle_pathout accRegBit acc_handle_by_name acc_handle_tfarg and acc_handle_itfarg If your PLI application uses these types of objects then it is important to call acc_close to free the memory allocated for these objects when the application is done using them If your PLI application places value change callbacks on accRegBit or accTerminal objects do not call acc_close while these callbacks are in effect ModelSim SE User s Manual Verilog Simulation 5 119 Using the Verilog PLI VPI Third party PLI applications Many third party PLI applications come with instructions on using them with ModelSim Verilog Even without the instructions it is still likely that you can get it to work with ModelSim Verilog as long as the application uses standard PLI routines The following guidelines are for preparing a Verilog XL PLI application to work with ModelSim Verilog Generally a Verilog XL PLI application comes with a collection of object files and a veriuser c file The veriuser c file contains the registrati
193. ce ModelSim VITAL compliance A simulator is VITAL compliant if it implements the SDF mapping and if it correctly simulates designs using the VITAL packages as outlined in the VITAL Model Development Specification ModelSim is compliant with the IEEE 1076 4 VITAL ASIC Modeling Specification In addition ModelSim accelerates the VITAL_Timing and VITAL_Primitives packages The procedures in these packages are optimized and built into the simulator kernel By default vsim CR 258 uses the optimized procedures The optimized procedures are functionally equivalent to the IEEE 1076 4 VITAL ASIC Modeling Specification VITAL v3 0 VITAL compliance checking Compliance checking is important in enabling VITAL acceleration to qualify for global acceleration an architecture must be VITAL level one compliant vcom CR 217 automatically checks for VITAL 3 0 compliance on all entities with the VITAL_Level0 attribute set and all architectures with the VITAL_Level0 or VITAL_Levell attribute set It also checks for VITAL 2000 compliance on all architectures using the vital2000 library If you are using VITAL 2 2b you must turn off the compliance checking either by not setting the attributes or by invoking vcom CR 217 with the option novitalcheck It is of course possible to turn off compliance checking for VITAL 3 0 as well we strongly suggest that you leave checking on to ensure optimal simulation VITAL compliance warnings The following L
194. ce file Object menu Describe display information about the selected HDL item same as the describe command CR 100 the item name is shown in the title bar Examine display the current value of the selected HDL item same as the Options menu examine CR 115 command the item name is shown in the title bar Colorize Source colorize key words variables and comments Highlight Executable Lines highlight the line numbers of executable lines Middle Mouse Button Paste enable disable pasting by pressing the middle mouse button Verilog specify Verilog style colorizing Highlighting VHDL Highlighting specify VHDL style colorizing Freeze File maintain the same source file in the Source window useful when you have two Source windows open one can be updated from the Structure window 8 210 the other frozen Freeze View disable updating the source view from the Process window 8 190 Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status b
195. ce file with a different name Compile compile HDL source files Close close this copy of the Source window you can create a new window with View gt New from the The Main window menu bar 8 160 Edit menu To edit a source file make sure the Read Only option in the Source Options dialog box is not selected use the Edit gt read only Source menu selection lt editing option gt basic editing options include Undo Cut Copy Paste Select All and Unselect All see Mouse and keyboard shortcuts in the Transcript and Source windows 8 168 Find find the specified text string or regular expression within the source file there is an option to match case or search backwards Find Next find the next occurrence of a string specified with the Find command Replace find the specified text string or regular expression and replace it with the specified text string or regular expression Previous Coverage when simulating with Code Coverage 10 291 finds the previous Miss line of code that was not used in the simulation Next Coverage Miss when simulating with Code Coverage 10 291 finds the next line of code that was not used in the simulation Breakpoints add edit or delete file line and signal breakpoints see Setting file line breakpoints 8 205 8 202 ModelSim Graphic Interface ModelSim SE User s Manual Source window read only toggle the read only status of the current sour
196. cedure is active then varName refers to a namespace variable global variable if the current namespace is the global namespace If a procedure is active then varName refers to a parameter or local variable of the procedure unless the global command was invoked to declare varName to be global or unless a Tcl variable command was invoked to declare varName to be a namespace variable More Tcl commands All Tcl commands are documented from within ModelSim Select Help gt Tcl Man Page Main window Command substitution Placing a command in square brackets will cause that command to be evaluated first and its results returned in place of the command An example is set a 25 set b 11 set c 3 echo the result is expr a Sb c will output the result is 12 This feature allows VHDL variables and signals and Verilog nets and registers to be accessed using examine lt radix gt name The name substitution is no longer supported Everywhere name could be used you now can use examine value lt radix gt name which allows the flexibility of specifying command options The radix specification is optional ModelSim SE User s Manual Tcl and ModelSim 16 375 Tcl commands Command separator A semicolon character works as a separator for multiple commands on the same line It is not required at the end of a line in a command sequence Multiple line commands With Tcl multiple line commands can be used wit
197. chnology Please contact Model Technology at license model com If you have trouble with licensing Contact your normal technical support channel Technical support electronic A 386 Technical support telephone A 387 Technical support other channels A 387 Maintenance renewals and licenses When maintenance is renewed a new license file that incorporates the new maintenance expiration date will be automatically sent to you If maintenance is not renewed the current license file will still permit the use of software versions built before maintenance expired until the stop date is reached License transfers and server changes Model Technology and Mentor Graphics both charge a fee for server changes or license transfers Contact sales model com for more information from Model Technology or contact your local Mentor Graphics sales office for Mentor Graphics purchases Additional licensing details A complete discussion of licensing is located in the Start Here for ModelSim guide For an online version of Start Here check the ModelSim Main window Help menu for SE Documentation ModelSim SE User s Manual Technical Support Updates and Licensing A 389 A 390 Technical Support Updates and Licensing ModelSim SE User s Manual B Model Sim Variables Appendix contents Variable settings report 2 ee B 392 Personal preferences s o o cs po s so B 392 Returning to the original ModelSim
198. ck functions are optional but most applications contain at least the calltf function which is called when the system task or function is executed in the Verilog code The first argument to the callback functions is the value supplied in the data field many PLI applications don t use this field The type field defines the entry as either a system task USERTASK or a 5 108 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI system function that returns either a register USERFUNCTION or a real USERREALFUNCTION The tfname field is the system task or function name it must begin with The remaining fields are not used by ModelSim Verilog On loading of a PLI application the simulator first looks for an init_usertfs function and then a veriusertfs array If init_usertfs is found the simulator calls that function so that it can call mti_RegisterUserTF for each system task or function defined The mti_RegisterUserTF function is declared in veriuser h as follows void mti_RegisterUserTF p_tfcell usertf The storage for each usertf entry passed to the simulator must persist throughout the simulation because the simulator de references the usertf pointer to call the callback functions It is recommended that you define your entries in an array with the last entry set to 0 If the array is named veriusertfs as is the case for linking to Verilog XL then you don t have to provide an init_usertfs functio
199. cking and dragging on the right border The selected signal is highlighted The white bar along the left margin indicates the selected dataset see Splitting Wave window panes 8 228 top clk top prw top pstrb top prdy top paddr top pdata top stw top sstrb top srdy top saddr top sdata 8 216 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Values pane A values pane displays the values of the displayed signals The radix for each signal can be symbolic binary octal decimal unsigned hexadecimal ASCII or default The default radix can be set by selecting Options gt Simulation Main window see Setting default simulation options 8 265 The data in this pane is similar to that shown in the Signals window 8 193 except that the values change dynamically whenever a cursor in the waveform pane below is moved values pane Waveform pane The waveform pane displays the waveforms that correspond to the displayed signal pathnames It also displays up to 20 cursors Signal values can be displayed in analog step analog interpolated analog backstep literal logic and event formats Each signal can be formatted individually The default format is logic The window pane below the pathnames window pane and to the left of the cursor panes is unused at this time Biss eer waveform pane cursors ModelSim SE User s Manual ModelSim Graphic Interface
200. closed when you exit from it If a file is declared in a subprogram the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram Alternatively the opening of files can be delayed until the first read or write by setting the DelayFileOpen variable in the modelsim ini file Also the number of concurrently open files can be controlled by the ConcurrentFileLimit variable These variables help you manage a large number of files during simulation See Appendix B ModelSim Variables for more details 4 60 VHDL Simulation ModelSim SE User s Manual Using the TextlO package Using STD_INPUT and STD_OUTPUT within Model Sim The standard VHDL 87 TextlO package contains the following file declarations file input TEXT is in STD_INPUT file output TEXT is out STD_OUTPUT The standard VHDL 93 TextIO package contains these file declarations file input TEXT open read_mode is STD_INPUT file output TEXT open write_mode is STD_OUTPUT STD_INPUT is a file_logical_name that refers to characters that are entered interactively from the keyboard and STD_OUTPUT refers to text that is displayed on the screen In ModelSim reading from the STD_INPUT file allows you to enter text into the current buffer from a prompt in the Main window The last line written to the STD_OUTPUT file appears at the prompt ModelSim SE User s Manual VHDL Simulation 4 61 TextlO implementation issues TextlO
201. clude click your right mouse button and select Exclude Selected Lines The lines you exclude will be shown in the Exclusions tab and also marked with a green X in The coverage_source window 10 296 The Exclusions tab lists all file and line exclusion filters for the current simulation This includes line or file exclusions made in the Misses tab or in the coverage_source window The Exclusions tab offers several commands via a context menu Click anywhere within the tab with your right mouse button to get the following context menu The menu has the following options Include Entire Selected Fil e Include Entire Selected Files A E ie Adds selected lines or files back into the Revert To Initial Filter coverage statistics If you have multiple lines Clear out Current Filter excluded in one file it will add back all of Load a New Filter them To add back individual lines use the coverage_source window Disable Filtering Cancel ModelSim SE User s Manual Code Coverage 10 293 The coverage_summary window Revert To Initial Filter Returns filtering to the default exclusion filter file Load a New Filter Clear Out Current Filter Clears active exclusion filters Opens a different exclusion filter file Disable Enable Filtering Disables enables filtering Acts as a toggle Allows you to temporarily turn off filtering to see raw code coverage statistics Cancel Closes the context menu The coverage_summary
202. computation differences to a file that can be reloaded later Write Report save computation differences to a text file Rules provides two options Show display the rules used to set up the waveform comparison Save save rules for waveform comparison to a file Reload load saved differences and rules files Bookmark menu Add Bookmark add a new bookmark that saves a specific zoom and scroll range Edit Bookmarks edit an existing bookmark lt bookmark_name gt list of currently defined bookmarks 8 222 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Format menu Radix set the selected item s radix Format set the waveform format for the selected item Literal Logic Event Analog Color set the color for the selected item from a color palette Height Window menu set the waveform height in pixels for the selected item Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window
203. ct verbose Returns Nothing Arguments Name Description spy_object Required A full hierarchical path or relative path with reference to the calling block to a VHDL signal or Verilog register wire Use the path separator to which your simulation is set i e or A full hierarchical path must begin with a or The path must be contained within double quotes dest_object Required A full hierarchical path or relative path with reference to the calling block to an existing VHDL signal or Verilog register Use the path separator to which your simulation is set 1 e or A full hierarchical path must begin with a or The path must be contained within double quotes verbose integer Optional Possible values are 0 or 1 Specifies whether you want a message reported in the Transcript stating that the spy_object s value is mirrored onto the dest_object Default is 0 no message Related functions None Limitations e When mirroring the value of a Verilog register wire onto a VHDL signal the VHDL signal must be of type bit bit_vector std_logic or std_logic_vector e Mirroring slices or single bits of a vector is not supported If you do reference a slice or bit of a vector the function will assume that you are referencing the entire vector ModelSim SE User s Manual VHDL Simulation 4 69 Util package Example library modelsim_lib use modelsim_lib
204. ction hash indicated by a lighter blue circle icon Task update_mru parameters registers nets module instantiations named forks named begins tasks and functions Function pick_set Task sysread Task syswrite Virtual items Function get_hit indicated by an orange diamond icon Ml s0 cache_set only virtual signals buses and functions M sl cache_set only see Virtual Objects User defined E s2 cache_set only buses and more 7 144 for more M s3 cache_set orly information Viewing the hierarchy sim top Whenever you see a tree view as in the Structure window displayed here you can use the mouse to collapse or expand the hierarchy Select the symbols as shown below to change the view of the structure Description click a plus box to expand the item and view the structure click a minus box to hide a hierarchy that has been expanded ModelSim SE User s Manual ModelSim Graphic Interface 8 155 Common window features Finding items within tree windows You can open the Find dialog box within all windows except the Dataflow windows by selecting Edit gt Find or by using lt control s gt Unix or lt control f gt Windows Options within the Find dialog box allow you to search unique text string fields within the specific window See also e Finding items by name in the List window 8 185 e Finding HDL items in the Signals window 8 198 and e F
205. ctions are also implicitly created by ModelSim when referencing bit selects or part selects of Verilog registers in the GUI or when expanding Verilog registers in the Signals Wave or List windows This is necessary because referencing Verilog register elements requires an intermediate step of shifting and masking of the Verilog vreg data structure Virtual regions User defined design hierarchy regions can be defined and attached to any existing design region or to the virtuals context tree They can be used to reconstruct the RTL hierarchy in a gate level design and to locate virtual signals Thus virtual signals and virtual regions can be used in a gate level design to allow you to use the RTL test bench Virtual regions are created and attached using the virtual region command CR 242 Virtual types User defined enumerated types can be defined in order to display signal bit sequences as meaningful alphanumeric names The virtual type is then used in a type conversion expression to convert a signal to values of the new type When the converted signal is displayed in any of the windows the value will be displayed as the enumeration string corresponding to the value of the original signal Virtual types are created using the virtual type command CR 248 7 146 Datasets saved simulations and virtuals ModelSim SE User s Manual Dataset logfile and virtual commands Dataset logfile and virtual commands The table below p
206. ctive_scope acc_set_pulsere acc_set_scope acc_set_value acc_vcl_add acc_vcl_ delete acc_version B Note acc_fetch_paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc_fetch_paramval_str has been added to the PLI for this use acc_fetch_paramval_str is declared in acc_user h It functions in a manner similar to acc_fetch_paramval except that it returns a char acc_fetch_paramval_str can be used on all platforms IEEE Std 1364 TF routines ModelSim Verilog supports the following TF routines described in detail in the IEEE Std 1364 io_mcdprintf io_printf mc_scan_plusargs tf_add_long tf_asynchoff tf_iasynchoff tf_asynchon tf_iasynchon tf_clearalldelays tf_iclearalldelays tf_compare_long tf_copypvc_flag tf_icopypvc_flag tf_divide_long tf_dofinish tf_dostop tf_error tf_evaluatep tf_ievaluatep tf_exprinfo tf_iexprinfo tf_getcstringp tf_igetcstringp tf_getinstance tf_getlongp tf_igetlongp tf_getlongtime tf_igetlongtime tf_getnextlongtime tf_getp tf_igetp tf_getpchange tf_igetpchange tf_getrealp tf_igetrealp tf_getrealtime tf_igetrealtime tf_gettime tf_igettime tf_gettimeprecision tf_igettimeprecision tf_gettimeunit tf_igettimeunit tf_getworkarea tf_igetworkarea tf_long_to_real
207. d in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of FITNESS FOR A PARTICULAR PURPOSE Starting the debugger Select Macro gt Tcl Debugger Main window to run the debugger Make sure you use the ModelSim and TDebug menu selections to invoke and close the debugger If you would like more information on the configuration of TDebug see Help gt Technotes gt tdebug The following text is an edited summary of the README file distributed with TDebug How it works TDebug works by parsing and redefining Tcl Tk procedures inserting calls to td_eval at certain points which takes care of the display stepping breakpoints variables etc The advantages are that TDebug knows which statement in what procedure is currently being executed and can give visual feedback by highlighting it All currently accessible variables and their values are displayed as well Code can be evaluated in the context of the current procedure Breakpoints can be set and deleted with the mouse Unfortunately there are drawbacks to this approach Preparation of large procedures is slow and due to Tcl s dynamic nature there is no guarantee that a procedure can be prepared at all This problem has been alleviated somewhat with the introduction of partial preparation of procedures There is still no possibility to get at code running in the global context The Chooser Select Macro gt Tcl Debugger Main window to open t
208. d language design Verilog from VHDL 6 132 VHDL from Verilog 6 136 Instantiation label 8 211 Interconnect delays 5 86 12 336 Iteration_limit detecting infinite zero delay loops E 436 IterationLimit ini file variable B 399 K Keyboard shortcuts List window 8 188 C 411 Wave window 8 244 C 410 L Libraries 64 bit and 32 bit in same library 3 52 alternate IEEE libraries 3 51 creating design libraries 3 43 design library types 3 42 design units 3 42 leee_numeric 3 51 leee_synopsis 3 51 mapping from the command line 3 48 mapping hierarchy B 403 mapping search rules 3 48 mapping with the GUI 3 47 moving 3 49 naming 3 47 predefined 3 50 rebuilding ieee_numeric 3 51 rebuilding ieee_synopsis 3 51 refreshing library images 3 51 resource libraries 3 42 setting up for groups E 434 std 3 50 verilog 5 78 6 129 VHDL library clause 3 50 working libraries 3 42 working with contents 3 44 libraries modelsim_lib 4 68 library simulator state variable B 408 Licensing License variable in ini file B 400 locating the license file D 418 using the FLEXIm license manager D 417 List window waveform comparison 11 322 List window see also Windows 8 175 List window see Windows LM_LICENSE_FILE environment variable B 393 Imdown license server utility D 422 Imgrd license server utility D 422 Imremove license server utility D 423 Imreread license server utility D 423 Imstat license server utility D 422 Imutil license server utility D 423 Lo
209. d partners OEM partners FPGA partners ASIC partners and training partners model com partners default asp Products A complete collection of Model Technology product information model com products default asp Technical Documents Technical notes application notes FAQs model com resources techdocs asp Sales Locate ModelSim sales contacts anywhere in the world model com contact_us asp Support Model Technology email support and software downloads model com support default asp A 388 Technical Support Updates and Licensing ModelSim SE User s Manual FLEXIm Licenses FLEXIm Licenses ModelSim uses Globetrotter s FLEXIm license manager and files Globetrotter FLEXIm license files contain lines that can be referred to by the word that appears first on the line Each kind of line has a specific purpose and there are many more kinds of lines that MTI does not use Mentor Graphics customers Mentor Graphics provides licensing information in the Mentor Graphics Licensing chapter in the Managing Mentor Graphics Software document In addition Model Technology provides some basic Mentor Graphics licensing files See the readme file in the MGLS related directory at ftp model com pub SE for more information Where to obtain your license Mentor Graphics customers must contact their Mentor Graphics salesperson for ModelSim licensing All other customers may obtain ModelSim licenses from Model Te
210. d_logic_1164 Expand All MM Package standard Collapse All Find g Project test gold top i The Structure page context menu includes the following options Save As Writes the HDL item names in the Structure page to a text file e Sort Sorts the HDL items in the Structure page by alphabetic ascending or descending or declaration order Expand Selected Shows the hierarchy of the selected HDL item Collapse Selected Hides the hierarchy of the selected HDL item Expand All Shows the hierarchy of all HDL items in the list Collapse All Hides the hierarchy of all HDL items in the list Find Opens the Find dialog See Finding items in the Structure window 8 212 for details ModelSim SE User s Manual Datasets saved simulations and virtuals 7 141 Datasets Managing datasets When you have one or more datasets open you can manage them using the Dataset Browser To open the browser select View gt Datasets Main window Dataset Browser A ES fcache sysread View control Simulation Open Dataset Close Dataset Make Active Rename Dataset _ ome The Dataset Browser dialog box includes the following options Open Dataset Opens the View Dataset dialog box see Opening datasets 7 139 so you can open additional datasets Close Dataset Closes the selected dataset This will also remove the dataset s Structure page in the Main window workspace Make Active Make
211. dard 8 252 se clause specifying a library 3 50 se explicit declarations only 8 253 Jser defined bus 7 144 8 154 serTimeUnit ini file variable B 401 util package 4 68 qqqaqcgc cag V Values of HDL items 8 208 Variables environment variables B 393 LM_LICENSE_FILE B 393 loading order at ModelSim startup B 407 personal preferences B 392 reading from the ini file B 402 setting environment variables B 393 simulator state variables current settings report B 392 iteration number B 408 name of entity or module as a variable B 408 resolution B 408 simulation time B 408 Variables window see also Windows 8 213 Variables HDL changing value of with the GUI 8 213 VCD files capturing port driver data 13 349 creating 13 344 dumpports tasks 13 343 extracting the proper stimulus 13 344 from VHDL source to VCD output 13 346 supported TSSI states 13 349 VCD system tasks 13 342 Verilog capturing port driver data with dumpports 13 349 cell libraries 5 97 compile options 8 254 compiler directives 5 106 compiling design units 5 75 compiling with XL uselib compiler directive 5 81 component declaration 6 134 creating a design library 5 75 instantiation criteria in mixed language design 6 132 instantiation of VHDL design units 6 136 library usage 5 78 mapping states in mixed designs 6 130 mixed designs with VHDL 6 127 parameters 6 129 SDF annotation 12 330 sdf_annotate system task 12 330 simulating 5 84 delay modes 5 97 event o
212. dded automatically to the Wave window 11 314 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison e Comparison Method dd Signal Options Clocked Strobed Comparison Allows you to select a default reference clock signal via a selection history or a browse button Continuous Comparison Allows you to set leading and trailing edge tolerances for the waveform comparison The leading edge tolerance specifies how much earlier the test signal edge may occur before the reference signal edge The trailing edge tolerance specifies how much later the test signal edge may occur after the reference signal edge The default value for both tolerances is zero Specify When Expression Allows you to specify a when expression that must evaluate to true or 1 at the signal edge for the clock to become effective Clicking the Builder button will give you access to The GUI Expression Builder 8 275 Save as Default Allows you to save all changes as the new default settings for subsequent waveform comparisons Reset to Default Resets all settings to original default values ModelSim SE User s Manual Waveform Comparison 11 315 Graphical Interface to Waveform Comparison Wave window display wave default File Edit Cursor Zoom Compare Bookmark Format Window Saus tse RR tT QQQ Q EF a lalesi Minimum SDF Timing
213. de Instance specific Values G lt Name gt lt Value gt Select to override generics that received explicit values in generic maps The name and value are specified as above The use of this switch is indicated in the Override Instance column of the Generics list The OK button adds the generic to the Generics listing Cancel dismisses the dialog box without changes VITAL e Disable Timing Checks notimingchecks Disables timing checks generated by VITAL models e Use Vital 2 2b SDF Mapping vital2 2b Selects SDF mapping for VITAL 2 2b default is Vital95 e Disable Glitch Generation noglitch Disables VITAL glitch generation TEXTIO files STD_INPUT std_input lt filename gt Specifies the file to use for the VHDL textio STD_INPUT file Use the Browse button to locate a file within your directories e STD_OUTPUT std_output lt filename gt Specifies the file to use for the VHDL textio STD_OUTPUT file Use the Browse button to locate a file within your directories 8 260 ModelSim Graphic Interface ModelSim SE User s Manual Simulating with the graphic interface Verilog settings page Load Design The Verilog page includes these options Delay Selection mindelays typdelays maxdelays Use the drop down menu to select timing for min typ max expressions Also see Timing check disabling 4 58 Pulse Options e Disable pulse error and warning messages no_pulse_msg Dis
214. de app c ld o app sl app o bE app exp bI lt install_dir gt modeltech rs6000 mti_exports bM SRE bnoentry lc The app exp file must export the PLI VPI initialization function or table For the PLI the exported symbol should be init_usertfs Alternatively if there is no init_usertfs function then the exported symbol should be veriusertfs For the VPI the exported symbol should be vlog_startup_routines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the shared object 64 bit RS 60000 platform Only version 4 3 of AIX supports the 64 bit platform A gcc 64 bit compiler is not available at this time The cc commands are as follows cc c q64 I lt install_dir gt modeltech include app c cc o app sl app o q64 bE app exp bI lt install_dir gt modeltech rs64 mti_exports W1 G bnoentry gt Note When using AIX 4 3 in 32 bit mode you must add the switch d use_inttypes to the compile command lines This switch prevents a name conflict that occurs between inttypes h and mti h Using 64 bit ModelSim with 32 bit PLI VPI Applications If you have 32 bit PLI VPI applications and wish to use 64 bit ModelSim you will need to port your code to 64 bits by moving from the ILP32 data model to the LP64 data model We strongly recommend that you consult the following 64 bit porting guides for the appropriate platform Sun Solaris 7 64 bit
215. de coverage use the 00 capital O zero argument when you compile your design files This argument minimizes compiler optimizations The coverage_summary window summary Jp gt misses and exclusions The coverage_summary window provides a graphical view of code coverage To display the coverage_summary window select View gt Other gt Source Coverage Main window or enter view_coverage at the VSIM prompt coverage_summary File Coverage Report i i Coverage E modelsim55_011801 win32 vhdl E modelsim55_011801 win32 vhdl E modelsim55_011801 win32 vhdl E modelsim55_011801 win32 vhdl control hd retrieve vhd ringrtl hd store vhd testing vhd IF csb 0 THEN control reg lt switch when 10 when 0l Y buffer_txd lt txd l buffer_txd lt txd 2 when 00 buffer_txd lt txd 3 when 10 rxd lt l buffer rxd amp 11 rvd antirra lo PES Y The window is split into two panes the top pane displays Summary information 10 293 on a per file basis the bottom pane displays lines misses on the Misses tab 10 293 and file or line exclusions on the Exclusions tab 10 293 10 292 Code Coverage ModelSim SE User s Manual The coverage_summary window The coverage_summary window is linked to The coverage_source window 10 296 When you select a file in the top pane that file displays in the coverage_source window Likewise if you
216. defaults B 392 Environment variables 2 a B 393 Preference variables located in INI files B 396 Library library path variables B 396 vcom VHDL compiler control variables B 396 vlog Verilog compiler control variables B 398 vsim simulator control variables B 398 Imc Logic Modeling variables B 402 Setting variables in INI files 2 2 2 2 1 B 402 Reading variable values from the INI file B 402 Variable functions a B 403 Preference variables located in TCL files B 406 Preference variable loading order B 407 Simulator state variables ee B 408 This appendix documents the following types of ModelSim variables e environment variables Variables referenced and set according to operating system conventions Environment variables prepare the ModelSim environment prior to simulation e ModelSim preference variables Variables used to control compiler or simulator functions usually in tcl files and modify the appearance of the ModelSim GUI usually in INI files e simulator state variables Variables that provide feedback on the state of the current simulation ModelSim SE User s Manual ModelSim Variables B 391 Variable settings report Variable settings report The report com
217. delSim Graphic Interface ModelSim SE User s Manual ModelSim tools ModelSim tools Several tools are available from ModelSim menus The menu selections to locate the tools are below the tool names Follow the links for more information on each tool The Button Adder 8 269 Window gt Customize any window Allows you to add a temporary function button or toolbar to any window The Macro Helper 8 270 Macro gt Macro Helper Main window Creates macros by recording mouse movements and key strokes UNIX only excluding Linux The Tcl Debugger 8 271 Macro gt Tcl Debugger Main window Helps you debug your Tcl procedures The GUI Expression Builder 8 275 Edit gt Search gt Search for Expression gt Builder List or Wave window Helps you build logical expressions for use in Wave and List window searches and several simulator commands For expression format syntax see GUI_expression_format CR 297 The Button Adder The ModelSim Button Adder creates a single button or a combined button and toolbar in any currently opened ModelSim window The button exists until you close the window See Buttons the easy way 8 279 gt Note When a button is created with the Button Adder the commands that created the button are echoed in the transcript The transcript can then be saved and used as a DO file allowing you to reuse the commands to recreate the button from a startup DO file See Using a startup
218. delSim SE User s Manual What s new in ModelSim F 453 Main window changes Design menu See The Main window menu bar 8 160 for complete menu option details 5 3 5 4 5 5 Design Iof Xx replaced in 5 5 by the Designs page in the Workspace new 5 5 context menuaccessed via right mouse button on the Project page F 454 What s new in ModelSim ModelSim SE User s Manual Main window changes View menu See The Main window menu bar 8 160 for complete menu option details IM Kiera lel ES new selections and sub menu Project menu The Project menu is new in version 5 5 See What are projects 2 26 for details 5 5 Project OF x new menu ModelSim SE User s Manual What s new in ModelSim F 455 Main window changes Compare menu The Compare menu is new in version 5 5 See Chapter 11 Waveform Comparison for details on waveform comparisons See also The Main window menu bar 8 160 for complete menu option details 5 5 l Compare ME E3 Start Comparison Comparison Wizard Aun Comparison End Comparison Add Options Differences gt Rules gt Reload Options menu new menu See The Main window menu bar 8 160 for complete menu option details See also What are projects 2 26 for details on Project operations 5 3 5 4 za Options Mi ES Compile Simulation Edit P
219. deltech win32 tcl vsim pref tcl ModelSim gt 5 3 5 4 No Desian Loaded gt Menu bar and toolbar The Main window toolbar in version 5 5 has not changed from version 5 3 5 4 The Main window menu bar has new Project and Compare menus See the following pages for additional menu changes ModelSim SE User s Manual What s new in ModelSim F 451 Main window changes new menus ModelSim ModelSim 5 3 5 4 File menu As shown below the version 5 5 Main window File menu contains two additions See The Main window menu bar 8 160 for complete menu option details 5 5 Pile Es new sub menu F 452 What s new in ModelSim ModelSim SE User s Manual Main window changes The graphic below shows the new menu command for importing adding a source file to a project See Step 2 Add files to the project 2 31 for details 5 3 5 4 5 5 New Iof x Compile Order new 5 5 context New Folder Compile All menuaccessed New Source PAPAS via right mouse a y b h Import Source Add file to Project pe in New Project Sort by Alphabetical Order the Workspace or l Project M Ed Compile Order Compile All new Project sme Add File to Project Edit menu See The Main window menu bar 8 160 for complete menu option details 5 5 Lopy Paste Select All Unselect All Find Breakpoint s new selection Mo
220. der see GUI expression builder Extended identifier 6 132 F F8 function key 8 170 C 414 file line breakpoints 8 205 Finding a cursor in the Wave window 8 240 a marker in the List window 8 187 Finding names and searching for values 8 153 FLEXIm license manager D 417 D 423 administration tools for Windows D 423 license server utilities D 422 force command defaults B 404 Foreign language interface tracing 5 125 format file Wave window 8 219 G GenerateFormat ini file variable B 399 Generics VHDL 6 128 get_resolution VHDL function 4 68 Graphic interface 8 149 8 279 UNIX support 1 16 graphical interface waveform comparison 11 305 GUL expression_format GUI expression builder 8 275 H Hazard ini file variable VLOG B 398 HDL item 1 20 Hierarchical profile 9 285 History shortcuts C 412 hm_entity 15 365 HOME environment variable B 393 ieee ini file variable B 396 TEEE libraries 3 51 IEEE std 1076 1 17 4 55 IEEE std 1364 1 17 5 73 IgnoreError ini file variable B 399 IgnoreFailure ini file variable B 399 IgnoreNote ini file variable B 399 Ignore VitalErrors ini file variable B 397 IgnoreWarning ini file variable B 399 ModelSim SE User s Manual Index 471 Incremental compilation automatic 5 77 manual 5 77 with Verilog 5 76 init_signal_spy 4 69 initial dialog box turning on off B 392 Initialization sequence 2 39 Installation locating the license file D 418 Instantiation in mixe
221. design has finer time precision As a result time values with finer precision are rounded to the nearest 100 ps Event order issues The Verilog language is defined such that the simulator is not required to execute simultaneous events in any particular order Unfortunately some models are inadvertently written to rely on a particular event order and these models may behave differently when ported to another Verilog simulator A model with event order dependencies is ambiguous and should be corrected For example the following code is ambiguous module top reg r initial r 0 initial r 1 initial 10 display r endmodule The value displayed for r depends on the order that the simulator executes the initial constructs that assign to r Conceptually the initial constructs run concurrently and the simulator is allowed to execute them in any order ModelSim Verilog executes the initial constructs in the order they appear in the module and the value displayed for r is 1 Verilog XL produces the same result but a simulator that displays 0 is not incorrect because the code is ambiguous Since many models have been developed on Verilog XL ModelSim Verilog duplicates Verilog XL event ordering as much as possible to ease the porting of those models to ModelSim Verilog However ModelSim Verilog does not match Verilog XL event ordering in all cases and if a model ported to ModelSim Verilog does not behave as expected the
222. ding signals with a log file 8 197 examining simulation results 8 184 formatting HDL items 8 181 locating time markers 8 153 saving to a file 8 189 setting display properties 8 178 setting triggers 8 179 E 444 Main window 8 157 status bar 8 168 text editing 8 168 C 413 time and delta display 8 168 toolbar 8 166 Process window 8 190 displaying active processes 8 190 specifying next process to be executed 8 190 viewing processing in the region 8 190 Signals window 8 193 VHDL and Verilog items viewed in 8 193 Source window 8 201 setting tab stops 8 209 text editing 8 168 C 413 viewing HDL source code 8 201 Structure window 8 210 HDL items viewed in 8 210 instance names 8 211 selecting items to view in Signals window 8 193 VHDL and Verilog items viewed in 8 210 viewing design hierarchy 8 210 Variables window 8 213 displaying values 8 213 VHDL and Verilog items viewed in 8 213 Wave window 8 216 adding HDL items 8 219 adding signals with a log file 8 197 changing display range zoom 8 240 changing path elements B 401 cursor measurements 8 240 locating time cursors 8 153 saving format file 8 219 searching for HDL item values 8 237 setting display properties 8 235 using time cursors 8 239 zoom options 8 240 zooming 8 240 Work library 3 42 workspace 8 158 write waveform comparison report 11 320 Z Zero delay loop detecting infinite E 436 Zoom from Wave toolbar buttons 8 241 from Zoom menu 8 240 options 8 240 saving range
223. dow opening a Source window if one is not open already Horizontal scroll bars for each window pane allow scrolling to the right or left in each pane individually The vertical scroll bar will scroll both panes together The HDL items can be sorted in ascending descending or declaration order HDL items you can view E signals sim El x File Edit View Window One entry is created for each of the following VHDL and Verilog items within the design clk VHDL items lk pstrb signals prdy 0 paddr 00000100 Verilog items pdata 0000000000000100 nets register variables named events srw and module parameters sstrb srdy Virtual items saddr 00000100 indicated by an orange diamond icon sdata 0000000000000 00 virtual signals and virtual functions see Virtual signals 7 144 for more information The names of any VHDL composite types arrays and record types are shown in a hierarchical fashion Hierarchy also applies to Verilog nets and vector memories Verilog vector registers do not have hierarchy because they are not internally represented as arrays Hierarchy is indicated in typical ModelSim fashion with plus expandable minus expanded and blank single level boxes See Tree window hierarchical view 8 155 for more information ModelSim SE User s Manual ModelSim Graphic Interface 8 193 Signals window The Signals window menu bar The following menu commands are available from the Sign
224. dyN is executed The then and else arguments are optional noise words to make the command easier to read There may be any number of elseif clauses including zero BodyN may also be omitted as long as else is omitted too The return value from the command is the result of the body script that was executed or an empty string if none of the expressions was non zero and there was no bodyN 16 374 Tcl and ModelSim ModelSim SE User s Manual Tcl commands set command syntax The Tcl set command reads and writes variables Note that in the syntax below the indicates an optional argument Syntax set varName value Description Returns the value of variable varName If value is specified then sets the value of varName to value creating a new variable if one doesnt already exist and returns its value If varName contains an open parenthesis and ends with a close parenthesis then it refers to an array element the characters before the first open parenthesis are the name of the array and the characters between the parentheses are the index within the array Otherwise varName refers to a scalar variable Normally varName is unqualified does not include the names of any containing namespaces and the variable of that name in the current namespace is read or written If varName includes namespace qualifiers in the array name if it refers to an array element the variable in the specified namespace is read or written If no pro
225. e B 392 ModelSim Variables ModelSim SE User s Manual Environment variables Environment variables Before compiling or simulating several environment variables may be set to provide the functions described in the table below The variables are in the autoexec bat file on Windows 95 98 machines and set through the System control panel on NT machines For UNIX the variables are typically found in the login script The LM_LICENSE_FILE variable is required all others are optional Model Sim Environment Variables Variable Description DOPATH used by ModelSim to search for simulator command files do files consists of a colon separated semi colon for Windows list of paths to directories optional this variable can be overridden by the DOPATH tcl file variable EDITOR specifies the editor to invoke with the edit command CR 110 HOME used by ModelSim to look for an optional graphical preference file and optional location map file see Preference variables located in INI files B 396 and Using location mapping E 437 LM_LICENSE_FILE used by the ModelSim license file manager to find the location of the license file may be a colon separated semi colon for Windows set of paths including paths to other vendor license files REQUIRED see Using the FLEXIm License Manager D 417 MODEL_TECH set by all ModelSim tools to the directory in which the binary executables reside YOU SHOULD NO
226. e A VCD file from source to output VCD simulator commands VCD output Capturing port driver data Supported TSSI states Strength values Port identifier code Example VCD output from ved ere 14 Logic Modeling SmartModels 14 353 VHDL SmartModel interface Creating foreign architectures oliha sm acti Vector ports Command channel SmartModel Windows Memory arrays Verilog SmartModel interface LMTV usage documentation Linking the LMTV interface to the sinaullates Compiling Verilog shells 15 Logic Modeling Hardware Models 15 363 VHDL Hardware Model interface Creating foreign architectures with hm canai Vector ports Hardware model commas 16 Tcl and ModelSim 16 369 Tcl features within ModelSim Tcl References Tcl commands Tcl command syntax if command syntax set command syntax Command substitution Command separator Multiple line commands Evaluation order 13 342 13 344 13 344 13 344 13 346 13 346 13 347 13 349 13 349 13 350 13 350 13 351 14 354 14 355 14 357 14 358 14 359 14 360 14 361 14 361 14 361 14 361 15 364 15 365 15 367 15 368 16 370 16 370 16 371 16 372 16 374 16 375 16 375 16 376 16 376 16 376 10 Table of Contents ModelSim SE User s Manual Tcl relational expression evaluation 16 376 Variable SODIO lt lt
227. e Properties from the context menu in Project tab Select the Edit Source button to view or edit a source file via the Compile dialog box See Source window 8 201 for additional source file editing information Locating source errors during compilation If a compiler error occurs during compilation a red error message is printed in the Main transcript Double click on the error message to open the source file in an editable Source window with the error highlighted ModelSim Al x File Edit Design View Project Run Compare Macro Options Window Help Zl feval compile Main vcom work test 87 explicit novital nowarn 1 nowarn 2 nowarn 3 nowarn 4 nowarn 5 E modelsim55_se exam ples adder vhd Model Technology ModelSim SE EE vcom 5 5 Alpha Compiler 20 00 07 Sep 13 2000 Loading package standard E Loading package toe 164 Compiling entity adder NE F s Compiling architecture rtl of adder File Edit Object Options Window H ERROR Could notfindtestgatef s PP eee eae Gog a ERROR E modelsim55_se examples ad d expandag name work gates ERROR E modelsim55_se examples ac field gates tH ERRNR F madelsimAR se evarmnles tar lt No Design Loaded gt zl a adder vhd laa counter vhd description of adder using componer architecture structural of adder is signal xorl_out andl_out and2_out orl_out std logic do
228. e brackets For example WARNING test v 2 TFMPC Too few port connections This warning message can be disabled with the nowarnTFMPC option This option treats all identifiers in the source code as all uppercase Options supporting source libraries The following options support source libraries in the same manner as Verilog XL Note that these libraries are source libraries and are very different from the libraries that the ModelSim compiler uses to store compilation results You may find it convenient to use these options if you are porting a design to ModelSim or if you are familiar with these options and prefer to use them Source libraries are searched after the source files on the command line are compiled If there are any unresolved references to modules or UDPs then the compiler searches the source libraries to satisfy them The modules compiled from source libraries may in turn have additional unresolved references that cause the source libraries to be searched again This process is repeated until all references are resolved or until no new unresolved references are found Source libraries are searched in the order they appear on the command line v lt filename gt This option specifies a source library file containing module and UDP definitions Modules and UDPs within the file are compiled only if they match previously unresolved references Multiple v options are allowed y lt directory gt This option spec
229. e gt Zoom Area a al a e E Zoom Full zoom out to view the full range of the simulation from time O to the current time Zoom gt Zoom Full keyboard f or F right mouse in wave pane gt Zoom Full ModelSim SE User s Manual ModelSim Graphic Interface 8 225 Wave window Wave window toolbar buttons Button Menu equivalent Other options Restart reloads the design elements and resets the simulation time to zero with the option of keeping the current formatting breakpoints and logfile Main menu Run gt Restart restart lt arguments gt see restart CR 170 Run run the current simulation for the default time length Main menu Run gt Run lt default_length gt use the run command at the VSIM prompt see run CR 176 Lu Continue Run continue the current simulation run Main menu Run gt Continue use the run continue command at the VSIM prompt see run CR 176 Run All run the current simulation forever or until it hits a breakpoint or Main menu Run gt Run All use run all command at the VSIM prompt find the last difference in a waveform comparison specified break event see run CR 176 also see Assertion settings page 8 266 Break none none stop the current simulation run Find First Difference none none ha find the first difference in a waveform comparison Find Previous Difference
230. e Eval entry supports a simple history mechanism available via the lt Up_arrow gt and lt Down_arrow gt keys If you evaluate a command while stepping through a procedure the command will be evaluated in the context of the procedure otherwise it will be evaluated at the global level The result will be displayed in the result field This entry is useful for a lot of things but especially to get access to variables outside the current scope ModelSim SE User s Manual ModelSim Graphic Interface 8 273 ModelSim tools Try entering the line global td_priv and watch the Variables box with global and array variables enabled of course ae treename wave tree wsimPriv signals 1 1 Configuration wsimPriw signals 0 1 You can customize TDebug by setting up a file wsimPriv signals gt 1 named tdebugrc in your home directory See the vsimPriv signals i 1 TDebug README at Help gt Technotes gt tdebug for more information on the configuration vsimPriv DisableB uttonList of TDebug vsimPriv DragDrop_DropHa vsimPriv DraoDrop_DropHa TclPro Debugger vsimPriv DragDrop_DropHa taima Dern Miranin T armana The Macro menu in the Main window contains a selection for the TclPro Debugger from Scriptics By a Corporation This debugger can be acquired from Delay 300 E Scriptics at their web site www scriptics com Once acquired do the following steps to use the TclPro Debugger Macro A ES Exec
231. e appropriate w f files vsim view wavesavl wlf Now you will be able to use the Waveform and List windows normally Setting up libraries for group use By adding an others clause to your modelsim ini file you can have a hierarchy of library mappings If the ModelSim tools don t find a mapping in the modelsim ini file then they will search the library section of the initialization file specified by the others clause For example library asic_lib cae asic_lib work my_work others usr modeltech modelsim ini Maintaining 32 bit and 64 bit modules in the same library It is possible with ModelSim to maintain 64 bit and 32 bit versions of a design in the same library To do this you must compile the design with one of the versions 64 bit or 32 bit and refresh the design with the other version For example Using the 32 bit version of ModelSim vcom filel vhd vcom file2 vhd Next using the 64 bit version of ModelSim vcom refresh Do not compile the design with one version and then recompile it with the other If you do this ModelSim will remove the first module because it could be stale E 434 Tips and Techniques ModelSim SE User s Manual Bus contention checking Bus contention checking Bus contention checking detects bus fights on nodes that have multiple drivers A bus fight occurs when two or more drivers drive a node with the same strength and that strength is the strongest o
232. e at 1 503 641 1340 from 8 00 AM to 5 00 PM Pacific Time Monday through Friday excluding holidays Be sure to have your server hostID ethernet card address or hardware security key authorization number handy gt Note Model Technology customers in Europe should contact their distributor for support See www model com contact_us asp for distributor contact information Mentor Graphics customers in North America For customers who purchased products from Mentor Graphics in North America and are under a current support contract technical telephone support is available from the central SupportCenter by calling toll free 1 800 547 4303 The coverage window is from 5 30am to 5 30pm Pacific Time Monday through Friday excluding Mentor Graphics holidays The more details you can supply about a problem or issue the sooner a Corporate Application Engineer can supply you with a solution or workaround Be prepared to provide the following important information e The priority of the call critical high medium low e The product about which you are calling e Your operating system and software version numbers accuracy is very important here e The steps that led to the problem or crash e If it is a crash the first few lines of a traceback e Any non Mentor Graphics tools or customized software that may be involved Mentor Graphics customers outside North America Customers who purchased products from Mentor Graphics outside of North Amer
233. e command CR 236 can be used to hide the display of the broken down bits if you dont want them cluttering up the Signals window If the virtual signal has elements from more than one logfile 1t will be automatically installed in the virtual region virtuals Signals Virtual signals are not hierarchical if two virtual signals are concatenated to become a third virtual signal the resulting virtual signal will be a concatenation of all the subelements of the first two virtual signals The definitions of virtuals can be saved to a macro file using the virtual save command CR 243 By default when quitting ModelSim will append any newly created virtuals that have not been saved to the virtuals do file in the local directory If you have virtual signals displayed in the Wave or List window when you save the Wave or List format you will need to execute the virtuals do file or some other equivalent to restore the virtual signal definitions before you re load the Wave or List format during a later run There is one exception implicit virtuals are automatically saved with the Wave or List format Implicit and explicit virtuals An implicit virtual is a virtual signal that was automatically created by ModelSim without your knowledge and without you providing a name for it An example would be if you expand a bus in the Wave window then drag one bit out of the bus to display it separately That action creates a one bit virtual signal wh
234. e eee 8 209 The Bitton Adder so s soe ee d ROR A Oe ewe eee we ee a 8209 The Macro Helper o s cocon e ea BO a ada er ec a OZ O The Tcl Debugger E A The GUI Expression Builder ood beh BOS we Sok bee Bb amp Sake a bo bk ae ch ZO Graphic Interlace commands s lt sos soe g Bee RE Dae e SBR TT Customizing the imterface lt lt co p os cos s poed noe g eo aope pooo pon ee eo 18279 9 Performance Analyzer 9 281 Introducing Performance Analysis 2 a ee ee ee ee ee eee 9282 A Statistical Sampling Profiler 2 7 na n ee 9 282 o m eor s on oe BE ee ae Ok ee eo BE S i amp 96283 Interpreting the data Po Mek OM oe a a e ee a 92289 Viewing Performance ln Results at Ble we ia oe BE ee ee ee 0284 Interpreting the Name Field be Soe doe a we 2 a 92286 Interpreting the Under and In Fields a 2286 Differences in the Ranked and Hierarchical Views 2 9287 Ranked Hierarchical Profile Window Features 2 2 1 ee 9288 Thereportoption 2 s s ss x e w es seser ee eee ey eo 9289 Setting preferences with Tcl variables 5 6 3 0 a ee o 9 290 Performance Analyzer commands 2 6 64 esos s weon o t 2 00 o e 2290 10 Code Coverage 10 291 Enabline Code Coverage 2 coeja ss ee ee e e a a 10 292 The coverage_summary window gt s so so esoe ar em one tosa 10292 Summary information e 10 293 Misses tabi c s 6 bos a tased ado momo w
235. e end of time step event scheduled by tf_synchronize reason_rosynch For the end of time step event scheduled by tf_rosynchronize reason_reactivate For the simulation event scheduled by tf_setdelay reason_paramdrc Not supported in ModelSim Verilog reason_force Not supported in ModelSim Verilog reason_release Not supported in ModelSim Verilog reason_disable Not supported in ModelSim Verilog 5 118 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI The sizetf callback function A user defined system function specifies the width of its return value with the sizetf callback function and the simulator calls this function while loading the design The following details on the sizetf callback function are not found in the IEEE Std 1364 e If you omit the sizetf function then a return width of 32 is assumed e The sizetf function should return 0 if the system function return value is of Verilog type real e The sizetf function should return 32 if the system function return value is of Verilog type integer PLI object handles Many of the object handles returned by the PLI ACC routines are pointers to objects that naturally exist in the simulation data structures and the handles to these objects are valid throughout the simulation even after the acc_close routine is called However some of the objects are created on demand and the handles to these objects become invalid after a
236. e libsm entry points to the ModelSim dynamic link library that interfaces the foreign architecture to the SmartModel software The libswift entry points to the Logic Modeling dynamic link library software that accesses the SmartModels The simulator automatically loads both the libsm and libswift libraries when it elaborates a SmartModel foreign architecture By default the libsm entry points to the libsm s supplied in the ModelSim installation directory indicated by the MODEL_TECH environment variable ModelSim automatically sets the MODEL_TECH environment variable to the appropriate directory containing the executables and binaries for the current operating system If you are running the Windows operating system then you must comment out the default libsm entry precede the line with the character and uncomment the libsm entry for the Windows operating system Uncomment the appropriate libswift entry for your operating system The LMC_HOME environment variable must be set to the root of the SmartModel library installation directory Consult Logic Modeling s SmartModel library documentation for details 14 354 Logic Modeling SmartModels ModelSim SE User s Manual VHDL SmartModel interface Creating foreign architectures with sm_entity The ModelSim sm_entity tool automatically creates entities and foreign architectures for SmartModels Its usage is as follows Syntax sm_entity xe xa c all v 93 lt
237. e of tracing files The purpose of the logfile is to aid you in debugging PLI or VPI code The primary purpose of the replay facility is to send the replay file to MTI support for debugging co simulation problems or debugging PLI VPI problems for which it is impractical to send the PLI VPI code We still need you to send the VHDL Verilog part of the design to actually execute a replay but many problems can be resolved with the trace only Invoking a trace To invoke the trace call vsim CR 258 with the trace_foreign option Syntax vsim trace_foreign lt action gt tag lt name gt ModelSim SE User s Manual Verilog Simulation 5 125 Using the Verilog PLI VPI Arguments lt action gt Specifies one of the following actions Action Result create log only writes a local file called mti_trace_ lt tag gt create replay only writes local files called mti_data_ lt tag gt c mti_init_ lt tag gt c mti_replay_ lt tag gt c and mti_top_ lt tag gt c create both log and replay tag lt name gt Used to give distinct file names for multiple traces Optional Examples vsim trace_foreign 1 mydesign Creates a logfile vsim trace_foreign 3 mydesign Creates both a logfile and a set of replay files vsim trace_foreign 1 tag 2 mydesign Creates a logfile with a tag of 2 The tracing operations will provide tracing during all user foreign code calls including PLI VPI user tas
238. e report command 9 289 Project files modelsim ini MODELSIM environment variable B 393 modelsim mpf project definition 2 26 projects accessing from the command line 2 36 adding files to 2 31 changing compile order 2 34 compiling the files 2 32 creating 2 29 customizing settings 2 34 differences in 5 5 2 27 loading a design 2 33 setting compiler options in 2 35 protect compiler directive E 433 Q Quiet ini file variable VCOM B 397 Quiet ini file variable VLOG B 398 R Radix specifying in List window 8 182 specifying in Signals window 8 196 Ranked profile 9 287 real type converting to time 4 71 Rebuilding supplied libraries 3 51 Reconstruct RTL level design busses 7 145 Records changing values of 8 213 reference region 11 311 reference signals 11 302 Refreshing library images 3 51 Register variables adding to the Wave and List windows 8 197 displaying values in Signals window 8 193 saving values as binary log file 8 197 viewing waveforms 8 216 RequireConfigForAllDefaultBinding variable B 397 Resolution 4 58 resolution 4 68 Resolution ini file variable B 400 resolution simulator state variable B 408 Resource library 3 42 Restart 8 163 8 166 8 226 restart command defaults B 405 Restoring defaults B 392 RunLength ini file variable B 400 S save differences 11 320 Saving and viewing waveforms 7 137 8 220 ScalarOpts ini file variable B 397 B 398 SDF errors and warnings 12 327 instance specificat
239. e strings are not case sensitive The default is max 15 366 Logic Modeling Hardware Models ModelSim SE User s Manual VHDL Hardware Model interface Vector ports Architecture details e The first part of the foreign attribute string hm_ init is the same for all hardware models e The second part MODEL_TECH libhm sl is taken from the libhm entry in the initialization file modelsim ini e The third part CY7C285 MDL is the shell software filename This name correlates the architecture with the hardware model at elaboration The entities generated by hm_entity only contain single bit ports never vectored ports However for ease of use in component instantiations you may want to create a custom component declaration and component specification that groups ports into vectors You can also rename and reorder the ports in the component declaration You can also reorder the ports in the entity declaration but you can t rename them The following is an example component declaration and specification that groups the address and data ports of the CY7C285 hardware model component cy7c285 generic DelayRange STRING Max port A in std_logic_vector 15 downto 0 CS in std_logic O out std_logic_vector 7 downto 0 WAIT_PORT inout std_logic end component for alls sey 7e285 use entity work cy7c285 port map AO gt A 0 Al gt A 1 A2 gt A 2 A3 gt A 3 A4 gt A A
240. e variable is defined it will be invoked 3 If neither 1 or 2 is true the macro aborts ModelSim SE User s Manual Tips and Techniques E 431 Using macros DO files Using the Tcl source command with DO files Either the do command or Tel source command can execute a DO file but they behave differently With the source command the DO file is executed exactly as if the commands in it were typed in by hand at the prompt Each time a breakpoint is hit the Source window is updated to show the breakpoint This behavior could be inconvenient with a large DO file containing many breakpoints When a do command is interrupted by an error or breakpoint it does not update any windows and keeps the DO file locked This keeps the Source window from flashing scrolling and moving the arrow when a complex DO file is executed Typically an onbreak resume command is used to keep the macro running as it hits breakpoints Add an onbreak abort command to the DO file if you want to exit the macro and update the Source window See also See the do command CR 104 Also see the DOPATH B 393 variable for adding a DO file path to your environment E 432 Tips and Techniques ModelSim SE User s Manual Source code security and nodebug Source code security and nodebug The nodebug option on both vcom CR 217 and vlog CR 250 hides internal model data This allows a model supplier to provide pre compiled libraries without providi
241. e variables located in INI files B 396 B 406 ModelSim Variables ModelSim SE User s Manual Preference variable loading order Preference variable loading order A ModelSim tcl ini and mpf files all contain variables that are loaded when you start ModelSim The files are evaluated for variable settings in the order below tcl file variables are evaluated before the design is loaded ModelSim evaluates tcl files prior to loading a design for simulation Any window user_hook_variables are evaluated after the associated window type is created The lt install_dir gt modeltech tcl vsim pref tcl file is always loaded The file specified by the MODELSIM_TCL B 393 environment variable is loaded next If MODELSIM_TCL does not exist the modelsim tcl in the current directory is evaluated If MODELSIM_TCL and modelsim tcl do not exist the file specified by the HOME B 393 environment variable is used ini and mpf file variables are evaluated after the design is loaded After the design is loaded ini or mpf file variables are found in these locations First the location specified by the MODELSIM B 393 environment variable If no MODELSIM variable exists Mode Sim looks for mpf and ini files in the locations shown below Project files mpf are evaluated first if no project file is found ModelSim looks for an ini file in the same location Next in the current directory if no MODELSIM variable exists Then
242. eaches a particular value Select the signal in the Wave window and click Insert Reference Signal and Then click the value buttons or type a value To evaluate only on clock edges Click the amp amp button to AND this condition with the rest of the expression Then select the clock in the Wave window and click Insert Reference Signal and rising You can also select the falling edge or both edges Operators Other buttons will add operators of various kinds see Expression syntax CR 302 or you can type them in To save the expression as a Tcl variable The Save button allows you to save the expression to a Tcl variable See Setting up a List trigger with Expression Builder E 444 for an additional Expression builder example 8 276 ModelSim Graphic Interface ModelSim SE User s Manual Graphic interface commands Graphic interface commands The following commands provide control and feedback during simulation as well as the ability to edit and add menus and buttons to the interface Only brief descriptions are provided here for more information and command syntax see the ModelSim Command Reference Window control and feedback commands Description batch_mode CR 42 returns a if ModelSim is operating in batch mode otherwise returns a 0 it is typically used as a condition in an if statement configure CR 88 invokes the List or Wave widget configure command for the current default L
243. ecifies how signals from different datasets are displayed Always Show Dataset Prefixes All dataset prefixes will be displayed along with the dataset prefix of the current simulation sim Show Dataset Prefixes if 2 or more Displays all dataset prefixes if 2 or more datasets are displayed sim is the default prefix for the current simulation Never Show No Dataset Prefixes No dataset prefixes will be displayed This selection is useful if you are running only a single simulation Sorting a group of HDL items Select Edit gt Sort to sort the items in the pathname and values panes Setting signal breakpoints You can set signal breakpoints a k a when breakpoints see the when command CR 273 or Setting signal breakpoints 8 198 for more details using a pop up menu Start by selecting a signal and then clicking your second Windows or third UNIX mouse button Select Signal Breakpoints from the pop up menu and you ll see six items e Add Creates a signal breakpoint on the selected signal Edit Breakpoints Opens the Edit When dialog See Setting signal breakpoints 8 198 for more information Edit All Breakpoints Opens the Breakpoints dialog See Setting file line breakpoints 8 205 for more information Remove Signal Removes the signal breakpoint from the selected signal Remove All Signals Removes all signal breakpoints Show All Shows a list of all signal breakpoints When a breakpoint is hit a mes
244. ecture associated with the entity not present for Verilog When you select a region in the Structure window it becomes the current region and is highlighted the Source window 8 201 and Signals window 8 193 change dynamically to reflect the information for that region This feature provides a useful method for finding the source code for a selected region because the system keeps track of the pathname where the source is located and displays it automatically without the need for you to provide the pathname Also when you select a region in the Structure window the Process window 8 190 is updated if In Region is selected in that window the Process window will in turn update the Variables window 8 213 The Structure window menu bar The following menu commands are available from the Structure window menu bar File menu Save As save the structure tree to a text file viewable with the ModelSim notepad CR 141 Environment allow the window contents to change when the active dataset is changed or fix to a specific dataset Close close this copy of the Structure window you can create a new window with View gt New from the The Main window menu bar 8 160 Edit menu Copy copy the current selection in the Structure window Sort sort the structure tree in either ascending descending or declaration order Expand Selected expand the hierarchy of the selected item Collapse Selected collapse the hierarch
245. ed MODEL_TECH_TCL identifies the path to all Tcl libraries installed with ModelSim HOME identifies your login directory UNIX only MGC_HOME identifies the path to the MGC tool suite TCL_LIBRARY identifies the path to the Tcl library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology TK_LIBRARY identifies the path to the Tk library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology TIX_LIBRARY identifies the path to the Tix library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology ITCL_LIBRARY identifies the path to the incr Tcl library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology ITK_LIBRARY identifies the path to the incr Tk library set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology VSIM_LIBRARY identifies the path to the Tcl files that are used by ModelSim set by ModelSim to the same path as MODEL_TECH_TCL must point to libraries supplied by Model Technology MTI_LIB_DIR identifies the path to all Tcl libraries installed with ModelSim 2 38 Projects and system initialization ModelSim SE User s Manual System initialization Environment variable Purpose MODELSIM_TCL identifie
246. ed design unit and opens a structure page in the workspace Related command line command is vsim CR 258 e Edit Opens the selected design unit in the Source window Refresh Rebuilds the library image of the selected item s without using source code Related command line command is vcom CR 217 with the refresh argument Recompile Recompiles the selected design unit Related command line command is vcom CR 217 Delete Deletes the selected design unit Related command line command is vdel CR 222 Deleting a package configuration or entity will remove the design unit from the library If you delete an entity that has one or more architectures the entity and all its associated architectures will be deleted ModelSim SE User s Manual Design libraries 3 45 Working with design libraries You can also delete an architecture without deleting its associated entity Expand the entity right click the desired architecture name and select Delete You are prompted for confirmation before any design unit is actually deleted The second context menu has the following options e Load Opens the Load Design dialog box See Simulating with the graphic interface 8 256 for details Related command line command is vsim CR 258 Create Library Opens the Create a New Library dialog box See Creating a library 3 43 earlier in this chapter for details Related command line command is vlib CR 249 e View Provides various op
247. ee Searching for binary signal values in the GUI CR 300 for details on how signal values are mapped between a binary radix and std_logic e Search Type Search for Expression Searches for the expression specified in the Expression field evaluating to a boolean true Activates the Builder button so you can use The GUI Expression Builder 8 275 if desired The expression can involve more than one signal but is limited to signals logged in the List window Expressions can include constants variables and DO files If no expression is specified the search will give an error See Expression syntax CR 302 for more information Search Options Match Count Indicates the number of transitions or matches to search You can search for the n th transition or the n th match on value Search Options Ignore Glitches Ignores zero width glitches in VHDL signals and Verilog nets The Search Results are indicated at the bottom of the dialog box 8 186 ModelSim Graphic Interface ModelSim SE User s Manual List window Setting time markers in the List window Select Markers gt Add Marker List window to tag the selected list line with a marker The marker is indicated by a thin box surrounding the marked line The selected line uses the same indicator but its values are highlighted Delete markers by first selecting the marked line then selecting Markers gt Delete Marker Finding a marker FS list Miel File Edit Markers Pr
248. efault Same as the 93 switch for the vcom command CR 217 Edit the VHDL93 B 405 variable in the modelsim ini file to set a permanent default Don t put debugging info in library Models compiled with this option do not use any of the ModelSim debugging features Consequently your user will not be able to see into the model This also means that you cannot set breakpoints or single step within this code Don t compile with this option until you re done debugging Same as the nodebug switch for the vcom command CR 217 See Source code security and nodebug E 433 for more details Edit the NoDebug B 397 variable in the modelsim ini file to set a permanent default 8 252 ModelSim Graphic Interface ModelSim SE User s Manual Compiling with the graphic interface e Use explicit declarations only Used to ignore an error in packages supplied by some other EDA vendors directs the compiler to resolve ambiguous function overloading in favor of the explicit function definition Same as the explicit switch for the vcom command CR 217 Edit the Explicit B 397 variable in the modelsim ini file to set a permanent default Although it is not intuitively obvious the operator is overloaded in the std_logic_1164 package All enumeration data types in VHDL get an implicit definition for the operator So while there is no explicit operator there is an implicit one This implicit declaration can be hidden by an explicit decl
249. egin net task or register variable 1 20 Introduction ModelSim SE User s Manual Where to find our documentation Where to find our documentation ModelSim documentation is available from our website at model com support documentation asp or in the following formats and locations Document Format How to get it Start Here for ModelSim SE installation amp support reference paper shipped with ModelSim PDF select Main window gt Help gt SE Documentation also available from the Support page of our web site www model com ModelSim SE Quick Guide command and feature quick reference shipped with ModelSim select Main window gt Help gt SE Documentation also available from the Support page of our web site www model com ModelSim SE Tutorial select Main window gt Help gt SE Documentation also available from the Support page of our web site www model com ModelSim SE User s Manual select Main window gt Help gt SE Documentation ModelSim SE Command Reference select Main window gt Help gt SE Documentation ModelSim Foreign Language Interface Reference select Main window gt Help gt SE Documentation ModelSim Command Help type help command name at the prompt in the Main window Tcl Man Pages Tcl manual select Main window gt Help gt Tcl Man Pages or find contents htm in nodeltech tcl_help_html techno
250. ejection limit is not specified then it defaults to the error limit For example consider a path delay of 10 along with a pulse_e 80 option The error limit is 80 of 10 and the rejection limit defaults to 80 of 10 This results in the propagation of pulses greater than or equal to 8 while all other pulses are filtered Note that you can force specify path delays to operate in transport mode by using the pulse_e 0 option pulse_int_e lt percent gt This option is analogous to pulse_e except it applies to interconnect delays only pulse_int_r lt percent gt This option is analogous to pulse_r except it applies to interconnect delays only pulse_r lt percent gt This option controls how pulses are propagated through specify path delays where lt percent gt is a number between 0 and 100 that specifies the rejection limit as a percentage of the path delay A pulse less than the rejection limit is suppressed from propagating to the output If the error limit is not specified see pulse_e 5 88 then it defaults to the rejection limit t pulse_e_style_ondetect This option selects the on detect style of propagating pulse errors see pulse_e lt percent gt A pulse error propagates to the output as an X and the on detect style is to schedule the X immediately as soon as it has been detected that a pulse error has occurred The on event style is the default for propagating pulse errors see tpulse_e_style_onevent p
251. elSim When you use vmap CR 257 this way you are modifying the modelsim ini file You can also modify modelsim ini manually by adding a mapping line To do this edit the modelsim ini file using any text editor and add a line under the Library section heading using the syntax lt logical_name gt lt directory_pathname gt More than one logical name can be mapped to a single directory For example suppose the modelsim ini file in the current working directory contains following lines Library work usr rick design my_asic usr rick design This would allow you to use either the logical name work or my_asic in a library or use clause to refer to the same design library Unix symbolic links You can also create a UNIX symbolic link to the library using the host platform command ln s lt directory_pathname gt lt logical_name gt The vmap command CR 257 can also be used to display the mapping of a logical library name to a directory To do this enter the shortened form of the command vmap lt logical_name gt Library search rules The system searches for the mapping of a logical name in the following order e First the system looks for a modelsim ini file e If the system doesn t find a modelsim ini file or if the specified logical name does not exist in the modelsim ini file the system searches the current working directory for a subdirectory that matches the logical name An error is generated by the compile
252. elSim SE User s Manual Design libraries 3 51 Specifying the resource libraries vcom work mylib refresh vlog work mylib refresh An important feature of refresh is that it rebuilds the library image without using source code This means that models delivered as compiled libraries without source code can be rebuilt for a specific release of ModelSim 4 6 and later only In general this works for moving forwards or backwards on a release Moving backwards on a release may not work if the models used compiler switches or directives Verilog only that do not exist in the older release gt Note You don t need to regenerate the std ieee vital22b and verilog libraries Also you cannot use the refresh option to update libraries that were built before the 4 6 release Verilog resource libraries ModelSim supports and encourages separate compilation of distinct portions of a Verilog design The vlog CR 250 compiler is used to compile one or more source files into a specified library The library thus contains pre compiled modules and UDPs and perhaps VHDL design units that are referenced by the simulator as it loads the design See Library usage 5 78 Maintaining 32 bit and 64 bit versions in the same library It is possible with ModelSim to maintain 32 bit and 64 bit versions of a design in the same library To do this you must compile the design with one of the versions 32 bit or 64 bit and refresh the design with
253. elSim screen that opens the first time you start ModelSim If this screen is not available you can enable it by selecting Help gt Enable Welcome Main window Welcome to ModelSim A ES Create a New Project Specify a name for the new project and it will be created and opened Create a Project T Do not show this dialog again You can also use the File gt New gt Project Main window command to create a new project 2 Clicking the Create a Project button opens the Create Project dialog box Create Project Project Name test Project Location E modelsim55 projects Browse Default Library Name work Ok Cancel ModelSim SE User s Manual Projects and system initialization 2 29 Getting started with projects 3 Specify a Project Name and Project Location The location is where the project mpf file and any copied source files will be stored You can leave the Default Library Name set to work or specify a different name if desired The name that is specified will be used to create a working library subdirectory within the Project Location After selecting OK you will see a blank Project page in the workspace area of the Main window You can hide or show the workspace at any time using the View gt Hide Show Workspace command l ModelSim 101 x File Edit Design view Diaa Run Macro Options Window Help Reading E modelsim55_se win32 2 tol vsimepref tol
254. eleting with the mouse 8 205 enabling and disabling 8 207 setting file line beakpoints 8 205 setting signal breakpoints 8 198 setting with the mouse 8 205 viewing in the Source window 8 201 Busses user defined 8 154 Button Adder add buttons to windows 8 269 C Cell libraries 5 97 Checkpoint restore E 426 CheckpointCompressMode ini file variable B 398 CheckSynthesis ini file variable B 396 clear differences 11 320 clocked comparison 11 303 11 308 11 312 Code Coverage coverage report command 10 300 coverage_summary window 10 292 enabling code coverage 10 292 10 300 excluding lines and files 10 293 10 296 invoking code coverage with vsim 4 59 miss and exclusion details 10 293 saving coverage reports 10 294 Tcl preference variables 10 300 Command reference 1 19 CommandHistory ini file variable B 398 Command line mode E 428 Commands graphic interface commands 8 277 VSIM Tel commands 16 378 commands compare commands 11 323 compare add clock 11 309 add region 11 311 add signals 11 307 by signal 11 307 clear differences 11 320 clocked 11 303 11 308 11 312 command line interface 11 323 continuous 11 303 11 310 11 313 difference markers 11 317 differences 11 321 end 11 319 graphical interface 11 305 icons 11 318 limit count 11 314 list window display 11 322 menu 11 318 modify clock 11 309 options 11 314 pathnames 11 317 preference variables 11 323 reference dataset 11 305 reference
255. ello io_printf Hi there n s_tfcell veriusertfs usertask 0 0 0 hello 0 Shello 10 last entry must be 0 y hello v module hello initial Shello endmodule Compile the PLI code for the Solaris operating system cc c I lt install_dir gt modeltech include hello c ld G o hello sl hello o ale le Compile the Verilog code vlib work vlog hello v 2 2 Simulate the design vsim c pli hello sl hello Loading work hello Loading hello sl VSIM 1 gt run all Hi there VSIM 2 gt quit VPI example The following example is a trivial but complete VPI application hello c include vpi_user h static hello vpi_printf Hello world n void RegisterMyTfs void s_vpi_systf_data systf_data systf_data type vpiSysTask systf_data sysfunctype vpiSysTask systf_data tfname Shello systf_data calltf hello systf_data compiletf 0 systf_data sizetf 0 5 116 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI systf_data user_data 0 vpi_register_systf amp systf_data vpi_free_object systf_handle void vlog_startup_routines RegisterMyTfs 0 y hello v module hello initial Shello endmodule Compile the VPI code for the Solaris operating system ole gcc c I lt install_dir gt include hello c ld G o hello sl hello o ole Compile the Verilog code ole
256. elow retrieve vhd 35 was selected in the Hierarchical Profile and consequently is highlighted in the Source window Bj profile_source retrieve vhd of E File Edit Object Options Window SO BBA OP Produces the decode logic which pointers to each location of the shift register retriever PROCESS buffers ramadrs counter_size downto 0 BEGIN for i in 0 to buffer_size 1 loop JF ff FINIDO STE PIS rd0a lt buffers i END IF end loop END PROCESS mda lt rd0a and outstrobe END RTL The actual line of VHDL code for retrieve vhd 35 is IF i ramadrs counter_size 1 downto 0 THEN Differences in the Ranked and Hierarchical Views The hierarchical view differs from the ranked view in two important respects e Entries in the Name column of the hierarchical view are indented in order to show which functions or routines call which others e A Parent column in the hierarchical view allows you to see what percentage of a parent routine s simulation time is used in which subroutines Indentation in the Name column of the Hierarchical Profile window indicates which line is calling a function For example in the hierarchical view above the line store vhd 43 calls ieee_src mti_std_logic_unsigned vhd 429 The hierarchical view presents data in a call graph style format that provides more context than does the ranked view about where simulation time is spent For example your models may
257. en 1 ModelSim SE User s Manual ModelSim Variables B 405 Preference variables located in TCL files Preference variables located in TCL files ModelSim TCL preference variables give you control over fonts colors prompts window positions and other simulator window characteristics Preference files which contain Tcl commands that set preference variables are loaded before any windows are created and so will affect all windows For complete documentation on Tcl preference variables see the following URL http www model com resources pref_variables frameset htm When ModelSim is invoked for the first time default preferences are loaded from the pref tcl file Customized variable settings may be set from within the ModelSim GUI on the ModelSim command line or by directly editing the preference file The default file for customized preferences is modelsim tcl If your preference file is not named modelsim tcl you must refer to it with the MODELSIM_TCL B 393 environment variable User defined variables Temporary user defined variables can be created with the Tcl set command Like simulator variables user defined variables are preceded by a dollar sign when referenced To create a variable with the set command set userl 7 You can use the variable in a command like echo userl Suserl1 More preferences Additional compiler and simulator preferences may be set in the modelsim ini and MPF files see Preferenc
258. enabled for the nets and registers that it operates on Suppose you want to dump all nets and registers in the entire design and that you have the following dumpvars call in your testbench no arguments to dumpvars means to dump everything in the entire design initial S dumpvars Then you need to compile your design as follows to enable net and register access for all modules in the design vlog fast acc rn testbench v design v As another example suppose you only need to dump nets and registers of a particular instance in the design the first argument of 1 means to dump just the variables in the instance specified by the second argument initial S dumpvars 1 testbench ul Then you need to compile your design as follows assuming testbench ul refers to a module named design vlog fast acc rn design testbench v design v ModelSim SE User s Manual Verilog Simulation 5 95 Compiling for faster performance Finally suppose you need to dump everything in the children instances of testbench ul the first argument of O means to also include all children of the instance initial dumpvars 0 testbench ul Then you need to compile your design as follows vlog fast acc rn design testbench v design v To gain maximum performance it may be necessary to enable the minimum required access within the design Using pre compiled libraries When using the fast option 1f the source code is unavailable for any
259. ent view e Selected Print all selected signals Time Range e Full Range Print all specified signals in the full simulation range e Current view Print the specified signals for the viewable time range e Custom Print the specified signals for a user designated From and To time Setup button See Printer Page Setup 8 248 ModelSim SE User s Manual ModelSim Graphic Interface 8 247 Wave window Printer Page Setup Clicking the Setup button in the Write Postscript or Print dialog box allows you to define the following options this is the same dialog that opens via File gt Page setup Paper Size Select your output page size from a number of options also choose the paper width and height Margins Specify the page margins changing the Margin will change the Scale and Page specifications Label width Specify Auto Adjust to accommodate any length label or set a fixed label width Cursors Turn printing of cursors on or off Grid Turn printing of grid lines on or off 8 248 ModelSim Graphic Interface ModelSim SE User s Manual Wave window e Color Select full color printing grayscale or black and white e Scaling Specify a Fixed output time width in nanoseconds per page the number of pages output is automatically computed or select Fit to to define the number of pages to be output based on the paper size and time settings if set the time width per page is automatically computed
260. entry points to the libhm sl supplied in the ModelSim installation directory indicated by the MODEL_TECH environment variable ModelSim automatically sets the MODEL_TECH environment variable to the appropriate directory containing the executables and binaries for the current operating system If you are running the Windows operating system then you must comment out the default libhm entry precede the line with the character and uncomment the libhm entry for the Windows operating system Uncomment the appropriate libsfi entry for your operating system and replace lt sfi_dir gt with the path to the hardware modeler software installation directory In addition you must set the LM_LIB and LM_DIR environment variables as described in the Logic Modeling documentation 15 364 Logic Modeling Hardware Models ModelSim SE User s Manual VHDL Hardware Model interface Creating foreign architectures with hm_entity The ModelSim hm_entity tool automatically creates entities and foreign architectures for hardware models Its usage is as follows Syntax hm_entity xe xa c 93 lt shell software filename gt Arguments xe Do not generate entity declarations xa Do not generate architecture bodies G Generate component declarations 93 Use extended identifiers where needed lt shell software filename gt Hardware model shell software filename see Logic Modeling documentation for details on shell software file
261. ep All signals in the following illustration are the same top clk signal Starting with analog step the top clk signal has been relabeled to illustrate each different wave format wave default Ele File Edit Cursor Zoom Compare Bookmark Format Window oh te RK Ai RQA Elia ftop clk analog step analog interpolated analog backstep literal logic event Ons to 306 ns Analog Step Displays a waveform in step style Analog Interpolated Displays the waveform in interpolated style Analog Backstep Displays the waveform in backstep style Often used for power calculations Offset and Scale Allows you to adjust the scale of the item as it is seen on the display Offset is the number of pixels offset from zero The scale factor reduces if less than 1 or increases if greater than 1 the number of pixels displayed Only the following types are supported in Analog format VHDL types All vectors std logic vectors bit vectors and vectors derived from these types Scalar integers Scalar reals Scalar time Verilog types All vectors Scalar real Scalar integers ModelSim SE User s Manual ModelSim Graphic Interface 8 233 Wave window e Height Allows you to specify the height in pixels of the waveform Wave Signal Properties The Compare tab includes the same options as those in the Add Signal Options dialog box see Adding Signals Regions and or Clocks 11 307 8 234 Mode
262. ere is no limit to the number of libraries that can be referenced but only one library is modified during compilation 3 50 Design libraries ModelSim SE User s Manual Specifying the resource libraries Alternate IEEE libraries supplied The installation directory may contain two or more versions of the IEEE library ieeepure Contains only IEEE approved std_logic_1164 packages accelerated for ModelSim ieee Contains precompiled Synopsys and IEEE arithmetic packages which have been accelerated by Model Technology including math_complex math_real numeric_bit numeric_std std_logic_1164 std_logic_misc std_logic_textio std_logic_arith std_logic_signed std_logic_unsigned vital_primitives vital_timing and vital_memory You can select which library to use by changing the mapping in the modelsim ini file The modelsim ini file in the installation directory defaults to the ieee library VITAL 2000 library ModelSim versions 5 5 and later include a separate VITAL 2000 library that contains an accelerated vital_memory package You ll need to add a use clause to your VHDL code to access the package For example LIBRARY vital2000 USE vital2000 vital_memory all Also when you compile use the vital2000 switch to vcom CR 217 Rebuilding supplied libraries Resource libraries are supplied precompiled in the modeltech installation directory If you need to rebuild these libraries the sources are provided in the vhdl
263. es see http www model com resources pref_variables frameset htm Save Preferences Window menu save current ModelSim settings to a Tcl preference file see http www model com resources pref_variables frameset htm Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window 8 164 ModelSim Graphic Interface ModelSim SE User s Manual Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 Help menu About ModelSim display ModelSim application information e g software version Release Notes view current release notes with the ModelSim notepad CR 141 Enable Welcome enable the Welcome screen for starting a new project or opening an existing project when ModelSim
264. espectively vsim t ps topmod vsim t 10ps topmod Note that there is no space between the value and the units i e 10ps not 10 ps The default time resolution can also be changed by modifying the Resolution B 400 variable in the modelsim ini file You can view the current resolution by invoking the report command CR 168 with the simulator state option See Preference variables located in INI files B 396 for more information on modifying the modelsim ini file vsim CR 258 is capable of annotating a design using VITAL compliant models with timing data from an SDF file You can specify the min typ max delay by invoking vsim with the sdfmin sdftyp and sdfmax options Using the SDF file f7 sdf in the current work directory the following invocation of vsim annotates maximum timing values for the design unit my_asic vsim sdfmax my_asic fl sdf my_asic Timing check disabling By default the timing checks within VITAL models are enabled They can be disabled with the notimingchecks option For example vsim notimingchecks topmod 4 58 VHDL Simulation ModelSim SE User s Manual Simulating VHDL designs Invoking Code Coverage with vsim ModelSim s Code Coverage feature gives you graphical and report file feedback on how the source code is being executed It allows line number execution statistics to be kept by the simulator It can be used during any design phase and in all levels and types of designs For com
265. ets default behavior for the restart commented force command out nobreakpoint nolist nolog nowave DelayFileOpen 0 1 if 1 open VHDL87 files on first read or off 0 write else open files when elaborated GenerateFormat Any non quoted control the format of a generate statement s__ d string containing label don t quote it at a minimum a s followed by a od IgnoreError 0 1 if 1 ignore assertion errors off 0 IgnoreFailure 0 1 if 1 ignore assertion failures off 0 IgnoreNote 0 1 if 1 ignore assertion notes off 0 IgnoreWarning 0 1 if 1 ignore assertion warnings off 0 IterationLimit positive integer limit on simulation kernel iterations during 5000 one time delta ModelSim SE User s Manual ModelSim Variables B 399 Preference variables located in INI files Variable name Value range Purpose Default License any single if set controls ModelSim license file search all lt license_option gt search license options include licenses nomgc excludes MGC licenses nomti excludes MTI licenses noqueue do not wait in license queue if no licenses are available plus only use PLUS license vlog only use VLOG license vhdl only use VHDL license viewsim accepts a simulation license rather than being queued for a viewer license see also the vsim command CR 258 lt license_option gt LockedMemory positive integer for HP UX 10 2 use only enables memory disa
266. even if there is a difference between the number of edge specific constructs in the SDF file and the Verilog specify block For example the Verilog specify block may contain separate setup timing checks for a falling ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 333 Verilog SDF and rising edge on data with respect to clock while the SDF file may contain only a single setup check for both edges SDF Verilog SETUP data posedge clock 5 setup posedge data posedge clk 0 SETUP data posedge clock 5 setup negedge data posedge clk 0 In this case the cell accommodates more accurate data than can be supplied by the tool that created the SDF file and both timing checks correctly receive the same value Likewise the SDF file may contain more accurate data than the model can accommodate SDF Verilog SETUP posedge data posedge clock 4 setup data posedge clk 0 SETUP negedge data posedge clock 6 setup data posedge clk 0 In this case both SDF constructs are matched and the timing check receives the value from the last one encountered Timing check edge specifiers can also use explicit edge transitions instead of posedge and negedge However the SDF file is limited to posedge and negedge The explicit edge specifiers are 01 Ox 10 1x x0 and x1 The set of 01 Ox x1 is equivalent to posedge while the set of 10 1x x0
267. ever changing the compiler command line options results in a recompile of all modules gt Note Changes to your source code that do not change functionality but that do affect source code line numbers such as adding a comment line will cause all affected modules to be recompiled This happens because debug information must be kept current so that ModelSim can trace back to the correct areas of the source code ModelSim SE User s Manual Verilog Simulation 5 77 Compilation Library usage All modules and UDPs in a Verilog design must be compiled into one or more libraries One library is usually sufficient for a simple design but you may want to organize your modules into various libraries for a complex design If your design uses different modules having the same name then you are required to put those modules in different libraries because design unit names must be unique within a library The following is an example of how you may organize your ASIC cells into one library and the rest of your design into another vlib work vlib asiclib vlog work asiclib and2 v or2 v Compiling module and2 Compiling module or2 Top level modules and2 or2 vlog top v Compiling module top Top level modules top Note that the first compilation uses the work asiclib option to instruct the compiler to place the results in the asiclib library rather than the default work library Since instantiation bindings are no
268. f all drivers currently driving the node The following table provides some examples for two drivers driving a std_logic signal driver 1 driver 2 Z Detection of a bus fight results in an error message specifying the node and its drivers current driving values If a node s drivers later change value and the node is still in contention a message is issued giving the new values of the drivers A message is also issued when the contention ends The bus contention checking commands can be used on VHDL and Verilog designs These bus checking commands are in ModelSim Commands CR 9 e check contention add CR 54 e check contention config CR 55 e check contention off CR 56 Bus float checking Bus float checking detects nodes that are in the high impedance state for a time equal to or exceeding a user defined limit This is an error in some technologies Detection of a float violation results in an error message identifying the node A message is also issued when the float violation ends The bus float checking commands can be used on VHDL and Verilog designs These bus float checking commands are in ModelSim Commands CR 9 e check float add CR 57 e check float config CR 58 e check float off CR 59 ModelSim SE User s Manual Tips and Techniques E 435 Design stability checking Design stability checking Design stability checking detects when circuit activity has not settled wit
269. f tst_pseud ftst_pseu 1060 000 0 1080 000 0 1100 000 0001le O00lc pep fa te 1114 078 1 1120 000 0 1120 000 1 1140 000 0 1160 000 0 1180 000 0 1200 000 0 1220 000 0 sleet hee Grab 1234 078 1 1240 000 0 1240 000 0 00038 00038 1 00071 00071 1 00071 00071 1 00071 00071 1 000e3 000e3 1 000e3 000e3 1 001c7 OOlc 1 il 1 0 0 001c7 001c 00lc OOlc porcz OOlc 0038e 0038e 0038e 0038e 4 4 4 4 4 4 4 4 4 DOPPPRPRPRPRRPRPRO Right clicking on a yellow highlighted difference gives you three options Diff info Annotate diff and Ignore Noignore diff With these options you can elect to display difference information you can ignore selected differences or turn off ignore and you can annotate individual differences 11 322 Waveform Comparison ModelSim SE User s Manual Command line interface to Waveform Comparison Command line interface to Waveform Comparison Preference Variables Various Tcl variables control the default options of the Waveform Comparison feature See http www model com resources pref variables frameset htm for details on how to set these variables Compare commands The table below provides a brief description of the compare commands Follow the links for complete command syntax See ModelSim Commands for complete command details Command Description compare add CR 63 defines a compariso
270. ferences to a DO macro file running the DO file will reformat the List window to match the display as it appeared when the DO file was created Close close this copy of the List window you can create a new window with View gt New from the The Main window menu bar 8 160 Edit menu Cut cut the selected item field from the listing see Editing and formatting HDL items in the List window 8 181 Copy copy the selected item field Paste paste the previously cut or copied item to the left of the currently selected item Delete delete the selected item field Combine combine the selected fields into a user defined bus keep copies of the original items rather than moving them see Combining signals into a user defined bus 8 154 Select All select all signals in the List window Unselect All deselect all signals in the List window Find find the specified item label within the List window Search search the List window for a specified value or the next transition for the selected signal Markers menu Add Marker add a time marker at the currently selected line Delete Marker delete the selected marker from the listing Goto choose the time marker to go to from a list of current markers 8 176 ModelSim Graphic Interface ModelSim SE User s Manual List window Prop menu Display Props set display pr
271. ferent entities Design unit information The information stored for each design unit in a design library is e retargetable executable code e debugging information e dependency information Design library types There are two kinds of design libraries working libraries and resource libraries A working library is the library into which a design unit is placed after compilation A resource library contains design units that can be referenced within the design unit being compiled Only one library can be the working library in contrast any number of libraries including the working library itself can be resource libraries during a compilation The library named work has special attributes within ModelSim it is predefined in the compiler and need not be declared explicitly i e library work It is also the library name used by the compiler as the default destination of compiled design units In other words the work library is the working library In all other aspects it is the same as any other library 3 42 Design libraries ModelSim SE User s Manual Working with design libraries Working with design libraries The implementation of a design library is not defined within standard VHDL or Verilog Within ModelSim design libraries are implemented as directories and can have any legal name allowed by the operating system with one exception extended identifiers are not supported for library names Creating a library When
272. fferences can be handled by ModelSim s Waveform Comparison feature If the test design is hierarchical but the hierarchy is different from the hierarchy of the reference design you can use the compare add command CR 63 to specify which region path in the test design corresponds to that in the reference design If the test design is flattened and test signal names are different from reference signal names the compare add command CR 63 allows you to specify which signal in the test design will be compared to which signal in the reference design If in addition buses have been dismantled or bit blasted you can use the rebuild option of the compare add command CR 63 to automatically rebuild the bus in the test design This will allow you to look at the differences as one bus versus another If signals in the RTL test design are different in type from the synthesized signals in the reference design registers versus nets for example the Waveform Comparison feature will automatically do the type conversion for you If the type differences are too extreme say integer versus real Waveform Comparison will let you know 11 304 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison Graphical Interface to Waveform Comparison Waveform Comparison is initiated from either the Main or Wave window by selecting Compare gt Start Comparison Opening Dataset Comparison The Start Compar
273. fication and source code 4 65 SDF to VHDL generic matching An SDF file contains delay and timing constraint data for cell instances in the design The annotator must locate the cell instances and the placeholders VHDL generics for the timing data Each type of SDF timing construct is mapped to the name of a generic as specified by the VITAL modeling specification The annotator locates the generic and updates it with the timing value from the SDF file It is an error if the annotator fails to find the cell instance or the named generic The following are examples of SDF constructs and their associated generic names SDF construct Matching VHDL generic name IOPATH a y 3 tpd_a y IOPATH posedge clk q 1 2 tpd_clk_q_posedge INTERCONNECT ul y u2 a 5 tipd_a SETUP d posedge clk 5 tsetup_d_clk_noedge_posedge HOLD negedge d posedge clk 5 thold_d_clk_negedge_posedge SETUPHOLD d clk 5 5 tsetup_d_clk amp thold_d_clk WIDTH COND reset 1 b0 clk 5 tpw_clk_reset_eq_0 12 328 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual VHDL VITAL SDF Resolving errors If the simulator finds the cell instance but not the generic then an error message is issued For example ERROR myasic sdf 18 Instance testbench dut ul does not have a generic named tpd_a_y In this case make sure that the design is using the appropriate VITAL l
274. files only not system commands in VHDL source signal datime string 1 to 28 28 spaces on VSIM command line or in macro proc set_date global env set do_the_echo set env DO_ECHO set s exec date force deposit datime s if do_the_echo echo New time is examine value datime bp src waveadd vhd 133 set_date continue sets the breakpoint to call set_date This is an example of using the Tcl while loop to copy a list from variable a to variable b reversing the order of the elements along the way set b wi set i expr llength a 1 while i gt 0 lappend b lindex Sa i incr i 1 This example uses the Tcl for command to copy a list from variable a to variable b reversing the order of the elements along the way set b wi for set i expr llength a 1 i gt 0 incr i 1 lappend b lindex Sa i This example uses the Tcl foreach command to copy a list from variable a to variable b reversing the order of the elements along the way the foreach command iterates over all of the elements of a list set bn foreach i a set b linsert b 0 i ModelSim SE User s Manual Tcl and ModelSim 16 381 Tcl examples This example shows a list reversal as above this time aborting on a particular element using the Tcl break command set bo foreach i a if i ZZZ break set b linsert b 0 i This example is a list reversal that ski
275. g Simulation 5 109 Using the Verilog PLI VPI Registering VPI applications Each VPI application must register its system tasks and functions and its callbacks with the simulator To accomplish this one or more user created registration routines must be called at simulation startup Each registration routine should make one or more calls to vpi_register_systf to register user defined system tasks and functions and vpi_register_cb to register callbacks The registration routines must be placed in a table named vlog_startup_routines so that the simulator can find them The table must be terminated with a 0 entry Example PLI_INT32 MyFuncCalltf PLI_BYTE8 user_data PLI_INT32 MyFuncCompiletf PLI_BYTE8 user_data PLI_INT32 MyFuncSizetf PLI_BYTE8 user_data PLI_INT32 MyEndOfCompCB p_cb_data cb_data_p PLI_INT32 MyStartOfSimCB p_cb_data cb_data_p void RegisterMySystfs void s_cb_data callback s_vpi_systf_data systf_data systf_data type vpiSysFunc systf_data sysfunctype vpiSizedFunc systf_data tfname Smyfunc systf_data calltf MyFuncCalltf systf_data compiletf MyFuncCompiletf systf_data sizetf MyFuncSizetf systf_data user_data 0 vpi_register_systf amp systf_data callback reason cbhEndOfCompile callback cb_rtn MyEndOfCompCB callback user_data 0 void vpi_register_cb amp callback callback reason cbStartOfSimulation callback cb_
276. g files open for write 0 Buffered 1 Unbuffered 0 UserTimeUnit fs ps ns us ms sec or default specifies the default units to use for the lt timesteps gt lt time_units gt argument to the run command CR 176 NOTE the value of this variable must be set equal to or larger than the current simulator resolution specified by the Resolution variable shown above ns Veriuser one or more valid shared objects list of dynamically loadable objects for Verilog PLI VPI applications see Using the Verilog PLI VPI 5 108 commented out WaveSignalName Width 0 positive integer controls the number of visible hierarchical regions of a signal name shown in the Wave window 8 216 the default value of zero displays the full name a setting of one or above displays the corresponding level s of hierarchy WLFCompress 0 1 turns WLF file compression on 1 or off 0 WLFDeleteOnQuit 0 1 specifies whether a WLF file should be deleted when the simulation ends if set to 0 the file is not deleted if set to 1 the file is deleted WLFSaveAllRegions 0 1 specifies whether to save all design hierarchy in the WLF file 1 or only regions containing logged signals 0 WLESizeLimit 0 nMB WLF file size limit limits WLF file by size as closely as possible to the specified number of megabytes if both size and time limits are specified the most restrictive is
277. g timing accuracy and functionality and is the first significant hurdle to complete on the way to achieving full ASIC vendor support As a consequence many ASIC and FPGA vendors Verilog cell libraries are compatible with ModelSim Verilog The cell models generally contain Verilog specify blocks that describe the path delays and timing constraints for the cells See section 13 in the IEEE Std 1364 1995 for details on specify blocks and section 14 5 for details on timing constraints ModelSim Verilog fully implements specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog XL compatible extensions SDF timing annotation Delay modes ModelSim Verilog supports timing annotation from Standard Delay Format SDF files See Chapter 12 Standard Delay Format SDF Timing Annotation for details Verilog models may contain both distributed delays and path delays The delays on primitives UDPs and continuous assignments are the distributed delays whereas the port to port delays specified in specify blocks are the path delays These delays interact to determine the actual delay observed Most Verilog cells use path delays exclusively with the distributed delays set to zero For example module and2 y a b input a b output y and y a b specify a gt y 5 b gt y 5 endspecify endmodule In the above two input and gate cell the distributed delay for the and primitive is zero a
278. ges oa a a a aa F459 Coverage_summary window changes F461 License Agreement 463 Index 469 ModelSim SE User s Manual Table of Contents 13 14 Table of Contents ModelSim SE User s Manual 1 Introduction Chapter contents Performance tools included with ModelSimSE 1 16 ModelSim s graphic interface 1 16 Standards supported 2 eT Assumptions o 117 Sections in this document 1 18 Command reference 2 4 19 Text conventions ee 120 What is an HDL item 1 20 Where tofindourdocumentation 1 21 Online References www model com 1 22 Comments 2 a a 2 8 8 amp amp bh 4 amp amp 1423 This documentation was written for ModelSim SE version 5 5 for UNIX and Microsoft Windows 95 98 ME NT 2000 see note below for exception If the ModelSim software you are using is a later release check the README file that accompanied the software Any supplemental information will be there Although this document covers both VHDL and Verilog simulation you will find it a useful reference for single HDL design work ModelSim SE User s Manual Introduction 1 15 Performance tools included with ModelSim SE Performance tools included with ModelSim SE All ModelSim SE versions include the follo
279. gin and dataset prefixes Signal Properties set label height color radix and format for the selected item use the Format menu selections below to quickly change individual properties also set properties related to waveform comparisons Cursor menu Add Cursor add a cursor to the center of the waveform window Delete Cursor delete the selected cursor from the window Goto choose a cursor to go to from a list of current cursors ModelSim SE User s Manual ModelSim Graphic Interface 8 221 Wave window Zoom menu Zoom lt selection gt Compare menu selection Full In Out Last Area with mouse button 1 or Range to change the waveform display range Start Comparison start a new comparison Comparison Wizard receive step by step assistance while creating a waveform comparison Run Comparison compute differences from time zero until the end of the simulation End Comparison stop difference computation and close the currently open comparison Add provides three options Compare by Signal specify signals for comparison Compare by Region designate a reference region for a comparison Clocks define clocks to be used in a comparison Options set options for waveform comparisons Differences provides four options Clear clear all differences from the Wave window Show display differences in a text format in the Main window Transcript Save save
280. gnal Properties list 2 si 2 2 s 2 9 The Modify Signal Properties dialog box includes these options e Signal Shows the full pathname of the selected signal e Label Specifies the label that appears at the top of the List window column e Radix Specifies the radix base in which the item value is expressed The default radix is symbolic which means that for an enumerated type the List window lists the actual values of the enumerated type of that item You can change the default radix for the current simulation using either Options gt Simulation Main window or the radix command CR 166 You can change the default radix permanently by editing the DefaultRadix B 399 variable in the modelsim ini file For the other radixes binary octal decimal unsigned hexadecimal or ASCII the item value is converted to an appropriate representation in that radix In the system initialization file modelsim tcl you can specify the list translation rules for arrays of enumerated types for binary octal decimal unsigned decimal or hexadecimal item values in the design unit 8 182 ModelSim Graphic Interface ModelSim SE User s Manual List window e Width Allows you to specify the desired width of the column used to list the item value The default is an approximation of the width of the current value Trigger Triggers line Specifies that a change in the value of the selected item causes a new line to be disp
281. gt Combine menu selection allows you to move the selected items to the new bus as long as they are all scalars or arrays of the same base type records are not yet supported In the Wave window 8 216 the Edit gt Combine menu selection requires all selected items to be either all scalars or all arrays of the same size The benefit of this added restriction is that the bus can be expanded to show each element as a separate waveform Using the flatten option allows scalars and various array sizes to be mixed but foregoes display of child waveforms The keep option in both windows copies the signals rather than moving them 8 154 ModelSim Graphic Interface ModelSim SE User s Manual Common window features Tree window hierarchical view ModelSim provides a hierarchical or tree view of some aspects of your design in the Main window Structure pages and the Structure Signals Variables and Wave windows HDL items you can view structure Ol EJ Depending on which window you are a ae File Edit Window viewing one entry is created for each of the following VHDL and Verilog E top toplonly HDL items within the design p proc VHDL items Dm memory indicated by a dark blue square icon signals variables component MM Package std_logic_util MM Package vl_types instantiations generate statements Ml Package std_logic_1164 block statements and packages MM Package standard ae cache cache Verilog items Fun
282. h backward left to the previous transition on the selected signal finds the previous edge lt control f gt Windows lt control s gt UNIX open the find dialog box searches within the specified field in the pathname pane for text strings 8 244 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Printing and saving waveforms Saving a eps file and printing under UNIX Select File gt Print Postscript Wave window to print all or part of the waveform in the current Wave window in UNIX or save the waveform as a eps file on any platform see also write wave command CR 285 Printing and writing preferences are controlled by the dialog box shown below Write Postscript Ip dipl El CAINNT Profiles charley T The Write Postscript dialog box includes these options Printer e Print command Enter a UNIX print command to print the waveform in a UNIX environment e File name Enter a filename for the encapsulated Postscript eps file to be created or browse to a previously created eps file and use that filename Signal Selection e All signals Print all signals e Current View Print signals in the current view e Selected Print all selected signals Time Range ModelSim SE User s Manual ModelSim Graphic Interface 8 245 Wave window e Full Range Print all specified signals in the full simulation range e Current view Print the specified signals for the vie
283. h the directory There are two ways you can do this e Add before app so in the PLI library specification or e Load the path as a UNIX shell environment variable LD_LIBRARY_PATH lt library path without filename gt 64 bit Solaris platform On a 64 bit Sun system use the following ec compiler commands to prepare PLI VPI code for dynamic linking with ModelSim cc v xarch v9 O ISMTI_HOME include c app c ld G app o o app so 5 112 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI HP700 platform ModelSim loads shared libraries on the HP700 workstation A shared library is created by creating object files that contain position independent code use the z or fpic compiler option and by linking as a shared library use the b linker option Use these gec or ce compiler commands gcc compiler gcc c fpic I lt install_dir gt modeltech include app c ld b o app sl app o lc cc compiler cc c z 1 lt install_dir gt modeltech include app c ld b o app sl app o lc Note that fpic may not work with all versions of gcc for HP UX 11 0 users If you are building the PLI VPI library under HP UX 11 0 you should not specify the Ic option to the invocation of ld since this will cause an incorrect version of the standard C library to be loaded In other words build libraries like this cc c z I lt install_dir gt modeltech include app c ld b o app sl app o If
284. hall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than your employer s employees and contractors excluding Mentor Graphics competitors whose job performance requires access You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not disclose it or use it except as permitted by this Agreement Except as otherwise permitted for purposes of interoperability as specified by the European Union Software Directive or local law you shall not reverse assemble reverse compile reverse engineer or in any way derive from Software any source code You may not sublicense assign or otherwise transfer Software this Agreement or the rights under it without Mentor Graphics prior written consent The provisions of this section shall survive the termination or expiration of this Agreement 5 LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon 464 License Agreement ModelSim SE User s Manual installation
285. he Edit gt Sort menu selection in the windows below to sort HDL items in ascending descending or declaration order Process Signals Structure Variables and Wave windows Names such as net_1 net_10 and net_2 will sort numerically in the Signals and Wave windows Multiple window copies Use the View gt New menu selection from the Main window 8 157 to create multiple copies of the same window type The new window will become the default window for that type Context menus Context menus refer to menus that pop up in the middle of the interface by clicking the right mouse button Windows 2nd button UNIX 3rd button The commands on the menu change depending on where in the interface you click In other words the menus change based on the context of their use Menu tear off All window menus can be torn off to create a separate menu window To tear off click on the menu then select the dotted line button at the top of the menu Customizing menus and buttons Menus can be added deleted and modified in all windows Custom buttons can also be added to window toolbars See e Customizing the interface 8 279 e Customizing menus and buttons 8 154 and e The Button Adder 8 269 for more information Combining signals into a user defined bus You can collect selected items in the List window 8 175 and Wave window 8 216 displays and combine them into a bus named by you In the List window the Edit
286. he TDebug chooser sy TDebug Choose ES vsim The TDebug chooser has three parts At the top the current interpreter vsim op_ is shown In the main section there are two list boxes All currently defined procedures are shown in the left list box By clicking the left mouse button on a procedure name the procedure gets prepared for debugging and its name is moved to the right list box Clicking a name in the right list box returns a procedure to its normal state PE TT Press the right mouse button on a ddw aveE ditMent procedure in either list box to get its ddwaveFileMen program code displayed in the main ddwavePropMer y debugger window Rescan Popup The three buttons at the bottom let you force a Rescan of the available procedures Popup the debugger window or Exit TDebug Exiting from TDebug doesnt ModelSim SE User s Manual ModelSim Graphic Interface 8 271 ModelSim tools terminate ModelSim it merely detaches from vsim op_ restoring all prepared procedures to their unmodified state The Debugger Select the Popup button in the Chooser to open the debugger window TDebug for vsim ojx Debugger Options Selection Variables Help Proc AppliwaveProp treename Variables treename wave tree treename waveconfig signalnamewidth vsimPriv wayveprop_sigwit treename waveconfig snapdistance vsimPriv waveprop_snapdi vsimPriv DisableButtonList vsimPriv DragDrop_DropHa vsi
287. he command line The following commands may be useful for handling such events Any other legal command may be executed as well command result run CR 176 continue continue as if the breakpoint had not been executed completes the run CR 176 that was interrupted resume CR 173 continue running the macro onbreak CR 144 specify a command to run when you hit a breakpoint within a macro onElabError CR 145 specify a command to run when an error is encountered during elaboration onerror CR 146 specify a command to run when an error is encountered within a macro status CR 186 get a traceback of nested macro calls when a macro is interrupted abort CR 25 terminate a macro once the macro has been interrupted or paused pause CR 147 cause the macro to be interrupted the macro can be resumed by entering a resume command CR 173 via the command line transcript CR 194 control echoing of macro commands to the Main window transcript B Note You can also set the OnErrorDefaultAction Tcl variable in the pref tcl file to dictate what action ModelSim takes when an error occurs Error action in DO files If a command in a macro returns an error ModelSim does the following 1 Ifan onerror CR 146 command has been set in the macro script ModelSim executes that command 2 If no onerror command has been specified in the script ModelSim checks the OnErrorDefaultAction Tcl variable If th
288. he license to return to the pool of available licenses Syntax imremove c lt file gt lt feature gt lt user gt lt host gt lt display gt Imremove removes all instances of user on the node host on the display if specified from usage of feature If the optional c lt file gt switch is specified the indicated file will be used as the license file The system administrator should protect the execution of Imremove since removing a user s license can be disruptive Imreread The Imreread utility causes the license daemon to reread the license file and start any new vendor daemons that have been added In addition all preexisting daemons will be signaled to reread the license file for changes in feature licensing information Syntax lmreread daemon c lt license_file gt B Note If the c option is used the license file specified will be read by the daemon not by Imgrd Imgrd rereads the file it read originally Also Imreread cannot be used to change server node names or port numbers Vendor daemons will not reread their option files as a result of Imreread Administration tools for Windows All of the Unix administration tools listed above may be used on Windows platforms as well However in Windows all of the tools are launched via the program Jmutil For example if you want to run mstat you would type the following at a command prompt imutil lmstat args The arguments for Windows are the same as those
289. hildren icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 ModelSim SE User s Manual ModelSim Graphic Interface 8 215 Wave window Wave window The Wave window like the List window allows you to view the results of your simulation In the Wave window however you can see the results as HDL waveforms and their values The Wave window is divided into a number of window panes All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes wave default File Edit Cursor Zoom Compare Bookmark Format Window top clk top prwy top pstrb top prdy top paddr top pdata top stw top sstrb top srdy top saddr UUUUUUUU UUUUUUUU 900 ns Ons to 873 ns Pathname pane The pathname pane displays signal pathnames Signals can be displayed with full pathnames as shown here or with only the leaf element displayed You can increase the size of the pane by cli
290. hin a period you define for synchronous designs You specify the clock period for the design and the strobe time within the period during which the circuit must be stable A violation is detected and an error message is issued if there are pending driver events at the strobe time The message identifies the driver that has a pending event the node that it drives and the cycle number The design stability checking commands can be used on VHDL and Verilog designs These design stability checking commands are in ModelSim Commands CR 9 e check stable on CR 61 e check stable off CR 60 Toggle checking Toggle checking counts the number of transitions to 0 and on specified nodes Once the nodes have been selected a toggle report may be requested at any time during the simulation The toggle commands can be used on VHDL and Verilog designs These toggle checking commands are in ModelSim Commands CR 9 e toggle add CR 190 e toggle reset CR 192 e toggle report CR 191 Detecting infinite zero delay loops Simulations use steps that advance simulated time and steps that do not advance simulated time Steps that do not advance simulated time are called delta cycles Delta cycles are used when signal assignments are made with zero time delay If a large number of delta cycles occur without advancing time it is usually a symptom of an infinite zero delay loop in the design In order to detect the presence of these loops ModelS
291. hin macros and on the command line The command line prompt will change as in a C shell until the multiple line command is complete In the example below note the way the opening brace is at the end of the if and else lines This is important because otherwise the Tcl scanner wont know that there is more coming in the command and will try to execute what it has up to that point which won t be what you intend if exa sig_a 001122 echo Signal value matches do macro_1 do else echo Signal value fails do macro_2 do Evaluation order An important thing to remember when using Tcl is that anything put in curly brackets is not evaluated immediately This is important for if then else procedures loops and so forth Tcl relational expression evaluation When you are comparing values the following hints may be useful e Tcl stores all values as strings and will convert certain strings to numeric values when appropriate If you want a literal to be treated as a numeric value don t quote it if exa var_1 345 The following will also work if exa var_1 345 e However if a literal cannot be represented as a number you must quote it or Tcl will give you an error For instance if exa var_2 0012 will give an error if exa var_2 001Z will work okay e Don t quote single characters in single quotes if exa var_3 X will give an error if exa var_3
292. ibrary cells If it is then there is probably a mismatch between the SDF and the VITAL cells You need to find the cell instance and compare its generic names to those expected by the annotator Look in the VHDL source files provided by the cell library vendor If none of the generic names look like VITAL timing generic names then perhaps the VITAL library cells are not being used If the generic names do look like VITAL timing generic names but don t match the names expected by the annotator then there are several possibilities The vendor s tools are not conforming to the VITAL specification The SDF file was accidentally applied to the wrong instance In this case the simulator also issues other error messages indicating that cell instances in the SDF could not be located in the design The vendor s library and SDF were developed for the older VITAL 2 2b specification This version uses different name mapping rules In this case invoke vsim CR 258 with the vital2 2b option vsim vital2 2b sdfmax testbench ul myasic sdf testbench For more information on resolving errors see Troubleshooting 12 337 ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 329 Verilog SDF Verilog SDF Verilog designs can be annotated using either the simulator command line options or the sdf_annotate system task also commonly used in other Verilog simulators The command line options annotate the design
293. ica should contact their local support organization A list of local Mentor Graphics support and sales offices can be found at www mentor com supportnet support_offices html Technical support other channels For customers who purchased ModelSim as part of a bundled product from an OEM or VAR please refer to the www model com partners default asp on the Model Technology website for contact information ModelSim SE User s Manual Technical Support Updates and Licensing A 387 Updates Updates Model Technology customers You can ftp the latest version of the software from the web site at ftp ftp model com Instructions are there as well Mentor Graphics customers You can ftp the latest SE or PE version of the software from the SupportNet site at ftp supportnet mentor com pub mentortech modeltech Instructions are there as well A valid license file from Mentor Graphics is needed to uncompress the ModelSim files Online References The Model Technology web site www model com includes links to support software downloads and many EDA information sources Check the links below for the most current information Latest version email Place your name on our list for email notification of new releases and updates model com support register_news_list asp News Current news of Model Technology within the EDA industry model com news_events default asp Partners Model Technology s value adde
294. ified field in the pathname pane for text strings C 410 ModelSim Shortcuts ModelSim SE User s Manual List window keyboard shortcuts Using the following keys when the mouse cursor is within the List window will cause the indicated actions Key Action lt arrow up gt scroll listing up selects and highlights the line above the currently selected line lt arrow down gt scroll listing down selects and highlights the line below the currently selected line lt arrow left gt scroll listing left lt arrow right gt scroll listing right lt page up gt scroll listing up by page lt page down gt scroll listing down by page lt tab gt searches forward down to the next transition on the selected signal lt shift tab gt searches backward up to the previous transition on the selected signal does not function on HP workstations lt control f gt Windows lt control s gt UNIX opens the find dialog box finds the specified item label within the list display ModelSim SE User s Manual ModelSim Shortcuts C 411 Command shortcuts You may abbreviate command syntax but there s a catch The minimum characters required to execute a command are those that make it unique Remember as we add new commands some of the old shortcuts may not work For this reason ModelSim does not allow command name abbreviations in macro files This minim
295. ifies a source library directory containing module and UDP definitions Files within this directory are compiled only if the file names match the names of previously unresolved references Multiple y options are allowed libext lt suffix gt This option works in conjunction with the y option It specifies file extensions for the files in a source library directory By default the compiler searches for files without extensions If you specify the libext option then the compiler will search for a file with the suffix appended to an unresolved name You may specify only one libext option but it may contain multiple suffixes separated by The extensions are tried in the order they appear in the libext option librescan This option changes how unresolved references are handled that are added while compiling a module or UDP from a source library By default the compiler attempts to resolve these references as it continues searching the source libraries If you specify the librescan option then the new unresolved references are deferred until after the current pass through the source libraries They are then resolved by searching the source libraries from the beginning in the order they are specified on the command line 5 80 Verilog Simulation ModelSim SE User s Manual Compilation tnolibcell By default all modules compiled from a source library are treated as though they contain a celldefine compiler directive This option
296. ile_uselibs argument finds the source files referenced in the directive compiles them into automatically created object libraries and updates the modelsim ini file with the logical mappings to the libraries When using compile_uselibs ModelSim determines into what directory to compile the object libraries by choosing in order from the following three values e The directory name specified by the compile_uselibs argument For example compile_uselibs mydir e The directory specified by the MTI_USELIB_DIR environment variable see Environment variables B 393 e A directory named mti_uselibs that is created in the current working directory pre 5 5 release implementation In ModelSim versions prior to 5 5 the library files referenced by the uselib directive were not automatically compiled by ModelSim Verilog To maintain backwards compatibility this is still the default behavior when compile_uselibs see above is not used The following describes the pre 5 5 release implementation Because it is an important feature of uselib to allow a design to reference multiple modules having the same name independent compilation of the source libraries referenced by the uselib directives is required Each source library should be compiled into its own object library The compilation of the code containing the uselib directives only records which object libraries to search for each module instantiation when the design is loaded
297. im defines a limit the iteration_limit on the number of successive delta cycles that can occur When the iteration_limit is exceeded vsim stops the simulation and gives a warming message You can set the iteration_limit from the Options gt Simulation menu by modifying the modelsim ini file or by setting a Tcl variable called IterationLimit B 399 The iteration_limit default value is 5000 When you get an iteration_limit warning first increase the iteration limit and try to continue simulation If the problem persists look for zero delay loops One approach to finding zero delay loops is to increase the iteration limit again and start single stepping You should be able to see the assignment statements or processes that are looping Looking at the Process window will also help you to see the active looping processes When the loop is found you will need to change the design to eliminate the unstable loop See Projects and system initialization 2 25 for more information on modifying the modelsim ini file And see Preference variables located in TCL files B 406 for more information on Tcl variables Also see the Main window Help menu for Tcl Help and man pages E 436 Tips and Techniques ModelSim SE User s Manual Referencing source files with location maps Referencing source files with location maps Pathnames to source files are recorded in libraries by storing the working directory from which the compile
298. immediately after it is loaded but before any simulation events take place The sdf_annotate task annotates the design at the time it is called in the Verilog source code This provides more flexibility than the command line options The sdf_annotate system task The syntax for sdf_annotate is Syntax Ssdf_annotate lt sdffile gt lt mtm_spec gt lt instance gt lt config_file gt lt log_file gt r lt scale_factor gt lt scale_type gt Arguments lt sdffile gt String that specifies the SDF file Required lt instance gt Hierarchical name of the instance to be annotated Optional Defaults to the instance where the sdf_annotate call is made lt config_file gt String that specifies the configuration file Optional Currently not supported this argument is ignored lt log_file gt String that specifies the logfile Optional Currently not supported this argument is ignored lt mtm_spec gt String that specifies the delay selection Optional The allowed strings are minimum typical maximum and tool_control Case is ignored and the default is tool_control The tool_control argument means to use the delay specified on the command line by mindelays typdelays or maxdelays defaults to typdelays lt scale_factor gt String that specifies delay scaling factors Optional The format is lt min_mult gt lt typ_mult gt lt max_mult gt Each
299. implementation issues Writing strings and aggregates A common error in VHDL source code occurs when a call to a WRITE procedure does not specify whether the argument is of type STRING or BIT_VECTOR For example the VHDL procedure WRITE L hello will cause the following error ERROR Subprogram WRITE is ambiguous In the TextlO package the WRITE procedure is overloaded for the types STRING and BIT_VECTOR These lines are reproduced here procedure WRITE L inout LINE VALUE in BIT_VECTOR JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 procedure WRITE L inout LINE VALUE in STRING JUSTIFIED in SIDE RIGHT FIELD in WIDTH 0 The error occurs because the argument hello could be interpreted as a string or a bit vector but the compiler is not allowed to determine the argument type until it knows which function is being called The following procedure call also generates an error WRITE L 010101 This call is even more ambiguous because the compiler could not determine even if allowed to whether the argument 010101 should be interpreted as a string or a bit vector There are two possible solutions to this problem e Use a qualified expression to specify the type as in WRITE L string hello e Call a procedure that is not overloaded as in WRITE_STRING L hello The WRITE_STRING procedure simply defines the value to be a STRING and calls the WRITE procedure but it serves as a
300. in macros using the Tcl env array mechanism echo Senv ENV_VAR_NAME Removing temp files VSOUT The VSOUT temp file is the communication mechanism between the simulator kernel and the ModelSim GUI In normal circumstances the file is deleted when the simulator exits If ModelSim crashes however the temp file must be deleted manually Specifying the location of the temp file with TMPDIR above will help you locate and remove the file gt Note There is one environment variable MODEL_TECH that you cannot and should not set MODEL_TECH is a special variable set by Model Technology software Its value is the name of the directory from which the vcom compiler or vsim simulator was invoked MODEL_TECH is used by the other Model Technology tools to find the libraries ModelSim SE User s Manual ModelSim Variables B 395 Preference variables located in INI files Preference variables located in INI files ModelSim initialization IND files contain control variables that specify reference library paths and compiler and simulator settings The following tables list the variables by section and in order of their appearance within the INI file INI file sections Library library path variables B 396 vcom VHDL compiler control variables B 396 vlog Verilog compiler control variables B 398 vsim simulator control variables B 398 Imc Logic Modeling variables B 402 Libr
301. in VHDL As a VHDL user you might be tempted to model a memory using signals Two common simulator problems are the likely result e You may get a memory allocation error message which typically means the simulator ran out of memory and failed to allocate more storage e Or you may get very long load elaboration or run times These problems are usually explained by the fact that signals consume a substantial amount of memory many dozens of bytes per bit all of which needs to be loaded or initialized before your simulation starts A simple alternative implementation provides some excellent performance benefits e storage required to model the memory can be reduced by 1 2 orders of magnitude e startup and run times are reduced associated memory allocation errors are eliminated The trick is to model memory using variables instead of signals In the example below we illustrate three alternative architectures for entity memory Architecture style_87_bad uses a vhdl signal to store the ram data Architecture style_87 uses variables in the memory process and architecture style_93 uses variables in the architecture For large memories architecture style_87_bad runs many times longer than the other two and uses much more memory This style should be avoided Both architectures style_87 and style_93 work with equal efficiently You ll find some additional flexibility with the VHDL 1993 style however because the
302. in the directory where the executable exists lt install_dir gt modeltech lt platform gt Finally in the parent of the directory where the executable is lt install_dir gt modeltech Note The MODELSIM variable is generally set to an ini file Setting the variable to an MPF file is not recommended since the file would contain project specific information Setting the MODELSIM variable to an mpf file is only recommended for batch mode usage ModelSim SE User s Manual ModelSim Variables B 407 Simulator state variables Simulator state variables Unlike other variables that must be explicitly set simulator state variables return a value relative to the current simulation Simulator state variables can be useful in commands especially when used within ModelSim DO files macros Variable Result argc returns the total number of parameters passed to the current macro architecture returns the name of the top level architecture currently being simulated for a configuration or Verilog module this variable returns an empty string configuration returns the name of the top level configuration currently being simulated returns an empty string if no configuration delta returns the number of the current simulator iteration entity returns the name of the top level VHDL entity or Verilog module currently being simulated library returns the library name for the current region MacroNestingLevel retur
303. inding items by name or value in the Wave window 8 237 8 156 ModelSim Graphic Interface ModelSim SE User s Manual Main window Main window The Main window is pictured below as it appears when ModelSim is first invoked Note that your operating system graphic interface provides the window management frame only ModelSim handles all internal window features including menus buttons and scroll bars ModelSim workspace Library lt No Design Loaded gt transcript The menu bar at the top of the window provides access to a wide variety of simulation commands and ModelSim preferences The toolbar provides buttons for quick access to the many common commands The status bar at the bottom of the window gives you information about the data in the active ModelSim window The menu bar toolbar and status bar are described in detail below ModelSim SE User s Manual ModelSim Graphic Interface 8 157 Main window Workspace The workspace is available in software versions 5 5 and later It provides convenient access to projects compiled design units and simulation dataset structures It can be hidden or displayed by selecting the View gt Hide Show Workspace command The workspace can display three types of pages as shown in the graphic below ModelSim olx File Edt Resign _ view Project Run TES Macro Options Window Help vsim work adder vsim work adder Loading E modelsim55_102500 win32
304. ines These requirements ensure that the appropriate symbol is exported and thus ModelSim can find the symbol when it dynamically loads the DLL The PLI and VPI have been tested with DLLs built using Microsoft Visual C C compiler version 4 1 or greater The gcc compiler cannot be used to compile PLI VPI applications under Windows This is because gcc does not support the Microsoft lib dll format ModelSim SE User s Manual Verilog Simulation 5 111 Using the Verilog PLI VPI Linux platform Under Linux ModelSim loads shared objects Use these gec or cc compiler commands to create a shared object gcc compiler gcc c I lt install_dir gt modeltech include app c ld shared E o app so app o cc compiler cc c I lt install_dir gt modeltech include app c ld shared E o app so app o Solaris platform Under SUN Solaris ModelSim loads shared objects Use these gee or ce compiler commands to create a shared object gcc compiler gcc c 1 lt install_dir gt modeltech include app c ld G B symbolic o app so app o cc compiler cc c I lt install_dir gt modeltech include app c ld G B symbolic o app so app o gt Note When using B symbolic with Id all symbols are first resolved within the shared library at link time This will result in a list of undefined symbols This is only a warning for shared libraries and can be ignored If app so is in your current directory you must force Solaris to searc
305. ing environment consists of nine window types Multiple windows of each type can be used during simulation with the exception of the Main window To make an additional window select View gt New Main window A brief description of each window follows Main window 8 157 The initial window that appears upon startup All subsequent ModelSim windows are opened from the Main window This window contains the session transcript Dataflow window 8 171 Lets you trace signals and nets through your design by showing related processes List window 8 175 Shows the simulation values of selected VHDL signals and variables and Verilog nets and register variables in tabular format Process window 8 190 Displays a list of processes in the region currently selected in the Structure window Signals window 8 193 Shows the names and current values of VHDL signals and Verilog nets and register variables in the region currently selected in the Structure window Source window 8 201 Displays the HDL source code for the design Your source code can remain hidden if you wish see Source code security and nodebug E 433 Structure window 8 210 Displays the hierarchy of structural elements such as VHDL component instances packages blocks generate statements and Verilog model instances named blocks tasks and functions In versions 5 5 and later this same information is displayed in the Main window workspace Variables window 8 213
306. initialization file modelsim ini e The third part cy7c285 is the SmartModel name This name correlates the architecture with the SmartModel at elaboration Vector ports The entities generated by sm_entity only contain single bit ports never vectored ports This is necessary because ModelSim correlates entity ports with the SmartModel SWIFT interface by name However for ease of use in component instantiations you may want to create a custom component declaration and component specification that groups ports into vectors You can also rename and reorder the ports in the component declaration You can also reorder the ports in the entity declaration but you can t rename them The following is an example component declaration and specification that groups the address and data ports of the CY7C285 SmartModel component cy7c285 generic TimingVersion STRING CY7C285 65 DelayRange STRING Max MemoryFile STRING memory port A in std_logic_vector 15 downto 0 CS in std_logic O out std_logic_vector 7 downto 0 WAIT_PORT inout std_logic end component for all cy7c285 use entity work cy7c285 port map AO gt A 0 Al gt A 1 ModelSim SE User s Manual Logic Modeling SmartModels 14 357 VHDL SmartModel interface A2 gt A 2 A3 gt A 3 A4 gt A A A5 gt A 5 A6 gt A 6 A7 gt A 7 A8 gt A 8 A9 gt A 9 A10 gt A 10 All gt A 11 A
307. interactive scope to the scope specified by hierarchical_name The equivalent simulator command is environment lt pathname gt Sshowscopes This system task displays a list of scopes defined in the current interactive scope The equivalent simulator command is show Sshowvars This system task displays a list of registers and nets defined in the current interactive scope The equivalent simulator command is show ModelSim SE User s Manual Verilog Simulation 5 103 System Tasks init_signal_spy The init_signal_spy system task mirrors the value of a VHDL signal or Verilog register wire called the spy_object onto an existing Verilog register or VHDL signal called the dest_object This system task allows you to reference VHDL signals at any level of hierarchy from within a Verilog module or reference Verilog registers wires at any level of hierarchy from within a Verilog module when there is an interceding VHDL block This system task works only in ModelSim versions 5 5 and newer Syntax Sinit_signal_spy spy_object dest_object verbose Returns Nothing Arguments Name Description spy_object Required A full hierarchical path or relative path with reference to the calling block to a VHDL signal or Verilog register wire Use the path separator to which your simulation is set ie or A full hierarchical path must begin with a or The path must be contained within double quotes
308. ion accSignal accSignal signal declaration The type and fulltype constants for VHDL objects are defined in the acc_vhdl h include file All of these objects except signals are scope objects that define levels of hierarchy in the Structure window Currently the PLI ACC interface has no provision for obtaining handles to generics types constants variables attributes subprograms and processes However some of these objects can be manipulated through the ModelSim VHDL foreign interface mti_ routines See the FLI Reference Manual for more information ModelSim SE User s Manual Verilog Simulation 5 121 Using the Verilog PLI VPI IEEE Std 1364 ACC routines ModelSim Verilog supports the following ACC routines described in detail in the IEEE Std 1364 acc_append_delays acc_append_pulsere acc_close acc_collect acc_compare_handles acc_configure acc_count acc_fetch_argc acc_fetch_argv acc_fetch_ attribute acc_fetch_attribute_int acc_fetch_attribute_str acc_fetch_defname acc_fetch_delay_mode acc_fetch_delays acc_fetch_direction acc_fetch_edge acc_fetch fullname acc_fetch_fulltype acc_fetch_index acc_fetch_location acc_fetch_name acc_fetch_paramtype acc_fetch_paramval acc_fetch_polarity acc_fetch_precision acc_fetch_pulsere acc_fetch_range acc_fetch_size acc_fetch_tfarg acc_fetch_itfarg acc_fetch_tf
309. ion 12 326 interconnect delays 12 336 mixed VHDL and Verilog designs 12 336 obtaining the specification 12 339 specification with the GUI 12 327 troubleshooting 12 337 ModelSim SE User s Manual Index 474 Verilog sdf_annotate system task 12 330 optional conditions 12 334 optional edge specifications 12 333 rounded timing values 12 335 SDF to Verilog construct matching 12 331 Verilog SDF annotation 12 330 VHDL Resolving errors 12 329 SDF to VHDL generic matching 12 328 Searching for values and finding names in windows 8 153 List window signal values transitions and names 8 185 Verilog libraries 5 78 waveform signal values edges and names 8 208 8 212 8 237 searchLog simulator command 7 147 Shortcuts command history C 412 command line caveat C 412 List window 8 188 C 411 text editing 8 168 C 413 Wave window 8 244 C 410 show differences 11 320 Show source lines with errors 8 253 Show_source ini file variable VCOM B 397 Show_source ini file variable VLOG B 398 Show_VitalChecksWarning ini file variable B 397 Show_Warning 1 ini file variable B 397 Show_Warning2 ini file variable B 397 Show_Warning3 ini file variable B 397 Show_Warning4 ini file variable B 397 Show_WarningS5 ini file variable B 397 signal breakpoints 8 198 Signal spy 4 69 Signal transitions searching for 8 240 Signals adding to a log file 8 197 adding to the Wave and List windows 8 197 applying stimulus to 8 196 combining into a user
310. ions in the Source window Select Edit gt Find or Edit gt Replace to bring up the Find dialog box If you select Edit gt Find the Replace field is absent from the dialog Enter the value to _ search for in the Find in source Find field If you are doing a replace Find Find Next enter the appropriate value in the Replace I Case sensitive T Search backwards Close field Optionally specify whether the entries are case sensitive and whether to search backwards from the current cursor location Check the Regular expression checkbox if you are using regular expressions Regular expression 8 208 ModelSim Graphic Interface ModelSim SE User s Manual Source window Setting tab stops in the Source window You can set tab stops in the Source window by selecting the Main window Options gt Edit Preferences command Follow these steps 1 Select the By Names tab 2 Select Source in the first column and then select the tabs item in the second column 3 Press the Change Value button 4 In the dialog that appears enter a single number n which sets a tab stop every n characters where a character width is the width of the 8 character or Enter a list of screen distances for the tab stops For instance 21 49 77 105 133 161 189 217 245 273 301 329 357 385 413 441 469 The number 21 or 21p means 21 pixels the number 3c means three centimeters the number li means one inch A Important D
311. ious transition on the selected signal does not function on HP workstations lt control f gt Windows lt control s gt UNIX opens the find dialog box finds the specified item label within the list display 8 188 ModelSim Graphic Interface ModelSim SE User s Manual List window Saving List window data to a file Select File gt Write List format List window to save the List window data in one of these formats e tabular writes a text file that looks like the window listing ns delta a b cin sum cout 0 0 X X U X U 0 1 0 1 0 X U 2 0 0 1 0 X U e event writes a text file containing transitions during simulation eO 0 a X b X cin U sum X cout U eo 1 a 0 b 1 cin 0 e TSSI writes a file in standard TSSI format see also the write tssi command CR 283 0 00000000000000010 2 00000000000000010 1 3 00000000000000010 010 4 00000000000000010000000010 100 00000001000000010000000010 You can also save List window output using the write list command CR 279 ModelSim SE User s Manual ModelSim Graphic Interface 8 189 Process window Process window The Process window displays a list of processes If View gt Active is selected then all processes scheduled to run during the current simulation cycle are displayed along with the pathname of the instance in which each process is located If View gt In Region is selected then only the processes in
312. irectives such as define and timescale take effect at the point they are defined in the source code and stay in effect until the directive is redefined or until it is reset to its default by a resetall directive The effect of compiler directives spans source files so the order of source files on the compilation command line could be significant For example if you have a file that defines some common macros for the entire design then you might need to place it first in the list of files to be compiled The resetall directive affects only the following directives by resetting them back to their default settings this information is not provided in the IEEE Std 1364 celldefine default_decay_time define_nettype delay_mode_distributed delay_mode_path delay_mode_unit delay_mode_zero timescale unconnected_drive uselib ModelSim Verilog implicitly defines the following macro define MODEL_TECH IEEE Std 1364 compiler directives The following compiler directives are described in detail in the IEEE Std 1364 celldefine default_nettype define else endcelldefine endif ifdef ifndef include Mine nounconnected_drive resetall timescale unconnected_drive undef Verilog XL compatible compiler directives The following compiler directives are provided for compatibility with Verilog XL default_decay_time lt time gt 5 106 Verilog Simulation
313. ironment variables Variable Description PLIOBJS used by ModelSim to search for PLI object files for loading consists of a space separated list of file or path names optional STDOUT the VSOUT temp file generated by the simulator kernel is deleted when the simulator exits the file is not deleted if you specify a filename for VSOUT with STDOUT specifying a name and location use TMPDIR for the VSOUT file will also help you locate and delete the file in event of a crash an unnamed VSOUT file is not deleted after a crash either TMPDIR specifies the path to a tempnam generated file VSOUT containing all stdout from the simulation kernel optional Setting environment variables in Windows In addition to the predefined variables shown above you can define your own environment variables This example shows a user defined library path variable that can be referenced by the vmap command to add library mapping to the modelsim ini file Using Windows 95 98 Open and edit the autoexec bat file by adding this line set MY_PATH temp work Restart Windows to initialize the new variable Using Windows NT Right click the My Computer icon and select Properties then select the Environment tab of the System Properties control panel Add the new variable to these fields Variable MY_PATH and Value MtempWwork Click Set and Apply to initialize the variable you don t need to restart NT Library mapping wi
314. is equivalent to negedge A match occurs if any of the explicit edges in the specify port match any of the explicit edges implied by the SDF port For example SDF Verilog SETUP data posedge clock 5 setup data edge 01 Ox clk 0 Optional conditions SDF Timing check ports and path delays can have optional conditions The annotator uses the following rules to match conditions A match occurs if the SDF does not have a condition e A match occurs for a timing check if the SDF port condition is semantically equivalent to the specify port condition e A match occurs for a path delay if the SDF condition is lexically identical to the specify condition Timing check conditions are limited to very simple conditions therefore the annotator can match the expressions based on semantics For example Verilog SETUP data COND reset 1 posedge clock 5 setup data posedge clk amp amp amp reset 0 0 12 334 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual Verilog SDF The conditions are semantically equivalent and a match occurs In contrast path delay conditions may be complicated and semantically equivalent conditions may not match For example SDF Verilog COND r1 II r2 OPATH clk q 5 if r1 1112 clk gt q 5 matches COND r1 Il r2 COPATH clk q 5 if r2 Il r1 clk gt q 5 does not match The
315. is initiated Welcome Menu open the Welcome screen Information about Help view the readme file pertaining to ModelSim s online documentation SE Documentation open and read ModelSim documentation in PDF or HTML format PDF files can be read with a free Adode Acrobat reader available on the ModelSim installation CD or from www adobe com Tcl Help open the Tcl command reference man pages in Windows help format Tcl Syntax open Tcl syntax details in HTML format Tcl Man Pages open the Tcl Tk 8 0 manual in HTML format Technotes select a technical note to view from the drop down list ModelSim SE User s Manual ModelSim Graphic Interface 8 165 Main window The Main window toolbar Buttons on the Main window toolbar give you quick access to these ModelSim commands and functions l ModelSim File Edit Design Wiew Project Run Compare Macro Options Window Help rake pases S X SS S 2 y e SI O 5 S y SI Ss 9 Y y 8 Q S S SS No RX 9 Main window toolbar buttons Button Menu equivalent Command equivalents Compile Design gt Compile also vcom lt arguments gt or open the Compile HDL Source Options gt Compile vlog lt arguments gt Files dialog box to select files for opens the Compile compilation Options dialog box see vcom CR 217 or vlog CR 250 Load Design Design gt Load Design vsim lt arguments gt open the Load Design dial
316. is invoked and the pathname to the file as specified in the invocation of the compiler The pathname may be either a complete pathname or a relative pathname ModelSim tools that reference source files from the library locate a source file as follows If the pathname stored in the library is complete then this is the path used to reference the file If the pathname is relative then the tool looks for the file relative to the current working directory If this file does not exist then the path relative to the working directory stored in the library is used This method of referencing source files generally works fine if the libraries are created and used on a single system However when multiple systems access a library across a network the physical pathnames are not always the same and the source file reference rules do not always work Using location mapping Location maps are used to replace prefixes of physical pathnames in the library with environment variables The location map defines a mapping between physical pathname prefixes and environment variables ModelSim tools open the location map file on invocation if the MGC_LOCATION_MAP B 393 environment variable is set If MGC_LOCATION_MAP is not set ModelSim will look for a file named mgc_location_map in the following locations in order the current directory your home directory the directory containing the ModelSim binaries the ModelSim installation directory Use these
317. ison dialog box allows you Start Comparison Reference Dataset define the Reference and Test Browse datasets Test Dataset Reference Dataset Use Current Simulation The Reference Dataset is the wlf file that the test dataset will be compared to It can be a saved dataset the current simulation dataset or any part of the current simulation dataset 7 Update comparison after each run Specify Dataset IS Browse OK Cancel Test Dataset The Test Dataset is the wlf file that will be compared against the Reference Dataset Like the Reference Dataset it can be a saved dataset the current simulation dataset or any part of the current simulation dataset e Use Current Simulation Selects the current simulation to be used as the Test Dataset Provides for an optional update on the comparison after each simulation run e Specify Dataset Allows you to select any saved wlf file to be used as the Test Dataset You can specify either dataset by typing in a dataset name by selecting a dataset from a drop down history of past dataset selections or by clicking either of the Browse buttons ModelSim SE User s Manual Waveform Comparison 11 305 Graphical Interface to Waveform Comparison Both Browse buttons take you to the Select Dataset File dialog where you can browse for the dataset you want Look jn examples gt El e datasets C vidpoker foreign A
318. ist or Wave window down CR 105 moves the active marker in the List window down to the next transition on the selected signal that matches the specifications getactivecursortime CR 124 gets the time of the active cursor in the Wave window getactivemarkertime CR 125 gets the time of the active marker in the List window left CR 129 searches left through the specified Wave window for signal transitions or values notepad CR 141 a simple text editor used to view and edit ASCII files or create new files play CR 148 UNIX only excluding Linux replays a sequence of keyboard and mouse actions that were previously saved to a file with the record command CR 167 property list CR 161 changes properties of an HDL item in the List window display property wave CR 162 changes properties of an HDL item in the waveform or signal name display in the Wave window record CR 167 UNIX only excluding Linux starts recording a replayable trace of all keyboard and mouse actions right CR 174 searches right through the specified Wave window for signal transitions or values search CR 178 searches the specified window for one or more items matching the specified pattern s seetime CR 182 scrolls the List or Wave window to make the specified time visible transcribe CR 193 displays a command in the Main window then executes the command up CR 196
319. ition or the n th match on value Match Count indicates the number of transitions or matches to search for The Search Results are indicated at the bottom of the dialog box 8 238 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Using time cursors in the Wave window wave default OS Ss ES Y Ss MON ES RA SL i CF These Wave window Ss y S o Y POS buttons give you quick SS e g e S O ES lt rsor placemen SS o S access to cursor placement amp e AS Ss e and zooming File Edit Cursor Zoom Compare Bookmark Format windok as jE Qa top clk top prw top pstrb top prdy top paddr top pdata top srw i a eT 1 K Se a are PS D ns to 950 ns 00000000 if I DOD000 0 L 900 ns 425 ns 52 ns E A interval measurement Click and drag with the center mouse button to zoom in on an area of the display selected cursor is bold When the Wave window is first drawn there is one cursor located at time zero Clicking anywhere in the waveform display brings that cursor to the mouse location You can add cursors to the waveform pane with the Cursor gt Add Cursor menu selection or the Add Cursor button shown below The selected cursor is drawn as a bold solid line all other cursors are drawn with thin dashed lines Remove cursors by selecting them and selecting Cursor gt Delete Cursor or the Delete Cursor button shown below Add Cu
320. ized using fast Compiling for faster performance 5 90 VCD file enhancements support multiple VCD files and dumpports tasks ModelSim VCD commands and VCD tasks 13 342 enhanced Code Coverage feature new interface and ability to exclude files and lines Chapter 10 Code Coverage ved2wlf new utility converts VCD files to WLF files vcd2wlf CR 216 bookmarks save zoom and scroll settings in Wave window Saving zoom range and scroll position with bookmarks 8 241 Workspace new Main window eases working with design units and datasets Workspace 8 158 find and replace in Source window Source window now supports search and replace for text and regular expressions Finding and replacing in the Source window 8 208 breakpoints dialog manage breakpoints via dialog boxes Setting signal breakpoints 8 236 import library wizard imports FPGA libraries Importing FPGA libraries 3 53 ModelSim SE User s Manual What s new in ModelSim F 447 Command and variable changes What Description Where select a link ModelSim release compile_uselibs argument for vlog eases use of uselib directives compile_uselibs argument 5 82 5 5 lint argument for vlog enables lint style checks lint CR 252 5 5 middle mouse button pasting control enables disables middle mouse button pasting Middle Mou
321. izes your need to maintain macro files as new commands are added Command history shortcuts The simulator command history may be reviewed or commands may be reused with these shortcuts at the ModelSim VSIM prompt Shortcut Description repeats the last command repeats command number n n is the VSIM prompt number e g for this prompt VSIM 12 gt n 12 labc repeats the most recent command starting with abc xyz ab replaces xyz in the last command with ab up and down arrows scrolls through the command history with the keyboard arrows click on prompt left click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active cursor his or history shows the last few commands up to 50 are kept C 412 ModelSim Shortcuts ModelSim SE User s Manual Mouse and keyboard shortcuts in the Transcript and Source windows The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor Mouse UNIX Mouse Windows Result lt left button click gt move the insertion cursor lt left button press gt drag select lt shift left button press gt extend selection
322. ks and functions calltf checktf sizetf and misctf routines and Verilog VCL callbacks 5 126 Verilog Simulation ModelSim SE User s Manual 6 Mixed VHDL and Verilog Designs Chapter contents Separate compilers common libraries 6 128 Mapping data types 6 128 VHDL generics 6 128 Verilog parameters 6 129 VHDL and Verilog ports 6 129 Verilog states 6 130 VHDL instantiation of Verilog design units 6 132 Verilog instantiation criteria 6 132 Component declaration 6 132 vgencomp component declaration 6 134 VCD output 6 135 Verilog instantiation of VHDL design units 6 136 VHDL instantiation criteria 6 136 SDF annotation 6 136 ModelSim single kernel simulation SKS allows you to simulate designs that are written in VHDL and or Verilog This chapter outlines data mapping and the criteria established to instantiate design units between HDLs The boundaries between VHDL and Verilog are enforced at the level of a design unit This means that although a design unit must be either all VHDL or all Verilog it may instantiate design units from either language Any instance in the design hierarchy may be a design unit from either HDL without restriction SKS technology allows the top level design unit to be either VHDL or Verilog As you traverse the design hierarchy instantiations may freely switch back and forth between VHDL and Verilog ModelSim SE User s Manual Mixed VHDL and Verilog Designs 6 127 Separate co
323. l 15 Logic Modeling Hardware Models Chapter contents VHDL Hardware Modelinterface 15 364 Creating foreign architectures with hm_entity 15 365 Vector ports ee ee 15 367 Hardware model commands 15 368 Logic Modeling hardware models can be used with ModelSim VHDL and Verilog A hardware model allows simulation of a device using the actual silicon installed as a hardware model in one of Logic Modeling s hardware modeling systems The hardware modeling system is a network resource with a procedural interface that is accessed by the simulator This chapter describes how to use Logic Modeling hardware models with ModelSim gt Note Please refer to the Logic Modeling documentation for details on using the hardware modeler This chapter only describes the specifics of using hardware models with ModelSim SE ModelSim SE User s Manual Logic Modeling Hardware Models 15 363 VHDL Hardware Model interface VHDL Hardware Model interface ModelSim VHDL interfaces to a hardware model through a foreign architecture The foreign architecture contains a foreign attribute string that associates a specific hardware model with the architecture On elaboration of the foreign architecture the simulator automatically loads the hardware modeler software and establishes communication with the specific hardware model The ModelSim software locates the hardware modeler interface
324. l Windows Some models in the SmartModel library provide access to internal registers with a feature called SmartModel Windows Refer to Logic Modeling s SmartModel library documentation for details on this feature The simulator interface to this feature is described below Window name syntax is important Beginning in version 5 3c of ModelSim window names that are not valid VHDL or Verilog identifiers are converted to VHDL extended identifiers For example with a window named z1110 GSR OR Modelsim will treat the name as z1110 GSR OR for all commands including Imcwin add wave and examine You must then use that name in all commands For example add wave top swift_model z1I10 GSR OR As with all extended identifiers case is important ReportStatus The ReportStatus command displays model information including the names of window registers For example imc top ul ReportStatus SmartModel Windows description WA Read Only Read Only WB 1 bit WC 64 bit This model contains window registers named wa wb and wc These names can be used in subsequent window Imewin commands SmartModel Imcwin commands The following window commands are supported Imewin read lt window_instance gt lt radix gt e Imewin write lt window_instance gt lt value gt e Imcwin enable lt window_instance gt e Imcwin disable lt window_instance gt e Imewin release lt window_instance gt Each command requires a window i
325. l library and the rest of the design One case where you wouldn t follow this flow is when the testbench has hierarchical references into the cell library Optimizing the library alone would result in unresolved references In such a case you ll have to compile the library design and testbench with fast in one invocation of the compiler The hierarchical reference cells are then not optimized You can use the write report command CR 281 command and the debugCellOpt argument to vlog command CR 250 to obtain information about which cells have and have not been optimized write report produces a text file that lists all modules Modules with cell following their names are optimized cells For example Module top Architecture fast Module bottom cell ModelSim SE User s Manual Verilog Simulation 5 91 Compiling for faster performance Architecture fast In this case both top and bottom were compiled with fast but top was not optimized and bottom was The debugCellOpt argument is used with fast when compiling the cell library Using this argument results in Transcript window output that identifies why certain cells were not optimized Referencing the optimized design The compiler automatically assigns a secondary name to distinguish the design specific optimized code from the unoptimized code that may coexist in the same library The default secondary name for optimized code is fast and the default sec
326. lSim Graphic Interface ModelSim SE User s Manual Wave window Setting Wave window display properties You can define the display properties of the pathname and values window panes by selecting Edit gt Display Properties Wave window MEET Window Properties iof x Display Signal Path Snap Distance fo H elements f 0 pixels Use 0 for full path Row Margin la pixels Child Row Margin Left Right 2 pixels Dataset Prefix Display Justify Value C Aways Show Dataset Prefixes Show Dataset Prefixes if 2 or more C Never Show Dataset Prefixes OK Cancel The Wave Window Properties dialog box includes the following options Display Signal Path Sets the display to show anything from the full pathname of each signal e g sim top clk to only its leaf element e g sim clk A non zero number indicates the number of path elements to be displayed The default is Full Path Justify Value Specifies whether the signal values will be justified to the left margin or the right margin in the values window pane Snap Distance Specifies the distance the cursor needs to be placed from an item edge to jump to that edge a O specification turns off the snap Row Margin Specifies the distance in pixels between top level signals Child Row Margin Specifies the distance in pixels between child signals ModelSim SE User s Manual ModelSim Graphic Interface 8 235 Wave window e Dataset Prefix Sp
327. lay mode with the delay_mode_unit compiler option or the delay_mode_unit compiler directive Zero delay mode In zero delay mode the distributed delays are set to zero and the specify path delays and timing constraints are ignored Select this delay mode with the delay_mode_zero compiler option or the delay_mode_zero compiler directive 5 98 Verilog Simulation ModelSim SE User s Manual System Tasks System Tasks The IEEE Std 1364 defines many system tasks as part of the Verilog language and ModelSim Verilog supports all of these along with several non standard Verilog XL system tasks The system tasks listed in this chapter are built into the simulator although some designs depend on user defined system tasks implemented with the Programming Language Interface PLI or Verilog Procedural Interface VPI If the simulator issues warnings regarding undefined system tasks then it is likely that these system tasks are defined by a PLI VPI application that must be loaded by the simulator IEEE Std 1364 system tasks The following system tasks are described in detail in the IEEE Std 1364 Timescale tasks Simulator Simulation time Command line control tasks functions input printtimescale finish realtime test plusargs timeformat stop stime value plusargs time Probabilistic Conversion Stochastic Timing check distribution functions analysis tasks tasks functions dist_chi_square bitstoreal q_add hold
328. layed in the List window Trigger Does not trigger line Specifies that a change in the value of the selected item does not affect the List window The trigger specification affects the trigger property of the selected item See also Setting List window display properties 8 178 ModelSim SE User s Manual ModelSim Graphic Interface 8 183 List window Examining simulation results with the List window Because you can use the Main window View menu 8 162 to create a second List window you can reformat another List window after the simulation run if you decide a different format would reveal the information you re after Compare the two illustrations File Edit Markers Prop Window The divider bar separates time and nsy top clk top paddr top pdata top saddr y delta from values delta top prw top stw y signal values are top pstb y top sstb y A top prd topesrd listed in symbolic ld i cello Dei pe een 500 0 1 01 1 00000010 0000000000000010 O O 1 00000010 Z ias 505 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 Of 520 0 001 1 00000010 0000000000000010 0 1 1 00000010 Of 540 0 1011 00000010 0000000000000010 0 1 1 00000010 OF 560 0 001 1 00000010 0000000000000010 0 1 1 00000010 Of 580 0 1011 00000010 0000000000000010 0 1 1 00000010 OF 585 0 1 0 1 1 00000010 0000000000000010 0 1 0 00000010 OF 590 0 1010 00000010 0000000000000010 0 1 0 00000010 OF 600 0 001 0 00000010 000
329. ler ModelSim SE User s Manual Verilog Simulation 5 83 Simulation Simulation The ModelSim simulator can load and simulate both Verilog and VHDL designs providing a uniform graphic interface and simulation control commands for debugging and analyzing your designs The graphic interface and simulator commands are described elsewhere in this manual while this section focuses specifically on Verilog simulation Invoking the simulator A Verilog design is ready for simulation after it has been compiled into one or more libraries The simulator may then be invoked with the names of the top level modules many designs contain only one top level module For example if your top level modules are testbench and globals then invoke the simulator as follows vsim testbench globals Note When working with designs that contain optimized code this syntax may vary Please see Compiling for faster performance 5 90 for details If a top level module name is not specified Model Sim will present the Load Design dialog box from which you can choose one or more top level modules See Simulating with the graphic interface 8 256 for more information After the simulator loads the top level modules it iteratively loads the instantiated modules and UDPs in the design hierarchy linking the design together by connecting the ports and resolving hierarchical references By default all modules and UDPs are loaded from the library named w
330. ler The Performance Analyzer feature in ModelSim is a statistical sampling profiler It periodically wakes up and samples the current simulation at a user determined rate and records what is executing in the simulation during the sample period The advantage of statistical analysis is that an entire simulation may not have to be run to get good information from the Performance Analyzer A few thousand samples for example can be accumulated before pausing the simulation to see where simulation time is being spent 9 282 Performance Analyzer ModelSim SE User s Manual Getting Started During sampling the Samples field in the footer of the Main window displays the number of profiling samples collected and each sample becomes one data point in the simulation profile jw ModelSim SE File Edit Design View Project Run Compare Macro Options Window Help eo Sff AXDA Mark at 4906800 ns Primary Channel test ringbuf test rin H AXDA Mark at 4907800 ns Primary Channel 7 a ETA RXDA Mark at 4908200 ns Primary Channel fing_inst ringbuf f 4 PDA Mark at 4908600 ns Primary Channel MM Package textio H RXDA Mark at 4909600 ns Primary Channel Pack td loai H AXDA Mark at 4910800 ns Primary Channel E Package std_logic HA DA Mark at 4911400 ns Primary Channel MM Package std_logic_ M Package std_logic_ MM Package standard H AXDA Mark at 4911800 ns Primary Channel H AXDA Mark
331. level testbench One exception is when you have a single instance in the SDF file See Instance specification 12 326 for an example A common example for both VHDL and Verilog test benches is provided below For simplicity the test benches do nothing more than instantiate a model that has no ports VHDL testbench entity testbench is end architecture only of testbench is component myasic end component begin dut myasic end Verilog testbench module testbench myasic dut endmodule The name of the model is myasic and the instance label is dut For either testbench an appropriate simulator invocation might be vsim sdfmax testbench dut myasic sdf testbench Optionally you can leave off the name of the top level vsim sdfmax dut myasic sdf testbench The important thing is to select the instance for which the SDF is intended If the model is deep within the design hierarchy an easy way to find the instance name is to first invoke the simulator without SDF options open the structure window navigate to the model instance select it and enter the environment command CR 114 This command displays the instance name that should be used in the SDF command line option ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 337 Troubleshooting Mistaking a component or module name for an instance label Another common error is to specify the component or module name rather than the i
332. log XL acc_decompile_expr routine The condition argument must be a handle obtained from the acc_handle_condition routine The value returned by acc_decompile_exp is the string representation of the condition expression char tf_dumpfilename void This routine returns the name of the VCD file void tf_dumpflush void A call to this routine flushes the VCD file buffer same effect as calling dumpflush in the Verilog code int tf_getlongsimtime int aof_hightime This routine gets the current simulation time as a 64 bit integer The low order bits are returned by the routine while the high order bits are stored in the aof_hightime argument 64 bit support in the PLI The PLI function acc_fetch_paramval cannot be used on 64 bit platforms to fetch a string value of a parameter Because of this the function acc_fetch_paramval_str has been added to the PLI for this use acc_fetch_paramval_str is declared in acc_user h It functions in a manner similar to acc_fetch_paramval except that it returns a char acc_fetch_paramval_str can be used on all platforms PLI VPI tracing The foreign interface tracing feature is available for tracing PLI and VPI function calls Foreign interface tracing creates two kinds of traces a human readable log of what functions were called the value of the arguments and the results returned and a set of C language files that can be used to replay what the foreign interface code did The purpos
333. log construct matching 12 331 Optional edge specifications 12 333 Optional conditions 12 334 Rounded timing values 12 335 SDF for Mixed VHDL and Verilog Designs 12 336 Interconnect delays 2 2 12 336 Troubleshooting por aa 1233 Specifying the wrong instance 12 337 Mistaking a component or module name fora an instance label 12 338 Forgetting to specify the instance 12 338 Obtaining the SDF specification 2 12 339 This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting Verilog and VHDL VITAL timing data can be annotated from SDF files by using the simulator s built in SDF annotator ASIC and FPGA vendors usually provide tools that create SDF files for use with their cell libraries Refer to your vendor s documentation for details on creating SDF files for your library Many vendors also provide instructions on using their SDF files and libraries with ModelSim The SDF specification was originally created for Verilog designs but it has also been adopted for VHDL VITAL designs In general the designer does not need to be familiar with the details of the SDF specification because the cell library provider has already supplied tools that create SDF files
334. ls and Drive is the default for resolved signals If you prefer Freeze as the default for resolved and unresolved signals you can change the default force kind in the modelsim ini file see Projects and system initialization 2 25 Kind Drive Attaches a driver to the signal and drives the specified value until the signal or net is forced again or until it is unforced with a noforce command CR 138 This value is illegal for unresolved VHDL signals 8 196 ModelSim Graphic Interface ModelSim SE User s Manual Signals window Kind Deposit Sets the signal or net to the specified value The value remains until there is a subsequent driver transaction or until the signal or net is forced again or until it is unforced with a noforce command CR 138 Delay For Allows you to specify how many time units from the current time the stimulus is to be applied Cancel After Cancels the force command CR 121 after the specified period of simulation time e OK When you click the OK button a force command CR 121 is issued with the parameters you have set and is echoed in the Main window If more than one signal is selected to force the next signal down appears in the dialog box each time the OK button is selected Unique force parameters can be set for each signal Adding HDL items to the Wave and List windows or a logfile Before adding items to the List or Wave window you may want to set the window display properties see
335. lt left button double click gt select word lt left button double click gt drag select word word lt control left button click gt move insertion cursor without changing the selection lt left button click gt on previous ModelSim or VSIM prompt copy and paste previous command string to current prompt lt middle button click gt paste clipboard lt middle button press gt drag scroll the window Keystrokes UNIX Keystrokes Windows Result lt left right arrow gt move cursor left right one character lt control gt lt left right arrow gt move cursor left right one word lt shift gt lt left right up down arrow gt extend selection of text lt control gt lt shift gt lt left right arrow gt extend selection of text by word lt up down arrow gt scroll through command history in Source window moves cursor one line up down lt control gt lt up down gt moves cursor up down one paragraph lt control gt lt home gt move cursor to the beginning of the text lt control gt lt end gt move cursor to the end of the text lt backspace gt lt control h gt lt backspace gt delete character to the left lt delete gt lt control d gt lt delete gt delete character to the right none esc cancel lt alt gt activate or inactivate menu bar mode
336. lt file name is mgc_location_map see How location mapping works E 438 for more details pref tcl contains defaults for fonts colors prompts window positions and other simulator window characteristics see Preference variables located in TCL files B 406 for specific details on the pref tcl file modelsim tcl contains user customized settings for fonts colors prompts window positions and other simulator window characteristics see Preference variables located in TCL files B 406 for specific details on the modelsim tcl file ModelSim SE User s Manual Projects and system initialization 2 37 System initialization Environment variables accessed during startup The table below describes the environment variables that are read during startup They are listed in the order in which they are accessed For more information on environment variables see Environment variables B 393 Environment variable Purpose MODEL_TECH set by ModelSim to the directory in which the binary executables reside e g modeltech lt platform gt MODEL_TECH_OVERRIDE provides an alternative directory for the binary executables MODEL_TECH is set to this path MODELSIM identifies path to the modelsim ini file MGC_WD identifies the Mentor Graphics working directory set by Mentor Graphics tools MGC_LOCATION_MAP identifies the path to the location map file set by ModelSim if not defin
337. lues in the List window Setting time markers in the List window List window keyboard shortcuts Saving List window data to a file Process window The Process window menu Mi Signals window The Signals window menu aba Selecting HDL item types to view Forcing signal and net values Adding HDL items to the Wave and Em ar ora log ila Finding HDL items in the Signals window Setting signal breakpoints Defining clock signals Source window The Source window menu ibat The Source window toolbar Setting file line breakpoints Editing the source file in the Source window Checking HDL item values and descriptions Finding and replacing in the Source window Setting tab stops in the Source window Structure window The Structure window menu ihar Finding items in the Structure window Variables window The Variables window menu vis Wave window Pathname pane Values pane Waveform pane Cursor panes HDL items you can view Adding HDL items in the Wave window The Wave window menu bar The Wave window toolbar Using Dividers Splitting Wave window panes i Combining items in the Wave window Editing and formatting HDL items in the Wave window E Setting Wave window display properties Setting signal breakpoints Finding items by name or value in the Wave window Searching for item values in the Wave window Using time cursors in the Wave window 8 180 8 181 8 184 8 185 8 185 8 187 8 188 8 189 8 1
338. ly modifies library mappings in the current INI file Reading variable values from the INI file These Tcl functions allow you to read values from the modelsim ini file GetIniInt lt var_name gt lt default_value gt Reads the integer value for the specified variable GetIniReal lt var_name gt lt default_value gt Reads the real value for the specified variable GetProfileString lt section gt lt var_name gt lt default gt Reads the string value for the specified variable in the specified section Optionally provides a default value if no value is present Setting Tcl variables with values from the modelsim ini file is one use of these Tcl functions For example set MyCheckpointCompressMode GetIniInt CheckpointCompressMode 1 set PrefMain file GetProfileString vsim TranscriptFile B 402 ModelSim Variables ModelSim SE User s Manual Preference variables located in INI files Variable functions Several of the more commonly used modelsim ini variables are further explained below Environment variables You can use environment variables in your initialization files Use a dollar sign before the environment variable name Examples Library work SHOME work_lib test_lib STESTNUM work vsim IgnoreNote SIGNORE_ASSERTS IgnoreWarning IGNORE_ASSERTS IgnoreError 0 IgnoreFailure 0 Tip There is one environment variable MODEL_TECH that you cannot and should not set MODEL
339. m VHDL supports both the IEEE 1076 1987 and 1076 1993 VHDL the 1164 1993 Standard Multivalue Logic System for VHDL Interoperability and the 1076 2 1996 Standard VHDL Mathematical Packages standards Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with either IEEE Standard 1076 1987 or 1076 1993 ModelSim Verilog is based on the IEEE Std 1364 Standard Hardware Description Language Based on the Verilog Hardware Description Language The Open Verilog International Verilog LRM version 2 0 is also applicable to a large extent Both PLI Programming Language Interface and VCD Value Change Dump are supported for ModelSim PE and SE users In addition all products support SDF 1 0 through 3 0 VITAL 2 2b VITAL 95 IEEE 1076 4 1995 and VITAL 2000 Assumptions We assume that you are familiar with the use of your operating system You should also be familiar with the window management functions of your graphic interface either OpenWindows OSF Motif CDE HP VUE KDE GNOME or Microsoft Windows 95 98 ME NT 2000 We also assume that you have a working knowledge of VHDL and Verilog Although ModelSim is an excellent tool to use while learning HDL concepts and practices this document is not written to support that goal If you need more information about HDLs check out our Online References www model com 1 22 Finally we make the assumption that you have worked the appropriate lessons in
340. m Verilog uses operating system calls to dynamically load PLI and VPI applications when the simulator loads a design Therefore the applications must be compiled and linked for dynamic loading on a specific operating system The PLI VPI routines are declared in the include files located in the ModelSim lt install_dir gt modeltech include directory The acc_user h file declares the ACC routines the veriuser h file declares the TF routines and the vpi_user h file declares the VPI routines The following instructions assume that the PLI or VPI application is in a single source file For multiple source files compile each file as specified in the instructions and link all of the resulting object files together with the specified link instructions Windows NT 95 98 2000 platforms Under Windows ModelSim loads a 32 bit dynamically linked library for each PLI VPI application The following compile and link steps are used to create the necessary dll file and other supporting files using the Microsoft Visual C C compiler cl c I lt install_dir gt modeltech include app c link dll export lt init_function gt app obj lt install_dir gt modeltech win32 mtipli lib For the Verilog PLI the lt init_function gt should be init_usertfs Alternatively if there is no init_usertfs function the lt init_function gt specified on the command line should be veriusertfs For the Verilog VPI the lt init_function gt should be vlog_startup_rout
341. m the registry Windows or HOME modelsim UNIX 12 Finds the modelsim tcl file by evaluating the following conditions e use MODELSIM_TCL if it exists Gf MODELSIM_TCL is a list of files each file is loaded in the order that it appears in the list else e use modelsim tcl else e use HOME modelsim tcl if it exists That completes the initialization sequence Also note the following about the modelsim ini file e When you change the working directory within ModelSim the tool reads the library vcom and vlog sections of the local modelsim ini file When you make changes in the compiler options dialog or use the vmap command the tool updates the appropriate sections of the file The pref tcl file references the default ini file via the GetPrivateProfileString Tcl command The ini file that is read will be the default file defined at the time pref tcl is loaded 2 40 Projects and system initialization ModelSim SE User s Manual 3 Design libraries Chapter contents Design library contents 2 2 8 42 Design unit information 3 42 Design library types 2 84D Working with design libraries 2 1 3 43 Creating a library 2 2 2 ee 8 48 Managing library contents A Assigning a logical name to a design ibrary e w op b a o s A Moving a library 0 aa 3 49 Specifying the resource libraries 3 50 V
342. m tools There are seven possible debugger states one for each button and an idle or waiting state when no button is active The button activated states are Button Description Stop stop after next expression used to get out of slow fast nonstop mode Next execute one expression then revert to idle Slow execute until end of procedure stopping at breakpoints or when the state changes to stop after each execution stop for delay milliseconds the delay can be changed with the and buttons Fast execute until end of procedure stopping at breakpoints Nonstop execute until end of procedure without stopping at breakpoints or updating the display Break terminate execution of current procedure Closing the debugger doesnt quit it it only does wm withdraw The debugger window will pop up the next time a prepared procedure is called Make sure you close the debugger with Debugger gt Close Breakpoints To set unset a breakpoint double click inside the listing The breakpoint will be set at the innermost available expression that contains the position of the click There s no support for conditional or counted breakpoints TDebug for sim Debugger Options Selection Variables Proc Apply WaveProp treename 5 treename waveconfig signalnamewidth vsimPriv wayeprop_sigwh treename waveconfig snapdistance vsimPriv waveprop_snapdi breakpoint Th
343. mPriv DragDrop_DropHa vsimPriv DragDrop_DropHa alt tiaia Dri ieee arabe The debugger window is divided into the main region with the name of the current procedure Proc a listing in which the expression just executed is highlighted the Result of this execution and the currently available Variables and their values an entry to Eval expressions in the context of the current procedure and some button controls for the state of the debugger A procedure listing displayed in the main region will have a darker background on all lines that have been prepared You can prepare or restore additional lines by selecting a region lt Button 1 gt standard selection and choosing Selection gt Prepare Proc or Selection gt Restore Proc from the debugger menu or by pressing P or R When using Prepare and Restore try to be smart about what you intend to do If you select just a single word plus some optional white space it will be interpreted as the name of a procedure to prepare or restore Otherwise if the selection is owned by the listing the corresponding lines will be used Be careful with partial prepare or restore If you prepare random lines inside a switch or bind expression you may get surprising results on execution because the parser doesn t know about the surrounding expression and can t try to prevent problems 8 272 ModelSim Graphic Interface ModelSim SE User s Manual ModelSi
344. mand CR 168 returns a list of current settings for either the simulator state or simulator control variables Use the following commands at either the ModelSim or VSIM prompt report simulator state report simulator control Personal preferences There are several preferences stored by ModelSim on a personal basis independent of modelsim ini or modelsim tcl files These preferences are stored in HOME modelsim on UNIX and in the Windows Registry under HKEY_CURRENT_USER Software Model Technology Incorporated ModelSim cwd History of the last five working directories pwd This history appears in the Main window File menu e phst Project History pinit Project Initialization state one of Welcome OpenLast NoWelcome This determines whether the Welcome To ModelSim dialog box appears when you invoke the tool printersetup All setup parameters related to Printing i e current printer etc The HKEY_CURRENT_USER key is unique for each user Login on Windows NT Returning to the original ModelSim defaults If you would like to return ModelSim s interface to its original state simply rename or delete the existing modelsim tcl and modelsim ini files ModelSim will use pref tcl for GUI preferences and make a copy of lt install_dir gt modeltech modelsim ini to use the next time ModelSim is invoked without an existing project if you start a new project the new MPF file will use the settings in the new modelsim ini fil
345. matches the specified Tcl glob pattern printenv CR 152 echoes to the Main window the current names and values of all environment variables 16 378 Tcl and ModelSim ModelSim SE User s Manual ModelSim Tel time commands ModelSim Tcl time commands ModelSim Tcl time commands make simulator time based values available for use within other Tcl procedures Time values may optionally contain a units specifier where the intervening space is also optional If the space is present the value must be quoted e g 10ns 10 ns Time values without units are taken to be in the UserTimeScale Return values are always in the current Time Scale Units All time values are converted to a 64 bit integer value in the current Time Scale This means that values smaller than the current Time Scale will be truncated to 0 Conversions Command Description intToTime lt intHi32 gt lt intLo32 gt converts two 32 bit pieces high and low order into a 64 bit quantity Time in ModelSim is a 64 bit integer RealToTime lt real gt converts a lt real gt number to a 64 bit integer in the current Time Scale scaleTime lt time gt lt scaleFactor gt returns the value of lt time gt multiplied by the lt scaleFactor gt integer Relations Command Description eqTime lt time gt lt time gt evaluates for equal neqTime lt time gt lt time gt evaluates for not equal gtTime lt time gt l
346. ment variable B 393 MODEL_TECH_TCL environment variable B 393 Modeling memory in VHDL E 440 ModelSim custom setup with daemon options D 420 license file D 418 MODELSIM environment variable B 393 modelsim ini default to VHDL93 B 405 hierarchial library mapping B 403 opening VHDL files B 405 to specify a startup file B 404 turning off arithmetic warnings B 404 turning off assertion messages B 404 using environment variables in B 403 using to create a transcript file B 403 using to define force command default B 404 using to define restart command defaults B 405 using to delay file opening B 405 MODELSIM_TCL environment variable B 393 MPF file loading from the command line 2 36 MTI_TF_LIMIT environment variable B 393 Multiple drivers on unresolved signal 8 253 multiple simulations 7 137 N n simulator state variable B 408 negative timing checks 5 102 Nets adding to the Wave and List windows 8 197 displaying in Dataflow window 8 171 displaying values in Signals window 8 193 forcing signal and net values 8 196 saving values as binary log file 8 197 viewing waveforms 8 216 New features F 447 Next and previous edges finding 8 244 C 410 No space in time literal 8 253 NoCaseStaticError ini file variable B 397 NoDebug ini file variable VCOM B 397 NoDebug ini file variable VLOG B 398 NoOthersStaticError ini file variable B 397 Notepad windows text editing 8 168 C 413 NoVital ini file variable B 397 NoVitalCheck i
347. menu CR 112 enables a previously disabled menu enable_menuitem CR 113 enables a previously disabled menu item 8 278 ModelSim Graphic Interface ModelSim SE User s Manual Customizing the interface Customizing the interface Try customizing ModelSim s interface yourself use the command examples for add button CR 26 and add_menu CR 31 to add a button to the Main window and a new menu to the Signals window 8 193 Results of the button and menu commands are shown below Buttons the easy way The Button Adder 8 269 tool makes adding buttons easy Select Window gt Customize in any window to access the Button Adder Buttons you create are not permanent they exist only during the current session To reuse a button save the Main transcript File gt Save Transcript As after the button is created Edit the file to contain only button creation commands then pass the filename as an argument to the do command CR 104 to recreate the button Xi ModelSim lel ES File Sa Denn sal Project Compare Options Window Help ModelSim gt add button pwd transcribe pwd NoDisable controls button_11 pwd E modelsim55_020701 Awin32 ModelSim gt P Project test Noa No Design Loaded gt lt No Conte 4 Jug Mne J mine ic clk pry pstrb pray paddr OOOUUULT pdata 0000000000000001 srw 0 sstrb 1 stdy 0 saddr 00000001 sdata 0000000000000001 Aoo i sim top
348. mes remove_netnames suppress_faults The following Verilog XL compiler directives produce warning messages in ModelSim Verilog These are not implemented in ModelSim Verilog and any code containing these directives may behave differently in ModelSim Verilog than in Verilog XL default_trireg_strength signed unsigned ModelSim SE User s Manual Verilog Simulation 5 107 Using the Verilog PLI VPI Using the Verilog PLI VPI The Verilog PLI Programming Language Interface and VPI Verilog Procedural Interface both provide a mechanism for defining system tasks and functions that communicate with the simulator through a C procedural interface There are many third party applications available that interface to Verilog simulators through the PLI see Third party PLI applications 5 120 In addition you may write your own PLI VPI applications ModelSim Verilog implements the PLI as defined in the IEEE Std 1364 with the exception of the acc_handle_datapath routine We did not implement the acc_handle_datapath routine because the information it returns is more appropriate for a static timing analysis tool In version 5 5 the VPI is partially implemented as defined in the IEEE Std 1364 The list of currently supported functionality can be found in the following directory lt install_dir gt modeltech docs technotes Verilog_VPI note The IEEE Std 1364 is the reference that defines the usage of the PLI VPI routines This
349. mmands and quits the simulator at time 1200 vcd files output vcd ved add r force reset 1 0 force data_in 0 0 force clk 0 0 run 100 force clk 1 0 0 50 repeat 100 run 100 ved off force reset 0 0 force data_in 1 0 run 100 vcd on run 850 force reset 1 0 run 50 ved checkpoint 13 346 Value Change Dump VCD Files ModelSim SE User s Manual A VCD file from source to output VCD output The VCD file created as a result of the preceding scenario would be called output vcd The following pages show how it would look VCD output Scomment File created using the following command vcd files output vcd Sdate Fri Jan 12 09 07 17 2000 Send Sversion ModelSim EE PLUS 5 4 Send Stimescale ins Send Sscope module shifter_mod Send Svar wire clk Send Svar wire reset Send Svar wire data_in Send Svar wire q 8 Send Svar wire q 7 Send Svar wire amp q 6 end Svar wire q 5 Send Svar wire q 4 Send Svar wire q 3 Send Svar wire q 2 end Svar wire q 1 Send Svar wire q 0 Send Supscope end Senddefinitions end 0 Sdumpvars 0 1 04 o 0 0 amp Ow 0 0 0 0 0 end 100 Li 150 o 200 ag Sdumpoff x x x x X X x x x x xt X end 300 Sdumpon 1 o 14 o 0 ModelSim SE User s Manual Value Change Dump VCD Files 13 347 A VCD file from source to output
350. modules of which 0 are inlined Optimizing module design cl Optimizing module testbench cl Optimizing module configl cl vlog fast c2 testbench v design v config2 v Compiling module testbench Compiling module design Compiling module config2 Top level modules testbench config2 ModelSim SE User s Manual Verilog Simulation 5 93 Compiling for faster performance Analyzing design Optimizing 3 modules of which 0 are inlined Optimizing module design c2 Optimizing module testbench c2 Optimizing module config2 c2 Since the module testbench has two secondary names you must specify which one you want when you invoke the simulator For example o vsim testbench cl configl Note that it is not necessary to specify the secondary name for config1 because it has only one secondary name If you omit the secondary name the simulator defaults to loading the secondary name specified in the most recent compilation of the module If you prefer to use the Load Design dialog box to select top level modules then those modules compiled with fast can be expanded to view their secondary names Click on the one you wish to simulate To view the library contents select Design gt Browse Libraries to see the modules and their associated secondary names Also you can execute the vdir command CR 223 on a specific module For example VSIM 1 gt vdir design MODULE desig
351. mpiler is building the design hierarchy propagating parameters and analyzing design object usage This information is then used in the final step of generating module code optimized for the specific design Note that some modules are inlined into their parent modules Once the design is compiled it can be simulated in the usual way vsim c testbench Loading work testbench fast Loading work cpu fast VSIM 1 gt run all VSIM 2 gt quit As the simulator loads the design it issues messages indicating that the optimized modules are being loaded There are no messages for loading the inlined modules because their code is inlined into their parent modules B Note If you want to optimize a very large netlist you should only optimize the cell libraries using the fast option The forcecode option should also be specified The netlist itself should be compiled with the default settings Optimizing in this manner reduces compilation time and compiler memory usage significantly Compiling gate level designs with fast Gate level designs often have large netlists that are slow to compile with fast In most cases we recommend the following flow for optimizing gate level designs e Compile the cell library using fast and the forcecode argument The forcecode argument ensures that code is generated for in lined modules e Compile the device under test and testbench without fast e Create separate work directories for the cel
352. mpilers common libraries Separate compilers common libraries VHDL source code is compiled by vcom CR 217 and the resulting compiled design units entities architectures configurations and packages are stored in a library Likewise Verilog source code is compiled by vlog CR 250 and the resulting design units modules and UDPs are stored in a library Libraries can store any combination of VHDL and Verilog design units provided the design unit names do not overlap VHDL design unit names are changed to lower case See Design libraries 3 41 for more information about library management and see the vcom CR 217 and the vlog commands Mapping data types VHDL generics Cross HDL instantiation does not require any extra effort on your part As ModelSim loads a design it detects cross HDL instantiations made possible because a design unit s HDL type can be determined as it is loaded from a library and the necessary adaptations and data type conversions are performed automatically A VHDL instantiation of Verilog may associate VHDL signals and values with Verilog ports and parameters Likewise a Verilog instantiation of VHDL may associate Verilog nets and values with VHDL ports and generics ModelSim automatically maps between the HDL data types as shown below VHDL type Verilog type integer integer or real real integer or real time integer or real physical integer or real enumerati
353. mplementation for ModelSim The VCD file format is specified in the IEEE 1364 standard It is an ASCII file containing header information variable definitions and variable value changes VCD is in common use for Verilog designs and is controlled by VCD system task calls in the Verilog source code ModelSim provides simulator command equivalents for these system tasks and extends VCD support to VHDL designs the ModelSim commands can be used on either VHDL or Verilog designs VHDL VCD files can be used for resimulation with the vsim vcdread command See Resimulating a VHDL design from a VCD file 13 344 B Note If you need vendor specific ASIC design flow documentation that incorporates VCD please contact your ASIC vendor ModelSim SE User s Manual Value Change Dump VCD Files 13 341 ModelSim VCD commands and VCD tasks ModelSim VCD commands and VCD tasks ModelSim VCD commands map to IEEE Std 1364 VCD system tasks and appear in the VCD file along with the results of those commands The table below maps the VCD commands to their associated tasks VCD commands VCD system tasks ved add CR 198 dumpvars ved checkpoint CR 199 dumpall ved file CR 208 dumpfile ved flush CR 212 dumpflush ved limit CR 213 dumplimit ved off CR 214 dumpoff ved on CR 215 dumpon ModelSim versions 5 5 and later support multiple VCD files This functionality is
354. multiplier is a real number that is used to scale the corresponding delay in the SDF file lt scale_type gt String that overrides the lt mtm_spec gt delay selection Optional The lt mtm_spec gt delay selection is always used to select the delay scaling factor but if a lt scale_type gt is specified then it will determine the min typ max selection from the SDF file The allowed strings are from_min from_minimum from_typ from_typical from_max from_maximum and from_mtm Case is ignored and the default is from_mtm which means to use the lt mtm_spec gt value 12 330 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual Verilog SDF Examples Optional arguments can be omitted by using commas or by leaving them out if they are at the end of the argument list For example to specify only the SDF file and the instance it applies to Ssdf_annotate myasic sdf testbench ul To also specify maximum delay values Ssdf_annotate myasic sdf testbench ul maximum SDF to Verilog construct matching The annotator matches SDF constructs to corresponding Verilog constructs in the cells Usually the cells contain path delays and timing checks within specify blocks For each SDF construct the annotator locates the cell instance and updates each specify path delay or timing check that matches An SDF construct can have multiple matches in which case each matching specify statemen
355. n Optimized Module t1 Optimized Module t2 gt Note In some cases an optimized module will have __ lt n gt appended to its secondary name This happens when multiple instantiations of a module require different versions of optimized code for example when the parameters of each instance are set to different values Enabling design object visibility with the acc option Some of the optimizations performed by the fast option impact design visibility to both the user interface and the PLI routines Many of the nets ports and registers are unavailable by name in user interface commands and in the various graphic interface windows In addition many of these objects do not have PLI Access handles potentially affecting the operation of PLI applications However a handle is guaranteed to exist for any object that is an argument to a system task or function In the early stages of design you may choose to compile without the fast option so as to retain full debug capabilities Alternatively you may use one or more acc options in conjunction with fast to enable access to specific design objects However keep in mind that enabling design object access may reduce simulation performance The syntax for the acc option is as follows t acc lt spec gt lt module gt 5 94 Verilog Simulation ModelSim SE User s Manual Compiling for faster performance lt spec gt is one or more of the following characters lt
356. n and the simulator will automatically register the entries directly from the array the last entry must be 0 For example s_tfcell veriusertfs usertask 0 0 0 abc_calltf 0 Sabc lusertask 0 0 0 xyz_calltf 0 Sxyz 10 last entry must be 0 y Alternatively you can add an init_usertfs function to explicitly register each entry from the array void init_usertfs p_tfcell usertf veriusertfs while usertf gt type mti_RegisterUserTF usertf It is an error if a PLI shared library does not contain a veriusertfs array or an init_usertfs function Since PLI applications are dynamically loaded by the simulator you must specify which applications to load each application must be a dynamically loadable library see Compiling and linking PLI VPI applications 5 111 The PLI applications are specified as follows e As a list in the Veriuser entry in the modelsim ini file Veriuser pliappl so pliapp2 so pliappn so e As a list in the PLIOBJS environment variable setenv PLIOBJS pliappl so pliapp2 so pliappn so e As a pli option to the simulator multiple options are allowed pli pliappl so pli pliapp2 so pli pliappn so The various methods of specifying PLI applications can be used simultaneously The libraries are loaded in the order listed above Environment variable references can be used in the paths to the libraries in all cases ModelSim SE User s Manual Verilo
357. n Menm o s 2 s 2 ele y FAM VIEW MEW lt lt eo so we es e osos o po FAS Project menu 0 ew FA535 Compare meda F456 Options Meda F 456 Signals window changes 0 ee a FAST Source window changes 0 F458 Edit m nt e gt e os bo 8 amp F458 Optionsmenu s p so e so F 458 Wave window changes aaa a a F 459 Menu bar and toolbar aaa a F 459 Edit ment s 2 e a s amp e a b oeoa sopo F9 Compare men aaa F460 Bookmark menu aaa a a F 460 Coverage_summary window changes F 461 F 450 What s new in ModelSim ModelSim SE User s Manual Main window changes Main window changes The most obvious change in the version 5 5 Main window is the addition of the workspace See Workspace 8 158 for full details lz ModelSim Edit Design View Project Run Compare Macro Options Window Help Ba El ELER R AEL OP les counter Model Technology ModelSim SEZEE vlog 5 5 Beta 4 Compiler 2001 01 Jan 18 2001 Compiling module counter 5 5 H Top level modules counter vsim work counter vsim work counter Bi E counter counter Function increment Loading work counter quit sim vsim work counter Workspace vsim work counter y Loading work counter SIM 8 gt ModelSim 101 x File Edit Design View Run Macro in Window Help Reading E mo
358. n between the signals in a specified reference design and the signals in a specified test design compare annotate CR 66 allows a difference to be flagged as ignore or an additional text string to be attached compare clock CR 67 defines a clock for clocked comparison or if delete is specified deletes a previously defined clock compare delete CR 71 deletes a signal or region from the current open comparison compare end CR 72 destroys the compare data structures and forgets clock definitions and signals selected for comparison compare info CR 73 writes out results of the comparison writes to the transcript unless the write option is specified compare list CR 74 shows all the compare region and compare signal commands currently in effect compare options CR 75 sets values for various compare options on the Tcl parser side when subsequent commands are called these values become the defaults compare reset CR 79 clears the current compare differences allowing another compare start to be executed compare reload CR 78 reloads comparison differences to allow viewing without recomputation compare run CR 80 registers required callbacks and runs the difference computation on the signals selected for comparison reports the total number of errors found compare savediffs CR 81 saves the comparison result differences in a form that can be reloaded later compare saverules CR 82 s
359. n hierarchy 8 155 viewing library contents 3 44 virtual hide command 7 145 Virtual objects 7 144 virtual functions 7 145 virtual regions 7 146 virtual signals 7 144 virtual types 7 146 virtual region command 7 146 Virtual regions reconstruct the RTL Hierarchy in gate level design 7 146 virtual save command 7 145 virtual signal command 7 144 Virtual signals reconstruct RTL level design busses 7 145 reconstruct the original RTL hierarchy 7 145 virtual hide command 7 145 VITAL compiling and simulating with accelerated VITAL packages 4 67 compliance warnings 4 66 obtaining the specification and source code 4 65 VITAL 2000 library 3 51 VITAL packages 4 66 VPI 5 108 VSIM commands searchLog 7 147 W Warnings turning off warnings from arithmetic packages B 404 Wave format file 8 219 Wave window compare waveforms 11 316 values column 11 317 Wave window see also Windows 8 216 Waveform Comparison 11 301 add clock 11 309 add region 11 311 adding signals 11 307 clear differences 11 320 clocked comparison 11 303 11 308 11 312 command line interface 11 323 compare by region 11 311 compare by signal 11 307 compare commands 11 323 compare menu 11 318 compare options 11 314 compare tab 11 306 comparison method 11 315 comparison method tab 11 312 comparison modes 11 303 comparison wizard 11 318 continuous comparison 11 303 11 310 11 313 dataset 11 302 difference markers 11 317 end 11 319 features 11 302 flattened designs 11
360. n the current directory If you run a new simulation in the same directory the vsim wif file is overwritten with the new results Therefore you should use the w1f lt filename gt argument to the vsim command CR 258 to specify a different name if you want to save the dataset A Important You must end a simulation session with a quit or quit sim command in order to produce a valid dataset If you don t end the simulation in this manner the dataset will not close properly and ModelSim will issue an error when you try to open the dataset in subsequent sessions 7 138 Datasets saved simulations and virtuals ModelSim SE User s Manual Datasets Opening datasets To open a dataset select either File gt Open gt Dataset Main window or File gt Open Dataset Wave window O Browse Logical Name for Dataset Ok Cancel The Open Dataset dialog box includes the following options Dataset Pathname Identifies the path and filename of the logfile you want to open e Logical Name for Dataset This is the name by which the dataset will be referred By default this is the filename of the logfile A Important You must end a simulation session with a quit or quit sim command in order to produce a valid dataset If you don t end the simulation in this manner the dataset will not close properly and ModelSim will issue an error when you try to open the dataset in subsequent sessions ModelSim SE User
361. n the location of the selected cursor Match indicates that the value of the test signal matches the value of the reference signal at the time of the selected cursor Diff indicates a difference between the test and reference signal values at the selected cursor ModelSim SE User s Manual Waveform Comparison 11 317 Graphical Interface to Waveform Comparison Compare icons The Wave window includes four Find first difference waveform comparison icons that enable you to quickly locate the first and last waveform difference and move the cursor in steps to the previous Find last difference ie fe gt i ol or next difference The next and Find previous difference Find next difference previous icons move between differences on all signals in the Wave window If you want to move between differences for the selected signal only use lt tab gt next or lt shift gt lt tab gt previous Compare menu The Compare menu provides a number of options for controlling waveform comparisons wave default File Edit Cursor Zoom SHS m0 Start Comparison Comparison Wizard Run Comparison End Comparison Options Differences Rules Reload e Start Comparison Bookmark Format Window QQA i ni HE Compare by Signal Compare by Region Clocks Opens the Compare Dataset dialog box page 1 1 305 where you can enter reference and
362. n you should suspect that there are event order dependencies Tracking down event order dependencies is a tedious task so ModelSim Verilog aids you with a couple of compiler options compat This option turns off optimizations that result in different event ordering than Verilog XL ModelSim Verilog generally duplicates Verilog XL event ordering but there are cases where it is inefficient to do so Using this option does not help you find the event order dependencies but it allows you to ignore them Keep in mind that this option does not account for all event order discrepancies and that using this option may degrade performance hazards This option detects event order hazards involving simultaneous reading and writing of the same register in concurrently executing processes vsim CR 258 detects the following kinds of hazards e WRITE WRITE Two processes writing to the same variable at the same time e READ WRITE One process reading a variable at the same time it is being written to by another process ModelSim calls this a READ WRITE hazard if it executed the read first ModelSim SE User s Manual Verilog Simulation 5 85 Simulation e WRITE READ Same as a READ WRITE hazard except that ModelSim executed the write first vsim issues an error message when it detects a hazard The message pinpoints the variable and the two processes involved You can have the simulator break on the statement where the hazard is detec
363. national Inc Sun Microsystems is a registered trademark and Sun SunOS and OpenWindows are trademarks of Sun Microsystems Inc All other trademarks and registered trademarks are the properties of their respective holders Copyright c 1990 2001 Model Technology Incorporated All rights reserved Confidential Online documentation may be printed by licensed customers of Model Technology Incorporated for internal business purposes only Model Technology Incorporated 10450 SW Nimbus Avenue Bldg R B Portland OR 97223 4347 USA phone 503 641 1340 fax 503 526 5410 e mail support model com sales model com home page http www model com Table of Contents 1 Introduction 1 15 Performance tools included with ModelSim SE 1 16 ModelSim s graphic interface 1 16 Standards supported 1 17 Assumptions 1 17 Sections in this document 1 18 Command reference 1 19 Text conventions 1 20 What is an HDL item 1 20 Where to find our documentation 1 21 Download a free PDF reader with Search 1 21 Online References www model com 1 22 Comments 1 23 2 Projects and system initialization 2 25 Introduction 2 26 How do projects diferi in version 5 57 2 27 Getting started with projects 2 28 Step 1 Create a new project 2 29 Step 2 Add files to the project 2 31 Step 3 Compile the files 2 32 Step 4 Simulate a design 2 33 Other project operations 2 33 C
364. nd the actual delays observed on the module ports are taken from the path delays This is typical for most cells but a complex cell may require non zero distributed delays to work properly Even so these delays are usually small enough that the path delays take priority over the distributed delays The rule is that if a module contains both path delays and distributed delays then the larger of the two delays for each path shall be used as defined by the IEEE Std 1364 This is the default behavior but you can specify alternate delay modes with compiler directives and options These options and directives are compatible with Verilog XL Compiler delay mode options take precedence over delay mode directives in the source code ModelSim SE User s Manual Verilog Simulation 5 97 Cell Libraries Distributed delay mode In distributed delay mode the specify path delays are ignored in favor of the distributed delays Select this delay mode with the delay_mode_distributed compiler option or the delay_mode_distributed compiler directive Path delay mode In path delay mode the distributed delays are set to zero Select this delay mode with the delay_mode_path compiler option or the delay_mode_path compiler directive Unit delay mode In unit delay mode the distributed delays are set to one the unit is the time_unit specified in the timescale directive and the specify path delays and timing constraints are ignored Select this de
365. ndow will ONLY paste from the clipboard e All menus highlight their accelerator keys Quick access toolbars wave default Al Xx File Edit Cursor Zoom Compare Bookmark Format Window oS 5606 RK eX QQQQ EH HEM dede sia Drag and Drop gt Buttons on the Main Source and Wave windows provide access to commonly used commands and functions See The Main window toolbar 8 166 The Source window toolbar 8 204 and The Wave window toolbar 8 224 Drag and drop of HDL items is possible between the following windows Using the left mouse button click and release to select an item then click and hold to drag it e Drag items from these windows Dataflow List Signals Source Structure Variables and Wave windows Drop items into these windows Dataflow List and Wave windows Note Drag and drop works to rearrange items within the List and Wave windows as well Command history Avoid entering long commands twice use the down and up keyboard arrows to move through the command history for the current simulation 8 152 ModelSim Graphic Interface ModelSim SE User s Manual Common window features Automatic window updating Selecting an item in the following windows automatically updates other related ModelSim windows as indicated below Select an item in this window To update these windows Dataflow window 8 171 Process window 8 190 Signals window 8 193
366. ne Invoke the add list CR 28 command to add one or more individual items separate the names with a space add list lt item_name gt lt item_name gt You can add all the items in the current region with this command add list Or add all the items in the design with add list r 8 180 ModelSim Graphic Interface ModelSim SE User s Manual List window Adding items with a List window format file To use a List window format file you must first save a format file for the design you are simulating The saved format file can then be used as a DO file to recreate the List window formatting Follow these steps e Add HDL items to your List window e Edit and format the items to create the view you want see Editing and formatting HDL items in the List window 8 181 e Save the format to a file by selecting File gt Save Format List window To use the format do file start with a blank List window and run the DO file in one of two ways e Invoke the do CR 104 command from the command line do lt my_list_format gt e Select File gt Load Format from the List window menu bar Select Edit gt Select All and Edit gt Delete to remove the items from the current List window or create a new blank List window by selecting View gt New gt List Main window You may find it useful to have two differently formatted windows open at the same time see Examining simulation results with the List windo
367. ng source code and without revealing internal model variables and structure gt Note ModelSim s nodebug compiler option provides protection for proprietary model information The Verilog protect compiler directive provides similar protection but uses a Cadence encryption algorithm that is unavailable to Model Technology If a design unit is compiled with nodebug the Source window will not display the design unit s source code the Structure window will not display the internal structure the Signals window will not display internal signals it still displays ports the Process window will not display internal processes and the Variables window will not display internal variables In addition none of the hidden objects may be accessed through the Dataflow window or with ModelSim commands Even with the data hiding of nodebug there remains some visibility into models compiled with nodebug The names of all design units comprising your model are visible in the library and you may invoke vsim CR 258 directly on any of these design units and see the ports Design units or modules compiled with nodebug can only instantiate design units or modules that are also compiled nodebug To restrict visibility into the lower levels of your design you can use the following nodebug switches when you compile Command and switch Result vcom nodebug ports makes the ports of a VHDL design unit invisible vlog nodebug ports makes the por
368. ng with design libraries e Library Maps to Type or Browse for a mapping for the specified library This field can be changed only when the Create a map to an existing library option is selected When you click OK ModelSim creates the specified library directory and writes a specially formatted file named _info into that directory The _info file must remain in the directory to distinguish it as a ModelSim library The new map entry is written to the modelsim ini file in the Library section See Library library path variables B 396 for more information gt Note Remember that a design library is a special kind of directory the only way to create a library is to use the ModelSim GUI or the vlib command CR 249 Do not create libraries using UNIX or Windows commands Managing library contents Library contents can be viewed deleted recompiled edited and so on using either the graphic interface or command line The Library page in the Main window workspace provides access to design units configurations modules packages entities and architectures in a library Note the icons identify whether a unit is an entity E a module M and so forth l ModelSim olx Fie Edit Design Wiew Project Run Macro Options Window Help ModelSim gt HIE ora Cc test_adder_behavioral Cc test_adder_structural N test_counter HIE testhench Library gi lt No Design Loaded gt A The Library page includes these
369. ng with the graphic interface 8 250 e Simulating with the graphic interface 8 256 ModelSim variables Several variables are available to control simulation provide simulator state feedback or modify the appearance of the ModelSim GUI To take effect some variables such as environment variables must be set prior to simulation See Appendix B ModelSim Variables for a complete listing of ModelSim variables 5 74 Verilog Simulation ModelSim SE User s Manual Compilation Compilation Before you can simulate a Verilog design you must first create a library and compile the Verilog source code into that library This section provides detailed information on compiling Verilog designs For information on creating a design library see Chapter 3 Design libraries The ModelSim Verilog compiler vlog compiles Verilog source code into retargetable executable code meaning that the library format is compatible across all supported platforms and that you can simulate your design on any platform without having to recompile your design specifically for that platform As you compile your design the resulting object code for modules and UDPs is generated into a library By default the compiler places results into the work library You can specify an alternate library with the work option The following is a simple example of how to create a work library compile a design and simulate it Contents of top v module top initial di
370. ni file variable B 397 Now simulator state variable B 408 now simulator state variable B 408 numeric_bit package 3 51 numeric_std package 3 51 NumericStdNoWarnings ini file variable B 400 O Online references 1 22 Operating systems supported 1 16 Optimize for std_logic_1164 8 254 Optimize_1164 ini file variable B 397 P Packages standard 3 50 textio 3 50 vital_memory 3 51 packages util 4 68 Parameters using with macros E 430 pathnames 11 317 PathSeparator ini file variable B 400 Performance Analyzer 9 281 parent field 9 287 commands 9 290 getting started 9 283 ModelSim SE User s Manual Index 473 hierarchical profile 9 285 in field 9 286 interpreting data 9 283 name field 9 286 profile report command 9 289 ranked profile 9 287 report option 9 289 setting preferences 9 290 statistical sampling 9 282 under field 9 286 view_profile command 9 285 view_profile_ranked command 9 286 viewing results 9 284 PLI VPI see Verilog PLI PLIOBJS environment variable B 394 port driver data capturing 13 349 Ports VHDL and Verilog 6 129 Postscript saving a waveform in 8 245 preference variables waveform compare 1 323 Preferences performance analyzer preferences 9 290 printing comparison differences 11 321 Process window see also Windows 8 190 Process without a wait statement 8 253 Processes displayed in Dataflow window 8 171 values and pathnames in Variables window 8 213 profil
371. nificant changes projects created in versions prior to 5 5 cannot be converted automatically If you created a project in an earlier version you will need to recreate itin version 5 5 With the new interface even the most complex project should take less than 15 minutes to recreate Follow the instructions in the ensuing pages to recreate your project ModelSim SE User s Manual Projects and system initialization 2 27 Getting started with projects Getting started with projects This section describes the four basic steps to working with a project For a discussion of more advanced project features see Customizing project settings 2 34 Step 1 Create a new project 2 29 This creates a mpf file and a working library Step 2 Add files to the project 2 31 Projects can reference or include HDL source files and any other files you want to associate with the project You can copy files into the project directory or simply create mappings to files in other locations Step 3 Compile the files 2 32 This checks syntax and semantics and creates the pseudo machine code ModelSim uses for simulation Step 4 Simulate a design 2 33 This specifies the design unit you want to simulate and opens a structure page in the workspace 2 28 Projects and system initialization ModelSim SE User s Manual Getting started with projects Step 1 Create a new project 1 Select Create a Project from the Welcome to Mod
372. ning messages specified by lt mnemonic gt This option only disables warning messages accompanied by a mnemonic enclosed in square brackets For example WARNING test v 2 TFMPC Too few port connections This warning message can be disabled with the nowarnTFMPC option ntc_warn This option enables warning messages from the negative timing constraint algorithm This algorithm attempts to find a set of delays for the timing check delayed net arguments such that all negative limits can be converted to non negative limits with respect to the delayed nets If there is no solution for this set of limits then the algorithm sets one of the negative limits to zero and recalculates the delays This process is repeated until a solution is found A warning message is issued for each negative limit set to zero By default these warnings are disabled ModelSim SE User s Manual Verilog Simulation 5 87 Simulation pulse_e lt percent gt This option controls how pulses are propagated through specify path delays where lt percent gt is a number between 0 and 100 that specifies the error limit as a percentage of the path delay A pulse greater than or equal to the error limit propagates to the output in transport mode transport mode allows multiple pending transitions on an output A pulse less than the error limit and greater than or equal to the rejection limit see pulse_r lt percent gt propagates to the output as an X If the r
373. nning with the number character are treated as comments If the filename in the REPORTLOG line starts with a plus character the old report logfile will be opened for appending For example the following options file would reserve one copy of the feature vsim for the user walter three copies for the user john one copy for anyone on a computer with the hostname of bob and would cause QUEUED messages to be omitted from the logfile The user rita would not be allowed to use the vsim feature RESERVE 1 vsim USER walter RESERVE 3 vsim USER john RESERVE 1 vsim HOST bob EXCLUDE vsim USER rita NOLOG QUEUED Tf this data were in the file named usr local options modify the license file DAEMON line as follows DAEMON modeltech lt install_dir gt lt platform gt modeltech Y usr local options ModelSim SE User s Manual Using the FLEXIm License Manager D 421 License administration tools License administration tools Imstat Imdown License administration is simplified by the Imstat utility Imstat allows a user of FLEXIm to instantly monitor the status of all network licensing activities Imstat allows a system administrator at a user site to monitor license management operations including e which daemons are running e which users are using individual features and e which users are using features served by a specific DAEMON The case sensitive syntax is shown below Syntax imstat a A S lt daemon
374. nput to vedread Assume that a VHDL testbench named testbench instantiates dut with an instance name of u1 and that you would like to simulate testbench and later be able to resimulate dut stand alone vsim VSIM VSIM VSIM VSIM VSIM 6 1 gt 2 gt 3 gt 4 gt 5 gt t ps testbench splitio wi vcd files nomap direction ved add ports ul run 1000 quit Now to resimulate using the VCD file vsim c t ps vcdread dump vcd dut VSIM 1 gt run 1000 VSIM 2 gt quit gt Note You must manually invoke the run command CR 176 even when using vedread ModelSim SE User s Manual Value Change Dump VCD Files 13 345 A VOD file from source to output A VCD file from source to output The following example shows the VHDL source a set of simulator commands and the resulting VCD output VHDL source code The design is a simple shifter device represented by the following VHDL source code library IEEE use TIEEE STD_L0GIC_1164 all1l entity SHIFTER_MOD is port CLK RESET IN STD_LOGIC Q INOUT STD_LOGIC_VECTOR 8 downto 0 END SHIFTER_MOD architecture RTL of SHIFTER_MOD is begin process CLK RESET begin if RESET 1 then Q lt others gt 0 elsif CLK event and CLK r Lc then Q lt Q Q left 1 downto 0 data_in end if end process end VCD simulator commands At simulator time zero the designer executes the following co
375. ns for Trigger Settings and Window Properties Window Properties page Modify Display Properties list fo S The Window Properties page includes these options Signal Names Sets the number of path elements to be shown in the List window For example 0 shows the full path 1 shows only the leaf element Max Title Rows Sets the maximum number of rows in the name pane Dataset Prefix Show All Dataset Prefixes Displays the dataset prefix associated with each signal pathname Useful for displaying signals from multiple datasets Dataset Prefix Show All Except sim Displays all dataset prefixes except the one associated with the current simulation sim Useful for displaying signals from multiple datasets 8 178 ModelSim Graphic Interface ModelSim SE User s Manual List window e Dataset Prefix Show No Dataset Prefixes Turns off display of dataset prefixes Trigger settings page The Triggers page controls the triggering for the display of new lines in the List window You can specify whether an HDL item trigger or a strobe trigger is used to determine when the List window displays a new line If you choose Trigger on Signals then you can choose between collapsed or expanded delta displays You can also choose a combination of signal or strobe triggers To use gating Signals or Strobe or both must be selected l Modify Display Properties list Deltas ExpandDeltas CollapseDeltas N
376. ns the current depth of macro call nesting n represents a macro parameter where n can be an integer in the range 1 9 returns the current simulation time expressed in the current time resolution e g 1000 ns returns the current simulation time as an absolute number of time steps e g 1000 resolution returns the current simulation time resolution Referencing simulator state variables Variable values may be referenced in simulator commands by preceding the variable name with a sign For example to use the now and resolution variables in an echo command type echo The time is now resolution Depending on the current simulator state this command could result in The time is 12390 10ps If you do not want the dollar sign to denote a simulator variable precede it with a For example now will not be interpreted as the current simulator time B 408 ModelSim Variables ModelSim SE User s Manual C Model Sim Shortcuts Appendix contents Wave window mouse and keyboard shortcuts C 410 List window keyboard shortcuts CAII Command shortcuts 2 ee C412 Command history shortcuts 2 C412 Mouse and keyboard shortcuts in the Transcript and Source windows C 413 Right mouse button 2 eee CATS This appendix is a collection of the keyboard and command shortcuts available in the ModelSim GUI ModelSim SE User s Man
377. nse files use the same license server nodes You can combine the license files by taking the set of SERVER lines from one license file and adding the DAEMON FEATURE and FEATURESET lines from all of the license files This combined file can be copied to lt install_dir gt license license dat and to any location required by the other applications Case 2 The applications use different license server nodes You cannot combine the license files if the applications use different servers Instead set the LM_LICENSE_FILE B 393 environment variable to be a list of files as follows setenv LM_LICENSE_FILE lic_filel lic_file2 lt install_dir gt license dat In Windows use semi colons to separate the file names Do not use the c option when you start the license manager daemon For example lmgrd gt report log ModelSim SE User s Manual Using the FLEXIm License Manager D 419 Format of the license file Format of the license file ModelSim license files contain three types of lines SERVER lines DAEMON lines and FEATURE lines For example SERVER hostname hostid TCP_portnumber DAEMON daemon name path to daemon path to options file FEATURE name daemon name version exp_date users_code description hostid Only the following items may be modified e the hostname on SERVER lines e the TCP_portnumber on SERVER lines e the path to daemon on DAEMON lines e the path to options file on DAEMON lines e an
378. nstance label For example the following invocation is wrong for the above testbenches vsim sdfmax testbench myasic myasic sdf testbench This results in the following error message ERROR myasic sdf The design does not have an instance named testbench myasic Forgetting to specify the instance If you leave off the instance altogether then the simulator issues a message for each instance path in the SDF that is not found in the design For example vsim sdfmax myasic sdf testbench Results in ERROR myasic sdf Failed to find INSTANCE testbench ul ERROR myasic sdf Failed to find INSTANCE testbench u2 ERROR myasic sdf Failed to find INSTANCE testbench u3 ERROR myasic sdf Failed to find INSTANCE testbench u4 ERROR myasic sdf Failed to find INSTANCE testbench u5 WARNING myasic sdf This file is probably applied to the wrong instance WARNING myasic sdf Ignoring subsequent missing instances from this file After annotation is done the simulator issues a summary of how many instances were not found and possibly a suggestion for a qualifying instance WARNING myasic sdf Failed to find any of the 358 instances from this file WARNING myasic sdf Try instance testbench dut it contains all instance paths from this file The simulator recommends an instance only if the file was applied to the top level and a qualifying instance is found one level d
379. nstance argument that identifies a specific model instance and window name For example top ul wa refers to window wa in model instance top u1 Imcwin read The Imewin read command displays the current value of a window The optional radix argument is binary decimal or hexadecimal these names can be abbreviated The default is to display the value using the std_logic characters For example the following command displays the 64 bit window wc in hexadecimal lmcwin read top ul wc h ModelSim SE User s Manual Logic Modeling SmartModels 14 359 VHDL SmartModel interface Memory arrays Imewin write The Imewin write command writes a value into a window The format of the value argument is the same as used in other simulator commands that take value arguments For example to write 1 to window wb and all 1 s to window we lmcwin write top ul wb 1 lmcwin write top ul wc X FFFFFFFFFFFFFFFEF Imcwin enable The Imcwin enable command enables continuous monitoring of a window The specified window is added to the model instance as a signal with the same name as the window of type std_logic or std_logic_vector This signal can then be referenced in other simulator commands just like any other signal the add list command CR 28 is shown below The window signal is continuously updated to reflect the value in the model For example to list window wa lmcwin enable top ul wa add list top ul wa Imcwin disable
380. nt exceeds natural range severity error for i in x range loop ns n 2 case x i is when 1 H gt n n 1 when 0 L gt null when others gt failure true end Case end loop assert not failure report sulv_to_natural cannot convert indefinite std_ulogic_vector severity error if failure then return 0 else return n end if end sulv_to_natural function natural_to_sulv n bits natural return std_ulogic_vector is variable x std_ulogic_vector bits 1 downto 0 others gt 0 variable tempn natural n E 442 Tips and Techniques ModelSim SE User s Manual Modeling memory in VHDL begin for iin x reverse_range loop if tempn mod 2 1 then ACL ms 117 end if tempn tempn 2 end loop return x end natural_to_sulv end conversions ModelSim SE User s Manual Tips and Techniques E 443 Setting up a List trigger with Expression Builder Setting up a List trigger with Expression Builder This example shows you how to set a List window trigger based on a gating expression created with the ModelSim Expression Builder If you want to look at a set of signal values ONLY during the simulation cycles during which an enable signal rises you would need to use the List window Trigger Gating feature The gating feature suppresses all display lines except those for which a specified gating function evaluates to true Select Prop gt Display Prop
381. ntinuous Comparison you can also use The GUI Expression Builder 8 275 to specify a when expression that must evaluate to true or 1 at the signal edge for the clock to become effective Specify When Expression PO Builder 11 310 Waveform Comparison ModelSim SE User s Manual Graphical Interface to Waveform Comparison Compare by Region Clicking Compare gt Add gt Compare by Region in the Wave window opens the Add Comparison by Region window where you can specify signals to be used in the comparison Add Comparison by Region Region Data Tab e Reference Region Allows you to specify the reference region that will be used in the comparison Test Region Allows you to specify a test region that might have a different name from that of the reference region e Compare Signals of Type Allows you to specify that All Types of signals will be used in the comparison or only Selected Types In Out InOut Internal or Port e Recursive Search Specifies whether to search for signals in the hierarchy below the selected region ModelSim SE User s Manual Waveform Comparison 11 311 Graphical Interface to Waveform Comparison Comparison Method Tab Allows you to select clocked or continuous comparison and provides the capability to specify a When expression Add Comparison by Region 2 cp O l A E 3 OTe e Clocked Comparison Allows you can select a
382. o Deltas Trigger On IV Signals FT Strobe Trigger Gating EE sean Use Expression Builder Expression On Duration es S OK Cancel Apply The Triggers page includes the following options e Deltas Expand Deltas When selected with the Trigger on Signals check box displays a new line for each time step on which items change including deltas within a single unit of time resolution Strobe Period 0 ns First Strobe at fo ns Deltas Collapse Deltas Displays only the final value for each time unit Deltas No Deltas Hides simulation cycle delta column Trigger On Signals Triggers on signal changes Defaults to all signals Individual signals can be excluded from triggering by using the Prop gt Signals Props dialog box or by originally adding them with the notrigger option to the add list command CR 28 ModelSim SE User s Manual ModelSim Graphic Interface 8 179 List window e Trigger On Strobe Triggers on the Strobe Period you specify specify the first strobe with First Strobe at Trigger Gating Expression Enables triggers to be gated on and off by an overriding expression much like a hardware signal analyzer might be set up to start recording data on a specified setup of address bits and clock edges Affects the display of data not the acquisition of the data e Use Expression Builder button Opens the Expression Builder to help you write a gating expression See
383. o not use quotes or braces in the list i e 21 49 or 21 49 This will cause the GUI to hang You can also set tab stops using the PrefSource tabs Tcl preference variable ModelSim SE User s Manual ModelSim Graphic Interface 8 209 Structure window Structure window gt Note In ModelSim versions 5 5 and later the information contained in the Structure window is shown in the structure pages of the Main window Workspace 8 158 The Structure window will not display by default You can display the Structure window at any time by selecting View gt Structure Main window The discussion below applies to both the Structure window and the structure pages in the Workspace The Structure window provides a hierarchical view of the structure of your design An entry is created by each HDL item within the design Your design structure can remain hidden if you wish see Source code security and nodebug E 433 HDL items you can view truct The following HDL items for VHDL s m AmE and Verilog are represented by Eie Edit window hierarchy within Structure window z top toplonly proc VHDL items Ore D m memory indicated by a dark blue square icon component instantiation generate MM Package std_logic_util MM Package vl_types statements block statements and MM Package std_logic_1164 packages I Package standard o cache cache Verilog items Function hash indicated by a lighter blue circle
384. og box to initiate simulation see vsim CR 258 Copy Edit gt Copy see Mouse and keyboard copy the selected text within the shortcuts in the Transcript and El Main window transcript Source windows 8 168 Paste Edit gt Paste see Mouse and keyboard A paste the copied text to the cursor shortcuts in the Transcript and location Source windows 8 168 Restart Run gt Restart restart lt arguments gt reload the design elements and resets the simulation time to see restart CR 170 zero with the option of using current formatting breakpoints and logfile Run Length none run lt specific run length gt 02 specify the run length for the current simulation see run CR 176 8 166 ModelSim Graphic Interface ModelSim SE User s Manual Main window Main window toolbar buttons Button Menu equivalent Command equivalents Run run the current simulation for the specified run length Run gt Run lt default_run_length gt run no arguments see run CR 176 ma Continue Run continue the current simulation run until the end of specified run length or until it hits a breakpoint or specified break event Run gt Continue run continue see run CR 176 Run All run the current simulation forever or until it hits a breakpoint or specified break event Run gt Run All run all see run CR 176 see Assertion settings page 8 266 Break none none stop
385. ommand 10 Each character is processed exactly once by the Tcl interpreter as part of creating the words of a command For example if variable substitution occurs then no further substitutions are performed on the value of the variable the value is inserted into the word verbatim If command substitution occurs then the nested command is processed entirely by the recursive call to the Tcl interpreter no substitutions are performed before making the recursive call and no additional substitutions are performed on the result of the nested script 11 Substitutions do not affect the word boundaries of a command For example during variable substitution the entire value of the variable becomes part of a single word even if the variable s value contains spaces if command syntax The Tcl if command executes scripts conditionally Note that in the syntax below the indicates an optional argument Syntax if expri then bodyl elseif expr2 then body2 elseif else bodyN Description The if command evaluates expr as an expression The value of the expression must be a boolean a numeric value where 0 is false and anything else is true or a string value such as true or yes for true and false or no for false if it is true then body is executed by passing it to the Tcl interpreter Otherwise expr2 is evaluated as an expression and if it is true then body2 is executed and so on If none of the expressions evaluates to true then bo
386. ommands select Help gt Tcl Man Pages Main window or refer to one of the Tcl Tk resources noted above Also see Preference variables located in TCL files B 406 for information on Tcl variables append array break case catch cd close concat continue eof error eval exec expr file flush for foreach format gets glob global history if incr info insert join lappend list llength lindex lrange Ireplace Isearch Isort open pid proc puts pwd read regexp regsub rename return scan seek set split string switch tell time trace source unset uplevel upvar while gt Note ModelSim command names that conflict with Tcl commands have been renamed or have been replaced by Tcl commands See the list below Previous ModelSim Command changed to or replaced by command continue run CR 176 with the continue option format list wave write format CR 277 with either list or wave specified if replaced by the Tcl if command see if command syntax 16 374 for more information list add list CR 28 nolist nowave delete CR 99 with either list or wave specified set replaced by the Tcl set command see set command syntax 16 375 for more information vsource CR 270 add wave CR 37 ModelSim SE User s Manual Tcl and ModelSim 16 371 Tcl commands Tcl command syntax The former ModelSim commands if and set are now Tcl commands You
387. omparison Adding Signals Regions and or Etocks Setting Compare Options Wave window display Printing compare differences List window display Command line interface to Waveform Comparison Preference Variables Compare commands 11 302 11 303 11 303 11 305 11 305 11 307 11 314 11 316 11 321 11 322 11 323 11 323 11 323 ModelSim SE User s Manual Waveform Comparison 11 301 Introducing Waveform Comparison Introducing Waveform Comparison The ModelSim Waveform Comparison feature allows you to compare the current live simulation against a reference wave logfile or dataset wlf file compare two saved datasets or compare different parts of the current live simulation You can view the results of these comparisons in the Wave and List windows and generate a text file of the results in the Main window With the Waveform Comparison feature you can e specify the signals or regions to be compared e define tolerances for timing differences e set a start time and end time for the comparison e limit the comparison to a specific number of timing differences and e step through a succession of timing differences via buttons in the Wave window By default Waveform Comparison computes the timing differences between test signals and reference signals from time zero to the end of the shortest dataset or to the end of the current live simulation But you can also specify an optional sta
388. on no_notifier This option disables the toggling of the notifier register argument of the timing check system tasks By default the notifier is toggled when there is a timing check violation and the notifier usually causes a UDP to propagate an X Therefore the no_notifier option suppresses X propagation on timing violations no_path_edge This option causes ModelSim to ignore the input edge specified in a path delay The result 1s that all edges on the input are considered when selecting the output delay Verilog XL always ignores the input edges on path delays no_pulse_msg This option disables the warning message for specify path pulse errors A path pulse error occurs when a pulse propagated through a path delay falls between the pulse rejection limit and pulse error limit set with the pulse_r and pulse_e options A path pulse error results in a warning message and the pulse is propagated as an X The no_pulse_msg option disables the warning message but the X is still propagated no_tchk_msg This option disables error messages issued by timing check system tasks when timing check violations occur However notifier registers are still toggled and may result in the propagation of X s for timing check violations t nosdfwarn This option disables warning messages during SDF annotation notimingchecks This option completely disables all timing check system tasks nowarn lt mnemonic gt This option disables the class of war
389. on information as described above in Registering PLI applications To prepare the application for ModelSim Verilog you must compile the veriuser c file and link it to the object files to create a dynamically loadable object see Compiling and linking PLI VPI applications 5 111 For example if you have a veriuser c file and a library archive libapp a file that contains the application s object files then the following commands should be used to create a dynamically loadable object for the Solaris operating system cc c I lt install_dir gt modeltech include veriuser c ld G o app sl veriuser o libapp a That s all there is to it The PLI application is ready to be run with ModelSim Verilog All that s left is to specify the resulting object file to the simulator for loading using the Veriuser modesim ini file entry the pli simulator option or the PLIOBJS environment variable see Registering PLI applications 5 108 B Note On the HP700 platform the object files must be compiled as position independent code by using the z compiler option Since the object files supplied for Verilog XL may be compiled for static linking you may not be able to use the object files to create a dynamically loadable object for ModelSim Verilog In this case you must get the third party application vendor to supply the object files compiled as position independent code 5 120 Verilog Simulation ModelSim SE User s Manual Using the Ve
390. on integer or real string string literal When a scalar type receives a real value the real is converted to an integer by truncating the decimal portion Type time is treated specially the Verilog number is converted to a time value according to the timescale directive of the module Physical and enumeration types receive a value that corresponds to the position number indicated by the Verilog number In VHDL this is equivalent to TVAL P where T is the type VAL is the predefined function attribute that returns a value given a position number and P is the position number 6 128 Mixed VHDL and Verilog Designs ModelSim SE User s Manual Mapping data types Verilog parameters VHDL type Verilog type integer integer real real string string The type of a Verilog parameter is determined by its initial value VHDL and Verilog ports The allowed VHDL types for ports connected to Verilog nets and for signals connected to Verilog ports are Allowed VHDL types bit bit_vector std_logic std_logic_vector vl_logic vl_logic_vector The vl_logic type is an enumeration that defines the full state set for Verilog nets including ambiguous strengths The bit and std_logic types are convenient for most applications but the vl_logic type is provided in case you need access to the full Verilog state set For example you may wish to convert between vl_logic and your
391. on of cellA compiled into libA is different from that compiled into libB In this case it is insufficient to just specify L libA L libB as the search libraries because instantiations of cellA from modB resolve to the libA version of cellA The appropriate search library options are L work L libA L libB 5 78 Verilog Simulation ModelSim SE User s Manual Compilation Verilog XL compatible compiler options See vlog CR 250 for a complete list of compiler options The options described here are equivalent to Verilog XL options Many of these are provided to ease the porting of a design to ModelSim Verilog define lt macro_name gt lt macro_text gt This option allows you to define a macro from the command line that is equivalent to the following compiler directive define lt macro_name gt lt macro_text gt Multiple define options are allowed on the command line A command line macro overrides a macro of the same name defined with the define compiler directive incdir lt directory gt This option specifies which directories to search for files included with include compiler directives By default the current directory is searched first and then the directories specified by the incdir options in the order they appear on the command line You may specify multiple inedir options as well as multiple directories separated by in a single inedir option delay_mode_distributed This o
392. ondary name for unoptimized code is verilog You may specify an alternate name other than fast for optimized code using the fast lt option gt For example to assign the secondary name optl to your optimized code you would enter the following vlog fast opt1 cpu_rtl v If you have multiple designs that use common modules compiled into the same library then you need to assign a different secondary name for each design so that the optimized code for a module used in one design context is not overwritten with the optimized code for the same module used in another context This is true even if the designs are small variations of each other such as different testbenches For example suppose you have two testbenches that instantiate and test the same design You might assign different secondary names as follows vlog fast t1 testbenchl v design v Compiling module testbenchl Compiling module design Top level modules testbenchl Analyzing design Optimizing 2 modules of which 0 are inlined Optimizing module design t1 Optimizing module testbenchl t1 vlog fast t2 testbed2 v design v Compiling module testbench2 Compiling module design Top level modules testbench2 5 92 Verilog Simulation ModelSim SE User s Manual Compiling for faster performance Analyzing design Optimizing 2 modules of which 0 are inlined Optimizing module design t2 Optimizing module test
393. onds lus 10us or 100us microseconds lms 10ms or 100ms milliseconds lsec 10sec or 100sec seconds See also Selecting the time resolution 4 58 8 258 ModelSim Graphic Interface ModelSim SE User s Manual Simulating with the graphic interface VHDL settings page Load Design Name Vale Override instance The VHDL page includes these options Generics The Add button opens a dialog box shown below that allows you to specify the value of generics within the current simulation generics are then added to the Generics list You can also select a generic on the listing to Delete or Edit ModelSim SE User s Manual ModelSim Graphic Interface 8 259 From the Specify a Generic dialog box you can sw Specify a Generic OF x set the following options A Generic Name tph_hi e Generic Name g lt Name gt lt Value gt Yale The name of the generic parameter Type it in as it appears in the VHDL source case is ignored Value OK Cancel Specifies a value for all generics in the design with the given name above that have not received explicit values in generic maps such as top level generics and generics that would otherwise receive their default value The value must be appropriate for the declared data type of the generic parameter No spaces are allowed in the specification except within quotes when specifying a string value Overri
394. ons gt Simulation or use the Run Length text box on the toolbar Run All run simulation until you stop it see also the run command CR 176 Continue continue the simulation see also the run command CR 176 and the continue option Run Next run to the next event time Step single step the simulator see also the step command CR 187 Step Over execute without single stepping through a subprogram call Restart reload the design elements and reset the simulation time to zero only design elements that have changed are reloaded you specify whether to maintain the following after restart list and wave window environment breakpoints logged signals and virtual definitions see also the restart command CR 170 Compare menu Start Comparison start a new comparison Comparison Wizard receive step by step assistance while creating a waveform comparison Run Comparison compute differences from time zero until the end of the simulation End Comparison stop difference computation and close the currently open comparison Add provides three options Compare by Signal specify signals for comparison Compare by Region designate a reference region for a comparison Clocks define clocks to be used in a comparison Options set options for waveform comparisons Differences provides four options Clear clear all differences from the Wave window Show displ
395. ons you make in the coverage_source window will show up in the Excluded tab of The coverage_summary window 10 292 ModelSim SE User s Manual Code Coverage 10 297 Merging coverage report files Merging coverage report files You can merge the results from two or more analyses Select File gt Open gt Coverage gt Merge Coverage from the coverage_summary window Merge Coverage Reports Coverage File Name To Read From Browse Rules To Use During Merge Clear out accumulated coverage data IV Keep coverage data for files not in the current design The Merge Coverage Reports dialog has the following options e Coverage File Name to Read From Specify one or more saved coverage reports that you want to merge into the current analysis Clear out accumulated coverage data When checked clears coverage statistics from the current analysis before merging in saved coverage reports Keep coverage data for files not in the current design When checked includes coverage data from all files you are merging in even if they are not part of the current design If you then select one of those included files in the coverage_source window it will pop up an Open Source dialog so you can point to the location of the file 10 298 Code Coverage ModelSim SE User s Manual Exclusion filter files Exclusion filter files Exclusion filter files specify files and line numbers that you wish to exclude from
396. op Window Add Marker Delete Marker top paddr y top pdata top saddr y Ho top stw top sstb y ftop stdy y DOOO0O0OO000001 00000001 O000000000000001 00000001 ZZZzzz D000000000000001 00000001 O00000 00000001 od00000000000001 00000001 000000 oo00o000000000001 00000001 000000 00000001 O00000 00000001 od00000000000001 O 00000001 O00000t 00000001 O000000000000001 0 00000001 O00000t ee E Default dataset sim Choose a specific marked line to view by selecting Markers gt Goto The marker name on the Goto list corresponds to the simulation time of the selected line ModelSim SE User s Manual ModelSim Graphic Interface 8 187 List window List window keyboard shortcuts Using the following keys when the mouse cursor is within the List window will cause the indicated actions Key Action lt arrow up gt scroll listing up selects and highlights the line above the currently selected line lt arrow down gt scroll listing down selects and highlights the line below the currently selected line lt arrow left gt scroll listing left lt arrow right gt scroll listing right lt page up gt scroll listing up by page lt page down gt scroll listing down by page lt tab gt searches forward down to the next transition on the selected signal lt shift tab gt searches backward up to the prev
397. operties for all items in the window delta settings trigger on selection strobe period label size and dataset prefix Signal Props set label radix trigger on off and field width for the selected item Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 ModelSim SE User s Manual ModelSim Graphic Interface 8 177 List window Setting List window display properties Before you add items to the List window you can set the window s display properties To change when and how a signal is displayed in the List window select Prop gt Display Props List window The resulting Modify Display Properties dialog box contains optio
398. options Postscript File specify the name of the file to save default is dataflow ps Orientation specify Landscape horizontal or Portrait vertical orientation Color Mode specify Color 256 colors Gray gray scale or Mono monochrome color mode Postscript specify Normal Postscript or EPS Encapsulated Postscript file type Color Map Dataflow Save Postscript Write Postscript Postscript File dataflow ps Browse Color Mode Drientation Color Landscape Postscript Normal Portrait EPS Color Map white 10 0 0 0 0 0 setrabcolor OK Cancel specify the color mapping from current Dataflow window colors to Postscript colors 8 174 ModelSim Graphic Interface ModelSim SE User s Manual List window List window The List window displays the results of your simulation run in tabular format The window is divided into two adjustable panes which allow you to scroll horizontally through the listing on the right while keeping time and delta visible on the left FS list Torx File Edit Markers Prop Window nsy top ck y top paddr top pdata top saddr y aE delta top prw top stw top pstb y top sstb y top prdy top stdy y 500 0 1 0 1 1 00000010 0000000000000010 0 0 1 00000010 zzzzz 505 0 1 0 1 1 00000010 0000000000000010 0 1 1 00000010 00000 520 0 0 0 1 1 00000010 0000000000000010 0 1 1 00000010 00000 540 0 1 0 1
399. options e Library Select the library you wish to view from the drop down list Related command line command is vdir CR 223 3 44 Design libraries ModelSim SE User s Manual Working with design libraries e DesignUnit Description list Select a plus box to view the associated architecture or select a minus box to hide the architecture The Library page also has two context menus that you access with your right mouse button Windows 2nd button UNIX 3rd button One menu is accessed by right clicking a design unit name the second is accessed by right clicking a blank area in the Designs page The graphic below shows the two menus ModelSim OL ES File Edit Design View Project Run Compare Macro Options Window Help Loading package gates Compiling architecture structural of adder Loading entity adder Loading entity xorg Loading entity andg Loading entity org Compiling entity addern Compiling architecture structural of addern Loading entity adder Compiling architecture behavioral of addern Loading entity addern ModelSim gt wm title ModelSim E Load Ls Load Edit Refresh Cieate Library a E View Update El Recompile E HHHHHHHHHHH test_counter ModelSim gt e Project test lt No Design Loaded gt lt No Context gt 4 The context menu at the left includes the following commands Load Simulates the select
400. or INTERCONNECT constructs that terminate at the same port are handled By default the Module Input Port Delay MIPD is set to the max value encountered in the SDF file Alternatively you can choose the min or latest of the values 8 264 ModelSim Graphic Interface ModelSim SE User s Manual Simulating with the graphic interface Setting default simulation options Select Options gt Simulation Main window to bring up the Simulation Options dialog box shown below Options you can set for the current simulation include default radix default force type default run length iteration limit warning suppression break on assertion specifications and WLF file configuration OK accepts the changes made and closes the dialog box Apply makes the changes with the dialog box open so you can test your settings Cancel closes the dialog box and makes no changes The options found on each page are detailed below gt Note Changes made in the Simulation Options dialog box are the default for the current simulation only Options can be saved as the default for future simulations by editing the simulator control variables in the modelsim ini file the variables to edit are noted in the text below You can use Notepad see notepad command CR 141 to edit the variables in modelsim ini if you wish See also Projects and system initialization 2 25 for more information Default settings page M Simulation Options ioj ES Default Radix Sup
401. or of the explicit function declaration not the one automatically created by the compiler for each type declaration IgnoreVitalErrors 0 1 if 1 ignores VITAL compliance checking errors off 0 NoCaseStaticError 0 1 if 1 changes case statement static errors to warnings off 0 NoDebug 0 1 if 1 turns off inclusion of debugging info within off 0 design units NoOthersStaticError 0 1 if 1 disables errors caused by aggregates that are off 0 not locally static NoVital 0 1 1f 1 turns off acceleration of the VITAL packages off 0 NoVitalCheck 0 1 1f 1 turns off VITAL compliance checking off 0 Optimize_1164 0 1 if 0 turns off optimization for IEEE std_logic_1164 on 1 package Quiet 0 1 if 1 turns off loading messages off 0 RequireConfigForAllDefault 0 1 1f 1 instructs the compiler not to generate a default off 0 Binding binding during compilation ScalarOpts 0 1 if 1 activates optimizations on expressions that off 0 don t involve signals waits or function procedure task invocations Show_source 0 1 if 1 shows source line containing error off 0 Show_VitalChecks Warnings 0 1 1f O turns off VITAL compliance check warnings on 1 Show_Warningl 0 1 if O turns off unbound component warnings on 1 Show_Warning2 0 1 if 0 turns off process without a wait statement on 1 warnings Show_Warning3 0 1 if 0 turns off null range warnings on 1 Show_Warning4 0 1 if 0 turns off no space in time literal warnings on 1 Show
402. or resolved signals This is designed to provide compatibility with version 4 1 and earlier force files But if you prefer freeze as the default for both resolved and unresolved signals you can change the defaults in the modelsim ini file vsim Default Force Kind The choices are freeze drive or deposit DefaultForceKind freeze B 404 ModelSim Variables ModelSim SE User s Manual Preference variables located in INI files Restart command defaults The restart command has force nobreakpoint nolist nolog and nowave options You can set any of these as defaults by entering the following line in the modelsim ini file DefaultRestartOptions lt options gt where lt opt ions gt can be one or more of force nobreakpoint nolist nolog and nowave Example DefaultRestartOptions nolog force Note You can also set these defaults in the modelsim tcl file The Tcl file settings will override the ini file settings VHDL93 You can make the VHDL93 standard the default by including the following line in the INT file vcom Turn on VHDL 1993 as the default Default is off VHDL 1987 VHDL93 1 Opening VHDL files You can delay the opening of VHDL files with an entry in the NI file if you wish Normally VHDL files are opened when the file declaration is elaborated If the DelayFileOpen option is enabled then the file is not opened until the first read or write to that file vsim DelayFileOp
403. ork On successful loading of the design the simulation time is set to zero and you must enter a run command to begin simulation Commonly you enter run all to run until there are no more simulation events or until finish is executed in the Verilog code You can also run for specific time periods e g run 100 ns Enter the quit command to exit the simulator Simulation resolution limit The simulator internally represents time as a 64 bit integer in units equivalent to the smallest unit of simulation time also known as the simulation resolution limit The resolution limit defaults to the smallest time precision found among all of the timescale compiler directives in the design The time precision is the second number in the timescale directive For example 10 ps in the following directive timescale 1 ns 10 ps The time precision should not be unnecessarily small because it will limit the maximum simulation time limit and it will degrade performance in some cases If the design contains no timescale directives then the resolution limit defaults to the resolution value specified in the modelsim ini file default is 1 ns In any case you can override the default resolution limit by specifying the t option on the command line For example to explicitly choose 100 ps resolution vsim t 100ps top 5 84 Verilog Simulation ModelSim SE User s Manual Simulation This forces 100 ps resolution even if the
404. ormation on the individual variables Performance Analyzer commands The table below provides a brief description of the profile commands follow the links for complete command syntax See the ModelSim Command Reference for complete command details Command Description profile clear CR 153 clears any data that has been gathered during previous run commands after this command is executed all profiling data will be reset profile interval CR 154 selects the frequency with which the profiler collects samples during a run command profile off CR 155 disables runtime profiling profile on CR 156 enables runtime analysis of where your simulation is spending its time profile option CR 157 changes various profiling options profile report CR 158 produces a textual output of the profiling statistics that have been gathered up to this point 9 290 Performance Analyzer ModelSim SE User s Manual 10 Code Coverage Chapter contents Enabling Code Coverage 2 wwe 10 292 The coverage_source window 10 296 Excluding lines and files 2 2 2 2 10 296 The coverage_summary window 10 292 Summary information 10 293 Misses tab 2 2 a eee 10 293 Exclusions tab 2 2 wee 10 293 The coverage_summary window menu bar 10 294 Merging coverage report files 10 298 Excl
405. ose definition is stored in a special location and is not visible in the Signals window or to the normal virtual commands All other virtual signals are considered explicit virtuals Virtual functions Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel They consist of logical operations on logged signals and can be dependent on simulation time They can be displayed in the Signals Wave and List windows and accessed by the examine command CR 115 but cannot be set by the force command CR 121 Examples of virtual functions include the following e a function defined as the inverse of a given signal e a function defined as the exclusive OR of two signals e a function defined as a repetitive clock e a function defined as the rising edge of CLK delayed by 1 34 ns Virtual functions can also be used to convert signal types and map signal values The result type of a virtual signal can be any of the types supported in the GUI expression syntax integer real boolean std_logic std_logic_vector and arrays and records of these types Verilog types are converted to VHDL 9 state std_logic equivalents and Verilog net strengths are ignored ModelSim SE User s Manual Datasets saved simulations and virtuals 7 145 Virtual Objects User defined buses and more Virtual functions can be created using the virtual function command CR 233 Virtual fun
406. ou are simulating Follow these steps 1 Add the items you want in the Wave window with any method shown above 2 Edit and format the items see Editing and formatting HDL items in the Wave window 8 230 to create the view you want 3 Save the format to a file by selecting File gt Save Format Wave window To use the format file start with a blank Wave window and run the DO file in one of two ways e Invoke the do command CR 104 from the command line do lt my_wave_format gt Select File gt Load Format Wave window Use Edit gt Select All and Edit gt Delete to remove the items from the current Wave window use the delete command CR 99 with the wave option or create a new blank Wave window with View gt New gt Wave Main window gt Note Wave window format files are design specific use them only with the design you were simulating when they were created ModelSim SE User s Manual ModelSim Graphic Interface 8 219 Wave window The Wave window menu bar wave default Al x File Edit Cursor Zoom Compare Bookmark Format Window she 328 RK tA QQQQ EF EEE fale sin The following menu commands and button options are available from the Wave window menu bar If you see a dotted line at the top of a drop down menu you can select it to create a separate menu window Many of these commands are also available via a context menu by clicking your right mouse button within the wave windo
407. ow menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 8 192 ModelSim Graphic Interface ModelSim SE User s Manual Signals window Signals window The Signals window is divided into two window panes The left pane shows the names of HDL items in the current region which is selected in the Structure window The right pane shows the values of the associated HDL items at the end of the current run The data in this pane is similar to that shown in the Wave window 8 216 except that the values do not change dynamically with movement of the selected Wave window cursor You can double click a signal and it will highlight that signal in the Source win
408. own Also see Resolving errors 12 329 for specific VHDL VITAL SDF troubleshooting 12 338 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual Obtaining the SDF specification Obtaining the SDF specification The SDF specification is available from Open Verilog International Lynn Horobin phone 408 358 95 10 fax 408 358 3910 email info ovi org home page http www ovi org ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 339 12 340 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual 13 Value Change Dump VCD Files Chapter contents ModelSim VCD commands and VCD tasks 13 342 Resimulating a VHDL design from a VCD file 13 344 Extracting the proper stimulus for bidirectional ports 13 344 Specifying a filename and state mappings 13 344 Creating the VCD file gt lt so s wo 1 13 344 A VCD file from source to output a 13 346 VHDL source code aa a a 13 346 VCD simulator commands 13 346 VCD output 2k ka ee e w 13 347 Capturing portdriverdata 1 13 349 Supported TSSI states 2 2 2 2 ee 13 349 Strength values 2 2 we 13 350 Port identifier code 2 1 13 350 Example VCD output from ved dumpports 13 351 This chapter explains Model Technology s Verilog VCD i
409. own user defined type The vl_logic type is defined in the vl_types package in the pre compiled verilog library This library is provided in the installation directory along with the other pre compiled libraries std and ieee The source code for the vl_types package can be found in the files installed with ModelSim See nodeltech vhdl_src verilog vitypes vhd ModelSim SE User s Manual Mixed VHDL and Verilog Designs 6 129 Mapping data types Verilog states Verilog states are mapped to std_logic and bit as follows Verilog std_logic HiZ Sm0 Sml SmX For Verilog states with ambiguous strength bit receives 0 strong strength strength std_logic receives X if either the 0 or 1 strength component is greater than or equal to std_logic receives W if both the 0 and 1 strength components are less than strong 6 130 Mixed VHDL and Verilog Designs ModelSim SE User s Manual Mapping data types VHDL type bit is mapped to Verilog states as follows Verilog Sto Stl VHDL type std_logic is mapped to Verilog states as follows std_logic Verilog StX StX St0 Stl HiZ Pux Pu0 Pul StX ModelSim SE User s Manual Mixed VHDL and Verilog Designs 6 131 VHDL instantiation of Verilog design units VHDL instantiation of Verilog design units
410. path delays Note that this option affects path delays only and not primitives Primitives always operate in inertial delay mode typdelays This option selects the typical value in min typ max expressions This is the default This option has no effect 1f the min typ max selection was determined at compile time ModelSim SE User s Manual Verilog Simulation 5 89 Compiling for faster performance Compiling for faster performance This section describes how to use the fast compiler option to analyze and optimize an entire design for improved simulation performance This option improves performance for RTL behavioral and gate level designs See below for important information specific to gate level designs ModelSim s default mode of compilation defers module instantiations parameter propagation and hierarchical reference resolution until the time that a design is loaded by the simulator see Incremental compilation 5 76 This has the advantage that a design does not have to be compiled all at once allowing independent compilation of modules without requiring knowledge of the context in which they are used Compiling modules independently provides flexibility to the user but results in less efficient simulation performance in many cases For example the compiler must generate code for a module containing parameters as though the parameters are variables that will receive their final values when the design is loaded by
411. patible routines 5 125 64 bit support in the PLI 5 125 PLIVPI tracing s eo oao a e 5 125 This chapter describes how to compile and simulate Verilog designs with ModelSim Verilog ModelSim Verilog implements the Verilog language as defined by the IEEE Std 1364 and it is recommended that you obtain this specification as a reference manual ModelSim SE User s Manual Verilog Simulation 5 73 In addition to the functionality described in the IEEE Std 1364 ModelSim Verilog includes the following features e Standard Delay Format SDF annotator compatible with many ASIC and FPGA vendor s Verilog libraries Value Change Dump VCD file extensions for ASIC vendor test tools Dynamic loading of PLI VPI applications Compilation into retargetable executable code Incremental design compilation Extensive support for mixing VHDL and Verilog in the same design including SDF annotation Graphic Interface that is common with ModelSim VHDL Extensions to provide compatibility with Verilog XL The following IEEE Std 1364 functionality is partially implemented in ModelSim Verilog e Verilog Procedural Interface VPI see lt install_dir gt modeltech docs technotes Verilog_VPI note for details Many of the examples in this chapter are shown from the command line For compiling and simulating within a project or ModelSim s GUI see e Getting started with projects 2 28 e Compili
412. pe 3 42 working type 3 42 Design units 3 42 viewing hierarchy 8 155 Directories moving libraries 3 49 See also Libraries ModelSim SE User s Manual Index 470 DO files macros error handling E 431 passing parameters to E 430 Tcl source command E 432 documentation 1 21 DOPATH environment variable B 393 dumpports tasks VCD files 13 343 E Editing in notepad windows 8 168 C 413 in the Main window 8 168 C 413 in the Source window 8 168 C 413 EDITOR environment variable B 393 Email Model Technology s email address 1 23 end comparison 11 319 ENDFILE function 4 63 ENDLINE function 4 63 entity simulator state variable B 408 Environment variables B 393 accessed during startup 2 38 for locating license file D 418 location of modelsim ini file B 407 referencing from ModelSim command line B 395 referencing with VHDL FILE variable B 395 setting before compiling or simulating B 393 setting in Windows B 394 specify transcript file location with TranscriptFile B 400 specifying library locations in modelsim ini file B 396 used in Solaris linking for FLI and PLI VPI 5 112 using with location mapping E 437 variable substitution using Tcl 16 377 Errors during compilation locating 8 251 Event order issues 5 85 excluding lines and files from Code Coverage 10 293 10 296 exclusion filter 10 293 Explicit ini file variable B 397 Expression Builder 11 312 specify when expression 11 310 11 312 11 313 Expression Buil
413. pecified text string within the Signals window choose the Name or Value field to search and the search direction down or up see also the search command CR 178 8 194 ModelSim Graphic Interface ModelSim SE User s Manual Signals window View menu Wave List Log place the Selected Signals Signals in Region or Signals in Design in the Wave window 8 216 List window 8 175 or logfile Filter choose the port and signal types to view Input Ports Output Ports InOut Ports and Internal Signals in the Signals window Window menu Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 Selecting HDL item types to view The View gt Filter menu selection allows
414. pecify signals to be used in the comparison You can also set signal options by clicking the Options button which opens the Add Signal Options dialog box Start Comparison Comparison Wizard Aun Comparison End Comparison Options Differences gt Rules Reload structure_browser min tst_pseudo tst_pseudo Register clock Register reset Register expected Register storage Net data Options Net expected_w chip pseudo QQA Hi HR Compare by Signal Compare by Region Clocks OK Cancel ModelSim SE User s Manual Waveform Comparison 11 307 Graphical Interface to Waveform Comparison Add Signal Options The Add Signal Options dialog allows you to select the Waveform Comparison method to be used Clocked Strobed or Continuous and to specify a when expression that must evaluate to true or 1 at the signal edge for the clock to become effective A when expression can be built using The GUI Expression Builder 8 275 which is accessed by clicking the Builder button Add Signal Options pp hock Bl cance Clocked Comparison If the Clocked Comparison method is chosen you can select a clock from the drop down history of past clock selections or click the Clocks button to add a new clock Comparison Clocks Clicking the Clocks button opens the Comparison Clocks dialog box where you can add
415. plete details see Chapter 10 Code Coverage To acquire code coverage statistics the coverage switch must be specified during the command line invocation of the simulator vsim coverage This will allow you to use the various code coverage commands coverage clear CR 92 coverage reload CR 93 and coverage report CR 94 ModelSim SE User s Manual VHDL Simulation 4 59 Using the TextlO package Using the TextlO package To access the routines in TextIO include the following statement in your VHDL source code USE std textio all A simple example using the package TextIO is USE std textio all ENTITY simple_textio IS END ARCHITECTURE simple_behavior OF simple _textio IS BEGIN PROCESS VARIABLE i INTEGER 42 VARIABLE LLL LINE BEGIN WRITE LLL i WRITELINE OUTPUT LLL WAIT END PROCESS END simple _behavior Syntax for file declaration The VHDL 87 syntax for a file declaration is file identifier subtype_indication iS mode file logical_name where file_logical_name must be a string expression The VHDL 93 syntax for a file declaration is file identifier_list subtype_indication file_open_information You can specify a full or relative path as the file_logical_name for example VHDL 87 file filename TEXT iS in usr rick myfile Normally if a file is declared within an architecture process or package the file is opened when you start the simulator and is
416. press Warnings Symbolic I From Synopsys Packages Binary FT From IEEE Numeric Std Packages Octal Decimal Default Run fo B Unsigned Hexadecimal Iteration Limit ASCII fiooo Default Force Type Freeze C Drive C Deposit OK Cancel Apply The Defaults page includes these options Default Radix Sets the default radix for the current simulation run You can also use the radix CR 166 command to set the same temporary default A permanent default can be set by editing the DefaultRadix B 399 variable in the modelsim ini file The chosen radix is used for all commands force CR 121 examine CR 115 change CR 52 are examples and for displayed values in the Signals Variables Dataflow List and Wave windows ModelSim SE User s Manual ModelSim Graphic Interface 8 265 Simulating with the graphic interface Suppress Warnings Selecting From Synopsys Packages suppresses warnings generated within the accelerated Synopsys std_arith packages Edit the StdArithNoWarnings B 400 variable in the modelsim ini file to set a permanent default Selecting From IEEE Numeric Std Packages suppresses warnings generated within the accelerated numeric_std and numeric_bit packages Edit the NumericStdNoWarnings B 400 variable in the modelsim ini file to set a permanent default Default Run Sets the default run length for the current simulation Edit the RunLength B 400 variable in the modelsim
417. ps a particular element by using the Tcl continue command set bo foreach i a if i ZZZ continue set b linsert b 0 i The last example is of the Tcl switch command switch x a incr tl b incr t2 ENLACE EAS Example 2 This next example shows a complete Tcl script that restores multiple Wave windows to their state in a previous simulation including signals listed geometry and screen position It also adds buttons to the Main window toolbar to ease management of the wave files This example works in ModelSim SE only dt id dt de dt dt dt dt de de dt tH tH H tH dt id dt This file contains procedures to manage multiple wave files Source this file from the command line or as a startup script source lt path gt wave_mgr tcl add_wave_buttons Add wave management buttons to the main toolbar new save and load new_wave Dialog box creates a new wave window with the user provided name named_wave lt name gt Creates a new wave window with the specified title save_wave lt file root gt Saves name window location and contents for all open wave windows Creates lt file root gt lt n gt do file for each window where lt n gt is 1 to the number of windows Default file root is wave Also creates windowSet do file that contains title and geometry info load_wave lt file root gt Opens and loads wave windows for all files matching lt file root gt lt n gt do where l
418. ption disables path delays in favor of distributed delays See Delay modes 5 97 for details delay_mode_path This option sets distributed delays to zero in favor of path delays See Delay modes 5 97 for details delay_mode_unit This option sets path delays to zero and non zero distributed delays to one time unit See Delay modes 5 97 for details delay_mode_zero This option sets path delays and distributed delays to zero See Delay modes 5 97 for details f lt filename gt This option reads more command line arguments from the specified text file Nesting of f options is allowed mindelays This option selects minimum delays from the min typ max expressions If preferred you can defer delay selection until simulation time by specifying the same option to the simulator typdelays This option selects typical delays from the min typ max expressions If preferred you can defer delay selection until simulation time by specifying the same option to the simulator maxdelays This option selects maximum delays from the min typ max expressions If preferred you can defer delay selection until simulation time by specifying the same option to the simulator ModelSim SE User s Manual Verilog Simulation 5 79 Compilation nowarn lt mnemonic gt This option disables the class of warning messages specified by lt mnemonic gt This option only disables warning messages accompanied by a mnemonic enclosed in squar
419. r if you specify a logical name that does not resolve to an existing directory 3 48 Design libraries ModelSim SE User s Manual Working with design libraries See also See ModelSim Commands CR 9 for more information about the library management commands ModelSim Graphic Interface 8 149 for more information about the graphical user interface and Projects and system initialization 2 25 for more information about the modelsim ini file Moving a library Individual design units in a design library cannot be moved An entire design library can be moved however by using standard operating system commands for moving a directory ModelSim SE User s Manual Design libraries 3 49 Specifying the resource libraries Specifying the resource libraries VHDL resource libraries Within a VHDL source file you can use the VHDL library clause to specify logical names of one or more resource libraries to be referenced in the subsequent design unit The scope of a library clause includes the text region that starts immediately after the library clause and extends to the end of the declarative region of the associated design unit Jt does not extend to the next design unit in the file Note that the library clause is not used to specify the working library into which the design unit is placed after compilation the vcom command CR 217 adds compiled design units to the current working library By default this is the lib
420. r s Manual ModelSim Graphic Interface 8 237 Wave window The Wave Signal Search dialog box includes these options You can locate values for the Signal Name s shown at the top of the dialog box The search is based on these options e Search Type Any Transition Searches for any transition in the selected signal s e Search Type Rising Edge Searches for rising edges in the selected signal s e Search Type Falling Edge Searches for falling edges in the selected signal s e Search Type Search for Signal Value Searches for the value specified in the Value field the value should be formatted using VHDL or Verilog numbering conventions see Numbering conventions CR 291 B Note If your signal values are displayed in binary radix see Searching for binary signal values in the GUI CR 300 for details on how signal values are mapped between a binary radix and std_logic Search Type Search for Expression Searches for the expression specified in the Expression field evaluating to a boolean true Activates the Builder button so you can use The GUI Expression Builder 8 275 if desired The expression can involve more than one signal but is limited to signals logged in the Wave window Expressions can include constants variables and DO files If no expression is specified the search will give an error See Expression syntax CR 302 for more information Search Options Match Count You can search for the n th trans
421. r the vsim command for more information on the relevant command line switches Per VHDL VITAL 95 there is no convenient way to handle interconnect delays from multiple outputs to a single input Interconnect delay is modeled in the receiving device as a single delay from an input port to an internal node The node is explicitly declared The default is to use the value of the maximum encountered delay in the SDF file Alternatively you can choose the minimum or latest value of the multiple delays with the vsim command CR 258 multisource_delay option multisource_delay min max latest Timing checks are performed on the interconnect delayed versions of input ports This may result in misleading timing constraint violations because the ports may satisfy the constraint while the delayed versions may not If the simulator seems to report incorrect violations be sure to account for the effect of interconnect delays 12 336 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual Troubleshooting Troubleshooting Specifying the wrong instance By far the most common mistake in SDF annotation is to specify the wrong instance to the simulator s SDF options The most common case is to leave off the instance altogether which is the same as selecting the top level design unit This is generally wrong because the instance paths in the SDF are relative to the ASIC or FPGA model which is usually instantiated under a top
422. rage tst_pseudo expected tst_pseudo data tst_pseudo clocked_data tst_pseudo clocked_delay4_data tst_pseudo tol_typ_exp_data tst_pseudo tol_min_exp_data tst_pseudo clocked_typ_exp_data tst_pseudo clocked_min_exp_data Timing differences are also indicated by red bars in the vertical and horizontal scroll bars of the waveform display and by red difference markers on the waveforms themselves Rectangular difference markers denote continuous differences Diamond difference markers denote clocked differences Placing your mouse cursor over any difference marker will initiate a popup display that provides timing details for that difference as ms as lt as ms difference markers Pathnames Values Waveform display Compare Data tst_pseudo clock match tst_pseudo reset match tst_pseudo storage match tst_pseudo expected match tst_pseudo data El tst_pseudo clocked_data mate tst_pseudo clocked_delay4_data matel Y compare tst_pseudo data 991647 ps tst_pseudo tol_typ_exp_data match Diff number 47 From time 980939 ps delta 1 to time 994078 ps delta 1 A e Suen ee tst_pseudo clocked_typ_exp_data tst_pseudo clocked_min_exp_data matc n The diff designation in the Values column relates to the ie difference details position of the selected cursor The values column of the Wave window displays the words match or diff for every test signal depending o
423. rary Type list To view the contents of a library Select the library then click the View button This brings up the Library page 3 44 in the Main window From there you can also delete design units from the library To create a new library mapping Click the Add button This brings up Create a New Library 3 43 dialog box that allows you to enter a new logical library name and the pathname to which it is to be mapped It is possible to enter the name of a non existent directory but the specified directory must exist as a ModelSim library before you can compile design units into it ModelSim will issue a warning message if you try to map to a non existent directory ModelSim SE User s Manual Design libraries 3 47 Working with design libraries To edit an existing library mapping Select the desired mapping entry then click the Edit button This brings up a dialog box that allows you to modify the logical library name and the pathname to which it is mapped Selecting Delete removes an existing library mapping but it does not delete the library The library can be deleted with this vdel command CR 222 vdel lib lt library_name gt all Library mapping from the command line You can issue a command to set the mapping between a logical library name and a directory its form is vmap lt logical_name gt lt directory_pathname gt This command may be invoked from either a UNIX DOS prompt or from the command line within Mod
424. rary named work To change the current working library you can use vcom work and specify the name of the desired target library Predefined libraries Certain resource libraries are predefined in standard VHDL The library named std contains the packages standard and textio which should not be modified The contents of these packages and other aspects of the predefined language environment are documented in the IEEE Standard VHDL Language Reference Manual Std 1076 1987 and ANSIIEEE Std 1076 1993 See also Using the TextlO package 4 60 A VHDL use clause can be used to select specific declarations in a library or package that are to be visible within a design unit during compilation A use clause references the compiled version of the package not the source By default every design unit is assumed to contain the following declarations LIBRARY std work USE std standard all To specify that all declarations in a library or package can be referenced you can add the suffix all to the library package name For example the use clause above specifies that all declarations in the package standard in the design library named std are to be visible to the VHDL design file in which the use clause is placed Other libraries or packages are not visible unless they are explicitly specified using a library or use clause Another predefined library is work the library where a design unit is stored after it is compiled as described earlier Th
425. ration or termination This Agreement will automatically terminate if you fail to comply with any term or condition of this Agreement or if you fail to pay for the license when due and such failure to pay continues for a period of 30 days after written notice from Mentor Graphics If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction 10 EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain countries and certain persons You agree that you will not export in any manner any Software or direct product of Software without first obtaining all necessary approval from appropriate local and United States government agencies 11 RESTRICTED RIGHTS NOTICE Software has been developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement under which Software was obtained pursuant to DFARS 227 7202 3 a or
426. rder issues 5 85 XL compatible options 5 86 simulation hazard detection 5 86 simulation resolution limit 5 84 SmartModel interface 14 361 source code viewing 8 201 standards 1 17 system tasks 5 99 XL compatible compiler options 5 79 XL compatible routines 5 125 XL compatible system tasks 5 102 verilog ini file variable B 396 Verilog PLI 64 bit support 5 125 callback reason argument 5 117 registering applications 5 108 support for VHDL objects 5 121 Verilog PLI VPI 5 108 5 126 compiling and linking PLI VPI applications 5 111 debugging PLI VPI code 5 125 specifying the PLI VPI file to load 5 115 Verilog Procedural Interface 5 108 Veriuser ini file variable B 401 version obtaining 8 165 VHDL compile options 8 252 compiling design units 4 57 creating a design library 4 57 delay file opening B 405 dependency checking 4 57 file opening delay B 405 Hardware Model interface 15 364 instantiation from Verilog 6 136 instantiation of Verilog 6 128 library clause 3 50 mixed designs with Verilog 6 127 object support in PLI 5 121 simulating 4 58 SmartModel interface 14 354 ModelSim SE User s Manual Index 477 source code viewing 8 201 standards 1 17 timing check disabling 4 58 VITAL package 3 51 VHDL utilities 4 68 4 69 get_resolution 4 68 to_real 4 70 to_time 4 71 VHDL393 ini file variable B 397 view_profile command 9 285 view_profile_ranked command 9 286 Viewing and saving waveforms 7 137 8 220 Viewing desig
427. re the simulator state during the same session as when the state was saved use the command restore lt filename gt To restore the state after quitting ModelSim invoke vsim as follows vsim restore lt filename gt nocompress The checkpoint file is normally compressed If there is a need to turn off the compression you can do so by setting a special Tcl variable Use set CheckpointCompressMode 0 to turn compression off and turn compression back on with set CheckpointCompressMode 1 E 426 Tips and Techniques ModelSim SE User s Manual How to use checkpoint restore You can also control checkpoint compression using the modelsim ini file in the vsim section use the same 0 or 1 switch vsim CheckpointCompressMode lt switch gt If you use the foreign interface you will need to add additional function calls in order to use checkpoint restore See the FLI Reference Manual for more information The difference between checkpoint restore and restarting The restart CR 170 command resets the simulator to time zero clears out any logged waveforms and closes any files opened under VHDL and the Verilog fopen system task You can get the same effect by first doing a checkpoint at time zero and later doing a restore But with restart you dont have to save the checkpoint and the restart is likely to be faster But when you need to set the state to anything other than time zero you will need to use checkpoint re
428. reakpoint on a selected signal select Add Breakpoint from the context menu To remove a breakpoint from a selected signal select Remove Signal Breakpoint To remove all breakpoints in the current region select Remove All Signal Breakpoints To see a list of currently set breakpoints select Show Breakpoints 8 198 ModelSim Graphic Interface ModelSim SE User s Manual Signals window The Edit Breakpoint command opens the Edit When dialog box Edit When Condition Opt Label top sdata echo Break on top sdata stop Command s The Edit When dialog includes the following options e Condition The condition s to be met for the specified command s to be executed Required See the when command CR 273 for more information on creating the condition statement Opt Label An optional text label for the when statement Command s The command s to be executed when the specified condition is met Any ModelSim or Tel command or series of commands are valid with one exception the run command CR 176 cannot be used The Edit All Breakpoints command opens the Breakpoints dialog box See Setting file line breakpoints 8 205 for details ModelSim SE User s Manual ModelSim Graphic Interface 8 199 Signals window Defining clock signals Select Edit gt Clock to define clock signals by Name Period Duty Cycle Offset and whether the first rising edge is rising or falling You can also
429. references Edit Project Save Preferences no equivalent in 5 5 all Project editing is done from the Project page in the Workspace F 456 What s new in ModelSim ModelSim SE User s Manual Signals window changes Signals window changes The menus accessed from the Signals menu bar are the same in version 5 5 as they were in version 5 3 5 4 However the context menu accessed with a right mouse click in the Signals window has changed See Setting signal breakpoints 8 198 for complete details on this context menu 5 3 5 4 5 5 Add Guan EE Remove A Remova l Add Breakpoint Edit Breakpoint Show All new selections Edit All Breakpoint s Remove Breakpoint Remove All Breakpoints Show Breakpoints ModelSim SE User s Manual What s new in ModelSim F 457 Source window changes Source window changes Edit menu See The Source window menu bar 8 202 for complete menu option details new selection Options menu See The Structure window menu bar 8 211 for complete menu option details 5 5 Options OF x new selection F 458 What s new in ModelSim ModelSim SE User s Manual Wave window changes Wave window changes Menu bar and toolbar The version 5 5 Wave window menu bar has two new menus and the toolbar has four new icons See The Wave window menu bar 8 220 for complete menu
430. rilog PLI VPI Support for VHDL objects The PLI ACC routines also provide limited support for VHDL objects in either an all VHDL design or a mixed VHDL Verilog design The following table lists the VHDL objects for which handles may be obtained and their type and fulltype constants Type Fulltype Description accArchitecture accArchitecture instantiation of an architecture accArchitecture accEntityVitalLevel0 instantiation of an architecture whose entity is marked with the attribute VITAL_Level0 accArchitecture accArchVitalLevelO instantiation of an architecture which is marked with the attribute VITAL_Level0 accArchitecture accArchVitalLevell instantiation of an architecture which is marked with the attribute VITAL_Levell accArchitecture accForeignArch instantiation of an architecture which is marked with the attribute FOREIGN and which does not contain any VHDL statements or objects other than ports and generics accArchitecture accForeignArchMixed instantiation of an architecture which is marked with the attribute FOREIGN and which contains some VHDL statements or objects besides ports and generics accBlock accBlock block statement accForLoop accForLoop for loop statement accForeign accShadow foreign scope created by mti_CreateRegion accGenerate accGenerate generate statement accPackage accPackage package declarat
431. ring these bindings and as a result some errors cannot be detected during compilation Commonly these errors include modules that were referenced but not compiled incorrect port connections and incorrect hierarchical references The following example shows how a hierarchical design can be compiled in top down order Contents of top v module top or2 nl a b and2 n2 nl c endmodule Contents of and2 v module and2 y a b output y input a b and y a b endmodule Contents of or2 v module or2 y a b output y input a b or y a b endmodule Compile the design in top down order assumes work library already exists o vlog top v Compiling module top Top level modules top vlog and2 v Compiling module and2 Top level modules and2 vlog or2 v Compiling module or2 Top level modules or2 5 76 Verilog Simulation ModelSim SE User s Manual Compilation Note that the compiler lists each module as a top level module although ultimately only top is a top level module If a module is not referenced by another module compiled in the same invocation of the compiler then it is listed as a top level module This is just an informative message and can be ignored during incremental compilation The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top level module names for the simulator For ex
432. rmance Analyzer ModelSim SE User s Manual Ranked Hierarchical Profile Window Features The report option You can also use the profile report command CR 158 to save the Performance Analyzer results profile report lt option gt The arguments to the command are hierarchical ranked file lt filename gt cutoff lt percentage gt For example the command profile report hierarchical file hier rpt cutoff 4 will produce a profile report in a text file called hier rpt as shown here hier rpt Mls ES File Edit Search Help Hierarchical profile generated Thu Dec 16 13 22 48 1999 Number of samples 563 Number of samples in user code 387 69 Cutoff percentage 4 Name Under In Parent control uhd 87 16 testring uhd 97 retrieve_array uhd 35 testring vhd 177 ModelSim SE User s Manual Performance Analyzer 9 289 Setting preferences with Tcl variables Setting preferences with Tcl variables Various Tcl variables control how the Hierarchical Profile and Ranked Profile windows are displayed You can set these preference variables by selecting Options gt Edit Preferences gt By Name gt Profile Main window Use the Apply button to view temporary changes or Save the changes to a local modelsim tcl file Once saved the preferences will be the default for subsequent simulations invoked from the same directory See http www model com resources pref_variables frameset htm for more inf
433. rned value to be in units of femtoseconds fs you would enter the function this way realval le 15 to_real 12 99 ns get_resolution to_time converts a real value into a time value with respect to the current simulator resolution The precision of the converted value is determined by the simulator resolution For example if you were converting 5 9 to a time and the simulator resolution was ps then the time value would be 6 ps Syntax timeval to_time realval Returns Name Description timeval The real value represented as a physical type time with respect to the simulator resolution Arguments Description The value of the type real Related functions get_resolution 4 68 to_real 4 70 Example If the simulator resolution is set to ps and you enter the following function timeval to_time 72 49 then the value returned to timeval would be 72 ps ModelSim SE User s Manual VHDL Simulation 4 71 4 72 VHDL Simulation ModelSim SE User s Manual 5 Verilog Simulation Chapter contents Compilation eo oao om Se we So ow ae oe ae DTD Incremental compilation Loe os Be E TO Library usage bobo e w E Verilog XL compatible comit options oe k ow ow amp 979 Verilog XL uselib compiler directive 5 81 Simulation oho we amp ge amp poas 584 Invoking the Golan eee Ss ke ee Sek S84 Simulation resolution limit 2
434. rocess shown as inputs on the left of the window and all the signals driven by the process on the right Verilog nets registers or processes in the Dataflow window e A net or register is displayed in the center of the window with all the processes that drive the net or register on the left and all the processes triggered by the net or register on the right e A process is displayed with all the nets or registers that trigger the process shown as inputs on the left of the window and all the nets or registers driven by the process on the right dataflow Iof xi File Window dataflow OF Xx File Window paddr sum top p ASSIGN H15 ftop c sO line__34 ftop c s1 line__34 cout ftop c s2 line__34 ftop c s3 line__34 signal net register process Link to active cursor in Wave window In versions 5 5 and later the value of a signal net or register in the Dataflow window is linked to the active cursor in the Wave window As you move the active cursor in the Wave window the value of the signal net or register in the Dataflow window will update ModelSim SE User s Manual ModelSim Graphic Interface 8 171 Dataflow window Dataflow window menu bar The following menu commands and button options are available from the Dataflow window menu bar File menu Save Postscript save the current dataflow view as a Postscript file see Saving the Dataflow window as a Postscript file
435. rol how the coverage data is displayed You can set these preference variables by selecting Options gt Edit Preferences gt By Name gt Coverage Main window Use the Apply button to view temporary changes or Save the changes to a local modelsim tcl file Once saved the preferences will be the default for subsequent simulations invoked from the same directory See http www model com resources pref variables frameset htm for more information on the individual variables Code Coverage commands The commands below are available once Code Coverage is active Enable code coverage with the coverage option to the vsim command CR 258 The table below provides a brief description of the coverage commands follow the links for complete command syntax See the ModelSim Command Reference for complete command details Command Description coverage clear CR 92 clears all coverage data obtained during previous run commands coverage reload CR 93 merges coverage statistics with the output of a previous coverage report command coverage report CR 94 used to produce a textual output of the coverage statistics that have been gathered up to this point 10 300 Code Coverage ModelSim SE User s Manual 11 Waveform Comparison Chapter contents Introducing Waveform Comparison Two Modes of Comparison Comparing Hierarchical and Phartened Dedins Graphical Interface to Waveform Comparison Opening Dataset C
436. rovides a brief description of the actions associated with datasets logfiles and virtual commands For complete details about syntax arguments and usage refer to the ModelSim Command Reference Command name Action dataset close CR 95 closes the specified dataset dataset list CR 96 lists all open datasets dataset open CR 97 opens a dataset dataset rename CR 98 assigns a new logical name to the specified dataset log CR 131 creates a logfile for the current simulation nolog CR 139 suspends writing of data to the logfile for the specified signals searchlog CR 180 searches one or more of the currently open logfiles for a specified condition virtual function CR 233 creates a new signal that consists of logical operations on existing signals and simulation time virtual region CR 242 creates a new user defined design hierarchy region virtual signal CR 245 creates a new signal that consists of concatenations of signals and subelements virtual type CR 248 creates a new enumerated type vsim CR 258 wlf lt filename gt creates a logfile for the simulation which can be reopened as a dataset ModelSim SE User s Manual Datasets saved simulations and virtuals 7 147 7 148 Datasets saved simulations and virtuals ModelSim SE User s Manual 8 ModelSim Graphic Interface Chapter contents Window overview
437. rs for the module name port names and parameter names If a Verilog identifier is not a valid VHDL 1076 1987 identifier it is converted to a VHDL 1076 1993 extended identifier in which case you must compile the VHDL with the 93 switch Any uppercase letters in Verilog identifiers are converted to lowercase in the VHDL identifier except in the following cases e The Verilog module was compiled with the 93 switch This means vgencomp CR 224 should use VHDL 1076 1993 extended identifiers in the component declaration to preserve case in the Verilog identifiers that contain uppercase letters e The Verilog module port and generic names are not unique unless case is preserved In this event vgencomp CR 224 behaves as if the module was compiled with the 93 switch for those names only 6 132 Mixed VHDL and Verilog Designs ModelSim SE User s Manual VHDL instantiation of Verilog design units Examples Verilog identifier VHDL identifier topmod topmod TOPMOD topmod TopMod topmod top_mod top_mod _topmod _topmod topmod topmod topmod topmod If the Verilog module is compiled with 93 Verilog identifier VHDL identifier topmod topmod TOPMOD TOPMOD TopMod TopMod top_mod top_mod _topmod _topmod topmod topmod topmod topmod ModelSim SE User s Manual Mixed VHDL and Verilog Designs 6 133 VHDL instan
438. rsor Delete Cursor add a cursor to the center XK delete the selected cursor E of the waveform window from the window ModelSim SE User s Manual ModelSim Graphic Interface 8 239 Wave window Finding a cursor The cursor value on the Goto list corresponds to the simulation time of that cursor Choose a specific cursor view by selecting Cursor gt Goto Making cursor measurements Each cursor is displayed with a time box showing the precise simulation time at the bottom When you have more than one cursor each time box appears in a separate track at the bottom of the display ModelSim also adds a delta measurement showing the time difference between two adjacent cursor positions If you click in the waveform display the cursor closest to the mouse position is selected and then moved to the mouse position Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display Clicking anywhere in a track selects that cursor and brings it to the mouse position The cursors are designed to snap to the closest wave edge to the left on the waveform that the mouse pointer is positioned over You can control the snap distance via the Edit gt Display Properties menu selection You can position a cursor without snapping by dragging in the area below the waveforms You can also move cursors to the next transition of a signal with these toolbar buttons Find Previous Find Next Transition
439. rt time and end time or you can limit the comparison to a specific number of encountered timing differences In addition you can exclude windows of time with when conditions in either the clock definitions or in the compare add command CR 63 The display will indicate intervals of time during which no attempt was made to compute differences All waveform differences encountered in the waveform comparison are summarized and listed in the transcript area of the Main window Waveform differences are also displayed in the Wave and List windows see Wave window display 11 316 and List window display 11 322 Icons in the toolbar of the Wave window allow you to step forward and backward through successive differences Or you can use the Tab and Shift Tab keys on your keyboard to move to the next or previous difference of a selected signal You can also write a list of the differences to a file using the compare info command CR 73 11 302 Waveform Comparison ModelSim SE User s Manual Introducing Waveform Comparison Two Modes of Comparison The Waveform Comparison feature provides two modes of comparison continuous and clocked Continuous Compare In the continuous mode a test signal or a group of test signals within a region is compared to a reference signal or a group of reference signals within a region at each transition of the reference Timing differences between the test and reference signals are highlighted with rec
440. rtn MyStartOfSimCB callback user_data 0 void vpi_register_cb amp callback void vlog_startup_routines RegisterMySystfs 0 last entry must be 0 y Loading VPI applications into the simulator is the same as described in Registering PLI applications 5 108 5 110 Verilog Simulation ModelSim SE User s Manual Using the Verilog PLI VPI PLI and VPI applications can co exist in the same application object file In such cases the applications are loaded at startup as follows e If an init_usertfs function exists then it is executed and only those system tasks and functions registered by calls to mti_RegisterUserTF will be defined e If an init_usertfs function does not exist but a veriusertfs table does exist then only those system tasks and functions listed in the veriusertfs table will be defined e If an init_usertfs function does not exist and a veriusertfs table does not exist but a vlog_startup_routines table does exist then only those system tasks and functions and callbacks registered by functions in the vlog_startup_routines table will be defined As aresult when PLI and VPI applications exist in the same application object file they must be registered in the same manner VPI registration functions that would normally be listed in a vlog_startup_routines table can be called from an init_usertfs function instead Compiling and linking PLI VPI applications ModelSi
441. ry_reference gt is dir lt library_directory gt file lt library_file gt libext lt file_extension gt lib lt library_name gt In Verilog XL the library references are equivalent to command line options as follows dir lt library_directory gt y lt library_directory gt file lt library_file gt v lt library_file gt libext lt file_extension gt libext lt file_extension gt For example the following directive uselib dir h vendorA libext v is equivalent to the following command line options y h vendorA libext v Since the uselib directives are embedded in the Verilog source code there is more flexibility in defining the source libraries for the instantiations in the design The appearance of a uselib directive in the source code explicitly defines how instantiations that follow it are resolved completely overriding any previous uselib directives For example the following code fragment shows how two different modules that have the same name can be instantiated within the same design uselib dir h vendorA file v NAND2 ul n1 n2 n3 ModelSim SE User s Manual Verilog Simulation 5 81 Compilation uselib dir h vendorB file v NAND2 u2 n4 n5 n6 This allows the NAND2 module to have different definitions in the vendorA and vendorB libraries compile_uselibs argument In ModelSim versions 5 5 and later a vlog argument eases the use of uselib directives The comp
442. s By default the hm_entity tool writes an entity and foreign architecture to stdout for the hardware model Optionally you can include the component declaration c exclude the entity xe and exclude the architecture xa Once you have created the entity and foreign architecture you must compile it into a library For example the following commands compile the entity and foreign architecture for a hardware model named LMTEST hm_entity LMTEST MDL gt lmtest vhd vlib lmc vcom work lmc lmtest vhd ale ole o9 To instantiate the hardware model in your VHDL design you will also need to generate a component declaration If you have multiple hardware models you may want to add all of their component declarations to a package so that you can easily reference them in your design The following command writes the component declaration to stdout for the LMTEST hardware model hm_entity c xe xa LMTEST MDL Paste the resulting component declaration into the appropriate place in your design or into a package The following is an example of the entity and foreign architecture created by hm_entity for the CY7C285 hardware model library ieee use ieee std_logic_1164 all entity cy7c285 is generic DelayRange STRING Max port AO in std logici ModelSim SE User s Manual Logic Modeling Hardware Models 15 365 VHDL Hardware Model interface Al in std_logic A2 in std_logic A3 in std_logic
443. s List window to access the Triggers page l Modify Display Properties list EE ts Deltas ExpandDeltas Collapse Deltas No Deltas Trigger On Strobe Period fo ns MV Signals Strobe First Strobe at 0 ns Trigger Gating Teen Use Expression Builder Expression I On Duration fo ns OK Cancel Apply Check the Trigger Gating Expression check box Then click on Use Expression Builder Select the signal in the List window that you want to be the enable signal by E 444 Tips and Techniques ModelSim SE User s Manual Setting up a List trigger with Expression Builder clicking on its name in the header area of the List window Then click Insert Selected Signal and rising in the Expression Builder Expression Builder a Expression Builder pes el PEA JE E ESE ES E Jen E e Pe E JE EJE PEA ES YES JE JES Click OK to close the Expression Builder You should see the name of the signal plus rising added to the Expression entry box of the Modify Display Properties dialog box Leave the On Duration field zero for now Click the OK button If you already have simulation data in the List window the display should immediately switch to showing only those cycles for which the gating signal is rising If that isn t quite what you want you can go back to the expression builder and play with it until you get it the way you want it If you want the
444. s a VSIM prompt allowing you to enter command line commands from within the graphic interface You can scroll backward and forward through the current work history by using the vertical scrollbar You can also use arrow keys to recall previous commands or copy and paste using the mouse within the window see Mouse and keyboard shortcuts in the Transcript and Source windows 8 168 for details Saving the Main window transcript file Variable settings determine the filename used for saving the Main window transcript If either PrefMain file in modelsim tcl or TranscriptFile in modelsim ini file is set then the transcript output is logged to the specified file By default the TranscriptFile variable in modelsim ini is set to transcript If either variable is set the transcript contents are always saved and no explicit saving is necessary If you would like to save an additional copy of the transcript with a different filename you can use the File gt Save Transcript As or File gt Save Transcript menu items The initial save must be made with the Save Transcript As selection which stores the filename in the Tcl variable PrefMain saveFile Subsequent saves can be made with the Save Transcript selection Since no automatic saves are performed for this file it is written only when you invoke a Save command The file is written to the specified directory and records the contents of the transcript at the time of the save Using the saved
445. s implemented poorly and to implement a change that runs several times faster More commonly the Performance Analyzer will tell you that 30 of simulation time was spent in model X 25 in model Y and 20 in model Z In such situations careful ModelSim SE User s Manual Performance Analyzer 9 283 Interpreting the data examination and improvement of each model may result in a significant overall speed improvement There are times however when the Performance Analyzer tells you nothing better than that the simulation has executed in several hundred different models and has spent less than 1 of its time in any one of them In such situations the Performance Analyzer provides little helpful information and simulation improvement must come from a higher level examination of how the design can be changed or optimized Viewing Performance Analyzer Results The Performance Analyzer provides two views of the collected data a hierarchical and a ranked view The hierarchical view is accessed by clicking View gt Other gt Hierarchical Profile Main window The ranked view is accessed by selecting View gt Other gt Ranked Profile l ModelSim 01 x File Edit Design MY All fe ark at 27852400 ns Primary Channel a config_rtl vhd Hide Workspace ark s at 29478800 ns Primary Channel Her ark at 29479600 ns Primary Channel laa control vhd El ark at 29480000 ns Primary Channel Pal retrieve vid
446. s shown in the picture below you may also see the following in the left hand pane e Green line numbers denote executable lines e Blue arrow denotes a process that you have selected in the Process window 8 190 e Red circles denote file line breakpoints hollow circles denote breakpoints that are currently disabled W source counter yhd Iof x File Edit Object Options Window SE BAA 00 end increment begin ctr process clk reset begin if reset 1 then if reset event then count lt others gt 0 after tpd_reset_to_count end if elsif clk event and clk 1l then count lt increment count after tpd clk to_count end if end process ModelSim SE User s Manual ModelSim Graphic Interface 8 201 Source window The Source window menu bar The following menu commands are available from the Source window menu bar File menu New edit a new VHDL Verilog or Other source file Open select a source file to open Use Source specify an alternative file to use for the current source file this alternative source mapping exists for the current simulation only Source Directory add to a list of directories the SourceDir variable in modelsim tcl to search for source files Properties lista variety of information about the source file for example file type file size file modification date Save save the current source file Save As save the current sour
447. s the path to the modelsim tcl file this environment variable can be a list of file pathnames separated by semicolons Windows or colons UNIX Initialization sequence The following list describes in detail ModelSim s initialization sequence The sequence includes a number of conditional structures the results of which are determined by the existence of certain files and the current settings of environment variables In the steps below names in uppercase denote environment variables except MTI_LIB_DIR which is a Tcl variable Instances of NAME denote paths that are determined by an environment variable except MTI_LIB_DIR which is determined by a Tcl variable Determines the path to the executable directory modeltech lt platform gt Sets MODEL_TECH to this path unless MODEL_TECH_OVERRIDE exists in which case MODEL_TECH is set to the same value as MODEL_TECH_ OVERRIDE Finds the modelsim ini file by evaluating the following conditions e use MODELSIM if it exists else e use MGC_WD modelsim ini else use modelsim ini else use MODEL_TECH modelsim ini else use MODEL_TECH modelsim ini else use MGC_HOME ib modelsim ini else set path to modelsim ini even though the file doesn t exist Finds the location map file by evaluating the following conditions use MGC_LOCATION_MAP if it exists if this variable is set to no_map ModelSim skips initialization of the location map else
448. s the selected dataset active You can also effect this change by double clicking the dataset name Active dataset means that 1f you type a region path as part of a command and omit the dataset prefix the active dataset will be assumed It is equivalent to typing env lt dataset gt at the VSIM prompt Rename Dataset Allows you to assign a new logical name for the selected dataset Using datasets with Model Sim commands Multiple datasets can be opened when the simulator is invoked by specifying more than one vsim view lt filename gt option By default the dataset prefix will be the filename of the WLF file A different dataset name can also be specified as an optional qualifier to the vsim view switch on the command line using the following syntax view lt dataset gt lt filename gt For example vsim view foo vsim wlf 7 142 Datasets saved simulations and virtuals ModelSim SE User s Manual Datasets Design regions and signal names can be fully specified over multiple logfiles by using the dataset name as a prefix in the path For example sim top alu out view top alu out golden top alu out Dataset prefixes are not required unless more than one dataset is open and you want to refer to something outside the default dataset When more than one dataset is open ModelSim will automatically prefix names in the Wave and List window with the dataset name You can change this default by selecting Edit gt Displ
449. sage appears in the transcript window about which signal caused the breakpoint Breakpoints created by the when command CR 273 are not affected by the Remove All Signals menu pick nor are they reported via Show All 8 236 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Finding items by name or value in the Wave window The Find dialog box allows you to search for text strings in the Wave window Select Edit gt Find Wave window to bring up the Find dialog box Choose either the Name or Value field to search Find in wave xi and enter the value to search for in the Find Find Find Next field Find the item by searching Down or Up Field Direction Close through the Wave Name Down window display Auto Wrap continues the Value Up IV Auto Wrap search at the top of the window The find operation works only within the active pane Searching for item values in the Wave window Select an item in the Wave window and then select Edit gt Search to bring up the Wave Signal Search dialog box Wave Signal Search window wave Signal Name s No Signals Selected Search Type Any Transition Rising Edge C Falling Edge Search for Signal Value Value Search for Expression Expression Builder Search Options Search Forward fi Match Count Search Reverse Search Results Status Time Done ModelSim SE Use
450. se Button Paste 8 203 5 5 init_signal_spy utility reference signals registers or wires at any level of hierarchy init_signal_spy 4 69 and init_signal_spy 5 104 5 5 get_resolution function returns the current simulator resolution as a real get_resolution 4 68 5 5 to_real function converts the physical type time to the type real to_real 4 70 5 5 to_time function converts the type real to the physical type time to_time 4 71 5 5 compare commands several commands for doing waveform comparisons Compare commands 11 323 5 3 bookmark commands several commands for saving editing bookmarks bookmark add wave CR 44 5 5 PrefCompare Tcl variables Tcl preference variables for waveform comparisons Preference variable database 5 3 delay argument for virtual signal and virtual function assign delay to signals within a virtual command virtual function CR 233 amp virtual signal CR 245 5 5 keeploaded and keeploadedrestart arguments for vsim leaves FLI PLI VPI shared libraries loaded during a restart or design load keeploaded CR 260 and keeploadedrestart CR 260 5 5 vsim arguments related to WLF files four arguments control WLF file creation 1f lt filename gt CR 263 lfslim lt size gt CR 263 1f t1im lt duration gt CR 263 and wlfnocompress CR 264
451. se jeee std_logic_1164 all ModelSim SE User s Manual Logic Modeling SmartModels 14 355 VHDL SmartModel interface package sml is lt component declarations go here gt end sml Compile the package into the Ime library vcom work lmc smlcomp vhd The SmartModels can now be referenced in your design by adding the following library and use clauses to your code library l1mc use lmc sml all The following is an example of an entity and foreign architecture created by sm_entity for the cy7c285 SmartModel library ieee use ieee std_logic_1164 all entity cy7c285 is generic TimingVersion STRING CY7C285 65 DelayRange STRING Max MemoryFile STRING memory port AO in std_logic Al in std_logic A2 in std_logic A3 in std_logic A4 in std_logic A5 in std_logic A6 in std_logic A7 in std_logic A8 in std_logic A9 in std_logic A10 in std_logic All in std_logic A12 in std_logic A13 in std_logic A14 in std_logic A15 in std_logic CS in std_logic 00 out std_logic O out std_logic 02 out std_logic 03 out std_logic 04 out std_logic 05 out std_logic 06 out std_logic O7 out std_logic WAIT_PORT inout std_logic end architecture SmartModel of cy7c285 is attribute FOREIGN STRING attribute FOREIGN of SmartModel architecture is sm_init SMODEL_TECH libsm sl cy7c285 begin end SmartModel 14 356 Logic
452. select a line number in the bottom pane that line is scrolled to in the coverage_source window In addition any exclusions you make in the coverage_summary window automatically show up in the coverage_source window and vice versa Summary information Misses tab Exclusions tab The top pane of the coverage_summary window shows all of the design files that have executable lines of code The columns of information include e The Pathname column shows the path and file name The Lines column contains the number of executable lines in the file The Hits column indicates the number of executable lines that have been executed in the current simulation e The Percentage column is the current ratio of Hits to Lines There is also a bar chart that graphically displays this percentage If the coverage percentage is below 90 the bar chart is displayed in red you can change the percentage by editing the PrefCoverage cutoff preference variable By default the summary information is sorted by Pathname You can sort by another column by clicking on the column heading i e Lines Hits A totals row at the bottom of the summary information shows coverage statistics for all of the files combined The Misses tab lists lines from the current file with no hits Select a file in the top pane of the coverage_summary window to see that file s missed lines This tab also lets you select lines to exclude Select the line s you want to ex
453. sic sdf testbench If the instance name is omitted then the SDF file is applied to the top level This is usually incorrect because in most cases the model is instantiated under a testbench or within a larger system level simulation In fact the design can have several models each having its own SDF file In this case specify an SDF file for each instance For example vsim sdfmax system ul asicl sdf sdfmax system u2 asic2 sdf system One exception to the rule of never omitting the instance name occurs when your SDF file contains only one instance In this case you can omit the instance name For example if myasic sdf has only one instance of ul the first command above would look as follows vsim sdfmax myasic sdf testbench 12 326 Standard Delay Format SDF Timing Annotation ModelSim SE User s Manual Specifying SDF files for simulation SDF specification with the GUI As an alternative to the command line options you can specify SDF files in the Load Design dialog box under the SDF tab ER Load Design OF ES NN sor SDF Files Region File Add Delete Edit SDF Options Multi Source delay latest Disable SDF warnings C min Reduce SDF errors to warnings C max Load Exit Cancel You can access this dialog by invoking the simulator without any arguments or by selecting Design gt Load Design Main window For Verilog designs you can also
454. sign unit entity e architecture arch SDF annotation A mixed VHDL Verilog design can also be annotated with SDF See SDF for Mixed VHDL and Verilog Designs 12 336 for more information 6 136 Mixed VHDL and Verilog Designs ModelSim SE User s Manual 7 Datasets saved simulations and virtuals Chapter contents Datasets 2 o 7 wee 138 Saving a simulation to a dataset 7 138 Opening datasets 2 eee 7 19 Viewing dataset structure 7 140 Managing datasets F142 Using datasets with ModelSim commands 7 142 Restricting the dataset prefix display 7 143 Virtual Objects User defined buses and more 7 144 Virtual signals o 7 144 Virtual functions lt s s s w e p e e e Ue LAS Virtual regions aaa 7 146 Virtual types s e s s so e w F146 Dataset logfile and virtual commands 7 147 A ModelSim simulation can be saved to a logfile using the w1f lt filename gt argument to the vsim command CR 258 for future viewing or comparison to a current simulation We use the term dataset to refer to a logfile that has been reopened in the program With ModelSim release 5 3 and later you can open more than one dataset for simultaneous viewing You can also create virtual signals that are simple logical combinations of or logical functions of signals from differen
455. signs 14 Logic Modeling SmartModels 14 353 This chapter describes the use of the SmartModel Library and SmartModel Windows with ModelSim 15 Logic Modeling Hardware Models 15 363 This chapter describes the use the Logic Modeling Hardware Modeler with ModelSim 16 Tcl and ModelSim 16 369 This chapter provides an overview of Tcl tool command language as used with ModelSim Additional Tcl and Tk Tcl s toolkit information can be found through several Tcl online references 16 370 A Technical Support Updates and Licensing A 385 This appendix describes how and where to get technical support and updates and licensing for ModelSim It also contains links to the Model Technology web site and references to books organizations and companies involved in EDA and simulation B ModelSim Variables B 391 This appendix describes environment system and preference variables used in ModelSim C ModelSim Shortcuts C 409 This appendix describes ModelSim keyboard and mouse shortcuts D Using the FLEXIm License Manager D 417 This appendix covers Model Technology s application of FLEXIm for ModelSim licensing E Tips and Techniques E 425 This appendix contains an extended collection of ModelSim usage examples taken from our manuals and tech support solutions F What s new in ModelSim F 447 This appendix lists new features and changes in the various versions of ModelSim Command reference The comple
456. specify SDF files by using the sdf_annotate system task See The sdf_annotate system task 12 330 for more details Errors and warnings Errors issued by the SDF annotator while loading the design prevent the simulation from continuing whereas warnings do not Use the sdfnoerror option with vsim CR 258 to change SDF errors to warnings so that the simulation can continue Warning messages can be suppressed by using vsim with either the sdfnowarn or nosdfwarn options Another option is to use the SDF page from the Load Design dialog box shown above Select Disable SDF warnings sdfnowarn or nosdfwarn to disable warnings or select Reduce SDF errors to warnings sdfnoerror to change errors to warnings See Troubleshooting 12 337 for more information on errors and warnings and how to avoid them ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 327 VHDL VITAL SDF VHDL VITAL SDF VHDL SDF annotation works on VITAL cells only The IEEE 1076 4 VITAL ASIC Modeling Specification describes how cells must be written to support SDF annotation Once again the designer does not need to know the details of this specification because the library provider has already written the VITAL cells and tools that create compatible SDF files However we provide the following summary to help you understand simulator error messages For additional VITAL specification information see Obtaining the VITAL speci
457. specify a simulation period after which the clock definition should be cancelled Define Clock Clock Name Sie Offset 0 First Edge Duty 50 Period 100 Cancel its Rising C Falling OK Cancel For clock signals starting on the rising edge the definition for Period Offset and Duty Cycle is as follows Period High Value Low Value Offset High Time Duty Cycle High Time Period If the signal type is std_logic std_ulogic bit verilog wire verilog net or any other logic type where 1 and 0 are valid then 1 is the default High Value and 0 is the default Low Value For other signal types you will need to specify a High Value and a Low Value for the clock 8 200 ModelSim Graphic Interface ModelSim SE User s Manual Source window Source window The Source window allows you to view and edit your HDL source code When you first load a design the source file will display automatically if the Source window is open Alternatively you can select an item in the Structure window 8 210 or use the File gt Open command Source window to add a file to the window Your source code can remain hidden if you wish see Source code security and nodebug E 433 The window is divided into two panes the left hand pane contains line numbers and the right hand pane contains the source file The pathname of the source file is indicated in the header of the Source window A
458. splay Hello world endmodule Create the work library vlib work Compile the design 2 vlog top v Compiling module top Top level modules top View the contents of the work library optional o vdir MODULE top Simulate the design vsim c top Loading work top VSIM 1 gt run all Hello world VSIM 2 gt quit In this example the simulator was run without the graphic interface by specifying the e option After the design was loaded the simulator command run all was entered meaning to simulate until there are no more simulator events Finally the quit command was entered to exit the simulator By default a log of the simulation is written to the file transcript in the current directory ModelSim SE User s Manual Verilog Simulation 5 75 Compilation Incremental compilation By default ModelSim Verilog supports incremental compilation of designs thus saving compilation time when you modify your design Unlike other Verilog simulators there is no requirement that you compile the entire design in one invocation of the compiler although you may wish to do so to optimize performance see Compiling for faster performance 5 90 You are not required to compile your design in any particular order because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator Incremental compilation is made possible by defer
459. store Using macros with restart and checkpoint restore The restart CR 170 command resets and restarts the simulation kernel and zeros out any user defined commands but it does not touch the state of the macro interpreter This lets you do restart commands within macros The pause mode indicates that a macro has been interrupted That condition will not be affected by a restart and if the restart is done with an interrupted macro the macro will still be interrupted after the restart The situation is similar for using checkpoint restore without quitting ModelSim that is doing a checkpoint CR 62 and later in the same session doing a restore CR 172 of the earlier checkpoint The restore does not touch the state of the macro interpreter so you may also do checkpoint and restore commands within macros ModelSim SE User s Manual Tips and Techniques E 427 Running command line and batch mode simulations Running command line and batch mode simulations The typical method of running ModelSimis interactive you push buttons and or pull down menus in a series of windows in the GUI graphic user interface But there are really three specific modes of ModelSim operation GUI command line and batch Here are their characteristics GUI mode This is the usual interactive mode it has graphical windows push buttons menus and a command line in the text window This is the default mode Command line mode This an operational mode
460. such that a delay is based on a transition from the current output value rather than the cancelled pending value of the net This option has no effect in transport mode see puls lt percent gt and pulse_r lt percent gt 1 lt filename gt By default the simulation log is written to the file transcript The l option allows you to specify an alternate file maxdelays This option selects the maximum value in min typ max expressions The default is the typical value This option has no effect 1f the min typ max selection was determined at compile time mindelays This option selects the minimum value in min typ max expressions The default is the typical value This option has no effect if the min typ max selection was determined at compile time multisource_int_delays This option enables multisource interconnect delays with transport delay behavior and pulse handling ModelSim uses a unique delay value for each driver to driven module 5 86 Verilog Simulation ModelSim SE User s Manual Simulation interconnect path specified in the SDF file Pulse handling is configured using the pulse_int_e and pulse_int_r switches described below no_neg_tchk This option disables negative timing check limits by setting them to zero By default negative timing check limits are enabled This is just the opposite of Verilog XL where negative timing check limits are disabled by default and they are enabled with the neg_tchk opti
461. t delete character to the left lt delete gt lt control d gt lt delete gt delete character to the right none esc cancel lt alt gt activate or inactivate menu bar mode lt alt gt lt F4 gt close active window lt control a gt lt home gt lt home gt move cursor to the beginning of the line lt control b gt move cursor left lt control d gt delete character to the right lt control e gt lt end gt lt end gt move cursor to the end of the line lt control f gt move cursor right one character lt control k gt delete to the end of line lt control n gt move cursor one line down Source window only under Windows lt control o gt none insert a newline character in front of the cursor lt control p gt move cursor one line up Source window only under Windows lt control s gt lt control f gt find lt F3 gt find next lt control t gt reverse the order of the two characters to the right of the cursor lt control u gt delete line ModelSim SE User s Manual ModelSim Graphic Interface 8 169 Main window Keystrokes UNIX Keystrokes Windows Result lt control v gt PageDn move cursor down one screen lt control w gt lt control x gt cut the selection
462. t shift left button press gt extend selection lt left button double click gt select word lt left button double click gt drag select word word lt control left button click gt move insertion cursor without changing the selection lt left button click gt on previous ModelSim or VSIM prompt copy and paste previous command string to current prompt lt middle button click gt paste clipboard lt middle button press gt drag scroll the window 8 168 ModelSim Graphic Interface ModelSim SE User s Manual Main window Keystrokes UNIX Keystrokes Windows Result lt left right arrow gt move cursor left right one character lt control gt lt left right arrow gt move cursor left right one word lt shift gt lt left right up down arrow gt extend selection of text lt control gt lt shift gt lt left right arrow gt extend selection of text by word lt up down arrow gt scroll through command history in Source window moves cursor one line up down lt control gt lt up down gt moves cursor up down one paragraph lt control gt lt home gt move cursor to the beginning of the text lt control gt lt end gt move cursor to the end of the text lt backspace gt lt control h gt lt backspace g
463. t datasets ModelSim SE User s Manual Datasets saved simulations and virtuals 7 137 Datasets Datasets The term dataset refers to a simulation waveform database that was saved and then subsequently reloaded for viewing or comparing Any number of datasets can be opened in view mode View mode allows you to view but not run a previous simulation A prefix identifies each dataset that is opened The current active simulation is prefixed by sim while any datasets loaded for viewing are prefixed by the filename of the logfile For example two datasets are displayed in the Wave window below the current simulation is shown in the top pane and is indicated by the sim prefix a dataset from a previous simulation is shown in the bottom pane and is indicated by the test1 prefix wave default Al x File Edit Cursor Zoom Compare Bookmark Format Window ob EB R le QQQQ BJE Jae ol sim 2proc clk St sim proc rdy Hiz sim proc addr 00000001 CO AO AT sim proc rw std sim proc strb sto sim proc data 2222222222222222 test top clk test top prwy test1 top pstrb D ns to 876 ns gt Note The simulator time resolution see Resolution B 400 must be the same for all datasets you re comparing including the current simulation Saving a simulation to a dataset The results of each simulation run are automatically saved to a dataset file called vsim wlf i
464. t determined at compile time you must instruct the simulator to search your libraries when loading the design The top level modules are loaded from the library named work unless you specify an alternate library with the lib option All other Verilog instantiations are resolved in the following order e Search libraries specified with Lf options in the order they appear on the command line e Search the library specified in the Verilog XL uselib compiler directive 5 81 e Search libraries specified with L options in the order they appear on the command line e Search the work library e Search the library explicitly named in the special escaped identifier instance name It is important to recognize that the work library is not necessarily a library named work the work library refers to the library containing the module that instantiates the module or UDP that is currently being searched for This definition is useful if you have hierarchical modules organized into separate libraries and if sub module names overlap among the libraries In this situation you want the modules to search for their sub modules in the work library first This is accomplished by specifying L work first in the list of search libraries For example assume you have a top level module top that instantiates module modA from library libA and module modB from library libB Furthermore modA and modB both instantiate modules named cellA but the definiti
465. t is updated with the SDF timing value SDF constructs are matched to Verilog constructs as follows IOPATH is matched to specify path delays or primitives SDF Verilog IOPATH posedge clk q 3 4 posedge clk gt q 0 IOPATH a y 3 4 buf ul y a The IOPATH construct usually annotates path delays If the module contains no path delays then all primitives that drive the specified output port are annotated INTERCONNECT and PORT are matched to input port SDF Verilog INTERCONNECT ul y u2 a 5 input a PORT u2 a 5 inout a Both of these constructs identify a module input or inout port and create an internal net that is a delayed version of the port This is called a Module Input Port Delay MIPD All primitives specify path delays and specify timing checks connected to the original port are reconnected to the new MIPD net PATHPULSE and GLOBALPATHPULSE are matched to specify path delays SDF Verilog PATHPULSE a y 5 10 a gt y 0 GLOBALPATHPULSE a y 30 60 a gt y 0 If the input and output ports are omitted in the SDF then all path delays are matched in the cell ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 331 Verilog SDF DEVICE is matched to primitives or specify path delays SDF Verilog DEVICE y 5 and ul y a b DEVICE y 5 a gt y 0 b gt y 0
466. t n gt are the numbers from 1 9 Default lt file root gt is wave Also runs windowSet do file if it exists 16 382 Tcl and ModelSim ModelSim SE User s Manual Tcl examples Add wave management buttons to the main toolbar proc add_wave_buttons _add_menu main controls right SystemMenu SystemWindowFrame Load Waves load_wave _add_menu main controls right SystemMenu SystemWindowFrame Save Waves save_wave _add_menu main controls right SystemMenu SystemWindowFrame New Wave new_wave Simple Dialog requests name of new wave window Defaults to Wave lt n gt proc new_wave global dialog_prompt vsimPriv set defaultName Wave llength SvsimPriv WaveWindows set dialog_prompt result defaultName set windowName GetValue Create Named Wave Window Debug puts Window name SwindowName n if SwindowName set windowName if SwindowName named_wave SwindowName else named_wave S defaultName Creates a new wave window with the provided name defaults to Wave proc named_wave name Wave global vsimPriv view new wave set newWave lindex vsimPriv WaveWindows expr llength Y SvsimPriv WaveWindows 1 wm title newWave name Writes out format of all wave windows stores geometry and title info in windowSet do file Removes any extra files with the same fileroot Default file name is wave lt n gt starting from 1 proc save_wa
467. t the Show_source B 397 variable in the modelsim ini file to set a permanent default Other Verilog Options Library Search Specifies the Verilog source library directory to search for undefined modules Same as the y lt library_directory gt switch for the vlog command CR 250 Extension Specifies the suffix of files in the library directory Multiple suffixes can be used Same as the libext lt suffix gt switch for the vlog command CR 250 Library File Specifies the Verilog source library file to search for undefined modules Same as the v lt library_file gt switch for the vlog command CR 250 Include Directory Specifies a directory for files included with the include filename compiler directive Same as the incdir lt directory gt switch for the vlog command CR 250 Macro Defines a macro to execute during compilation Same as the compiler directive define macro_name macro_text Also the same as the define lt macro_name gt lt macro_text gt switch for the vlog command CR 250 ModelSim SE User s Manual ModelSim Graphic Interface 8 255 Simulating with the graphic interface Simulating with the graphic interface You can use a project or the Load Design dialog box to simulate a compiled design For information on simulating in a project see Getting started with projects 2 28 To open the Load Design dialog select the Load Design button Main window or Design gt Load Design
468. t time gt evaluates for greater than gteTime lt time gt lt time gt evaluates for greater than or equal ltTime lt time gt lt time gt evaluates for less than lteTime lt time gt lt time gt evaluates for less than or equal All relation operations return 1 or 0 for true or false respectively and are suitable return values for TCL conditional expressions For example if eqTime Now 1750ns ModelSim SE User s Manual Tcl and ModelSim 16 379 ModelSim Tcl time commands Arithmetic Command Description add Time lt time gt lt time gt add time divTime lt time gt lt time gt 64 bit integer divide mulTime lt time gt lt time gt 64 bit integer multiply subTime lt time gt lt time gt subtract time 16 380 Tcl and ModelSim ModelSim SE User s Manual Tcl examples Tcl examples Example 1 The following Tcl ModelSim example for UNIX shows how you can access system information and transfer it into VHDL variables or signals and Verilog nets or registers When a particular HDL source breakpoint occurs a Tcl function is called that gets the date and time and deposits it into a VHDL signal of type STRING If a particular environment variable DO_ECHO is set the function also echoes the new date and time to the transcript file by examining the VHDL variable Note In a Windows environment the Tcl exec command shown below will execute compiled
469. tangular red difference markers in the Wave window and yellow markers in the List window The continuous compare mode allows you to specify two edge tolerances for timing differences The leading edge tolerance specifies how much earlier the test signal edge may occur before the reference signal edge The trailing edge tolerance specifies how much later the test signal edge may occur after the reference signal edge The default value for both tolerances is zero In addition these tolerances may be specified differently for each signal compared Clocked Compare In the clocked mode also called strobed comparison one or more clocks are defined A test signal is then compared to a reference signal and both are sampled relative to the defined clock The clock can be defined as the rising or falling edge or either edge of a particular signal plus a user specified delay The design need not have any events occurring at the specified clock time Differences between the test signal s and clock are highlighted with red diamonds in the Wave window ModelSim SE User s Manual Waveform Comparison 11 303 Introducing Waveform Comparison Comparing Hierarchical and Flattened Designs If you are comparing a hierarchical RTL design simulation against a flattened synthesized design simulation you may have different hierarchies different signal names and the buses may be broken down into one bit signals in the gate level design All of these di
470. td 1076 1987 and IEEE Std 1076 1993 it allows human readable text input from a declared source within a VHDL file during simulation ModelSim SE User s Manual VHDL Simulation 4 55 Compiling and simulating with the GUI Many of the examples in this chapter are shown from the command line For compiling and simulating within a project or the ModelSim GUI see e Getting started with projects 2 28 e Compiling with the graphic interface 8 250 e Simulating with the graphic interface 8 256 ModelSim variables Several variables are available to control simulation provide simulator state feedback or modify the appearance of the ModelSim GUI To take effect some variables such as environment variables must be set prior to simulation See Appendix B ModelSim Variables for a complete listing of ModelSim variables 4 56 VHDL Simulation ModelSim SE User s Manual Compiling VHDL designs Compiling VHDL designs Creating a design library Before you can compile your design you must create a library in which to store the compilation results Use vlib CR 249 to create a new library For example vlib work This creates a library named work By default compilation results are stored in the work library B Note The work library is actually a subdirectory named work This subdirectory contains a special file named _info Do not create libraries using UNIX MS Windows or DOS commands always use the vlib command
471. te command reference for all ModelSim commands is located in the ModelSim Command Reference Command Reference cross reference page numbers are prefixed with CR e g ModelSim Commands CR 9 ModelSim SE User s Manual Introduction 1 19 Text conventions Text conventions Text conventions used in this manual include italic text provides emphasis and sets off filenames path names and design unit names bold text indicates commands command options menu choices package and library logical names as well as variables and dialog box selection monospace type monospace type is used for program and command examples The right angle gt 1s used to connect menu choices when traversing menus as in File gt Save path separators examples will show either UNIX or Windows path separators use separators appropriate for your operating system when trying the examples UPPER CASE denotes file types used by ModelSim e g DO WLF INI MPF PDF etc What is an HDL item Because ModelSim works with both VHDL and Verilog HDL refers to either VHDL or Verilog when a specific language reference is not needed Depending on the context HDL item can refer to any of the following VHDL block statement component instantiation constant generate statement generic package signal or variable Verilog function module instantiation named fork named b
472. ted by setting the break on assertion level to error To enable hazard detection you must invoke vlog CR 250 with the hazards option when you compile your source code and you must also invoke vsim with the hazards option when you simulate Limitations of hazard detection e Reads and writes involving bit and part selects of vectors are not considered for hazard detection The overhead of tracking the overlap between the bit and part selects is too high e A WRITE WRITE hazard is flagged even if the same value is written by both processes e A WRITE READ or READ WRITE hazard is flagged even if the write does not modify the variable s value e Glitches on nets caused by non guaranteed event ordering are not detected Verilog XL compatible simulator options See vsim CR 258 for a complete list of simulator options The options described here are equivalent to Verilog XL options Many of these are provided to ease the porting of a design to ModelSim Verilog talt_path_delays Specify path delays operate in inertial mode by default In inertial mode a pending output transition is cancelled when a new output transition is scheduled The result is that an output may have no more than one pending transition at a time and that pulses narrower than the delay are filtered The delay is selected based on the transition from the cancelled pending value of the net to the new pending value The alt_path_delays option modifies the inertial mode
473. tended VCD format is supported only for pure VHDL designs Specifying a filename and state mappings After using splitio the VCD filename and state mapping are specified using the ved files command CR 210 with the nomap direction options Note that the nomap option is not necessary if the port types on the top level design are bit or bit_vector It is required however for std_logic ports because it records the entire std_logic state set This allows the vedread option to duplicate the original stimulus on the ports The default VCD file is dump vcd but you can specify a different filename with ved files Creating the VCD file After invoking ved files you can create the new VCD file by executing ved add CR 198 at the time you wish to begin capturing value changes To dump everything in a design to a dump file you might use a command like this ved add r At a minimum the VCD file must contain the in and inout ports of the design unit Value changes on all other signals are ignored by vedread This also means that the simulation results are not checked against the VCD file After the VCD file is created it can be input to vsim CR 258 with the vedread option to resimulate the design unit stand alone 13 344 Value Change Dump VCD Files ModelSim SE User s Manual Resimulating a VHDL design from a VCD file Example The following example illustrates a typical sequence of commands to create a VCD file for i
474. ter outlines data mapping and the criteria established to instantiate design units between HDLs 7 Datasets saved simulations and virtuals 7 137 This chapter describes datasets and virtuals both methods for viewing and organizing simulation data in ModelSim 8 ModelSim Graphic Interface 8 149 This chapter describes the graphic interface available while operating ModelSim ModelSim s graphic interface is designed to provide consistency throughout all Operating system environments 9 Performance Analyzer 9 281 This chapter describes how the ModelSim Performance Analyzer is used to easily identify areas in your simulation where performance can be improved 10 Code Coverage 10 291 This chapter describes the Code Coverage feature Code Coverage gives you graphical and report file feedback on how the source code is being executed 11 Waveform Comparison 11 301 This chapter describes Waveform Comparison a feature that lets you compare simulations 12 Standard Delay Format SDF Timing Annotation 12 325 This chapter discusses ModelSim s implementation of SDF Standard Delay Format timing annotation Included are sections on VITAL SDF and Verilog SDF plus troubleshooting 1 18 Introduction ModelSim SE User s Manual Command reference 13 Value Change Dump VCD Files 13 341 This chapter explains Model Technology s Verilog VCD implementation for ModelSim The VCD usage is extended to include VHDL de
475. tes select Main window gt Help gt Technotes or located in the modeltech docs technotes directory Download a free PDF reader with Search Model Technology s PDF documentation requires an Adobe Acrobat Reader for viewing The Reader may be installed from the ModelSim CD It is also available without cost from Adobe at http www adobe com Be sure to download the Acrobat Reader with Search to take advantage of the index file supplied with our documentation the index makes searching for key words much faster ModelSim SE User s Manual Introduction 1 21 Online References www model com Online References www model com The Model Technology web site includes links to support software downloads and many EDA information sources Check the links below for the most current information Latest version email Place your name on our list for email notification of new releases and updates model com support register_news_list asp News Current news of Model Technology within the EDA industry model com news_events default asp Partners Model Technology s value added partners OEM partners FPGA partners ASIC partners and training partners model com partners default asp Products A complete collection of Model Technology product information model com products default asp Technical Documents Technical notes application notes FAQs model com resources techdocs asp Sales Lo
476. th environment variables Once the MY_PATH variable is set you can use it with the vmap command CR 257 to add library mappings to the current modelsim ini file If you re using the vmap command from DOS prompt type vmap MY_VITAL MY_PATH If you re using vmap from ModelSim VSIM prompt type vmap MY_VITAL SMY_PATH If you used DOS vmap this line will be added to the modelsim ini MY_VITAL c temp work If vmap is used from the ModelSim VSIM prompt the modelsim ini file will be modified with this line MY_VITAL MY_PATH You can easily add additional hierarchy to the path For example vmap MORE_VITAL MY_PATH more_path and_more_path B 394 ModelSim Variables ModelSim SE User s Manual Environment variables vmap MORE_VITAL SMY_PATH more_path and_more_path B Note The character in the examples above is Tcl syntax that precedes a variable The character is an escape character that keeps the variable from being evaluated during the execution of vmap Referencing environment variables within Model Sim There are two ways to reference environment variables within ModelSim Environment variables are allowed in a FILE variable being opened in VHDL For example entity test is end use std textio all architecture only of test is begin process FILE in_file text is in SENV_VAR_NAME begin wait end process end Environment variables may also be referenced from the ModelSim command line or
477. that match their libraries gt Note In order to conserve disk space ModelSim will read sdf files that were compressed using the standard unix gnu file compression algorithm The filename must end with the suffix Z for the decompress to work ModelSim SE User s Manual Standard Delay Format SDF Timing Annotation 12 325 Specifying SDF files for simulation Specifying SDF files for simulation ModelSim supports SDF versions 1 0 through 3 0 The simulator s built in SDF annotator automatically adjusts to the version of the file Use the following vsim CR 258 command line options to specify the SDF files the desired timing values and their associated design instances sdfmin lt instance gt lt filename gt sdftyp lt instance gt lt filename gt sdfmax lt instance gt lt filename gt Any number of SDF files can be applied to any instance in the design by specifying one of the above options for each file Use sdfmin to select minimum sdftyp to select typical and sdfmax to select maximum timing values from the SDF file Instance specification The instance paths in the SDF file are relative to the instance to which the SDF is applied Usually this instance is an ASIC or FPGA model instantiated under a testbench For example to annotate maximum timing values from the SDF file myasic sdf to an instance ul under a top level named testbench invoke the simulator as follows vsim sdfmax testbench ul mya
478. the ModelSim Tutorial or the Quick Start and are therefore familiar with the basic functionality of ModelSim The ModelSim Tutorial and Quick Start are both available from the ModelSim Help menu The ModelSim Tutorial is also available from the Support page of our web site www model com For installation instructions please refer to the Start Here for ModelSim guide that was shipped with the ModelSim CD Start Here may also be downloaded from our website www model com ModelSim SE User s Manual Introduction 1 17 Sections in this document Sections in this document In addition to this introduction you will find the following major sections in this document 2 Projects and system initialization 2 25 This chapter provides a definition of a ModelSim project and discusses the use of a new file extension for project files 3 Design libraries 3 41 To simulate an HDL design using ModelSim you need to know how to create compile maintain and delete design libraries as described in this chapter 4 VHDL Simulation 4 55 This chapter is an overview of compilation and simulation for VHDL within the ModelSim environment 5 Verilog Simulation 5 73 This chapter is an overview of compilation and simulation for Verilog within the ModelSim environment 6 Mixed VHDL and Verilog Designs 6 127 ModelSim Plus single kernel simulation SKS allows you to simulate designs that are written in VHDL and or Verilog This chap
479. the current simulation run Step Run gt Step step H step the current simulation to the next HDL statement see step CR 187 Step Over Run gt Step Over step over pp HDL statements are executed but treated as simple statements instead of entered and traced line by line see step CR 187 ModelSim SE User s Manual ModelSim Graphic Interface 8 167 Main window The Main window status bar Now 1 100 ns Delta 1 Env top m Fields at the bottom of the Main window provide the following information about the current simulation Description the current simulation time using the default resolution units see Simulating with the graphic interface 8 256 or a larger time unit if one can be used without a fractional remainder Delta the current simulation iteration number lt dataset name gt name of the current dataset item selected in the Structure window 8 210 Mouse and keyboard shortcuts in the Transcript and Source windows The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window They can also be used in editing the file displayed in the Source window and all Notepad windows enter the notepad command within ModelSim to open the Notepad editor Mouse UNIX Mouse Windows Result lt left button click gt move the insertion cursor lt left button press gt drag select l
480. the hold check This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments The tcheck_cond argument conditions the data_event for the hold check and the clk_event for the setup check This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments The delayed_clk argument is a net that is continuously assigned the value of the net specified in the clk_event The delay is non zero if the setup_limit is negative zero otherwise The delayed_data argument is a net that is continuously assigned the value of the net specified in the data_event The delay is non zero if the hold_limit is negative zero otherwise The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that may have negative timing constraints The model s logic should reference the delayed_clk and delayed_data nets in place of the normal clk and data nets This ensures that the correct data is latched in the presence of negative constraints The simulator automatically calculates the delays for delayed_clk and delayed_data such that the correct data is latched as long as a timing constraint has not been violated Srecovery reference event data_event removal_limit recovery_limit notifier tstamp_cond tcheck_cond delayed_reference delayed_data The recovery system task normally takes a recovery_limit as the third argument and an op
481. the item s label in the pathname pane or its waveform in the waveform pane then select Edit gt Signal Properties Wave window The resulting Wave Signal Properties dialog box has three tabs View Format and Compare e Signal Properties The View tab includes these options e Display Name Specifies a new name in the pathname pane for the selected signal Radix Specifies the Radix of the selected signal s Setting this to default causes the signal s radix to change whenever the default is modified using the radix command CR 166 Item values are not translated if you select Symbolic e Wave Color Specifies the waveform color Select a new color from the color palette or enter an X Windows color name e Name Color Specifies the signal name s color Select a new color from the color palette or enter an X Windows color name ModelSim SE User s Manual ModelSim Graphic Interface 8 231 Wave window Wave Signal Properties The Format tab includes these options e Format Literal Displays the waveform as a box containing the item value if the value fits the space available This is the only format that can be used to list a record Format Logic Displays values as U X 0 1 Z W L H or e Format Event Marks each transition during the simulation run 8 232 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Format Analog Step Interpolated Backst
482. the other version For example Using the 32 bit version of ModelSim vcom filel vhd vcom file2 vhd Next using the 64 bit version of ModelSim vcom refresh Do not compile the design with one version and then recompile it with the other If you do this ModelSim will remove the first module because it could be stale 3 52 Design libraries ModelSim SE User s Manual Importing FPGA libraries Importing FPGA libraries ModelSim includes an import wizard for referencing and using vendor FPGA libraries The wizard scans for and enforces dependencies in the libraries and determines the correct mappings and target directories A Important The FPGA libraries you import must be pre compiled Most FPGA vendors supply pre compiled libraries configured for use with ModelSim To import an FPGA library select Design gt Import Library Main window Import Library Wizard Follow the instructions in the wizard to complete the import ModelSim SE User s Manual Design libraries 3 53 3 54 Design libraries ModelSim SE User s Manual 4 VHDL Simulation Chapter contents Compiling VHDL designs 457 Creating a design library 2 457 Invoking the VHDL compiler 4 57 Dependency checking 2 1 4 57 Simulating VHDL designs rr Invoking the simulator from the Main window rn Invoking Code Coverage with vsim
483. the simulator If the compiler is allowed to analyze the entire design at once then it can determine the final values of parameters and treat them as constants in expressions thus generating more efficient code This is just one example of many other optimizations that require analysis of the entire design Compiling with fast The fast compiler option allows the compiler to propagate parameters and perform global optimizations A requirement of using the fast option is that you must compile the source code for your entire design in a single invocation of the compiler The following is an example invocation of the compiler and its resulting messages vlog fast cpu_rtl v Compiling module fp_unit Compiling module mult_56 Compiling module testbench Compiling module cpu Compiling module i_unit Compiling module mem_mux Compiling module memory32 Compiling module op_unit Top level modules testbench Analyzing design Optimizing 8 modules of which 6 are inlined Inlining module i_unit fast Inlining module mem_mux fast Inlining module op_unit fast 5 90 Verilog Simulation ModelSim SE User s Manual Compiling for faster performance Inlining module memory32 fast Inlining module mult_56 fast Inlining module fp_unit fast Optimizing module cpu fast Optimizing module testbench fast The Analyzing design message indicates that the co
484. ther project operations In addition to the four actions just discussed the following are common project operations Open an existing project When you leave a ModelSim session ModelSim will remember the last opened project You can reopen it for your next session by clicking Open Project in the Welcome to ModelSim dialog You can also open an existing project by selecting File gt Open gt Project Main window Close a project Select File gt Close gt Project Main window This closes the Project page but leaves the Library and Structure labeled Sim in the graphic above pages open in the workspace Delete a project Select File gt Delete gt Project Main window ModelSim SE User s Manual Projects and system initialization 2 33 Customizing project settings Customizing project settings Though the default project settings will work for many designs it is easy to customize the settings if needed You can change the compile order and set compiler options Changing compile order When you compile all files in a project ModelSim by default compiles the files in the order in which they were added to the project You have two alternatives for changing the default compile order 1 select and compile each file individually 2 specify a custom compile order using the Compile Order dialog gt Note Files can be displayed in the Project tab in alphabetical or compile order using the Sort by Alphabetical Order or Sort
485. this example in the READLINE or WRITELINE procedure call Providing stimulus You can stimulate and test a design by reading vectors from a file using them to drive values onto signals and testing the results A VHDL test bench has been included with the ModelSim install files as an example Check for this file lt install_dir gt modeltech examples stimulus vhd 4 64 VHDL Simulation ModelSim SE User s Manual Obtaining the VITAL specification and source code Obtaining the VITAL specification and source code VITAL ASIC Modeling Specification The IEEE 1076 4 VITAL ASIC Modeling Specification is available from the Institute of Electrical and Electronics Engineers Inc IEEE Customer Service 445 Hoes Lane Piscataway NJ 08855 1331 Tel 800 678 4333 908 562 5420 from outside the U S Fax 908 98 1 9667 home page http www ieee org VITAL source code The source code for VITAL packages is provided in the lt install_dir gt modeltech vhdl_src vital2 2b vital95 or vital2000 directories VITAL packages VITAL v3 0 accelerated packages are pre compiled into the ieee library in the installation directory B Note By default ModelSim is optimized for VITAL v3 0 You can however revert to VITAL v2 2b by invoking vsim CR 258 with the vital2 2b option and by mapping library vital to lt install_dir gt modeltech vital2 2b ModelSim SE User s Manual VHDL Simulation 4 65 ModelSim VITAL complian
486. tiation of Verilog design units vgencomp component declaration vgencomp CR 224 generates a component declaration according to these rules Generic clause A generic clause is generated if the module has parameters A corresponding generic is defined for each parameter that has an initial value that does not depend on any other parameters The generic type is determined by the parameter s initial value as follows Parameter value Generic type integer integer real real string literal string The default value of the generic is the same as the parameter s initial value Examples Verilog parameter VHDL generic parameter pl 1 3 pl integer 2 parameter p2 3 0 p2 real 3 000000 parameter p3 Hello p3 string Hello Port clause A port clause is generated if the module has ports A corresponding VHDL port is defined for each named Verilog port You can set the VHDL port type to bit std_logic or vl_logic If the Verilog port has a range then the VHDL port type is bit_vector std_logic_vector or vl_logic_vector If the range does not depend on parameters then the vector type will be constrained accordingly otherwise it will be unconstrained Examples Verilog port VHDL port input pl pl in std_logic output 7 0 p2 p2 out std_logic_vector 7 downto 0 output 4 7 p3 p3 out std_logic_vector 4 to 7 inout
487. til package Util package The util package is included in ModelSim versions 5 5 and later and serves as a container for various VHDL utilities The package is part of the modelsim_lib library which is located in the modelsim tree and mapped in the default modelsim ini file To access the utilities in the package you would add lines like the following to your VHDL code library modelsim_lib use modelsim_lib util all get_resolution get_resolution returns the current simulator resolution as a real number For example 1 femtosecond corresponds to le 15 Syntax resval get_resolution Returns Description The simulator resolution represented as a real Arguments None Related functions to_real 4 70 to_time 4 71 Example If the simulator resolution is set to 10ps and you invoke the command resval get_resolution the value returned to resval would be le 11 4 68 VHDL Simulation ModelSim SE User s Manual Util package init_signal_spy The init_signal_spy utility mirrors the value of a VHDL signal or Verilog register wire called the spy_object onto an existing VHDL signal or Verilog register called the dest_object This allows you to reference signals registers or wires at any level of hierarchy from within a VHDL architecture e g a testbench This system task works only in ModelSim versions 5 5 and newer Syntax init_signal_spy spy_object dest_obje
488. time hazard checking code Same as the hazards switch for the vlog command CR 250 Edit the Hazard B 398 variable in the modelsim ini file to set a permanent default 8 254 ModelSim Graphic Interface ModelSim SE User s Manual Compiling with the graphic interface Disable debugging data Models compiled with this option do not use any of the ModelSim debugging features Consequently your user will not be able to see into the model This also means that you cannot set breakpoints or single step within this code Don t compile with this option until you re done debugging Same as the nodebug switch for the vlog command CR 250 See Source code security and nodebug E 433 for more details Edit the NoDebug B 397 variable in the modelsim ini file to set a permanent default Convert Verilog identifiers to upper case Converts regular Verilog identifiers to uppercase Allows case insensitivity for module names Same as the u switch for the vlog command CR 250 Edit the UpCase B 398 variable in the modelsim ini file to set a permanent default Disable loading messages Disables loading messages in the Main window Same as the quiet switch for the vlog command CR 250 Edit the Quiet B 397 variable in the modelsim ini file to set a permanent default Show source lines with errors Causes the compiler to display the relevant lines of code in the transcript Same as the source switch for the vlog command CR 250 Edi
489. ting a VHDL design from a VCD file A VCD file intended for resimulation is created by capturing the ports of a VHDL design unit instance within a testbench or design The following discussion shows you how to prepare a VCD file for resimulation Note that the preparation varies depending on your design Also note that you cannot resimulate with VCD stimulus in a Verilog or mixed language design Extracting the proper stimulus for bidirectional ports To extract the proper stimulus for bidirectional ports the splitio command CR 185 must be used before creating the VCD file This splits bidirectional ports into separate signals that mirror the output driving contributions of their related ports By recording in the VCD file both the resolved value of a bidirectional port and its output driving contribution an appropriate stimulus can be derived by vsim vedread The splitio command CR 185 operates on a bidirectional port and creates a new signal having the same name as the port suffixed with __o This new signal must be captured in the VCD file along with its related bidirectional port See the description of the splitio command CR 185 for more details gt Note When using the splitio command in conjunction with VCD files be aware that VCD file output will vary between a model coded in VHDL and the same model coded in Verilog with timing wrapped in VHDL The difference occurs because splitio generates Extended VCD stimulus files and the Ex
490. tional notifier as the fourth argument By specifying a limit for both the third and fourth arguments the recovery timing check is transformed into a combination removal and recovery timing check similar to the recrem timing check The only difference is that the removal_limit and recovery_limit are swapped The following system tasks are Verilog XL system tasks that are not implemented in ModelSim Verilog but have equivalent simulator commands 5 102 Verilog Simulation ModelSim SE User s Manual System Tasks Sinput filename This system task reads commands from the specified filename The equivalent simulator command is do lt filename gt list hierarchical_name This system task lists the source code for the specified scope The equivalent functionality is provided by selecting a module in the graphic interface Structure window The corresponding source code is displayed in the source window Sreset This system task resets the simulation back to its time 0 state The equivalent simulator command is restart Srestart filename This system task sets the simulation to the state specified by filename saved in a previous call to save The equivalent simulator command is restore lt filename gt Ssave filename This system task saves the current simulation state to the file specified by filename The equivalent simulator command is checkpoint lt filename gt Sscope hierarchical_name This system task sets the
491. tions for displaying design units e Update Reloads the library in case any of the design units were modified outside of the current session e g by a script or another user 3 46 Design libraries ModelSim SE User s Manual Working with design libraries Assigning a logical name to a design library VHDL uses logical library names that can be mapped to ModelSim library directories By default ModelSim can find libraries in your current directory assuming they have the right name but for it to find libraries located elsewhere you need to map a logical library name to the pathname of the library You can use the GUI a command or a project to assign a logical name to a design library Library mappings with the GUI To associate a logical name with a library select Design gt Browse Libraries Main window This brings up a dialog box that allows you to view add edit and delete mappings as shown below Library Browser OF ES Show all Visible Libraries 3 ieee maps to MODEL_TECH ieee mac_portable maps to MODEL_TECH mgc_portable std maps to MODEL_TECH std std_developerskit maps to MODEL_TECH std_developerskit Synopsys maps to M0DEL_TECH synopsys verilog maps to MODEL_TECH verilog work maps to mixed local directory el e el The Library Browser dialog box includes these options e Show Choose the mapping and library scope to view from the drop down list e Lib
492. to nomgc and use the lic_plus option from the command line vsim will search only for MTI SE PLUS licenses Unix To start the license manager daemon place the license file in the lt install_dir gt modeltech lt platform gt directory and enter the following commands cd lt install_dir gt modeltech lt platform gt lmgrd c license dat gt amp report log D 418 Using the FLEXIm License Manager ModelSim SE User s Manual Starting the license server daemon where lt platform gt can be sunos5 sunos5v9 hp700 hppa64 rs6000 rs64 or linux This can be done by an ordinary user you should not be logged in as root Windows To start the license manager daemon in Windows place the license file in the modeltech installation directory and enter the following commands cd lt install_dir gt modeltech win32 imgrd app c license dat Automatic start at boot time Unix You can cause the license manager daemon to start automatically at boot time by adding the following line to the file etc rc boot or to etc rc local lt install_dir gt modeltech lt platform gt lmgrd c lt install_dir gt license dat Windows You can use the FLEXIm Control Panel to enact an automatic start See the FLEXIm End User s Manual for more information What to do if another application uses FLEXIm If you have other applications that use FLEXIm you can handle any conflict in one of the following ways Case 1 All the lice
493. to use embedded software development ESD Software Mentor Graphics or its authorized distributor grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate or incorporate copies of Mentor Graphics real time operating systems or other ESD Software except those explicitly granted in this section into your products without first signing a separate agreement with Mentor Graphics for such purpose 3 BETA CODE ModelSim SE User s Manual License Agreement 463 3 1 Portions or all of certain Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics ma
494. transcript as a macro DO file Saved transcript files can be used as macros DO files See the do command CR 104 for more information ModelSim SE User s Manual ModelSim Graphic Interface 8 159 Main window The Main window menu bar The menu bar at the top of the Main window lets you access many ModelSim commands and features The menus are listed below with brief descriptions of each command s use l ModelSim File Edit Design View Project Run Compare Macro Options Window Help os SB y E File menu New provides three options Folder create a new folder in the current directory Source create a VHDL Verilog or Other source file Project create a new project Open provides three options File open the selected hdl file Project open the selected mpf project file Dataset open the specified logfile and assign it the specified dataset name Close provides three options Project close the currently open project file Dataset close the specified dataset Delete provides one option Project delete the selected mpf project file Change Directory change to a different working directory Save Transcript save the current contents of the transcript window to the file indicated with a Save Transcript As selection this selection is not initially available because the transcript is written to the transcript file by default see Saving
495. ts 8 205 for details Design menu Browse Libraries browse all libraries within the scope of the design see also Managing library contents 3 44 Create a New create a new library or map a library to a new name see Creating Library a library 3 43 Import Library import FPGA libraries see Importing FPGA libraries 3 53 for details Compile compile HDL source files into the current project s work library Load Design initiate simulation by specifying the top level design unit in the Design tab specify HDL specific simulator settings with the VHDL and Verilog tabs specify the library to search for design units instantiated from Verilog with the Libraries tab specify settings relating to the annotation of design timing with the SDF tab End Simulation end the simulation returns to the ModelSim command line ModelSim SE User s Manual ModelSim Graphic Interface 8 161 Main window View menu All open all ModelSim windows Hide Show hide or show the workspace Workspace Layout Style provides five options Default restore the window layout to that used for versions 5 5 and later Classic restore the window layout to that used in versions prior to 5 5 Cascade Cascade all open windows Horizontal Tile all open windows horizontally Vertical Tile all open windows vertically Source open and or view the Source window 8
496. ts of a Verilog design unit invisible vlog nodebug pli prevents the use of PLI functions to interrogate the module for information vlog nodebug ports pli combines the functions of nodebug ports and nodebug pli or pli ports gt Note Don t use the ports switch on a design without hierarchy or on the top level of a hierarchical design if you do no ports will be visible for simulation To properly use the switch compile all lower portions of the design with nodebug ports first then compile the top level with nodebug alone Also note the pli switch will not work with vcom the VHDL compiler PLI functions are valid only for Verilog design units ModelSim SE User s Manual Tips and Techniques E 433 Saving and viewing waveforms Saving and viewing waveforms You can run vsim as a batch job but view the resulting waveforms later 1 When you invoke vsim the first time use the wlf option to rename the logfile and redirect stdin to invoke the batch mode The command should look like this vsim wlf wavesavl wlf counter lt command do Within your command do file use the log command CR 131 to save the waveforms you want to look at later run the simulation and quit When vsim runs in batch mode it does not write to the screen and can be run in the background 2 When you return to work the next day after running several batch jobs you can start up vsim in its viewing mode with this command and th
497. ual ModelSim Shortcuts C 409 Mouse action Wave window mouse and keyboard shortcuts The following mouse actions and keystrokes can be used in the Wave window Result lt control left button click on a scroll arrow gt scrolls window to very top or bottom vertical scroll or far left or right horizontal scroll lt middle mouse button click in scroll bar trough gt UNIX only Keystroke scrolls window to position of click Action il or zoom in oOo zoom out for F zoom full mouse pointer must be over the the cursor or waveform panes lor L zoom last ror R zoom range lt arrow up gt scroll waveform display up by selecting the item above the currently selected item lt arrow down gt scroll waveform display down by selecting the item below the currently selected item lt arrow left gt scroll waveform display left lt arrow right gt scroll waveform display right lt page up gt scroll waveform display up by a page lt page down gt scroll waveform display down by a page lt tab gt search forward right to the next transition on the selected signal finds the next edge lt shift tab gt search backward left to the previous transition on the selected signal finds the previous edge lt control f gt Windows lt control s gt UNIX open the find dialog box searches within the spec
498. uble click on the error in the Main window and the error is highlighted and ready rori xorg piri mani o inl gt a to edit in the Source window inZ gt b outl gt xorl_out woman eo someras ee ms ModelSim SE User s Manual ModelSim Graphic Interface 8 251 Compiling with the graphic interface Setting default compile options Select Options gt Compile Main window to bring up the Compiler Options dialog box shown below OK accepts the changes made and closes the dialog box Apply makes the changes with the dialog box open so you can test your settings Cancel closes the dialog box and makes no changes The options found on each page of the dialog box are detailed below Changes made in the Compiler Options dialog box become the default for all future simulations VHDL compiler options page Compiler Options VHDL Verilog Use 1993 Language Syntax T Disable loading messages I Don t put debugging info in library F Show source lines with errors IV Use explicit declarations only Check for Flag Warnings On T Synthesis Y Unbound component IV Vital Compliance M Process without a WAIT statement Dptimize for M Null Range I StdLogicl 164 IV No space in time literal e g 5ns IV Vital IV Multiple drivers on unresolved signals OK Cancel Apply Use 1993 language syntax Specifies the use of VHDL93 during compilation The 1987 standard is the d
499. ulogic vl_ulogic_vector or their subtypes The port clause may have any mix of these types e The generics are of type integer real time physical enumeration or string String is the only composite type allowed Port associations may be named or positional Use the same port names and port positions that appear in the entity Named port associations Named port associations are not case sensitive unless a VHDL port name is an extended identifier 1076 1993 If the VHDL port name is an extended identifier the association is case sensitive and the VHDL identifier s leading and trailing backslashes are removed before comparison Generic associations are provided via the module instance parameter value list List the values in the same order that the generics appear in the entity The defparam statement is not allowed for setting generic values An entity name is not case sensitive in Verilog instantiations The entity default architecture is selected from the work library unless specified otherwise Verilog does not have the concept of architectures or libraries so the escaped identifier is employed to provide an extended form of instantiation mylib entity arch ul a b c mylib entity ul a b c entity arch ul a b c If the escaped identifier takes the form of one of the above and is not the name of a design unit in the work library then the instantiation is broken down as follows e library mylib e de
500. ulse_e_style_onevent This option selects the on event style of propagating pulse errors see pulse_e lt percent gt A pulse error propagates to the output as an X and the on event style is to schedule the X to occur at the same time and for the same duration that the pulse would have occurred if it had propagated through normally The on event style is the default for propagating pulse errors sdf_nocheck_celltype By default the SDF annotator checks that the CELLTYPE name in the SDF file matches the module or primitive name for the CELL instance It is an error if the names do not match The sdf_nocheck_celltype option disables this error check sdf_verbose This option displays a summary of the design objects annotated for each SDF file Htransport_int_delays By default interconnect delays operate in inertial mode pulses smaller than the delay are filtered The transport_int_delays option selects transport mode with pulse control for single source nets one interconnect path In transport mode narrow pulses are propagated through interconnect delays This option works independent from multisource_int_delays 5 88 Verilog Simulation ModelSim SE User s Manual Simulation transport_path_delays By default path delays operate in inertial mode pulses smaller than the delay are filtered The transport_path_delays option selects transport mode for path delays In transport mode narrow pulses are propagated through
501. used setting to O results in no limit WLFTimeLimit WLF file time limit limits WLF file by time as closely as possible to the specified amount of time If both time and size limits are specified the most restrictive is used setting to 0 results in no limit ModelSim SE User s Manual ModelSim Variables B 401 Preference variables located in INI files Imc Logic Modeling variables Logic Modeling SmartModels and hardware modeler interface ModelSim s interface with Logic Modeling s SmartModels and hardware modeler are specified in the Imc section of the INI MPF file for more information see VHDL SmartModel interface 14 354 and VHDL Hardware Model interface 15 364 respectively Spaces in path names For the Src_Files and Work_Libs variables each element in the list is enclosed within curly braces This allows spaces inside elements since Windows allows spaces inside path names For example a source file list might look like Src_Files MODELSIM_PROJECT counter v MODELSIM_PROJECT tb counter v Where the file tb counter v contains a space character between the b and c Setting variables in INI files Edit the initialization file directly with any text editor to change or add a variable The syntax for variables in the file is lt variable gt lt value gt Comments within the file are preceded with a semicolon gt Note The vmap command CR 257 automatical
502. usion filter files 2 lt e e s 10 299 Syntax o s e so o e o 10 299 Arguments 2 s o o owo we e e we 10 299 Example e s e s e so s e s 10 299 Default filter file 2 aa aaa a 10 299 Code Coverage preference variables 10 300 Code Coverage commands 10 300 Code Coverage gives you graphical and report file feedback on how your source code is being executed This integrated feature provides three important benefits to the ModelSim user 1 Because it s integrated into the ModelSim engine it is totally non intrusive it doesn t require instrumented HDL code as do third party code coverage products 2 It has very little impact on simulation performance typically less than 5 3 There is no need to recompile to obtain code coverage statistics ModelSim version 5 3 and later libraries fully support this feature ModelSim SE User s Manual Code Coverage 10 291 Enabling Code Coverage Enabling Code Coverage To enable code coverage begin simulation with the coverage option to the vsim command CR 258 With coverage enabled ModelSim counts how many times each executable line is executed during simulation number of hits The information is then displayed in the coverage_source and coverage_summary windows Or you can save the information in several different text reports see below for details Note To view the maximum number of lines while doing co
503. ustomizing project settings 2 34 Changing compile order 2 34 Setting compiler options 2 35 Accessing projects from the command line 2 36 System initialization A 2 37 Files accessed during startap 2 37 Environment variables accessed dadig aie 2 38 Initialization sequence 2 39 3 Design libraries 3 41 Design library contents 3 42 Design library types 3 42 Working with design libraries 3 43 Managing library contents 3 44 Assigning a logical name to a design ls 3 47 Moving a library 3 49 Specifying the resource libraries 3 50 Predefined libraries 3 50 ModelSim SE User s Manual Table of Contents 3 Altemate IEEE libraries supplied o o o e s 2 ee 0 0540 00 0 a VITAL 2000 library lt lt eor s oe mocok o eee E a e a Sl Reb ilding supplied libraries o eo soso lt 60 ss 3 91 Regenerating your design libraries 2 2 a ee 3 91 Verilog resource libraries A GBS Maintaining 32 bit and 64 bit versions in n the same Notre O E Iniporting FPGA Dbra es sos e s a sowo a ese O 4 VHDL Simulation 4 55 Compiling VHDL designs a a a a 497 Invoking the VHDL compiler o o sa sec ss seoa saa aa soo 457 Dependener checking lt eos toroa a ate a a A Simulating VHDL designs O lo Invoking the simulator from the Main window koek ok oh hob 2 e 2 4 24608 Invoking Code Coverage with vsim ee ee eee 4
504. ute Macro Execute Old PE Macro Convert Old PE Macro Tcl Debugger TclPro Debugger 1 Launch TclPro Debugger 2 Launch ModelSim 3 Select Macro gt TclPro Debugger Main window This will connect ModelSim to the Scriptics TclPro Debugger 8 274 ModelSim Graphic Interface ModelSim SE User s Manual ModelSim tools The GUI Expression Builder The GUI Expression Builder is a feature of the Wave and List Signal Search dialog boxes and the List trigger properties dialog box It aids in building a search expression that follows the GUI_expression_format CR 297 To locate the Builder select Edit gt Search List or Wave window e select the Search for Expression option in the resulting dialog box e select the Builder button Expression Builder TT Expression Builder Insert Selected Signal EN l zA o lel 0 sa xf 2 sj 2 7 The Expression Builder dialog box provides an array of buttons that help you build a GUI expression For instance rather than typing in a signal name you can select the signal in the associated Wave or List window and press Insert Reference Signal in the Expression Builder The result will be the full signal name added to the expression field All Expression Builder buttons correspond to the Expression syntax CR 302 ModelSim SE User s Manual ModelSim Graphic Interface 8 275 ModelSim tools To search for when a signal r
505. ve fileroot wave global vsimPriv set n 1 set fileld open windowSet_ fileroot do w 755 foreach w vsimPriv WaveWindows echo Saving wm title w set filename fileroot n do write format wave window w filename puts fileld wm title w wm title w puts fileId wm geometry w wm geometry Sw puts fileId mtiGrid_colconfig w grid name width mtiGrid_colcget w grid name width puts fileId mtiGrid_colconfig w grid value width mtiGrid_colcget w grid value width flush fileld incr n ModelSim SE User s Manual Tcl and ModelSim 16 383 Tcl examples if catch glob fileroot n 9 do foreach f lsort glob fileroot n 9 do echo Removing f exec rm Sf Provide file root argument and load_wave restores all saved widows Default file root is wave proc load_wave fileroot wave global vsimPriv foreach f lsort glob fileroot 1 9 do echo Loading f view new wave do f if file exists windowSet_S fileroot do do windowSet_ fileroot do 16 384 Tcl and ModelSim ModelSim SE User s Manual A Technical Support Updates and Licensing Appendix contents Technical support electronic A 386 Technical support telephone A 387 Technical support other channels A 387 Updates o 4 s 8h 4 8 e e we ee amp e po e A 388 Online References 2 2
506. vider Properties from the pop up menu To delete a divider Select the divider and either press the lt Delete gt key on your keyboard or select Delete from the pop up menu ModelSim SE User s Manual ModelSim Graphic Interface 8 227 Wave window Splitting Wave window panes The pathnames values and waveforms window panes of the Wave window display can be split to accommodate signals from one or more datasets Selecting File gt New Window Pane Wave window creates a space below the selected waveset and makes the new window pane the selected pane The selected wave window pane is indicated by a white bar along the left margin of the pane In the illustration below the Wave window is split showing the current active simulation with the prefix sim and a second view mode dataset with the prefix testl For more information on viewing multiple simulations see Chapter 7 Datasets saved simulations and virtuals wave default Al x File Edit Cursor Zoom Compare Bookmark Format Window oho 528 RK HA QQQQ EF ELELELM Jade im proc clk im proc rdy in proc addr 00000001 im proc ru so im proc strb sto im proc data 2222222222222222 i l 3 Ss 3 i test top clk test top prwy test1 top pstrb g s ME wk Ons to 876 ns 8 228 ModelSim Graphic Interface ModelSim SE User s Manual Wave window Combining items in the Wave window
507. w 8 184 B Note List window format files are design specific use them only with the design you were simulating when they were created If you try to use the wrong format file ModelSim will advise you of the HDL items it expects to find Editing and formatting HDL items in the List window Once you have the HDL items you want in the List window you can edit and format the list to create the view you find most useful See also Adding HDL items to the List window 8 180 To edit an item Select the item s label at the top of the List window or one of its values from the listing Move copy or remove the item by selecting commands from the List window Edit menu 8 176 menu You can also click drag to move items within the window to select several contiguous items click drag to select additional items to the right or the left of the original selection to select several items randomly Control click to add or subtract from the selected group to move the selected items re click on one of the selected items hold and drag it to the new location ModelSim SE User s Manual ModelSim Graphic Interface 8 181 List window To format an item Select the item s label at the top of the List window or one of its values from the listing then select Prop gt Signal Props List window The resulting Modify Signal Properties dialog box allows you to set the item s label label width triggering and radix MEIN Si
508. w itself File menu Open Dataset open a dataset New Divider insert a divider at the current location New Group setup a new group element a container for other items that can be moved cut and pasted like other objects NOT CURRENTLY IMPLEMENTED Save Format save the current Wave window display and signal preferences toa DO macro file running the DO file will reformat the Wave window to match the display as it appeared when the DO file was created Load Format run a Wave window format DO file previously saved with Save Format Page Setup setup page for printing options include paper size margins label width cursors color scaling and orientation Print Windows only Print Postscript send the contents of the Wave window to a selected printer options include All signals print all signals Current View print signals in current view for the time displayed Selected print all or current view signals for user designated time save or print the waveform display as a Postscript file options include All Signals print all signals Current View print signals in current view for the time displayed Selected print all or current view signals for user designated time New Window split the pathname values and waveform window panes to provide Pane room for a new waveset Remove remove window split and active waveset Window Pane 8 220 Model
509. wable time range e Custom Print the specified signals for a user designated From and To time Setup button See Printer Page Setup 8 248 Printing on Windows platforms Select File gt Print Wave window to print all or part of the waveform in the current Wave window or save the waveform as a printer file a Postscript file for Postscript printers Printing and writing preferences are controlled by the dialog box shown below MLINKAGEMHP LaserJet 5L El Printer e Name Choose the printer from the drop down menu Set printer properties with the Properties button Status Indicates the availability of the selected printer e Type Printer driver name for the selected printer The driver determines what type of file is output if Print to file is selected 8 246 ModelSim Graphic Interface ModelSim SE User s Manual Wave window e Where The printer port for the selected printer e Comment The printer comment from the printer properties dialog box e Print to file Make this selection to print the waveform to a file instead of a printer The printer driver determines what type of file is created Postscript printers create a Postscript ps file non Postscript printers create a prn or printer control language file To create an encapsulated Postscript file eps use the File gt Print Postscript menu selection Signal Selection e All signals Print all signals e Current View Print signals in curr
510. width 1 0 p4 p4 inout std_logic_vector 6 134 Mixed VHDL and Verilog Designs ModelSim SE User s Manual VHDL instantiation of Verilog design units Configuration declarations are allowed to reference Verilog modules in the entity aspects of component configurations However the configuration declaration cannot extend into a Verilog instance to configure the instantiations within the Verilog module VCD output When creating a VCD file for designs that have bi directional ports you first have to use the splitio command see Extracting the proper stimulus for bidirectional ports 13 344 Be aware that VCD file output will vary between a design coded in VHDL and the same design coded in Verilog with timing wrapped in VHDL The difference occurs because splitio generates Extended VCD stimulus files and the Extended VCD format is supported only for pure VHDL designs ModelSim SE User s Manual Mixed VHDL and Verilog Designs 6 135 Verilog instantiation of VHDL design units Verilog instantiation of VHDL design units You can reference a VHDL entity or configuration from Verilog as though the design unit is a module of the same name in lower case VHDL instantiation criteria A VHDL design unit may be instantiated from Verilog if 1t meets the following criteria e The design unit is an entity architecture pair or a configuration declaration e The entity ports are of type bit bit_vector std_ulogic std_ulogic_vector vl_
511. window menu bar The coverage_summary window has three menus File Coverage and Report Brief descriptions of each command are given below File menu Open gt Coverage gt Merge Coverage Merges saved reports into the current analysis See Merging coverage report files 10 298 for more details Open gt Coverage gt Apply a Previous Clears the current coverage statistics and loads a previously saved coverage report Coverage Open gt Load a New Loads an exclusion filter file See Exclusion filter files 10 Filter 299 for more details Save gt Line Coverage Saves a textual report of the source file summary data and details for each executable line in the file Save gt Current Filter Saves the current exclusion filter to a file that can be reloaded later See Exclusion filter files 10 299 for more details Close Coverage menu Clear Current Coverage Closes the view_coverage window Clears the current coverage statistics Revert To Initial Filter Returns filtering to the default exclusion filter file Clear out Current Filter Clears active exclusion filters Disable Enable Filtering Disables Enables filtering Acts as a toggle 10 294 Code Coverage ModelSim SE User s Manual The coverage_summary window Report menu Save Summary Coverage Saves a textual report of the summary lines hits and percentages for each source file
512. wing performance tools e Performance Analyzer 9 281 Identifies areas in your simulation where performance can be improved gt Note Performance Analyzer will not operate on Windows 95 e Code Coverage 10 291 Gives you graphical and report file feedback on how the source code is being executed ModelSim s graphic interface While your operating system interface provides the window management frame ModelSim controls all internal window features including menus buttons and scroll bars The resulting simulator interface remains consistent within these operating systems e SPARCstation with OpenWindows OSF Motif or CDE e IBM RISC System 6000 with OSF Motif e Hewlett Packard HP 9000 Series 700 with HP VUE OSF Motif or CDE e Linux Red Hat v 6 0 or later with KDE or GNOME e Microsoft Windows 95 98 ME NT 2000 Because ModelSim s graphic interface is based on Tcl TK you also have the tools to build your own simulation environment Preference variables and configuration commands Preference variables located in INI files B 396 and Graphic interface commands 8 277 give you control over the use and placement of windows menus menu options and buttons See Tcl and ModelSim 16 369 for more information on Tcl For an in depth look at ModelSim s graphic interface see Chapter 8 ModelSim Graphic Interface 1 16 Introduction ModelSim SE User s Manual Standards supported Standards supported ModelSi
513. x display The default for dataset prefix viewing is set with a variable in pref tcl PrefMain DisplayDatasetPrefix Setting the variable to 1 will display the prefix setting it to 0 will not It is set to 1 by default Either edit the pref tcl file directly or use the Options gt Edit Preferences Main window command to change the variable value Additionally you can restrict display of the dataset prefix if you use the environment nodataset command to view a dataset To display the prefix use the environment command CR 114 with the dataset option you won t need to specify this option if the variable noted above is set to 1 The environment command line switches override the pref tcl variable ModelSim SE User s Manual Datasets saved simulations and virtuals 7 143 Virtual Objects User defined buses and more Virtual Objects User defined buses and more Virtual objects are signal like or region like objects created in the GUI that do not exist in the ModelSim simulation kernel Beginning with release 5 3 ModelSim supports the following kinds of virtual objects e Virtual signals 7 144 e Virtual functions 7 145 e Virtual regions 7 146 e Virtual types 7 146 Virtual objects are indicated by an orange diamond as illustrated by BUSI below wave default Iof x File Edit Cursor Zoom Compare Bookmark Format Window ohne 2M RA eA QQQQi E ES Jade wl top clk top prwy top pstrb top prd
514. xd lt buffer_rxd 111 rxd_active lt buffer_rxd when 10 gt rxd lt l buffer rxd 11 rxd_active lt l when Ol gt rxd lt 11 amp buffer_rxd l rxd_active lt l when OO gt rxd lt 111 amp buffer_rxd rxd_active lt l when others gt rxd lt XXXX rxd_active lt X end case END PROCESS You can skip to missed lines using the Edit gt Previous Coverage Miss and Edit gt Next Coverage Miss commands or by pressing lt Shift gt lt Tab gt previous miss or Tab next miss Excluding lines and files There may be certain lines or files that you do not want to include in the code coverage statistics In the coverage_source window click your right mouse button in the far left column the one with the hit counts to display the following context menu The menu has the following options Exclude Coverage Line F s aa ao Exclude Entire File Excludes the specified line number from the A code coverage statistics Do Not Exclude Coverage Line 73 Do Not Exclude Entire File Exclude Entire File Eepe Excludes the entire file from the code coverage statistics 10 296 Code Coverage ModelSim SE User s Manual The coverage_source window Do Not Exclude Coverage Line Adds the specified line number back into the code coverage statistics Do Not Exclude Entire File Adds the file back into the code coverage statistics Any exclusi
515. y ftop paddr 00000010 10 1001 top pdata PH BUSI 011 1 LLI a l 2 top srw 0 00000010 ji Y ji 1 top sstrb 1 0 4top srdy 1 Hopestw 0 Ma e a 50 ns to 928 ns Virtual signals Virtual signals are aliases for combinations or subelements of signals written to the logfile by the simulation kernel They can be displayed in the Signals List and Wave windows accessed by the examine command and set using the force command Virtual signals can be created via a menu in the Wave and List windows Edit gt Combine or with the virtual signal command CR 245 Virtual signals can also be dragged and dropped from the Signals window to the Wave and List windows Virtual signals are automatically attached to the design region in the hierarchy that corresponds to the nearest common ancestor of all the elements of the virtual signal The virtual signal command has an install lt region gt option to specify where the virtual signal should be installed This can be used to install the virtual signal in a user defined region in 7 144 Datasets saved simulations and virtuals ModelSim SE User s Manual Virtual Objects User defined buses and more order to reconstruct the original RTL hierarchy when simulating and driving a post synthesis gate level implementation A virtual signal can be used to reconstruct RTL level design buses that were broken down during synthesis The virtual hid
516. y choose not to release commercially in any form 3 2 If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements 3 3 You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceives or makes during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this subsection shall survive termination or expiration of this Agreement 4 RESTRICTIONS ON USE You may copy Software only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and s
517. y of the selected item ModelSim SE User s Manual ModelSim Graphic Interface 8 211 Structure window Expand All expand the hierarchy of all items that can be expanded Collapse All collapse the hierarchy of all expanded items Find Window menu find the specified text string within the structure tree see Finding items in the Structure window 8 212 Initial Layout restore all windows to the size and placement of the initial full screen layout Cascade cascade all open windows Tile Horizontally tile all open windows horizontally Tile Vertically tile all open windows vertically Icon Children icon all but the Main window Icon All icon all windows Deicon All deicon all windows Customize use the The Button Adder 8 269 to define and add a button to either the tool or status bar of the specified window lt window_name gt list of the currently open windows select a window name to switch to or show that window if it is hidden when the source window is available the source file name is also indicated open additional windows from the View menu 8 162 in the Main window or use the view command CR 226 Finding items in the Structure window The Find dialog box allows you to search for text strings in the Structure window Select Edit gt Find Structure window to bring up the Find dialog box Enter the value to search for in
518. you create a project see Getting started with projects 2 28 ModelSim automatically creates a working design library If you don t create a project you need to create a working design library before you run the compiler This can be done from either the command line or from the ModelSim graphic interface From the ModelSim prompt or a UNIX DOS prompt use this vlib command CR 249 vlib lt directory_pathname gt To create a new library with the ModelSim graphic interface select Design gt Create a New Library Main window This brings up a dialog box that allows you to specify the library name and its logical mapping Create a New Library OF x Create anew library and a logical mapping to it Ca map to an existing library Library Name mo work Browse The Create a New Library dialog box includes these options Create a new library and a logical mapping to it Type the new library name into the Library Name field This creates a library sub directory in your current working directory initially mapped to itself Once created the mapped library is easily remapped to a different library Create a map to an existing library Type the new library name into the Library Name field then type into the Library Maps to field or Browse to select a library name for the mapping Library Name Type the new library name into this field ModelSim SE User s Manual Design libraries 3 43 Worki
519. you receive the error Exec format error when the simulator is trying to load a PLI VPI library then you have most likely built under 11 0 and specified the Ic option Just rebuild without lc or rebuild on an HP UX 10 0 machine 64 bit HP platform On a 64 bit HP system use the following cc compiler commands to prepare PLI VPI code for dynamic linking with ModelSim cc v DA2 0W O I lt install_dir gt modeltech include c app c ld G app o 0o app so IBM RS 6000 platform ModelSim loads shared libraries on the IBM RS 6000 workstation The shared library must import ModelSim s PLI VPI symbols and it must export the PLI or VPI application s initialization function or table ModelSim s export file is located in the ModelSim installation directory in rs6000 mti_exports If your PLI VPI application uses anything from a system library you 1l need to specify that library when you link your PLI VPI application For example to use the standard C library specify Ic to the Id command The resulting object must be marked as shared reentrant using these gcc or ec compiler commands for AIX 4 x gcc compiler gcc c I lt install_dir gt modeltech include app c ld o app sl app o bE app exp bI lt install_dir gt modeltech rs6000 mti_exports bM SRE bnoentry lc ModelSim SE User s Manual Verilog Simulation 5 113 Using the Verilog PLI VPI cc compiler cc c I lt install_dir gt modeltech inclu
520. ything in the daemon options file described in the following section Format of the daemon options file You can customize your ModelSim licensing with the daemon options file This options file allows you to reserve licenses for specified users or groups of users to determine which users have access to ModelSim software to set software time outs and to log activity to an optional report writer RESERVE Ensures that ModelSim will always be available to one or more users on one or more host computers INCLUDE Allows you to specify a list of users who are allowed access to the ModelSim software EXCLUDE Allows you to disallow access to ModelSim for certain users GROUP Allows you to define a group of users for use in the other commands NOLOG Causes messages of the specified type to be filtered out of the daemon s log output To use the daemon options capability you must create a daemon options file and list its pathname as the fourth field on the line that begins with DAEMON modeltech A daemon options file consists of lines in the following format RESERVE number feature USER HOST DISPLAY GROUP name INCLUDE feature USER HOST DISPLAY GROUP name EXCLUDE feature USER HOST DISPLAY GROUP name GROUP name lt list_of_users gt NOLOG IN OUT DENIED QUEUED REPORTLOG file D 420 Using the FLEXIm License Manager ModelSim SE User s Manual Format of the daemon options file Lines begi

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