Real Time Video Engine 2.0 Implementation in Kintex-7
Contents
1. Import 7 Select gt Create new projects from an archive file or directory _ Select an import source wv General Archive File Existing Projects into Workspace G File System S Preferences gt amp C C gt amp Remote Systems gt Run Debug gt Team sk e ee asi X1091_07_031213 Figure 7 Populate the RTVE SDK Workspace 6 Under Import Projects select the Select root directory radio button and then use the Browse button to locate the release rtve 2 0 kc705 4x sw sw directory 7 SDK identifies three projects and automatically selects each for importing as shown in Figure 8 Click Finish to import the three projects XAPP1091 v1 0 1 March 18 2014 www xilinx com Build the RTVE 2 0 Project XILINX E Import Import Projegts Select a directory to search for existing Eclipse projects Select root directory proj bfeng rtve k7 rtve2 0 x4 release rtv Browse O Select archive file Projects kc705_4x_bsp proj bfeng rtve k7 rtve2 0 x4 release rtve_2_ Select All Vl ke 70S 4x hw proj bfeng rtve k7 rtve2 0 x4 release rmtve_ 2 Deselect All kc705_rtve proj bfeng rtve k7 rtve2 0 x4 release rtve_2 0 kh Refresh Loo o o S 8 86 6COUmUCUCGMUMUMLMLMLlLUmD O Copy projects into workspace Working sets O Add project to working sets X1091_08_031213 Figure 8 amp Import All Three RTVE 2 0 Software Projects At this point SDK locates2. all drivers and builds the software 8 In a successful build the Microblaze software reve _kc705 el1f is generated in the release rtve 2 0 kc705 4x sw sw SDK Workspace Debug directory Table 2 provides a checklist for the reference design Table 2 Design Checklist Parameter Desription Simulation Functional simulation performed Y Timing simulation performed N Testbench used for functional and timing Functional Only simulations Testbench format VHDL Simulator software version used Modelsim 6 6d XAPP1091 v1 0 1 March 18 2014 www xilinx com 9 Build the RTVE 2 0 Project Table 2 Design Checklist Cont d amp XILINX Parameter Desription SPICE IBIS simulations NA Implementation Synthesis software tools version used ISE 14 4 Implementation software tools versions used ISE 14 4 Static timing analysis performed Y Hardware Verification Hardware verified Y Hardware platform used for verification KINTEX 7 KC705 plus TED TB TB FMCH 3GSDI2A and TB FMCL HDMI cards XAPP1091 v1 0 1 March 18 2014 Table 3 provides RTVE 2 0 resource breakdown values Table 3 Resource Utilization BRAM FIFO 36 bit FF LUT DSP OSVP Core OSVP2 2 input channels 108 22240 18412 102 OSVP4 4 input channels 192 41398 34623 204 OSVP8 8 input channels 379 80500 69406 408 Supporting IP SDI Inp
3. box also provides all input and output format information System Status Version V2 0 006 IP Address Output Format HDMI 1 Status 50 SDI 1 Status 1920x1080 SDI 2 Status 192 Ox xl Q 08 0 I50 SDI 3 Status 1 ae oie Ox gt 080 T50 SDI 4 Status 192 80 59 1i F X1091_11_031213 Figure 11 System Status Text Overlay Box To open the RTVE 2 0 control GUI see Figure 12 open a web browser type the IP address in the address bar and press Enter XAPP1091 v1 0 1 March 18 2014 www xilinx com 14 Demonstration Setup XILINX A Si 2 rat pif e 1 Freeze Image Show Text Overlay Snapshot Deinterlacer aS SO 4 a Format 1320 Frame Rate Freeze Colour Space Oe Show Text Overlay p ae Snapshot Desnterlacer Use Motion 1020x1080 P50 1250x720 P50 Use Angles 1920x1080 P60 1280x720 P850 a a a Detect 3 2 F Detect 2 2 FF input Offset Input Size 1920 Output Size OSD Enable Eil Screen Offset Alpha Blend Z Plane X1091_12_031213 Figure 12 RTVE 2 0 Web based Control GUI The left side of the control GUI shows possible settings for each video processing pipeline including selection of video source deinterlacer modes scaler geometry and OSD alpha percentage value The right side provides controls to the video output screens The output format can be changed by clicking the desired radio button XAPP1091 v1 0 1 March 18 2014 www xilin
4. function in this design is scalable support for 2x 4x and up to 8x parallel video pipelines RTVE 2 0 includes the following features e On the fly switchable video sources HDMI and Triple Rate SDI e Support for progressive or interlaced format video e Multiple video output ports HD 3G SDI and HDMI e Scalable design optimized for different FPGAs e 2 pipeline XC7K160T logic density e 4 pipeline XC7K160T logic density e Up to 8 pipeline XC7K325T logic density e Completely based on Xilinx AXI infrastructure e AXI Lite CPU control interface e AXl Memory Map for external memory access e AX Streaming for video streaming among video processing blocks e Full featured video processing on every pipeline e Motion Adaptive and Edge Adaptive deinterlacer e Polyphase scaler with and on the fly customizable coefficient table e 10 bit 4 4 4 processing engine e Frame buffer readback e On the fly window resizing and magnifying glass function e Composite onto video output with graphic overlay Copyright 2013 2014 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Vivado Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners XAPP1091 v1 0 1 March 18 2014 www xilinx com 1 RTVE 2 0 FPGA Design RTVE 2 0 FPGA Design amp XILINX e Live video picture in picture e Professional fade
5. mini din SDI cables e One WiFi Ethernet router providing DHCP server e One Ethernet cable e One Micro USB cable for FPGA configuration e One Mini USB cable optional for UART debugging e One PC with at least two free USB ports Hardware Setup The hardware setup is illustrated in Figure 9 The TED TB FMCH 3GSDI2A card must be plugged in to High Pin Count HPC FMC connector on the KC705 evaluation board The TED TB FMCL HDMI card must be plugged into LPC FMC connector on the KC705 evaluation board XAPP1091 v1 0 1 March 18 2014 www xilinx com 11 Demonstration Setup XILINX HDMI Video Source Control PC SDI Video HDMI Monitor Signal Analyzer a SDI Video Input Wireless Coming From monte SDI Video Source Xilinx KC705 Board TED HDMI FMC TED SDI 2A X1091_09_031213 Figure 9 KC705 RTVE 2 0 Demo Setup Figure 10 shows the demo setup with wire connections The CHO RX CH1 RX CH2 and CH3 connectors on the TED TB FMCH 3GSDI2A card are connected to four SDI video sources using the mini din SDI cables Optionally a HDMI source can be fed into the TB FMCL HDMI RX port XAPP1091 v1 0 1 March 18 2014 www xilinx com 12 Demonstration Setup XILINX 4 gt FPGA JTAG E j Configuration KINTEX RJ45 X1091_10_031213 Figure 10 RTVE 2 0 Design Block Diagram The video output can be monitored through either a HDMI or SDI monitor The HDMI output is d
6. 01 b TOTE 1 01 b TONE 1 03 a 1 00 a 1 01 a 1 01 a 1 01 a 1 01 a 2 01 a X1091_04_031213 Figure 4 RTVE 2 0 XPS Build 3 On the Menu bar select Device Configuration then select Update Bitstream This step first builds a FPGA bitstream rtve_2_0_kc705_4x bit under release rtve 2 0 kc705 4x hw implementation directory and updates the bitstream with MicroBlaze processor bootstrap binary code The updated bitstream is saved into a new file named download bit SDK Software Build The RIVE 2 0 software resides in a local SDK Workspace with all RTVE 2 0 specific drivers contained within the hierarchy of the RTVE 2 0 project All built in Xilinx drivers are automatically located by SDK Use the following steps to create the SDK software 1 To create a new user workspace in the hierarchy of the RTVE 2 0 at a fixed directory level select File gt Switch Workspace gt Other EDK exports files to the default location relative to the top directory in the project 2 Inthe dialog box ensure that the directory ends with the SDK directory in release rtve 2 0 kc705 4x sw sw SDK Workspace see Figure 5 XAPP1091 v1 0 1 March 18 2014 www xilinx com 6 Build the RTVE 2 0 Project amp XILINX i Workspace Launcher Select a workspace Xilinx SDK stores your projects in a folder called a workspace Choose a workspace folder to use for this session Workspace MARHESIVNG ele dem deemee gt ay LEE E2 Co
7. Application Note Kintex 7 Family 2 XI LI NX drakes re Engine 2 0 Implementation in XAPP1091 v1 0 1 March 18 2014 Summary Introduction Author Bob Feng and Kavoos Hedayati In the broadcast video landscape video content with various formats flows across acquisition contribution distribution and consumption sectors To properly archive distribute and display the content the video signal often needs to be properly processed with the appropriate format conversion For example to correctly display NTSC PAL signals on a FHD LCD screen a series of deinterlacing scaling chroma upsampling and color correction operations must be performed as well as alpha blending This application note leverages the latest Xilinx Kintex 7 FPGA architecture to provide a truly scalable video processor reference design to serve multi stream multi pipeline video processing needs It is targeted for applications like multi viewer display video switches and multichannel video routers as well as multi stream up down converters This broadcast quality video processing reference design is targeted to a wide range of video applications The Real Time Video Engine Reference Design version 2 0 RTVE 2 0 primarily performs video de interlacing and scaling and includes other features such as a triple rate SDI interface DVI interface on screen display OSD video frame buffer control chroma resampler and color space conversion The video processing
8. TT Povey eevee a ITTE Merry teert oe ILT Bette Rete ee Ae aaa ott Seiad Eon te Tre a To Bie SE Ai A o a M Vm O e iJ Bus interfaces Name Bus Name iP Type BE IP Version DDR3_SDRAM 5 axi4_ddr_bridge 5 axi4lite_0_to_1 axi4lite_ddr_bridge H debug_module microblaze_O_intc H ETHERNET _dma ETHERNET H osd_O 5 R5232 Uart 1 5 axi_vtc_O omni_hdmi_rx_0 omni_hdmi tx_0 omni_offset_capability_0 5 DIP_Switches_8Bits 5 CD_GPIO 5 LEDS 8Bits 3 Push_Buttons_SBits axi_timer_O omni_overlay_0 ommni_sdi_rx_0 2 omni_sdi_rx_1 H omni_sdi_rx_2 5 omni_sdi_rx_3 5 omni sdi tx_0 a omni vpo omni_xsvi_ccm_out 5 omni_xsvi_splitter_O 5 omni_xsvi_switch_inputs Clock_generator_0 ommni_7series_gtx_0 ni vr axi_7series_ddrx r axi2axi_connector vr axi2axi_connector r axi2axi_connector A axi_ethernet A axi_osd vr axi_uartlite A axi_vtc ye omni_hdmi_rx ve omni_hdmi_tx vr omni_offset_capability tre axi_gpio vr axi_gpio r axi_gpio vr axi_gpio ve axi_timer yr omni_overlay ve omni_sdi_rx ve omni_sdi_rx ve ormni_sdi_rx ve omni_sdi_rx r ormni_sdi_tx omni_vp_4x_kintex _325 ve omni_xsvi_ccm ve omni_xsvi_splitter wre omni_xsvi_switch yr clock_generator wr omni_7series_gtx 1 07 4 1 00 4 1 00 4 1 00 4 2 10 4 1 03 a 6 03 4 3 01 a 3 00 a 1 02 a 3 00 a 1 01 a 1 01 a 1 00 a 1
9. _downloa J datz Microblaze di repository p P Software r Cc 4 rtve_2 0_kc705_4x hw rn l pcores data p rtve 2 0 _kc705_4x mhs etc rtve_2 0_kc705_4x xmp EDK Hardware di pcores Project Files a Ji rtve 20 kc705_4x sw F d Sw gt di repository F B ener d SDK Software SDK_Workspace Workspace A kc705_4x_bsp A kc705_4x_hw gt L kc705_rtve di web r 4 Th x1091_03 031313 Figure 3 RTVE 2 0 Project Directory Structure Tools The project is implemented based on a complete Xilinx EDK flow so ISE Design Suite 14 4 Embedded Edition or later must be used The hardware must first be built using EDK The SDK project can then be built to deploy the FPGA BIT file and MicroBlaze processor software onto the KC705 development system EDK Hardware Build These steps are used to build the EDK hardware 1 Launch XPS Xilinx Platform Studio 2 Select and load the rtve 2 0 kc705 4x xmp project file from the release rtve 2 0 kc705_4x_ hw directory as shown in Figure 3 The EDK screen should resemble a system view with all the connectivity of the various pcores used by the RTVE 2 0 design shown in Figure 4 XAPP1091 v1 0 1 March 18 2014 www xilinx com 5 Build the RTVE 2 0 Project amp XILINX file Edit View Project Hardware Device Configuration Debug Simulation Window Help D e Hg mm amp OA X me oh ee eere yore eet et terre era sF a ens H EEIE E ey ee TTT et ee UT
10. ata processed to just the active image and spreading its processing of any line over the whole of a single line sweep This allows the required maximum data flow to be reduced by a factor corresponding to the difference between the actual line length and the active line length In this example case that corresponds to an average maximum data flow that results by multiplying the calculated total by 0 93091 Table 1 RTVE 2 0 Memory Utilization Breakdown Deinterlacer 2 pipeline OSVP 3 000 x 3 x 2 18 000 Mb s 4 pipeline OSVP 3 000 x 3 x 4 36 000 Mb s 8 pipeline OSVP 3 000 x 3 x 8 72 000 Mb s Resizer 4500 Mb s 4500 Mb s 4500 Mb s OSD 4500 Mb s 4500 Mb s 4500 Mb s Total 27000 Mb s 45000 Mb s 81000 Mb s Average 25134 6 Mb s 41891 Mb s 75403 6 Mb s XAPP1091 v1 0 1 March 18 2014 The x2 and x4 configurations are well suited with a DDR3 64 bit 800 Mb s memory setup For the x8 configuration DDR3 64 bit 1 600 Mb s is needed to fully leverage the Xilinx Kintex 7 FPGA performance advantage www xilinx com 4 Build the RTVE 2 0 Project XILINX Build the RTVE The following example walks through detailed steps to build a x4 OSVP configured RTVE 2 0 2 0 Project design Project Directory Structure The RTVE 2 0 project directory structure is shown in Figure 3 4 d release m Name j Pre compiled IE ready for download Bitstream arn ready for
11. e of The information disclosed to you hereunder the Materials is provided solely for the selection and use of Disclaimer Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http Awww xilinx com warranty htm IP core
12. ey video processing function blocks are Chroma Upsampling The OSVP conducts a straight 4 4 4 10 bit processing pipeline for the best possible picture quality Incoming 4 2 2 video streams are pre upsampled to 4 4 4 streams e Color Space Conversion The OSVP allows conversion between a wide range of color spaces e Deinterlacing The OSVP uses motion and edge enhancement techniques to convert an interlaced input video to an equivalent progressive video format Additionally the OSVP can detect film mode based cadences such as 2 2 and 3 2 pull down The OSVP then corrects the video to reconstruct the original video format XAPP1091 v1 0 1 March 18 2014 www xilinx com 3 RTVE 2 0 FPGA Design amp XILINX e Cropping The OSVP allows a specific region of the input video to be selected for further processing This occurs for example in a 4 3 or 16 9 aspect ratio switch on a video stream that transports different footage types films and advertisements e Scaling Resizing In the OSVP the scaler resizer takes the progressive output from the deinterlacer and resizes the image to a new output size The user can select a variety of input output scaling operations up scaling down scaling Zooming and aspect ratio adjusting e OSD By taking outputs from the OSVP the OSD is used to render the final scaled image with video graphics and text overlay onto the output video streams The OSD block allows overlapping of up to eight video
13. g blocks including video streaming input and output Microblaze soft processor On Screen Display OSD LogiCORE Video Time Controller VTC LogiCore and AXI Interconnect and AXI DDR to form a full featured Real Time Video Engine Figure 2 illustrates the design architecture XAPP1091 v1 0 1 March 18 2014 www xilinx com 2 RTVE 2 0 FPGA Design XILINX AXI4 Kon Chroma Colour De j Frame Upsample xN Channels eure AXI4 HDMI Tx Stream Overlay AXI Lite Input Video Module omae AXl4 Stream Component Video Processing gt AXI4 MM Module Video Output Non Productized AX 4 Lite Module Component System Module XSVI X1091_02_031213 Figure 2 RTVE 2 0 Design Block Diagram Video Input The RTVE 2 0 supports up to eight SDI and one HDMI input sources The supported input formats are e SDI SD NTSC SD PAL HD 1080i HD 1080p HD 720p e HDMI 480p 576p 720p 1080i 1080p Video Output The RTVE v2 0 generates video output on all interfaces HDMI and SDI concurrently The output format is user selectable among the 720p50 720p60 1080p50 and 1080p60 rates The output frame rate is derived from the input frame rate and matched with either frame repeat or frame drop For example deinterlacing and scaling a 480i 59 94 Hz input to a 720p60 or 1080p60 output results in frame repeat Similarly if the output format is set at 720p50 or 1080p50 proper frame drop occurs Video Processing The k
14. in fade out effect e Contrast enhancement through Color Correction Matrix e Web server based control GUI The core video processing engine in the RTVE 2 0 design is built on OmniTek s state of the art OSVP Scalable Video Processor Ref 1 see Figure 1 The OSVP contains a series of configurable video pipelines supporting x2 x4 and x8 parallel processing Each pipeline consists of chroma upsampling color space conversion deinterlacing cropping scaling resizing and video output frame synchronization In addition each OSVP is equipped with one or two built in multiport video DMA blocks depending on the number of processing pipelines to streamline balance and arbitrate all external memory access requests from all video processing blocks The OSVP fully adopts Xilinx AXI4 peripheral bus technology Its control plane is directed from an AXI4 Lite interface external memory access is through one or two AXI4 MM interfaces and video input and output are carried from AX 4 Streaming interfaces This makes it highly compatible with the Xilinx design environment and methodology AX 4 Lite CPU Interface CPU Backplane RGB or YUV RGB or YUV 4 2 2 or 4 4 4 4 2 2 or 4 4 4 AXI 4 Stream AXI 4 Stream Video Video aL Deinterfacer Frame Store Multiport DMA AXI4 MM Memory Interface X1091_01_040113 Figure 1 OmniTek Scalable Video Processor Leveraging the AXI4 infrastructure the OSVP is easily integrated with other Xilinx IP buildin
15. ough its native SDI interface or by running from a regular DVD player to a HDMI DVI to SDI conversion box For example see the video interface converter at http www blackmagic design com products dviextender This section provides design advisories for the RTVE demonstration e HDMI RX Video Mode The NTSC PAL video reception through the HDMI RX port on the TB FMCL HDMI card is not supported The limitation is twofold e The HDMI specification does not mandate support for NTSC PAL Therefore the transmission capability of this video format is dependent on the individual media player e The TB FMCL HDMI Hardware User Manual Ref 2 does not support NTSC or PAL e 2 2 Film Mode Cadence Detection Depending on the media content and player the 2 2 cadence might not always be detectable 7 OmniTek Scalable Video Processor OSVP User Guide http omnitek tv sites default files OSVP pdf 2 TB FMCL HDMI Hardware User Manual http solutions inrevium com products pdf pdf_TB FMCL HDMI_HWUserManual_3 00e p df 3 Kintex 7 FPGA Broadcast Video Kit http solutions inrevium com products kits broadcast tb 7k 325t bvk html The following table shows the revision history for this document Date Version Description of Revisions 04 05 2013 1 0 Initial Xilinx release 03 18 2014 1 0 1 Corrected figure reference to Figure 5 XAPP1091 v1 0 1 March 18 2014 www xilinx com 16 Notice of Disclaimer XILINX Notic
16. py Settings X1091_05_031213 Figure 5 Set up the RTVE 2 0 SDK Workspace 3 To ensure that the automatic build process can locate all drivers immediately after the import process is complete add the local driver repository specific to the RTVE 2 0 project before importing the project a Select Xilinx Tools gt Repositories b Inthe top field labeled Local Repositories available to the current workspace click New and browse to the repository directory and select it c Click OK to accept the new local repository of drivers Figure 6 shows the window after the repository has been added type fitertext gt General E gt C C gt Help gt Install Update b Remote Systems gt Run Debug gt Team Terminal wv Xilinx SDK Boot Image Flash Programr Hardware Spec Log Informatio Target Manager i Preferences Add remove or change the s software repositories the current workspace E TAGEN 0 x4 software sw repository New up Relative across workspaces X1091_06_031213 Figure 6 Set Up RTVE 2 0 SDK Repositories 4 To import the predefined software and hardware projects from which SDK builds the RTVE reference software select File gt Import XAPP1091 v1 0 1 March 18 2014 www xilinx com 7 Build the RTVE 2 0 Project XILINX 5 Inthe Import dialog box select General gt Existing Projects into Workspace as shown in Figure 7 and click Next
17. riven through the TB FMCL HDMI TX port The SDI outputs are driven through CHO TX and CH1 TX connectors on the TB FMCH 3GSDI2A card Both use mini din cables The KC705 Ethernet port must be connected to the wireless router LAN port so that an IP address can be allocated to the RTVE 2 0 If a bundled Kintex 7 FPGA broadcast video kit is desired TB 7K 325T BVK RTVE can be purchased from Xilinx ecosystem partner Inrevium s website Ref 3 Software Inventory e Microsoft Windows 7 XP Vista e Xilinx ISE 14 4 or newer version design tools package including all necessary KC705 device drivers FPGA Configuration To configure the Kintex 7 FPGA on the KC705 Board FPGA connect a micro USB cable to the KC705 micro USB port through the control PC as shown in Figure 10 and then perform these steps 1 Launch Xilinx Microprocessor Debugger XMD XAPP1091 v1 0 1 March 18 2014 www xilinx com 13 Demonstration Setup XILINX 2 Change directory to release ready for download where prebuilt FPGA bitstream download bit Microblaze software kc705 rtve elf image file image mfs and FPGA configuration script start kc 4x tcl are located 3 Configure the FPGA by running the command source start kc 4x tcl RTVE 2 0 Web Based Control GUI The RTVE 2 0 is controlled through a web based GUI which is accessed through an IP address This address is found in the output screen s system status box at the top right corner Figure 11 The status
18. s may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications htto www xilinx com warranty htm critapps XAPP1091 v1 0 1 March 18 2014 www xilinx com 17
19. streams Detailed descriptions of each video processing function block are in the OSVP User Guide Ref 1 External Memory Utilization Analysis Efficient memory utilization is key to implementing a truly scalable video processor In OSVP each video processing pipeline has five concurrent memory access ports The deinterlacer has two read and one write ports the resizer has one write port and the OSD has one read port For an eight pipeline configuration up to 40 concurrent access ports are required Actual memory utilization varies on a case by case basis The following provides a case analysis for multiple pipeline configurations working with 4 4 4 interlaced video with 30 bit color delivered at a rate of 75 x 106 pixels s and all video windows displayed without overlap on a single screen Table 1 shows the memory utilization With video of this format each deinterlacer read or write port sees a maximum data flow of 40 x 75 3 000 Mb s including the motion vector overhead The deinterlacer output is streamed directly to the OSVP resizer input Because the video being processed by the different pipelines is shown on a single screen without overlap the total flow from the resizer write ports of the different pipelines is 30 x 150 4 500 Mb s This value also applies to the total flow to the OSD read ports While summing these factors provides the absolute maximum data flow the OSVP reduces its bandwidth requirement by restricting the d
20. ut per input channel 0 1 900 2 500 0 SDI Output 0 409 445 0 HDMI Input 0 405 287 0 HDMI Output 0 79 53 0 AXI Interconnect CPU Peripherals 0 2 000 1 091 0 AXI Interconnect High Bandwidth 0 12 231 8 056 Onscreen Display 4 channels 2 5 093 2 983 12 MicroBlaze 19 3 168 7 850 6 DDR3 MIG supporting 4 8 channels 0 17 891 15 511 0 Video Timing Controller 0 764 757 Totals 2 input RTVE 2 0 149 83 695 73 937 183 4 input RTVE 243 105 801 96 547 291 Kintex 7 160T resources 325 202 800 101 400 600 8 input RTVE 415 158 013 136 767 504 Kintex 7 325T resources 445 407 600 203 800 840 www xilinx com Demonstration Setup XILINX Demonstration The following 4x configuration demonstration consists of two parts hardware setup and Setup software setup To load the software into the FPGA the following are required and included in the project file e Apre generated FPGA bit stream kc705 4x bit e A pre compiled Microblaze firmware binary kc705 rtve 4x elf e Animage file image mfs e An FPGA configuration script start kc 4x tcl Hardware Inventory The following hardware is required for the demonstration e One Xilinx KC705 Evaluation Board XC7K325T 2FFG900 FPGA e One TED TB FMCH 3GSDI2A card e One TED HDMI 1 3 Rev 3 TB FMCL HDMI FMC card providing HDMI input and output e One HDMI monitor supporting at least 720p 60 Hz 1280x720 p 60 e Four SD HD 3G SDI Video Sources e One HDMI video source optional e One HDMI cable e Four
21. x com 15 Design Advisory Design Advisory References Revision History amp XILINX Initially a quadratic layout diagram is shown on the bottom right side Clicking the Next Layout button rotates the various preset layouts The size of any of the four video windows can be changed by clicking and dragging the window s border or corner Click and hold within a window to move it anywhere in the output screen Windows can overlap each other Changing the alpha blending percentage value for each window enables picture in picture capability RTVE 2 0 allows a maximum of eight windows to overlap each other with individually controllable transparency which can be used to deliver fade in fade out effects In addition the GUI software allows each processed video pipeline s Resizer output to be captured by clicking the Snapshot Scaler button on the top right side Recommended Demonstrations and Benchmarks To effectively use the two major RTVE building blocks the deinterlacer and the scaler Xilinx recommends using professional video benchmark tools containing enough diagonal lines motions chroma color bursting film mode cadences and other challenging sequences Due to the limitations inherent in transmitting NTSC PAL interlaced video through the HDMI DVI interface Xilinx recommends using the SDI interface to benchmark both deinterlacing and scaling functions The video content can be transmitted from a professional video server thr
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