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FS1610

1. 5 56 gt y tc 2 20 29 gt 270 5 15 i 5 lt p Buck x x CC Boost Buck Boost X X too x When a fault in an enabled channel is detected the FS1610 responds as configured for that channel in the EEPROM The options are B Shutdown channel and set channel fault status bit B Shutdown channel set channel fault status bit and auto restart channel option not available for Boost and Buck Boost channels B Shutdown the chip Note Setting the fault status bit for a channel will result in an interrupt to the host if the 51610 is so programmed Note Over voltage in the CC Boost channel SW 6 is not classified as a fault and a fault condition is not indi cated in that event See WHITE LED DRIVER SW 6 section for additional information In addition to the type of fault response there are also two EEPROM programmable parameters asso ciated with the fault response Fault Delay is the in FyreStorm Inc 27 FS1610 terval between the time the channel reports a fault and the FS1610 recognizes the fault and takes any action related to it A value of 0 for Fault Delay means to ignore all faults for the channel Auto Hestart Delay is the time the FS1610 will wait after it shuts down the channel until it attempts to restart it Each of t
2. Digital Ground forinternal RTC Supply 8 _ areca X5R bypass capacitor between this pin AVSS Amg mud odo TEST 1 Test Input 1 For FyreStorm use only Connect to ground for normal operation TEST 2 Test Input 2 For FyreStorm use only Connect to ground for normal operation P12 V EEPROM Supply for Internal EEPROM Connect the specified voltage during programming of the internal EEPROM Do not connect during normal operation EEPROM Data Input Output active high Used for EEPROM programming only R12 SDA Leave unconnected for normal operation EEPROM Clock input active high Used for EEPROM programming only Leave SCL unconnected for normal operation N C No Internal Connection These ball pads may be used for routing DNC Do Not Connect Make no connection to these balls 1 digital input digital output P power input or output la analog input analog output 2 See Table 1 for asserted state for digital inputs and outputs and digital output driver type 3 While in SHUTDOWN state these pins are not powered and resemble floating open drain outputs to the system When the device enters READY state they are configured as inputs with input pull down resistors The chip stays in this configuration until the end of Boot 2100 mS or when SW 2 goes into regulation depending upon EEPROM configuration option at which
3. WDT are enabled and running if they were so programmed before entering SD state The serial interface is active After loading the power up settings the device will transition from READY to ACTIVE if any power rail is enabled by assertion of a PWREN input or if pro grammed as default PWREN O supplies in the EEPROM It will return from READY to SD if ten seconds have elapsed since entry into the READY state and no supplies have been enabled except if presence of an AC adapter is detected The FS1610 may not fully enter the READY state from SD state if several tests based on the configura tion data read from the EEPROM are not satisfied These include a test that VIN is above the Minimum Voltage to Boot value Vgruw test that nEX TON stays Low for the time specified in the ExtOn Timeout EEPROM variable if the TIMED WAKEUP EEPROM option is enabled See Figure 18 PRELIMINARY Rev 6 2 Aug 06 A channel fault occurs Ten seconds since entry into READY state and no supplies have been en abled nEXTON does not stay Low for the time specified in the ExtOnTimeout EEPROM variable Transitions from SHUTDOWN State 2 5 1 voltage rails are disabled 1 5 A channel fault occurs 2 5 An RTC alarm Assertion of the PWREN 1 input The nEXTON input goes from High to READY Low Note 6 nEXTON stays Low for the time speci fied in the ExtOnTimeout EEPROM 3 10 variable AC adapter i
4. 2 5V Vo 2 0V 57 60 Vo 1 5V gt 5 TP 2 0V 5 1 0 40 1 5V i 40 1 0 2090 2090 0 0 1 1 10 100 1000 0 Load Current mA 0 1 1 10 100 Load Current mA Figure 2 Typical Buck Converter Efficiency Figure 4 Typical Buck Converter Efficiency Normal Mode Vin 5 0V Low Power Mode VIN 5 0V PRELIMINARY FyreStorm Inc 9 Rev 6 2 Aug 06 Q FyreStorm FS1610 Efficiency 100 100 80 Vout 15V o o 3 5 5 Vout 10V 40 a 40 Vout 5V 20 20 0 T T 096 4 0 1 1 10 100 0 1 1 10 100 Load Current mA Load Current mA Figure 5 Typical Boost Converter Efficiency Figure 7 Typical Buck Boost Converter Effi VIN z 3 9V ciency VIN z 3 9V 10096 100 80 Vout 15V gt 60 5 5 Vout 10V E 8 40 Vout 5V 2096 2090 096 0 1 1 0 1 1 10 100 0 1 1 10 100 Load Current mA Load Current mA Figure 6 Typical Boost Converter Efficiency Vin Figure 8 Typical Buck Boost Converter Effi ciency VIN z 5 0V 5 0V PIN DESCRIPTIONS Nme Note clock is required for device operation even if the RTC and or Watchdog are not used Power On Reset Output nRSTO is asserted during the internal power on reset pe riod of the 51610 See COLD START POWER ON SEQUENCE It can be nRSTO grammed to be asserted during
5. response time to out regulation program 255 ns ming range 50 External output capacitor Les lt 470 1000 2200 n 1Mhz f 50 MHz PSRR f 10KHz lour 60mA_ 40 e100 Ke 1 The aggregate internal power dissipation for all LDOs combined must not exceed 500 mW A Electrical Parameters Switching Regulators VIN 3 0 V 5 5 V Ta 20 C to 85 C unless otherwise noted Typical values are at Ta 25 C and VIN 3 6V symbol Parameter Conditions min Max Unit Constant Current Boost Regulator SW 6 i Maximum outputcurent im output curent programmingresouon wo m jOupucuremaccmay fiam zb _ Dupucurm 2 mA _ mwutlwagecuent HSENB LSENS jOwputowvolageSDDiS S oupu fazom few Swtchigfreqeny _____ operating current VIN 152 61 0 30mA 90 0 NN 5 es 2 NNNM E m IN uM NEN s 5 2 5 5 meememaisuppycurenaVINGS SWIG enabled hep 20 sequencing tro thresh _ response time to out of regulation program ming range Synchronous Buck Regulators SW 0 SW 2 SW 4 6 3 Output voltage programming resolu
6. Test access For fast design optimization exposed connec tions to all balls except C2 G2 H14 R3 should be available on either top or bottom layer Spare Pad Fields If space permits add spare pad fields for quickly breadboarding new circuits 35 Q FyreStorm FS1600 1610 PMP PMC CHARGER FS1610 ONLY BOOST 1 BOOST 3 BOOST 5 Figure 23 Typical Applications of the FS16xx Power Management Controller Q FyreStorm FyreStorm Inc 255 San Geronimo Way Sunnyvale 94085 3839 408 523 6300 Fax 408 328 1339 Email sales FyreStormlC com http www FyreStormlC com O 2004 2006 by FyreStorm Inc FyreStorm All rights reserved This document describes a device currently under development by FyreStorm and the information in this document is subject to change without notice PRELIMINARY FyreStorm Inc 36 Rev 6 2 Aug 06
7. hbopSupy ipu 0000000 P LDOp SuppyRetum 00000000 P P DOSSuph imput O LE EN AN Fe On _ P14 LSD O Low Side Drive Switcher 0 When SW 0 is turned off the low side driver will dis charge the output capacitance at a rate programmable via the configuration EEPROM HSENG output Voltage High Side Sense Switehero SEND output Voltage Low Side Sense P vae Supply Return Swichers SD lowside Drive Switcher SSS Hsen Output Voltage High Side Sense Switcher SENI OuputVotajelowSieSenseSwicheri mA Shutdown Disconnect 1 This output is used to reduce leakage current via the resis SDDIS 1 tor divider on the output of SW 1 SDDIS 1 turns on prior to the output ramping up when SW 1 is enabled and turns off high impedance after the output goes below VIN when SW 1 is disabled VIN 2 Supply Input Switcher 2 Connect a bypass capacitor between this pin and VRET 2 VRET 2 Supply Return Switcher 2 HSD 2 High side Drive Switcher 2 la la la PRELIMINARY FyreStorm Inc 12 Rev 6 2 Aug 06 ESTEE Q FyreStorm Type Low side Drive Switcher 2 When SW 2 is turned off low side driver will dis une ae charge the output capacitance at a rate programmable via the configuration EEPROM HS
8. Q FyreStorm Leading the Digital Power Revolution GENERAL DESCRIPTION FyreStorm s FS1610 Advanced Power Management Controller utilizes proprietary digital technology to pro vide a fully programmable power subsystem solution for sophisticated mobile devices such as digital still cam eras feature phones smart phones PDAs hand held computers Compared to traditional implementa tions an FS1610 based solution reduces PCB area and its digital technology which allows full programma bility results in faster design cycles allowing quicker time to market for the end product It reduces glue logic by interfacing seamlessly to processors such as Intel s PXA family Freescale Semiconductors MX families Samsung s ARM9 based family and AMD s 1200 family The FS1610 provides eight highly efficient switch mode converters three buck converters one White LED driver three boost converters and one buck boost con verter and has integrated drivers that directly drive ex ternal MOSFETs A patented digital control algorithm reduces capacitor and inductor size and cost reduces quiescent current and improves conversion efficiency Additionally the FS1610 provides three low power LDO regulators with internal pass FETs a Real Time Clock with a programmable alarm and a Watchdog Timer Start up configuration of the device is stored in an inter nal EEPROM that can be programmed by the user and can then be managed by the host pr
9. 0 _ 58 Input voltage V EEPROM Not connected for normal operation Input voltage ___ 55 V Input voltage O 90 Operating Current WAN SHUTDOWN state LOWPOWER SW 2 0 D Sedan SHUTDOWN _____ 5 m Rav 4 m olm NRSTI input debounce time nRSTI de asserted 3 m 2 9 nEXTON asserted or de texton NEXTON input debounce time 3 LINES nRSTO timer period programmable in EEPROM 1 65 535 ms Rsro nIRSTO timer period nRSTI asserted 65 ms Dead battery threshold programming range 3 10 3 30 Dead Battery detect threshold programming resolu tion NN Dead Battery detect threshold accuracy VMAIN decreasing Dead Battery detect comparator hysteresis VMAIN increasing tbd 150 mV Vieru Low battery threshold programming range Low Battery detect threshold programming resolu tion LOWPOWER Low Battery detect threshold accuracy DBOUT output High voltage lo 100 pA DBOUT output Low voltage lo 100 ADPTR detect threshold voltage ADPTR increasing ADPTR detect comparator hysteresis ADPTR_IN decreasing Taper ADPTR IN detect debounce time 2 ADPTR asserted 1 Thermal Sensor Accuracy Junction temperature C T isi 1 Tra oio
10. SLEEP MODE SUPPLY OUTPUT Intended primarily for Intel PXA27x applications VBAT can be used with any processor requiring an active voltage rail during their Sleep mode It is the first supply to be active and the last to power off This provides a means to supply power for circuits such as a time clock and memory that need to oper ate even in the absence of main battery input power VBAT VINSW 2 if SW 2 is enabled and in regu lation VBAT BATBU if SW 2 is disabled or out of regu lation REAL TIME CLOCK RTC The FS1610 provides an RTC operating from the crystal clock It features a span of 10 years with a granularity of one second A programmable alarm can cause an interrupt to be issued to the host CPU The RTC and the RTC alarm are automatically cleared and the RTC is enabled upon power up If the RTC alarm occurs while the FS1610 is in SHUTDOWN state the event will wake up the de vice and cause it to transition to READY state The nINTR output will be asserted to alert the host to en able appropriate supplies in the device if not auto matically enabled see POWER CONTROL AND SEQUENCING so it can determine the cause of the interrupt WATCH DOG TIMER The device incorporates a watch dog timer WDT with an EEPROM programmable timeout of up to 32 seconds and a granularity of one millisecond The can be optionally disabled at power up via the EEPROM so configured it begins to operate whe
11. Typical Back Up Battery Configura tions nEXTON SWITCH INPUT This input is normally connected to a momentary con tact switch and is used to control ON and OFF events for the device The input is normally High via an in ternal pull up resistor and is connected to ground Low to initiate ON and OFF events as described below FyreStorm Inc 22 251610 There are three EEPROM parameters associated with the nEXTON input ExtOnTimeout a variable configurable from 250 ms to 12 seconds The 250 ms timer is a system timer that is not synchronized to the High to Low transition of nEXTON so the actual time may be up to one count 250 ms longer than programmed Timing for this event begins after the nEXTON input debounce interval texton proximately 100 ms and reading of the EEPROM when transitioning out of SHUTDOWN state ap proximately an additional 80 ms When the device is in ACTIVE or LOWPOWER states and nEXTON goes from High to Low and stays Low for the time specified in ExtOnTimeout the 51610 sets a bit in its Status Register See the 51610 HSI User Manual for additional in formation TIMED WAKEUP if this option is turned On it requires that nEXTON goes from High to Low and stays Low for the time specified in ExtOn Timeout to cause a transition from SHUTDOWN to READY states If this option is turned Off that transition is initiated immediately upon detecting that has changed from Hig
12. and lower cost Three LDOs Input voltage range 2 8 to 5 5 Volts Battery backup switching support Dynamic programming for all buck and LDO power rails Power up supply characteristics can be modi fied without hardware changes by reprogram ming the device s EEPROM Fastand simple design with FyreStorm s Web based Design Center B Capable of stand alone operation using the pa rameters loaded from the EEPROM at start up serial interface with host required Utilize device pins for status control B Integrated system support time clock with alarm and Watchdog timer Programmable host controller interrupt output Power Good and Power on Reset outputs Remote management via or UART interface to host processor B Operates from a low cost 32 768 KHz crystal or external clock input Provides buffered 32 KHz output to the system B Low power consumption 50 A in shutdown mode with RTC enabled 128 bytes user data space in EEPROM 8 x 8 mm FBGA package with 0 5 mm ball pitch PRELIMINARY Q FyreStorm FS1610 CONFIGURATION 123 456 7 8 9101112131415 BALLS HIGHLIGHTED AREA ARE FOR HEAT DISSIPATION ONLY AND SHOULD BE CONNECTED TO GROUND PLANE 3 gt FS1610 Pin Configuration Top View Looking Through Package PIN FUNCTION PIN FUNCTION PIN FU
13. 0x64 0x64 0x65 0x65 0x66 0x66 Read Device Rev ID Enable Disable Alarm Read Alarm Time RTC Write Alarm Time Read RTC Time Write RTC Time Read Voltage t Voltage 0x03 0x06 0x03 Enable Disable Power 0x04 Rail Group 0x03 Enable Disable Specific Power Rail Set Specific Power Rail to Standby Normal Driver Read Internal POK Status for All Rails Set POK Configuration 0x04 0x03 CD CD D D 4 D gt lt ___0 61 ___0 62 0x62 0x64 0x64 ___0 65 0x65 0x66 ___0 66 0x04 N A 0x03 N A 0x02 N A 0x03 0x03 0x03 Ee 0x02 N A 0x05 SW Status Set Configuration 0x04 N A 0x03 Write User EEPROM 0x04 N A Segment Byte 0x03 Read User EEPROM 0x03 Segment Byte 0x04 N A Note Responses are shown for the ACK case For any NAK the response will be PRELIMINARY FyreStorm Inc 31 Rev 6 2 Aug 06 Q FyreStorm 51610 PROGRAVMING VOLTAGE EE 2 SDA M T 180 m 18 1 24 QAN EA 47 00 uF 2 1206 4 Cid 3620 01 50 224 iin MBRO0530 a BOOST 1 1 14 lt ___ Abos 47 00 uF nIRSTO 1210 EE i ADFTR_DET RSTI m R2 10 v Fa wng 1 0K a nz 8 2 BOOST 3 T C5 2 20 uH 05 220 uF 805 LE sand E M R3 R4
14. 15W 10 0K O 03 BOOST 5 220uH 06 M 19 AO3418 ue 180 E 3 S SEIL PWREMTI PWRENS ics E D4 gt a TO OK 0 150K 0 MBROS30 17 BOOST c MR 28V bi 510uH 1306 AO3418 305 C23 160 mQ L veers i GNDLDO HSENS Y 500158 LSENG R8 10 0K 0 309K Q 40V 24 H D7 7 Tu Qs 11 BUCK BOOST 7 C106 18 2 8 1 15 UM TS __ 003 VRET el Me HSEN LSEN v R9 R10 80 6K Q tu Figure 22 Typical FS1610 Configuration PRELIMINARY FyreStorm Inc 32 Rev 6 2 Aug 06 FS1610 Q FyreStorm PACKAGE MECHANICAL CHARACTERISTICS A B p area D _ _ VIEW DETAIL f SIDE VIEW i bbb C C Y Y P A CT 4 ccc AA DETAIL A gt gt OOO nX b A dddM C AM BM DETAIL DETAIL B 14 12 10 8 6 42 15 13 11 917 5 3 1 OOO A B D OO E OO D1 UU H 00 J K OOIL e e M OO N e e P OO R N ___ _ E1
15. Indicates that presence of an AC adapter has been de pps tected the ADPTR input Refer to Table 1 if not used B12 PWREN 3 Power Enable 3 1 Power on off control for any group of rails can be mapped to be controlled PWREN 1 or PWREN 2 PWREN 3 A low high transition enables the B11 PWREN 2 voltage rail group a high low transition disables the group Once enabled or disabled a pre programmed sequencing defined in the configuration EEPROM is activated A PWREN 1 LINNE N iss Note 3 operating mode See Low Power Mode Standalone Mode nLB Low Battery Detect Output This pin is asserted when ever VIN goes below the low battery detect threshold Note does NOT apply to PWREN 1 Serial Mode SCL Clock Input MFP 2 UART Serial mode EXTPEN2 External Power Enable Output This output is asserted HIGH at the conclusion of the internal power up boot process before turning on any power rails and is de asserted when the FS1610 transitions to SHUTDOWN state after all F51610 power rails are turned off Standalone Serial Modes PWREN 4 WDRST Power En able 4 Input or Watchdog Timer Reset Input or External Power Enable Output The function of this pin is selected via the EEPROM If configured as PWREN 4 a group of power rails can be mapped the EEPROM to be enabled disabled via this input See PWREN 3 1 for additional informa
16. Intel s PXA27x processors The behavior described above is designed to ensure that an anomaly in that device which causes it to draw exces sive current from this voltage rail before the processor 15 properly initialized for Sleep operation does not drain the back up battery See FyreStorm application note AN52 1 o The internal system controller and other cir cuitry are powered up and begin operation o Device configuration parameters are read from the internal EEPROM and loaded into appro priate internal registers o VIN is checked to make sure it is above the Minimum Voltage to Boot value read 23 FS1610 Q FyreStorm from the EEPROM If it is not the device re activated using the power on sequencing pa turns to SHUTDOWN state rameters read from the configuration EEPROM Note An EEPROM configurable option can be used to force continuation of the boot process even if this test o nRSTO is de asserted and the serial interface fails becomes active tRSTO after EEPROM o The EXTPEN 3 2 output is asserted to enable specified set of voltage rails reach their power external power rails if this function has been good threshold o When the group of rails specified to be moni tored by POK in the EEPROM reach their power good threshold the POK output is as selected by configuration option o If so programmed PWREN O any supply or group of rails can be automatically activated at this time This pro
17. Management Output Voltage Range Checking SWI4 2 0 may be programmed independently to limit their output voltage to minimum and maximum voltages specified in the configuration EEPROM programmed to operate in this manner any com mand to change the output voltage to a value outside the specified minimum and maximum limits will be rejected Low Power Mode When the FS1610 is in LOWPOWER mode buck converters SW 2 0 operate pulse frequency modulation mode which increases efficiency at low power levels Output current in this mode is limited to 10 of the programmed ACTIVE mode maximum Current PRELIMINARY Rev 6 2 Aug 06 Q FyreStorm The output voltage of buck converters SW 2 0 is automatically changed to a preset low power value configured in the EEPROM which can be the same or different from the ACTIVE mode value This al lows compatibility with the processor others requiring this feature Active Discharge SWIA 2 0 can be configured to actively discharge the output capacitance when disabled lf this feature is enabled the output voltage is monitored for a specified voltage level If the output is at a higher voltage the low side driver is pulsed at a program mable rate to discharge the output capacitance until the specified voltage level is sensed Shutdown Restore Shutdown Restore can be enabled for the buck con verters via the EEPROM See Shutdown Res
18. Placement Keep crystal input at least 4 mm away from all power FETs diodes and inductors Place bypass capacitors near FS1610 package For buck channels 0 2 4 bypass capacitors should be between FS1610 and FETs For all other switching channels bypass capaci tors should be between FS1610 and inductor Place input capacitor near balls A6 and A7 For each channel place MOSFET and diode on same layer as inductor Place buck channels 0 2 4 near balls J15 to P15 Place boost channels 1 3 5 6 near balls B15 to H15 Place buck boost channel 7 near ball B15 Place sense resistors near balls M1 to 9 There should be one ground plane split such that all VRET x returns are in one half and all other returns are in the other half including DVSS and AVSS For layouts with no ground planes not rec ommended tie all output channels together at the output capacitors with a star connec tion From this star connection run a ground trace to all FS1610 signal digital and LDO ref 34 PRELIMINARY Rev 6 2 Aug 06 FS1610 erences Run a separate trace to each output RET x pad If using dual or complementary MOSFETs for two different channels channels should be adjacent and output voltages should be of similar voltage rating Minimize the loop areas of each channel in cluding bypass capacitor MOSFET diode in ductor output capacitor and return path Keep switch net short and on one layer wit
19. checked against Vetmin value read from EEPROM VPG Note 2 VBAT VSWIZ IN Note 6 VSW 2 IN Note 4 Notes O Measured from active trigger until the first enabled supply reaches its power good threshold De asserted trsto after EEPROM specified set of voltage rails reach their power good threshold Mlustrates several voltage rails being activated in sequence per parameters read from configuration EEPROM The input at VSW 2 IN is routed to VBAT when SW 2 is in regulation This is an open drain output The transition on this signal indicates the time when the internal driver floats the output The actual waveform will depend on external connection at this output On cold boot VBAT is connected to SW 2 IN during this period If SW 2 IN is connected to SW 2 output the output at VBAT will be 0 during this time For subsequent entries to SHUTDOWN state an EEPROM option can be used to connect VBAT to either SW 2 IN or BATBU during this period Figure 19 Cold Start Power up Timing Diagram Reset Outputs The FS1610 provides dual reset outputs The nIRSTO output is intended for the Intel PXA27x or similar processors that do not support assertion of power on reset subsequent to activation of their core and power rails nIRSTO is asserted under the following conditions When a valid trigger event occurs during the cold
20. is not in or READY states 2 Active Output internal active pull up OD Output Open Drain an external pull up is required AOD Output Active Open Drain when transitioning from Low to High the output is driven High to 2 5V for one clock period before it is set to open drain condition a weak external pull up is required to take the signal all the way to the desired rail PD Input pull down not PRELIMINARY FyreStorm Inc 15 Rev 6 2 Aug 06 Q FyreStorm POWER STATES Figure 9 illustrates the power states of the FS1610 Table 2 summarizes the state transition events OPERATION Note The polarity or active state of some signals de scribed in this section may change if the default configura tion Table 1 is changed SERIAL INTERFACE AND STAND ALONE MODES NOPOWER VBaTBU The FS1610 can operate in two modes Serial Mode In this mode of operation the de SHUTDOWN vice communicates with and can be remotely managed by a host processor an UART interface The type of serial interface the port address and the UART baud rate are speci READY fied in the configuration EEPROM Stand alone Mode In this mode of operation ACTIVE the device is initially configured via the internal EEPROM and the system uses external pins to control the device Since the serial interface is not operating som
21. start power up sequence Figure 19 When the manual reset input nRSTI in asserted The nRSTO output is intended for processors that require their reset input to be asserted until appropri ate power rails are active and valid This output is asserted under the following conditions Shortly after a valid trigger event It is then de asserted trsto after all the power rails designated in the EEPROM to trigger this action have reached their POK threshold PRELIMINARY FyreStorm Inc Rev 6 2 Aug 06 26 251610 When the manual reset input nRSTI in asserted When the WDT timer expires When the device transitions from ACTIVE or LOWPOWER states to SHUTDOWN state For the last three events the signal de asserts automatically Manual Reset Input The Manual Reset input nRSTI is used to initiate a hardware reset that can be used as a system reset for the host CPU Assertion of nRSTI will trigger as sertion of the nIRSTO and nRSTO outputs for and trsto respectively as shown in Figure 20 Note that the interface is reset at the rising edge of tRSTO Thus if the host initiates an HSI command transmission on the between the trailing edge of nIRSTO and the trailing edge nRSTO it will be lost nRSTI 100 mS nIRSTO tirsto nRSTO 65 mS typ 4 trsto 0 65 535 mS Figure 20 Manual Reset Timing FAULT MANAG
22. this mode is ig nored Table 6 summarizes the transition conditions into and out of the LOWPOWER state PRELIMINARY Rev 6 2 Aug 06 Q FyreStorm Table 6 LOWPOWER State Transitions From Condition Note To Condton Note ACTIVE L Htansiton of the nLOPWRpm _ Notes 1 SWIO and or SW 2 must be enabled 2 FS1610 waits until SW 7 6 5 4 3 1 are disabled be fore it begins the transition to LOWPOWER state 3 To ensure that a pending interrupt is not missed because of this transition by a host such as the PXA270 that handles wake up interrupts only once in sleep mode an EEPROM option causes the device to pulse nINTR once at the end of the transition if an interrupt was pending at the start of the transition Shutdown Restore When the FS1610 enters SHUTDOWN from ACTIVE or LOWPOWER states it stores the voltages of SWIA 2 0 and the LDOs and the current of SW 6 If the Shutdown Restore option is enabled via the EEPROM those stored values override the values read from the EEPROM during the transition to AC TIVE state Thus their outputs will be at the same values they were at before going to SHUTDOWN BUCK CONVERTERS SWI A 2 0 These three power rails Figure 10 use a patented digital control algorithm to provide a high efficiency step down converter implementation The output voltage of these converters is program mable from 0 85 V to 3 3 V Each converter is inde pendently pro
23. B is asserted during a dead battery condition This output typically connects to the Battery Fault host processor input Note If ADPTR is active nDB is not asserted and any of the actions described above relative to dead battery detection will not take place The VBAT output is provided for use in Intel PXA27x or other applications requiring a power source during Sleep conditions internal switch connects the voltage from SW 2 IN to VBAT when SW 2 is active and in regulation Otherwise the switch supplies the VBAT output from BATBU Thermal Shutdown While in ACTIVE mode the FS1610 monitors its junc tion temperature to prevent possible damage to the IC due to thermal overload There are two over temperature conditions that are monitored the junction temperature exceeds Tra this state is latched and nINTR is asserted if so programmed so that the processor can perform an orderly shutdown of high power supplies If the junction temperature exceeds then all power supply channels are shut off immediately nRSTO is asserted and the FS1610 transitions to the SHUTDOWN state Hysteresis is built into each thermal threshold to pre vent multiple redundant alarms INTERRUPTS The FS1610 provides an interrupt capability that can be used to alert the host of conditions requiring its attention such as a low battery condition a power rail fault or an RTC alarm The interrupt facility is handled by serial comman
24. BALLS IN HIGHLIGHTED AREA ARE FOR HEAT BOTTOM VIEW DISSIPATION ONLY AND SHOULD BE CONNECTED TO GROUND PLANE MAX Dimensioning and tolerancing per ASME Y14 5 1994 All dimensions are in millimeters Dimension represents the solder ball grid pitch Symbol represents the basic solder ball matrix size and symbol N is the actual number of balls after depopulating Dimension 0 is measured at the maximum solder ball diameter in a plane parallel to Datum C Primary Datum C is defined by the crowns of the solder balls 7 Package surface shall be matte finish Charmilles 24 to 27 8 Substrate material base is BT resin 9 The outline drawing is referenced to JEDEC specification MD 207 issue G 10 Ball matrix variation CR 2 pe ONS PRELIMINARY FyreStorm Inc 33 Rev 6 2 Aug 06 FS1610 PACKAGE MARKING NOT TO SCALE COMPONENT AND PCB LAYOUT GUIDELINES Careful component selection and proper PC board layout techniques are very important for successful power management design MOSFETs must have the right breakdown voltage threshold voltage and RDSon Inductors must not saturate on peak current significantly higher than output current Capacitors must use the right dielectric and be properly de rated The PC layout must implement the FS1610 in put output voltage sense strategy correctly and be grounded properly Improper components or poor layout can affect performance and disr
25. EMENT POK Status Each power rail can be programmed via the EEPROM to be monitored by the POK output signal This initial setting can subsequently be changed via serial commands if required If a monitored power rail is not in regulation whether it is enabled or not the POK output is de asserted An internal delay is implemented before the POK status is latched within the FS1610 to prevent false indications see Fault Delay in next section Power Rail Fault Monitoring The FS1610 monitors the status of each power rail except VBAT any enabled rail indicates an out of regulation condition the device will make one of sev eral possible responses as programmed for the rail in the configuration EEPROM PRELIMINARY Rev 6 2 Aug 06 Q FyreStorm Table 7 summarizes the fault conditions and re sponses for each power rail All constant voltage CV switcher power rails have over current protec tion with a limit value that can be programmed in the EEPROM SW 6 the constant current CC Boost channel has over voltage protection with the protec tion threshold configured in the EEPROM Note The Buck channels that operate in LOWPOWER mode SW 0 SW 2 have a separate programmable current limit used during that mode of operation Table 7 Channel Faults and Response Options Fault Response Options oO sc cis A 5 LLI Wi rm
26. EN 2 Output Voltage High Side Sense Switcher 2 LSEN 2 Output Voltage Low Side Sense Switcher 2 Input Voltage for internal VBAT switch connection Typically connected to the out SW 2 IN put of SW 2 Supply Input Switcher 3 and Switcher 1 Connect a bypass capacitor between this G14 VIN 31 Supply Return Switcher 3 LSD S Low Side Drive Switcher 3 HSEN 3 Output Voltage High Side Sense Switcher 3 Shutdown Disconnect 3 This output is used to reduce leakage current via the resis O SDDISI 3 tor divider on the output of SW 3 SDDIS 3 turns on prior to the output ramping up when SW 3 is enabled and turns off high impedance after the output goes below VIN when SW 3 is disabled la la la 15014 Low Side Drive Switcher 4 When SW 4 is turned off the low side driver will dis charge the output capacitance at a rate programmable via the configuration EEPROM Shutdown Disconnect 5 This output is used to reduce leakage current via the resis SDDIS 5 tor divider on the output of SW 5 SDDIS turns on prior to the output ramping up when SW 5 is enabled and turns off high impedance after the output goes below VIN when SW 5 is disabled VIN 65 Supply Input Switcher 6 and Switcher 5 Connect a bypass capacitor between this pin and VRET 6 Shutoff Disconnect This output is used to reduce leakage current via the resis
27. HER 3 BOOST CONVERTER SWITCHER 5 BOOST CONVERTER VOLTAGE RAIL SENSING numbered bits e g D 7 D 6 D 0 the family of bits may also be shown collectively e g as D 7 0 The designation indicates a number ex pressed in hexadecimal notation 0 1 2 9 A E F The designation ODXXXX indicates a number expressed in binary notation X O 1 Ma Continuous power dissipation Continuous power dissipation Junction temperature Operating ambient temperature range 20 Notes 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only func tional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not im plied Exposure of the device to Absolute Maximum Rating conditions for extended periods may affect device reliability PRELIMINARY Rev 6 2 Aug 06 FyreStorm Inc 3 ESTEE Q FyreStorm Electrical Parameters General 20 C to 85 C unless otherwise noted Typical values are at T4 25 C and VIN 3 6 Symbo Conditions min Uni Input voltage VMAIN VIN VIN O VIN 2 VIN 4 28 55 VIN 7 VIN 31 VIN 65 VBIAS LDO2 input voltage 1 ww Input voltage IN Do
28. Incremental operating current VIN pin SW 7 Rail enabled static load Rail enabled switching at Incremental supply current at VIN xy pin Current limit as percentage of programmed output Vea threshold POK response time to out of regulation program ming range Input leakage current HSEN AT B7 5 3 1 LSEN T 5 3 1 d A A L N Output sequencing turn off threshold Output is disabled VIN EE PRELIMINARY FyreStorm Inc 7 Rev 6 2 Aug 06 Q FyreStorm FS1610 Electrical Parameters A Input VIN 3 0 5 5 V Ta 20 to 85 C unless otherwise noted Typical values are at T4 25 C and VIN 3 6 Paamte O Mm Max Unit E Measurement data quantization Range is EEPROM Range 0 1975V ange0 55V measurement dstaaccuraey 88 Electrical Parameters VBAT Switch VIN 3 0 V 5 5 V Ta 20 to 85 unless otherwise noted Typical values are at T4 25 C and VIN 3 6 lati V Output voltage VBAT SWI2 on and in regulation SWI2 off or out of regulation Ve Wenn 0 1 Switch is the internal SPDT switch that connects BATBU or SW 2 IN to the VBAT output AC Electrical Parameters VINA VIND 3 0 V 5 5 V Ta 20 C to 85 unless otherwise noted Typical values are at
29. NCTION PIN FUNCTION PIN FUNCTION x2 ___ 2 __ 4 VRETI 115 2 ADPTR DET DVD 2 NC 5 VINO 86 A13 15 150 6 Jf VINSENH P2 1 R8 500 5 3 14 4 01 J VINSENL LSEN4 R9 SDDIS 6 B2 GNDLDO 3 015 K1 P6 12 EE SDA B4 RTOVSS E2 VBIAS LDO2 Ki4 LSD4 SDDISI RI4 TESTE 85 DBOUT 5 5 VvRET4 P9 SDOISS 15 TESTI Be SW ZIN _ E15 18015 Li DAS BYP2 10 niRSTO PRELIMINARY FyreStorm Inc 2 Rev 6 2 Aug 06 FS1610 FS1610 BLOCK DIAGRAM CRYSTAL OSC amp CLOCK GENERATOR ance NW 38 STATUS RESET 5 CONTROL VOLTAGE REFERENCE WHLED BRIGHTNESS OR GP A D INPU 5 Unless otherwise noted a positive logic active High convention is assumed throughout this document whereby a positive voltage causes assertion of an input signal and indicates an asserted output sig nal An n preceding the signal name e g nINTR indicates that the input or output signal is asserted in a Low state Vi Whenever a signal is separated into ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Q FyreStorm SWITCHER 1 BOOST CONVERTER SWITC
30. Output UART Serial mode RxD Serial Data Input B7 BATBU Backup battery input A voltage must be present on BATBU in order for the device to operate Connect a bypass capacitor from this pin to RTCVSS PRELIMINARY FyreStorm Inc 11 Rev 6 2 Aug 06 ESTEE Q FyreStorm Type Wme Keep Alive Supply output is the first supply to be active and the last to power off It is compliant with the Intel PXA27x specifications B8 VBAT VBAT 5 2 if SW 2 is enabled and within regulation BATBU if SW 2 is disabled out of regulation See COLD START POWER ON SEQUENCE for additional information Dead Battery Output This pin is asserted when VMAIN is below the dead battery R11 nDB threshold and an AC adapter is not present This pin typically connects to the Battery Fault host processor input Refer to Table 1 if not used Disconnect Battery Output active high This output is asserted when a DB thresh 5 O DBOUT old is detected at VMAIN unless in ACTIVE mode or if the presence of an AC adapter 2 is detected at IN is meant to connect an external P channel FET switch to disconnect the main battery attery condition See Figure 21 s P VN Input Main power supply input P ND MenSupyReum _ er P Loom supy Reim OOOO O P _ O P
31. Ta 25 C and VINA VIND 3 6V ______ Conditions Unit o pee STaRTanasror _ e powera 7 e mme Fepeated START condition setupime _ Real Time Clock Timing Granularity 2 o 4 4 1 ___ 0 Alam Setting Accuracy NENNEN Alarm latency Alarm triggered to nINTR output asserted Watch dog Timer Timing ms EK EN o e output asserte PRELIMINARY FyreStorm Inc 8 Rev 6 2 Aug 06 Um er Q FyreStorm symbol Parameter Conditions Mm Unit Crystal Oscillator Input OnstalFrequeny Tek 30498 ___ ___ V O eacee O mamie 18 1 For accurate timekeeping with the RTC and WDT a crystal frequency of 32 768 KHz 100 ppm should be used 100 4 10096 Efficiency Efficiency 0 0 0 1 1 10 100 1000 0 1 1 10 100 Load Current mA Figure 1 Typical Buck Converter Efficiency Figure 3 Typical Buck Converter Efficiency Normal Mode Vin 3 9V Low Power Mode Vin 3 9V 100 100 80 3 0V 80 Vo 3 0V Vo 2 5V GEE
32. ail can be enabled or disabled by serial command This should not be used to con trol rails that are controlled by PWREN 5 0 Note a channel that is part of PWREN group is turned ON individually by a command a subsequent PWREN group disable command may not turn it off Note The PWREN 5 1 inputs are edge triggered A low high transition enables the power rail group a high low transition disables the group Note The FS1610 permits a maximum of 11 in stances of power rails in PWREN 5 0 Thus for ex ample if one rail is placed in three groups only 8 of the remaining 10 rails can be controlled by PWREN 5 0 and the remaining two rails if used have to be controlled by single rail enable disable serial commands When group of supplies mapped to PWREN 5 0 is enabled or disabled a programmed load activa tion shedding sequence defined in the configuration EEPROM is activated for that group of supplies This is illustrated in Figure 15 ims 4 1 ON Threshold Supply 1 ON Threshold OFF Threshold OFF Threshold Supply n 1ms Note For turn on sequencing delay can also be configured to start when previous is enabled Figure 15 Power Sequencing FyreStorm Inc 21 251610 As illustrated the supplies within the group sequence each other on and off This ensures that any number of supplies is well controlled wi
33. an out of regulation condition on any supply or upon an 1857 event Refer to Table 1 if not used Intel Power On Reset Output nIRSTO is asserted for tinsro during initial power up nlRSTO See COLD START POWER ON SEQUENCE Connect to nRESET of Intel PXA27x processors It is also asserted upon an nRHSTI active event if the WDT expires and when the chip transitions to SHUTDOWN state Refer to Table 1 if not used Manual Reset Input If this input is asserted nRSTO and nIRSTO are asserted These outputs remain asserted until tasto and tinsro respectively after nRSTI is deas nRSTI serted and the de bounce interval trsti is completed No power rails are modified An internal pull up resistor is provided driven from logic it must be driven from an open drain output to prevent reverse leakage current PRELIMINARY FyreStorm Inc 10 Rev 6 2 Aug 06 EHE 4 FyreStorm Pin No Type Mme _ Power OK Output POK is asserted when all the rails specified in the EEPROM to be B10 POK monitored by this status signal are above their regulation thresholds Refer to Table 1 if not used External Power On Input An internal de bounce filter and a pull up resistor are pro P11 nEXTON vided If driven from logic it must be driven from an open drain output to prevent re verse leakage current ADPTR AC Adapter Present An input at the specified level indicates that an AC adapter is present Adapter Detected Output
34. attery If the presence of an AC adapter is detected the ADPTR_IN input the FS1610 reads the con tents of the configuration EEPROM and checks whether this condition is programmed to wake up the chip If it is the boot up process continues at step 7 below Otherwise go to step 5 below AC adapter is not connected the chip re mains in the SHUTDOWN state monitoring the VMAIN input for a valid main battery voltage us ing the default dead battery voltage of 3 1V asa reference The FS1610 now waits until it detects a Low at the nEXTON input to continue the initial power on sequence FS1610 reads the contents of the configuration EEPROM and checks whether the TIMED WAKEUP option is enabled If it is it continues to monitor nEXTON to check if it re mains low for the time specified in the ExtOn Timeout parameter read from the EEPROM the test fails the 51610 returns to SHUTDOWN If it passes or if the TIMED WAKEUP option is not enabled the initial boot up process continues The following actions occur during the initial boot up sequence o nDBis de asserted o The reset output nIRSTO is asserted for tIRSTO and the nRSTO output is asserted o POKis driven Low indicating that one or more power rails are not in regulation o BATBU is routed to the VBAT output to serve as a Sleep power source for the host proces SOr Note The VBAT output is intended primarily as the Sleep power source VCC_BATT for
35. ds Table 9 provides an overview of those commands The commands dealing with interrupts are B Get Status Shows current status of the device Additional bytes in this command are related to the supply fault event and show the specific power rails in fault if any FyreStorm Inc 28 FS1610 B Clear Status Clears designated bits in the de vice status register B Enable Disable Interrupt Used to enable se lected status conditions to assert the nINTR out put from the device All status bits are cleared and interrupts are disabled during a cold start power up Subsequent to this the Q FyreStorm enabled disabled interrupt status is saved when the chip goes to SHUTDOWN state and automatically restored when the chip next transitions to ACTIVE state The signal itself is active only during READY LOWPOWER and ACTIVE states Refer to the Host Serial Interface User Manual for a complete list of status conditions and a full descrip tion of all commands AC x ADAPTER NE DT MAIN BATTERY ADPTR VMAIN DBOUT VIN ADPTR DET FS16xx nDB VBAT BACKUP BATTERY SWI2 IN BATBU i Figure 21 Battery Switching Circuit PROGRAMMING Programming of the FS1610 is done via a set of reg isters that configure control and provide status for the device These registers are subdivided into sev eral classe
36. e device features will not be LOWPOWER available POWER MANAGEMENT Low power is a top priority the FS1610 Nothing on Figure 9 FS1610 Power States the device is active unless its operation is required To minimize power consumption clocks are gated at their sources and parts of the device are completely powered down if not operating Table 2 FS1610 State Transitions NEXT STATE CURRENT STATE NOPOWER SHUTDOWN READY ACTIVE LOWPOWER NOPOWER lt _ Voss lt 00 00 Bl gt Veuin gt 10 seconds and All voltage rails dis voltage rails dis rails enabled abled abled nEXTON goes HIGH Power rail fault Note Power rail fault Note before programmed 2 2 SHUTDOWN timeout Note 2 E Shutdown command Dead battery or SD pin assertion alarm nEXTON input at LOW level Note 2 B LOWPOWER Notes 1 This table is a general overview only See detailed descriptions that follow for additional details 2 EEPROM option alarm PWREN 1 asserted level AC adapter detected Note 2 PRELIMINARY FyreStorm Inc 16 Rev 6 2 Aug 06 ESTEE Q FyreStorm NOPOWER State In this state the backup battery is below the threshold value required for operation of the device The inter nal circuits have insufficient power to operate Table 4 SHUTDOWN State Transi
37. grammable to be enabled by one of the PWREN enable inputs by a serial command or via the configuration EEPROM The buck converters support several features that may be required in the system application Soft Start Each regulator includes a soft start circuit that limits start up inrush current to a value specified in the con figuration EEPROM Dynamic Voltage Management DVM 4 2 0 support the ability to alter their output voltage with a prescribed ramp interval If this mode is enabled the voltage ramp is initiated when a new target voltage is programmed Figure 11 depicts the timing for transitioning between voltages The step size is programmable in increments of approximately 5 mV to a maximum of 300 mV The time between steps is programmable in increments of approxi mately N x 7 6 us where N is a value from O to 31 FyreStorm Inc 18 251610 N 0 or when this mode is disabled the voltage transition to the final value is made without any inter mediate steps If a serial command to change the voltage of a rail operating with DVM enabled is received while a pre viously requested voltage change is in progress the new command will be rejected NAK VIN VIN n HSDIn V n our LSD n VRETIn HSEN n LSEN n FS16xx Figure 10 Buck Converter SW 4 2 0 5 300 mV Target Vout Initial Figure 11 Dynamic Voltage
38. h no vias Buck 0 2 4 switch net connects 2 MOSFET drains and inductor Boost 1 3 5 7 switch net connects MOSFET drain diode anode and inductor Buck Boost 7 switch net connects MOSFET drain diode cathode and inductor Wide traces on all switch nets 20 mil 0 5 mm average and very short Wide traces on all power supply return ref 20 mil 0 5mm average Multiple vias should be used for power FETs diodes inductors and output capacitors to reduce impedance Output and bypass capacitors route traces directly to capacitor pad Do not add traces in series with capacitors All sense nets do not route directly beneath power FETs diodes or inductors Use ground plane as intermediate shield between sense nets and FETs diodes and inductors FyreStorm Inc Q FyreStorm Input capacitor sense Route VINSENH directly to positive side of input Capacitor Route VINSENL directly to negative side of input Capacitor Buck channels 0 2 4 sense Route HSEN x net directly to output capacitor positive side Route LSEN x net directly to output capacitor ground side Boost channels 1 3 5 6 sense Route divider resistor net directly to output ca pacitor positive side Route LSEN x net directly to output capacitor ground side Buck boost channel 7 sense Route divider resistor net directly to output ca pacitor negative voltage Route LSEN x net directly to output capacitor ground side
39. h to Low e TIMED ACTIVE SHUTDOWN if this option is turned On and the device is in ACTIVE state and nEXTON goes from High to Low and stays Low for the time specified in ExtOnTimeout the chip will transition from ACTIVE to SHUTDOWN states via a simultaneous shutdown of all Power Enable groups with specified sequencing within each group If this option is turned Off bringing nEXTON Low while in ACTIVE state has no ef fect on the power rails COLD START POWER ON SEQUENCE The FS1610 performs a pre defined startup se quence upon initial power on The chip s startup power supplies are powered via the BATBU input supply which must be connected and at or above Veum order to guarantee that the device begins operation noted previously application of the main battery power Vyam Viy by itself will not initiate device startup Refer to the simplified flow chart Figure 18 and the timing diagram Figure 19 for the following discussion 1 An internal power on reset POR cycle is initi ated when BATBU reaches the operational threshold The following events occur this time is asserted VBAT is kept off PRELIMINARY Rev 6 2 Aug 06 FyreStorm Inc Q FyreStorm o All RTC time values and alarms are cleared and the RTC is enabled The FS1610 enters the SHUTDOWN state In this state most internal subsystems are powered and the FS1610 draws very little power from the backup b
40. hese parameters is independently program mable for each channel from 0 255 ms the EEPROM The auto restart activity is repeated until the fault is removed or the channel is disabled by the host If a channel is shutdown and not configured to auto restart it can be restarted by toggling the respective external power enable input or by a serial command A power rail fault event can be programmed to gen erate an interrupt to the host controller The host can then use a serial command to determine which rail s experienced a fault A power rail fault can also be configured to assert the nRSTO output independently for each channel When the fault causing that assertion is cleared nRSTO will de assert after its programmed duration Battery Voltage Monitor and Backup Battery The battery voltage monitor periodically checks the voltage at the main battery test input VMAIN There are three battery states defined Battery good low battery LB and dead battery DB The LB and DB thresholds are EEPROM programmable Internal aver aging and hysteresis prevent nuisance tripping when the battery voltage is near the LB and DB val ues When VMAIN falls below the low battery threshold nINTR if so programmed and the LB output are asserted If the 51610 is in ACTIVE or LOWPOWER states when VMAIN reaches the dead battery threshold the FS1610 automatically shuts down the power rail groups des
41. ignated in the EEPROM PWREN 5 0 An EEPROM option also determines whether this follows the programmed sequencing or is an immediate shutdown of the rails in the specified power rail groups The FS1610 remains in the AC TIVE or LOWPOWER state with other enabled power groups or individually enabled power rails still active in order to allow the host to perform an orderly shut down of the system When the host subsequently disables the enabled power rails and power rail groups the FS1610 will transition to SHUTDOWN state If the 51610 is in LOWPOWER state when is detected internal switches route power from BATBU to VIN to supply the active power rails The DBOUT PRELIMINARY Rev 6 2 Aug 06 Q FyreStorm output is asserted during that time and should be used to switch the main battery out of the circuit while power is being routed to VIN from BATBU See Figure 21 NOTE dead battery condition occurs while in LOWPOWER mode and a request for a transition to ACTIVE mode is re ceived the FS1610 first checks the battery condition It does not complete the requested transition until four consecutive tests taken at 250 ms intervals indicate that the battery is not below the dead battery threshold DBOUT is also asserted if the presence of an AC adapter is detected the ADPTR IN input In that case the battery is switched out of the circuit and VIN is supplied from the adapter via an isolation diode nD
42. is enabled the device section 3 above enters the ACTIVE state and the voltage rails are PRELIMINARY FyreStorm Inc 24 Rev 6 2 Aug 06 Q FyreStorm NOPOWER e Boot internal system controller e Boot internal system controller e Load EEPROM configuration e Load EEPROM configuration parameters parameters FS1610 VBATBU gt 2 WAKEUP YES e Internal POR cycle SHUTDOWN e Set ADPT TESTRES to FALSE ADPTR IN YES Set to TRUE by POR e Turn off system controller Wake up on nEXTON stays Low for gt xtOnTimeout YES READY e Enable all internal sub systems e Turn on EXTPEN output e Start READY state 10 second time out e Enable PWREN O0 voltage rails if any YES VMAIN Default YES ADPTR IN READY state time out expired e f gt H transition on PWREN 5 1 enable rails controlled by those signals Any voltage rail enabled YES e urn off READY time out ACTIVE Figure 18 Simplified Cold Start Power up Flow Chart PRELIMINARY FyreStorm Inc 25 Rev 6 2 Aug 06 FS1610 Q FyreStorm powersrares norom OE i de Note 1 ACTIVE TRIGGER VBUMIN BATBU checked against default 9 VMAIN VBTMIN VIN Note 5 VOUT n Note 3 wes ULL VIN
43. l Parameters LDO Regulators 3 0V 5 5 V Ta 20 to 85 C unless otherwise noted Typical values are at Ta 25 and VIN 3 6V Cour 0 47 UF unless oth erwise specified symbol Conditions Typ Max Unit LDO 1 LDO 3 output votageprosrammingrange Output programming reson Jo w votage accuracy _________ 05 wewuwdap ems m 9 MWemmomaumn 11 curer MO _______ ria ___ W tr response time to out of regulation program 1 255 ms ming range Resr lt 50 lt 3 nH 470 1000 2200 nF 1 Mhz lt f lt 50 MHz LDO 2 Output voltage programming range Output voltage programming resolution lour 0 to 60 mA _ _ Output voltage change under load Court 2 2 pF 5 35 50 PRELIMINARY FyreStorm Inc Rev 6 2 Aug 06 Q FyreStorm _ Max Unit menm __ CT ___ __ VBIAS 1002 3 3V uV 10 Hz f 100 KHz 9021 RMS Quiescent current VBIAS 1002 Enabled no load ___ 45 tbd LDO disabled Risi threshold Rising Ss Tl Falling ___
44. n it receives an Enable WDT serial command from the host Expiration of the WDT asserts nRSTO for testo To ensure that this event does not occur the Host must reset the WDT before the programmed time out pe riod expires The WDT is reset upon receipt of any valid serial command addressed to the device see Table 9 FS1610 Command Set Overview or if so configured via any transition at the input in stand alone mode or serial mode Note The WDT does not operate LOWPOWER mode and is not reset when the FS1610 transitions from LOWPOWER to ACTIVE modes To prevent in advertent expiration of the WDT when returning to AC TIVE mode it is recommended that the WDT be reset before placing the device in LOWPOWER mode PRELIMINARY Rev 6 2 Aug 06 Q FyreStorm POWER CONTROL AND SEQUENCING The FS1610 provides multiple levels of power on off sequencing via a very flexible scheme to control and sequence power of all voltage rails Any number rails can be programmed via the EEPROM to be automatically turned on when the device is loaded with the EEPROM contents when entering the READY state Any rail thus enabled is said to belong to PWREN O group These rails are disabled when transition ing to the SHUTDOWN state after a SHUTDOWN command or assertion of the SD input Groups of rails can be programmed to be con trolled by the PWREN 5 1 inputs or by equivalent serial commands single r
45. ng the cold start power up XTAL 18 pF I 0 2 T 18 pF XTAL Tuning fork type 32 768 KHz Citizen CFS 308 or equivalent X1 CLKOUT FS16xx Figure 16 Crystal Oscillator EEPROM options can be used to enable or disable CLKOUT after the first time that the device enters the READY state as follows e Always off e Always on PRELIMINARY Rev 6 2 Aug 06 Q FyreStorm e Always on except in SHUTDOWN mode when it is turned off onif nDB 1 off if nDB 0 BACKUP BATTERY INPUT The FS1610 has a separate input for a backup bat tery BATBU for use if the main input VIN is not pre sent As described previously a voltage must be present on BATBU in order for the device to operate Normally a primary or rechargeable backup battery is connected to this pin If a backup battery is not used then BATBU should connect to VIN through a diode or external regulator See Figure 17 and Figure 22 If the voltage of the main battery falls below the dead battery threshold and if the device is operating in LOWPOWER mode the device will be powered from the backup battery if gt See Battery Voltage Monitor and Backup Battery section for addi tional information Main Supply Input To System a No Backup Battery Main Battery BATBU VBAT Rechargeable FS1610 Backup Battery b To Support Intel PXA27x To System Figure 17
46. nverter is illustrated in Figure 13 Q FyreStorm VIN V nlour VIN nm LSD n VRET n LSEN n HSEN n SDDIS n FS16xx Figure 13 Boost Converter SW 5 3 1 LOW DROP OUT REGULATORS LDO 3 1 These linear regulators are designed for low quiescent current operation and incorporate internal pass transis tors All are fully programmable by software commands LDO 2 provides low noise performance via a bypass capacitor Each LDO has a separate input voltage pin that allows the input to be selected to maximize system efficiency Shutdown Restore can be enabled for the LDOs the EEPROM See Shutdown Restore section The LDOs can operate during LOWPOWER mode Note The LDO should be disabled before command ing an output voltage change and then re enabled Failure to do so may result in an LDO fault condition See Power Rail Fault Monitoring for fault handling op tions BUCK BOOST CONVERTER SW 7 This power rail illustrated in Figure 14 is a high efficiency switching converter operating in a step up configuration and is capable of supplying a negative output voltage of 20 V maximum The output voltage is specified in the EEPROM and cannot be changed dur ing operation VIN V 7 our VRET 7 HSD 7 VIN 7 4 LSEN 7 HSENA 7 HSENBI7 FS16xx PRELIMINARY FyreStorm Inc 20 Rev 6 2 Aug 06 FS1610 Figure 14 Buck Boost Converter SW 7 VBAT
47. ocessor via the device s or UART serial port Load activation and shedding profiles can also be specified in the EEPROM and by the host The FS1610 is also capable of stand alone operation using the parameters loaded from the EEPROM at start up The FS1610 is provided in a space efficient 8 x 8 FBGA package APPLICATIONS Feature phones and smart phones Portable media players and MP3 players PDAs and hand held computers Digital still cameras and camcorders Other portable electronics equipment Data Sheet Revision 6 2 August 2006 FyreStorm Inc 2004 2006 FyreStorm Inc FS1610 Advanced Power Management Controller KEY FEATURES B Eight switching converters Three buck step down converters o Two converters available in Low Power mode for high efficiency at low load currents Three boost step up converters One buck boost step up converter for nega tive output voltage constant current boost White LED driver High efficiency typically 90 from 596 to 10096 of programmed maximum current in ac tive mode Converters drive external MOSFET s directly B Switching converters feature all digital loop control technology Real time analysis provides optimal power sys tem control and operation Precise supply to supply matching and tracking Programmable power up and down slew rates Programmable load connection and shedding Reduced component count yields smaller size
48. on the output of this converter SDDIS 6 turns on connecting the resistive divider to SEN ground prior to the output ramping up when the FyreStorm Inc 19 FS1610 converter is enabled and turns off high impedance disconnecting the resistive divider after the output goes below VIN when the converter is disabled Output Current Range Checking SWI6 limits the output current to minimum maximum values specified in the configuration EEPROM regardless of the value programmed into its current programming register The output current will not go below the specified minimum value or above the specified maximum value VIN VIN 65 LSD 6 VRETI6 LSEN 6 HSEN 6 SDDIS 6 FS16xx Figure 12 White LED Driver SW 6 BOOST CONVERTERS SW 5 3 1 These power rails are high efficiency switching convert ers operating in a step up configuration to supply posi tive output voltages of up to 25 V The output voltages for these rails are specified in the EEPROM and cannot be changed during operation The SDDIS n pin is used to reduce leakage current from the resistor divider on the output of these convert ers SDDIS n turns on connecting the resistive divider to LSEN ground prior to the output ramping up when the converter is enabled and turns off high impedance disconnecting the resistive divider after the output goes below VIN when the converter is disabled The boost co
49. onses Additional detail is in the HSI User Manual that is available upon request never sends an unsolicited message to the host The host issues commands and the FS1610 responds Table 8 FS1610 Command Response Structure Command Command code 3 _________ ACK 0x00 or NAK OxFF Optional byte 1 4 Optomlbye2 O 5 J Optionalbyte2 6 4 X 8 Checksum 2 s complement sum of previous bytes Checksum 25 complement of sum of previous bytes PRELIMINARY Rev 6 2 Aug 06 FyreStorm Inc 30 FS1610 Q FyreStorm Table 9 51610 Command Set Overview CIR Byte1 Byte2 4 Byte5 Byte6 Byte7 Description Enable Disable WDT _ 0x0 0x0 Checksum oo oo oxo0 Checksum N A Get Status 7 x2 INTRH status INTRLstatus SW Status LDO Status Checksum 0x04 0x03 N A C C 0x03 0x02 N A 0x07 0x43 MSBaam __ LSBalarm Checksum 0x06 0x44 MSBaam __ LSBalarm Checksum 4 0x03 0x02 N A 0x07 0x47 0x00 MSBRTC LSBRTC Checksum 0x06 0x48 MSBRTC LSBRTC Checksum N A 0x03 0x04 0x05 0x61 0x62 0x62
50. s Configuration Registers These are read from the internal EEPROM at power up and set various options for device operation These configuration options can not be changed by host commands during operation Channel Control Registers These have an initial setting that is loaded from the EEPROM at power up but can be written by the host PRELIMINARY Rev 6 2 Aug 06 FyreStorm Inc processor via serial interface commands during de vice operation These registers are specific to a power channel although different types of channels may have different registers Device Control Registers These registers control chip functions that are not typically channel specific They have an initial setting that is loaded from the EEPROM at power up but can be written by the host processor via the serial interface during device operation Device Status Registers These provide device status to the host processor The status is transmitted to the host via the serial in terface in response to a status read command 29 FS1610 SERIAL COMMANDS The serial interface between the host CPU and the FS1610 is command response interface The FS1610 acts as a slave device on the serial bus and Q FyreStorm Commands range from three to eight bytes in length and responses from four to eight bytes in length Table 8 summarizes the serial command and re sponse structures Table 9 provides an overview of the commands and corresponding resp
51. s detected 7 Notes If AC adapter not detected If channel fault is configured to shutdown the chip If VMAIN Not during a cold start boot The last commanded values for the output voltages of 5 4 2 0 LDO 3 1 and the last commanded current for SW 6 are saved See Shutdown Restore section for additional informa tion 6 The FS1610 reads the contents of the configuration EEPROM and the transition to READY state continues if VIN is above the Minimum Voltage to Boot value read from the EEPROM If it is not the device returns to SD state 7 if Wake on IN option is enabled via the EEPROM 8 If the TIMED ACTIVE SHUTDOWN EEPROM option is en abled 9 Ifthe TIMED WAKEUP EEPROM option is disabled 10 If the TIMED WAKEUP EEPROM option is enabled 11 Only if Wake on ADPTR IN option is disabled via the EEPROM ACTIVE State This is the normal operational state The RTC and Vpp Power Domains are active The serial interface begins operating at the conclusion of the RSTO time out This timeout expires after the set of voltage CO D pru m FyreStorm Inc 17 51610 rails specified in the EEPROM are enabled reach POK status Table 5 summarizes the transition conditions into and out of the ACTIVE state Table 5 ACTIVE State Transitions Transitions into ACTIVE State From Condition One or more power rail
52. s enabled IM READY via PWREN inputs or by initial con figuration setting LOPWR L Htransition ofthe nLOPWR pn Transitions from ACTIVE State To Condition Note LO PWR PWREN group 0 are disabled SHUTDOWN A Shutdown command is received or the SD pin is asserted nEXTON goes from High to Low and stays Low for the time speci fied in the ExtOnTimeout EEPROM variable Notes 1 SW 0 and or SW 2 must be enabled 2 The FS1610 waits until SW 7 6 5 4 3 1 are disabled be fore it begins the transition to LOWPOWER state 3 The last commanded values for the output voltages of SW 4 2 0 LDO 3 1 and the last commanded current for SW 6 are saved See Shutdown Restore section for additional informa tion 4 If channel fault is configured to shutdown the chip 5 the TIMED ACTIVE SHUTDOWN EEPROM option is en abled LOWPOWER State In LOWPOWER state the RTC and Vpp Power Do mains are active Buck converters SW 2 0 operate in PFM pulse frequency modulation mode and are limited to 596 of their ACTIVE mode programmed maximum current This reduces their quiescent cur rent and improves efficiency at low load currents The LDO regulators and RTC operate normally but the WDT and serial interface are not operational An EEPROM option allows selected PWREN inputs to be disabled while in this mode An attempt to en able any power rail other than SW 2 0 or LDO 3 1 via a non disabled PWREN while in
53. th respect to each other regardless of load capacitance and ramp time Core and relationships are one example of where this mode would be useful The ON threshold Figure 15 is the internal POK sig nal for every supply Also note that the ON sequence delay can start from when a rail is enabled rather than from its POK The OFF threshold is EEPROM configurable for switchers 2 0 VIN 0 4 V for switchers SW 5 1 and SW 6 For SW 7 the same as the SW 0 OFF threshold programmed in the EEPROM There is no OFF Threshold for LDO 3 1 and the turn off delay for the next voltage rail begins immedi ately after the LDO is disabled N can range from 0 to 255 and is independently pro grammable for each voltage rail transition Where N 0 the subsequent supply immediately begins its power on or power off cycle after the previous sup ply s output reaches its ON or OFF threshold CRYSTAL OSCILLATOR A crystal oscillator operating from a low cost 32 768 KHz crystal is used for all internal timing If a clock at the proper frequency and voltage is available in the system it may be connected to the X1 input and the crystal is eliminated Error Reference source not found illustrates the external connections required for this oscillator Capacitor values may be different for a different crystal A 32 768 KHz output is provided on CLKOUT for ex ternal use This output is initially enabled and thus is active duri
54. threshold based on thermal sensor Temperature rising 15 Thermal shutdown threshold based on thermal 115 sensor accuracy Logic Level Signals owpuiowvorgeAldgedoupus _____ PRELIMINARY FyreStorm Inc 4 Rev 6 2 Aug 06 lt ajal lt l lt afk 3 lt a i Q FyreStorm Symbo Conditions Unit When configured as active 20 Output High voltage All digital outputs unless oth outputs lou 4 2 4 V drain output OwpurHghvolapeCLKOUT __________ 1201124 V mughvege Aldgtaimus _____ __________ 36 326 mutiowwoag Aldglaimus Input leakage current All digital inputs except Input voltage 3 6 V 1 1 nRSTI and nEXTON Input voltage 0 V 1 __ 1 Output High leakage current All open drain outputs Output voltage 3 6 02 Input leakage current nRSTI and nEXTON Input voltage 2 5 V 1 1 pA Input voltage 0 V 1 is set to default value of 3 10 V during the internal power on reset cycle It may then be changed by data in the EEPROM 2 Debounce interval is measured from the last bounce detected 3 Based on 32 768 KHz crystal frequency 4 VIN VIN 2 VIN 4 VIN 7 VIN 31 VIN 65 must be at the same voltage Electrica
55. time they are configured as specified See COLD START POWER ON SEQUENCE and Table 1 PRELIMINARY FyreStorm Inc 14 Rev 6 2 Aug 06 ESTEE Q FyreStorm Table 1 Digital I O Configuration Options Serial F PinName Mode unction polarity Active OD AOD PD 2 Polarity Active OD AOD 2 b CLKOUT ANY CLKOT ACT ACT nRSTO ANY __ Y X ODAOD OD ___ JjSetto OD and connect to ground if not used ANY nRSTO ODAOD 9 Set to OD and connect to ground if not used 1 ANY nRSTI __ _ _ nEXTON nADPTR ANY nADPTR DET te 2 lt OD AOD Set to OD and connect to ground if not used OD AOD Set to OD and connect to ground if not used PWREN PWREN PWRENJ3 PWRENB ANY sa O_o Too oS T EE scL_ o ANY eso o oOo SooS OD OD and connect to ground if not used 1 N __ Leavefloatingitnotused lt Y PD Advel Noei jSelectinputpuldownoptonitnotused Active L Note t Select input pulldown option if no
56. tion 5 lout 0 to 300 mA includes mE Ouiput voltage accuracy ine and load regulation mE PRELIMINARY FyreStorm Inc 6 Rev 6 2 Aug 06 0 5 5 00 55 3 9 00 Ohm Ohm UA mV Hz mA Hz V ms V mV mV Q FyreStorm Parameter Conditions Mm Unit mE Incremental operating current at VIN pin Foi mwresagecwen 2 AU Ouiputcurent 25mA 24 aeneum ee M Outputcurent 25ma 48 63 Ohm ourer imit as percentage programmed _ Wes Pomesa POK response time to out of regulation program 1 255 ming range Output sequencing turn off threshold EEPROM 500 programmable Boost Regulators SW 1 SW 3 SW 5 Buck Boost Regulator SW 7 Output Voltage Accuracy Output current 0 30 mA 405 05 Output voltage programming resolution Of programmed range 25 4 h Output impedance LSD 5 3 1 Output current 25 m 2 4 3 1 m ms mV V V Output current 25 mA Output current 25 mA Output impedance HSD 7 Output current 25 mA T gt Output Low voltage SDDIS 5 3 1 outputs Switching frequency Incremental operating current at VIN pin SW 5 3 1 Rail enabled static load in lo 01 mA
57. tion If configured as WDRST any transition on this input will reset the Watchdog Timer and restart the programmed time out interval If configured as External Power Enable the output is asserted HIGH at the conclusion of the internal power up boot process before turning on any power rails and is de asserted when the FS1610 transitions to SHUTDOWN state after all F51610 power rails are turned off UART Serial mode TxD Serial data output Standalone Mode SD Shutdown Input When asserted the FS1610 disables all power enable groups PWREN 5 0 simultaneously The sequence of disabling the individual rails within each power enable group is as specified in the EEPROM Any rails that were enabled by serial commands and are not members of a power en able group are also disabled after all power enable groups have been disabled UART and Serial Modes nINTR Interrupt Output This pin is the output for all internally generated interrupts A read to the FS1610 via the serial bus provides the MFP 3 A15 I O Note 3 MFP 4 Note 3 status of the interrupt The interrupts include RTC alarm and Low battery detect See HSI User Manual for additional information Standalone Mode PWREN 5 Power Enable 5 input A group of power rails can be mapped via the EEPROM to be enabled disabled via this input See A9 5 PWREN 3 1 for additional information N Serial Mode SDA Data Input
58. tions Transitions into SHUTDOWN State Condition NOPWR A good backup battery VBATBU gt VBU MIN is inserted All voltage rails including rails in PWREN group 0 are disabled A channel fault occurs Table 3 summarizes the transition conditions into and out of the NOPOWER state Table 3 NOPOWER State Transitions Transitions into NOPOWER State From Condition Note Backup battery removed or discharges mE Over temperature alarm occurs A Shutdown command is received or the SD pin is asserted nEXTON goes from High to Low and stays Low for the time specified in the ExtOnTimeout EEPROM variable All voltage rails are disabled below VBU MIN Transitions from NOPOWER State To Condtio Note SDOWN gt LOPWR SHUTDOWN State The SHUTDOWN SD state is the Sleep state of the FS1610 In this state the Power Domain is active and the Power Domain is off While in the SD state the RTC is operational the and the serial interface do not operate and the VBAT output is active Table 4 summarizes the transition conditions into and out of the SD state READY State In this state The and Vpp Power Domains are active Shortly after the 51610 enters this state the device s internal registers are loaded with the power up settings specified in the configuration EEPROM The only active power supply output is VBAT The
59. tor 00196 divider the output SW 6 SDDIS 6 turns on prior to the output ramping up when SWI6 is enabled and turns off high impedance after the output goes below VIN when SWI6 is disabled Analog Backlight Brightness Control or General Purpose Input An EEPROM option enables the constant current output of SW 6 to be controlled via an analog con BLCTL A trol signal applied to this input The voltage current relationship is programmed in the EEPROM The voltage at this input can be read by a serial command Leave uncon nected if not used NN EN D lt PWM Backlight Brightness Control Input The constant current output of SW 6 can A12 BLCTL D be controlled via a digital PWM control signal applied to this input The PWM signal frequency must be between 100 Hz and 500 Hz Leave unconnected if not used PRELIMINARY FyreStorm Inc 13 Rev 6 2 Aug 06 ESTEE Q FyreStorm Pinno Mme _ DAS Internal Reference Voltage Bypass 1 Connect 2 resistor between this pin and AVSS 1 DAS 2 Internal Reference Voltage Bypass 2 Connect an 0 01 uF bypass capacitor be tween this pin and AVSS Bypass Capacitor for Internal Regulator for Digital Circuits Connect a 2 2 uF X5R A11 DVDD is bypass capacitor between this pin and DVSS P DVSS Digital Ground B3 RTOVDD Supp Y Connect an 0 1 uF X5R or better bypass capacitor between P
60. tore sec tion WHITE LED DRIVER SW 6 The White LED driver illustrated in Figure 12 uses step up boost architecture and is designed to drive from two to ten LEDs in series providing identical LED currents and eliminating the need for ballast re sistors The unit operates in programmable constant current mode The full scale constant current is programmable up to 30mA the serial interface This current can then be controlled by one of several methods digital PWM signal applied to the D input can control the duty cycle The average current can also be controlled by analog signal applied at the input For this mode of operation parameters stored in the EEPROM provide for eight levels of brightness cor responding to specified input voltage ranges Serial commands can specify of the eight pre configured brightness levels in the EEPROM or can specify the current in increments of one mA The White LED Driver has over voltage protection at a value read from the EEPROM at power up If the output voltage exceeds the over voltage threshold the channel will switch to constant voltage mode operation at the threshold voltage If the cause of the over voltage is removed the channel will automatically revert to con stant current operating mode See Power Rail Fault Monitoring for additional information The SDDIS 6 pin is used to reduce leakage current from the resistor divider
61. tused SALONE nLoPWR Pb Note 1 Select input pulldown option if not used EG Sd N ACTODIAOD 90 oar exen SALONE Ace OD ACT T notused 1 EC PWRENZJWDRSI Configure as an input and select inpol ec ExrENS ACT option if not used _ __ _ SALONE EXTPENS Aste acr Configure as an input and select input SALONE PWRENMJWDRSI Y Active H Note 1 pulidown option if not used EC 9B nNrR ACTODAOD SALONE sb Pb Note 1 Select input pulldown option used 05 x gt U gt 2 5 UJ VH 2 vo C SDA N ACT OD AOD 5 UART elect input pulldown option if used I S ALONE PWREND Y Active H Note 1 Select input pulldown option if not used Notes 1 Edge triggered input Note that on PWREN 5 2 the 51610 may miss an edge if it happens while the chip
62. upt system operation if the following guidelines are not followed B MOSFETs RDSon 50 milliOhm minimum to 200 milliOhm maximum at Ves 2 5 V Buck Channels Vps 8 V minimum to 20 V maximum Boost Channels 20 V or up to 5 White LEDs Buck Boost Channel 15 V O Vos 25 V Boost Channels 20 V to 25 V or 6 White LEDs Buck Boost Channel 15 V to 20 V VDS 30V For Boost channel gt 25 V or more than 6 White LEDs Buck Boost channel 20 V o Contact FyreStorm Applications Engineering Inductors most applications use inductors approxi mately 3 2 mm x 3 2 mm per side such as Pana sonic ELLSGM Series or equivalent Inductor selection can be further optimized for smallest size or highest efficiency by contacting Fyre Storm Applications Engineering B Capacitors PRELIMINARY Rev 6 2 Aug 06 FyreStorm Inc Q FyreStorm PRODUCT REVISION PACKAGE CODE EEPROM CODE IDENTIFIER Assigned by FyreStorm WAFER FAB ID AND LOT ID ASSEMBLY ID AND DATE CODE COUNTRY OF ASSEMBLY FF 104 ball fBGA lead free FG 104 ball fBGA RoHS Level 1 compliant Output and bypass capacitors should always be ceramic with a voltage rating at least 50 higher than maximum output voltage Electrolytic ca pacitors must not be used ESR is too high DVDD AVDD VBAT BATBU bypass capacitors should be 0603 case size or higher capacitance degrades with voltage in smaller case sizes Component
63. vision allows CPUS with serted out a resume power block running from VBAT SHUTDOWN After Cold Start Powe Meee es When the FS1610 goes into SHUTDOWN mode for o The device enters the READY state and starts the ten second READY timeout It remains in this state until a voltage rail is enabled via PWREN 0 or any one of the hardware power any reason after the cold start boot the transition from that state to READY is as previously described with the following differences enable inputs PWREN 5 1 An EEPROM programmable option can be en Note An EEPROM configurable option can be used to abled to route BATBU to VBAT while in SHUT cause the FS1610 to ignore PWREN 5 1 or PWREN 5 2 DOWN instead of only after the trigger event that until SW 2 is in regulation If configured to ignore initiates the SHUTDOWN to READY state transi PWREN 5 1 SW 2 must be configured to belong to tion Figure 19 PWREN 0 so that it automatically turns on at power up o If no power rail is enabled and the READY e A transition from SHUTDOWN to READY states timeout expires the device returns to the will be initiated if an RTC alarm occurs SHUTDOWN state except if ADPTR_IN indi e A transition SHUTDOWN to READY states cates that AC adapter power 15 present and will be initiated if the PWREN 1 input is asserted the wake up on ADPTR option is enabled in addition to the events described in 8 lf at least one power rail

FS1610

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