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FAMILY PRELIMINARY USER MANUAL (ST10 FAMILY)

1. 167 FAMILY PRELIMINARY USER MANUAL Besides devices with two chip select inputs which can be connected via the method described above there exist a number of external 16 bit devices which have only one chip select input but two separate write inputs a Write Low Byte WRL and a Write High Byte WRH input Connecting these devices can be done as illustrated in Figure 11b As it can be seen both methods require external glue logic and it is very desirable to save these gates and have integrated solutions instead To integrate separate chip selects for low or high byte instead of BHE and AO Figure 11a would require double the number of chip selects and pins which are not available in the C167 Integrating the second method however does not require additional pins since the write signals run parallel to all read write devices Thus this method was chosen for implementation The C167 will incorporate an option to automatically generate a WRL and WRH signal instead of WR and BHE This option can be selected via the control bit WRCFG Write Configuration SYSCON 7 When this bit is set the WR pin will be configured as a Write Low Byte strobe and the BHE pin as a Write High Byte WRH strobe The following table shows the resulting relationship WR BHE Operation WRL WRH Write to a word Low and High byte Write to the low byte Write to the high byte No write access either read or
2. 7 y Injected Channel Injection Conversion Request by CC31 Y Write ADDAT2 of Channel Y Z Y ADDAT2 Full zzz Int Request ADEINT Read ADDAT2 2 Y Temp Latch Full Conversion of Channel 2 Write ADDAT 1 X X 1 X 2 X 3 A Read ADDAT X 1 X x X 1 X 2 X 3 Temp Latch Full A Channel Injection Request by CC31 4 Wait until ADDAT2 is Write ADDAT2 read ADDAT2 Full Int Request AbENT Y Read ADDAT2 PEDE VR001913 124 180 S7 SGS THOMSON Af ie sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Figure 36 shows the operation of the channel injection mode In Figure 37 some special conditions are illustrated which have to be regarded when using the Channel Injection mode These items are described in the following a When starting a channel injection the following conditions can occur ADDAT ADDAT2 TEMP LATCH Converter Operation Empty Empty Empty Channel Injection was started while converter was idle gt start conversion of injected channel Previous conversion result was written to ADDAT gt Start conversion of injected channel ADDAT Wait for Read conflict gt Wait until ADDAT read Full Full Empty Previous conversion result was written to ADDAT Last Channel Injection result not read gt Start conversion of injecte
3. b7 to b0 P8 y Port 8 Data Register y 0to 7 DP8 FFD6h EBh Port 8 Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DP8 7 DP8 6 DP8 5 DP8 4 DP8 3 DP8 2 DP8 1 DP8 0 b7 to 60 DP8 y Port P8 Direction Control y 0 to 7 DP8 y 0 Port line P8 y is input high impedance DP8 y 1 Port line P8 y is output ODP8 F1D6h EBh Port 8 Open Drain Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 ODP8 7 ODP8 6 ODP8 5 ODP8 4 ODP8 3 ODP8 2 ODPS8 1 ODP8 0 b7 to 0 ODP7 y Port P7 Open Drain Control y 0 to 7 ODPT y 0 Port P7 y is output driver in push pull mode ODPT y 1 Port P7 y is output driver in open drain mode All lines of Port 8 can be used for the alternate compare output capture input functions of registers CC16 through CC23 of the 2 Unit Alternate Function SGS THOMSON 163 180 SYA MIERGELESTRORIES 167 FAMILY PRELIMINARY USER MANUAL CC16lO CC16 Capture Input Compare Output 1 CC17 Capture Input Compare Output CC18lO CC18 Capture Input Compare Output CC19lO CC19 Capture Input Compare Output 2 CC20 Capture Input Compare Output CC21IO CC21 Capture Input Compare Output CC22lO CC22 Capture Input Compare Output CC23lO CC23 Capture Input Compare Output The port input output buffer structure of the pins of Port 8 is the same as for the pins of Port 2 Figure 52 shows a block diagram of a Port 8 pin For a detailled description please refer to Cha
4. a a r r e e pj T7 T8 44 PORT P7 VR0A1904 84 180 S7 SGS THOMSON Af ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL b registers CC24 through CC27 only have external input pins as an alternate function at Port P1H This means that only external capture inputs can be used it is not possible to use these pins for compare output However these registers can still be used in the interrupt only compare modes to generate interrupt requests at predefined events S7 SGS THOMSON 85 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 86 180 ST SGS THOMSON Af DELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL 6 ASYNCHRONOUS SYNCHRONOUS SERIAL INTERFACE 6 1 Even Odd Parity Selection The serial interface ASCO of the C167 will have one enhancement compared to the respective interfaces in the ST10x166 For the parity now a selection for even or odd parity generation check will be available When an asynchronous mode with parity is enabled a new control bit SOODD SOCON 12 selects between even and odd parity generation check The default after reset SOODD 0 selects even parity as in the ST10x166 Hereafter is the ASCO control register SOCON SOODD 0 Even parity If the data contains an even number of 1s then the parity bit 0 If the data contains an odd number of 1s then the parity bit 1 SOODD 1 Odd pa
5. 7 44 Detailled Operation of the SSC Figure 27 shows a block diagram of a typical serial configuration with the SSC Three wires are connected between the different devices a clock line a transmit line and a receive line The clock line is connected parallel to all devices while the connection of the data line s depends on full or half duplex operation This configuration can be used for single or multi master operation Figure 27 Basic Serial Configuration with the SSC Device 1 Device 2 Transmit MASTER T 10r2 Lines Device 3 SLAVE Device n SLAVE VROG1628 SGS THOMSON 105 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 7 4 1 Single Master Full Duplex Operation Such a configuration is illustrated in Figure 28 The master device can either be a C167 or a member of the ST10 or 8051 families LSB first operation only or other master mode capable devices compatible to the SSC As slave devices C167 components or again devices compatible to the SSC and capable of slave mode operation can be used Due to being only capable to operate in the master mode the ST10x166 or members of the 8051 family cannot be used as slave devices To simplify the further description it is assumed that only C167 components are used for both master and slave devices if not stated otherwise Figure 28 Full Duplex Single Master Configuration Example Master Device 1 Device 2 Slave
6. Alternate Function Chip Select 0 Output BUSCONO Chip Select 1 Output BUSCON 1 Chip Select 2 Output BUSCON2 Chip Select Output BUSCON3 Chip Select 4 Output BUSCON4 External Hold Request Input Hold Acknowledge Output Bus Request Output The selection between the function and the alternate chip select function is done during reset see Chapter 3 5 Either zero two CSO and CS1 three 50 CS1 and CS2 or all five chip select outputs can be selected The remaining pins can be used for general purpose I O The table below shows these options Selected Number of Chip Select Signals 155 180 yy S65 S MIGAOELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL The chip select lines of Port 6 additionally have an internal weak pullup device This device is switched on under the following conditions always during reset if the Port 6 line is used as a chip select output and the C167 is in the Hold mode invoked through HOLD and the respective ODP6 x control bit is O This feature is implemented in order to have the chip select lines high during reset in order to avoid multiple chip selection and to allow another master to access the external memory via the same chip select lines Wired AND while the C167 is in the Hold mode With ODP6 x 1 open drain output selected the internal pullup device will not be active during the Hold mode external user defined pullup devices must be used in
7. FO9A 4D Eora OD reserved 167 FAMILY PRELIMINARY USER MANUAL RPOH DP1H DP1L reserved DPOH reserved DPOL reserved S7 SGS THOMSON 177 180 SYA ine RUE TROUPE 167 FAMILY PRELIMINARY USER MANUAL 14 INDEX FIGURES A D Converter Channel Injection Example 123 A D Converter Channel Injection Wait for Read Examples 124 A D Converter Wait for Read Mode Example 121 Address Chip Select Operation MUX Bus Example 45 Address Range Configuration Example 32 Basic Serial Configuration with the SSC 105 versus WRH WRL Operation DEMUX Bus Example 50 Block Diagram of a PORT6 Pin P6 7 P6 6 P6 4 P6 0 157 Block Diagram of a PORT7 Pin P7 3 P7 0 161 Block Diagram of a PORT7 Pin P7 7 P7 4 162 Block Diagram of a PORTS Pin 165 Block diagram of the major units of the C167 6 Block Diagram of the PORT6 Pin P6 5 HOLDE 158 BUSCON Configuration Examples 42 CAPCOM 1 CAPCOM Configuration Example 84 2 Unit Block Diagram 80 Connection Possibilities of an External Read Write Device 48 Dedicated Pins and Alternate Functions 168 Example Half Duplex Config Slave Transmit Open Drain Outputs 112 Example Half Duplex Config Slave Transmit Push pull Outputs 111 Full Duplex Multi Master Configuration Example 109 Full Duplex Single Master Configuration Example 106 Half Duplex Configuration Example Push Pull Outputs 110 Inte
8. 561 ecje Fraa os 9 reM s ajs Fras D4 reas sa reas ia Frag D3 reas ss Fee 33 FEM s2 aje 22 si re2 t FFAO DO ADCON FF20 90 T78CON FE20 0 BUSCON4 FETA 00 ADDRSEL2 174 80 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL FE16 0B STKUN FF12 SYSCON FE12 o9 sP 08 FFOC BUSCONO FEOC 06 Fros 84 FFoo so FEO0 00 DPPO S7 SGS THOMSON 175 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Table 2 4 2 Special Function Registers in Extended ESFR Space Bitaddressable ESFRs Non Bitaddressable ESFRs FIDE er EE ED EC rips ea Fino es rica es Fics ea rica e FBE DF 2 Fc DE FIBA bo rips oc Figs B F184 DA ripe bo Figo os Fae o7 Fac e Faa o Fas D4 Fas o3 o m oi 2 Fiao bo 176 180 T8 T7 PP3 PP2 PP1 PT3 PT2 PT1 PTO reserved FOSE OF reserved reserved Fooc 4E FO1C OE reserved reserved
9. 67 180 7 SGS THOMSON SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Burst Mode This mode allows the combination of two PWM signals onto one output pin This mode is only possible for channels 0 and 1 When Burst Mode is selected through bit 1 in register PWMCON1 then the output signals of channel 0 and 1 are ANDed together onto the pin associated with channel 0 The output of channel 1 can still be used at its associated output pin if the output is enabled Figure 16 illustrates this mode Note that each of the two channels can either operate in mode O or 1 it is recommended however to have both channels operating in the same mode when using the burst mode Note that it is guaranteed by design that no spurious spikes will occur at the output pin of channel 0 in this mode Instead the signal will be transferred to the output pin synchronously to internal clocks after the logical ANDing of channel 0 and channel 1 Note that the EXORing of the alternate output function and the port output latch value is done after the ANDing of channel 0 and 1 Figure 16 PWM Pulse Burst Mode Operation Example PPO Period Value PTO Count Value Channel 0 PP1 PP1 Count Value Channel 1 Resulting Output POUTO VR001902 68 180 Sz SGS THOMSON aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL Single Shot Operation This mode is available only for channels 2 and 3 of the
10. DP1H7 DP1H6 DP1H5 DP1H4 DP1H3 DP1H2 DP1H1 DP1HO b7 to 60 DP1H y Direction Control 0 7 DP1H y 0 Port line P1Hy is input high impedance DP1H y 1 Port line P1Hy is output The symbol PORT1 is used to refer to both parts of this port The upper four pins of P1H will have additional alternate functions besides the address output in the non multiplexed bus modes These alternate functions are capture inputs of the 2 Unit see Chapter 5 The relation between the pins and the alternate functions is as follows NIMM Alternate Function CC24lO CC24 Capture Input CC25lO CC25 Capture Input CC26lO CC26 Capture Input CC271O CC27 Capture Input SGS THOMSON 145 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL As all other capture inputs the capture input function of pins P1H 4 through P1H 7 can also be used as external interrupt inputs 400 ns sample rate 20 MHz CPU clock Note that when used as the address bus in the non multiplexed bus mode P1L and P1H are treated as one word wide port Either all 16 lines are used for the address bus or can be used for general purpose I O depending on the bus mode As a side effect the capture input capability of lines P1H 4 7 can also be used in the address bus mode With this one could detect changes of the upper address lines and trigger an interrupt request in order to perform some special service routines Figure 41 illustrates the
11. Error VR001911 7 5 1 Receive Error Master and Slave Mode SSCEINT SSCEIE Error Interrupt amp SSCEIR A receive error will be generated when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the indication flag SSCRE and the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost 7 5 2 Phase Error Master and Slave Mode The incoming data at pin MRST is sampled with the same frequency as the CPU Clock If the data changes between one sample before and one sample after the latching edge of the clock signal see Figure 25 the phase error indication flag SSCPE and the error interrupt request flag SSCEIR is set 114 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 7 5 3 Baud Rate Error Slave Mode Using this error detection capability requires that the slave s baud rate generator is programmed to the same baud rate as the master device The baud rate error indication flag will then be set if the incoming clock signal deviates from the programmed baud rate such that it either is more than double or less than half the expected baud rate This feature allows to detect false additional or missing pulses on the clock line within a certain frame The indication flag SSCBE and the err
12. For more information on Port 5 please refer to the ST10 User Manual S7 SGS THOMSON 117 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Note that in the C167 the upper six lines of Port 5 have a second alternate function for the GPT1 and GPT2 timer inputs Figure 34 SFRs and Port Pins Associated with the A D Converter Ports Data Control Interrupt Registers Registers Control ADDAT ADCON ADCIC AN15 ANO P5 15 P5 0 ADDAT2 ADEIC P5 Port 5 Register VROA1914 ADDAT A D Converter Result Register ADDAT2 A D Converter Channel Injection Result Register ADCON A D Converter Control Register ADCIC A D Converter End of Conversion Interrupt Control Register ADEIC A D Converter Overrun Error Channel Injection Interrupt Control Register Registers in Extended SFR Space 8 2 Wait for ADDAT Read Mode In the default mode of the ADC an overrun error interrupt request will be generated if a new conversion result is written into the result register ADDAT before the last result stored in this register was read by the CPU or PEC In this case the old result will be overwritten and is unretrievably lost Note that in the continuous and auto scan modes the ADC immediately starts a new conversion when the current conversion is completed In order to avoid the overrun error a relatively high interrupt priority level must be assigned to the conversion complete interrupt and short interrupt response times must be gu
13. P7 4 pe 28 1 4 28 SORTS 1 4 75 m 29 CC29IR 1 4 P76 m CC30 t CC30IR 4 12 P 6 4 Capt Comp Reg CC31 CC31IR Eee System Clock Input 6 Interrupt Request LL LL IL IL Interrupt Requests e LL I i ea Trigger A D Channel Injection Interrupt Request VR001904 167 FAMILY PRELIMINARY USER MANUAL The two new timers will be named T7 and T8 and the associated reload registers are T7REL T8REL respectively The control register for these timers is 78 sixteen additional compare registers will be CC16 through CC31 Four additional registers CCM4 through CCM7 control the operating modes of registers CC16 through CC31 The 2 unit will use the pins of Port 8 four pins of Port 1 and four pins of Port 7 for the alternate capture input compare output functions see also Chapter 11 Figure 20 gives an overview on all the Special Function Registers SFRs related to the 2 Unit while the following table lists their associated address Note that some of these registers which are mostly only used once during the initialization are moved to the new extended SFR space ESFR When accessing these registers with REG or BITADDR addressing modes an Extend Register EXTR EXTPR EXTSR instruction is required Normal SFR Space Extended ESFR Space bitaddressable non bitaddressab
14. Reset Value 0000h 15 14 13 12 11 10 9 8 RGSAD 11 4 7 6 5 4 3 2 1 0 RGSAD RGSZ b15 to b4 RGSAD BUSCON Address Range Start Address Selection b3 to b0 RGSZ BUSCON1 Address Range Selection Registers BUSCON2 4 and ADDRSEL2 4 organized in the same manner For more details on the BUSCON and ADDRSEL registers please refer to the ST10 User Manual The address locations of these registers in the SFR space are as follows Register Physical 8 Bit Address Address BUSCONO OFFOCh bitaddressable BUSCON1 OFF14h bitaddressable BUSCON2 OFF16h bitaddressable BUSCON3 OFF18h bitaddressable BUSCON4 OFF1Ah bitaddressable ADDRSEL1 OFE18h not bitaddressable ADDRSEL2 OFE1Ah not bitaddressable ADDRSEL3 OFE1Ch not bitaddressable ADDRSEL4 OFE1Eh not bitaddressable Note that due to the fact that the bus parameter bits are more often affected by software than the other system control bits the BUSCONO register in the C167 is placed on the same SFR address as the SYSCON register in the ST10x166 This requires the least amount of changes in existing software when transferred to the C167 The new SYSCON register in the C167 is located to a new SFR address FF12h 89h Note One must never program two or more ADDRSEL registers such that the selected address ranges overlap either entirely or partially otherwise unexpected results may occur An exception to this restriction of course is the address range for the BUSCONO regist
15. the Wait for Read mode and a new conversion result is present in the temporary latch the start of new conversions is disabled When register ADDAT is read by the CPU or a PEC transfer the internal flag is reset and the next conversion will start The ADC Busy Flag ADBSY and the Start Flag ADST remain set while the converter is waiting for a read of ADDAT In the default operating mode with overrun error generation continuous or auto scan conversions are started in a fixed timeframe the specified conversion time In the wait for read mode the time required for several conversions is dependent on the response time of the routine reading the result register ADDAT Thus the time for several conversions in the new mode can not under all circumstances be predetermined However as long as software is able to keep track with the A D converter there are no delays and the ADC runs with the fastest possible speed Figure 35 illustrates the differences between the default mode and the new Wait for Read mode of the ADC 120 180 S7 SGS THOMSON Af ie aDELERTRONISS 167 FAMILY PRELIMINARY USER MANUAL Figure 35 A D Converter Wait for Read Mode Example Example Auto Scan Continuous Mode Default Operation ADWR 0 Conversion Write ADDAT 3 2 1 0 3 ADDAT Full m Generate l Interrupt Request Y Y Y Y ADDAT Full Read of ADDAT ia Channel 0 Result of Channel x 3 2 4 Result Los
16. 3 and 4 of this register reflect the bit combination which was read during reset at the POH pins 3 and 4 see Table 3 5 These bits read only and can be used to check the selected configuration during run time 152 180 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL The input output structure of the new additional Port 4 pins is the same as for pins P4 0 and P4 1 described in the ST10 User Manual Chapter 10 1 4 The only difference to the ST10x166 s Port 4 operation is that the automatic switch of the alternate output function will only be performed for the pins selected for segment address function 11 5 5 Port 5 will be extended to 16 pins shown hereafter The Port 5 lines can either be used as analog input channels for the A D converter or as digital input only lines The upper six pins of Port 5 have additional alternate input functions for the GPT1 and GPT2 timers Figure 45 illustrates the input and alternate input functions of Port 5 For more details on the Port 5 pins please refer to the ST10 User Manual Chapter 10 2 Figure 45 PORT5 Input and Alternate Functions General Purpose Alternate Function 1 0 a b P5 15 AN15 T2EUD P5 14 AN14 T4EUD P5 13 AN13 5 12 12 T6IN P5 11 AN11 T5EUD P5 10 AN10 T6EUD P5 9 AN9 P5 8 AN8 PORT 5 5 7 7 5 6 AN6 P5 5 5 5 4 4 P5 3 AN3 P5 2 AN2 P5 1 AN1 P5 0 ANO VR001921 P5 FFA2h D1h
17. 7 D7 D7 AD7 AD7 POL 6 D6 D6 AD6 AD6 POL 5 D5 D5 AD5 AD5 POL 4 D4 D4 AD4 AD4 POL POL 3 D3 D3 AD3 AD3 POL 2 D2 D2 AD2 AD2 POL 1 D1 D1 AD1 AD1 POL O DO DO ADO ADO 8 Bit 16 Bit 8 Bit 16 Bit Non MUX Bus Non MUX Bus MUX Bus MUX Bus VR001916 PORTO is also used to select the system startup configuration During reset PORTO is configured to input and each line is held high through an internal pullup device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pulldown device A default configuration is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pullup devices are designed such that an external pulldown resistors of about 15 to 20 KOhm see Data Sheet specification can be used to apply a correct low level These external pulldown resistors can remain connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong SGS THOMSON 143 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL With the end of the reset the selected bus configuration will be written to the BUSCONO register The configuration of the high byte of PORTO wi
18. 8K n 1 3 results to an access in the respective address range 000000h 007FFFh 010000h 017FFFh in segment 1 respectively See also Chapter 2 5 Internal Address Space S7 SGS THOMSON 29 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 2 On chip ROM Address Range Mapping Option and Expandability Address Space 03 0000 02 0000 01 7FFF 01 0000 00 7FFF 00 0000 2 2 RAM The C167 incorporates a total of 2 KByte on chip RAM located in the address range from OOF600h through OOFDFFh shown in Figure 3 The stack size options are extended accordingly described in detail in section 3 3 The entire 2 KByte of internal ROM Expansion gt 32 KByte lt 32 KByte Segment 1 via ROM Mapping lt 32 KByte Segment 0 gt Segment 2 Segment 1 Segment 0 VR001890 RAM can be used for variables stack and general purpose register banks 24 180 yy 55 S MISROELECTRORICS 167 FAMILY PRELIMINARY USER MANUAL Figure 3 On Chip RAM Address Map 00 FDFFh 00 FDOOh 00 00 FBOOh 00 00 F900h 00 F800h 00 F700h 00 F600h L Bit Addressable Space PEC Pointers 26506 Sat a a a aS yy 55 S MISROELECTRORICS 2 KByte Dual Port RAM used for Data Registerbanks Stack Code Stack Size Options 2 5 10 66 Options E Additional VR0
19. Control Register x 2 4 6 8 ODPx Port x Open Drain Control Register x 2 4 6 8 P5 Port 5 Register Read Only Registers in Extended SFR Space VR001914 138 180 S7 SGS THOMSON Af ie sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL In the C167 a new feature is implemented in certain ports The Open Drain Control allows to switch the output driver of a port pin from a push pull configuration to an open drain configuration In the push pull configuration shown on the left in Figure 39 a port output driver has an upper and lower transistor thus it can actively drive the line either to a low or a high level In the open drain mode illustrated on the right in Figure 39 the upper transistor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower transistor is switched off and the output goes to a high impedance state The high level must then be performed through an external user defined pullup device With this feature it is possible to connect several port pins together through a Wired AND configuration saving external glue logic and or additional software overhead for enabling disabling output signals This new feature is implemented for ports P2 P3 P6 P7 and P8 see respective sections and is controlled through respective Open Drain Control Registers ODPx These registers allow the individ
20. For example only one pulldown resistor is required to select either a non multiplexed 16 bit bus or a multiplexed 8 bit bus The maximum number of pulldowns would be required for the very unlikely case of an initial 8 bit non multiplexed bus with three chip select lines and a 4 bit segment address The startup configuration is continuously sampled during reset however the last value sampled before the reset sequence is terminated is taken as valid This configuration is then latched internally in different ways and at different locations The state of the PORTO lines POH 0 7 is latched into a special register RPOH ESFR space address OF108h 84h RPOH F108h 84h System Startup Configuration Register Read Only Reset Value xxxxh 7 6 5 4 3 2 1 0 b7 to b5 R Reserved 04 b3 SALSEL Number of Segment Address Lines configured during reset read only b2 b1 CSSEL Number of Chip Select Lines configured during reset read only 00 R Reserved Bus Mode and Data Width Selection If external start of execution is selected EA 0 PORTO lines POL 6 7 are used to define the initial bus mode of the C167 The state of these two pins sampled at the end of the reset sequence is copied into the bus type field of the BUSCONO register POL 7 determines the data width of the bus while POL 6 controls whether multiplexed bus or a non multiplexed bus is used These values can be changed after reset at any time via a write
21. I O and alternate functions of PORT1 Figure 41 PORT1 I O and Alternate Functions General Purpose Alternate Function y o a b P1H 7 A15 CC2710 P1H 6 14 CC2610 P1H 5 A13 251 P1H 4 A12 241 11 2 10 P1H 1 A9 P1H 0 A8 FORT P1L 7 A7 P1L 6 A6 P1L 5 A5 P1L 4 A4 BAL P1L 3 A3 P1L 2 A2 P1L 1 P1L 0 A1 8 16 Bit Non MUX Bus VR001917 As mentioned in the introduction to the port description in the C167 Port 2 has an open drain output feature The respective control register ODP2 is shown below ODP2 F1C2h E1h Port 2 Open Drain Control Register Reset Value 0000h 146 180 S7 SGS THOMSON Af Ie aDELEETRONISE 15 14 13 12 11 10 9 8 ODP2 15 ODP2 14 ODP2 13 ODP2 12 ODP2 11 ODP2 10 ODP2 9 ODP2 8 7 6 5 4 3 2 1 0 ODP2 7 ODP2 6 ODP2 5 ODP2 4 ODP2 3 ODP2 2 ODP2 1 ODP2 0 C167 FAMILY PRELIMINARY USER MANUAL b15 ODP2 y Port 2 Open Drain Control bit 0 to 15 ODP2 y 0 Port 2 y output driver in push pull mode ODP2 y 1 Port 2 y output driver in open drain mode As described in Chapter 10 eight pins of Port 2 pins P2 8 through P2 15 will have additional alternate functions for the fast external interrupt inputs while P2 15 also serves as count input T7IN for timer T7 The following table shows the relationship between the Port 2 pins and their alternate functions a b and c Alternate Function a CC1IO CC2lIO CCS
22. OPERATION Before Transmission Transmission Reception Bit 0 1 2 3 4 5 6 7 Complete Register SSCTB Register SSCTB 0000 0000 0110 0101 0000 0000 0110 0101 00h 65h 00h 65h Transmit Line Register SSCRB Register SSCRB XXXX XXXX XXXX XXXX 0000 0000 1001 0011 XXh XXh Receive Line 00h 93h LSB b MSB FIRST OPERATION Before Transmission Transmission Reception Register SSCTB Register SSCTB 0000 0000 0110 0101 0000 0000 0110 0101 00h 65h 00h 65h Transmit Line Register SSCRB Register SSCRB XXXX XXXX XXXX XXXX 0000 0000 1001 0011 XXh XXh Receive Line 00h 93h MSB VR001887 98 180 ST SGS THOMSON Af tc tronics 167 FAMILY PRELIMINARY USER MANUAL Clock Control Two bits in register SSCCON are provided to control the polarity and the phase of the serial clock SCLK Bit SSCPO allows to select the idle level of the clock With SSCPO 0 the clock line is at a low level between transfers and with SSCPO 1 the clock idle state is a high level Bit SSCPH determines the operation to be performed at a certain clock edge For transmission one edge of the clock signal is always used for shifting while the other edge is used for latching the data Figure 25 shows the possible combinations for the clock and illustrates the shifting and latching edges with respect to the dat
23. Port 5 Data Register Read Only Reset Value xxxxh SGS THOMSON 153 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 15 14 13 12 11 10 9 8 P5 15 P5 14 P5 13 P5 12 P5 11 P5 10 7 6 5 4 3 2 1 0 bO to B15 P5 y Port 5 Data Register 0 to 15 11 6 PORT6 Port 6 is an 8 bit bidirectional general purpose l O port Each port line is bit addressable and can individually be programmed for input or output via the direction control register DP6 The open drain output option is available for Port 6 The registers of Port 6 are shown hereafter P6 FFCCh E6h Port 6 Data Register Reset Value 0000h 7 6 5 4 3 2 1 0 m Imm me b7 to b0 P6 y Port 6 Data Register 0 7 DP6 FFCEh E7h Port 6 Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DP6 7 DP6 6 DP6 5 DP6 4 DP6 3 DP6 2 DP6 1 DP6 0 b7 to 60 DP6 y Port P6 Direction Control y 0to7 DP6 y 0 Port line P6 y is input high impedance DP6 y 1 Port line P6 y is output 154 180 S7 SGS THOMSON 167 FAMILY PRELIMINARY USER MANUAL ODP6 F1CEh E7h Port 6 Open Drain Control Register Reset Value 0000h b7 to 0 ODP6 y Port P6 Open Drain Control y 0 to 7 ODP6 y 0 Port P6 y is output driver in push pull mode ODP6 y 1 Port P6 y is output driver in open drain mode All lines of Port 6 can also be used for alternate functions shown in the following
24. Register SSCTB Synchronous Serial Channel Transmit Buffer Register SSCRB Synchronous Serial Channel Receive Buffer Register SSCCON Synchronous Serial Channel Control Register SSCTIC Synchronous Serial Channel Transmit Interrupt Control Register SSCRIC Synchronous Serial Channel Receive Interrupt Control Register SSCEIC Synchronous Serial Channel Error Interrupt Control Register Registers in Extended SFR Space VR001908 7 3 1 SSC Control Register SSCCON Hereafter are shown the bits and functions of the SSC Control Register SSCCON From a programming point of view SSCCON is partly divided into two registers located to the same physical address The upper two bits SSCEN and SSCMS are always available An access to bits 13 0 addresses two different registers depending on the state of the SSC enable bit SSCEN When the SSC is disabled with SSCEN 0 the bits which control the basic operation of the SSC are available for initialisation After enabling the SSC with setting SSCEN to 1 an access to SSCCON 13 0 returns status information such as the busy and the error flags which are necessary during the operation of the SSC The partitioning of register SSCCON is illustrated by showing the register twice The first register represents the function and symbols of the bits while SSCEN 0 while the second register represents the function and symbols with SSCEN 1 94 180 S7 SGS THOMSON 06 AN crt tronics 167 FAMILY PRELIMIN
25. S1TRINT S1EINT Note also that due to the replacement of the three ST10x166 ASC1 interrupts the following table shows 27 interrupt sources Nevertheless the C167 has 24 interrupt sources more than the ST10x166 134 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Interrupt Source Control Interrupt Vector Trap Register Vector Location Number 5 Transmit SSCTIC SCTINT SCC Receive SSCRIC SCRINT SCC Error SSCEIC SCEINT 2 Register 16 CC16IC CC16INT 2 Register 17 CC171C CC17INT 2 Register 18 CC18IC CC18INT 2 Register 19 CC19IC CC19INT 2 Register 20 20 CC20INT 2 Register 21 CC21IC CC21INT 2 Register 22 CC221C CC22NT 2 Register 23 CC23IC CC23INT 2 Register 24 24 24 2 Register 25 CC25IC CC25INT 2 Register 26 CC261C CC26INT 2 Register 27 CC271C CC27INT 2 Register 28 CC28IC CC28INT 2 Register 29 29 29 2 Register 30 CC30IC CC30INT CAPCOM2 Register 31 CC311C CC31INT 2 Timer T7 T7IC T7INT 2 Timer T8 T8IC T8INT PWM Channels 0 3 PWMIC PWMINT Software Bit Set XPOIC XPOINT Software Bit Set 1 Software Bit Set XP2IC XP2INT Software Bit Set XP3IC 11Ch The operation and functions of these interrupts are the sam
26. USER MANUAL Sometimes it is necessary in an application to switch an output off to the high impedance mode in order to avoid external collisions and short circuits This switch is performed by setting the direction to input however to distinguish it from using the line as an input an symbol is used in this case This does not indicate special mode of the pin instead it indicates the idea behind this operation Figure 39 Push Pull and Open Drain Output Drivers Port Pin Symbols Push Pull and Open Drain Output Drivers External Pull up E E Push Pull Output Driver Open Drain Output Driver ol Port Pin Symbols Pin Symbol Pin Symbol Push Pull Output Input Pin Symbol Pin Symbol Open Drain Output Output Driver Switched OFF by Switching Pin to Input VR001915 140 180 S7 SGS THOMSON e DELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 11 0 PORTO Ports POL In the C167 the 16 bit Port 0 known from the ST10x166 will be split into two 8 bit ports named POL lower half of former upper half The corresponding direction registers are then DPOL and DPOH respectively These registers and the associated addresses are shown hereafter In the description and Figures however the symbol PORTO is used to refer to both parts POL and POH POL FFOOh 80h PORT 0 Low Byte Data Register Reset Value 0000h 7 6 5 4 3 2 1 0 POL7 P
27. Width Register PWx This 16 bit register holds the actual PWM value which corresponds to the duty cycle of the PWM signal This register is connected to a 16 bit shadow register The operation of these two registers is as follows The contents of the shadow register are constantly compared to the contents of the associated counter PTx When the comparison shows that the timer contents are greater than or equal to the contents of the shadow register the PWM signal is set otherwise it is reset This type of comparison allows a flexible control of the PWM signal see also the section on PTx The shadow register is loaded with the contents of the pulse width register PWx depending on the following conditions a When the counter PTx is not running PTRx 0 a write to register PWx writes to both the pulse width register PWx and the shadow register of that channel This is used to initially load both registers b When the counter is running then in mode 0 the shadow register is loaded from register PWx with the same signal that clears the counter PTx to 0000h marked with LSR in Figure 14 In mode 1 the shadow register is loaded when the count direction of the counter is switched from down to up marked with LSR in Figure 15 PWM Control Register PWMCONO This 16 bit control register controls the function of the timers of the four PWM channels and it holds the individual interrupt enable and request flags The bits and functio
28. and output pins however are all connected together onto one line Figure 30 Half Duplex Configuration Example Push Pull Outputs Master Device 1 Device 2 Slave Shift Register Shift Register Common Transmit Device 3 Slave Receive Line Shift Register VR0A1910 Other than for the full duplex configuration where a transmission from a slave to a slave is not possible transmissions receptions between any stations can be performed with the half duplex configuration Depending on the output driver mode of the port pins different methods can be used to avoid conflicts on the serial data line When using push pull output drivers only the transmitting device may enable its data output pin as shown in Figure 31 All other devices must disable their output drivers through switching the port line to input The clock signal for the transfer is provided by the master device All devices even the transmitting device can receive the data 110 180 S7 SGS THOMSON Ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Figure 31 Example Half Duplex Config Slave Transmit Push pull Outputs Master Device 1 Device 2 Slave Shift Register Shift Register Common Transmit Device 3 Slave Receive Line Shift Register VROB1910 With the open drain output configuration shown in Figure 32 no enabling or disabling of the port lines is necessary for the half
29. b4 SSCHB if SSCEN 0 SSC Heading control bit b3 to b0 SSCBM if SSCEN 0 SSC Data Width Selection bit field SSCBC if SSCEN 1 SSC bit Count Field S7 SGS THOMSON 95 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL Enable Disable Control Bit SSCEN globally enables or disables the synchronous serial interface Setting SSCEN to 0 stops the baud rate generator and all internal activities of the SSC Current transfers are aborted The alternate output functions at pins P3 8 MRST P3 9 MTSR and P3 13 SCLK return to their disable state which is a logic high These pins can now be used for general purpose Special care should be taken with pin P3 13 SCLK when operating with a clock polarity SSCPO 0 detailled in Chapter 7 4 1 When SSCEN 0 default after reset register SSCCON provides the bits used to control the operation of the SSC When SSCEN 1 any access to register SSCCON returns the status flags The selection which part of the SSCCON register is accessed is done according to the state of SSCEN valid before the current access That means when SSCEN 0 register SSCCON can be written to with one instruction initializing the control bits and setting bit SSCEN to 1 for example MOV SSCCON 0C057h The new state of SSCEN becomes valid after this instruction The same operation is true when SSCEN is 1 An instruction which resets SSCEN to 0 would write bits 0 13 into the flag portion
30. be found in Chapters 7 4 7 3 3 Baud Rate Register SSCBR This 16 bit register is used to program the serial transfer baud rate When the SSC is disabled register SSCBR can be loaded with the baud rate value Reading this register returns either 0000 default after reset or the programmed baud rate value The baud rate generator is a down counter and uses the value in SSCBR as a reload value The baud rate generator is started when the SSC is enabled through setting bit SSCEN When SSCEN is 717 SSCBR should never be written to Reading SSCBR while the SSC is enabled returns the current count of the baud rate generator It is recommended however to only access register SSCBR when the 100 180 S7 SGS THOMSON Af Ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 55 is disabled The baud rate generator is clocked with CPU Clock 2 such that maximum baud rate of up to 5 MBaud is available The formula for calculating the baudrate is SSC Baud Rate CPU Clock 2 SSCBR 1 with SSCBR gt 0 or for a desired baud rate the calculation of the reload value SSCBR is SSCBR CPU Clock 2 Baud Rate 1 55 must be gt 0 It must be noted that although the clock is only generated in the master mode operation if one wants to use the baud rate error detection capability the baud rate must also be correctly programmed to the serial system baud rate in the slave mode The following table gives an
31. duplex mode Instead a line conflict is avoided through setting the data in the non transmitting devices shift registers to all ones Since the data inputs and outputs are connected together a transmitting device will clock in it s own data at the input pin MRST for a master device MTSR for a slave In this way it is possible to detect any corruptions on the common data line if the received data is not equal to the transmitted data S7 SGS THOMSON 111 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 32 Example Half Duplex Config Slave Transmit Open Drain Outputs Master Device 1 Device 2 Slave Shift Register Shift Register Common Transmit Device 3 Slave Receive Line Shift Register VR0C1910 7 4 4 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty and ready to be written to with the next transmit data If by the time a previous transmission is finished register SSCTB is full it is immediately transferred into the shift register and the next transmission will start without any extra delay From an external point of view a transmission of two data frames in this case would look like a transmission of one data frame of double the data length Two byte transfers for example would produce the same characteristics as one word transfer This feature can be used to interface with devices which ca
32. example to clip on to a soldered C167 with the emulator pod The bondout chip in the emulator pod will not react on the state of pin POL 1 it will come up in normal mode after reset In this way it is possible to perform testing with the emulator although a C167 is soldered in the board The C167 will remain in this mode until a hardware reset is performed with pin POL 1 sampled at a high level at the end of the reset sequence Adapt Mode PORTO Internal Pullup Internal Pullup PORT1 High Impedance High Impedance Ports P2 P3 P4 High Impedance High Impedance P7 P8 Port P6 7 5 High Impedance High Impedance Internal Pulldown Internal Pullup 56 180 Sz SGS THOMSON Af ie sDELERTRONISS 167 FAMILY PRELIMINARY USER MANUAL Special care has to be taken regarding the oscillator pins XTAL1 and XTAL2 In the Adapt Mode the oscillator is switched off When an external oscillator circuit driving XTAL1 is used while XTAL2 is left unconnected this signal can also be used to drive another device such as the bondout chip clipped on to the C167 device If a crystal oscillator circuit is used however it is not possible to use this circuit for clocking other devices At least XTAL2 must not have a connection with the clipped on component Emulation Mode PORTO pin POL O is used to enter a special mode provided for emulation purposes of customer specific derivatives of the C167 This mode has no relevance for the standard C167 a
33. ie aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL 11 7 PORT7 Port 7 is 8 bit bidirectional general purpose port Each port line is bit addressable and can individually be programmed for input or output via the direction control register DP7 The open drain output option is available for Port 7 Herebelow are shown registers P7 DP7 and ODP7 P7 FFDOh E8h Port 7 Data Register Reset Value 0000h 7 6 5 4 3 2 1 0 b7 to b0 P7 y Port 7 Data Register y 0 to 7 DP7 FFD2h E9h Port 7 Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DP7 7 DP7 6 DP7 5 DP7 4 DP7 3 DP7 2 DP7 1 DP7 0 b7 to 60 DP7 y Port P7 Direction Control y 0 to 7 DP7 y 0 Port line P7 y is input high impedance DP7 y 1 Port line P7 y is output ODP7 F1D2h E9h Port 7 Open Drain Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 ODP7 7 ODP7 6 ODP7 5 ODP7 4 ODP7 3 ODP7 2 ODP7 1 ODP7 0 b7 to 60 ODP7 y Port P7 Open Drain Control y 0 to 7 ODPT y 0 Port P7 y is output driver in push pull mode ODPT y 1 Port P7 y is output driver in open drain mode SGS THOMSON 159 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL All lines of Port 7 can also be used for alternate functions of the PWM module and the Unit as follows Alternate Function POUTO PWM Channel 0 Output POUT1 PWM Channel 1 Output POUT2 PWM Channel 2 Output POUT3 PWM Channel 3 Output
34. in all slave s shift registers while the data of the selected slave can be found in the master s shift register In the master and all slaves the contents of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set Note The mechanism to start a transmission by writing into the transmit buffer register SSCTB is only active when the SSC is enabled SSCEN 1 If register SSCTB is written to prior to the enabling of the SSC no transmission will start Other than for a master device in a slave device the selected first bit MSB or LSB of the transfer data will immediately be put out at pin MRST when the contents of the transmit buffer is copied into the slave s shift register In a master device this will occur with the next signal from the baud rate generator The reason for this is that depending on the selected clock phase the first clock edge generated by the master may be already used to clock in the first data bit Thus the slave s first data bit must already be valid at this time This behaviour can also be seen in Figure 25 One can see that other than for the asynchronous serial interface ASCO always a transmission and reception takes place regardless whether valid data has been transmitted or received 108 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 7 4 2 Multi Master Full Duplex Operation Figure 29 basically shows the s
35. no access Figure 12 shows the timing of these signals compared to the default mode WR and BHE Note that after reset the default mode is the WR BHE operation If the BYTDIS bit BHE Pin Disable bit SYSCON 9 is set also the WRH operation if selected is disabled The can then be used for general purpose SGS THOMSON 49 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 12 BHEZ AO versus WRH WRL Operation DEMUX Bus Example BUS LU S Uf BHE AO OPERATION NN WRH WRL OPERATION WRL WRH gt WRITE ACCESS WRITE ACCESS TOA WRITE ACCESS TOA WORD LOW BYTE HIGH BYTE VR001897 If the WRHZ WRL option is selected and an access via 8 bit data bus is performed the WRL signal is activated for every write access while the WRH signal is activated only for high byte accesses 0 1 Note When the WRH WRL option is selected the two signals are also affected by the read write delay control RWDCx in a BUSCONx register Note This distinction between the low byte or high byte is only necessary for write accesses to external memory or peripherals For read accessses always the entire word can be read the C167 itself determines whether to read the lower or upper byte from the 16 bit data bus There might be rare cases however where the reading of a byte might affect status information in a peripheral for example re
36. overview of some possible baud rates at a CPU Clock of 20 MHz together with the resulting bit times SSCBR Baud Rate reserved 5 MBaud 3 3 MBaud 2 5 MBaud 2 0 MBaud 1 0 MBaud 100 KBaud 10 KBaud 1 0 KBaud 152 6 Baud 7 3 4 Interrupt Control Registers Three interrupt control registers are associated with the SSC one for a transmit interrupt SSCTIC one for a receive interrupt SSCRIC and one for an error interrupt SSCEIC These registers and their functions shown hereafter are identical to all other interrupt control registers in the C167 and in the entire ST10x166 family and are not explained here please refer to the ST10 User Manual for details The conditions for generating the individual interrupt requests are explained in Chapters 7 4 and 7 5 S7 SGS THOMSON 101 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 55 FF72h B9h Synchronous Serial Channel Transmission Interrupt Control Reset Value 0000h b7 SSCTIR SSC Transmission Interrupt Request b6 SSCTIE SSC Transmission Interrupt Enable b5 to b2 ILVL Interrupt Priority Level b1 b0 GLVL Group Priority SSCRIC FF74h BAh Synchronous Serial Channel Reception Interrupt Control Reset Value 0000h b7 SSCRIR SSC Reception Interrupt Request 06 SSCRIE SSC Reception Interrupt Enable b5 to b2 ILVL Interrupt Priority Level b1 50 GLVL Group Priority SSCEIC FF76h BBh Synchronous Serial Channel E
37. selected Due to the ANDing of the port latch value and the alternate data output the pin will switch from a 1 to a 0 To avoid this first the SSC of the master should be enabled then the port latch should be programmed to a 1 In the case of a clock polarity of 1 the port latch should be first programmed to 1 When the serial interfaces are enabled the master device can initiate the first data transfer This is performed by writing the transmit data into register SSCTB This value is copied into the shift register which is assumed to be empty at this time and with the next signal of the baud rate generator the busy flag and the transmit interrupt request flag will be set The selected first bit of the transmit data will be placed onto the MTSR line Depending on the selected clock phase also a clock pulse will be generated on the SCLK line see Figure 25 The master then continues to shift out the contents of it s shift register with each clock pulse while at the same time latching and shifting in the data detected at it s input line MRST Since the clock line is connected in parallel to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection have been generated the data transmitted by the master is contained
38. the open drain output feature For this an external pullup device is connected to the serial receive line and all slaves program their MRST line to open drain output This forms a Wired AND connection To avoid the corruption of the data on the receive line if two or more slaves try to place different logic levels onto this line all slaves which are not selected for transmission to the master just have to transmit the value FFFFh depending on selected data width Since in this case the high level is not actively driven onto the line but only held through the pullup device the selected slave can pull this line actively to a low level without the danger of a short circuit After performing all necessary initializations of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start for further transfers the alternate data line will always remain at the logic level of the last transmitted data bit S7 SGS THOMSON 107 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL Note The state of the internal alternate output lines is 1 as long as the SSC is disabled If the SCLK pin of the master is already completely initialized at the time the SSC is enabled an unwanted clock edge could be produced when the SSC is enabled in the case a clock polarity of 0 is
39. this case anyway The number of chip select lines selected during reset can be read in register RPOH Bits 1 and 2 of this register reflect the bit combination which was read during reset at the POH pins 1 and 2 see Chapter 3 5 and Table 3 5 These bits are read only and can be used to check the selected configuration during run time Figure 46 shows a block diagram of a Port 6 pin used for the chip selects P6 4 P6 0 Since the chip select signals are required directly after reset the pins selected during reset for this function are switched automatically to the alternate output function It has to be taken into account however that the open drain output option can only be selected through software earliest during the initialization routine at least signal CSO will be in the push pull output driver mode directly after reset 156 180 S7 SGS THOMSON Af e aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Figure 46 Block Diagram of a PORT6 Pin P6 7 P6 6 P6 4 P6 0 Write ODP6 y Open Drain Latch ODP6 y Symbols P6 y lt Input P6 y Push Pull Output Read ODP6 y Write DP6 P6 t tpi EE Open Drain Output Direction Latch DP6 y Read DP6 y Alternate Function Enable Alternate Data Write P6 y Output Port Output Latch P6 y Output Buffer 6 0 50 P6 1 CS1 Read P6 y 6 2 52 P6 3 CS3 P6 4 CS4
40. two different options exist selectable through bits 15 CSWENx and 14 CSRENx of the respective BUSCON1 4 registers This is illustrated in the following table see also Figures 8 and 9 These options are described in detail in the next sections Note that for the BUSCONO chip select line 50 these options are not available The reason is that if CSO is enabled during reset see Chapter 3 5 it must go active directly after reset to enable fetching of the first instructions There is no way to additionally select whether CSO should operate as address or read write chip select directly after reset Furthermore since BUSCONO and 50 are nearly in all cases used to access code memory such a chip select option is not useful CSWENx CSRENXx Chip Select Operation Chip Selects CS1 CS4 Address Chip Select Read Chip Select Write Chip Select Read Write Chip Select Note that the chip selects whether Address or Read Write Chip Selects will not be generated for internal accesses even if the access is to an address within the range specified through an ADDRSEL register SGS THOMSON 43 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL In order to avoid undefined levels of pins used as chip select lines internal pullup devices of about 50 KOhm are implemented at these pins This pullups are switched on during reset either hardware software or watchdog timer reset such that these lines are held at a high l
41. writing the same or a higher value 2 PPx as contained in the shadow latch into the timer before the PWM pulse has started results to an immediate setting of the PWM signal Setting the timer to a value lower than the one in the shadow latch will set the output to low To disable further PWM pulses one can first stop the timer by clearing the run bit PTRx To abort a pulse in the single shot mode one can set the timer to the same value as in PPx With the next clock pulse the timer will be reset to 0 and stopped through clearing bit PTRx by hardware It is also important to note in this context that a write to PWx will immediately be copied into the shadow latch if bit PTRx is 0 Note that is also possible to affect the PWM output signal through enabling disabling the output with the control bits PENx or through changing the respective port latch value S7 SGS THOMSON 73 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL Period Register PPx The 16 bit period register PPx of a PWM channel is used to determine the period and thus the frequency of the PWM signal For this purpose the contents of the associated counter PTx is constantly compared to the contents of the period register PPx When a match is found between the two values the counter is either reset to 0000h or the count direction is switched from counting up to counting down depending on the selected operating mode of that PWM channel Pulse
42. 000h F600h Reserved 4000h F200h Extended SURE pace 000 2000h oe Internal Address Space 0000h u External Addresses Generated VR001893 SGS THOMSON SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 3 BUS CONTROL UNIT 3 1 Extended Address Space The C167 provides the full addressing capability of the ST10 family The total address space is extended to the maximum range of 16 MByte This requires 24 bit addressing address lines A23 A0 The lower 16 bits of the address are provided via Port 0 in multiplexed bus mode or via Port 1 in non multiplexed bus mode The upper 8 bits of the address are optionally provided via Port 4 which in the C167 is extended to 8 bits see Chapter 11 The C167 has the capability of addressing up to 16 MByte however there are several options for the user to configure the part for the number of physical external address lines actually required in the system First one can switch between segmented or non segmented mode In the non segmented mode the total address range is 64 KByte segment 0 Second in the segmented mode the user can specify the number of segment address lines required in the system Either 0 2 4 or all 8 segment address lines can be configured By this the user can select the external address space addressable through physical external address lines to be either 64 KByte 256 KByte 1 MByte or the full 16 MByte range And third up to five chip selec
43. 01891 25 180 167 FAMILY PRELIMINARY USER MANUAL 2 3 PEC Pointer Address Space The source and destination pointers for the PEC channels which in the ST10x166 occupy the bitaddressable address range OFDEOh through OFDFFh remapped in the C167 to the address range OFCEOh through FCFFh as illustrated in Figure 3 This change enables the user to utilize all 2048 bits in the RAM without having to sacrifice this valuable space when using the PEC channels Note This change is an incompatibility with the ST10x166 2 4 Extended Special Function Register Space ESFR In the C167 due to the amount of registers required to control the additional on chip peripherals the address range for the special function registers SFRs is extended This new Extended SFR range ESFR is located in the address range 00 000 through 00F1FFh It has the same size as the normal SFR range and it is also split into a bitaddressable and a non bitaddressable section Due to the special addressing modes available for SFRs some exceptions have to be taken into account when accessing registers in the ESFR space SFRs can be addressed via a 16 bit direct MEM or indirect address Rw via a bit address BITOFF or via a short 8 bit address REG Accessing SFRs via a 16 bit address MEM or Rw is no problem since they are easily distinguished by that address The short addressing modes REG or BITOFF however implicitly use the fixed base address o
44. 0h 15 14 13 12 11 10 EXI7ES EXI6ES 5 EXI4ES 5 4 3 2 EXI3ES 2 5 EXHES EXIOES b15 b14 EXI7ES External Interrupt 7 Edge Selection bit field b13 b12 EXIGES External Interrupt 6 Edge Selection bit field b11 b10 EXIBES External Interrupt 5 Edge Selection bit field 09 b8 EXI4ES External Interrupt 4 Edge Selection bit field b7 b6 EXI3ES External Interrupt 3 Edge Selection bit field b5 b4 EXI2ES External Interrupt 2 Edge Selection bit field b3 b2 EXI1ES External Interrupt 1 Edge Selection bit field b1 60 EXIOES External Interrupt 0 Edge Selection bit field N A 0 5 0 0 Fast interrupt disabled EXIOES 0 1 Interrupt on the positive edge EXIOES 1 0 Interrupt on the negative edge EXIOES 1 1 Interrupt on the positive and the negative edge 10 2 Additional Peripheral Interrupts In the following the additional peripheral interrupt sources of the C167 compared to the ST10x166 are listed Four interrupt nodes will be implemented which have no associated peripheral source These interrupts can be activated through software by setting the respective interrupt request flag XPxIR in register XPxIC This can be used to have software traps with programmable priority levels Note that the SCC interrupts will use interrupt vector locations B4h B8h and BCh In the ST10x166 these interrupt vectors were used by the serial interface ASC1 interrupts S1TINT
45. 3IO CCA4IO CC5IO CC6lO CC7IO CC8lO CC9IO CC101O CC1110 1210 14 CC1510 Alternate Function b Alternate Function c Fast External Interrupt 0 Input Fast External Interrupt 1 Input Fast External Interrupt 2 Input Fast External Interrupt 3 Input Fast External Interrupt 4 Input Fast External Interrupt 5 Input Fast External Interrupt 6 Input Fast External Interrupt 7 Input T7IN Timer T7 External Count Input SGS THOMSON 147 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 42 illustrates the I O and alternate functions of Port 2 Note that the second alternate functions of Port 2 pins P2 13 through P2 15 in the ST10x166 the bus arbitration signals HOLD HLDA and BREQ are now in the C167 alternate functions of the Port 6 pins P6 5 through P6 7 Figure 42 PORT2 I O and Alternate Functions General Purpose Alternate Function yo a b 2 15 T7IN 2 14 14 EX6IN P2 13 2 12 1210 EX4IN P2 11 CC1110 2 10 10 2 2 9 CC9IO EX1IN PORTS P2 8 CC8lO EXOIN P2 7 CC7lO P2 6 CC6IO P2 5 CC5IO P2 4 CCA4IO P2 3 CC3IO P2 2 CC2lO P2 1 CC1IO P2 0 VR001918 11 3 PORT3 In the C167 the two alternate functions WR and READY of pins P3 13 and P3 14 in the ST10x166 are performed through dedicated pins Due to pin limitations in the target MQFP 144 package P3 14 will not
46. 6 7 4 2 Multi Master Full Duplex 109 7 4 8 Half Duplex 110 7 4 4 Continuous Iratis Leld eite biete berba rene 112 725 Error Det t Na M D EE 113 7 5 1 Receive Error Master and Slave 114 7 5 2 Phase Error Master and Slave 114 7 5 8 Rate Error Slave 115 7 5 4 Transmit Error Slave 0 0000 115 8 A D Converter ADC i iiid di eet EE edo aicut ce dere 117 8 1 Additional A D Input Channels sss ne 117 8 2 Wait for ADDAT Read Mode sess 118 8 3 Channel Injection Mode n 22 9 GPT1 and GPT2 Enhancements eene 27 10 Interr pt System 133 External Intert plsauuiucu pO Go Pee Lo eed 133 10 2 Additional Peripheral eese 134 TI POS tec eee uot in tto 11 0 PORTO Ports POL ard POP oie E 141 111 PORTI Ports PTE rede tort neret 144 11 2 PORTE ette don te tea ete 146 11 9 PORTS 2t tie det a AN A IPM E 14
47. 66 this bit does not automatically configure port P4 to output the segment address lines this is performed through the system startup configuration described in section 3 5 The SGTDIS bit in the C167 is only used to enable segment addresses to port P4 and to determine the correct stack operations for traps and interrupts optionally push pop the Code Segment Pointer CSP S7 SGS THOMSON 35 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL ROM Enabling and Mapping The ROM Enable bit ROMEN determines whether the on chip ROM is enabled or not This bit is set automatically during reset according to the state of the External Access input pin EA If this pin is high during reset ROMEN will be set to 71 and the C167 will start execution out of the internal ROM A low level at this pin during reset will force the C167 to start execution out of external memory with external bus parameters determined through the System Startup Configuration Selection see section 3 5 Bit ROMEN will be cleared in this case For the mapping of the internal ROM to either segment 0 or segment 1 other than in the ST10x166 an individual bit ROMS1 is implemented The default after reset is ROMS 0 mapping the ROM to segment 0 If the ROM is enabled one has to take care of that no external addresses will be generated in the lower 32 KByte address space of either segment 0 ROMS1 0 or segment 1 ROMS 1 Note that until the execu
48. 8 ITA PO PRA 151 153 PEE 154 TIG PORTZ po db tg kk tia ule Ut 159 11 8 PORTO coder rode cede id 163 12 Dedicated PINS chase 13 c 169 RE Mae rmm ccn 4 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL ST10167 This Preliminary User Manual describes the enhancements bring to the new ST10 Family the C167 Family and specially the ST10167 which is the first derivative component of the C167 Family Compared to the ST10x166 besides adding functionality in the peripheral and bus controller section some enhancements and changes are made in the CPU core of the C167 The following list gives a short overview on the additional features and functions of the ST10167 8 KByte On Chip Mask Programmable ROM 2 KByte On Chip RAM Extended System Stack Variable and Register Bank Space PEC Pointers Mapped to Non Bitaddressable Space Additional Instructions to Support HLL and Operating Systems Extended Address Range up to 16 MByte Five Bus Configuration Registers Five Selectable Chip Select Signals Extended SFR Space Enhanced A D Converter Operation 16 Analog Input Channels Wait for Read Mode Start New Conversion after ADDAT Read Channel Injection Convert Specific Channel during Auto Scan or Con
49. ANUAL Table 2 4 1 Special Function Registers in Normal SFR Space Bitaddressable SFRs Non Bitaddressable SFRs __ rere 7F 2 Ris rrA BD mo Re rere ze e FEF6 78 FA Ro Fera fro Re Fr72 sscro rea 9 tre R8 Fero e 7 FEEE z 0 me sonc rec 7e R5 FEEA 75 _ 4 Fees a 83 Fees 74 R Fees z2 2 pen ep reee 71 Fo Rmo 0 rac reco o Froe ___ rese ar rre Jer re zr reoc ee P ire ee FFDA eo resa fao rena eo Frog ec reo ec ress zc Feo eB FFD4 EA Pe FEDA ea FED2 eo FEDO e e7 pre Frac FE4E 27 ee Pe reoc ee Pecce tram Aso Feco 60 Pecco Free o res Jor or rex tr o P rec o reg se oo res op 50 FEsA t0 erse oe rea ec ews 50 res to Free o 98 ss Esa FFB2 D9 SSCCON FF32 99 PWMCON D8 SOCON FF30 98 PWMCONO FEzE i7 Frac 061 reac
50. ARY USER MANUAL Care should be taken when accessing the SSCCON register and the partitioning of this register should always be kept in mind When SSCEN 0 bits 7 12 and 13 of register SSCCON are not defined and should be set to 0 With SSCEN 1 bits 4 through 7 and bit 13 of SSCCON are reserved and should be set to 0 This has to be taken into account when accessing register SSCCON via Read Modify Write instructions such as BSET BCLR AND OR XOR BFLDL H etc In the following the individual bits and bit fields of the SSCCON are discussed SSCCON FFB2 D9 Synchronous Serial Channel Control Register Reset Value 0000h SSCBEN SSCPEN SSCREN SSCTEN SSCBM b15 SSCEN Synchronous Serial Channel Enable control bit b14 SSCMS SSC Master Select bit b13 Reserved b12 SSCBSY SSC Busy Flag If SSCEN 1 b11 SSCBEN if SSCEN 0 SSC Baudrate Error Enable control bit SSCBE if SSCEN 1 SSC Baudrate Error Indication Flag b10 SSCPEN if SSCEN 0 SSC Phase Error Enable control bit SSCPE if SSCEN 1 SSC Phase Error Indication Flag b9 SSCREN if SSCEN 0 SSC Receive Error Enable control bit SSCRE if SSCEN 1 SSC Receive Error Indication Flag b8 SSCTEN if SSCEN 0 SSC Transmit Error Enable control bit SSCTE if SSCEN 1 SSC Receive Error Indication Flag b7 Reserved b6 SSCPO if SSCEN 0 SSC Clock Parity control bit b5 SSCPH if SSCEN 0 SSC Clock Phase control bit
51. C167 FAMILY PRELIMINARY USER MANUAL MSON 77 3 C167 FAMILY PRELIMINARY USER MANUAL USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED SGS THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS THOMSON Microelectronics As used herein 1 Life support devices or systems are those which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided with the product can be reasonably expected to result in significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system or to affect its safety or effectiveness 2 180 S7 SGS THOMSON AXI e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL TABLE OF CONTENTS TABLE OF CONTENTS EEG 3 67 a aaa meres Oren cere enter er ren 5 AMI se Lm T 1 1 Atomic Instruction exe e EE 7 1 2 Extend Segment Extend Page 2 4 022 4 222 8 1 3 Extend Register 2 44441044 00 8 A mee 23 n M
52. CC28lO CC28 Capture Input Compare Output CC29lO CC29 Capture Input Compare Output CC30lO CC30 Capture Input Compare Output CC311O CC31 Capture Input Compare Output The port structure of pins P7 0 through P7 3 is similar to the structure of Port 3 pins with an alternate output function e g T3OUT T6OUT etc as it is described in the ST10 User Manual Chapter 10 1 3 2 The exception is however that the port output latch value and the alternate data output are not ANDed but EXORed This feature allows to invert the alternate output by writing a 1 into the respective output latch With a 0 in the port latch the alternate output is not inverted With this option however separate alternate output enable control bits must be provided i e PENx in register PWMCON1 Figure 49 shows a block diagram of a P7 pin P7 0 through 7 160 180 S7 SGS THOMSON DELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL Figure 49 Block Diagram of a PORT Pin P7 3 P7 0 Write ODP7 y Open Drain Symbols Latch ODP7 BLY I Read ODP7 y y 11 Input P7 y n Push Pull Output t Write DP7 y P7 y Output e r Direction Latch Read DP7 y DP7 y a Alternate Write 7 Data Output Port Output Output B Latch P7 y P7 y POUTy q EXOR Buffer Read P7 y 5 24 1 Input Latch 0 3 VROP1643 Th
53. Condition TRUE next instruction count lt count 1 END WHILE count 0 Data Page Enable Interrupts and Traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTP instruction becomes immediately active such that no additional NOPs are required For any long or indirect address in the EXTP 2 sequence the 10 bit page number address bits A is not determined by the contents of a DPP register bar by re value of itself The 14 bit page offset address bits is derived from the long or indirect address as usual Depending on the value of op2 the period of validity of the EXTP instruction extends over the sequence of the next 1 to 4 instructions being executed after the EXTP instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the EXTP instruction 14 180 S7 SGS THOMSON Af ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL EXTP begin EXTended Page sequence NOTE A lot of care must be taken over the use of the EXTP instruction with other system control or branch instructions One must also be very careful when a class B trap condition becomes present before t
54. EO C0 23 2 2 On Ghlp RAM eo Wom ua 24 2 3 PEC Pointer Address 26 2 4 Extended Special Function Register Space 26 2 5 internal Address tete o eere tee eo teen de 29 2 Bus Conirol iio tertio dee iai SURE er 31 3 1 Extended Address uoce ep e ri vay breeds 31 3 2 System and Bus Configuration 2 33 3 2 1 SYSCON Register scr et Li E e 33 3 2 2 BUSGCONO RGGIBIOL pde deter aos ee blo de pet reu d ebd 36 3 2 8 BUSCON 1 4 and ADDRSEL1 4 38 suce AMANO Selects wx cog tts Gace 43 3 3 1 Address Chip S8leots 44 3 3 2 Read Write Chip 45 3 4 Byte High Enable or Write High Write Low 47 3 5 System Startup ConfiguratiOl 52 ben 51 3 6 On Chip ter eoe ee ente ier eee due s 58 es cete crt eicere e natur 861 AA PAN ME CAG Li scott toti b ate toit o a a tte 62 4 1 1 Operating ei Mete pe eto 63 4 1 2 PWM Module Heglslers tetto rt inet ie eei eo
55. L Since each data page has an address range of 16 KByte there exist 1024 data pages To select the data pages four Data Page Pointers DPPO through DPP3 available giving access to four data pages at one time The data page pointers are selected through the two most significant bits of any 16 bit data address Each of the four data page pointers in the C167 is extended to 10 bits which represent address bits A23 A14 See also Chapter 1 for a scheme to bypass the segments and pages For more information on the data page pointers please refer to the ST10 User Manual 3 2 System and Bus Configuration Control In the ST10x166 the SYSCON register is used to control the overall system configuration and the external bus In addition the BUSCON register and the associated ADDRSEL1 register allow the user to partition the address space for external devices with different bus access parameters such as bus width wait states etc Now in the C167 five bus configuration registers BUSCONO through BUSCON4 and four address range select registers ADDRSEL1 through ADDRSELA are implemented offering the option to have at least five address ranges with different bus parameters adapted to the needs of the memories or peripherals located to these address ranges The SYSCON register known from the ST10x166 is separated into two registers in the C167 Into one new BUSCONO register which is used for programming the bus related parameters as with the
56. N 149 180 MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 43 and Alternate Functions General Purpose Alternate Function Vo a b P3 15 CLKOUT No Pin P3 13 SCLK P3 12 BHE WRH P3 11 RxDO P3 10 TxDO P3 9 MTSR BOTH P3 8 MRST P3 7 T2IN P3 6 P3 5 T4IN P3 4 T3EUD P3 3 T3OUT P3 2 CAPIN P3 1 T6OUT P3 0 TOIN VR001919 ODP3 F1C6h E3h Port 3 Open Drain Control Register Reset Value 0000h 15 14 13 12 11 10 9 8 ODP3 13 EM ODP3 11 ODP3 10 ODP3 9 ODP3 8 7 6 5 4 3 2 1 0 ODP3 7 ODP3 6 ODP3 5 ODP3 4 ODP3 3 ODP3 2 ODP3 1 ODP3 0 b15 b14 Reserved b12 R Reserved b13 b11 to bO ODP3 y Port Open Drain Control bit y 11 13 ODP3 y 0 Port 3 y output driver in push pull mode ODP3 y 1 Port 3 y output driver in open drain mode 150 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 11 4 PORT4 As already mentioned above Port 4 in the C167 is extended to 8 bits Registers P4 and DP4 are shown hereafter FFC8h E4h Port 4 Data Register Reset Value 0000h b7 to b0 P4 y Port 4 Data Register y 0to 7 FFCAh E5h Port 4 Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DP4 7 DP4 6 DP4 5 DP4 4 DP4 3 DP4 2 DP4 1 DP4 0 b7 to 60 DP4 y Port P4 Direction Control y 0to7 DP4 y 0 Port line P4 y is input high impedance DP4 y 1 Port line P4 y is output T
57. OL6 POL5 POL4 POL3 POL2 POL1 POLO b7 to b0 POL y Port Data Register y Oto 7 FF02h 81h PORT 0 High Byte Data Register Reset Value 0000h 7 6 5 4 3 2 1 0 6 5 4 POH2 POH1 POHO b7 to b0 POH y Port Data Register 0 to 7 DPOL F100h 80h PORT 0 Low Byte Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DPOL7 DPOL6 DPOL5 DPOL4 DPOL3 DPOL2 DPOL1 DPOLO b7 to 60 DPOL y Direction Control y 0to 7 DPOL y 0 Port line POLy is input high impedance DPOL y 1 Port line POLy is output S7 SGS THOMSON 141 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL DPOH F102h 81h PORT 0 High Byte Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DPOH7 DPOH6 DPOHS DPOH4 DPOHS DPOH2 DPOH1 DPOHO b7 to 60 DPOH y Direction Control y 0 to 7 DPOH y 0 Port line POHy is input high impedance 1 Port line POHy is output This splitting of Port 0 has two advantages for the user First when using an 8 bit demultiplexed bus only POL is used for the data bus and POH can now be used for general purpose I O This gives the user an extra 8 I O lines which are not available in the ST10x166 Of course this option is only possible when using the 8 bit demultiplexed bus exclusively The second advantage is with byte writes to a port Byte moves to an SFR and a port is an SFR cause the not addressed byte to be cleared Thus
58. OMSON 129 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL b7 TSUD Timer 5 Up Down Control bit 06 Timer 5 Run bit 0 Timer Counter 5 stops TER 1 Timer Counter 5 runs b5 R Reserved b4 b3 T5M Timer 5 Mode Control b2 to bO T5I Timer 5 Input Selection T6CON FF48h A4h Auxiliary Timer T6 Control Register Reset Value 0000h b15 TeSR Timer 6 Reload Mode Enable bit T6SR 0 Reload from register CAPREL disabled T6SR 1 Reload from register CAPREL enabled b14 tob11 R Reserved b10 T60TL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software b9 60 Timer 6 Alternate Output Function Enable T60E 0 Alternate output function disabled T60E 1 Alternate output function enabled 08 T6UDE Timer 6 External Up Down Control Enable bit b7 T6UD Timer 6 Up Down Control bit 06 Timer 6 Run bit T6R 0 Timer Counter 6 stops T6R 1 Timer Counter 6 runs b5 Reserved 04 b3 Timer 6 Mode Control b2 to bO T6l Timer 6 Input Selection 130 180 S7 SGS THOMSON Af e DELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL External Connection of Alternate Inputs The additional external input lines described above are connected to the upper six pins of Port 5 in the C167 Since P5 is an input only port no special programming is necessary in order to select the al
59. P6 6 HLDA P6 7 BREQ Nia 0 4 6 7 VROM1643 The bus arbitration signals HOLD HLDA and BREQ are selected with bit HLDEN in register PSW Please refer to the ST10 User Manual for details on these pin functions Figure 46 also represents the block diagram of the Port 6 pins used for Hold Acknowledge HLDA and Bus Request BREQ P6 7 P6 6 When the bus arbitration signals are enabled via HLDEN also these pins are switched automatically to the appropriate direction Figure 48 shows the port structure of the P6 5 HOLD pin Figure 47 illustrates the I O and alternate functions of Port 6 Again a shaded bar indicates that these functions can only be selected in groups S7 SGS THOMSON 157 180 9 Af MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL Figure 47 PORT6 I O Alternate Functions General Purpose Alternate Function vO P6 7 6 6 HLDA P6 5 HOLD PORT 6 094 P6 3 CS3 P6 2 CS2 P6 1 CS1 P6 0 cso VR001922 Figure 48 Block Diagram of the PORT6 Pin P6 5 HOLD OX Write ODP6 5 Open Drain Symbols Latch P6 5 Read ODP6 5 ODP6 5 _ Input 6 5 rH Push Pul n Output t Write ODP6 5 P6 5 ET Open Drain Output r Direction Latch Read DP6 5 DP6 5 a Alternate Function Enable Write P6 5 Port Output Latch P6 5 Read P6 5 Alternate Data Input VRON1643 158 180 S7 SGS THOMSON Af
60. PWM module In this mode after the timer is started the PWM channel will produce one single pulse provided the PWM value is between 0000h and the period value and then the timer is stopped by hardware e g the run bit PTRx is reset to 0 In order to generate further pulse the timer has to be started again through software by setting bit PTRx Figure 17 shows the single shot operation of one PWM channel Note that a retriggering of the output pulse is possible by software When the pulse has started i e the output pin is set then a write of the pulse width value into timer PTx causes the output pulse to be extended by the specified pulse width This retriggering also multiple retriggering is always possible after the pulse has started and before the timer has expired S7 SGS THOMSON 69 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 17 PWM Single Shot Mode Operation amp Output Waveforms Examples PPx Period 7 PTx Count Value PWx Pulse Width 4 Set PTRx by LSR Set PTRx by LSR Software PTRX Reset by Software for Hardware Next Pulse PTx stopped PPx Period 7 PTx Count Value PWx Pulse Width 4 Retrigger after Pulse Trigger before Pulse has has started Write started Write PWx value PWx value to PTx to PTx Shortens Delay Time t VR001903 70 180 S7 SGS THOMSON Af mexotecinomcs 167 FAMILY PRELIMINARY
61. Registers Control Registers Interrupt Control Alternate Functions an PWMCONO PWMIC I NER M POUTS POUTO 7 7 0 1 PWMCON1 PW1 PT2 PP2 2 PW3 ODP7 Port 7 Open Drain Control Register DP7 Port 7 Direction Control Register P7 Port 7 Data Register PTO OT3 PWM Channel 0 3 Timer Register PPO PP3 PWM Channel 0 3 Period Register PWO PW3 PWM Channel 0 3 Pulse Width Register PWMCONO PWM Control Register 0 PWMCON 1 PWM Control Register 1 PWMIC PWM Interrupt Control Register Registers in Extended SFR Space VR001906 Up Down Counter PTx The counter PTx of a PWM channel is clocked by either the CPU clock or the CPU clock divided by 64 selected through a respective control bit PTIx in the control register PWMCONO Thus with a maximum CPU clock of 20 MHz the resolutions and frequencies listed in Table 4 1 2 can be achieved The counter can be started or stopped through the respective run control bit PTRx In the Single Shot Mode the counter run bit PTRx of channels 2 and 3 is cleared by hardware when the timers reach the value in the respective period register PPx The counter can count up or down however the count direction is controlled by hardware depending on the selected operating mode it can not be altered by software 72 80 S7 SGS THOMSON Af ie sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Table 4 1 2a PWM Unit Frequencies and Resolutio
62. SCON2 eee Si Start 4K CS1 1M 4KCS2 __ B N FE B N DERE Range 4K Start OK CSO USCONO CS0 VR001898 42 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 3 3 Chip Selects In order to save external glue logic mostly required for the generation of separate chip select signals for external devices such as memories or peripherals on chip automatic chip select signal generation is implemented in the C167 For this purpose each BUSCON register also the new BUSCONO register is designated a port line see Chapter 11 which provides a chip select signal as an alternate function When a chip select output is enabled for BUSCONx register see Chapter 3 5 for enabling disabling chip selects the associated output pin will go to a low level each time an external access to an address in the specified range for this BUSCONx register is performed The pin returns to a high level for any access outside of the specified range and for internal accesses Each BUSCONXx register is assigned a chip select line CSx Chip selects CS1 CS4 will go active if enabled when an external access within the address range specified through the associated ADDRSELx register is performed Chip select line CSO which is associated to the BUSCONO register will go active if enabled for any external access outside the ranges specified through registers ADDRSEL1 4 For chip selects CS1 CS4
63. Select Signals 50 and CS1 Three Chip Select Signals 50 51 and 52 During reset the port P6 lines with an alternate chip select function are pulled high through an internal pullup device If external access is selected EA 0 and at least two chip selects are configured the signal CSO will immediately go to a low level when the reset sequence has been finished while all other lines configured for chip select operation will drive a high level If Internal access is selected 1 signal 50 and all other lines configured for chip select operation will drive a high level The port P6 lines which are not selected for chip select operation can be used for general purpose Segment Address Lines Selection PORTO lines POH 3 4 are used to select the number of segment address lines on port P4 Either all eight four two or no segment address lines can be selected The state of pins POH 3 4 sampled at the end of a reset sequence is latched into bits RPOH S 4 The number of segment address lines can not be changed once the reset sequence has been finished Software can only read the bits RPOH 3 4 to check the configuration Only during a reset hardware software or watchdog timer reset the configuration can be changed The default configuration when the state of these pins sampled at the end of reset is 11 2 bit segment address is selected giving an address range addressable through physical addres
64. Shift Register Shift Register MTSR Transmit MTSR n MRST NEN L LI LI Device 2 Slave Shift Register VR001909 As mentioned before the different devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to it s data input line MRST and the clock line is the line connected to pin SCLK Only the device selected for master operation can generate and output the serial clock at pin SCLK All slaves must receive this clock pin SCLK is an input In the block diagram only the actual shift register of a device s synchronous serial interface is represented with an indication of the shift direction this is regardless whether the MSB or LSB is shifted first The external transmit line is connected to the input of a 106 180 S7 SGS THOMSON Af e aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL slave s shift register The output of the slave s shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave Since the external lines are hard wired also the pins connected to these lines are fixed Therefore it is obvious that the function and direction of these pins is determined by the master or slave operation of the individual device That is the reason why the pins M
65. TIN Reset Input RSTOUT Reset Output XTAL1 2 Oscillator Input Output VAREF VAGND Analog Power Supply VPP Reserved VCC VSS Digital Power Supply 20 Pins total There is a total of 33 dedicated pins Figure 54 gives an overview on these pins Other than in the ST10x166 the WR WRL pin is no more an alternate function thus there is no external pullup device necessary in order to apply a high level to this line during the initialization procedure This is now a push pull output during normal operation and is held high through an internal pullup device during reset S7 SGS THOMSON 167 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL Figure 54 Dedicated Pins and Alternate Functions General Purpose Alternate Function y o ALE RD WR READY EA NMI RSTIN RSTOUT XTAL1 XTAL2 VAREF VAGND V PP reserved 10 10 Dedicated Pins V 55 VR001924 168 180 S7 SGS THOMSON Af e aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL 13 The following table gives a pin description of the 56710167 Input to the oscillator amplifier and input to the external clock generator Output of the oscillator amplifier circuit To drive the device from an external source XTAL1 should be driven while XTAL2 is left unconnected Minimum and maximum high low and rise fall times specified in the AC characteristics must be observed RSTIN Reset inpu
66. TSR and MRST have to reverse their meaning and direction on a slave device To operate with this configuration first all devices must be initialized according to the desired operation One of the devices must be selected for master operation SSCMS 1 all others must be programmed to slave operation SSCMS 0 Besides the modes of operation of the device s SSC the respective port lines have to be initialized according to the table shown for master and slave mode clock line exceptions see note below However when studying the block diagram one can see that the slave s data output pins MRST are connected together onto on line Without provisions this would result in a short circuit when the slaves try to drive different logic levels onto this line Of course only one slave is allowed to output it s transmit data onto this line however the other slaves would drive their idle state onto this line There are two ways to avoid this collision One is that all or all except one of the slaves program there MRST pins to input That means that no or only one slave can put it s data onto the master s receive line Only receiving of data from the master is possible The master has to select the slave device from which it expects data either by separate select lines or by sending a special command to the slave The selected slave then would program it s MRST line for output until it gets a deselection signal or command The other way is by using
67. The module interrupt request flag PWMIR is cleared by hardware when the service routine is vectored to regardless whether the interrupt was caused by one or several channels However it will be set again if during execution of the service routine a new channel interrupt request is generated S7 SGS THOMSON 77 180 SYA MISROELECTROMICS 167 FAMILY PRELIMINARY USER MANUAL 4 1 4 PWM Output Signals In the C167 the output signals of the four PWM channels are connected as alternate output functions to four pins of Port 7 For each of the four channels an individual output enable control bit PENx is available in control register PWMCON1 The following table shows the reference between the PWM output signals and the associated port pins PortPin PWM Alternate Function POUTOPWM Channel 0 Output POUT1PWM Channel 1 Output POUT2PWM Channel 2 Output POUT3PWM Channel 3 Output Different to other alternate output functions the PWM signals are EXORed with the respective port latch outputs see Chapter 11 7 In this way it is possible to select whether the PWM signal is inverted at the output or not If the port latch is 0 default after reset the associated PWM signal is not inverted the output signal is as shown in Figures 14 to 17 If the port latch is 1 the PWM signal is inverted It is interesting to note that in the C167 Port 7 has additional open drain control This feature can be used to combine two or more PWM outputs throu
68. USER MANUAL If a write of the pulse width value to the timer PTx occurs before the pulse has started the pulse will be started at that time point since the PTx and PWx contents match By setting the period PPx the timer start value PTx and the pulse width value PWx appropriately the user has a wide variety of options to set the pulse width tw and an optional pulse delay td Figure 17 illustrates some of these options Note It is recommended to use the Single Shot Mode only together with Mode 0 standard PWM generation 4 1 2 PWM Module Registers Figure 18 gives an overview of all Special Function Registers SFRs of the PWM Module while the following table lists their associated address Note that some of these registers which are mostly only used once during the initialization are moved to the new extended SFR space ESFR When accessing these registers with REG or BITADDR addressing modes an Extend Register EXTR EXTPR EXTSR instruction is required Normal SFR Space Extended ESFR Space bitaddressable non bitaddressable bitaddressable non bitaddressable PWMCONO FF30h 98h FESOh 18h F17Eh BFh F030h 18h PWMCON1 FF32h 99h FE32h 19h F032h 19h FE34h 1Ah F034h 1Ah FE36h 1Bh FO36h 1Bh F038h 1Ch FOSAh 1Dh FO3Ch 1Eh FOSEh 1Fh S7 SGS THOMSON 71 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 18 SFRs and Port Pins Associated with the PWM Unit Ports amp Port Control Reg Data
69. Wrapping F600h FDFFh Entire internal RAM see Note As one can see from this table the internal system stack may be mapped to the single port RAM area Stack size options 0 4 mean that the stack will always reside in the specified address range there is a wrap around mechanism implemented for the stack although the contents of the stack pointer itself will not perform this wrapping see ST10 User Manual When the No Wrapping option is selected the stack may occupy the entire internal RAM space from 00F600h to OOFDFFh In this case the Stack Underflow and Overflow SFRs should be used to ensure that unintentional accesses do not occur In all cases the internal system stack can never be mapped to external memory Note Special care must be taken when the no wrapping option is selected In this case the Stack Pointer SP can be loaded with any word address between FOOOh and FFFEh No hardware protection exists against address values which are occupied by either the reserved address space or the standard or extended SFR ranges thus the SP must never be loaded with addresses in the range through F1FEh ESFR space F200h through F5FFh reserved space and FEOOh through FFFEh SFR space otherwise unexpected results will occur Segmentation Control As in the ST10x166 the bit SGTDIS controls whether segmentation is enabled or not After reset this bit is 0 thus segmentation is enabled However different to the ST10x1
70. a With SSCPH 1 the first edge of the clock is used for latching the data and with the second edge a shift by one bit is performed With SSCPH 0 the selection is performed vice versa With this flexible control an adaption to a variety of different operating modes of other synchronous serial interfaces is possible Figure 25 Serial Clock Phase and Polarity Options Serial Clock MTSR MRST Transmit Latch Data Data Shift Data VR001888 Error Detection Four different types of error conditions can be detected by the SSC If an error occurs an error interrupt request can be generated in order to allow appropriate reactions in such a case For each of these types of error a separate error detection enable bit and error indication flag is provided in register SSCCON A detailled discussion of the types of error detection can be found in Chapter 7 5 S7 SGS THOMSON 99 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Busy Flag The busy flag SSCBSY accessible only when the SSC is enabled SSCEN 1 indicates whether a transfer is currently in progress or not The busy flag is set and reset by hardware and software should only read this bit to check the status of the SSC SSCBSY is set in master mode when the contents of SSCTB is copied to the shift register and transmission begins It remains set until the last transfer has been finished That means as long as the transmit buffer SSCTB is not empty trans
71. a read access to this range and that it has the same timing characteristics as the write signal Figure 9 shows the timing for these read write chip select signals There are three selectable options The chip select can be generated either only for read accesses CSRENx 1 Read Chip Select or only for write accesses CSWENx 1 Write Chip Select or for both read and write accesses CSRENx amp CSWENx 1 Read Write Chip Select This feature saves external glue logic when accessing devices with only one enable input Figure 10 shows two examples for this SGS THOMSON 45 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 9 Read Write Chip Select Operation MUX Bus Example ALE v ADDRESS BUS READ CSx 1 N WRITE CSx N READ WRITE N N 5 VROA1894 Figure 10 Read Write Chip Select Examples Read Chip Select Example b Write Chip Select Example gt gt Ll Data Data Data Input ii Data Input 4 Output 8 Bit le eg 8 Bit Output Latch 2 e g Latch 07 00 aa 07 00 eg 07 00 9 Switches S 573 aa i HC574 L Read CS Write CS ead CS OC c rite CS C OC 45V VR001895 Note When the WRH WRL option see next chapter is selected the Write or Read Write Chip Select will go active if any of t
72. ading an interrupt pending register clears the request flags automatically In this case it might be necessary to use AO and BHE also for read accesses such that only the addressed byte is read The WRH WRL option cannot be used then 50 180 Sz SGS THOMSON Af ie sDELEETRONISS C167 FAMILY PRELIMINARY USER MANUAL 3 5 System Startup Configuration In the ST10x166 three dedicated pins EBCO EBC1 and BUSACT are used during reset to configure the bus operation of the chip The further configuration such as segmentation is done such that a default configuration is automatically assumed For example the default configuration is segmentation enabled causing the two pins of Port 4 to output address bits A16 and A17 which at 0 after reset Users not requiring segmentation have to take care of this effect when using Port 4 for general purpose This is a minor disadvantage for these users In the C167 when keeping with this scheme all 8 pins of Port 4 will output Os the full address of segment 0 directly after reset The problem for users requiring no segmentation would increase In addition in the C167 some more startup initializations such as chip selects enabled disabled have to be performed These considerations resulted to the following new scheme for setting up the system configuration during after reset Instead of three pins only one dedicated pin External Access will be used to determine wheth
73. al Channel SSC Block Diagram Slave Clock Clock Generator Control Master Clock Receive Int Request Transmit Int Request SSC Control Block Error Int Request Status Control y 16 Bit Shift Register Transmit Buffer Register SSCTB Internal Bus As the 55 is synchronous serial interface for each transfer separate clock signal must be provided The SSC has implemented a full featured clock control circuit which can generate the clock via a 16 bit baud rate generator in the master mode or receive the transfer clock in the slave mode The clock signal is fully programmable for clock polarity and phase The pin used for the clock signal is P3 13 SCLK 1 _ Control HL P3 9 MRST HL P3 8 Receive Buffer SSCRB VR001886 The SSC control block is responsible for controlling the different modes and operation of the SSC checking the status and generating the respective interrupt signals one for transmit one for receive and one for possible error conditions 92 180 S7 SGS THOMSON l AN e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 7 2 General Operation of the SSC After initialisation of the SSC the data to be transmitted is written into the transmit buffer register SSCTB If no transfer is currently in progress the contents of SSCTB is immediately copied into the shift register In master mode this will initiate th
74. ame configuration as Figure 28 however now the role of the master has been passed to the next device either through a type of token passing scheme or through special hand shaking lines The previous master is now switched to the slave mode by setting bit SSCMS to 40 and the previous slave is now the master SSCMS 1 Since the external connections can not be changed one can see that the new master and the previous master both have switched their connection of the shift register input and output to the respective port lines This switch is automatically performed when switching from master to slave mode and vice versa The port direction control however must be changed by the user as already explained above The basic operation now is the same as described for a single master system also in a multi master system at one time only one single master can exist Figure 29 Full Duplex Multi Master Configuration Example Slave Device 1 Device 2 Master Shift Register Shift Register Transmit LI L E L Device 3 Slave Shift Register VR001910 SGS THOMSON 109 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 7 4 3 Half Duplex Operation It is also possible to use only one data line for receive and transmit between the devices Figure 30 shows such a configuration As for the full duplex mode the clock line is again connected in parallel to all devices The data input
75. aranteed due to the fast conversion time of the ADC In many applications especially when operating with external program memory requiring a number of wait states it may be hard to fulfill this requirement In the C167 a new operational mode is implemented which helps to overcome such problems In this mode selected by bit ADWR Wait for Read Control Bit ADCON 9 see hereafter a double buffering of the ADDAT result register is performed At the completion of a conversion the ADC writes the result into register ADDAT and starts the next conversion When this conversion is complete the ADC checks whether the previous result was read out of register ADDAT If this is true the new result is written to ADDAT and the next conversion is started However if the previous result was not read in the meantime the ADC stores the new result in a temporary latch and waits in an idle loop It will not start the next conversion When finally register 118 180 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL ADDAT is read either by the CPU or the PEC the new result is transferred from the temporary latch to ADDAT an interrupt request is generated and the converter starts the next conversion This procedure is also true if the previous conversion was a single channel conversion or the last conversion of a series of conversions e g continuous or auto scan and the converter is started again by software No ov
76. are always accessible in both ranges gt EXTR scope not required for this instruction Example 3 Access to both SFR spaces No EXTR instruction required MOV SOTBUF SSCRB reg mem SOTBUF via reg SSCRB via mem MOV SSCTB SORBUF mem reg SSCTB via mem SORBUF via reg In order to optimize accesses to the ESFR space the distribution of the special function registers between the two SFR ranges was chosen such that the ESFR space holds registers which are rarely used during normal program execution These registers are mainly only written to during the initialization of the peripherals and are in most cases accessed via direct MEM addressing However except for the direction control registers of PORTO and PORT1 only registers new in the C167 are moved to the extended SFR space This is done to provide compatibility with existing designs With one new module however a retranslation or even rewriting of pieces of code is necessary The 2 Unit is on hand new in the C167 on the other hand it is somehow an old peripheral since it is equal to the CAPCOM Unit known from the ST10x166 Due to the amount of registers required for this unit it is not possible to place all registers into the normal SFR space in order to use code written for the CAPCOM Unit to be used for the CAPCOM Unit without any changes except for address modifications To minimize the modification effort mostly used 2 registers su
77. ations have shown that the output drivers are strong enough to hold the specified output voltage also at higher currents To avoid a violation of Data Sheet parameters it is planned to increase the specification of IOH in the Data Sheet to an appropriate value S7 SGS THOMSON 51 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL The following Table 3 5 illustrates the relationship between PORTO pin and the associated system configuration Table 3 5 PORTO Pin Assignment for System Startup Configuration POL O Emulation Mode Hardware Reset POL 1 Adapt Mode Hardware Reset POL 2 reserved POL 3 POL 4 Bootstrap Loader Mode Hardware Reset POL 6 Hardware Software and Watchdog Timer Reset POL 7 Bus Data Width Hardware Software and Watchdog Timer Reset POH 1 Number of Chip Selects Hardware Software and Watchdog Timer Reset POH 2 POH 3 Number of Segment Hardware Software and Watchdog Timer Reset POH 4 Address Lines POH 5 reserved POH 6 POH 7 The default configuration for the bus operation is as follows Multiplexed Bus 16 Bit Data Bus 2 Bit Segment Address at Port 4 18 Bit total Address Five Chip Select Outputs CSO CS1 CS2 CS3 CS4 52 180 SGS THOMSON sDELEETRONISE C167 FAMILY PRELIMINARY USER MANUAL One can see that the configuration selection is chosen such that in most cases a minimum number of external pulldown devices is required
78. ave s transmit buffer prior to any transfer S7 SGS THOMSON 115 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 116 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 8 A D CONVERTER ADC The ADC Module is based on the module implemented in the ST10x166 enhanced by additional analog input channels two new operating modes a second result register ADDAT2 and a programmablity for the sample and conversion times In the following the new additional functions and features are described 81 Additional A D Input Channels The C167 has 16 analog input channels to the on chip A D Converter For this purpose the input only Port 5 is extended to 16 bits The channel selection field ADCH in the A D Converter Control register ADCON now allows the specification of all sixteen channels The following table lists all Port 5 pins and their alternate functions together with the selection via ADCH Alternate Function Channel Selection ADCH Analog Input 0 Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 Analog Input 8 Analog Input 9 Analog Input 10 Analog Input 11 Analog Input 12 Analog Input 13 Analog Input 14 Analog Input 15 The lines of Port 5 can also be used as digital inputs No special distinction has to be made between Port 5 lines being used as analog inputs and Port 5 lines being used as digital inputs
79. b3 to b0 MCTC Memory CYcle Time Control If during reset the EA pin is at a high level the BUSCONO register is cleared to 0000 and execution begins out of the on chip ROM An external bus can then be selected via programming the BUSCONO BUSCON1 4 and ADDRSEL1 4 registers appropriately If the pin is low forcing execution to start with external memory register BUSCONO is set according to the selected bus type with default values for the bus parameters MCTC 0000 15 Memory Cycle Time Waitstates RWDCO 0 Read Write Delay Enabled MTTCO 0 One Memory Tri State Waitstate BTYP XX set according to the level at pins and during reset ALECTLO 1 ALE Lengthening Enabled BUSACTO 1 External Bus Enabled RDYENO 0 READY Input Disabled The coding of the BTYP bits in the BUSCONO and also in registers BUSCON1 4 is changed compared to the ST10x166 The new BTYP coding is shown in the following Selected Bus Operation 8 Bit Non Multiplexed Bus 8 Bit Multiplexed Bus 16 Bit Non Multiplexed Bus 16 Bit Multiplexed Bus S7 SGS THOMSON 37 180 SYA iie LEE TROUPE 167 FAMILY PRELIMINARY USER MANUAL With this coding a clear reference of a BTYP bit to the selected operation is given BTYP 1 controls the width of the bus 8 bit or 16 bit while BTYP 0 controls whether the bus is multiplexed or non multiplexed In addition this coding directly reflects the default bus configuration selection during r
80. be connected to a pin P3 13 received a new alternate function which is the clock input output line SCLK of the Synchronous Serial Channel SSC Pins P3 8 and P3 9 which served for the second synchronous asynchronous serial interface ASC1 in the ST10x166 now have the alternate data in data out functions of the SSC The following table shows Port 3 and the available pins for I O or alternate functions 148 180 SGS THOMSON Af e aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL ee Alternate Function TOIN T6OUT CAPIN T3EUD T4IN 2 MTSR MRST TxDO RxDO BHE WRH CLKOUT Timer 0 Count Input Timer 6 Toggle Output GPT2 Capture Input Timer 3 Toggle Output Timer 3 External Up Down Input Timer 4 Count Input Timer 3 Count Input Timer 2 Count Input SSC Master Transmit Slave Receive SSC Master Receive Slave Transmit ASCO Transmit Data Output ASCO Receive Data Input Byte High Enable Write High Output SSC Shift Clock Input Output No Pin assigned in the C167 System Clock Output With the exception of pins P3 15 P3 14 and P3 12 each line of Port 3 has an open drain output option The respective control register hereafter The I O and alternate functions of Port 3 are illustrated in Figure 43 The port structures of pins P3 8 MRST P3 9 MTSR and P3 13 SCLK are the same as for P3 11 RxDO Alternate Input and Alternate Output Function see Figure 26 SGS THOMSO
81. ble the user to write uninterruptable instruction sequences in a very effective way A further instruction is used to support the Extended SFR space in the C167 see Chapter 2 4 The new instructions are described below the syntax and formats of these instructions are detailled on the next pages 1 1 Atomic Instruction This instruction is intended to allow the user to write an uninterruptable sequence of code The execution of this instruction causes the interrupt system standard interrupts and PEC requests and Class A Traps to be disabled for a specific number of instructions between 1 to 4 instructions All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense e g MUL is one instruction The atomic instruction is immediately active such that no NOPs are required Any instruction type can be used with this instruction Note that while Class A Traps NMI Stack Overflow Underflow are disabled during the scope of the atomic instruction the occurence of a Class B Trap Illegal Opcode Illegal Bus Access etc will interrupt the atomic sequence since it indicates severe hardware problem The operation of the atomic instruction is the basis also for the Extend instructions Example ATOMIC 3 Scope is 3 instructions the following 3 instructions are uninterruptable MOV R0 1234h instr 1 MOV R1 5678h instr 2 MUL RO R1 instr 3 MUL regarded as one instruction MOV R2 MDL t
82. ch as the capture compare or the mode control registers are located in the normal SFR space and rarely used registers are placed into the ESFR space Figure 4 Standard and Extended SFR Spaces S7 SGS THOMSON 27 180 SYA MISROELECTROMICS 167 FAMILY PRELIMINARY USER MANUAL Standard SFR space Extended ESFR Space 8 Bit 16 Bit 8 Bit 16 Bit Address Address Address Address FEh FEh 4 FFDFh 7 F1DFh Bit J Bit Addressable Addressable A ASSN N Yj 90h FF20h 90h F120h CPU Reg Reserved 80h FFOOh 80h iy Lts t A 100h Non Bit Non Bit Addressable Addressable 10h FE20h 10h F020h 00h OPU Rg FEOOh 00h Reserved Except for Port 0 1 Direction Registers VR001892 Figure 4 shows an overview of both the normal SFR space and the ESFR space One can see that the two spaces are very similar The General Purpose Register area in the upper portion of the normal SFR space is also reflected in the ESFR range Thus the 5 are also available within an EXTR instruction sequence Note that the GPR area in both SFR spaces the upper 16 word locations must not be accessed via 16 bit address Except for the PORTO and PORT1 direction control registers the address range occupied by the CPU registers 00 FE1E and FF00 FF1E are reserved in the ESFR space Tables 2 4 1 and 2 4 2 at the end of the Manual list all the Special Function Registers in the C167 Note With respect to some S
83. contents With the following count pulse the timer will increment to 0001h and the procedure described continues The PWM value stored in the shadow register is constantly compared to the timer contents When a match is found while the timer is counting up the output signal is switched to a high level It remains on this high level until the timer decrements again to a value lower than that of the shadow register In this way both edges the positive and the negative edge of the signal are controlled by the PWM value Figure 15 illustrates the operation of a PWM channel in this mode and shows examples for different possible output waveforms Note that in this mode the period of the PWM signal is twice the period of the timer 2 PPx 1 Note also that in this mode the distance from the center point of a high pulse to the center point of the next high pulse is always equal to the period of the signal also with changing duty cycles Thus this mode is often referred to as Center Aligned PWM 66 180 Sz SGS THOMSON Af e aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL Figure 15 PWM Mode 1 Operation and Output Waveforms Examples PPx Period 7 PTx Count Value Duty Cycle PWx Pulse Width 0 PWx 4 50 PWx 6 25 PWx 7 12 596 100 PWx 8 0 LSR Change Count LSR Latch Shadow Direction Register VR001901 Interrupt Request
84. ction bit P1H 0 P1H 7 128 135 For a pin configured as an input the output driver is put into high impedance state PORT is also used as the 16 bit address bus Ax in the non multiplexed bus modes In this mode P1L and P1H are treated as one word wide port Four lines of P1H are also used for alternate functions of the 2 Unit P1H 7 2710 CAPCOM Reg CC27 Capture Input P1H 7 CC26lO 2 Reg CC26 Capture Input P1H 7 CC25IO CAPCOM Reg CC25 Capture Input P1H 7 2410 2 Reg CC24 Capture Input P2 0 P2 15 Port 2 is a 16 bit bidirectional I O port It is bit wise programmable for input or output via a direction bit and the output drivers can be switched into push pull or open drain operation For a pin configured as input the output driver is put into high impedance state The pins of Port 2 are also used for different alternate functions for the CAPCOM Units and for fast external interrupt inputs P2 0 CAPCOM Register Cap In Comp Out P2 7 CC7IO CAPCOM Register CC7 Cap In Comp Out P2 8 CC8lO CAPCOM Register CC8 Cap In Comp Out EXOIN Fast External Interrupt O Input P2 15 CAPCOM Reg 15 Cap In Com Out Fast External Interrupt 7 Input T7IN 2 Timer 7 Count Input 170 180 S7 SGS THOMSON P3 0 P3 13 P3 15 P4 0 P4 7 P5 0 P5 15 27 36 39 44 37 A D converte
85. d Reg Port 7 Open Drain Control Reg CC16 CC31 CAPCOM Registers CC16 31 Port 7 Direction Control Reg CCM4 CCM7 CAPCOM Mode Control Reg 4 7 Port 7 Data Reg CAPCOM Timer 7 Interrupt Control Port 8 Open Drain Control Reg CAPCOM Timer 8 Interrupt Control Port 8 Direction Control Reg CC16IC CC31IC CAPCOM Reg CC16 31 Int Control Port 8 Data Reg Registers in Extended SFR Space VR001905 82 180 SGS THOMSON Af C167 FAMILY PRELIMINARY USER MANUAL In the C167 when using the CAPCOM2 unit some differences compared to the known 1 unit have to be taken into account described in the following section Besides these exceptions all the functions and operation of the CAPCOM1 Unit described in the ST10 User Manual also refer to the CAPCOM2 Unit in a respective manner a Timer T7 has no separate count input comparable to TOIN for timer TO Instead when selected for counter operation T7 will use the 2 15 151 as a count input P2 15 can either be used as general purpose l O pin or for capture input or for compare output With this the user has several options Counter T7 can either be clocked by software toggling or by compare output signals of pin P2 15 an external clock pulse for T7 can be used to trigger an interrupt request CC15INT and additionally a capture of either TO or T1 contents can be performed It is also possible to provide the same external count ev
86. d channel Empty Full Empty Channel Injection was started while converter was idle Last Channel Injection result not read gt Start conversion of injected channel ADDAT Wait for Read conflict previous injection result not read gt Wait until ADDAT read ADDAT2 Wait for Read conflict gt Wait until ADDAT2 read b At the end of an injected conversion the following conditions can occur Injected conversion result was written to ADDAT2 gt Start next conversion if necessary see Note Empty Full Full ADDAT2 Wait for Read conflict previous injection result not read gt wait until ADDAT2 read Full Full Empty Injected conversion result was written to ADDAT2 gt Start next conversion if necessary see Note Full Full Full ADDAT2 Wait for Read conflict previous injection result not read gt wait until ADDAT2 read Note The continuation of conversions is necessary in any case if the channel injection had interrupted either a continuous or an autoscan continuous conversion If an auto scan conversion was interrupted a continuation will only be performed if the last conversion before the channel injection was not the conversion of channel 0 S7 SGS THOMSON 125 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL c While an injected conversion is in progress no further channel injection request can be triggered The Channel Injection Request flag ADCRQ remains set until the the result of the injec
87. ddress output of PORT1 to generate user defined chip select signals in a system where besides other modes a non multiplexed bus mode is used When the initial bus mode is a multiplexed bus PORT will be in the high impedance mode until a non multiplexed bus is selected Thus a chip select logic connected to PORT1 might not work correctly in such a case until the appropriate initialization has taken place If internal start of execution is selected 1 the state of pins POL 6 7 is not relevant The BTYP bits in register BUSCONO are in any case set to 00 Chip Select Selection PORTO lines POH 1 2 are used to select the number of chip select lines on port P6 Either all five three two or no chip select line can be configured The state of pins POH 1 2 sampled at the end of a reset sequence is latched into bits RPOH 1 2 The number of chip select lines can not be changed once the reset sequence has been finished Software can only read the bits RPOH 1 2 to check the configuration Only during a reset hardware software or watchdog timer reset the configuration can be changed 54 180 S7 SGS THOMSON Af ie Orestes 167 FAMILY PRELIMINARY USER MANUAL The default configuration when the state of these pins sampled at the end of reset is 117 all five chip selects CSO CS4 are selected 2 por Number of Chip Selects Five Chip Select Signals CSO CS4 Default No Chip Select Signals Two Chip
88. drate no special actions are necessary If the loop is designed to store the received data into external memory however first the external bus must be enabled and programmed to the appropriate bus parameters During these operations the C167 is still in the bootstrap loading mode In this mode the address range from 000000h through 007FFFh is reserved for internal accesses In order to access external memory in this range first bit ROMS1 in register SYSCON must be set With this the 32 KByte address range reserved for internal accesses is mapped to the lower 32 KByte in segment 1 and external memory can now be accessed in the address range 000000h through 007FFFh It is not possible in the BTL mode to disable the reservation of the 32 KByte for internal accesses In order to return to normal operation a software reset SRST instruction must be executed to terminate the BTL mode Since the activation of the BTL is only performed with an external hardware reset RSTIN the software reset ignores pin POL 4 Care must be taken however that the configurations for the bus type chip selects and segment addresses are set appropriately and that a further hardware reset would again activate the BTL if pin POL 4 is sampled at a low level 58 180 Sz SGS THOMSON Af ie sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Note When the bootstrap loader is invoked the following system configuration is automatically programmed Watchdog Time
89. e no transmission is currently in progress the contents of the SOTBUF will be copied into the transmit shift register and the transmission will be started At the same time the transmit buffer empty interrupt request flag SOTBIR will be set Now the text data to be transmitted can be loaded into SOTBUF An internal flag is used to indicate that the transmit buffer is full i e has been written to Directly before the last stop bit of the current transmission is sent out the transmit complete interrupt request flag SOTIR will be set to indicate that a data frame has been sent out When the transmit buffer SOTBUF is full its data is transferred into the transmit shift register and the transmit buffer empty interrupt request SOTBIR is set In this way there are two informations flagged to the user through two different interrupt requests the transmit buffer empty interrupt SOTBINT indicates that the transmit buffer SOTBUF is ready to be loaded with the next data to be transmitted while the transmit complete interrupt SOTINT indicates that a transmission of a data frame has been finished The great advantage of this double buffering transmit is that for continuous transmissions the time frame available for loading the next data into the transmit buffer is the time required for the transmission of one complete data frame Without this feature the next data frame must be loaded within the time required to sent out the last stop bit of the previ
90. e transfer in slave mode the transfer is started through an external clock signal When the transfer is started the busy flag SSCBSY is set and the transmit interrupt request flag SSCTIR will be generated This indicates that the transmit buffer now is empty and the next transmit data can already be written into register SSCTB While the transmit data in the shift register is shifted out bit per bit the incoming receive data shifted in synchronized with the clock signal at SCLK When the preprogrammed number of bits are shifted out the same number is shifted in the contents of the shift register is transferred to the receive buffer register SSCRB and the receive interrupt request flag SSCRIR is generated If no further transfer is to take place the busy flag SSCBSY will be reset by hardware at the same time S7 SGS THOMSON 93 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 7 3 55 Control Status and Data Registers Figure 23 gives an overview of the SFRs and port pins associated with the SSC Figure 23 SFRs and Port Pins Associated with the Synchronous Serial Channel Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions SSCBA SEER E NE n MTSR P3 9 SSCTB MRST P3 8 SCLK P3 13 SSCRB ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register P3 Port 3 Data Register SSCBR Synchronous Serial Channel Baud Rate
91. e EXTS instruction 18 180 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL EXTS begin EXTended Segment sequence NOTE A lot of care must be taken over the use of the EXTS instruction with other system control or branch instructions One must also be very careful when a class B trap condition becomes present before the EXTS instruction sequence is completed In such a case the EXTS instruction ceases its validity the interrupt locking is removed and the class B trap is executed An EXTS instruction sequence can normally not be continued properly if it was interrupted FLAGS E Z V Not affected Not affected Not affected Not affected Not affected 2 lt INSTRUCTION FORMAT Mnemonic Operands Format Bytes EXTS Rwm data2 DC 00 m 2 5 seg data2 D7 00 0 ss 00 4 S7 SGS THOMSON 19 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTSR begin EXTended Segment and Register sequence EXTSR OPERATION 20 180 1 2 count lt 1 1 lt op2 lt 4 Disable Interrupts and Class A Traps Data Segment 0p1 AND SFR range Extended DO WHILE count 0 AND Class B Trap Condition TRUE next instruction count lt count 1 END WHILE count 0 Data AND SFR range Standard Enable Interrupts and Traps Overrides the standard DPP addressin
92. e as for all other standard interrupts See the ST10 User Manual Chapter 7 for more details SGS THOMSON 135 180 SYA MIERGELESTAORIES C167 FAMILY PRELIMINARY USER MANUAL 136 180 S7 SGS THOMSON Af e aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 11 PORTS In the C167 nine ports Port 0 through Port 8 are implemented with a total of 111 port lines The ports are either organized as 8 bit or 16 bit with Port 3 however providing only 15 pins Figure 38 gives an overview on all Special Function Registers SFRs and pins associated with the ports S7 SGS THOMSON 137 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 38 SFRs and Port Pins Associated with the I O Ports Port Data Registers Port Direction Control Registers Port Open Drain Control Registers POL DPOL POH 7 0 POL 7 0 P1H P1L DP1H DP1L P1H 7 0 P1L 7 0 P DP2 ODP2 i P2 15 P2 0 P3 15 P3 13 P3 0 2i P4 DP4 4 7 4 0 P i P5 15 P5 0 P DP6 ODP6 6 7 6 0 7 DP7 7 Ji 3 Bi P8 DP8 ODP8 P8 7 P8 0 POH POL Port 0 High Byte Low Byte Data Register DPOH DPOL Port 0 High Byte Low Byte Direction Control Register P1H P1L Port 1 High Byte low Byte Data Register DP1H DP1L 1 High Byte low Byte Direction Control Register Px Port x Data Register x 2 4 6 8 DPx Port x Direction
93. e port structure of pins P7 4 through P7 7 is the same as for the pins of Port 2 and is shown in Figure 50 For a detailled description please refer to Chapter 10 1 2 of the ST10 User Manual S7 SGS THOMSON 161 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL Figure 50 Block Diagram of PORT Pin P7 7 P7 4 Write ODP7 y Open Drain Symbols Latch 7 Read ODP7 y ODP7 y Input Push Pul Output Write DP7 y FEY L Open Drain Output Direction Latch Read DP7 y DP7 y Port Output Latch Alternate Pry Output Data Output Buffer P7 y CCzlO Write P7 y Compare Trigger Read P7 y Alternate Latch Data Input NT y 4 7 z 28 31 VR0Q1643 Alternate Pin Data Input Figure 51 PORT7 I O and Alternate Functions General Purpose Alternate Function Vo P7 7 CC31IO P7 6 CC30lO P7 5 CC29lO P7 4 CC28lO PORT 7 P7 3 7 2 2 7 1 POUT1 P7 0 POUTO VR001923 11 8 PORT8 162 180 S7 SGS THOMSON Aff ie aDELERTRONISS 167 FAMILY PRELIMINARY USER MANUAL Port 8 is 8 bit bidirectional general purpose port Each port line is bit addressable and can individually be programmed for input or output via the direction control register DP8 The open drain output option is available also for Port 8 Registers P8 DP8 and ODP8 are shown herebellow P8 FFD4h EAh Port 8 Data Register Reset Value 0000h
94. e state In case of an external bus configuration the lines of Port 4 can be used for output of the segment address lines 4 0 16 Least Significant Segment Address Line P4 7 A23 Most Significant Segment Address Line Port 5 is a 16 bit input only port with Schmitt Trigger characteristics The pins of Port 5 are also used as the analog inputs to the A D converter and for timer inputs P5 0 Analog Input 0 P5 15 AN15 Analog Input 15 P5 10 T6EUD GPT2 Timer T6 External Up Down Control Input P5 11 TSEUD GPT2 Timer T5 External Up Down Control Input P5 12 T6IN GPT2 Timer T6 Count Input P5 13 GPT2 Timer 5 Count Input P5 14 T4EUD GPT1 Timer T4 External Up Down Control Input P5 15 T2EUD GPT1 Timer T4 External Up Down Control Irput S7 SGS THOMSON 171 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL P7 0 P7 7 P8 0 P8 7 172 180 17 46 56 72 82 93 109 126 136 144 18 45 55 71 83 94 110 127 139 143 Port 6 is an 8 bit bidirectional I O port It is bit wise programmable for input or output via a direction bit and the output drivers can be switched into push pull or open drain operation For a pin configured as input the output driver is put into high impedance state The pins of Port 6 are also used for various alternate functons P6 0 50 Chip Select 0 Output P6 4 CS4 Chip Select 4 Output P6 5 HOLD External Master Hold Request Input P6 6 HLDA Hold Acknowl
95. ed to be any number between two and sixteen bits The 4 bit field SSCBM determines the transfer data width according to the following table Transfer SSCBM Transfer Data Width Data Width reserved 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit Bit 4 SSCHB Heading Bit Control of register SSCCON determines whether the LSB least significant bit or the MSB most significant bit of the data is the first transmitted bit With SSCHB 0 the LSB will be shifted first This mode is required by the synchronous mode of the 5 0 in the C167 and also the synchronous modes of ASCO ASC1 of the ST10x166 family and the serial ports of the 8051 family Serial interfaces operating compatible to the SPI mode however require the MSB to be the first transmitted bit In this case SSCHB must be set to 17 Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSCTB and SSCRB with the LSB of the transfer data at the LSB position of these registers i e bit 0 The internal logic at the shift register totally takes care of correctly performing the selected operation Examples for this feature are shown in Figure 24 S7 SGS THOMSON 97 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 24 LSB First MSB First Operation Examples Example 8 Bit Data Width Transmit Data 65h 0110 0101 Receive Data 93h 1001 0011 LSB FIRST
96. edge Output P6 7 BREQ Bus Request Output Port 7 is an 8 bit bidirectional I O port It is bit wise programmable for input or output via a direction bit and the output drivers can be switched into push pull or open drain operation For a pin configured as input the output driver is put into high impedance state The pins of Port 7 are also used for alternate functions of the PWM and the CAPCOM2 Unit P7 0 POUTO PWM Channel 0 Output P7 3 POUT3 PWM Channel 3 Output P7 4 CC28IO CAPCOM2 Register CC28 Cap In Comp Out 7 7 CC31IO 2 Register CC31 Cap In Comp Out Port 8 is an 8 bit bidirectional I O port It is bit wise programmable for input or output via a direction bit and the output drivers can be switched into push pull or open drain operation For a pin configured as input the output driver is put into high impedance state The pins of Port 8 are also used for alternate functions of the 2 Unit P8 0 6 CAPCOM Register CC16 Cap In Comp Out P8 7 CC23IO CAPCOM2 Register CC23 Cap In Comp Out Digital 5 V Power Supply Digital Ground reserved SGS THOMSON SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL ST10167 is housed 144 Metric Plastic Quad Flat Pack package according to the EIAJ standard The body dimensions are 28 28 mm the pitch is 0 65 mm S7 SGS THOMSON 173 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER M
97. egister which specifies the active address range for this BUSCON register That means for an external access to an address range specified through an ADDRSELx register the parameters of the bus are controlled by the respective BUSCONXx register The second difference is the initialization after reset The BUSCON 1 4 registers are always initialized to all 0000 while the BUSCONO register is loaded according to the selected startup configuration during reset A further difference between the BUSCON1 4 and the BUSCONO registers is in the options for the chip selects detailled in Chapter 3 3 38 180 ST SGS THOMSON Af crt tronics 167 FAMILY PRELIMINARY USER MANUAL Note Special care must be taken when programming the BUSCON registers An external bus will be enabled as long as at least in one of the BUSCON register the BUSACTx bit is set Port 1 will be used for address output if at least through one of the BUSCON registers a non multiplexed bus is selected Port 1 will also continue to output the addresses for an access via a multiplexed bus controlled through another BUSCON register BUSCON1 FF14h 8Ah Bus Configuration Register 1 Reset Value 0000h 15 14 13 12 11 10 9 8 CSWEN1 CSREN1 EM RDYEN1 BUSACT1 ALECTL1 7 6 5 4 3 2 1 0 BTYP MTTC1 RWDC1 MCTC 015 CSWEN1 Write Chip Select Enable control bit b14 CSREN1 Read Chip Select Enable control bit B13 R Reserved b12 RDYEN1 READY I
98. ents for both CAPCOM units by externally connecting the signal to both inputs TOIN and CC15lO In this way TO and T7 count synchronously the same external event with an optional capture and interrupt request for this count event Figure 21 shows both CAPCOM units and a configuration example for synchronous operation Since in this example TO and T7 are clocked by the same event the two timers can be regarded as one timer having access to all 32 capture compare registers In a similar manner T1 and T8 can be clocked with the same internal clock or GPT2 timer T6 clock and they can be regarded in this case as one timer having also access to all 32 registers However since it is not possible to start both timers with one instruction a slight time delay may be possible S7 SGS THOMSON 83 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 21 CAPCOM1 CAPCOM2 Configuration Example TOIN CPU Clock ly CCO CC1 D a a p CC2 t CC3 EI r CC4 roo e CC5 External d ____4 gt PORT P2 Connection G ccs C m r 9 m E CC10 CC11 r er e e 12 TO CC13 14 15 6 CC15 Signal Sele Description 1 p p td amp PORT ps t t e u r roo e e rj Internal m lt Connection C C J o m 7L 4
99. er This register controls the bus for any accesses outside the ranges defined through the ADDRSEL register If no other BUSCONXx register selects a bus in a specific address range the external bus in the entire address range of up S7 SGS THOMSON 41 180 SYA MISROELECTROMICS 167 FAMILY PRELIMINARY USER MANUAL to 16 MByte is controlled by the BUSCONO register Thus programming another BUSCON to a certain address range always overlaps the BUSCONO address range however this is an intended implemented operation and no problems will occur in this case It can be regarded in this way that the BUSCON1 4 and ADDRSEL1 4 registers have the same level of priority among them thus it is not possible to determine the preference in an address overlap case while BUSCONO has a lower priority It is possible however to overlap an ADDRSEL address range with an internal ROM RAM SFR ESFR etc address range In this case accesses to addresses in the overlapping regions are always made to the internal space Figure 7 BUSCON Configuration Examples Non Segmented Mode Segment Mode Example Example 16M 64K BUSCONS 4MByte CS3 12M TT 7 TT R 32K 48K BUSCON4 a Start 32K CS4 BUSCON1 4MByte CS1 8M 32K 0 0 a BUSCON3 Range 8K ded Start 24K CS3 SEES CS4 BUSCONO Range 8K Start 16K CSO n 8 BUSCON0 CS0 BUSCON2 Lc Start 8K CS2 1 Range 4K BU
100. er the chip will start with internal ROM or external memory The lines of PORTO are then used during reset to configure the system such that the state of the PORTO pins read during reset determines the system startup configuration The pins of PORTO i e POL and POH contain weak pullup devices ca 100 KOhm which are switched on during the entire time that a reset sequence is active this is true for any hardware software or watchdog timer reset and pull the pins to a high level The state of these pins are read during reset If all pins are read as 1 a default configuration is selected If a different configuration is required this can be selected by pulling individual PORTO lines low during reset with external pulldown devices of ca 15 KOhm After the reset sequence has terminated the internal pullup devices at PORTO are switched off If external pulldown devices are connected to individual PORTO pins they can be left connected also after reset if no corruption of the function of the PORTO pins can occur Special care should be taken with respect to output load and voltage levels when using values of less than 15 KOhm Note The current DC specification for the output voltages VOH in the Data Sheet specify an output voltage of VOHmin of 0 9 VCC at an output current IOH of 100 uA Using an external pulldown device of 15 KOhm would violate this specification since the current drawn through this pulldown is much higher However characteriz
101. errun error interrupt request will be generated in this mode since this condition is not possible ADCON FFAOh DOh A D Converter Control Register Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b15 to b12 R Reserved b11 ADCRQ ADC Channel Injection Request Flag Can be set by software or by a capture compare event of register CC31 to trigger a channel injection This bit has only an effect if ADCIN 1 ADCRQ 0 No channel injection request ADCRQ 1 Channel injection request enabled b10 ADCIN ADC Channel Injection Enable control bit ADCIN 0 Channel injection disabled ADCIN 1 Channel injection enabled b9 ADWR ADC Wait for Read control bit ADWR 0 New conversion is immediately started in autoscan or continuous modes overrun error enabled ADWR 1 New conversion in autoscan or continuous modes is not started if ADDAT ADDAT2 is full and new conversion results is ready overrun error is disabled b8 ADBSY ADC Busy Flag ADBSY 0 No conversions in progress ADBSY 1 Conversion in progress b7 ADST ADC Start bit b6 R Reserved b5 b4 ADM ADC Mode Selection b3 to 60 ADCH ADC Analog Input Channel Selection S7 SGS THOMSON 119 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL An internal flag ADDAT Full the same used for flagging an overrun error is used to indicate a write of a conversion result to register ADDAT As long as this flag is set in
102. ery external high byte write access READY Ready Input When the Ready function is enabled a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level External Access Enable pin A low level at this pin during and after reset forces the C167 to begin instruction execution out of external memory A high level forces execution out of the internal ROM For ROMless versions this pin must be tied to 0 SGS THOMSON 169 180 SYA MIERGELESTAORIES C167 FAMILY PRELIMINARY USER MANUAL PORTO PORTO consists of the two 8 bit bidirectional I O ports POL and POL O POL 7 100 107 They are bit wise programmable for input or output via a direction bit 0 POH 7 108 For configured as input the output driver is put into high 111 117 impedance state In case of an external bus configuration PORTO serves as the address and address data bus in the multiplexed bus modes and as the data bus in the non multiplexed bus modes Non Multiplexed Bus Modes Data Width 8 Bit 16 Bit POL O POL 7 DO D7 DO D7 0 7 D8 D15 Multiplexed Bus Modes Data Width 8 Bit 16 Bit POL O POL 7 ADO AD7 ADO AD7 0 7 A8 A15 AD8 AD15 1 PORT1 consists of the two 8 bit bidirectional I O ports P1L and P1H P1L O P1L 7 118 125 They are bit wise programmable for input or output via a dire
103. eset at the PO pins see System Startup Configuration One can see that other than in the ST10x166 external execution will start with the ALE lengthening enabled offering the slowest possible bus The user can reprogram the bus parameters during the initialization or during normal run time to values required by the external hardware Other than for the bus configuration registers BUSCON1 4 the BUSCONO register has no associated address select register ADDRSEL Instead the BUSCONO register controls the bus for any external accesses to addresses which are not covered by one of the address select register i e it fills the gaps between these address ranges To indicate an external access controlled through the BUSCONO register and to allow a simple selection of the memory or peripheral an individual chip select line 50 is assigned to the BUSCONO register If CS0s is enabled through System Startup Configuration see section 3 5 it goes to a low level for each external access controlled through BUSCONO i e for each external access outside the range of the ADDRSEL registers It will go to a high level for each other access See section 3 3 for details on the chip select lines 3 2 3 BUSCON 1 4 and ADDRSEL1 4 Registers Hereafter is shown the configuration of a BUSCON1 4 register Although these registers look similar to the BUSCONO register some differences exist Each of the BUSCON1 4 registers has an associated ADDRSEL1 4 r
104. evel After the reset sequence has been finished the pullup devices are switched off The lines selected for chip select operation are then be automatically switched to the output mode and drive the appropriate level The pins not configured for chip select operation will return to the high impedance state When an HOLD is requested by an external device then besides switching the address and data bus to the high impedance mode the C167 also turns the chip select signals off when generating the acknowledge signal HLDA This enables the external master to not only control the address and data bus but to also use the same chip select lines to access the individual external devices connected to the bus The chip selects can be turned off in such a case in two ways controlled through the respective Open Drain Control register see section 11 6 for the port If the respective control bit ODPx y is 0 the chip select line will be held high through switching on the internal pullup device at this pin If ODPx y 1 this pullup device will not be activated the pin will float to the high impedance state Either an external pullup device has to be connected in this case or the external master is capable of pulling the lines to an appropriate level 3 3 1 Address Chip Selects A chip select which is generated by decoding the address lines and which is activated for the whole duration of an external bus cycle is named an Address Chip Select in the co
105. f the normal SFR range and the addressing capability with 8 bits is totally occupied by this range Thus a method is implemented to allow the short address access REG or BITOFF also for the new ESFR range Instead of a windowing option where either one or the other of the SFR ranges would be available this method allows both ranges to be accessible at the same time For this purpose an Extend Register EXTR EXTPR EXTSR instruction is implemented This instruction is required before an access to a register in the ESFR range is made with a short addressing mode see also Chapter 1 Instruction Set The tools will provide options to insert this instruction automatically depending on the addressing mode used The following examples show accesses to the normal and the extended SFR ranges 26 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Example 1 Direct MEM access to an ESFR No EXTR instruction required MOV RO const16 GPRs are directly accessible in both ranges MOV ODP2 RO mem reg addressing mode for the ESFR ODP2 Example 2 Direct REG access to an ESFR EXTR instruction required EXTR 4 Extend Register for the following four instructions MOV ODP2 data16 reg data16 addressing mode BFLDL DP6 mask data8 bitoff addressing mode BSET DP1H 7 bitaddr bitoff bitnr addressing mode MOV XPOIC R1 mem reg addressing mode XPOIC via mem R1 via reg GPRs
106. fers are continued and SSCBSY remains set In the slave mode SSCBSY is set as soon as the value in the transmit buffer is copied into the shift register and remains set until the last bit of the last data is received That means the busy flag is not reset between continuous transfers see Chapter 7 4 4 for details on continuous transfers SSC Bit Count Field When the SSC is disabled the lower four bits SSCBM of register SSCCON are used to initialize the data width of the transfer data When the SSC is enabled these four bits represent the shift counter SSCBC and are updated with each shift Software should never modify this bit field if the SSC is enabled and should only read SSCBC if certain analysis routines are necessary after the occurence of an error 7 3 2 Buffer Registers SSCTB and SSCRB Register SSCTB holds the data to be transmitted while SSCRB contains the data which was received during the last transfer Both registers are 16 bit registers however only the number of least significant bits defined through the data transfer width in SSCBM are relevant This means for example when the data transfer width is set to 10 bits bits O through 9 hold the data to be transmitted or received while bits 10 through 15 are unused As mentioned above the data in these registers is always right aligned that means bit O of these registers always holds the LSB of the data A further discussion of the operation of these registers can
107. g scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any long or indirect address in the EXTSR instruction sequence the value of op1 determines the 8 bit segment address bits A valid for the corresponding data access The long or Mdire t address itself represents the 16 bit segment offset address bits A z Depending on the value of op2 the period of validity of the EXTSR instruction extends over the sequence of the next 1 to 4 instructions being executed after the EXTSR instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the EXTSR instruction yy 55 S v NIGHOELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTSR begin EXTended Segment and Register sequence NOTE A lot of care must be taken over the use of the EXTSR instruction with other system control or branch instructions One must also be very careful when a class B trap condition becomes present before the EXTSR instruction sequence is completed In such a case the EXTSR
108. gdom U S A 180 180 SGS THOMSON Af e sDELEETRONISS
109. gh a Wired AND configuration using an external pullup device In this way it is possible for example to have any channels to operate in a burst mode besides the implemented burst mode for channels 0 and 1 78 180 S7 SGS THOMSON aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 5 SECOND CAPTURE COMPARE UNIT CAPCOM2 In the C167 the entire CAPCOM Unit known from the ST10x166 will be implemented twice In the following the two units will be referred to as CAPCOM1 the unit known from the ST10x166 and 2 The 2 unit gives the user two extra timers and 16 extra capture compare registers The new 2 Unit is shown in Figure 19 S7 SGS THOMSON 79 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 19 CAPCOM2 Unit Block Diagram 80 180 yy 5 S NIGHOELECTRONICS System P2 15 eee o Bas Control Timer T6 RENE P8 0 Capt Comp Reg CC16 7 1 4 P81 m CC17 CC17IR P82 CC18 t i Mm 19 L PORT8 pm CC20 CC20IR 85 CC21 CC21IR P amp 6 m 22 r CC22lR 987 CC23 tr CC23IR LL ping CC24 H CC24IR 1 5 1 CC25 gt CC25IR ree 2 4 P1H 6 CC26 t CC26IR i 7 27 CC27IR z
110. h that no additional NOPs are required Depending on the value of the period of validity of the EXTR instruction extends over the sequence of the next 1 to 4 instructions being executed after the EXTR instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the EXTR instruction NOTE A lot of care must be taken over the use of the EXTR instruction with other system control or branch instructions One must also be very careful when a class B trap condition becomes present before the EXTR instruction sequence is completed In such a case the EXTR instruction ceases its validity the interrupt locking is removed and the class B trap is executed An EXTR instruction sequence can normally not be continued properly if it was interrupted SGS THOMSON SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL EXTR begin EXTended Register sequence FLAGS 7 V C N Not affected Not affected Not affected Not affected Not affected lt INSTRUCTION FORMAT Mnemonic Operands Format Bytes EXTR data2 D1 1044 0 2 S7 SGS THOMSON 19 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTP begin EXTended Page sequence EXTP 1 2 OPERATION count lt 2 1 lt op2 lt 4 Disable Interrupts and Class A Traps Data Page 0p1 DO WHILE count 0 AND Class B Trap
111. he EXTP instruction sequence is completed In such a case the EXTP instruction ceases its validity the interrupt locking is removed and the class B trap is executed An EXTP instruction sequence can normally not be continued properly if it was interrupted FLAGS 7 V C N Not affected Not affected Not affected Not affected Not affected ZO lt NM INSTRUCTION FORMAT Mnemonic Operands Format Bytes EXTP Rwm data2 DC 01 m 2 EXTP pag data2 D7 01 0 pp 0 00pp 4 S7 SGS THOMSON 15 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTPR begin EXTended Page and Register sequence EXTPR OPERATION 16 180 1 2 count lt op2 1 lt op2 lt 4 Disable Interrupts and Class A Traps Data Page 0p1 AND SFR range Extended DO WHILE count 0 AND Class B Trap Condition TRUE next instruction count lt count 1 END WHILE count 0 Data Page SFR range Standard Enable Interrupts and Traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTPR instruction becomes immediately active such that no additional NOPs are re
112. he WRH or WRL signals goes active There will be no distinction between writing to the low byte to the high byte or to both The read write chip selects will also be affected by the read write delay control RWDCx of a BUSCONx register 3 4 Byte High Enable or Write High Write Low Operation 46 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL When writing bytes to external word wide memories or peripherals regardless whether they are true word wide devices or two 8 bit devices in parallel a distinction has to be made between writing to the low or to the high byte or to both For this purpose the address line AO and the Byte High Enable signal BHE are used to properly select either half or both halfs of the device Figure 11 shows an example for this connection where the chip select signal is gated with and see also the ST10 User Manual SGS THOMSON 47h80 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 11 Connection Possibilities of an External Read Write Device a Separate Chip Select Inputs 16 Bit Device CS HIGH Address Bus Data Bus cs from Decoder b Separate Write Strobe Inputs 16 Bit Device RD cs from Decoder AO WR LOW WR HIGH Address Bus DO D15 lt gt Bus VR001896 48 180 S7 SGS THOMSON Af
113. he pins of Port 4 can either be used as general purpose pins or they can serve for the segment addresses A23 A16 The following table lists the Port 4 pins and their alternate functions Alternate Function Segment Address Line 16 Segment Address Line 17 Segment Address Line 18 Segment Address Line 19 Segment Address Line 20 Segment Address Line 21 Segment Address Line 22 Segment Address Line 23 S7 SGS THOMSON 151 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL The selection between the general purpose function or alternate segment address function is done during reset see Chapter 3 5 The selection can be done in steps of zero segment address two A17 A16 four A19 A16 or all eight port lines A23 A16 As an example when selecting 4 segment address lines Port 4 pins P4 0 through P4 3 will be used for the segment address and lines P4 4 through P4 7 can be used for general purpose I O The table below illustrates these options Selected Number of Segment Address Lines Figure 44 illustrates the 1 0 and alternate functions of Port 4 The shaded bars in the Figure indicate that the alternate function is selected in groups Figure 44 PORTA I O and Alternate Functions General Purpose Alternate Function VO A23 A22 A21 A20 A19 A18 A17 A16 VR001920 The number of segment address lines selected during reset can be read in register RPOH see Chapter 3 5 Bits
114. his instruction is out of the scope of the atomic sequence S7 SGS THOMSON 7180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 1 22 Extend Segment Extend Page Instructions These instructions allow the user to bypass the code segment and data page scheme for specific number of instructions between 1 10 4 These instructions will mainly be used by HLL Compilers to access large data areas without the overhead of data page pointer swapping As with the atomic instruction interrupts and Class A Traps are disabled for up to 4 instructions after the extend instructions Additional instruction formats are implemented for a combination of the Extend Segment Extend Page instructions with the Extend Register instruction 1 3 Extend Register Instructions In the C167 due to the amount of Special Function Registers SFRs required to control the on chip peripherals the SFR space is extended This new Extended SFR range ESFR can be accessed like any other memory location with a 16 bit address mem or Rw However when using short 8 bit addresses REG or BITOFF distinction has to be made between the normal and the extended SFR space see also Chapter 2 4 For this purpose Extend Register instructions are implemented which allow access to the ESFR space with short 8 bit addresses for a specific number of instructions between 1 and 4 Again interrupts and Class A Traps are disabled during execution of this code sequence Add
115. iary Timer T2 Control Register Reset Value 0000h 15 14 13 12 11 10 9 8 Pee me 7 6 5 4 3 2 1 T2R T2M Tel b15 to b9 R Reserved b8 T2UDE Timer 2 External Up Down Control Enable bit b7 T2UD Timer 2Up Down Control bit b6 T2R Timer 2 Run bit 128 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 0 Timer Counter 2 stops T R 1 Timer Counter 2 runs b5 to b3 T2M Timer 2 Mode Control b2 to bO 21 Timer 2 Input Selection TACON FF44h A2h Auxiliary Timer T4 Control Register Reset Value 0000h 15 14 13 12 11 10 9 8 6 5 4 3 b15 to b9 Reserved b8 T4UDE Timer 4 External Up Down Control Enable bit b7 TAUD Timer 4 Up Down Control bit b6 Timer 4 Run bit T4R 0 Timer Counter 4 stops 1 Timer Counter 4 runs b5 to b3 TAM Timer 4 Mode Control b2 to bO TAI Timer 4 Input Selection T5CON FF46h A3h Auxiliary Timer 5 Control Register Reset Value 0000h b15 T5SC Timer 5 Capture Mode Enable bit T5SC 0 Capture into register CAPREL disabled T5SC 1 Capture into register CAPREL enabled b14 T5CLR Timer 5 Clear bit T5CLR 0 Timer 5 is not cleared on a capture T5CLR 1 Timer 5 is cleared on a capture b13 b12 CI Register CAPREL Input Selection b11 to b9 R Reserved b8 T5UDE Timer 5 External Up Down Control Enable bit S7 SGS TH
116. instruction ceases its validity the interrupt locking is removed and the class B trap is executed An EXTSR instruction sequence can normally not be continued properly if it was interrupted FLAGS 7 V C N Not affected Not affected Not affected Not affected Not affected ZO lt NM INSTRUCTION FORMAT Mnemonic Operands Format Bytes EXTSR data2 DC 10 m 2 EXTSR seg 2 D7 10 0 ss 00 4 S7 SGS THOMSON 21 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 22 180 S7 SGS THOMSON Af ict tronics 167 FAMILY PRELIMINARY USER MANUAL 2 ON CHIP MEMORY 2 1 ROM In this version of the 5710167 8 KByte of internal ROM are implemented depending on market needs future versions with different ROM sizes may follow The ROM can either be mapped to segment 0 addresses 000000 001FFFh or to segment 1 addresses 010000 011FFFh Although the ROM is 8 Kbyte in size a full 32 KByte address range will be reserved for it When mapping the ROM to segment 0 the address range 000000h through 007FFFh will be mapped internally that is no external addresses will be generated within this range When mapping the ROM to segment 1 the address range 010000h through 017FFFh will be reserved and no external addresses are generated within this range In either case the internal ROM is multiple mapped to this 32 KByte range Crossing the ROM boundary at n
117. instruction to BUSCONO POL 7 POL 6 Selected Bus Type Multiplexed 16 Bit Bus Default Non Multiplexed 16 Bit Bus Multiplexed 8 Bit Bus Non Multiplexed 8 Bit Bus O O Depending on the selected initial bus mode PORTO and PORT1 will be automatically switched into the appropriate mode directly after reset S7 SGS THOMSON 53 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Note If an initial 8 bit non multiplexed bus mode is selected the pins of POL will operate as the 8 bit data bus while POH will be switched to the high impedance input mode and be used as general purpose provided none of the other bus modes will be activated through programming of the BUSCON registers during the initialization or later Note If an initial multiplexed bus is selected the pins of PORT1 will remain in the high impedance mode after reset until either a non multiplexed bus is selected through programming of the BUSCON registers during the initialization or later or the pins are programmed for general purpose I O As soon as in a system once non multiplexed bus is enabled through one or more of the BUSCON register PORT1 will from now on always output the address regardless whether the access is via a non multiplexed or a multiplexed bus It will only stop the output of the address if in none of the BUSCON registers a non multiplexed bus is selected This behaviour must be specially regarded when using the a
118. itional instruction formats are implemented for a combination of the Extend Register instruction with the Extend Segment Extend Page instructions Examples for these instructions can be found in section 2 4 8 180 Sz SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Note Signal active low will be marked in the text with and with in the figures S7 SGS THOMSON 9 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL ATOMIC ATOMIC OPERATION 10 180 begin ATOMIC sequence 1 count lt 1 1 lt 1 lt 4 Disable Interrupts Class Traps DO WHILE count 0 AND Class B Trap Condition TRUE next instruction count lt count 1 END WHILE count 0 Enable Interrupts and Traps Causes standard interrupts and class hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active such that no additional NOPs are required Depending on the value of the period of validity of the ATOMIC sequence extends over the sequence of the next 1 to 4 instructions being executed after the ATOMIC instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC instruction NOTE A lot of care must be taken over the use of the ATOMIC instruction wi
119. jection Request bit ADCRQ ADCON 11 is set The converter will complete the current conversion if any is in progress and will then inject the conversion of the specified channel When the conversion of this channel is complete the result will be placed into the new result register ADDAT2 and a Channel Injection Complete Interrupt request will be generated For this interrupt request the ADC Overrun Error interrupt node is used which in the Wait for Read mode as described above is not used The new result register ADDAT2 is organized as register ADDAT However the difference is that with register ADDAT the number of the channel just converted is written to the upper 4 bits while with ADDAT2 the upper 4 bits are written to by software to specify the number of the channel to be converted by the Channel Injection These 4 bits in ADDAT2 are not modified by the A D converter Note Since there is no buffering of the channel number for an injected conversion the upper four bits of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to only change the channel number after an injected conversion was performed and before a new one is requested 122 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL As mentioned above the channel injection can be initiated by different events One is a set
120. k enabled b5 SOPEN Parity Check Enable bit SOPEN 0 Parity check disabled SOPEN 1 Parity check enabled b4 SOREN Receiver Enable bit Used to initiate reception Reset by hardware after a byte in synchronous mode has been received SOREN 0 Receiver disabled SOREN 1 Receiver enabled b3 SOSTP Number of Stop Bits Selection SOSTP 0 One stop bit SOSTP 1 Two stop bits b2 to 60 SOM ASCO Mode Control 6 2 Double Buffered Transmit An additional buffer register is implemented for the transmit buffer SOTBUF in the asynchronous synchronous serial interface ASCO This allows a double buffered transmission that is while a transmission is in progress the next data to be transmitted can already be loaded into the transmit buffer SOTBUF In this way it is possible to perform continuous transmissions without any gaps other than the programmed number of stop bits between two consecutive transmissions An additional interrupt source and vector will be implemented in order to flag the condition that the transmit buffer is empty and ready to be loaded with the next data 88 180 Sz SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL The Transmit Buffer Empty interrupt is controlled through register SOTBIC see Chapter 10 The operation of the buffered transmission is as follows the data to be transferred is written into the transmit buffer SOTBUF If the transmit shift register is empty i
121. le bitaddressable non bitaddressable CCM4 FF22h 91h FE60h 30h CC16IC F160h BOh F050h 28h 5 FF24h 92h FE62h 31h CC171C F162h B1h F052h 29h CCM6 FF26h 93h FE64h 32h CC18IC F164h B2h F054h 2Ah COM7 FF28h 94h FE66h 33h CC19IC F166h B3h FO56h 2Bh 78 FF20h 90h FE68h 34h 20 F168h B4h FE6Ah 35h CC21IC F16Ah B5h FE6Ch 36h 221 F16Ch B6h FE6Eh 37h CC23IC F16Eh B7h FE70h 38h CC24IC F170h B8h FE72h 39h CC25IC F172h B9h FE74h 8Ah 26 F174h BAh FE76h 3Bh 27 F176h BBh FE78h 3Ch 28 F178h BCh FE7Ah 3Dh 291 F184h C2h FE7Ch 3Eh CC30IC F18Ch C6h FE7Eh SFh CC31IC F194h CAh T7IC F17Ah BDh T8IC F17Ch BEh S7 SGS THOMSON 81 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL Figure 20 SFRs and Port Pins Associated with the CAPCOM2 Unit Ports amp Direction Control Data Registers Control Registers Interrupt Control T7REL T7 T7IN CC15I0 T8REL P2 15 L T8 Alternate Functions T78CON CC19IC CC161O CC23lO P8 0 P8 7 CC23 E CC23IC P1H CC24IO CC271O CC27 271 1 4 1 7 1 1 CC28lO CC311O P7 4 P7 7 Port 1 High Byte Direction Ctl T78CON CAPCOM Timer 7 amp 8 Control Port 1 High Byte Data Reg Timer 7 Register Port 2 Open Drain Control Reg T7REL CAPCOM Timer 7 Reload Reg Port 2 Direction Control Reg T8 CAPCOM Timer 8 Register Port 2 Data Reg CAPCOM Timer 8 Reloa
122. ll be copied into the special register RPOH shown in Chapter 3 5 This register is read only and holds the selection for the number of chip selects and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pullup devices are switched off and PORTO will be switched to the appropriate operating mode 11 1 PORT1 Ports P1L and P1H As with PORTO described above also PORT1 known from the ST10x166 is split into two byte wide ports in the C167 The registers are P1L P1H DP1L and DP1H analogous to the PORTO registers shown hereafter P1L FFO4h 82h PORT 1 Low Byte Data Register Reset Value 0000h 7 6 5 4 3 2 1 0 b7 to b0 P1L y Port Data Register y Oto 7 FFO6h 83h PORT 1 High Byte Data Register Reset Value 0000h 7 6 5 4 3 2 1 0 P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1HO b7 to b0 P1H y Port Data Register 0 to 7 144 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL DP1L F104h 82h PORT 1 Low Byte Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 DP1L7 DP1L6 DP1L5 DP1L4 DP1L3 DP1L2 DP1L1 DP1LO b7 to b0 DP1L y Direction Control y 0to 7 DP1L y 0 Port line P1Ly is input high impedance DP1L y 1 Port line P1Ly is output DP1H F106h 83h PORT 1 High Byte Direction Control Register Reset Value 0000h 7 6 5 4 3 2 1 0
123. lock is CPU clock PTIO 1 PTO input clock is CPU clock 256 PTR3 PWM Timer Run Control bit b2 PTR2 PWM Timer PT2 Run Control bit b1 1 PWM Timer PT1 Run Control bit 00 PTRO PWM Timer PTO Run Control bit PTRO 0 PTO stops PTRO 1 PTO is running PWM Control Register PWMCON1 This register controls the modes of operation and the outputs of the PWM channels The mode of a channel whether it operates in standard or symmetrical PWM mode edge or center aligned mode is controlled by a mode bit PMx For channels 0 and 1 burst mode can be enabled disabled by the control bit 01 The single shot mode of channels 2 and 3 is selected through bits PS2 and PS3 respectively For each PWM channel one bit PENx controls whether the associated output pin is enabled or not If the output is not enabled the respective pin can be used for general S7 SGS THOMSON 75 180 SYA MISROELECTROMICS 167 FAMILY PRELIMINARY USER MANUAL purpose I O and the PWM signal can only be used to generate an interrupt request The register is shown hereafter PWMCON1 FF32h 99h PWM Module Control Register 1 Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 b15 PS3 PWM Channel 3 Single shot Mode control bit b14 PS2 PWM Channel 2 Single shot Mode control bit PS2 0 Normal operation PS2 1 Single shot operation b13 Reserved b12 1 PWM Channel 0 and 1 Burst Mode Con
124. m 2 pag data2 D7 11 0 pp 0 00pp 4 S7 SGS THOMSON 17 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTS begin EXTended Segment sequence EXTS 1 2 OPERATION count lt 2 1 lt op2 lt 4 Disable Interrupts and Class A Traps Data Segment 0p1 DO WHILE count 0 AND Class B Trap Condition TRUE next instruction count lt count 1 END WHILE count 0 Data Page DPPx Enable Interrupts and Traps Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTS instruction becomes immediately active such that no additional NOPs are required For any long or indirect address EXTS instruction sequence the value of op1 determines the 8 bit segment address bits valid for the corresponding data access The long or address itself represents the 16 bit segment offset address bits A 5 Ao Depending on the value of op2 the period of validity of the EXTS instruction extends over the sequence of the next 1 to 4 instructions being executed after the EXTS instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with th
125. mer 4 External Up Down Control Input GPT2 Timer 5 External Count Input GPT2 Timer 6 External Count Input GPT2 Timer 5 External Up Down Control Input GPT2 Timer 6 External Up Down Control Input To control these new functions the following additional control bits are implemented in the respective timer control registers T2CON 8 Timer 2 External Up Down Control Enable Bit T4CON 8 Timer 4 External Up Down Control Enable Bit T5CON 4 Timer 5 Mode Control Bit 1 T6CON 4 Timer 6 Mode Control Bit 1 T6CON 3 Timer 6 Mode Control Bit 0 T5CON 8 Timer 5 External Up Down Control Enable Bit T6CON 8 Timer 6 External Up Down Control Enable Bit S7 SGS THOMSON 127 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Since a software up down control bit TxUD is already implemented for all timers T2 through T6 with the additional input lines a number of options now is available for the up down control of the general purpose timers x 2 6 Input Count TxEUD b Direction With the new mode control bits for T5 and T6 now all the options for timer counter and gated timer modes are available The following table shows these options Timer 5 6 Timer Mode Timer 5 6 Counter Mode Timer 5 6 Gated Timer Mode gate is active low Timer 5 6 Gated Timer Mode gate is active high The bits and functions of the control registers TxCON of timers T2 T4 T5 and T6 are shown hereafter T2CON FF40h A0h Auxil
126. n in Mode 0 Operation Input Clock 20 MHz CPU Clock 78 13 19 53 4 88 KHz 1 22 KHz 305 Hz 50 ns Resolution OPY black A94 1 22 KHz 305 Hz 76 19 1 Hz 4 77 Hz 3 2 usec Resolution Table 4 1 2b PWM Unit Frequencies and Resolution in Mode 1 Operation Resolution gt i 12 Bit Input Clock 20 MHz 39 1 KHz 9 77 KHz 2 44 KHz 610 Hz 152 6 Hz 50 ns Resolution Hd 610 Hz 152 6 Hz 38 15 Hz 9 54 Hz 2 4 Hz 3 2 usec Resolution Note The timer run bit PTRx only enables or disables the input clock to the timer it has no direct effect on the generation of the PWM signal The timer is started through setting bit PTRx and it will continue counting until bit PTRx is reset If bit PTRx is cleared by software the timer will stop when the instruction writes to the control register PWMCONO and the timer contents will remain at the last value The PWM output signal will then also remain at the level which was active at the time the timer was stopped one wants to stop the generation of a PWM signal there are several different options Since the PWM output signal is generated through a greater than or equal to comparison between the timer contents and the contents of the PWx register respectively the shadow register PWM Output Signal PTx gt PWx one can force the output signal to a certain level through writing appropriate values either to the PWx register or to the timer PTx itself For example
127. n operate with or require more than 16 data bits per transfer It is just a matter of software how long a total data frame length can be Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly This option can also be used to for example interface to byte and word wide slaves at the same serial bus 112 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 7 5 Error Detection Four different types of error conditions can be automatically detected by the SSC Two of these can be detected in master mode while in slave mode all four can be detected An error indication flag 55 will be set if the error condition occurs and an error interrupt request can optionally be generated Defined for Enable Bit Indication Flag Transmit Error Slave Mode SSCTEN Receive Error Master and Slave Mode SSCREN Phase Error Master and Slave Mode SSCPEN Baudrate Error Slave Mode SSCBEN The error detection enable bits SSCxEN are only accessible for initialization when the SSC is disabled SSCEN 0 while the respective error indication flags are accessible only when the SSC is enabled SSCEN 1 When an error occurs in any case the respective error indication flag SSCxE will be set All four error types can be programmed to generate the same error interrupt SSCEINT controlled through regis
128. nd is not described here One should take care that pin POL O is always at a high level during and at the end of a reset see Note Bootstrap Loader Mode PORTO pin POL 4 is used to enter the on chip bootstrap loader If at the end of the reset sequence a low level is sampled at this pin the internal bootstrap loader is invoked regardless of the state of the other PORTO pins specified for system startup configuration The operation of the bootstrap loader is detailled in the next chapter Note that the bootstrap loader mode must be terminated with a software reset instruction this does not check line POL 4 or through a hardware reset provided pin POL 4 is now at a high level Note Special care has to be taken that only the specified system startup configurations are selected If one or more of the PORTO pins marked as reserved in Table 3 5 are sampled at a low level at the end of a reset unexpected results and hang up situations may occur If the design is critical such that the specified high level can not be guaranteed through the internal pullup device for example if an external device connected to a PORTO pin sinks a too high current an additional external pullup device should be connected in such a case S7 SGS THOMSON 57 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 3 6 On Chip Bootstrap Loader In the C167 an on chip bootstrap loader BTL is implemented Via this BTL it is possible to load a pr
129. nput Enable control bit RDYEN1 0 READY function disabled for BUSCON1 accesses RDYEN1 1 READY function enabled for BUSCON1 accesses 011 R Reserved b10 BUSACT1 Bus Active control bit b9 ALECTL1 ALE Lengthening control bit b8 R Reserved b7 b6 BTYP External Bus Configuration Control b5 MTTC1 Memory Tri state Time Control b4 RWDC1 Read Write Delay Control b3 to b0 MCTC Memory Cycle Time Control For each BUSCON1 4 register an individual chip select line CS1 CS4 is associated to save external glue logic for chip select generation If a CSx is enabled through System Startup Configuration see section 3 5 the signal will go low for any external access in the range defined through the respective address select register ADDRSELx It will go to a high level for any internal access or accesses outside the specified address range In order to support the extended address range of 16 MByte the possible address range selections in the Address Select Registers ADDRSEL1 4 are also extended The Range Size field now allows the selections shown in the following table This table also shows the reference between the range size and the range start address S7 SGS THOMSON 39 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL All sixteen bits of the ADDRSEL registers are now used for the specification of the address range for a BUSCON register Note that the relevant bits R define the a
130. ns of this control register are shown hereafter In order to modify the operation of several channels with one instruction e g bitfield instruction the control bits are organized into functional not channel respective groups This allows for example to start or stop all 4 timers simultaneously with one bitfield instruction 74 80 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL PWMCONO FF30h 98h PWM Module Control Register 0 Reset Value 0000h 15 14 13 12 11 10 9 8 PIR3 PIR2 PIR1 EN 2 PIE1 PIEO 7 6 5 4 3 2 1 0 PTI2 PTH PTIO PTR2 PTR1 PTRO b15 PIR3 PWM Channel 3 Individual Interrupt Request bit b14 PIR2 PWM Channel 2 Individual Interrupt Request bit b13 PIR1 PWM Channel 1 Individual Interrupt Request bit b12 PIRO PWM Channel 0 Individual Interrupt Request bit PIRO 0 No interrupt request PIRO 1 Interrupt pending b11 PIE3 PWM Channel 3 Individual Interrupt Enable bit b10 PIE2 PWM Channel 2 Individual Interrupt Enable bit b9 PIE1 PWM Channel 1 Individual Interrupt Enable bit b8 PIEO PWM Channel 0 Individual Interrupt Enable bit PIEO 0 Individual Interrupt disabled PIEO 1 Individual Interrupt enabled b7 PTI3 PWM Timer PT3 Input Clock Control bit b6 PTI2 PWM Timer PT2 Input Clock Control bit b5 PTI1 PWM Timer PT1 Input Clock Control bit b4 PTIO PWM Timer PTO Input Clock Control bit PTIO 0 PTO Input c
131. ntext of this paper This is done to distinguish it from the Read Write Chip Selects described in the next section The activation of an Address Chip Select is selected with CSWENx CSRENx 0 default after reset in the BUSCON registers Note that for CSO this is the only option the respective bits in BUSCONO are reserved When an access within the address range specified by the associated ADDRSEL register is performed the respective chip select line CSx 0 4 will go to a low level with the falling edge of ALE and remain at this level until an access outside of this range is made It will then be deactivated again with the falling edge of ALE of the bus cycle accessing the new range No spurious spikes will be generated on the chip select lines Figure 8 shows the timing of the address chip select signals 44 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Figure 8 Address Chip Select Operation MUX Bus Example ALE x N ADDRESS BUS VR001894 3 3 2 Read Write Chip Selects For accessing external devices such as latches or direction drivers which often only have one enable input another chip select option is implemented This option allows to internally gate the chip select signal derived from the addresses with the read or write signal This means for example that a write chip select signal will only be generated when writing to a specific address range not for
132. of register SSCCON since the previous state of SSCEN was 1 Since the flags are modified by hardware it is strongly recommended to avoid Read Modify Write instructions on register SSCCON while SSCEN 1 To disable the SSC for example to select a different data width use a MOV 55 0 instruction to clear the SSCEN bit Master or Slave Operation Other than the synchronous mode of the ASCO which can only operate as a master interface the SSC can operate either in master or in slave mode This operation is selected through the Master Select Bit SSCMS In the master mode SSCMS 1 the SSC of the C167 generates and outputs the clock at pin P3 13 SCLK and initiates data transfers All other devices connected to the serial bus must be in slave mode receiving the shift clock and only responding to transfers In the slave mode SSCMS 0 default after reset the shift clock is received through pin P3 13 SCLK The SSC can only respond to transfers initiated by another master connected to the serial bus it is not possible in this mode to initiate a data transfer The master slave modes are discussed in more detail in Chapter 7 4 96 180 ST SGS THOMSON Af ie aDELEETRONISS C167 FAMILY PRELIMINARY USER MANUAL Selecting Transfer Data Width and Shift Direction 55 in the 167 is not dedicated to certain data width for instance only byte or a word transfer Instead the data width can be programm
133. ogram into the internal RAM or external memory of the C167 via the serial port even if there is no internal or external program memory available The BTL is activated if at the end of a hardware reset pin POL 4 is sampled at a low level This mode is entered regardless of the state of the EA pin and of the bus type chip select and segment address configuration pins In this bootstrap loading mode the C167 now expects the reception of a zero byte 00h one start bit 8 data bits one stop bit from a host at pin RxDO P3 11 from which it calculates the necessary factor for the serial port baudrate generator taking into account the operating frequency of the CPU According to the calculated baudrate the serial port ASCO is initialized one start bit 8 data bits one stop bit no parity and an acknowledge byte OA5h is send back to the host After this the BTL goes into a receive loop expecting to receive 32 bytes from a host These bytes are stored sequentially into the internal RAM beginning at address 40 After the reception of the 32 bytes the BTL automatically performs a jump to location OFA40h and the loaded program is executed Normally for a program more than 32 bytes are required Thus to load larger routines the 32 byte program loaded via the BTL will in most cases be another receive loop now with user defined start and end addresses Since the serial port ASCO is already initialized to the correct mode and bau
134. ontrol 114 Standard and Extended SFR Spaces 28 Synchronous Serial Channel SSC Block Diagram 92 S7 SGS THOMSON 179 180 SYA MICROELECTRONICS SALES OFFICES NOTES Information furnished is believed to be accurate and reliable However SGS THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor forany infringement of patents or other rights of third parties which may results from its use No license is granted by implication or otherwise under any patent or patent rights of SGS THOMSON Microelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied SGS THOMSON Microelectronics products are not authorized for use as critical componentsin life support devices or systems without the express written approval of SGS THOMSON Microelectronics 01994 SGS THOMSON Microelectronics All Rights Reserved Purchase of Components by SGS THOMSON Microelectronics conveys a license under the Philips4C Patent Rights to use these components in an Fc system is granted provided that the system conforms to the FC Standard Specification as defined by Philips SGS THOMSON Microelectronics Group of Companies Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kin
135. or interrupt request flag SSCEIR will be set on such a condition If this error condition is enabled to generate interrupt request through setting bit SSCBEN during the initialization of the SSC an automatic reset of the SSC will occur in the case of this error This is done to reinitialize the SSC if too less or too many clock pulses have been detected 7 5 4 Transmit Error Slave Mode This error indicates that a transfer was initiated by the master but the transmit buffer SSCTB of the slave was not updated i e not written to with a new value If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transmission In the half duplex open drain serial configuration such an operation will lead to a corruption of the data on the transmit receive line if this slave is not selected for transmission This mode requires that slaves not selected for transmission shift out all ones thus their transmit buffers must be loaded with the value FFFFh depending on selected transfer data width prior to any transfer When using push pull output drivers the value shifted out of the shift register of a slave not selected for transmission will normally present no problem since the output is switched off in this case However in order to avoid possible conflicts or misinterpretations it is recommended to always load the sl
136. other BUSCON registers and into one SYSCON register which holds the bits to program the overall configuration of the system With this separation it is now possible for instance to have the ALE lengthening feature directly after reset and to have a clear and transparent way of programming the ROM mapping bus enable etc In the following sections the new registers are described Note This is an incompatibility with the ST10x166 3 2 1 SYSCON Register The new SYSCON register is dedicated to global system functions and is primarily only written once during the initialization routine The entire SYSCON register is locked out from being written after the first occurrence of the EINIT instruction This improves system security such that if software were to unintentionally execute a write access to this SFR after the execution of the EINIT instruction that it would be ignored S7 SGS THOMSON 33 180 SYA MISROELECTROMICS 167 FAMILY PRELIMINARY USER MANUAL The new SYSCON register hereafter will occupy the bit addressable address OFF12h In the following some important controls of the SYSCON register are described SYSCON FF12h 89h System Configuration Register Reset Value xxxxh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wee n m wm mj 015 014 613 STKSZ System Stack Size Selection b12 ROMS1 ROM Segment Mapping control bit ROMS1 0 internal ROM mapped to segment 0 ROMS 1 internal ROM map
137. ous data frame S7 SGS THOMSON 89 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 90 180 Sz SGS THOMSON Af ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 7 SYNCHRONOUS SERIAL CHANNEL SSC In addition to the asynchronous synchronous serial interface ASCO the C167 has a dedicated high speed Synchronous Serial Channel the SSC This interface provides the same synchronous mode as the ASCO and is also compatible to the popular SPI interface It can be used for simple expansion via shift registers for connection of a variety of peripheral components such as A D converters EEPROMs etc or for allowing several microcontrollers to be interconnected in a master slave or multimaster configuration It supports full duplex or half duplex operation and can run a master or a slave mode 7 1 SSC Block Diagram Figure 22 shows a rough block diagram of the SSC The central element of the SSC is a shift register which is configurable in length from 2 to 16 bits The input and the output of this shift register are each connected via a control logic to a pin P3 9 MTSR Master Transmit Slave Receive and P3 8 MRST Master Receive Slave Transmit This shift register can be written to through a Transmit Buffer Register SSCTB and can be read through a Receive Buffer Register SSCRB S7 SGS THOMSON 91 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 22 Synchronous Seri
138. pecial Function Registers this is an incompatibility with the ST10x166 28 180 S7 SGS THOMSON Af tierce tronics 167 FAMILY PRELIMINARY USER MANUAL 2 5 Internal Address Space In the C167 the entire address range 00F000h through OOFFFFh in segment 0 is mapped to internal addresses that means no external addresses will be generated within this range The right hand side of Figure 5 illustrates the different portions of this area Although the address space F200h through F5FFh is currently not used in the C167 it is reserved for future expansion and should not be used in an application An access to this area will result in a dummy access and no external addresses will be generated The data of a write access will be lost and a read returns no valid data As already described in Chapter 2 1 the lower 32 KByte of either segment 0 or 1 depending on ROM mapping will also be mapped to internal addresses if the ROM is enabled The left hand side of Figure 5 shows the internal address spaces within segment 0 Note This is an incompatibility with the ST10x166 S7 SGS THOMSON 29 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL Figure 5 Internal Address Space Segment 0 Internal ROM if enabled nd mapped o Segment SKS N 30 180 FFFFh Normal F000h SFR Space FEOOh 2 KByte Dual Port RAM FAOOh 8
139. ped to segment 1 b11 SGTIS Segmentation Disable bit SGTDIS 0 Segmentation enabled SGTDIS 1 Segmentation disabled This bit does not control the number of Part 4 pins used b10 ROMEN ROM Enable bit ROMEN 0 Internal ROM disabled all instruction and data accesses to the ROM space will be accessed externally ROMEN 1 Internal ROM enabled all instruction and data accesses to the ROM space will access the ROM FLASH 09 BYTDIS Byte High Enable BHE pin control bit BYTDIS 0 BHE enabled BYTDIS 1 BHE disabled pin can be used for normal I O b8 CLKEN System Clock Output CLKOUT Enable bit CLKEN 0 CLKOUT disabled can be used for normal I O CLKEN 1 CLKOUT enabled pin used for system clock output b7 WRCFG Write Configuration Control Bit WRCFG 0 Normal configuration of WR and BHE WRCFG 1 WR pin acts as WRL BHE pin acts as WRH to 00 R Reserved Stack Size Parameters The stack size selection is extended in the new SYSCON register from two to three bits due to the extended RAM space The following table shows the possible options for the stack 34 180 S7 SGS THOMSON Af e aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL SYSCON 15 13 Maximum System Address Range STKSZ Stack Size 256 Words FAOOh FBFFh 128 Words FBOOh FBFFh 64 Words FB80h FBFFh 32 Words FBCOh FBFFh 512 Words F800h FBFFh reserved reserved reserved reserved No
140. period register is reached With the next count pulse the timer is reset to 0000h and starts counting again with the next count pulses The PWM output signal is switched to high level when a match between the timer contents and the contents of the shadow register is detected The signal is switched back to a low level with the same signal that clears the timer to 0000h The period of the resulting PWM signal is the value of the register plus 1 counted in units of the timer resolution The duty cycle of the PWM output signal is controlled by the value in the pulse width register PWx respectively the value in the shadow register This is true also for duty cycles of 0 and 100 For a PWM value of 0000h the output will remain at a high level representing a duty cycle of 100 For a PWM value higher than the value in the period register the output will remain at a low level which corresponds to a duty cycle of 0 Note that in this mode the PWM value only affects the positive edge of the output signal The negative edge is always fixed and related to the clearing of the timer Therefore this mode is often referred to as Edge Aligned PWM Figure 14 illustrates the operation of a PWM channel in this mode and shows examples for different possible output waveforms The period of the resulting PWM signal is PWM PPx 1 Period Mode 0 Note that in this mode the distance from one negative signal edge to the next is always e
141. problems occur when using the PEC to write a byte to a port normal instructions could use AND OR or bitfield instructions to get around this problem Now with Port O split into two bytes byte write problems are solved Although this change is an incompatibility with the ST10x166 minor difficulties are expected since Port 0 in most cases is currently used as external data bus Note that when using an external 16 bit data bus the two halfs of PORTO are treated as one word wide bus The lines of PORTO are used by the External Bus Controller depending on the selected bus mode Figure 40 shows the configuration and alternate functions of PORTO in the different modes It must be noted that the general purpose function can only be used for pins POL O through POL 7 if no external bus and for pins 0 through POH 7 if only the 8 bit non multiplexed bus is used in an application While Figure 40 shows four single alternate function configurations of PORTO it must be taken into account that in an application mostly several external bus modes are used 142 180 S7 SGS THOMSON Aff miexottectaomes 167 FAMILY PRELIMINARY USER MANUAL Figure 40 PORTO I O Alternate Functions General Purpose Alternate Function VO a b 7 D15 A15 AD15 POH 6 D14 A14 AD14 5 D13 A13 AD13 POH POH 4 D12 A12 AD12 POH 3 D11 A11 AD11 POH 2 D10 A10 AD10 POH 1 D9 A9 AD9 0 D8 A8 AD8 PORT 0 POL
142. pter 10 1 2 of the ST10 User Manual 164 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL Figure 52 Block Diagram of a PORT8 Pin Write ODP8 y Open Drain Latch Read ODP8 y ODP8 y Write DP8 y Direction Latch DP8 y Read DP8 y S7 Port Output Latch Alternate P8 y Data Output Output P8 y CCzlO Buffer Write P8 y 1 Trigger u 5 Read P8 y Clock Input Latch S UE Alternate Latch Data Input y 0 7 Alternate Pin Data Input z 16 23 VROR1643 Symbols P8 y Input P8 y Push Pull Output P8 y Output THOMSON 165 180 NIGROELECTRORIGS 167 FAMILY PRELIMINARY USER MANUAL Figure 53 PORT8 I O and Alternate Functions General Purpose Alternate Function P8 7 CC23lO P8 6 2210 P8 5 211 8 4 201 P8 3 19 8 2 P8 1 CC171O P8 0 6 VR0A1923 166 180 S7 SGS THOMSON Af Ie aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL 12 DEDICATED PINS A number of pins of the C167 are dedicated to specific functions These pins are listed in the following Address Latch Enable External Memory Read Strobe WR WRL External Memory Write Write Low Strobe READY Ready Input EA External Access Enable NMI Non Maskable Interrupt Input RS
143. qual to the period of the signal also with changing duty cycles The distance of the center points of the high pulses however changes with changing duty cycles 64 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL Figure 14 PWM Mode 0 Operation and Output Waveforms Examples PPx Period 7 PTx Count Value Duty Cycle PWx Pulse 100 Width 0 A ee D M PWx 4 50 PWx 6 25 PWx 7 12 5 PWx 8 LSR LSR LSR Latch Shadow Register VR001900 Interrupt Request S7 SGS THOMSON 65 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Mode 1 Symmetrical PWM Generation Center Aligned PWM This mode is mainly intended to be used in electrical motor control applications The main characteristic of this mode is that when the PWM value is changed both edges of the output signal will be affected This is achieved by the following operation The PWM timer is counting up from 0000h until the value in the period register is reached With the next count pulse the count direction is switched to count down the timer contents however will not be changed until the next count pulse which decrements the timer The timer continues counting down until it reaches 0000h again The next count pulse will change the count direction again to count up but will not change the timer
144. quired For any long or indirect address in the EXTPR aed sequence the 10 bit page number address bits A is determined by the contents of DPP register bar by 14h value of op1 itself The 14 bit page offset address bits A is derived from the long or indirect address as usual Depending on the value of op2 the period of validity of the EXTPR instruction extends over the sequence of the next 1 to 4 instructions being executed after the EXTPR instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the EXTPR instruction yy 55 S v NIGHOELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTPR begin EXTended Page and Register sequence NOTE A lot of care must be taken over the use of the EXTPR instruction with other system control or branch instructions One must also be very careful when a class B trap condition becomes present before the EXTPR instruction sequence is completed In such a case the EXTPR instruction ceases its validity the interrupt locking is removed and the class B trap is executed An EXTPR instruction sequence can normally not be continued properly if it was interrupted FLAGS Z V C N Not affected Not affected Not affected Not affected Not affected 2 lt INSTRUCTION FORMAT Mnemonic Operands Format Bytes EXTPR Rwm data2 DC 11
145. r Disabled SOCON Register 08011 SYSCON Register 00E00h P3 10 TxD DP3 10 1 Context Pointer CP OFAOOh Stack Pointer SP OFA40h BUSCONO according to selected system STKUN Register OFA40h startup configuration STKOV Register OFAOCh S7 SGS THOMSON 59 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 60 180 Sz SGS THOMSON Af DELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL 4 PWM MODULE In the C167 a 4 channel Pulse Width Modulation PWM Module is implemented The PWM module allows the user to generate PWM signals with a frequency range of up to 78 KHz at 8 bit resolution down to 4 8 Hz with 16 bit resolution see Table 4 1 2 In the following the functions and operation of one PWM channel is explained the description refers for the other channels too if not noted otherwise S7 SGS THOMSON 61 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 4 4 PWM Channel The Pulse Width Modulation Module consists of a block of 4 independant channels Each channel has 16 bit up down counter 16 bit period register PPx 16 bit pulse width register PWx with a shadow latch two comparators and the necessary control logic The operation of all four channels is controlled by two common control registers PWMCONO PWMCON1 and the interrupt control and status is handled by one interrupt control register PWMIC which is also common for all channels Fig
146. r analog reference voltage 38 A D converter analog reference ground C167 FAMILY PRELIMINARY USER MANUAL Port 3 is 16 bit bidirectional I O port It is bit wise programmable for input or output via a direction bit and the output drivers can be switched into push pull or open drain operation For a pin configured as input the output driver is put into high impedance state The pins of Port 3 are also used for various functions as timer inputs and outputs and bus control signals P3 0 TOIN CAPCOM Timer TO Count Input P3 1 T6OUT GPT2 Timer T6 Toggle Latch Output P3 2 CAPIN GPT2 Register CAPREL Capture Input P3 3 T3OUT GPT1 Timer T3 Toggle Latch Output P3 4 T3EUD GPT1 Timer T3 External Up Down Control Input P3 5 T4IN GPT1 Timer T4 Count Capture Reload Input P3 6 T3IN GPT1 Timer T3 Count Input P3 7 T2IN GPT1 Timer T2 Count Capture Reload Input P3 8 MRST SSC Master Receive Slave Transmit In Out P3 9 MTSR SSC Master Transmit Slave Receive Out In P3 10 TxDO ASCO Data Output Clock Output Async Sync P3 11 RxDO ASCO Data Input Async Data Input Output Sync P3 12 BHE External Memory High Byte Enable Signal WRH External Memory High Byte Write Strobe P3 13 SCLK SSC Master Clock Output Slave Clock Input P3 15 CLKOUT System Clock Output CPU Clock Port 4 is a 8 bit bidirectional I O port It is bitwise programmable for input or output via a direction bit For a pin configured as input the output driver is put into high impedanc
147. rity If the data contains an even number 01715 then the parity bit 1 If the data contains an odd number of 1s then the parity bit 0 SOCON FFBOh D8h Serial Channel Control Register Reset Value 0000h 015 SOR Baud Rate Generator Run bit SOR 0 Baud rate generator disabled SOR 1 Baud rate generator enabled 014 SOLB Loop Back Mode Enable bit SOLB 0 Loop back mode disabled SOLB 1 Loop back mode enabled 013 SOBRS Baud Rate Selection bit SOBRS 0 Baud rate factor is 1 SOBRS 1 Baud rate factor is 2 3 b12 SOODD Even Odd Parity Selection S7 SGS THOMSON 87 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL SOODD 0 Even parity If the data contains an even number of 1 then parity bit 0 SOODD 1 Odd parity If the data contains an even number of 1 then parity bit 1 b11 R Reserved b10 SOOE Overrun Error Flag Set by hardware when an overrun error occurs and SOOEN 1 Must be reset by software b9 SOFE Framing Error Flag Set by hardware when a framing error occurs and SOFEN 1 Must be reset by software b8 SOPE Parity Error Flag Set by hardware when a parity error occurs and SOPEN 1 Must be reset by software b7 SOOEN Overrun Check Enable bit SOOEN 0 Overrun check disabled SOOEN 1 Overrun check enabled b6 SOFEN Framing Check Enable bit SOFEN 0 Framing check disabled SOFEN 1 Framing chec
148. rnal Address Space Segment 0 30 LSB First MSB First Operation Examples 98 On Chip RAM Address Map 25 On chip ROM Address Range Mapping Option and Expandability 24 PORTO Alternate Functions 143 PORT I O and Alternate Functions 146 PORT I O and Alternate Functions 148 PORTS and Alternate Functions 150 PORTA I O and Alternate Functions 152 178 180 S7 SGS THOMSON Af ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL PORT5 Input and Alternate Functions 153 PORT6 I O Alternate Functions 158 PORT7 and Alternate Functions 162 PORTS and Alternate Functions 166 Push Pull and Open Drain Output Drivers Port Pin Symbols 140 PWM Channel Block Diagram 62 PWM Mode 0 Operation and Output Waveforms Examples 65 PWM Mode 1 Operation and Output Waveforms Examples 67 PWM Pulse Burst Mode Operation Example 68 PWM Single Shot Mode Operation amp Output Waveforms Examples 70 Read Write Chip Select Examples 46 Read Write Chip Select Operation MUX Bus Example 46 Serial Clock Phase and Polarity Options 99 SFRs and Port Pins Associated with the A D Converter 118 SFRs and Port Pins Associated with the CAPCOM2 Unit 82 SFRs and Port Pins Associated with the I O Ports 138 SFRs and Port Pins Associated with the PWM Unit 72 SFRs and Port Pins Associated with the Synchronous Serial Channe 94 SSC Alternate Input Output Port Structures 103 SSC Error Interrupt C
149. rror Interrupt Control Reset Value 0000h b7 SSCEIR SSC Error Interrupt Request b6 SSCEIE SSC Error Interrupt Enable b5 to b2 ILVL Interrupt Priority Level b1 b0 GLVL Group Priority 102 180 S7 SGS THOMSON Af GLVL 167 FAMILY PRELIMINARY USER MANUAL 7 3 5 Port Control Registers The SSC uses three pins of port P3 to operate with the external world Pin P3 13 SCLK serves as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines Figure 26 shows the configuration of the port structure for these pins Figure 26 SSC Alternate Input Output Port Structures 3 i SGS THOMSON 103 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL The operation of these pins depend on the selected master or slave mode see tables In order to enable the alternate output functions of these pins instead of the general purpose I O operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output function lines are ANDed When the alternate data output line is not used it is held at a high level allowing 1 operations via the port latch The direction of the port lines is depending on the master or slave operation The SSC will automatically use the correct alternate input or output line of the po
150. rts when switching the modes however the direction of the pins must be programmed by the user as shown in the tables Master Mode P3 13 SCLK Serial Clock Output DP3 13 1 P3 9 MTSR Serial Data Output DP3 9 1 P3 8 MRST Serial Data Input DP3 8 0 Slave Mode P3 13 SCLK Serial Clock Input P3 9 MTSR Serial Data Input P3 8 MRST Serial Data Output In the tables above an means the actual value is irrelevant however it is recommended to set these bits to 1 such that they are already in the correct state when switching between master slave mode The tables above show the programming of the direction of the pins when using normal push pull operation In the C167 however port P3 has the feature of being switched to an open drain output mode see Chapter 11 This is controlled by the respective Open Drain Control Register ODP3 and can individually be selected for each line of port For the SSC the control bits ODP3 13 ODP3 9 and ODP3 8 are relevant This feature can perfectly be used in a serial communication system with the SSC It helps to avoid bus contention problems and reduces the need for hardwired hand shaking or slave select lines When using the open drain feature it is not always necessary to switch the direction of the port pin The application of the open drain feature is explained in detail in Chapter 7 4 104 180 S7 SGS THOMSON Af e sDELEETRONISS 167 FAMILY PRELIMINARY USER MANUAL
151. s lines of 256 KByte as in the ST10x166 Number of Segment Address Lines 2 Bit Segment Address A17 A16 Default 8 Bit Segment Address A23 A16 No Segment Address 4 Bit Segment Address A19 A16 When the reset sequence has been finished the port P4 lines selected for segment address output will automatically be switched to the segment address output operation The remaining pins of port P4 can be used for general purpose S7 SGS THOMSON 55 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Note As mentioned before the selection for the segment address lines only determines the number of external physical address lines used in a system Internally however all 24 bits of addressing capability is used if segmentation is enabled This is true also for the generation of the chip select signals according to the address ranges defined through the ADDRSEL registers Thus the chip select lines can be used to address up to five blocks of for example 256 KByte with 18 physical address lines for the offset address within such a block Adapt Mode If at the end of a reset sequence the state of pin POL 1 is sampled as 0 the C167 will go into a special Adapt mode regardless of the state of the other PORTO pins The part will remain in this mode even after the reset sequence has been terminated This mode is similar to the reset mode with the exception of RSTOUT and XTAL1 XTAL2 This mode can be used for
152. ssociated upper address bits of the selected address range they are associated with address lines A23 A12 One can see that the upper 8 bits of the ADDRSEL1 4 registers directly relate to the respective code segment A23 A16 The bits marked with x are don t care bits Relevant R bits of Range Start Address RGSAD Range Size Selected Address RGSZ Range 4 KByte RRRRRRRRRRRR 8 KByte RRRRRRRRRRR x 16 KByte RRRRRRRRRR xx 32 KByte RRRRRRRRR xxx 64 KByte RRRRRRRR xxxx 128 KByte RRRRRRR xxxxx 256 KByte RRRRRR xxxxxx 512 KByte RRRRR 1 MByte RRRR 2 MByte RRRXXxxxxxxx 4 MByte RR 8 MByte R reserved Note In order to allow sections of 4 and 8 KByte and to implement a more general scheme the ADDRSEL register organization has been rearranged compared to the ST10x166 The smallest section will be 4 KByte instead of 2 KByte in the ST10x166 the Range Size field is now 4 bits and the Start Address field is now 12 bits Although this leads to incompatibility with existing programs the advantages justify this change Note This is an incompatibility with the ST10x166 Hereabove is the bus configuration register BUSCON1 while the associated address range select register ADDRSEL1 is shown herafter 40 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL ADDRSEL1 FE18h 0Ch Address Select Register 1
153. t 3 Y Overrun Error Interrupt Request Auto Scan Continuous Mode with Wait for Read Operation ADWR 1 Conversion Write ADDAT X 3 2 1 0 3 Temp Latch Full Hold Result in Generate Temp Latch Interrupt Request Read of ADDAT PEE NEU DNA UNE Result of Channel VR001912 S7 SGS THOMSON 121 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 8 3 Channel Injection Mode In many applications it is necessary to convert a specific analog channel in response to a time event or another signal while the ADC is running in a continuous or auto scan mode After the conversion of this specific channel the original operating mode of the ADC should continue For this purpose a Channel Injection mode is implemented in the ADC module This mode allows to interrupt the current conversion mode to inject the conversion of a specific channel and to then continue the interrupted operating mode where it was left off The Channel Injection mode is selected with bit ADCIN Channel Injection Enable bit ADCON 10 and with bit ADWR 1 Wait for Read mode The channel to be converted in this mode is specified through the upper 4 bits of a second result register ADDAT2 The event to trigger the channel injection can either be a compare or capture event of the Capture Compare register CC31 of the 2 Unit or a setting of bit ADCRQ by software When such an event occurs the Channel In
154. t signals can be generated automatically to select several different address ranges For example the segment address lines may be limited to four lines giving direct addressing capability of up to 1 MByte but the chip select signals can be used to enable several blocks or memory devices of 1 MByte giving a total address range of for instance 5 MByte Figure 6 shows such a configuration example S7 SGS THOMSON 31 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Figure 6 Address Range Configuration Example Example Using 20 Address Lines and 5 Chip Selects to Access a Range of 5 MByte EP i meye cso Device 1 3 1 MByte Device 2 yo D15 DO Data Bus A19 A16 1 MByte Device 3 4 7 4 4 5 0 Address Bus 1 MByte CS3 Device 4 ST10167 EEK CS4 Device 5 P4 3 P4 0 PORT 1 VROD1646 The total address space is divided into code segments and data pages Each code segment has an address range of 64 KByte thus there exist 256 code segments The currently active code segment is specified by the Code Segment Pointer CSP which is modified only through any JMPS Jump Segment or CALLS Call Segment instruction The CSP is also extended to 8 bits which represent address bits A23 A16 32 180 SGS THOMSON Ie aDELEETRONISS 167 FAMILY PRELIMINARY USER MANUA
155. t with Schmitt Trigger characteristics A low level at this pin for a specified duration while the oscillator is running resets the C167 An internal pullup resistor permits power on reset using only a capacitor connected to Vas RSTOUT Internal Reset Indication Output This pin is set to a low level when the part is executing eiter a hardware a software or a watchdog timer reset RSTOUT remains low until the EINIT end of initialization instruction is executed Non Maskable Interrupt Input A high to low transition at this pin causes the CPU to vector the NMI trap routine When the PWRDN power down instruction is executed the NMI pin must be low in order to force the C167 to go into power down mode If NMI is high when PWRDN is executed the part will continue to run in normal mode Address Latch Enable Output Can be used for latching the address into external memory or an address latch in the multiplexed bus modes 95 External Memory Read Strobe RD is activated for every external instruction or data read access WR WRL External Memory Write Strobe This pin has two modes of operation selected through WRCFG in register SYSCON In the WR mode this pin is activated for every external data write access In the WRL mode this pin is activated for every low byte write access for 16 bit data busses and for every byte write access for 8 bit busses In this mode this pin is used together with pin BHE WRH which indicates ev
156. ted conversion is written to the ADDAT2 register d If the converter was idle before the channel injection and during the injected conversion the converter is started by software for normal conversions the channel injection is aborted and the converter starts in the selected mode It is recommended therefore to always check the busy bit ADBSY before starting a new operation 126 180 S7 SGS THOMSON Af C167 FAMILY PRELIMINARY USER MANUAL 9 GPT1 AND GPT2 ENHANCEMENTS To improve the flexibility and programmability of the general purpose timers a number of additional input lines and control bits are provided in the C167 With this enhancement all of the five timers in the GPT1 and GPT2 blocks can run either in timer and counter mode and have the option to be controlled for up down counting through an external signal For the GPT1 timers two additional input lines now allow the two auxiliary timers T2 and T4 to be also externally controlled for up or down counting as it was already implemented for the core timer T3 For the two timers T5 and T6 in the GPT2 block also the option to externally control them for up or down counting is provided through two additional input lines For counting external events two more inputs have been added thus that both T5 and T6 can now be used as counters In total six additional input signals are implemented GPT1 Timer 2 External Up Down Control Input GPT1 Ti
157. teet ital 4 1 3 Interrupt Request 76 4 1 4 ANM Output Signals ee rore n 78 Second Capture Compare Unit 2 79 6 Asynchronous Synchronous Serial 87 b T Even Odd Party Selectlart soie eid tei notet se eds 87 6 2 Double Buffered TransmiL oder peer nere ee tu e pesi 88 Synchronous Serial Channel SSC eene 91 7 1 SSC Block Diagram soo t hoe tb o ad e dC dide 91 7 2 General Operation of the 55 00 93 7 3 SSC Control Status and Data 94 S7 SGS THOMSON 3 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL 7 3 1 SSC Control Register 94 7 3 2 Buffer Registers SSCTB and SSCRB 100 7 3 8 Baud Rate Register 5 100 7 3 4 Interrupt Control Registers 101 7 3 5 Port Control Registers oie datteren 103 7 4 Detailled Operation of the 55 0 105 7 4 1 Single Master Full Duplex 10
158. ter SSCEIC This interrupt request however will only be generated when an error condition occurs and the respective error enable bit was set during the initialization of the SSC Figure 33 shows a functional diagram of the error interrupt generation In the error interrupt service routine the error indication flags in register SSCCON can be polled to determine which type of error had occurred While the general error interrupt request flag SSCEIR is automatically cleared by hardware when the interrupt is serviced the error indication flags SSCxE must be cleared by software otherwise further interrupt requests may be generated after the return from the service routine In this way it is possible to program one or more error conditions to generate an error interrupt while checking the remaining error conditions through software polling techniques Note that if enabled through the respective enable bit SSCxEN the setting of an error indication flag SSCxE by software will also cause the error interrupt request flag SSCEIR to be set This can be used for testing the respective error service routine without having to specifically produce the error condition S7 SGS THOMSON 119 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL Figure 33 SSC Error Interrupt Control Register SSCCON Register SSCEIR SSCTEN Transmit s Error SSCTE L3 SSCREN l amp Receive SSCRE Error F SSCPEN Phase SSCPE Error SSCBEN Baudrate SSCBE
159. ternate timer inputs Note that Port 5 is also used for the analog input signals for the A D Converter The following table shows the reference between the upper six Port 5 pins and their alternate funtions Alternate Alternate Function I Function T2EUD T4EUD TSIN T6IN TSEUD T6EUD S7 SGS THOMSON 131 180 SYA MICROELECTRONICS C167 FAMILY PRELIMINARY USER MANUAL 132 180 S7 SGS THOMSON Af e DELERTRONISS 167 FAMILY PRELIMINARY USER MANUAL 10 INTERRUPT SYSTEM In the C167 a total of 56 interrupt sources and vectors is implemented This is 24 interrupts more than in the ST10x166 10 1 External Interrupts As in the ST10x166 the C167 will have no dedicated external interrupt inputs Instead each peripheral s external input which can generate an interrupt request such as the capture inputs of the CAPCOM units can be used as an external interrupt input The sample time of the external input however is always tied to the cycle time of the associated peripheral device That means for instance that the capture inputs of the CAPCOM units are sampled every 400 ns 20 MHz CPU clock thus external interrupt signals can only be detected in that time frame In order to provide faster interrupt detection the C167 will provide the option to use 8 pins of Port 2 for fast external interrupts If this feature is enabled the pins P2 8 through P2 15 function as external interrupt inpu
160. th other system control or branch instructions One must also be very careful when a class B trap condition becomes present before the ATOMIC instruction sequence is completed In such a case the ATOMIC instruction ceases its validity the interrupt locking is removed and the class B trap is executed An ATOMIC instruction sequence can normally not be continued properly if it was interrupted SGS THOMSON SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL ATOMIC begin ATOMIC sequence FLAGS E 7 V C N Not affected Not affected Not affected Not affected Not affected ZOs NI INSTRUCTION FORMAT Mnemonic Operands Format Bytes ATOMIC data2 D1 00 0 2 S7 SGS THOMSON 11 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL EXTR begin EXTended Register sequence EXTR OPERATION 12 180 1 count lt 1 1 lt lt 4 Disable Interrupts Class Traps SFR range Extended DO WHILE count 0 AND Class B Trap Condition TRUE next instruction count lt count 1 END WHILE count 0 SFR range Standard Enable Interrupts and Traps Causes all SFR or SFR bit accesses via the bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class hardware traps are locked The EXTR instruction becomes immediately active suc
161. ting of bit ADCRQ by software The second is a compare event of capture compare channel CC31 This method allows to trigger a channel injection at a specific time or on the occurence of a predefined count value of the CAPCOM timers The third option is a capture event of register CC31 This can be either the positive negative or both the positive and the negative edge of an external signal In addition this option allows to record the time of occurrence of this signal Optionally the capture or compare event can generate an interrupt request see also Chapter 5 CAPCOMA2 Unit Note The channel injection request bit ADCRQ will be set through any interrupt request of CAPCOM2 channel CC31 regardless whether the channel injection mode is enabled or not It is recommended to always clear bit ADCRQ before enabling the channel injection mode Figure 36 A D Converter Channel Injection Example Conversion Write ADDAT X 1 X 2 X 3 X4 ADDAT Full Read ADDAT X41 xe X 3 tx Injected Channel Injection PN Request by CC31 Y Write ADDAT2 of Channel Y Int Request ADEINT Read ADDAT2 VROA1913 123 180 yy S65 MISROELECTRORICS 167 FAMILY PRELIMINARY USER MANUAL Figure 37 A D Converter Channel Injection Wait for Read Examples Conversion A o Channel x read Write ADDAT X 1 X X4 j 9 X 2 X 3 ADDAT Full X Read ADDAT PE tx X 1 X 2
162. tinuous Mode Second Capture Compare Unit with 16 Channels Serial Interfaces One Synchronous Asynchronous Serial Interface ASCO with Even Odd Parity Selection One Synchronous Serial Interface SSC with Master Slave Option Pulse Width Modulation PWM Unit with 4 Independent Channels Up to 78 KHz Frequency with 8 Bit Resolution Four Modes of Operation Standard Symetrical Burst Mode Single Shot Extended Interrupt System 8 Fast External Interrupt Inputs 50 ns Sample Rate 24 Additional Interrupt Sources and Vectors On Chip Bootstrap Loader 144 Pin MQFP Package S7 SGS THOMSON 5 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL In this document only these add on features and differences of the C167 compared to the ST10x166 are described For more detailled information about features and functions of the ST10 family please refer to the ST10 User Manual Figure 1 Block diagram of the major units of the ST10167 CPU ROM RAM CORE OSC Interrupt Controller PEC WDT 2 ADC PWM GPT1 P8 BUS CTL 1 1 5 55 2 7 VR001925 6 180 Sz SGS THOMSON Af ie aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL 1 INSTRUCTION SET The instruction set of the C167 is enhanced by a number of instructions which can greatly reduce the code size generated by C Compilers and which ena
163. tion of the EINIT instruction the default values in the SYSCON register can be changed through software One has to take care however that bits ROMEN and ROMS should never be changed when executing out of the on chip ROM otherwise unexpected results may occur Note The Write Configuration WRCFG control is explained in detail in section 3 4 3 2 2 BUSCONO Register As mentioned above the bus related control bits of the ST10x166 SYSCON register are moved to a new BUSCONO register in the C167 This register is shown hereafter This change allows to organize the BUSCONO register in the same way as any other BUSCON register giving the same functionality and a consistent way of programming BUSCONO FFOCh 86h Bus Configuration Register 0 Reset Values 0000h 0600h 0640h 0680h 06COh 15 14 13 12 11 10 9 8 Ce o on mme a men mms 7 6 5 4 3 2 1 0 BTYP MTTCO RWDCO MCTC 36 180 ST SGS THOMSON aDELEETRONISE 167 FAMILY PRELIMINARY USER MANUAL b15 b14 0 b13 Reserved 012 RDYENO READY Input Enable control bit RDYENO 0 READY function disabled for BUSCONO accesses RDYENO 1 READY function enabled for BUSCONO accesses b11 R Reserved b10 BUSACTO Bus Active control bit b9 ALECTLO ALE Lengthening control bit b8 Reserved b6 b7 BTYP External Bus Configuration Control b5 MTTCO Memory Tri state Time Control 04 RWDCO Read Write Delay Control
164. transferred to the shadow latch for being compared to the timer contents and that register PWx is now empty to receive the next value The module interrupt for all four channels is controlled by the PWM Module Interrupt Control register PWMIC This register is organized like any other standard interrupt control register shown hereafter If the module interrupt enable bit PWMIE is set then the interrupt request flag PWMIR is set if any of the channel interrupt request flags PIRx is set provided this interrupt is enabled through the respective PIEx bit Software is used to then poll the channel interrupt request flags to determine which channel s caused the interrupt PWMIC F17Eh BFh PWM Module Interrupt Control Register Reset Value 0000h 7 6 5 4 3 2 1 0 PWMIR PWMIE ILVL GLVL b7 PWMIR PWM Module Interrupt Request Flag PWMIR 0 No interrupt request PWMIR 1 Interrupt request b6 PWMIE PWM Module Interrupt Enable control bit PWMIE 0 Interrupt disabled PWMIE 1 Interrupt enabled b5 to b2 ILVL PWM Module Interrupt Priority Level ILVL Fh Highest priority level ILVL 0 Lowest priority level b1 b0 GLVL PWM Module Interrupt Group Priority GLVL 3 Highest group priority GLVL 0 Lowest group priority Note that the channel interrupt request flags in register PWMCONO will not be automatically cleared by hardware when the interrupt service routine is vectored to they must be cleared by software
165. trol bit 01 0 Normal operation of channels 0 an 1 01 1 Outputs of channels 0 and 1 are ANDed onto POUTO b11 to b8 R Reserved b7 PM3 PWM Channel 3 Mode Control bit b6 PM2 PWM Channel 2 Mode Control bit b5 PM1 PWM Channel 1 Mode Control bit b4 PWM Channel 0 Mode Control bit PMO 0 Mode operation PMO 1 Mode 1 operation PEN3 PWM Channel 3 Output Enable control bit b2 PEN2 PWM Channel 2 Output Enable control bit b1 PEN1 PWM Channel 1 Output Enable control bit 00 PENO PWM Channel 0 Output Enable control bit PENO 0 Output POUTO disabled PENO 1 Output POUTO enabled 4 1 3 Interrupt Request Generation Each of the four channels of the PWM Module can generate an interrupt request furthermore referred to as channel interrupt however only one interrupt vector is assigned to all four channels furthermore referred to as module interrupt To distinguish between the channel interrupts register PWMCONO has individual interrupt enable and interrupt request flags for each channel When the individual enable flag PIEx of a channel is set then the interrupt request flag PIRx of that 76 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL channel is set with the same signal that loads the shadow register with the value from register PWx see signal LSR in Figures 4 1 2 4 1 3 This indicates that the newest PWM value was
166. ts with a sample rate of 50 ns 20 MHz CPU clock This option is selected via register EXICON External Interrupt Control register shown hereafter For each interrupt input two control bits are used to enable the interrupt input and to select whether an interrupt is requested on the positive the negative or both the positive and the negative edge of the external signal These interrupts use the interrupt nodes from the capture compare registers through CC15 of the CAPCOM unit and are controlled by registers CC8IC through Note that the capture and compare functions of the eight Port 2 pins not be used when the fast external interrupts are selected lt gt 007 however the pin can be used for general purpose in any case The following table shows the possible options for the external interrupt inputs x 0 7 y x 8 EXIxES Selected Function Fast Ext Interrupt disabled Pin can be used for capture compare functions Interrupt on positive edge at pin P2 y Interrupt on negative edge at pin P2 y Interrupt on positive and negative edge at Note that the sampling of the external fast interrupt inputs is done every 50 ns 20 MHz CPU Clock the interrupt request arbitration and processing however is done in steps of 200 ns SGS THOMSON 133 180 SYA MIERGELESTAORIES 167 FAMILY PRELIMINARY USER MANUAL EXICON F1COh EOh External Interrupt Control Register Reset Value 000
167. ual bit wise selection of the open drain outputs for each port line If the respective control bits ODPx y is 0 default after reset the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space Besides being used as general purpose ports each port line has one or more associated alternate function which serves as an input or output for the bus controller and or the on chip peripheral components These alternate functions are also described in the following sections To ease the description of a port pin s configuration in an application new symbols have been introduced in this Preliminary User Manual These symbols are shown in Figure 39 Instead of showing only the pin symbol when illustrating an alternate input or output function an extra block is added to indicate that the entire port structure with port latch direction control and optional open drain control has to be considered when initializing and programming the port line In this extra block besides the pin name the appropriate configuration of the port line is shown through arrows The arrows indicate the direction of the port line with an output double arrow symbolizing a push pull output and an output single arrow symbolizing an open drain output and a single input arrow representing an input SGS THOMSON 139 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY
168. ure 13 PWM Channel Block Diagram PPx Period Register Clock 1 Input PTx Up Down Clock 2 Q 16 Bit Up Down Clear Control Run Counter Control Match Comparator _ P POUTx H Control Enable Shadow Register wale Control PWx Pulse Width Reg User Read amp Writeable VR001899 Note For the following descriptions it is important to notice that the comparison of the timer contents and the PWM value is performed through a greater than or equal to comparison PWM Output Signal PTx gt PWx 62 180 S7 SGS THOMSON Af 167 FAMILY PRELIMINARY USER MANUAL 4 1 1 Operating Modes Four different operating modes are available described in the following sections Note In these sections the description and the associated figures state that the respective PWM output pins POUTx are set on a match and reset on timer overflow etc This is the default operation after reset However since the PWM output signals are EXORed with the outputs of the respective port output latches it is possible to invert the PWM output signals by writing 1 to the associated port output latch Please refer also to Chapter 11 7 Port 7 S7 SGS THOMSON 63 180 SYA MICROELECTRONICS 167 FAMILY PRELIMINARY USER MANUAL Mode 0 Standard PWM Generation Edge Aligned PWM In this mode the PWM timer PTx is always counting up until the value in the

FAMILY PRELIMINARY USER MANUAL (ST10 FAMILY)

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