User Manual
Contents
1. 3 1 1 H W Environment In the ATLAS and ALICE experiments the RF2TTC is controlled by a VMEbus SBC from Concurrent Technologies either a VP110 or a VP315 CMS uses a PCI VMEbus link from CAEN and LHCb a USB VMEbus link from the same manufacturer In all four experiments the crate that houses the RF2TTC should be VME64X compatible as otherwise it is not possible use geographical addressing 3 1 2 S W Environment On the low end ATLAS and ALICE will use the vme rcc driver developed by ATLAS to communicate with the RF2TTC CMS and LHCb will use S W packages provided by CAEN for the respective interface The common S W will be programmed in a way that it is compatible with any of these bus access packages At the top end each experiment has to develop appropriate secondary libraries and applications to interface the RF2TTC to their respective control systems The development of the interface to the DIP server is also up to the experiments TEST PROGRAMS Currently there exists one program that comes in three flavours rf2ttcscope_atlice for ATLAS and ALICE rf2ttsscope_cms and rf2ttcscope_lhcb This interactive application can be used to read decode and write any register of the RF2TTC in a hopefully intuitive way If a users feels that some functionality is lacking he is welcome to contact the developer M Joos It is e g possible to extend rf2ttcscope by additional command line parameters such that certain tests can be executed2. IPH ESS Document No 4 of 25 PH ESS 29 01 2007 A global multiplexer allows selection between the three Bunch Clocks and the internal clock to generate a fourth Bunch Clock output called Main BC which can also be delayed The two orbit signals middle and bottom right parts of the diagram are first converted using the same adjustable comparator stage as for the Bunch Clocks They are then lengthened to more than 25ns finely delayed with 0 5ns steps before going into an FPGA grey block of the diagram where they are synchronized to their corresponding clock multiplexed with an internal orbit and coarse delayed Their length and polarity can be adjusted and they are then again finely delayed before being transmitted by the ECL drivers A global multiplexer also allows selection between the two orbits and an internal one synchronized to the Main Bunch Clock This orbit signal is called Main Orbit and can as well be finely delayed before being transmitted The BST Beam Synchronous Timing optical signal on the bottom left part of the diagram is received decoded and analyzed to recover the machine mode This mode is useful to know when the timing signals are stable and can be used In deed neither the Bunch Clocks nor the Orbit signals are fully guaranteed out of the physics modes flat top of the LHC energy curve It is thus advised to use internal signals when the machine mode indicates that there is no beam All t
3. Description A reset is triggered by writing a 1 to the address of the respective register The 3 bits of the counter_reset register can reset the counters of ORB1 ORB2 and or ORBmain by writing various patterns Bit number Related orbit Bit Counter mode value te a eee ee a IPH ESS Document No Page 19 of 25 PH ESS 29 01 2007 DELAY25_REG TTCrx_REG DELAY25_ REG 0xD200 TTCrx_REG 0xE200 Description These registers are required to read values from the TTC and Delay25 registers described below Due to delays introduced by the I2C bus it is not possible to read these registers directly Instead a sequence of three steps is required 1 Read a dummy data word from the address of the TTC or Delay25 register that is to be read out 2 Wait for at least 2 ms 3 Read the data value from the DELAY25_REG or TTCrx_REG FIFO contents of the read access to delay25 and TTCrx chips If multiple registers are to be read one can group the dummy reads step 1 and data reads step 3 such that they are only separated by one 2 ms delay This pipelining however works for up to 256 read requests BC_ DELAY25_x Name Offset Used Access BC DELAY25 GCR 0xD014 R W BC_DELAY25_BCmain 0xD00c BC_DELAY25 BCref 0xD008 BC_DELAY25 BC2 0xD004 BC_DELAY25 BC1 0xD000 Description These registers control the configuration of the Delay25 chips for the BC signal
4. and with the geographical address if the manual address 0x00 So until the BAR value is not changed the board address is the geographical address of the module if the manual rotary switches are set to 0x00 If the BAR is changed the board address is the content of the BAR see below The address used to access the CR CRS space is hence defined as follows BAR content value BAR 7 4 BAR 3 Comments SW 7 0 0x00 GEOG ADD After a sysreset SW 7 0 0x00 SW1 0 SW2 0 After a sysreset SW2 4 1 VmeData 7 4 VmeData 3 If BAR is written via a VME access with 0x2F AM CR CSR space address A23 A20 A19 A18 A1 BAR 7 4 BAR 3 _ Register offset in the CR CSR space IPH ESS Document No Page 6 of 25 PH ESS 29 01 2007 2 2 1 CSR Space The registers available on CR CSR space are some of the registers defined on the VME64 specification You can find them in the following table Register Offset Purpose Access UBSET User defined BSET Register assignment Description This register is declared in the VME64x as a User defined Bset register It is used here to define partial reset functions QPLL only Delay25 chips only TTCrx only The bit definition is as follows Bit Value Write Read 1 place Delay25 chips in reset Delay25 chips in reset mode mode no effect Delay25 chips not in reset mode place QPLL chips in reset mode QPLL ch
5. from scripts A tcltk graphical user interface rf2ttc tcl is also available for test purpose It has been written for SBCs from Concurrent Technologies VP110 and VP315 THE USER LIBRARY This library consists of a common source file that implements the access to the registers of the RF2TTC in a generic way and a number of files to implement glue layers to the VMEbus access libraries from ATLAS and CAEN respectively
6. 7C 32 bits Description This register controls the operation of the RF2TTC in automatic mode Each bit controls one machine mode A bit that is set to 0 causes the RF2TTC to use the NOBEAM_ SELECT registers for BC and orbit to be active when the machine is in the mode that corresponds to that bit If a bit is set to 1 the RF2TTC applies the settings in the BC and orbit BEAM SELECT registers for as long as the machine is in the respective mode Bit MODE Description Default Name No Beam 0 NOBEAM mode Filling l BEAMMODE when automatic mode is activated Ramping Physics IPH ESS Document No Page 16 of 25 PH ESS 29 01 2007 WORKING_MODE WORKING MODE Ox7FA78 Description The bits in this register control the operational modes of the outputs of the RF2TTC Each bit corresponds to one signal Bit number Related output Bit Selected mode value BCl Manual Automatic Manual Automatic Manual Automatic BCmain Manual Automatic Manual Automatic Manual Automatic Manual Automatic ORB_INT_ENABLE Offset Access ORB_INT ENABLE OxFA6C Description This register controls the status of the BC counters that generate the internal orbit pulses Bit number Related orbit Bit value Counter mode Orbit 1 counts BC1 ticks aa ai Disabled Orbit 2 coun
7. 8 ORBmain NOBEAM SELECT 0xFAE4 Description These registers select the sources of the orbit outputs Only one set of registers is active at any time The ORBx_MAN_SELECT registers are active when the RF2TTC is operating in manual mode If the card is in automatic mode and the beam is on the orbit outputs are controlled by the ORBx BEAM_SELECT registers The ORBx_NOBEAM_SELECT registers control the orbit outputs when the RF2TTC is in automatic mode and the beam absent Bit definition for ORB1 and ORB2 registers Value Description 0 Output follows the respective orbit input 1 Output from internal BC synchronized orbit generator Bit definition for ORBmain registers Value Description IPH ESS Document No Page 11 of 25 PH ESS 29 01 2007 Output follows the orbit input Output follows the orbit 2 input Output from internal BCmain synchronized orbit generator ORBx_POLARITY ORB1 POLARITY OxFB60 ORB2_ POLARITY OxFB20 ORBmain POLARITY OxFAEO Description If set this bit inverts the polarity of the orbit output with respect to the orbit input i e the orbit output is negative active ORBx_COARSE_DELAY ORB1 COARSE DELAY OxFBSC 12 bits ORB2 COARSE DELAY 0xFB1C ORBmain COARSE_DELAY OxFADC Description This register allows the orbit output signal to be shifted by multiples of 25 ns with respec
8. Class VME Function cial aaa Created 11 10 2006 Page 1 of 25 PH ESS 29 01 2007 Modified 29 01 2007 1 USER MANUAL RF2TTC 1 0 RF to TTC VMEbus Interface Card and S W Summary This document describes the functionality of the RF2TTC card as well as the generic S W that has been developed for it Prepared by Checked by Approved by Sophie Baron PH ESS Markus Joos PH ESS for information Tel Fax E Mail you can contact Sophie Baron 41 22 7677339 41 22 7678925 sophie baron cern ch Markus Joos 41 22 7672364 41 22 7678925 markus joos cern ch 3 IPH ESS Document No PH ESS 29 01 2007 Table of Contents Introduction RF2TTC Hardware 2 1 VMEbus interface 2 2 VME64x CR CSR space 2 2 1 CSR Space 22 2 CR Space 2 3 Control and status registers 2 4 Calibration procedures 2 5 Board configuration 2 6 Fibre cable connections 2 7 Front panel LEDs 2 8 Improvements for the version 3 2 8 1 Initialisation procedure 2 8 2 others RF2TTC common software 3 1 Introduction 3 1 1 H W Environment 3 1 2 S W Environment 3 2 Test programs 3 3 The user library Page Rev No IPH ESS Document No 3 of 25 PH ESS 29 01 2007 1 INTRODUCTION The RF2TTC RF to TTC VMEbus Interface Card is an interface card between the optical receiver modules receiving timing signals coming from the SR4 buil
9. D024 ORBIN DELAY25 ORBI 0xD020 Description These registers control the configuration of the Delay25 chips for the orbit input signals Finely adjusting the delay of the orbit inputs allows centralising the orbit pulse with the rising edge of the corresponding bunch clock to ensure a good synchronisation of the 2 signals For details about the read protocol see above Bit definition see BC_DELAY _x register ORBOUT_DELAY25_ x Name Offset Used Size Access ORBOUT DELAY25 GCR 0xD054 8 bits R W ORBOUT_DELAY25 ORBmain 0xD048 ORBOUT_DELAY25 ORB2 0xD044 ORBOUT_DELAY25 ORB 0xD040 Description These registers control the configuration of the Delay25 chips for the orbit output signals This adjustment is to allow the experiments fine tuning the orbit for its use in their trigger electronics For details about the read protocol see above Bit definition see BC_DELAY_x register TTCrx registers Name Offset Access TTCrx_pointer to the register 0xE000 R W TTCrx_pointer to the data 0xE004 W IPH ESS Document No Page 21 of 25 PH ESS 29 01 2007 Description These are the two registers used to read and write all the internal registers of the TTCrx used to receive the BST message see TTCrx user manual Only one register requires to be accessed for the purpose of receiving the BST message the control register internal address 0x03 Its val
10. GEOG ADD Ox7 SW 7 0 0x00 SW1 7 5 SW2 4 0 BCx_MAN_SELECT BCx_BEAM_SELECT amp BCx_NOBEAM_SELECT Name Offset Size Access BC1 MAN SELECT 0xFBFC 1 bit R W BC2 MAN SELECT 0xFBCC BCref MAN SELECT 0xFBAC BC1 BEAM SELECT 0xFBF8 BC2 BEAM SELECT 0xFBC8 BCref BEAM SELECT 0xFBA8 BC1 NOBEAM SELECT 0xFBF4 BC2 NOBEAM SELECT 0xFBC4 BCref NOBEAM SELECT 0xFBA4 BCmain MAN SELECT OxFB8C BCmain BEAM SELECT OxFB88 BCmain NOBEAM_ SELECT 0xFB84 Description These registers select the sources of the BC outputs Only one set of registers is active at any time The BCx_ MAN SELECT registers are active when the RF2TTC is operating in manual mode If the card is in automatic mode and the beam is on the BC outputs are controlled by the BCx BEAM SELECT registers The BCx NOBEAM SELECT registers control the BC outputs when the RF2TTC is in automatic mode and the beam absent Bit definition for BC1 BC2 and BCref registers Value Description 0 Output taken from internal 40 078MHz clock 1 Output follows the respective BC input Bit definition for BCmain registers IPH ESS Document No 9 of 25 PH ESS 29 01 2007 Value Description Output taken from internal 40 078MHz clock Output follows BCref input Output follows BC2 input Output follows BC1 input BCx_QPLL_MODE Name Offset Access BC1 Q
11. PLL MODE OxFBFO BC2 QPLL MODE 0xFBC0 BCref QPLL MODE 0xFBAO BCmain_QPLL_ MODE OxFB80 Description These registers define the QPLL locking mode Value Description Re lock only after a reset Re lock automatically if the lock gets lost BCx_DAC BCI DAC 0xFBEC BC2 DAC 0xFBBC BCref DAC 0xFB9C Description These registers define the threshold of the input comparator for the respective BC input channel in a range from 1 25V to 1 25V The threshold is linked to the value of the register by the formula Threshold 1 25 value 2 5 255 BCx_QPLL_STATUS Name Offset i Access BC1 QPLL STATUS 0xFBE8 i R BC2 QPLL STATUS 0xFBB8 BCref QPLL STATUS 0xFB98 BCmain QPLL STATUS 0xFB7C IPH ESS Document No Page 10 of 25 PH ESS 29 01 2007 Description These registers contain the status of the QPLLs of the BC channels Bit 1 indicates that the QPLL detected an error and bit 0 indicates the locking status 0 QPLL OK QPLL has error QPLL not locked QPLL locked ORBx_MAN_SELECT ORBx_BEAM_SELECT amp ORBx_NOBEAM_SELECT Name Offset Size ORBI MAN SELECT OxFB6C 1 bit ORB2 MAN SELECT 0xFB2C ORBI BEAM SELECT 0xFB68 ORB2 BEAM SELECT 0xFB28 ORB1 NOBEAM SELECT 0xFB64 ORB2 NOBEAM SELECT 0xFB24 ORBmain MAN SELECT OxFAEC ORBmain BEAM SELECT OxFAE
12. T optical fibres two are normally available one per ring The optical power level should be between 5dBm and 25dBm BC INPUTS BCI ECL AC coupled signal Should be connected to the BC1 output of the RF_Rx D BC INPUTS BC2 ECL AC coupled signal Should be connected to the BC2 output of the RF_Rx D BC INPUTS BC_REF ECL AC coupled signal Should be connected to the BCref output of the RF_Rx_D ORB INPUTS ORB1 ECL AC coupled signal Should be connected to the ORB1 output of the RF_Rx_D ORB INPUTS ORB2 ECL AC coupled signal Should be connected to the ORB2 output of the RF_Rx_D BC OUTPUTS BCI ECL AC coupled signal Experiments electronics BC OUTPUTS BC2 ECL AC coupled signal Experiments electronics BC OUTPUTS BC_REF ECL AC coupled signal Experiments electronics BC OUTPUTS BCmain ECL AC coupled signal Experiments electronics ORB OUTPUTS ORB1 ECL AC coupled signal Experiments electronics ORB OUTPUTS ORB2 ECL AC coupled signal Experiments electronics ORB OUTPUTS ORBmain ECL AC coupled signal Experiments electronics IPH ESS Document No Page 24 of 25 PH ESS 29 01 2007 2 7 FRONT PANEL LEDs LED Description BC1_LOCK Displays the state of the QPLL chip connected to the selected BC1 signal ON locked OFF not locked BC2_LOCK Displays
13. channel in bits 0 13 Reading the last period stored in the FIFO or from an empty FIFO results in reading a 1 in bit 14 FIFO empty Bit 15 if set to 1 indicates that the FIFO is full For the moment it is not possible to read these FIFOs with a constant address block transfer ORBx_DAQ Offset Access ORB1 DAQ 0xFB3C ORB2_DAQ OxFAFC Description These registers allow setting the threshold voltage of the orbit input comparator in a range from 1 25 V to 1 25 V The threshold is linked to the value of the register by the formula Threshold 1 25 value 2 5 255 TTCrx_status TTCrx_status OxFAAO Description This register reflects the status of the on board TTCrx chip Bit definitions Description Value 0 TTCrx not ready 1 TTCrx ready the BST message is correctly decoded at least a 40MHz clock is sent over the optical fibre connected to the TTCrx BST_Machine_Mode Offset Access BST _ Machine Mode OxFA9C IPH ESS Document No Page 15 of 25 PH ESS 29 01 2007 Description This register holds the LHC machine mode as decoded from the BST messages received by the TTCrx Each number here in hexadecimal corresponds to one machine mode as transmitted by the BST Value Description 0 No Beam 1 Filling Ramping Physics 2 3 4 5 6 7 8 BEAM NO _BEAM_DEF Offset Access BEAM NO BEAM DEF OxFA
14. ding in Echenevex and the TTC electronics within the experiments gee ba i b pe poe T be peas Lae Re RP PRR Cer Rae ame The timing signals treated by the RF2TTC are the three 40 0783MHz Bunch Clocks BC1 BC2 and BCref and the two orbit signals Orb1 and Orb2 necessary to drive the 2 beam lines of the LHC The RF2TTC module converts them into ECL signals and performs various adjustments on each signal before making them available for the in detector TTC electronics RF2TTC module diagram The three Bunch Clocks represented on the top part of the above diagram are all treated in the following way A comparator with an adjustable threshold first converts the input signal into a PECL signal before being multiplexed with an internal 40 078MHz clock in case of absence of the Bunch Clock on the front panel The signal is then shifted by an adjustable delay with 0 5ns precision before being cleaned by a QPLL and transmitted on the front panel via an ECL 50 Ohm coaxial cable driver with an AC coupled output
15. ess 2 VME WRITE AM 0x09 RegOFFSET 0xE004 offset of the data register 0x0000YOURDATA Read fine delay register I2C address 1 l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 2 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning 3 VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x000XYOURDATA with X 0 if the fIFO is not empty X 1 if you are reading the last word stored in a FIFO Successively read fine delay registers 1 and 2 I2C address 1 and 2 VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 ME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning ME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x2 ME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x0O000 YOURDATA ME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x0001 YOURDATA V V VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning V V CALIBRATION PROCEDURES For a proper functioning of the RF2TTC in its environment a number of coarse and fine grained pulse delay and stretch registers have to be tuned by the user A description of this procedure will follow once if that been analyzed to what extent the RF2TTC can perform FPGA based auto calibrations BOARD CONFIGURATION Element Description LSB rotary switch TBD MSB rotary switch TBD FIBRE CABLE CONNECTIONS Connector name IPH ESS Document No PH ESS 29 01 To be connected to TTC encoded signal One of the BS
16. gt 2 I2C_data ID_I2C lt 5 0 gt 2 1 Table 12 I2C address calculation The registers accessible via I2C are the following Default content After reset I2C reg address decimal Register name Fine Delay 1 00000000 Fine Delay 2 00000000 Coarse Delay 00000000 Control 10010011 Single error count lt 7 0 gt 00000000 Single error count lt 15 8 gt 00000000 Double error count lt 7 0 gt 00000000 SEU error count lt 15 8 gt 00000000 ID lt 7 0 gt 00000000 MasterModeA lt 1 0 gt ID lt 13 8 gt 00000000 MasterModeB lt 1 0 gt I2C_ID lt 5 0 gt 00000000 Config 1 00011010 Config 2 10000100 Config 3 10100111 Status 11100000 Bits lt 7 0 gt 00000000 Bits lt 15 8 gt 00000000 Bits lt 7 0 gt 00000000 Bits lt 15 8 gt 00000000 Bits lt 23 16 gt 00000000 2 5 IPH ESS Document No Page 22 of 25 PH ESS 29 01 2007 Example of registers read and write via VME access Read control register I2C address 3 l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x3 register I2C address 2 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning 3 VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x00000003 Write Fine Delay Register I2C address 1 l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 register I2C addr
17. he adjustments are done using VME registers Many status registers are available as well as special configurations for stand alone or debugging work This document contains a description of all accessible registers of the RF2TTC card as well as description of the generic S W that has been developed for this card At the end of this document some basic examples of configuration procedures are proposed IPH ESS Document No Page 5 of 25 PH ESS 29 01 2007 2 RF2TTC HARDWARE 2 1 VMEBUS INTERFACE The VMEbus interface of the RF2TTC cards is implemented in its FPGA and based on the VME interface developed by Peter Lichard for the TRT TTC board ATLAS It provides three types of VMEbus addressable resources as described in Table 1 Resource VMEbus access mode Description Geographical or Manual addressing The RF2TTC provides a limited set of A24 D32 with AM code 0x2F CR CSR registers Control and status A32 D32 with A19 0 and AM code These are the registers that control the registers 0x09 behaviour of a RF2TTC card and provide information about its current status EPROM A32 D32 with A19 1 and AM code The access to the EPROM is reserved for in 0x09 crate reconfiguration Table 1 VMEbus resources of the RF2TTC VME64x CR CSR SPACE This space is accessible using A24 D32 0x2F AM code The BAR is loaded at sysreset with the value set by the rotary switch if it is different from 0x00
18. ips in reset mode no effect QPLL chips not in reset mode place TTCrx chips in reset TTCrx chips in reset mode mode no effect TTCrx chips not in reset mode IPH ESS Document No Page 7 of 25 PH ESS 29 01 2007 UBCLEAR User defined BCLEAR Register assignment Description This register is declared in the VME64x as a User defined Bclear register It is used here to remove partial reset functions QPLL only Delay25 chips only TTCrx only The bit definition is as follows Bit Value Write Read 1 remove Delay25 chips from Delay25 chips in reset mode reset mode no effect Delay25 chips not in reset mode remove QPLL chips from reset QPLL chips in reset mode mode no effect QPLL chips not in reset mode remove TTCrx chips from reset TTCrx chips in reset mode mode no effect TTCrx chips not in reset mode 2 2 2 CR Space Register Address Value REVISION ID 0x00040 Hardware version PROGRAM ID 0x00074 Firmware date number ee pee Ex 0x28112006 28 of November 2006 IPH ESS Document No 8 of 25 PH ESS 29 01 2007 CONTROL AND STATUS REGISTERS This space is accessible using 0x09 AM A32 D32 The board address is the geographical address of the module if the manual rotary switches are set to 0x00 The address used to access the user space is hence defined as follows A31 A28 A27 A24 A23 A20 A19 A16 SW 7 0 0x00 0
19. ory as the outputs are all disabled The same for the TTCrx which does not allow by default the transmission of the broadcast words Finally the DAC in charge of the threshold adjustments are set to 1 25V by default after power up Hence the Delay25 TTCrx and DAC chips need to be initialised first and it requires using some internal protocols I2C or other controlled by VME accesses A solution will be provided to ensure the board initialisation without using a crate processor This initialisation will ensure that e All the delay25 chips are enabled i e transmit the signals present at their inputs e All the DACs are configured correctly to allow latching the input signals if any e The TTCrx chips is configured to transmit the BST message to the FPGA 2 8 2 others IPH ESS Document No Page 25 of 25 PH ESS 29 01 2007 3 RF2TTC COMMON SOFTWARE 3 1 INTRODUCTION Even though the RF2TTC performs the same task in each of the four LHC experiments it will be operated in H W and S W environments that are specific to the respective experiment Therefore the common S W is limited to the lowest level which consists of some diagnostic programs and a user library This S W is implemented in the rf2ttc package and can be found in CERN CVS repository at http isscvs cern ch cgi bin viewcvs all cgi rf2ttc cvsroot rf2ttc For direct access from Unix use e g setenv CVSROOT kserver isscvs cern ch local reps rf2ttc
20. s These chips ensure the BC signal to be shifted by steps of 0 5ns with a jitter lower than 19ps rms For details about the read protocol see above Bit definition from Delay25 manual The bit allocation of each channel control register is as given in the following table Bits Del lt 5 0 gt control the delay for each channel and the Enable bit enables the channel output Upon a reset bit Enable and bits Del lt 5 0 gt are cleared Control registers CRO to CR4 bit allocation B7 B6 B5 B4 B3 B2 Bl Bo EA E a a The general control register GCR controls the operation of the Delay Locked Loop DLL and allows to reset the DLL or the ASIC via the I2C interface The bit allocation for this register is given in Table 4 IPH ESS Document No Page 20 of 25 PH ESS 29 01 2007 General Control Register GCR bit allocation B6 BS B4 B3 B B7 B2 B1 i reserve IDL nu n nu nu M lt 1 gt M lt 0 gt Function d L u Not Not Reset State cleared cleared The ASIC can operate with for different clock frequencies 32 40 64 and 80 MHz For this application the M lt 0 gt and M lt 1 gt bits must be set to 0 40MHz IDLL bit IDLL is used to force the resynchronization of the DLL without resetting the chip Writing a 1 to this bit forces the resynchronization of the DLL This bit always reads as a 0 ORBIN_DELAY25 x Offset Access ORBIN _ DELAY25 GCR 0xD034 ORBIN _DELAY25 ORB2 0x
21. t No Page 13 of 25 PH ESS 29 01 2007 ORBx_COUNTER ORB1 COUNTER OxFB4C 32 bits ORB2_ COUNTER OxFBOC ORBmain COUNTER OxFACC Description This register holds the number of orbit pulses that have been received since the counter was reset enabled At an orbit period of 89 us this counter will overflow after approximately 106 hours and will be reset ORBx_PERIOD_RD ORB1 PERIOD RD 0xFB48 12 bits ORB2 PERIOD RD 0xFB08 ORBmain PERIOD_RD OxFAC8 Description This register holds the time in units of 25 ns BC ticks that has elapsed between the last two orbit output pulses ORBx_PERIOD_FIFO_STATUS Offset Access ORB1 PERIOD FIFO STATUS 0xFB44 ORB2 PERIOD FIFO STATUS 0xFB04 ORBmain PERIOD FIFO STATUS OxFAC4 Description This register holds the status of the FIFO that contains the most recent 128 orbit periods of the respective orbit output channel Bit definitions Bit Value Description 0 Fifo not empty 1 Fifo empty 0 Fifo not full Fifo full IPH ESS Document No Page 14 of 25 PH ESS 29 01 2007 ORBx_PERIOD_FIFO_RD ORBI PERIOD FIFO RD 0xFB40 16 bits ORB2 PERIOD FIFO RD 0xFB00 ORBmain PERIOD FIFO RD OxFACO Description These registers provide access to three 256 word deep FIFOs which contain the most recent 256 orbit periods of the respective orbit output
22. t to the input If set to 0 the output is shifted by the minimum intrinsic delay induced by the board itself Values above OxDEB 3563 are illegal because they would result in a shift longer than the LHC orbit period 88 93 us ORBx_LENGTH Offset Access ORB1 LENGTH OxFB58 ORB2_ LENGTH OxFB18 ORBmain LENGTH OxFAD8 Description This register allows the orbit pulse to be stretched in steps of 25 ns If set to 0 the width of the orbit pulse is stretched by 75 ns The largest pulse width with all 8 bits set to 1 is 6 4 us The original width of the internally generated orbit pulse is 75ns ORBx_INT_PERIOD SET Name Offset Access IPH ESS Document No Page 12 of 25 PH ESS 29 01 2007 ORBI_INT PERIOD SET 0xFB54 12 bits R W ORB2 INT PERIOD SET 0xFB14 ORBmain INT PERIOD SET OxFAD4 Description This register allows setting the period of the internally generated orbit signal in units of 25 ns The default value is OxDEB which corresponds to 3563 bunch clocks between two orbits ORBx_INT_PERIOD_COUNTER Offset Access ORB1_INT PERIOD COUNTER OxFB50 12 bits ORB2_INT PERIOD COUNTER OxFB10 ORBmain INT PERIOD COUNTER 0xFADO Description This register is provided for debugging purposes It holds the value of the BC counter that is used to generate the internal orbit signal This can be reset by the ORB_INT_RESET register IPH ESS Documen
23. the state of the QPLL chip connected to the selected BC1 signal ON locked OFF not locked BCREF LOCK Displays the state of the QPLL chip connected to the selected BC1 signal ON locked OFF not locked BCmain_LOCK Displays the state of the QPLL chip connected to the selected BC1 signal ON locked OFF not locked ORB1 OK Monitors the presence of the external orbit after the comparator ON signal present OFF no signal When OFF it can mean either that the orbit is not present or that the DAC setting the threshold at the input does not deliver an adapted threshold Monitors the presence of the external orbit after the comparator ON signal present OFF no signal When OFF it can mean either that the orbit is not present or that the DAC setting the threshold at the input does not deliver an adapted threshold BEAM Monitors if the current machine mode corresponds to a BEAM mode or a NO BEAM mode ON BEAM OFF NO BEAM BST ready Monitors the state of the TTCrx in charge of receiving and transmitting the BST message to the FPGA ON TTCrx ready received frame is consistent and can be decoded OFF no consistent BST message Flashes when the RF2TTC generates a BERR Not implemented yet Flashes if the RF2TTC has replied to a VMEbus cycle 2 8 IMPROVEMENTS FOR THE VERSION 3 2 8 1 Initialisation procedure The state of the Delay25 chips after a reset is not satisfact
24. ts BC2 ticks P Disabled Main orbit counts BCmain fF 0 Disabled ticks IPH ESS Document No Page 17 of 25 PH ESS 29 01 2007 ORB_COUNTER_ENABLE Offset Access ORB COUNTER ENABLE OxFA68 Description This register controls the status of the orbit pulse counters Once a channel has been enabled the registers ORBx COUNTER count the orbit pulses of that channel Bit number Related orbit Bit value Counter mode ae Sn oe i cee et oe ft a PERIOD_COUNTER_ENABLE Offset Access PERIOD COUNTER ENABLE OxFA64 Description This register controls the status of the orbit period counters Once a channel has been enabled the FIFOs and ORBx_PERIOD_FIFO_RD start measuring and storing the duration of orbit signals Bit number Related orbit Bit Counter mode value i oe i eos oe a_i IPH ESS Document No Page 18 of 25 PH ESS 29 01 2007 RESET registers Name Offset Access Function ORB_ INT RESET OxFA4C W Reset the three counters that generate the internal orbits 1 2 and Main One bit per counter Same definition than the ORB_INT_ENABLE register PERIOD COUNTER RE OxFA48 Reset the counters that measure the SET period of the orbit pulses 1 2 and Main At the same time the period FIFOs are cleared One bit per counter Same definition than the PERIOD COUNTER ENABLE register ORB COUNTER RESET OxFA44 Reset the orbit pulse counters 1 2 and Main
25. ue should be 0xB3 instead of 0x93 its default value The 1 added on bit 5 allows enabling the Dout bus of the TTCrx which contains the broadcast data and hence the Machine Mode Register access protocol The TTCrx chip needs to be ready ie the optical fibre needs to deliver a correct encoded 40MHz clock in order to access the internal registers The way to access the TTCrx registers is described in the TTCrx manual p30 I2C_pointer register and the I2C_data register The I2C_pointer register is five bits wide and contains the address of the internal register as defined in Table 3 page 16 When reading the I2C_data register the content of the TTCrx register being addressed by the pointer register is transferred Conversely writing a byte to the I2C_data register in fact writes to the TTCrx register addressed by the I2C_pointer register Hence each I2C access is performed in two steps 1 Write the register number in the I2C_pointer register 2 Read or write the I2C_data register According to the I2C bus specification each device on the bus is addressed by a 7 bit wide I2C device address Each TTCrx chip occupies two consecutive positions in the 7 bit I2C address space Hence it is possible to address 64 devices in the system The 7 bit I2C address is derived from the content of the ID _I2C lt 5 0 gt base address register in the following way 12C access register name Resulting 7 bit 12C address I2C_pointer ID_I2C lt 5 0
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