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TM8705 User`s Manual

1. 89 m 91 4 3 Segment PLA Circuit for LCD Display 92 CHAPTER 5 Detail Explanation of TM8706 Instructions 98 5 1 Input Ouiput InsIric loris aida dns eR pud cic RC 98 5 2 Accumulator Manipulation Instructions and Memory Manipulation 105 107 5 4 Load Store InStruClionS 118 5 5 CPU Control Instructions done ane 120 5 6 Index Address Instructions ee ee 129 5 7 Decimal Arithmetic Instructions UE Getae 124 5 8 EIN ISTIC 126 5 9 Miscellaneous Instructions I N 127 APPNDIX A TM8705 Instruction Table 133 2 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM8705 is an embedded high performance 4 bit microcomputer with LCD driver It contains all the necessary functions such as 4 bit parallel processing ALU ROM RAM l O ports timer clock generator dual clock operation Resistance to Frequency Converter RFC EL panel driver LCD driver look up table watchdog timer and key matrix scanning circuitry i
2. H ES Fis 34 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 1 0 PH5 po 1 1 FREQ i D 0 PH pt fof a PH 1 10 PHI Notes 1 When the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH1 1 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 error 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 The 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR1 clock is FREQ TMR1 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 12 2 RE LOAD OPERATION TMR1 provides the re
3. CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver the waveform for the IR remote controller For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example 67 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SHE 1 Enable timer 1 halt release enable flag TMSX 3Fh Setvalue for timer 1 is 3Fh and the clock source is PHY SCC 40h Setthe clock source of the frequency generator as BCLK FRQX 2 3 FREQ BCLK 4 2 setting value for the frequency generator iis 3 and duty cycle is 1 2 ALM 1COh FREQ signal is outputted This instruction must be executed after the FRQ related instructions HALT Wait for the halt release caused by timer 1 uyana s Halt released ALM 0 Stop the buzzer output 3 5 INPUT OUTPUT PORTS Four I O ports are available in TM8705 IOA IOB IOC and IOD Each I O port is composed of 4 bits and has the same basic function When the I O pins are defined as non lO function by mask option the input output function of the pins will be disabled 3 5 1 IOA PORT IOA4 pins are MUX with CX SEG24 RR SEG25 RT SEG26 and RH SEG27 pins respectively by mask option
4. r Fora if ACO 1 ele i 1 Ex 136 tenx technology inc Rev 1 2 2003 7 31 ele x t X E E c qq C C C I C C C cw O N Z Z UJ Z UJ S N 5 Na gt Z r 1100 PXXX XXXX XXXX PX 1101 PXXX XXXX XXXX c B HL 1110 0001 0000 0000 TR7 6 11 TR7 6 10 TR7 6 01 TR7 6 00 TR5 0 1110 001X XXXX XXXX X8 7 62111 X8 7 6 110 X8 7 6 101 X8 7 6 100 X8 7 6 011 X8 7 6 010 X8 7 6 001 X8 7 6 000 X5 0 lt gt aa I 1110 011X X8 7 62111 X8 7 6 110 X8 7 6 101 X8 7 6 100 X8 7 6 011 X8 7 6 010 X8 7 6 001 X8 7 6 000 0 1110 101X OXXX XXX NN 0 1110 1100 XX o m m m 1110 1101 XOXX X000 137 Machine Code x 1110 0000 XXXX AC3 2210 AC3 2 01 AC3 2 00 AC1 0 Rx3 0 TM8705 Users Manual Flag Remark PC gt 000h 7FFh PC gt 800h BFFh PC gt 000h 7FFh PC gt 800h BFFh Ctm PH15 Ctm PH3 Ctm PH9 Set Timer1 Value Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set Timer1 Value Ctm PH13 Ctm PH11 Ctm PH7 Ctm PH5 Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set Timer1 Value HIPOND OSEE mer fe Fy AG 1110 0101 0000 0000 T HL Ctm PH13 Ctm PH11 Ctm PH7 Ctm PH5 Ctm FREQ Ctm PH15 Ctm PH3 Ctm PH9 Set
5. M m 2 x 140 tenx technology inc Rev 1 2 2003 7 31
6. The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition Backup flag flag 3 flag 2 flag 1 BCF SCF3 SCF2 SCF1 Halt release Halt release Halt release caused by the caused by caused by the m IOD port SCF4 5 6 7 9 IOC port Start condition flag 3 SCF3 When the SCA instruction specified signal change occurs at port IOD to release the halt mode SCF3 will be set Executing the SCA instruction will cause SCF3 to be reset to 0 Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 Start condition flag 2 SCF2 When a factor other than port IOA and IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags in SCF4 5 6 7 9 is set to 1 SCF2 will also be set to 1 simultaneously When all of the flags in SCF4 5 6 7 9 are clear start condition flag 2 SCF2 is reset to 0 Note If start condition flag is set to 1 the program will not be able to enter halt mode 42 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Backup flag BCF This flag could be set reset by executing the SF 2h RF 2h instruction 2 14 3 STATUS REGISTER 3 STS3 When the halt mode is released by start condition flag 2 SCF2
7. DBUSA to DBUSH is applied to the latch input L and one of the PSTBO to PSTB3Fh outputs are applied to clock CLK TM8705 provide a flash type instruction to update the LCD pattern When LCTX D LCBX D LCPX D and LCDX D instruction are executed the pattern of DBUS will be outputted to 16 latches Lz specified by D simultaneously 95 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual D Specified range of latched x O Lz 00h 0Fh Lz 10h 1Fh Refer to Chapter 5 for detail description of these instructions PSTBO PSTB3Fh Driver option Mask option COM6 Figure Sample Organization of Segment PLA Option 4 3 4 THE CONFIGURATION FILE FOR MASK OPTION When configuring the mask option of LCD PLA the cfg file provides the necessary format for editing the LCD configuration The syntax in cfg file is as follows SEG COM PSTB DBUS SEG Specifies the segment pin No 1 40 represents segment pin No C1 C6 represents common pin No When the common pin COM is specified as DC output pin assigned C1 C6 in this column C1 C6 represents COM1 COM6 respectively 96 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual COM Specifies the corresponding latch in each segment pin Only 0 1 2 3 4 5 6 can be specified in this column 1 6 represents COM1 latch COM6 latch respectively 0 is for CMOS typ
8. AC Rx Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx Carry flag CF will be affected AC HL HL AC B CF The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC and data memory HL HL indicates an index address of data memory Carry flag CF will be affected AC HL HL AC B CF HL HL 1 The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected AC Rx AC The contents of Rx and AC are binary added the result is loaded to AC Carry flag CF will be affected AC e HL AC The contents of HL and AC are binary added the result is loaded to AC HL indicates an index address of data memory Carry flag CF will be affected AC HL AC HL HL 1 110 tenx technology inc Rev 1 2 2003 7 31 Description ADD Rx Function Description ADD HL Function Description ADD Function Description SUB Rx Function Description SUB HL Function Description SUB HL Function Description TM8705 Users Manual The contents of HL and AC are binar
9. 0101 0100 0000 0000 0101 0101 OX XK H 0101 0101 1000 0000 HL 0101 0101 1100 0000 AC R HL BCD AC HL HL 1 0101 0110 0000 0000 JAC BCD AC 0101 0111 OXX XXX AGCRx H 0101 0111 1000 0000 AC R HL BCD AC AC 0101 0111 1100 0000 AC R HL BCD HL lt HL 1 zz w DAA gt Qo DAS DAS DS DH LDH Rx HL Rx HL 0110 0001 OXXX XXX AC Rx lt H T HL Rx HL O0110 0010 XOX LDL Rx HL 0110 0011 OXXX XXX AC Rx lt L T HL HL HL 1 0110 0110 0XO XK 110 1000 WOK 10 1000 1000000 ac 1 mO lt a j 8838 O 5 ojo 110 1100 OXXX XXX DA 100 1100 1000 0000 LDA HL 0100 1100 1100 0000 AO AC Rx Rx Rx Ry D T lt R HL HL HL 1 AC R HL ACGR HL En lt MRA MRW O 110 1101 OXXX 110 1110 OXXX XX 0110 1110 1 XXXX HL Rx HL Rx rr N 5 gt E gt gt gt x gt gt gt So z p 2 T lt 0110 1111 OXXX XXXX 0110 1111 1 XXX ACR AC Rx R HL 111 OYYY YXXX AC Ry 111 1YYY YXXX AC Rx 1000 ORK KK KKK PC 1000 DOO OK XK PC 1001 099090 WOK PC 011 OXXX XXXX XXXX 011 DOK XXXX XXXX Rx HL y Rx x Ry O U U u QU U gt S gt o o o ol o 9
10. 233 082 0 248 242 246 942 0 53 R O a N Ic Xo head oO B5 TM8705 Users Manual Note 1 Above variation does not include X tal variation 2 If PH0 65536Hz C3 B5 may have more accurate frequency During the application of melody output sound effect output or carrier output of remote control the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 3 3 3 Halver Doubler Tripler The halver doubler tripler circuits are used to generate the bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 PH5 When the Li battery application is used the 1 2 VDD voltage generated by the halver operation is supplied to the circuits which are not related to input output operation 3 3 4 Alternating Frequency for LCD The alternating frequency for LCD is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ Each is MUXed with IOB3 and IOB4 by mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When buzzer output function combined with the clock source comes from the frequency generator this output function may generate melody sound effect or carrier output of remote control MASK OPTION table Mask Option name Selected item SEG30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 3 BZ This figure
11. LDS 11h 1 Load immediate data 1 to data memory address 11H and AC 32 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual HF 1h Reset CF to 0 ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to AC amp data memory address 10H Rio AC Ar CF 0 DAA 10h Convert the content of AC to decimal format The result in the data memory address 10H is 0 and in the CF is 1 This represents the decimal number 10 Instructions DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0c AC 6 lt AC lt F AC AC A Example 2 LDS 10h 1 Load immediate data 1 to the data memory address 10H LDS 11h 2 Load immediate data 2 to the data memory address 11H and AC SF 1h Set CF to 1 which means no borrowing has occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H Rio AC Fu CF 0 DAS 10h Convert the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 33 tenx technology inc Rev
12. When the stop release enable flag 7 SRF7 and the HEF5 are set the H signal from OR ed output of K1 4 latch signals can cause the stop mode to be released 2 15 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 7 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset by SIE instruction The bit pattern of control register 3 CTL3 is shown below I eni IEF6 IEF5 DEC flag Bst SUE Enable the interrupt request Enable the interrupt request Enable the interrupt request E 3 caused by RFC counter to caused by Key Scanning caused by TMR2 underflow 2 be finished HRF6 EET i Interrupt flag Interrupt 6 merpt4 4 Interrupt4 4 I I maripi anang IEF3 IEF2 IEF1 flag Enable the interrupt request Enable the interrupt request Interrupt request db divid Enable the interrupt request d by TM1 underfi cause redivider cause underflow flag yP caused by INT pin HRF2 7 overflow HRF3 Interrupt flag Interrupt 3 Interrupt 2 e l dmempti Oe 1 l nterrupt enable IEF0 flag Enable the interrupt request Interrupt request caused by IOC or IOD port signal to be changed HRF0 Interrupt flag Interrupt 0 48 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automatically Therefore t
13. i T gt gt gt gt J gt gt lt lt D D titr 333 lt lt lt gt gt z O ORI NC NC 0100 0000 0100 0000 1000 0000 lt 1 HL 0100 0001 OHO WOK 0100 0001 1000 0000 lt 1 HL 0 HL 0100 0001 1100 0000 AC R HL R HL c HL 1 zz O 5 o DEC DEC w m O 3E gt 100 0010 0X6 WORK 0100 0100 0XO XK 01000111 OK Xx ACARx IO O 0 A D T lt T 100 1000 0100 1010 OXXX XXXX AC Rx STS1 B3 CF ZERO No use 0100 1011 OXXX XXXX AC Rx lt STS2 SCF3 DPT SCF2 HRx SCF1 CPT BCF 0100 1100 OXXX XXXX AC Rx lt STS3 SCF7 PDV PH15 SCF5 TM1 SCFA INT 0100 1101 OXXX XXXX AC Rx lt STS3X SCF9 RFC No use SCF6 TM2 SCF8 SKI 0100 1110 OXXX XXXX AC Rx lt STS4 No use RFOVF WDF CSF 135 tenx technology inc Rev 1 2 2003 7 31 RyD yD O yD O yD O 7 O Rx RK i TM8705 Users Manual Flag Remark RO ACn Rxn lt Rx n 1 AC3 Rx3 0 0101 0001 OXXX XXXX ACn Rxn n1 AC3 Rx3 1 ACn Rxn Rx n 1 AC0 Rx0 0 0101 0011 OXXX XXXX n 1 1 Q 9 8 eo Oo Rx Rx x O R ACn Rxn Rx n 1 ACO Rx0 ie i
14. Description EORI Ry D TM8705 Users Manual D 0H FH Ry Ry Y 1 D represents the immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC e Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC The result will not affect the carry flag CF D OH FH AC Ry Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The result will not affect the carry flag CF D 0H FH AC lt Ry amp D D represents the immediate data The contents of Ry and D are binary ANDed the result is loaded to AC D OH FH AC Ry Ry amp D D represents the immediate data The contents of Ry and D are binary ANDed the result is loaded to AC and working register Ry D 0H FH AC lt Ry EOR D D represents the immediate data The contents of Ry and D are exclusive ORed the result is loaded to AC D 0H FH 117 tenx technology inc Rev 1 2 2003 7 31 Function Description ORI Ry D Function Description ORI Ry D Function Description TM8705 Users Manual AG Ry Ry D represents the immediate data The contents of Ry and D are exclusive OREd the result is
15. HEF 3 S SHE 8 IEF4 SIE 10h E Interrupt 4 Timer2 HRF4 underflow HEF4 SHE 10h IEF5 SIE 20h Interrupt 5 overflow HEF5 DS SHE 20h counter overflow HEF6 E SHE 40h condition flags for TM8705 IEF6 SIE 40h D Interrupt 6 2 14 1 STATUS REGISTER 1 STS1 Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the result of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 41 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual If the content of the accumulator is not 0 the zero flag is reset to 0 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 Bit 0 Carry flag AC Zero flag Z Read only Read only Read only 2 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 SCF1 SCF2 and the backup flag The MSB instruction can be used to transfer data of status register 2 STS2 to the accumulator AC and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2
16. Interrupt 0 Specified signal change at X0 Priority IOC or IOD port control circuit L Interrupt 1 Timer TM underflow X1 Interrupt Specified signal Interrupt 2 request change at INT pin signal Interrupt vector address generator Interrupt 3 Predivider overflow Interrupt 4 2 underflow Specified signal enable at Key Interrupt 5 matrix Scanning RFC counter Interrupt 6 overflow Interrupt accept signal SIE instruction Initial clear 56 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC or IOD ports or Key matrix Scanning 1 External INT pin interrupt request By using mask option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the signal on the INT pin change that matches the mask option will issue the HRF2 interrupt 2 is accepted and the instruction at address10H is executed automatically It is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 port IOC IOD interrupts request An interrupt request signal HRFO is delivered when the input signal changes at I O port IOC IOD specified by the SCA instruction In this case if the interrupt enabled by
17. KO5 8 X3 2 10 gt KO9 12 X3 2 11 gt KO13 16 Set two of KO1 16 1 by X3 2 1 X3 1 000 gt KO1 2 X3 1 001 gt KO3 4 X3 1 010 gt KO5 6 X3 1 011 gt KO7 8 X3 1 100 gt KO9 10 X3 1 101 gt KO11 12 X3 1 110 gt KO13 14 X3 1 111 gt KO15 16 ALL Return Cfq BCLK Cfq PHO Set P C Cch Set P D Cch Cch PH10 Cch PH8 Gch PH6 Set Ca 1 Pull Low Low Level Hold Set C4 1 I O ipso D4 1 Pull Low ipso D4 1 I O Reload 1 Set WDT Enable HALT after EL EL LIGHT On BCF Set CF Set tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Instruction Machine Code Flag Remark 1111 0111 X00X OXXX Reload 1 Reset 1111 10XX XXX XXXX X9 5 4 001 X9 5 4 000 X3 2 11 X3 2 10 X3 2 01 X3 2 00 X1 0 11 X1 0 10 X1 0 01 X1 0 00 WDT Reset EL LIGHT Off BCF Reset CF Reset Enable INT powerful Pull low Close all Segments 1111 110X XXX XXX Dis ENX Set 1111 1110 0000 XXXX x Reload 2 Set 1111 1110 1000 XXXX Disable INT powerful Pull a X0 low Release Segments Dis ENX Reset Reload 2 Reset 1111 1111 0000 0000 Halt Operation 1111 1111 1000 0000 Stop Operation 139 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Symbol Description Description Symbol Description ontent of Register D mmediate Data ccumulator DB Complement of Immediate Data PC D B ontent of Accumulator bit n PG rogram Counter CF
18. MRF1 Rx Function Description MRF2 Rx Function Description TM8705 Users Manual AC e HL The content specified by HL is loaded to AC HL indicates an index address of data memory AC e HL HL HL 1 The content specified by HL is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Rx AC TAB HL high nibble The higher nibble data of look up table specified by HL is loaded to data memory specified by Rx Rx AC TAB HL high nibble HL HL 1 The higher nibble data of look up table specified by HL is loaded to data memory specified by Rx and then is increased in HL Rx AC TAB HL low nibble The lower nibble data of look up table specified by HL is loaded to the data memory specified by Rx Rx AC TAB HL low nibble HL HL 1 The lower nibble data of look up table specified by HL is loaded to the data memory specified by Rx and then is increased in HL Rx AC RFC 3 0 Loads the lowest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 3 Bit 2 RFC 2 Bit 1 RFC 1 Bit 0 RFC 0 Rx AC RFC 7 4 Loads the 2 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 7 Bit 2 RFC 6 119 tenx technology inc Rev 1 2 2003 7 31 MRF3
19. R HL AC CF HL HL 1 0010 0001 1100 0000 AC R HL R HL AC CF UE en erta A 0010 0010 1100 0000 R HL AC B CF HL 1 AGR 0010 0011 XOX AC Rx Rx AC B CF 0010 0011 1000 0000 AC R HL R HL AC B CF E 0010 0011 1100 0000 AC R HL R HL AC B CF HL lt HL 1 TOTO 0010 0100 1000 0000 A C H Rx AC AC 0010 0100 1100 0000 C R HL AC eee je eomm Rx AC AC AC H H 0010 OTOT_ OX XXX AC F 8 ADC ADC ADC SBC H H SBC H thi SBC H H L i SBC O O UJ UJ ik gt DD ADD ADD ADD ADD H H H ADD H 0010 0101 1000 0000 R HL L L 0010 0101 1100 0000 AC R HL R HL HL HL 1 L O UB SUB SUB A 0010 0110 1000 000 X e RGHD AC B 1 A 0010 0110 1100 0000 C R HL AC B 1 e QHL 1 0010 0111 OXXX XX R3 AGB 1 SUB SUB SUB L L L L L L L L L L L H H H 0010 0111 1000 0000 R HL AC B 1 E HL 0010 0111 1100 0000 AC R HL lt R HL AC B 1 HL lt HL 1 0010 0170 ORK XX Ac PX ROB ADN ADN ADN 0010 1000 OX XXX AC A c je 0010 1000 1000 000 JAC R HL o e Rx AC AC HL 0010 1000 1100 0000 R HL AC ADN ADN GHL A
20. The specified columns are defined by the setting of Xs and X X3X 00 active K1 K4 columns simultaneously X3X 01 active K5 K8 columns simultaneously X3X 10 active K9 K12 columns simultaneously X3X2 11 active K13 K16 columns simultaneously X1 Xo don t care X7X5X4 111 in this setting each scanning cycle check two specified columns on key matrix The specified columns are defined by the setting of Xs X and X1 X3X 5X 000 active K1 K2 columns simultaneously X3X25X 001 active K3 K4 columns simultaneously X3X2X1 110 active K13 K14 columns simultaneously X3X2X1 111 active K15 K16 columns simultaneously Xo don t care Sets Key matrix scanning output state When SEG1 16 is are used for LCD driver pin s set the content of AC and Rx to specify the key matrix scanning output state for each SEGn pin in scanning interval The bit setting is the same as SPKX instruction and bit pattern of AC and Rx corresponding to SPKX is shown below n SPK Rx SPKX X SPK HL 103 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Function Sets Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s set the content of table ROM HL to specify the key matrix scanning output state for each SEGn pin in scanning interval The bit setting is the same as SPKX instruction and bit pattern of table ROM corresponding to SPKX is shown b
21. once the signal on the IOC port returns to L the TM8705 will enter the stop mode immediately The backup flag BCF will be set to 1 automatically after the program enters the stop mode The following diagram shows the stop release procedure STOP HALT normal MODE Yes released mode release Figure 3 16 The stop release state machine Before the stop instruction is executed the following operations must be completed Specify the stop release conditions by the SRE instruction Specify the halt release conditions corresponding to the stop release conditions if needed Specify the interrupt conditions corresponding to the stop release conditions if needed HALT released decision When the stop mode is released by an interrupt request the TM8705 will enter the halt mode immediately While the interrupt is accepted the halt mode will be released by the interrupt request The stop mode returns by executing the RTS instruction after completion of interrupt service 52 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual After the stop release it is necessary that the MSB MSC or MCX instruction be executed to test the halt release signal and that the PLC instruction then be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter the stop mode but the halt mode When the stop mode is releas
22. status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal change at the INT pin causes the halt release request flag 2 HRF2 to be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC instruction must be used to reset the halt release request flag 2 HRF2 or the SHE instruction must be used to reset the halt release enable flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF1 or the SHE instruction must be used to reset the halt release enable flag 1 HEF1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the halt release enable flag 3 HEF3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag 3 HRF3 or the SHE instruction must be used to reset the halt release enable flag 3 HEF3 4 T
23. 1 2 2003 7 31 TM8705 Users Manual 2 12 TIMER 1 TMR1 Re load RL1 TMS instruction IEF1 Initial reset TMR1 Interrupt SCF5 Halt release HEF1 Operand data xX5 x0 TMS instruction Interrupt accept signal Operand data PLC 2 instruction x8 x7 x6 TMS instruction Initial reset This figure shows the TMR1 organization 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or TMSX instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag 1 HRF1 to 1 and then stop to count down When HRF1 1 and the TMR1 interrupt enable flag IEF1 1 the interrupt is generated When HRF1 1 if the IEF1 0 and the TMR1 halt release enable HEF1 1 program will escapes from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurred the clock source of TMR1 will still keep the previous selection The following table shows the definition of each bit in TMR1 instructions OPCOD Select clock Initiate value of timer E TMSX X TMS Rx 0 AC3 AC2 AC1 ACO Rx3 R2 Rx0 TMS bit7 bit bit5 Bit4 bit3 bit2 biti bit0 HL The following table shows the clock source setting for TMR1
24. 2 PH12 2 In this option the reset cycle time will be extended 2048 clocks clock source comes form pre divider long at least 3 2 1 POWER ON RESET TM8705 provides a power on reset function If the power VDD is turned on or power supply drops below 0 6V it will generate a power on reset signal Power on reset function can be disabled by mask option MASK OPTION table Mask Option name Selected item POWER ON RESET 1 USE POWER ON RESET 2 NO USE 3 2 2 RESET PIN RESET When H level is applied to the reset pin the reset signal will issue Built in a pull down resistor on this pin Two types of reset method for RESET pin and the type could be mask option the one is level reset and other is pulse reset lt is recommended to connect a capacitor 0 1uf between RESET pin and VDD This connection will prevent the bounce signal on RESET pin 3 2 2 1 Level Reset Once a 1 signal applied on the RESET pin TM8705 will not release the reset cycle until the signal on RESET pin returned to 0 After the signal on reset pin is cleared to 0 TM8705 begins the internal reset cycle and then release the reset status automatically MASK OPTION table Mask Option name RESET PIN TYPE 1 LEVEL 3 2 2 2 Pulse Reset Once a 1 signal applied on the RESET pin TM8705 will escape from reset state and begin the normal operation after internal reset cycle automatically no matter what the signal on RESET pin returned t
25. AC The contents of OHL and AC are exclusive Ored the result is loaded to AC HL indicates an index address of data memory AC e HL 6 AC HL HL 1 The contents of HL and AC are exclusive ORed the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Rx Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC and data memory Rx AC HL HL AC The contents of HL and AC are exclusive Ored the result is loaded to AC and data memory HL HL indicates an index address of data memory AC HL HL 6 AC HL HL 1 The contents of HL and AC are exclusive ORed the result is loaded to AC and data memory HL 114 tenx technology inc Rev 1 2 2003 7 31 OR Rx Function Description OR HL Function Description OR HL Function Description OR Rx Function Description OR HL Function Description OR HL Function Description ADCI Ry D Function Description TM8705 Users Manual The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Rx AC The contents of Rx and AC are binary Ored the result is loaded to AC AC e HL AC The contents of HL and AC are binary Ored t
26. Function Defines the input output mode of each pin for IOC port and enables disables the pull low device or low level hold device Description The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting Enables all of the pull low and Disables all of the pull X4 1 disables the low level hold devices X4 0 low and enables the low level hold devices OPC Rx Function VOC lt Rx Description The content of Rx is outputted to I OC port IPC Rx Function Rx AC VOC Description The data of I OC port is loaded to AC and data memory Rx 101 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SPD X Function Defines the input output mode of each pin for IOD port and enables disables the pull low device Description Sets the I O mode and turns on off the pull low device The meaning of each bit of X X4 X3 X2 X1 X0 is shown below X4 1 Enable the pull low X4 0 Disable the pull low a device on bul device on IOD1 IOD4 IOD1 IOD4 simultaneously simultaneously X3 1 IOD4 as output X3 0 IOD4 as input mode npu mode mode mode O uu OPD Rx Function VOD lt Rx Description The content of Rx is outputted to I OD port IPD Rx Function Rx AC Description The data of I OD port is loaded to AC and data memory Rx SPKX X Function Sets Key matrix scanning output state Description When SEG1 16 is are used for LCD d
27. IOD pins as output the OPD instruction must be executed to output the data to those output latches This will prevent the chattering signal when the IOD pins change to output mode IOD port had built in pull low device for each pin and that is selected by mask option To enable or disable this device by executing SPD instruction When the IOD pin has been defined as the output mode the pull low device will be disabled MASK OPTION table Pull low function option 75 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual bit0 Initial clear SPD Control 1 Data Bus D d C O edge dectect amp F chattering J D o a 4 o Control 2 IPD OPD This figure shows the organization of IOD port Note M O is mask option Note If the input level is in the floating state a large current straightthrough current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 3 5 4 1 Chattering Prevention Function and Halt Release The port IOD is capable of preventing high low chattering of the switch signal applied on IOD1 to IOD4 pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOD port are defined as output the signals applied to the output pins wi
28. O 3 ACn AC B omplement of content of Accumulator CF Cary Flag ddress of program or control data Zero Flag dress X of data RAM Watch Dog Timer Enable Flag it n content of Rx 7 segment decoder for LCD ddress Y of working register System clock for instruction ddress of data RAM specified by HL nterrupt Enable Flag ck up Flag HALT Release Flag eneric Index address register HALT Release Enable Flag ntent of generic Index address register Address of LCD PLA Latch ntent of lowest nibble Index register STOP Release Enable Flag ontent of middle nibble Index register Start Condition Flag ontent of highest nibble Index register Clock Source of Chattering prevention ckt ddress of Table ROM Clock Source of Frequency Generator igh Nibble content of Table ROM Switch Enable Flag ow Nibble content of Table ROM Frequency Generator setting Value imer Overflow Release Flag Clock Source Flag lock Source of Timer P Program Page re Divider RFC Overflow Flag ontent of stack Resistor to Frequency counter imer 1 Bit data of Resistor to Frequency counter imer 2 it content of Table ROM specified by HL gt Rx Rxn Ry R HL BCF HL HL L H U T HL H T HL L T HL TMR Ctm PDV STACK TM1 TM2 ojo 9 d Symbol ACn AOB xX Rx Pn Hy BCF HL QL QU T HL H T HL L T HL TMR Ctm PDV STACK
29. T D Es 2 4 4 3 2 2 4 2 0 500KHz 1 2V 1 5V 550KHz 650KHz 750KHz 2 4V 5 0V 400KHz 500KHz 600KHz 8 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual ELECTRICAL CHARACTERISTICS at 1 VDD1 1 2V A9 at 2 VDD2 2 4V Li at 3 VDD2 4V Ext V Input Resistance Symb L Level Hold Tr IOC 1 Rilh2 100 Rilh3 V V V IOC Pull Down Tr Rmad1 Rmad2 Rmad3 INT Pull up Tr Rintu1 Rintu2 Rintu3 i i i i VDD1 1 i i VDD2 3 i i i V VDD2 2 INT Pull Down Tr Rintd1 Vi GND 1 Rintd2 Vi GND 2 Rintd3 Vi GND 3 100 250 500 i RES Pull Down R Rres1 10 VDD1 1 VDD2 2 Rres3 Vi GND or VDD2 3 DC Output Characteristics Typ Unit bal hal 200uUA 1 COM5 6 SEG1 40 loh 3mA 3 25 30 35 V Output L 03 06 09 V Voltage Segment Driver Output Characteristics Static Display Mode Output H Vol2d Vol3d Vohle Voh2e 9 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual COM n V Output L Voltage 1 2 Bias Display Mode Output H Voh12f loh 1uA 1 2 Voltage Voh3f loh 1uA 3 SEG n Output L Voltage Output H Montano TO Ee an Voltage COM n Output M lol h 1 0UA 1 2 Voltage loV h 1 0UA 3 1 3 Bias display Mode Output H Voh12h Voltage Voh3h loh 1uA 3 1 h h oh 1uA 1 2 u T Voltage lol h 1 0UA 3 M2 od loV h 1 0UA 1 2 loV h 10UA 3 O
30. Timer2 Value Enable HEF6 Enable HEF5 Enable HEF4 Enable HEF3 Enable HEF2 Enable HEF1 Enable IEF6 Enable IEF5 Enable IEF4 Enable IEF3 Enable IEF2 Enable IEF1 Enable IEFO Reset PH15 11 Reset HRF6 0 Enable Cx Control Enable TM2 Control Enable Counter ENX Enable RH Output EHM Enable RT Output ETP Enable RR Output ERR Enable SRF7 SRF7 KEY_S Enable SRF5 SRF5 INT tenx technology inc Rev 1 2 2003 7 31 Instruction Machine Code SPKX 110 1110 0000 0000 110 1110 1000 0000 10 1111 XXXX XXX 111 0000 OXXX 111 0001 0000 0000 1111 0010 XXXX XXXX mm P OU O 10 gu Tr HL X7 5 4 000 X7 5 4 001 X7 5 4 010 X7 5 4 10X X7 5 4 110 X7 5 4 111 1111 0100 0000 0000 1111 0100 1X0X XXX O H Il parte X2 1 0 001 X2 1 0 010 100 1111 0101 000X X000 1111 0101 100X XXX 2 0 1111 0101 101X XXX X3 0 1111 0101 110X XXX a 0 1111 0101 111X XXX zi 0 1111 0110 X00X XXX X2 X1 X00 gt 138 Enable SEF3 Set A4 1 Pull Low Set B4 1 Pull Low TM8705 Users Manual Enable SRF3 SRF3 if XI 04 DET 0 aa aS Y_S release by scanning PUE KEY S release by normal key scanning Set one of KO1 16 1 by X3 0 Set all 1 Set all Hi z Set eight of KO1 16 1 by X3 1 gt KO9 16 Set four of KO1 16 1 by X3 2 X3 2 00 gt KO1 4 X3 2 01 gt
31. Unit L 32 2 11 Hexadecimal Convert to Decimal 32 OSSA ULL mee 34 2 13 Timer 2 IMR2 u u 36 2 14 Status Register STS 41 2 15 Control Register CT LL eurer l nu 46 2 16 HALT Nro MET P L ainai 50 2 17 Heavy Load Function n etna tatnen tren 50 2 18 STOP IE BIO aiio bites bison ttd awak E deese 52 l tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 19 Back UP FUNGCHON aaa shasqa sasaqa waq ssssalawaakasassaqusuQuaqua 53 CHAPTER 3 Control Function U 55 3 1 Interrupt Function E 55 3 2 z u u u o aysan 59 3 3 Clock Generator Frequency Generator and Predivider 63 3 4 Buzzer 66 3 5 Input Output Ports 68 96 ELPanel DIVE MT 77 3 7 External INT PN eto 79 3 8 Resistor to Frequency Converter RFO sse 80 3 9 Key Matrix Scanning n nsn 84 CHAPTER 4 LCD Driver Outpult1 J J J J 89 4 1 LCD Lighting System in TM8705
32. error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 The 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 13 2 RE LOAD OPERATION TMR2 also provides the re load function is the same as TMR1 The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 2 13 3 TIMER 2 TMR2 RESISTOR TO FREQUENCY CONVERTER RFC TMR2 also controlled the operation of RFC function 38 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual TMR2 will set TENX flag to 1 to enable the RFC counter once the TMR2 underflows the TENX flag will be reset to 0 automatically In this case Timer 2 could set an accurate time period without setting a value error like the other operations of TMR1 and TMR2 Refer to 2 16 for detailed information on controlling the RFC counter The following figure shows the operating timing of TMR 2 in RFC mode Clock source of dM Ll LIL Timer 2 TM2X X C T _ Timer2 7 HRF4 gm be E TENX ammi TMR2 also provides the re load function when
33. flag 0 IEFO is set to 1 interrupt O is accepted and the instruction at address 14H is executed automatically 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal generated in scanning interval If the interrupt enable flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 3 1 1 2 Internal interrupt factor The internal interrupt factor involves the use of timer 1 TMR1 timer 2 TMR2 RFC counter and the pre divider 1 Timer1 2 TMR1 2 interrupt request An interrupt request signal HRF1 4 is delivered when timer1 2 TMR1 2 underflows In this case if the interrupt enable flag 1 4 IEF1 4 is set interrupt 1 4 is accepted and the instruction at address 18H 20H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set interrupt 3 is accepted and the instruction at address 1CH is executed automatically 3 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is delivered when the p falling edge applied on CX pin and 16 bit counter stops to operate In this case if the interrupt enable flag6 IEF6 is set interrupt 6 is accepted and the instruction at address 28H is executed automatically 3 1 2 INTERRUPT PRIORIT
34. flag 4 HEF4 is set beforehand To reset the start condition flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 or the SHE instruction must be used to reset the halt release enable flag 4 HEF4 3 Start condition flag 9 SCF9 SCF9 is set when a finish signal from mode 3 of RFC function causes the halt release request flag 6 HRF6 to be outputted and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the start condition flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 or the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 Halt release Halt release Halt release caused by RFC caused by TMR2 caused by SKI counter finish underflow underflow Read only Read only Read only Read only 2 14 5 STATUS REGISTER 4 STS4 Status register 4 STS4 consists of 3 flags 1 System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generat
35. index address register HL specifies the address of the data memory and all address space from 00H to 17FH can be accessed The 16 specified addresses 70H to 7FH in the direct addressing memory are also used as 16 working registers The function of working register will be described in detail in section 2 6 00H DATA RAM Working Register 7FH Direct Address Access Index Address Access 1FFH This figure shows the Data Memory RAM and Working Register Organization 2 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory RAM are not only used as general purpose data memory but also as the working register WR The following will introduce the general usage of working registers 1 Be used to perform operations on the contents of the working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 Be transferred the data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 31 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 3 Decode or directly transfer the contents of the working register and output to the LCD PLA circuit Such as LCT LCB LCP 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and
36. load function and the counting is completed 7th Ls du Dar ih us count count count count In this example S W enters the halt mode to wait for the underflow of TMR1 LDS 0 0 initiate the underflow counting register PLC 2 SHE 2 enable the HALT release caused by TMR1 TMSX 34h initiate the TMR1 value 52 and clock source is 9 SF 80h enable the re load function RE_LOAD HALT 0 increase the underflow counter PLC 2 clear HRF1 JB3 END TM1 if the TMR1 underflow counter is equal to 8 exit subroutine JMP RE LOAD END TM 1 RF 80h disable the re load function 2 13 TIMER 2 TMR2 The following figure shows the TMR2 organization 36 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual TM2 instruction IEF Initial reset TM2 Interrupt SCF Operand Data X5 X0 TM2 instruction 6 Halt release Operand Data X8 X7 X6 TM2 instruction Interrupt accept signal PLC 10hinstruction Initial reset TENX Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 2 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TM2 or TM2X instruction Once the TMR2 counts down to 3Fh it stops counting then generates an underflow signal and the halt release request flag 4 HRF4 will be set to 1 When HRF4 1 and the TMR2 interrupt enabler IEF4 is setto 1 th
37. load function which can extend any time interval greater than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again During this operation the program must use the halt release request flag or interrupt to check the wanted counting value 35 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual It is necessary to execute the TMS or TMSX instruction to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled e Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the TMR1 will stop operating immediately after the re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the initiate count down value of TMR1 to 52 and start counting then enable the TMR1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs dear the HRF1 flag by PLC instruction After halt release or interrupt occurs 8 times disable the re
38. matrix scanning input KI1 4 is in used the 0 signal applied to all these pins that had be set as input mode in the same time KI1 4 pins need to wait scanning time reset signal is delivered MASK OPTION table IOC or KI pins are used as key reset Mask Option name IOC1 KI1 FOR KEY RESET 1 IOC2 KI2 FOR KEY RESET USE IOC3 KI3 FOR KEY RESET 1 USE 4 4 FOR KEY RESET 1 USE IOC or KI pins aren t used as key reset IOC4 KI4 FOR KEY RESET The following figure shows the key reset organization FS t 1 IOC1K1 F VDD Key Scanning latch circuit loca Kl2 a E VDD Key Scanning latch circuit IOC4 KI4 mA E VDD 3 2 4 WATCHDOG RESET The timer is used to detect unexpected execution sequence caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider IOCS KI3 62 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual When the watchdog timer overflows it generates a reset signal to reset TM8705 and most of the functions in TM8705 will be initiated except for the watchdog timer which is still active WDF flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watchdog timer organization Edge detector WDRST to reset TM8705 Reset pin POR RF 10H During initial res
39. or 50 5 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary that the MSB MSC or MCX instruction is executed in order to test the halt release signal and that the PLC instruction is then executed to reset the halt release signal HRF Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 2 17 HEAVY LOAD FUNCTION When heavy loading lamp light up motor start etc causes a temporary voltage drop on supply voltage the heavy loading function set BCF 1 prevents TM8705 from malfunctioning especially where a battery with high internal impedance such as Li battery or alkali battery is used During back up mode the 32 768KHz Crystal oscillator will add an extra buffer in parallel and switch the internal power BAK from VDD1 to VDD2 Li power option only In this condition all of the functions in TM8705 will work under VDD voltage range this will cause TM8705 to get better noise immunity For shorten the start up time of 32 768KHz Crystal oscillator TM8705 will set the BCF to 1 during reset cycle and reset BCF to 0 after reset cycle automatically in Ag and Li power mode option In EXT V power mode option however BCF is set to 1 by default setting and can not be reset to 0 and BCF will be reset to 0 by default setting during normal operatio
40. organization of Key matrix scanning input port Each one of SKI1 4 change to High will set HRF5 to 1 If HEF5 had been set to 1 beforehand this will cause SCF7 to be set and release the HALT mode After the key scanning cycle the states of SKI1 4 will be latched and executing IPC instruction could store these states into data RAM Executing PLC 20h instruction to clear HRF5 flag Since the key matrix scanning function shared the timing of LCD waveform so the scanning frequency is corresponding to LCD frame frequency and LCD duty cycle The formula for key matrix scanning frequency is shown below key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for key matrix is 320Hz 32 x 5 x 2 86 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 Kl4 k i PLC 20h ey scanning ETE enable signal IPC nitial Reset Interrupt 5 request This figure shows the organization of Key matrix scanning input Example SPC Ofh Disable all the pull down device on internal IOC port Set all of the IOC pins as output mode SPKX 10h Generate HALT released request when key depressed Scanning all columns simultaneous in each cycle PLC 20h Clear HRF5 SHE 20h Set HEF5 HALT wait for the halt release caused by key matrix MCX 10h Check SCF8 SKI JBO ski r
41. reset to 0 X7 1 Disables the re load function of timer 1 X6 5 3 is reserved Sets flag Description of each flag X3 1 Enable the strong pull low device on INT pin X2 1 Turn off the LCD display temporarily X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 Resets flag Description of each flag X3 1 Disable the strong pull low device on INT pin 1 Turn on the LCD display X1 1 Resets the DED flag Refer to 2 12 3 for detail XO 1 Disables the re load function of timer 2 Pulse control The pulse corresponding to the data specified by X is generated 1 Halt release request flag HRFO caused by the signal at I O port C is reset 132 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 X2 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset X3 1 Halt release request flag HRF3 caused by overflow from the predivider is reset X4 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 X5 1 Halt release request flag HRF5 caused by the signal change to L on KI1 4 in scanning interval is reset X6 1 Halt release request flag HRF6 caused by overflow from the RFC coun
42. to DBUSH without passing through the data decoder Table 2 2 The mapping table of LCP and LCD instructions 93 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH LCP R0 Rx R2 Rx ACO ACI AC2 AC3 T HLO T HL1 wa T HL4 T HL5 T HL6 T HL7 T HL2 There are 8 data decoder outputs of DBUSA to DBUSH and 32 LO to L4 decoder outputs of PSTB Oh to PSTB 3Fh The input data and clock signal of the latch circuit are DBUS A to DBUSH and PSTB Oh to PSTB 1Fh respectively Each segment pin has 8 latches corresponding to COM1 8 The segment PLA performs the function of combining DBUSA to DBUSH inputs to each latch and strobe PSTB Oh to PSTB3Fh is selected freely by mask option Of 512 signals obtainable by combining DBUSA to DBUSH and PSTB Oh to PSTB 3Fh any 320 corresponding to the number of latch circuits incorporated in the hardware signals can be selected by programming and the above mentioned segment PLA Table 2 7 shows the PSTB Oh to PSTB 3Fh signals concretely Table 2 3 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction strobe signal for Strobe in LCT LCB LCP LCD LCD latch instructions The values of Lz in LCT Lz Q PSI 0H jH 5 PSI PSTB C 3H PSTBA 484 PSTB 5H REN
43. to 4 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output the output data on this port will not be affected while the program entered stop mode or LCD turn off mode 91 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual VDD L P SEG Figure 5 1 CMOS Output Type Figure 5 2 P Open Drain Output Type Only unused COM and SEG pad could be defined as DC output pin The COM pad sequence for LCD driver could not be interrupted when defined the COM pads as the DC output port For example when the LCD lighting system is specified as 1 5 duty the used COM pad for LCD driver must be COM1 COM5 Only COM6 pad could be defined as DC output port refer to section 4 3 4 4 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION Explained below is how the LCD driver section operates when the instructions are executed 3 memory x Multiplexer RAM 5 LCD output D Strobe data Decoder of tion P related strobe L0 to L4 Ed instruction Figure 5 3 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units e Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LOtoL4 decoder to decode the Lz specified data in the LCD related instructions which specifies the strobe of the latch
44. 12 CF Clocks 9 This figure shows the System Clock Switches from Slow to Fast After executing SLOW instruction the system clock generator will hold 2 XT clocks and then switches XT clock to BCLK 22 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual CF Fast clock stops operating clock clock SLOW BCLK This figure shows the System Clock Switches from Fast to Slow 2 2 3 2 Single Clock MASK OPTION table For Fast clock oscillator only CLOCK SOURCE 1 FAST ONLY For slow clock oscillator only Mask Option name CLOCK SOURCE 2 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option The backup flag BCF will be set to 1 automatically before the program enters the stop mode Halt Halt Halt mode released OSC active Reset Reset release Stop Release Normal mode OSC active Stop Stop mode OSC stop Reset mode Power on reset OSC active Reset Reset pin reset Watchdog timer reset Key reset This figure shows the State Diagram of Single Clock Option 23 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry PHO as inp
45. 35 pins and selected by mask option MASK OPTION table 3 Kl2 84 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SEG34 IOC3 KI3 3 KI3 SEG35 lIOC4 KI4 3 Kl The typical application circuit of key matrix scanning is shown below K16 K15 Ki4 K13 K12 Kii K10 K9 K8 K7 K6 K5 K4 os ttt ttt 55 t Executing SPKX X SPK Rx and SPK HL instructions could set the scanning type of key matrix The bit pattern of these 3 instructions is shown below s e utete iao SPKX X Em SPK Rx RX3 0 0 SPK QHL T HL7 usu e eus ER x 5 The following description shows the bit definitions in the operand of SPKX instruction Xe 0 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after the key depressed on the key matrix and then set SCF7 to 1 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle no matter the key is depressed or not and then set SCF7 to 1 X7X5X4 000 in this setting each scanning cycle only check one specified column K1 K16 on key matrix The specified column is defined by the setting of X3 Xo X3 Xo 0000 active K1 column X3 Xo 0001 active K2 column X3 Xo 1110 active K15 column Xa Xo 1111 active K16 column X7X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cy
46. 8Hz The LCD alternating frequency in duplex 1 2 duty type OHZ LCD not used The LCD alternating frequency in 1 3 duty type The LCD alternating in 1 4 duty type The LCD alternating frequency in 1 5 duty type The LCD alternating frequency in 1 6 duty type 1 SLOW Ys frame frequency 5 FAST LCD frame frequency 2 O P 0Hz LCD not used 90 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments LCD Lighting Maximum Number of ping LOD Segments i bias 1 2 Connect VDD3 to VDD2 EI 1 3duty Connect VDD3 to VDD2 1 2bias 1 4duty Connect VDD3 to VDD2 1 2bias 1 5dut Connect VDD3 to VDD2 1 2bias 1 6duty Connect VDD3 to VDD2 p pe U3bisi 3duy 123 0 0 O U3biast Aduy 164 O U3biast bduy 205 9 O tU 3biast 6 duy 246 When choosing the LCD frame frequency it is recommended to choice the frequency that higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 4 2 DC OUTPUT TM8705 permits LCD driver output pins COM5 COM6 and SEG1 SEG40 to be defined as CMOS type DC output or P open drain DC output ports by mask option In this case it is possible to use some LCD driver output pins for DC output and the rest LCD driver output pins for LCD driver Refer
47. A RE EAE BBR Z3 o tenx technology inc 1M5 705 4 Bit Micro Controller with LCD Driver User s Manual tenx technology inc tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual CONTENTS CHAPTER 1 General Description J J J 3 1 1 General Description nnna 3 1e2 y uu 4 T S lees MR p 4 1 4 Block Diagram E 5 1 5 sr ocio fc DR m 5 1 6 Pad Coordinate 6 Ter Pin ua 6 1 8 Characterization nenne 7 eas etes 11 CHAPTER 2 TM8705 Internal System Architecture 12 Supply s m Se er ee 12 2 2 uem tC en tee eee er eee ee cbe a 18 2 3 aieo c iei gi t TT Y 26 2 4 Program Table Memory 27 2 5 Index Address Register HL Q 29 2 6 Stack Register STACK l u 30 2 Data M mory RAM u aR ace ior asua 31 2 8 Working Register WR u 31 2 9 Acc um lator 92 2 10 ALU Arithmetic and Logic
48. Bit 2 Zero AC 0 flag Bit 1 No Use Bit 0 No Use 5 3 OPERATION INSTRUCTIONS INC Rx Function Description INC HL Function Rx AC Rx 1 Add 1 to the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected HL AC R HL 1 107 tenx technology inc Rev 1 2 2003 7 31 Description INC HL Function Description DEC Rx Function Description DEC HL Function Description DEC Function Description ADC Rx Function Description ADC HL Function Description TM8705 Users Manual Add 1 to the content of HL the result is loaded to data memory HL and AC Carry flag CF will be affected HL indicates an index address of data memory HL AC R HL 1 HL HL 1 Add 1 to the content of HL the result is loaded to data memory HL and AC The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected HL indicates an index address of data memory Rx AC Rx 1 Substrate 1 from the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected R HL AC R HL 1 Substrate 1 from the content of HL the result is loaded to data memory HL and AC Carry flag CF will be affected OHL indicates an index address of data memory R HL AC R Q
49. Bit pattern Setting X421 Enable the pull low device on X4 0 Disable the pull low 4 simultaneously device on IOA1 1OA4 simultaneously IOA4 as output mode X3 0 IOA4 as input mode IOA3 as output mode X2 0 3 as input mode IOA2 as output mode X1 0 2 as input mode X0 1 IOA1 as output mode X0 0 OA1 as input mode OPA Rx Function VOA lt Rx Description The content of Rx is outputted to I OA port OPAS Rx D Function 2 Rx IOA3 D IOA4 lt pulse Description Content of Rx is outputted to IOA port D is outputted to IOA3 pulse is outputted to IOA4 D 2 0or 1 IPA Rx Function Rx AC I OA Description The data of I OA port is loaded to AC and data memory Rx 100 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SPB X Function Defines the input output mode of each pin for IOB port and enables disables the pull low device Description Sets the I O mode and turns on off the pull low device The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Bit pattern X4 1 Enable the pull low device on X4 0 Disable the pull low IOB1 IOBA simultaneously device on IOB1 IOB4 simultaneously X3 0 X2 0 X1 0 X0 0 OPB Rx Function VOB Rx Description The contents of Rx are outputted to I OB port IPB Rx Function Rx AC I OB Description The data of I OB port is loaded to AC and data memory Rx SPC X
50. Clock switch System clock circuit generator circuit XT Clock CF Clock Single clock option Dual clock option The system clock generator provided the necessary clocks for execution of instruction The pre divider generated several clocks with different frequencies for the usage of LCD driver frequency generator etc The following table shown the clock sources of system clock generator and pre divider in different conditions BCLK ssaesconr opio clock only option XT clock XT clock fast clock only option CF clock CF clock Initial state dual clock XT clock XT clock option Halt mode dual clock option XT clock XT clock Slow mode dual clock XT clock XT clock option Fast mode dual clock XT clock CF clock option 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by mask option or it will be active all the time after the initial reset In stop mode the oscillator will be stopped There are 2 type oscillators can be used in slow clock oscillator selected by mask option 18 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 2 1 1 External 32 768KHz Crystal oscillator MASK OPTION table Mask Option name SLOW CLOCK TYPE FOR SLOW ONLY OR D
51. D port PHO X2 X1 X0 00 clock of IOC port PHO 1 1 Chattering prevention X4 X3 10 Chattering prevention X2 X1 X0 01 clock of IOD port PH8 X2 X1 X0 01 clock of IOC port PH8 0 0 X4 X3 01 Chattering prevention X4 X3 10 Chattering prevention X2 X1 X0 10 clock of IOD port PH6 X2 X1 X0 10 clock of IOC port PH6 0 0 X5 is reserved FRQ D Rx Function Frequency generator D Rx AC Description Loads the content of AC and data memory specified by Rx and D D1 DO to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern of preset letter N Pas Programmi Bit7 Bit Bit5 Bit4 Bit3 Bit2 Bit1 Bit 0 ng divider Di DO J 0 0 dwy 1 day 1 0 lady OE FRQ D HL Function Frequency generator D T HL Description Loads the content of Table ROM specified by HL and D D1 D0 to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting ThebitpatemofpresetleterN Programming divider Note TO T7 represents the data of table ROM Preset Letter D Duty Cycle Dt DO Jj 0 1 4 duty 1 duy 128 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual o 1 0 1 2 dut 1 1 duty FRQX D X Function F
52. DAS HL Function Description DAS HL Function Description AC BCD AC Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC Rx BCD AC Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC HL BCD AC Converts the content of AC to binary format and then restores to AC and data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC HL BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected 125 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual AC data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 0 lt ACK9 6 lt AC lt F AC AC A 5 8 JUMP INSTRUCTIONS JBO X Function Description JB1 X
53. DN HL 0010 1001 1100 0000 AC R HL R HL AC UU Jon eur AND AND AC AND 0010 1010 1000 0000 lt R HL AND AC 0010 1010 1100 0000 lt R HL AND AC 0010 1011 1100 0000 AC R HL RGHL AND AC P fen canta GRE HL 0010 1100 1100 0000 AC R HL EOR AC HL HL 1 0010 1101 OX XOX AC Rx Rx EOR AC HL 0010 1101 1000 0000 AC R HL R HL EOR AC AC HL 134 tenx technology inc Rev 1 2 2003 7 31 C C A AC AC AND AND HL AND HL EOR SUB SUB dl E PDN PN ASD incall sm BNE EOR R 1 ES m O TM8705 Users Manual Machine Code Flag Remark re 0010 THO ORK XX c Fo OR AG 00 A AG H T 101110 1000000 JAC J e R HL OR 0010 1110 1000 0000 0010 1110 1100 0000 R HL OR AC L QHL 1 ACR O ib ORO XOX ACR AC R HL e R HL OR AC D en Cente Ry D B CF D D D D RyD jon 100 mow c RyD RyD RyD yD D D hi 3 8 8 ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI lt HL HL HL HL D D T lt TIT D D D B CF T lt T lt lt lt T T lt y B 1 D D D B 1 D D
54. Description SR1 Rx Function Description AC Rx e R HL HL HL 1 The content of data memory specified by HL is loaded to AC and data memory specified by Rx The content of index register HL will be increment automatically after executing this instruction Rx n ACn Rx n 1 AC n 1 Rx 3 AC3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC Content of Rx Rx n ACn Rx n 1 AC n 1 Rx 3 AC3 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC Rx3 Rx0 106 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SLO Rx Function Description SL1 Rx Function Description MRA Rx Function Description MAF Rx Function Description Rx n ACn Rx n 1 ACn 1 Rx 0 ACO 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC Bits Bit2 Biti Bito After Rd Ro Rx n ACn Rx n 1 AC n 1 Rx 0 ACO lt 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC Bit Bit Bito CF lt Rx 8 Bit3 of the content of Rx is loaded to carry flag CF AC Rx CF Zero flag The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 CF
55. F 9 build up the RR network and enable the counter HALT SRF 1 stop the counter when TMR1 underflows MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h MSD 20h JB2 CNT1_OF check the overflow flag of counter JMP DATA_ACCEPT CNT1_OF DEC 2 decrease the TM1 value LDS 20h 0 SBC 1 JZ CHG_CLK_RANGE change the clock source of TMR1 PLC 1 clear the halt release request flag of TMR1 JMP RE_CNT 3 8 3 Enable Disable the Counter by Timer 2 TMR2 will control the operation of the counter in this mode When the counter is controlled by SRF 18 instruction the counter will start to operate until TMR2 is enabled and the first falling edge of the clock source gets into TMR2 When the TMR2 underflow occurs the counter will be disabled and will stop counting the CX clock at the same time This mode can set an accurate time period with which to count the clock numbers on the CX pin For a detailed description of the operation of TMR2 please refer to 2 12 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically 82 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SRF 18h SRF 02h SRF control Pa Counter active L4 we Cim QN Gk GS Gunes my 3Fh Gontentof aN a i Lm the counter Ko 2 5 ANA Na e Halt release request counter starts Counting stops caused to count by the Timer 2 underflow This figure shows the timin
56. F1 SCF3 to 1 Because the input signal of IOC IOD port were ORed so it is necessary to keep the unchanged input signals at 0 state and only one of the input signal could change state SEF3 SCF3 SCA 8h Interrupt accept 2 15 1 2 The Setting for Stop Mode If SRF4 SRF3 and SEFA SEF3 are set the stop mode will be released to set the SCF1 SCF3 when a high level signal is applied to one of the input mode pins of IOC IOD port and the other pins stay in O state After the stop mode is released TM8705 enters the halt condition The high level signal must hold for a while to cause the chattering prevention circuitry of IOC IOD port to detect this signal and then set SCF1 SCF3 to release the halt mode or the chip will return to the stop mode again 2 15 1 3 Interrupt for 1 The control register 1 CTL1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC IOD port will deliver the SCF1 SCF3 when SEFA SEF3 has been set to 1 by executing SCA instruction Once the SCF1 SCF3 is delivered the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag O IEFO is set to 1 by executing SIE instruction the interrupt request flag 0 interrupt 0 will be delivered to interrupt the program If the interrupt 0 is accepted by SEFA SEF3 and IEFO the interrupt 0 request to the next sign
57. Function Description JB2 X Function Description JB3 X Function Description JNZ X Function Description JNC X Function Description Program counter jumps to X in current page if ACO 1 If bitO of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to X in current page if AC1 1 If bit of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X in current page if AC2 1 If bit2 of AC is 1 jump occurs If O the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to X in current page if AC3 1 If bit3 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to X in current page if AC 0 If the content of AC is not O jump occurs If 0 the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to X in current page if CF 0 If the content of CF is 0 jump occurs If 1 the PC increases by 1 The range of X is from OOOH to 7FFH 126 tenx technology inc Rev 1 2 2003 7 31 JZ X Function Description JC X Function Description JMP P X Function Description BFFH CALL P X Function Description BFFH RTS Function Description TM8705 Users Manual Program counter jumps to X in current page i
58. G35 IOCA KIM 72 50 1627 50 602 50 SEG36 IOD1 72 50 1627 50 717 50 SEG37 IOD2 72 50 1627 50 832 50 SEG38 IOD3 72 50 1627 50 947 50 SEG39 IOD4 72 50 1627 50 1062 50 SEG40 72 50 1627 50 1177 50 RESET 72 50 1627 50 1292 50 INT 72 50 1627 50 1407 50 TEST 72 50 1 7 PIN DESCRIPTION BAK Positive Back up voltage power mode connect a o tu capactorio anD VDD1 2 3 LCD supply voltage and positive supply voltage In Ag Mode connect positive power to VDD1 Li or ExtV power mode connect positive power to VDD2 RESET _ Input pin for external reset request signal built in internal pull down resistor INT Input pin for external INT request signal Falling edge or rising edge triggered is defined by mask option Internal pull down or pull up resistor is defined by mask option TEST _ Test signal input pin 6 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Switching pins for supply the LCD driving voltage to the VDD1 2 3 pins Connect the CUP1 and CUP2 pins with non polarized electrolytic capacitors when chip operated in 1 2 or 1 3 bias mode Inno BIAS mode application leave these pins opened Time base counter frequency clock specified LCD alternating frequency Alarm signal frequency or system clock oscillation The usage of 32KHz Crystal oscillator or external RC oscillator is defined by mask option E System clock oscillation for FAST clock
59. HL 1 HL HL 1 Substrate 1 from the content of HL the result is loaded to data memory HL and AC The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected OHL indicates an index address of data memory AC Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC Carry flag CF will be affected AC e HL AC CF The contents of QHL AC and CF are binary added the result is loaded to AC Carry flag CF will be affected 108 tenx technology inc Rev 1 2 2003 7 31 ADC HL Function Description ADC Rx Function Description ADC HL Function Description ADC Function Description SBC Rx Function Description SBC HL Function Description TM8705 Users Manual HL indicates an index address of data memory AC e HL AC CF HL HL 1 The contents of HL AC and CF are binary added the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction Carry flag CF will be affected HL indicates an index address of data memory AC Rx Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC HL HL AC CF The contents of HL AC and CF are binary added the result is loa
60. IC INSTRUCTIONS DAA Function AC e BCD AC Description Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected DAA Rx Function AC Rx BCD AC Description Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected DAA HL Function AC HL BCD AC Description Converts the content of AC to binary format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected 124 tenx technology inc Rev 1 2 2003 7 31 DAA HL Function Description TM8705 Users Manual AC HL BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and data memory specified by HL The content of index register HL will be increment automatically after executing this instruction When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected execution execution execution execution 3 AC AC 6 DAS Function Description DAS Rx Function Description
61. L light driver ELC ELP Muxed with SEG28 SEG29 3 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 9 Built in Alarm clock or single tone melody generator BZB BZ Muxed with SEG30 SEG31 10 Built in resistance to frequency converter eCX RR RT RH Muxed with SEG24 SEG27 11 Built in key matrix scanning function eK1 K16 Shared with SEG1 SEG16 12 KI1 KI4 Muxed with SEG32 SEG35 13 Two 6 bit programmable timer with programmable clock source 14 Watch dog timer 15 Built in Voltage doubler halver tripler charge pump circuit 16 Dual clock operation slow clock oscillation can be defined as X tal or external RC type oscillator by mask option fast clock oscillation can be defined as 3 58MHz ceramic resonator internal R or external R type oscillator by mask option 17 HALT function 18 STOP function 1 3 APPLICATION m Timer Calendar Calculator Thermometer 4 tenx technology inc Rev 1 2 2003 7 31 1 4 BLOCK DIAGRAM B1 4 ELC ELP BZB BZ A1 4 CX RR RT RH panog C1 4 KI1 4 D1 4 TM8705 Users Manual COM1 6 s SEG1 40 VDD1 3 nen Dag LCD DRIVER SEGMENT PLA B PORT EL DRIVER A PORT C PORT ALARM RFC KEY IN TLE 4 BITS DATA BUS Lx E T L FREQUENCY INDEX ROM ALU GENERATOR 73 256 16 N X 8 BITS L l DIVIDER T 1 LI PROGRAM ROM 6 BITS PRESET STACK 12 BITS PROGRAM E 1024 128N
62. Logic Unit data transfer between the accumulator and other registers or data memory can be performed 2 10 ALU Arithmetic and Logic Unit This is a circuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift SRO SR1 SLO SL1 Decision JBO JB1 JB2 JB3 JC JNC JZ and JNZ BCD operation DAA DAS 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format is another number format for TM8705 When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0s AC 9 AZACEF AC 6 0 ACS3 AC AC 6 Example 1 LDS 10h 9 Load immediate data 9 to data memory address 10H
63. M value 52 and clock source is 9 SF2 3h enable the re load function and set DED flag to 1 RE LOAD HALT increase the underflow counter 39 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual PLC 10h clear HRF4 LDS 20h 7 SUB 0 when halt is released for the 7 time reset DED flag JNZ NOT RESET DED RF2 2 reset DED flag NOT_RESET_DED subroutine 2 LDA 0 store underflow counter to AC JB3 END TM2 if the TM2 underflow counter is equal to 8 exit this JMP RE LOAD RF2 1 disable the re load function ist x po e ha 7th 8th l count d ant is zu deo count count na P lt count sunt TM2 This figure shows the operating timing of TMR2 re load function for RFC 40 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start IEFO Chattering PLCO SIE 1h prevention output of IOC SCF 1 PLC 1h HRFO Interrupt 0 SEF4 R Initial reset prevention SCA 10h Interrupt accept gt Halt release request output of IOD SEF3 SCF3 IEF1 Chattering SCF2 SCA 8h SIE 2h D 5 Timer Ww Interrupt 1 HEF1 SHE 2h IEF2 Signal Interrupt 2 A LJ on INT pin HEF2 SHE 4h IEF3 2 Interrupt 3 SIE 8h Predivide 9 overflorw a
64. MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX SEG25 IOA2 RR SEG26 IOA3 RT SEG27 IOA4 RH In initial reset cycle the IOA port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined as the input mode will still remain the input mode Executing IPA instructions may store the signals applied to the IO pins into the specified data memory When the IO pins are defined as the output mode executing IPA instruction will store the content that stored in the latch of the output pin into the specified data memory Before executing SPA instruction to define the I O pins as the output mode the OPA instruction must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changed IOA port had built in pull down resistor The pull low device for each pin is selected by mask option and executing SPA instruction to enable disable this device Pull low function option Mask Option name IOA PULL LOW RESISTOR 1 USE IOA PULL LOW RESISTOR 2 NO USE 68 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Initial clear SPA 1 Initial clear SPA 2 Initial clear SPA 8 This figure shows the organization of IOA port Not
65. OA1 SEG37 to IOA4 SEG40 respectively and selected by mask option MASK OPTION table SEG2MIOM CX CX SEG26 IOA3 RT SEG27 IOA4 RH 3 8 1 RC Oscillation Network The RFC circuitry may build up 3 RC oscillation networks through RR RT or RH and CX pins with external resistors Only one RC oscillation network may be active at a time When the oscillation network is built up executing SRF 1h SRF 2h SRF 4h instructions to enable RR RT RH networks respectively the clock will be generated by the oscillation network and transferred to the 16 bit counter through the CX pin It will then enable or disable the 16 bit counter in order to count the oscillation clock Build up the RC oscillation network 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins for RC networks respectively The RR RT RH pins will become of a tri state type when these networks are disabled 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and 16 bit counter The RC oscillation network will not operate if these instructions have not been executed and the RR RT RH pins output 0 state at this time To get a better oscillation clock from the CX pin activate the output pin for each RC network before the counter is enabled The RFC function provides 3 modes for the operatio
66. R 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Mask Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE 79 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual IEF2 Interrupt request HEF2 SCF2 Halt release request Mask option HRF 2 PLC 4h Initial clear pulse Interrupt 2 receive signal Mask option Open type Note For Ag battery power supply positive power is connected to VDD1 for anything other than Ag battery power supply it is connected to VDD2 This figure shows the INT Pin Configuration 3 8 Resister to Frequency Converter RFC The resistor to frequency converter RFC can compare two different sensors with the reference resister separately This figure shows the block diagram of RFC SRF 8h Controlled by Timer 2 SRF 18h SRF 28h CX pin signal interrupt request SCF9 counter over flow flag CX FREQ output from MRF1 4 i frequency generator to data memory Foie data D and AC 80 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual This RFC contains four external pins CX the oscillation Schemmit trigger input RR the reference resister output pin RT the temperature sensor output pin RH the humidity sensor output pin this can also be used as another temperature sensor or can even be left floating These CX RR RT and RH pins are MUXed with I
67. Rx Function Description MRF4 Rx Function Description TM8705 Users Manual Bit 1 RFC 5 Bit 0 RFC 4 Rx AC RFC 11 8 Loads the 3 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 11 Bit 2 RFC 10 Bit 1 RFC 9 Bit 0 RFC 8 Rx AC RFC 15 12 Loads the highest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 15 Bit 2 RFC 14 Bit 1 RFC 13 Bit 0 RFC 12 5 5 CPU CONTROL INSTRUCTIONS NOP Function Description HALT Function Description STOP Function Description no operation no operation Enters halt mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to port IOC SCF1 or IOD SCF3 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When an interrupt is accepted to release the halt mode the halt mode returns by executing the RTS instruction after completion of interrupt service Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 120 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 1 One of the signals on the input mode pin of IOD or IOC port is in H stat
68. UAL 1 Xtal When backup flag BCF is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time but this will increase the power consumption Therefore the backup flag should be reset unless required otherwise The following table shows the power consumption of Crystal oscillator in different condition __ Ag power option Li power option EXT V option BCF 1 BCF 0 reset reset 2 2 1 2 External RC oscillator MASK OPTION table Mask Option name SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 2 RC 19 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock is a multiple type oscillator mask option which provide a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer I O port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to system clock generator only When the dual clock option is selected by mask option this oscillator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock and the clock source for other functions will still come from XT clock Halt mode stop mode or SLOW instru
69. Y If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the 57 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual interrupt service routine is initiated all of the interrupt enable flags IEFO IEF6 are cleared and should be set with the next execution of the SIE instruction Refer to Table 3 1 Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been defined as input mode PLC 7Fh Clear all of the HRF flags SCA 10h enable the interrupt request of IOC SIE 7Fh enable all interrupt requests a ree all interrupts are requested simultaneously Interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 77h Enable the interrupt request except the predivider interrupt caused by the TM1 underflow occurs and interrupt service is concluded SIE 75h Enable the interrupt request except the predivider and TMR1 interrupt caused by the TM2 underflow occurs and interrupt service is concluded SIE 65h Enable the interrupt request except the predivider TMR1 and TMR2 Interrupt caused by the RFC counter overflow occurs and interrupt service is concluded SIE 25h Enable the interrupt request except the predivider TMR1 TMR2 and the RFC counter In
70. al clock source N 1 Hz 1 4 duty carrier out 1 3 duty carrier out 1 2 duty carrier out 1 1 duty carrier out 3 3 2 Melody Output The frequency generator may generate the frequency for melody usage When the frequency generator is used to generate the melody output the tone table is shown below The clock source is PHO i e 32 768 Hz 2 The duty cycle is 1 2 Duty D 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 is the frequency deviation The following table shows the note table for melody application N FREQ Ideal 260 063 261 626 0 60 292 571 309 132 3 38 gt mm O zBesncsvBos ne FREQ Ideal 96 69 4237 69 2957 0 73 4709 73 4162 0 7 6493 77 7817 0 1 7 8 9 0 7 82 331 87 1489 87 3071 0 1 92 565 0 109 960 110 000 131 072 130 813 1 1 oO OoO oj ojo eo k NI oo cO olo Oo olo N IN G co t gt T nm nm nm n n5 no5 n5 C9 C5 CO0 CO CO S T BR BR OT O1 OI O NI 00 O O P BR OT NJ O N O o G5 O CO NI OI OO Po eo e 2 38 847 46 286 104 olo wl g o Oo 16 65 tenx technology inc Rev 1 2 2003 7 31 o d EN als ojo 4 o o IN Oo cO t TI 221 405 220 000 0 234 057
71. al change at IOC IOD will be inhibited To release this mode SCA instruction must be executed again Refer to 2 16 1 1 2 15 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 HEF1 2 3 4 5 6 and is set by SHE instruction The bit pattern of the control register CTL2 is shown below Halt release HEF6 HEF5 HEF4 enable flag 47 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Enable the halt Enable the halt Enable the halt Halt release release caused by release caused by release caused by condition RFC counter to be TMR2 underflow lt MEFS mera 6 enable flag Enable the halt Enable the halt Enable the halt Halt release release caused by release caused by release caused by condition pre divider overflow INT pin HRF2 TM1 underflow When the halt release enable flag 6 HEF6 is set a finish signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF1 to HEF4 are setto 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMR1 the signal change at the INT pin an overflow signal from the pre divider and an underflow signal from TMR2 a H signal from OR ed output of Kl1 4 latch signals When the stop release enable flag 5 SRF5 and the HEF2 are set the signal change at the INT pin can cause the stop mode to be released
72. are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the first level will be overwritten Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the content of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupi accepted RTS instruction STACK ring with e first in last out function ty 30 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 7 DATA MEMORY RAM The static RAM is organized with 384 addresses x 4 bits and is used to store data The data memory may be accessed using two methods 1 Direct addressing mode The address of the data memory is specified by the instruction and the addressing range is from 00H to 7FH 2 Index addressing mode The
73. at the port IOD must be read into the RAM immediately after the halt mode is released 3 6 EL PANEL DRIVER TM8705 provides an EL panel driver for the backlight of the LCD panel The user can choose different voltage pumping frequencies duty cycle and ON OFF frequency to operate with few external components This circuitry could generate output voltage up to AC 150V or above for driving the EL plant the ELC and ELP output is MUXed with IOB1 SEG28 and IOB2 SEG289 and is selected by mask option MASK OPTION table Mask Option name SEG28 IOB1 ELC 3 ELC SEG29 IOB2 ELP 3 ELP The ELP pin will output clocks to pump voltage to the EL plant the ELC pin will output the pulse to discharge the EL plant The EL plant driver will not operate until the light control signal LIT is enabled Once the light control signal LIT is enabled the ELC pin will output a pulse to discharge the capacitor before the pumping clocks output to ELP pin This will insure that there is no residual voltage that may cause damage while the first pumping clock is applied 77 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual When the light control signal LIT is disabled the ELC pin will output a pulse to discharge the EL plant after the last pumping clock EL plant This figure shows the application circuit of EL plant ELP ELC This figure shows the output waveform of EL plant driver Executin
74. be lighted or unlighted by mask option All of the LCD output will keep the initial setting until the LCD relative instructions are executed to change the output data MASK OPTION table Mask Option name Selected item LCD DISPLAY IN RESET CYCLE 1 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 LCD LIGHTING SYSTEM IN TM8705 There are several LCD lighting systems could be selected by mask option in TM8705 they are e 1 2bias 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 4 duty 1 2bias 1 5duty 1 2bias 1 6duty 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5duty 1 3 bias 1 6duty 1 3 bias 1 7duty All of these lighting systems are combined with 2 kinds of mask options the one is LCD DUTY CYCLE and the other is BIAS MASK OPTION table LCD duty cycle option Mask Option Name Selected Item LCD DUTY CYCLE 1 O P CD DUTY CYCLE 2 DUPLEX note 1 2 duty CD DUTY CYCLE 3 1 3 DUTY CD DUTY CYCLE 4 1 4 DUTY CD DUTY CYCLE 5 1 5 DUTY CD DUTY CYCLE 6 1 6 DUTY CD DUTY CYCLE 7 1 7 DUTY CD DUTY CYCLE 8 1 8 DUTY 89 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual LCD bias option BIAS 1 NO BIAS BIAS 2 1 2 BIAS BIAS 3 1 3 BIAS The frame frequency for each lighting system is shown below these frequencies could be selected by mask option All of the LCD frame frequencies in the following tables based on the clock source frequency of the pre divider PHO is 3276
75. circuit e Multiplexer to select 1 2duty 1 3duty 1 4duty 1 5duty 1 6duty LCD driver circuitry Segment PLA circuit connected between data decoder LO to L4 decoder and latch circuit 92 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The data decoder is used for decoding the content of the working register specified in LCD related instructions as 7 segment pattern on LCD panel The decoding table is shown below Output of data decoder Note The DBUSF of decoded output can be selected as 0 or 1 by mask option The LCD pattern of this option is shown below DBUSA DBUSA DBUSF DBUSB 4 DBUSB DBUSG DBUSE i aml DBUSC DBUSD DBUSH DBUSD DBUSH DBUSF 0 DBUSF 1 The following table shows the option table for displaying digit 7 pattern MASK OPTION table Mask Option name F SEGMENT FOR DISPLAY 7 1 ON F SEGMENT FOR DISPLAY 7 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of data memory that specified When the content of data memory that specified by LCB instruction is 0 the decoded output of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on LCD panel The LCP instruction transferred the data of the RAM Rx and accumulator AC directly from DBUS A to DBUSH without passing through the data decoder The LCD instruction transfers the table ROM data T HL directly from DBUSA
76. cle Xs Xo don t care X7X5X4 010 in this setting the key matrix scanning function will be disable Xs Xo don t care X7X5X4 10X in this setting each scanning cycle check 8 specified columns on key matrix The specified column is defined by the setting of Xs 0 active K1 K8 columns simultaneously Xs 1 active K9 K16 columns simultaneously X Xo don t care X7X5X4 110 in this setting each scanning cycle check four specified columns on key matrix The specified columns are defined by the setting of X3 and X X3X 00 active K1 K4 columns simultaneously X3X 01 active K5 K8 columns simultaneously 85 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual X3X 10 active K9 K12 columns simultaneously X3X2 11 active K13 K16 columns simultaneously X1 Xo don t care X7X5X4 111 in this setting each scanning cycle check two specified columns on key matrix The specified columns are defined by the setting of X and X4 XsX gt X1 000 active K1 K2 columns simultaneously X3X2X1 001 active K3 K4 columns simultaneously X3X2X1 110 active K13 K14 columns simultaneously X3X2X1 111 active K15 K16 columns simultaneously Xo don t care When KI1 4 is defined for Key matrix scanning input by mask option it is necessary to execute SPC instruction to set the internal unused IOC port as output mode before the key matrix scanning function is active Fig 2 27 shows the
77. controlled the RFC function The SF2 1h instruction enables the re load function and the DED flag should be set to 1 by SF2 2h instruction Once DED flag had been set to 1 TENX flag will not be cleared to 0 while TMR2 underflows but HRF4 will be set to1 The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HRF4 occurs thus the TENX flag will be reset to 0 when the last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurred disable the re load function by executing RF2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 Set the initiate value of TMR2 to 52 and start counting 2 Enable the TMR2 halt release or interrupt function 3 Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue counting even if TMR2 underflows 4 When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase the counting value to count the underflow times 5 When halt release or interrupt occurs for the 7 time reset the DED flag 6 When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed In this example S W enters the halt mode to wait for the underflow of TM2 LDS 0 0 initiate the underflow counting register PLC 10h SHE 10h enable the halt release caused by TM2 SRF 19h enable RFC and controlled by TM2 TM2X 34h initiate the T
78. covered 800h to BFFh Both instruction ROM PROM and table ROM TROM shares this memory space together The partition formula for PROM and TROM is shown below Instruction ROM memory space 1024 128 N words Table ROM memory space 256 16 N bytes N 0 16 Note The data width of table ROM is 8 bit The partition of memory space is defined by mask option the table is shown below MASK OPTION table Mask Option name Selected item Instruction ROM Table ROM memory space memory space Words Bytes co o I I 1 1 n 2 S S L 2 e eleiftitititiftiftif Plo Sle I 11 B N 10 C N 11 D N 12 27 tenx technology inc Rev 1 2 2003 7 31 N II co N IO O z Z Z EE O 12 TM8705 Users Manual INSTRUCTION ROM lt gt TABLE ROM i INSTRUCTION ROM lt gt TABLE ROM F N 14 2816 INSTRUCTION ROM lt gt TABLE ROM G N 15 2944 INSTRUCTION ROM lt gt TABLE ROM H N 16 3072 fo 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as the interrupt service routines such as reset address 000H interrupt 0 address 014H interrupt 1 address 018H interrupt 2 address 010H interrupt 3 address 01CH interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory When the useful address range of PROM exceeds 2048 addresses 800h the memory space of PROM will be define
79. ct clock Presetting value of timer 1 TMS HL The clock source selection for timer 1 olol 9 3 ofif 5 pt oO Selects timer 1 clock source and preset timer 1 The data specified by X X7 X0 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 1 TMSX X X8 X7 X6 X5 x4 X3 X2 XO TM2 Rx Function Description The clock source selection for timer 1 clock source OJo PH9 0 1 PH3 ENE E PH15 1 Output of frequency generator FREQ 0 f PH NM pt o Selects timer 2 clock source and preset timer 2 The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following a shows the bit pattern for this instruction OPCODE M2 Rx 3 2 ACI ACO Rx2 Rxt Rx0 130 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The clock source selection for timer 2 PH9 0 1 O PH pt of PH5 1 1 Output of frequency generator FREQ TM2 HL Function Selects timer 2 clock source and preset timer 2 Description The content of Table ROM specified by HL is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 TM2 HL The clock source sel
80. ction execution will stop this oscillator and the system clock BCLK will be switched to XT clock There are 3 type oscillators can be used in slow clock oscillator selected by mask option 2 2 2 1 External 3 58MHz Ceramic Resonator oscillator MASK OPTION table Mask Option name FAST CLOCK TYPE FOR FAST ONLY OR DUAL 4 3 58MHz Ceramic Resonator 3 58MHz Ceramic Resonator Notes 1 Don t use 3 58MHz Ceramic Resonator as the oscillator when Ag battery option is used 2 When the program has to reset the BCF flag to 0 in Li battery power mode don t use 3 58MHz Ceramic Resonator as the oscillator 2 2 2 2 RC oscillator with External Resistor connection diagram is shown below MASK OPTION table Mask Option name FAST CLOCK TYPE FOR FAST ONLY OR DUAL 3 EXTERNAL RESISTOR R Extema 20 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 2 2 3 Internal RC Oscillator MASK OPTION table For 250KHz output frequency Mask Option name FAST CLOCK TYPE FOR FAST ONLY OR DUAL 1 INTERNAL RESISTOR FOR 250KHz For 250KHz output frequency Mask Option name FAST CLOCK TYPE FOR FAST ONLY OR DUAL 2 INTERNAL RESISTOR FOR 500KHz CFOUT N C CFIN N C Intema RC FREQUENCY RANGE OF INTERNAL RC OSCILLATOR 500KHz 1 2V 1 550KHz 650KHz 750KHz 2 4V 5 0V 400KHz 500KHz 600KHz 2 2 3 COMBINATION OF THE CLOCK SOURCES There are three types of combination of the clock sources that can be s
81. d as 2 pages automatically Refer to section 2 3 Address address 000h DOUM oan oen rl l j 01Ch High Low SSE Nibble Nibble 020h DEM 024h PT 028h XFFH F 8 Bits 10M4 128 N 1 X 15 N N 1 gt 15 N 0 16 l 16bits Instruction ROM PROM organization Table ROM TROM organization This figure shows the Organization of ROM 256 16 N addresses 2 4 2 TABLE ROM TROM The table ROM is organized with 256 16 N x 8 bits that shared the memory space with instruction ROM as shown inthe figure above This memory space stores the constant data or look up table for the usage of main program All of the table ROM addresses are specified by the index address register HL The data width could be 8 bits 256 16 N x 8 bits or 4 bits 512 16 N x 4 bits which depends on the different usage Refer to the explanation of instruction chapter 28 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM andtable ROM TROM The index address register HL is a 12 bit register and the contents of the register can be modified by executing MVH MVL and MVU instructions Executed MVL instruction will load the content of specified data memory to the lower nibble of the index register L In the same manner executed MVH and MVU instructions may load the content of the data RAM Rx to the hig
82. ded to AC and data memory HL Carry flag CF will be affected HL indicates an index address of data memory AC HL HL AC CF HL HL 1 The contents of HL AC and CF are binary added the result is loaded to AC and data memory HL The content of index register HL wil be increment automatically after executing this instruction Carry flag CF will be affected HL indicates an index address of data memory AC lt Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC e HL AC B CF The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC HL indicates an index address of data memory Carry flag CF will be affected 109 tenx technology inc Rev 1 2 2003 7 31 SBC HL Function Description SBC Rx Function Description SBC HL Function Description SBC Function Description ADD Rx Function Description ADD HL Function Description ADD HL Function TM8705 Users Manual AC e HL AC B CF HL HL 1 The contents of AC and CF are binary subtracted from content of HL the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected
83. e If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo serial output port by executing OPAS instruction IOA port must be defined as the output mode before executing OPAS instruction 1 BITO and BIT1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS 3 BIT3 of the port delivers pulses Shown below is a sample program using the OPAS instruction 1 LDS OAH 0 2 OPA OAH SPA LDS 15 3 OPAS 1 1 Bit 0 output shift gate open 4 SRO 1 Shifts bit 1 to bit 0 5 OPAS1 1 Bit 1 output 69 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 6 SRO 1 Shifts bit2 to bit 0 7 OPAS 1 1 Bit 2 output 8 SRO 1 Shifts bit 3 to bit 0 9 OPAS 1 1 Bit 3 output 10 OPAS 1 1 Last data 11 OPAS1 Shift gate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 1 10 11 AC 0 AC 5 AC 2 AC 1 IOA1 BitO for Rx 5 Bit1 for Rx 5 Bit2 for Rx 5 Bit3 for Rx 5 M M IOA2 M M N L 1 1 t BCLK 2 If IOA1 pin is used as the CX pin for RFC function and the other pins IOA2 IOA3 are used for normal IO pins IOA1 pin must always be defined as the output mode to avoid the influence from the CX when the input chattering prev
84. e DC output option and 10 is for P open drain DC output option PSTB Specifies the strobe data for the latch DBUS Specifies the DBUS data for the latch 97 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Chapter 5 Detail Explanation of TM8705 Instructions elt is necessary to initialize the content of data memory after initial reset because the initial content of the data memory is unknown eThe working registers are part of the data memory RAM and the relationship between them was shown as follows The absolute address of working register Rx Ry 70H Address of working registers Absolute address of data memory specified by Ry Rx Lz represents the address of the latch of LCD PLA PSTB data in cfy file the address range specified by Lz is from OOH to 1FH 5 1 INPUT OUTPUT INSTRUCTIONS LCT Lz Ry Function Description LCB Lz Ry Function Description LCP Lz Ry Function Description LCD latch Lz data decoder Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder Lz 00 1FH Ry 0 FH LCD latch Lz data decoder Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the outputs of the data decoder are all 0 Lz 00 1FH Ry 0 FH LCD latch Lz Ry AC The working register conte
85. e and holds long enough to cause the CPU to be released from halt mode 2 A signal change in the INT pin 3 The stop release condition specified by the SRE instruction is met SCA X Function The data specified by X causes the halt mode to be released Description The signal change at port IOC IOD is specified The bit meaning of X X4 X3 is shown below to IOC to IOD X2 0 dont care SIE X Function Set Reset interrupt enable flag Description mic IEFO is set so that interrupt O Signal change at port IOC or IOD specified by X0 1 SCA is accepted X1 1 The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted X2 1 The IEF2 is set so that interrupt 2 the signal change at the INT pin is accepted X3 1 The IEF3 is set so that interrupt 3 overflow from the predivider is accepted X4 1 The IEF4 is set so that interrupt 4 underflow from timer 2 is accepted X5 1 The IEF5 is set so that interrupt 5 key scanning is accepted X6 1 The IEF6 is set so that interrupt 6 overflow from the RFC counter is accepted SHE X Function Set Reset halt release enable flag Description X1 1 The HEF1 is set so that the halt mode is released by TMR1 underflow 2 1 The HEF2 is set so that the halt mode is released by signal changed on INT pin X3 1 The HEF3 is set so that the halt mode is released by predivider overflow X4 1 The HEF4 is set so that the halt mode is released by TMR2 under
86. e interrupt occurred When HRF4 1 IEF4 0 and the TMR2 halt release enabler HEF4 is setto 1 program will escapes from halt mode if CPU is in halt mode and then HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 STS4 After power on reset the default clock source of TMR2 is PH7 If watchdog reset occurred the clock source of TMR2 will still keep the previous selection The following table shows the definition of each bit in TMR2 instructions ui de Select clock Initiate value of timer TX XS TM2 Rx 0 AC3 2 AC Rx0 A ddl d al lid HL The following table shows the clock source setting for TMR2 01 0 0 1 1 PHO 37 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Notes 1 When the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value
87. ection for timer 2 Output of frequency generator FREQ TM2X X Function Selects timer 2 clock source and preset timer 2 Description The data specified by X X8 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Presetting value of timer 2 TM2X X The clock source selection for timer 2 Output of frequency generator FREQ PH13 131 tenx technology inc Rev 1 2 2003 7 31 SF X Function Description RF X Function Description SF2 X Function Description RF2 X Function Description PLC Function Description TM8705 Users Manual Sets flag Description of each flag X0 1 The CF flag is set to 1 X1 1 The chip enters backup mode and BCF flag is set to 1 X2 1 The EL panel driver output pin is active X3 1 For X221 when the SF instruction is executed at X3 1 the EL panel driver is active and the halt request signal is outputted then the program enters halt mode similar to HALT instruction X4 1 The watchdog timer is initiated and active and WDF flag is to 1 X7 1 Enables the re load function of timer 1 X6 5 is reserved Resets flag Description of each flag 1 The CF flag is reset to 0 X1 1 The chip escaped from backup mode and BCF flag is reset to 0 X2 1 The EL light driver is inactive X4 1 The watchdog timer is disable and WDF flag is
88. ed and an interrupt is accepted the halt release signal HRF is reset automatically 2 19 BACK UP FUNCTION TM8705 provide a back up mode to avoid system malfunction when heavy loading occurred such as buzzer is active LED is lighting etc Since the heavy loading will cause a large voltage drop on the supply voltage and the system will be malfunction in this condition Once the program enter back up mode BCF 1 32 768KHz Crystal oscillator will operate in a large driver condition and internal logic function operates with higher supply voltage TM8705 will get more power supply noise margin while back up mode is active but also increases more power consumption The back up flag BCF indicated the status of back up function BCF flag could be set or reset by executing SF or RF instruction respectively The back up function has different performance corresponding to different power mode option shown in the following table TM8705 status BCF flag status Initial reset cycle BCF 1 hardware controlled After initial reset cycle BCF 1 hardware controlled 1 5V battery mode Executing RF 2h instruction BCF 0 Executing SF 2h instruction BCF 1 HALT mode STOP mode BCF 1 hardware controlled TM8705 status BCF 0 32 768KHz Crystal Oscillator Small driver Voltage on BAK pin VDD1 VDD1 Internal operating voltage VDD1 VDD1 3V battery or higher mode TM8705 status Initial reset cycle After initia
89. edge on INT Kl1 4 IOC IOD port pin Stop release request flag Stop release request flag CSR DSR Stop release enable flag SRF7 SRF4 SRF3 SRF5 2 15 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 CTL1 to control register 4 CTL4 2 15 1 CONTROL REGISTER 1 CTL1 The control register 1 CTL1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC defined as input mode that causes the halt mode or stop mode to be released 2 Switch enable flag 3 SEF3 Stores the status of the input signal change at pins of IOD defined as input mode that causes the halt mode or stop mode to be released Executed SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 CTL1 Bit 4 Bit3 Switch enable flag 4 Switch enable flag 3 SEF4 SEF3 Enables the halt release Enables the halt release caused by the signal caused by the signal change on IOC port change on IOD port The following figure shows the organization of control register 1 CTL1 46 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual E HALT IOC dge Released detector R SEF4 equest SCA 10h Interrupt 0 request IOD Edge detector 2 15 1 1 The Setting for Halt Mode If the SEF4 SEF3 is set to 1 the signal changed on IOC IOD port will cause the halt mode to be released and set SC
90. elease ski release IPC 10h read KI1 4 input latch state JBO ki release JB1 ki2 release 87 tenx technology inc Rev 1 2 2003 7 31 JB2 JB3 ki1_release SPKX PLC CALL scan again IPC JBO wait_scan_again HALT PLC 20h RTS TM8705 Users Manual ki3 release ki4 release 40h Check key depressed on K1 column 20h Clear HRF5 to avoid the false HALT released wait scan again Waiting for the next key matrix scanning cycle The waiting period must longer than key matrix scanning cycle 10h Read KI1 input latch state ki1 seg1 4fh Only enable SEG16 scanning output 20h Clear HRF5 to avoid the false HALT released wait scan again Wait for time over halt LCD clock cycle to sure 10h Read KI1 input latch state kil seg16 88 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual CHAPTER4 LCD DRIVER OUTPUT The number of the LCD driver outputs in TM8705 is 40 segment pins with 6 common pins All of these output pins could also be used as DC output ports mask option If more than one of LCD driver output pin was defined as DC output the following mask option must be selected MASK OPTION table When more than one of SEG or COM pins have been used to drive LCD panel Mask Option name LCD ACTIVE TYPE 1 LCD When all of SEG and COM5 6 pins had been used for DC output Mask Option name LCD ACTIVE TYPE 2 O P During the initial reset cycle all of LCD s lighting system may
91. elected by mask option 2 2 3 1 Dual Clock MASK OPTION table Mask Option name CLOCK SOURCE 3 DUAL The operation of the dual clock option is shown in the following figure When this option is selected by mask option the clock source BCLK of system clock generator will switch between XT clock and CF clock according to the user s program When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically The XT clock provides the clock to the pre divider timer I O port chattering prevention and LCD circuitry in this option 21 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Halt Halt Halt mode 4 Slow mode Slow Fast mode XTOSC active XTOSC active XTOSC active CFOSCstop HALT V CFOSC stop LE88ty CFOSC active released T Stop Stop Reset release Reset Reset state Reset Stop mode XTOSC active A XTOSC stop Power on reset Reset pin reset Watchdog timer reset Key reset CFOSC stop CFOSC stop State Diagram of Dual Clock Option was shown on above figure After executing FAST instruction the system clock generator will hold 12 CF clocks after the CF clock oscillator starts up and then switches CF clock to BCLK This will prevent the incorrect clock from delivering to the system clock in the start up duration of the fast clock oscillator CF clock XT clock FAST BCLK HOLD
92. elow n SPK T HL T HL T HL T HL T HL T HL TCHL T HL HL 7 6 5 4 3 2 1 0 SPKX X ALM X Function Sets buzzer output frequency Description The waveform specified by X X8 X0 is delivered to the BZ and BZB pins The output frequency could be any combination in the following table The bit pattern of X for higher frequency clock source X7 clock source higher frequency 1 FREQ o ko 0 PHA 2KHz O PDCO clock source lower frequency PH15 1Hz PH13 4Hz PH12 8Hz X0 PH10 32Hz Notes 1 FREQ is the output of frequency generator 2 When the buzzer output does not need the envelope waveform X5 should be set to 0 3 The frequency inside the bases on the PHO is 32768Hz ELC X Function The bit control of EL panel driver Description The meaning of each bit specified by X X9 X0 is shown below For ELP pin output clock setting 104 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual X8 X7 X6 Pumping clock X9 X5 X4 Duty cycle frequency 00 PH 10 3 4 duty BCLK 2 3 dut Lo 1 A 0 O Note X represents don t care For ELC pin output clock setting frequency 00 PH j f duy SRF X Function The operation control for RFC Description The meaning of each control bit X5 X0 is shown below X021 enables the RC oscillation 0 0 disables the RC osc
93. em POWER SOURCE 1 EXT V BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased 2 1 3 2 1 2 BIAS AT EXT V POWER SUPPLY Internal logic 16 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 2 1 3 3 1 3 BIAS AT EXT V POWER SUPPLY Internal logic MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required 17 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 2 SYSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below BCLK Ti T2 T3 T4 Sclk
94. ention function is active On the other hand the RFC counter can receive the signal changes on IOA1 when the RFC counter is enabled 3 5 2 IOB PORT IOB1 IOB4 pins are MUXed with ELC SEG28 ELP SEG29 BZB SEG30 and BZ SEG31 pins respectively by mask option MASK OPTION table Mask Option name SEG28 IOB1 ELC 2 IOB1 2 SEG29 IOB2 ELP 2 IOB2 SEC30 IOB3 BZB 2 IOB3 SEG31 IOBA BZ 2 IOB4 70 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The following figure shows the organization of IOB port Initial clear SPB1 Initial clear SPB2 Initial clear SPB4 Initial clear SPB 8 S Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may output the content of specified data memory to the pins defined as output mode the other pins which are defined as the input will still be input Executed IPB instructions may store the signals applied on the IOB pins into the specified data memory When the IOB pins are defined as the output executing IPB instruction will save the data stored in the output latch into the specified data memory Before executing SPB instruction to define the I O pins as output
95. et power on reset POR or reset pin the timer is inactive and the watchdog flag WDF is reset Instruction SF 10h will enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the content of the timer will be cleared Once the watchdog timer is enabled the timer will be paused when the program enters the halt mode or stop mode When the TM8705 wakes up from the halt or stop mode the timer operates continuously It is recommended to execute SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute SF 10h instruction periodically to prevent the timer overflowed The overflow time interval of watchdog timer is selected by mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER OVERFLOW 1 8 x PH10 TIME INTERVAL TIME INTERVAL TIME INTERVAL Note timer overflow time interval is about 16 seconds when PH0 32 768KHz 3 3 CLOCK GENERATOR 3 3 1 FREQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter 63 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The following shows the organization of the frequency generator 8 bit Pr
96. f AC 0 If the content of AC is O jump occurs If 1 the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to X in current page if CF 1 If the content of CF is 1 jump occurs If 0 the PC increases by 1 The range of X is from OOOH to 7FFH Program counter jumps to P 800h X Unconditional jump When P 0 page 0 the program jump to address X 000H to 7FFH When P 1 page 1 the program jump to address 800h X 800H to STACK e PC 1 Program counter jumps to P 800h X A subroutine is called When P 0 page 0 the program jump to address X 000H to 7FFH When P 1 page 1 the program jump to address 800h X 800H to PC STACK A return from a subroutine occurs 5 9 MISCELLANEOUS INSTRUCTIONS SCC X Function Setting the clock source for IOD and IOC chattering prevention PWM output and frequency generator Description The following table shows the meaning of each bit for this instruction Bit pattern Clock source setting Bit pattern Clock source setting X6 1 The clock source of X6 0 The clock source of frequency generator frequency generator comes from the PHO Refer to section 3 3 4 for 90 comes from the system clock BCLK 127 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Bit pattern Bit pattern X4 X3 0 X2 X1 X0 1 X4 X3 0 0 1 Chattering prevention X4 X3 10 Chattering prevention 00 clock of IO
97. flow X5 1 The HEF5 is set so that the halt mode is released by the signal is L applied on KI1 4 during scanning interval X6 1 The HEF6 is set so that the halt mode is released by RFC counter overflow Note X0 don t care SRE X Function Set Reset stop release enable flag 121 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Description X3 1 The SRF3 is set so that the stop mode is released by the signal changed on IOD port X4 1 The SRF4 is set so that the stop mode is released by the signal changed on IOC port X5 1 The SRF5 is set so that the stop mode is released by the signal changed on INT pin X7 1 The SRF7 is set so that the stop mode is released by the signal is L applied on KI1 4 in scanning interval Note X2 0 don t care FAST Function Switches the system clock to CFOSC clock Description Starts up the CFOSC high speed osc and then switches the system clock to high speed clock SLOW Function Switches the system clock to XTOSC clock low speed osc Description Switches the system clock to low speed clock and then stops the CFOSC MSB Rx Function AC Rx SCF3 SCF2 BCF1 BCF Description The SCF1 SCF2 SCF3 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condit
98. g ELC instruction can change ELP ELC pulse frequency and duty cycle When ELC pin outputs the discharge pulse the clock on ELP pin will be inhibited For ELP setting frequency PH0 m 111 Boks PP For ELC setting Discharge pulse co sow oar PH8 1 4duty The default setting after the initial reset is ELP PHO clock of pre divider and 1 4 duty cycle ELC PH8 clock of pre divider and 1 4 duty cycle 78 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The timing of the duty cycle is shown below PH0 PH8 1 4 duty 1 3 duty le suo ij 1 1 duty Example ELC 110h ELP outputs BCLK clock with 1 3 duty cycle and ELC outputs PH8 clock with 1 4 duty cycle SF 4h Enables the light control signal LIT and turns on the EL light driver HF 4h Disables the light control signal and turns off the EL light driver 3 7 EXTERNAL INT PIN The INT pin can be selected as pull up or pull down or open type by mask option The signal change either rising edge or falling edge by mask option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted MASK OPTION table For internal resistor type Mask Option name INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTO
99. g of the RFC counter controlled by timer 2 Example In this example use the RT network to generate the clock source SRF 1Ah Build up the RT network and enable the counter controlled by TM2 SHE 10h enable the halt release caused by TM2 TM2X 20h 561 the PH9 as the clock source of TM2 and the down count value is 20h HALT PLC 10h Clear the halt release request flag of TM2 MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 8 4 Enable Disable the Counter by CX Signal This is another use for the 16 bit counter In previous modes CX is the clock source of the counter and the program must specify a time period by timer or subroutine to control the counter In this mode however the counter has a different operation method CX pin becomes the controlled signal to enable disable the counter and the clock source of the counter comes from the output of the frequency generator FREQ The counter will start to count the clock FREQ after the first rising edge signal applied on the CX pin when the counter is enabled Once the second rising edge is applied to the CX pin after the counter is enabled the halt release request HRF6 will be delivered and the counter will stop counting In this case if the interrupt enable mode IEF6 is provided the interrupt is accepted and if the halt release enable mode HEF6 is provided the halt release request signal is delivered setting the start condition flag 9 SCF9
100. g this instruction HL indicates an index address of data memory 111 tenx technology inc Rev 1 2 2003 7 31 SUB Rx Function Description SUB HL Function Description SUB Function Description ADN Rx Function Description ADN HL Function Description AND HL Function Description ADN Rx Function TM8705 Users Manual Carry flag CF will be affected AC Rx Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC and Rx Carry flag CF will be affected AC HL HL AC B 1 The content of AC is binary subtracted from content of HL the result is loaded to AC and data memory HL HL indicates an index address of data memory Carry flag CF will be affected AC HL HL AC B 1 HL HL 1 The content of AC is binary subtracted from content of HL the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected AC Rx AC The contents of Rx and AC are binary added the result is loaded to AC The result will not affect the carry flag CF AC e HL AC The contents of HL and AC are binary added the result is loaded to AC The result will not affect the carry flag CF HL indicates an index addre
101. h the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry The data of the RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown below 5 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 6 LCB Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUSA to DBUSH are all 0 when the input data of the data decoder is 0 7 LCP Lz HL The data of the index RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown below Table 2 4 The mapping table of LCP and LCD instructions __ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH T HLO T HL1 T HL2 T HL3 T HL4 T HL5 T HL6 T HL7 5 SF2 4h Turns off the LCD display 6 RF2 4h Turns on the LCD display 4 3 3 CONCRETE EXPLANATION Each LCD driver output corresponds to the LCD 1 6 duty panel and has 6 latches refer to Figure Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of the segments in the LCD driver outputs is flexible In other words one of the data decoder outputs
102. he 15th stage s content of the pre divider The MSC instruction is used to transfer the contents of status register 3 STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3 STS3 Bit 3 Bit 2 Bit 1 Bit 0 Start condition 15th stage of the Start condition Start condition flag 7 pre divider flag 5 flag 4 SCF7 SCF5 SCF4 Halt release Halt release Halt release caused by pre caused by TMR1 caused by INT divider overflow underflow pin 43 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 14 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags 1 Start condition flag 8 SCF8 SCF8 is set to 1 when any one of KI1 4 1 0 KI1 4 1 in LED mode KI1 4 0 in LCD mode causes the halt release request flag 5 HRF5 to be outputted and the halt release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 2 Start condition flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be outputted and the halt release enable
103. he desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 2 15 4 CONTROL REGISTER 4 CTL4 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 press SRF7 SRF4 SRF3 enable flag Enable the stop release Enable the stop release Enable the stop release Stop release request caused by signal request caused by signal request caused by signal request flag change on KI1 4 SKI change on INT pin change on IOC IOD When the stop release enable flag 7 SRF7 is set to 1 the input signal change at the Kl1 4 pins causes the stop mode to be released In the same manner when SRF4 SRF3 and SRF5 are set to 1 the input signal change at the input mode pins of IOC IOD port and the signal changed on INT pin causes the stop mode to be released respectively Example This example illustrates the stop mode released by port IOC Kl1 4 and INT pin Assume all of the pins in IOD and IOC have been defined as input mode PLC 25h Reset the HRF0 HRF2 and HRF5 SHE 24h HEF2 and HEF5 is set so that the signal change at INT or Kl1 4 pin causes start condition flag 4 or 8 to be set SCA 10h SEF4 is set so that the signal changes at port IOC cause the start conditions SCF1 to be set SRE ObOh SRF7 5 4 are set so that the signal changes at KI1 4 pins port IOC and INT pin cause the st
104. he result is loaded to AC HL indicates an index address of data memory AC e HL AC HL HL 1 The contents of HL and AC are binary ORed the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Rx Rx AC The contents of Rx and AC are binary Ored the result is loaded to AC data memory Rx AC HL HL AC The contents of HL and AC are binary ORed the result is loaded to AC and data memory HL HL indicates an index address of data memory AC HL HL AC HL HL 1 The contents of HL and AC are binary ORed the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Ry D CF D represents the immediate data The contents of Ry D and CF are binary ADDed the result is loaded to AC The carry flag CF will be affected 115 tenx technology inc Rev 1 2 2003 7 31 ADCI Ry D Function Description SBCI Ry D Function Description SBCI Ry D Function Description ADDI Ry D Function Description ADDI Ry D Function Description SUBI Ry D Function Description TM8705 Users Manual D 0H FH Ry Ry D CF D represents the immediate data The c
105. her nibble of the register OH QU respectively IDBF11 IDBF10 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO The index address register can specify the full range addresses of the table ROM and data memory DATA RAM TABLE ROM BF HL addressing This figure shows the diagram of the index address register The index address register is a write only register CPHL X instruction could specified a 8 bit immediate data to compare the content of H and L When the result of comparison is equivalent the instruction that behind CPHL X will be skipped NOP if not the instruction behind CPHL X will be executed normally Note In the duration of comparison the index address all the interrupt enable flags IEF has to be cleared to avoid malfunction The comparison bit pattern is shown below CPHL X IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO Example HL 30h CPHL 30h SIE Oh disable IEF JMP Jlable1 this instruction will be force as NOP JMP lable2 this instruction will be executed and than jump to lable2 29 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual lable1 2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stack register
106. i TIMER 1 amp 2 CONTROL OSCILLATOR pound OSCILLATOR j CIRCUIT b COUNTER BITS TM8705 BLOCK DIAGRAM N 0 gt 16 g DATA RAM 512 X 4 BITS INSTRUCTION DECODER O O D D CUPO 1 XTIN OUT CFIN OUT RESET INT 1 5 PAD DIAGRAM DJ o D 0 D o D o O D LI LI LI D O LI LI O DJ D O DJ DJ D DJ o o O o o O D D DJ o DJ The substrate chip should be connected to GND 5 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 1 6 PAD COORDINATE BAK 99 35 717 50 SEG14 K14 1627 50 XIN 72 50 602 50 SEG15 K15 1627 50 XOUT 72 50 487 50 SEG16 K16 1627 50 CFIN 72 50 372 50 SEG17 1627 50 CFOUT 72 50 247 50 SEG18 1627 50 GND 72 50 122 50 SEG19 1627 50 VDD1 197 50 72 50 SEG20 1502 50 VDD2 322 50 72 50 SEG 1 1377 50 VDD3 447 50 72 50 SEG22 1252 50 CUP1 562 50 72 50 SEG23 1137 50 CUP2 677 50 72 50 SEG24 IOA1 CX 1022 50 COMI 792 50 72 50 SEG25 IOA2 RR 907 50 COM2 907 50 72 50 SEG26 IOA3 RT 792 50 COM3 1022 50 72 50 SEG27 IOA4 RH 677 50 COM4 1137 50 72 50 SEG28 IOB1 ELC 562 50 5 1252 50 72 50 SEG29 IOB2 ELP 447 50 COM6 1377 50 72 50 SEG30 IOB3 BZB 322 50 1502 50 72 50 SEG31 IOBA BZ 197 50 1627 50 122 50 SEG32 IOC1 KI1 72 50 1627 50 247 50 SEG33 IOC2 Kl2 72 50 1627 50 372 50 SEG34 OC3 KIBB 72 50 1627 50 487 50 SE
107. ill set to 1 automatically to insure that the low speed oscillator will start up in a proper condition while stop release occurs 51 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 18 STOP FUNCTION STOP The stop function is another solution to minimize the current dissipation for TM8705 In stop mode all of functions in TM8705 are held including oscillators All of the LCD corresponding signals COM and Segment will output L level In this mode TM8705 does not dissipate any power in the stop mode Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins defined as input mode of IOD and IOC ports must be in the L state and no stop release signal SRFn should be delivered The CPU will then enter the stop mode The following conditions cause the stop mode to be released One of the signals on the input mode pin of IOD or IOC port is in H state and holds long enough to cause the CPU to be released from halt mode Asignal change in the INT pin The stop release condition specified by the SRE instruction is met When the TM8705 is released from the stop mode the TM8705 enters the halt mode immediately and will process the halt release procedure If the H signal on the IOC IOD port does not hold long enough to set the SCF1 SCF3
108. illation db d gd ns the RC oscillation network of RT network of RT L R 3 s the RC oscillation network of RH network of RH must be set to 1 when this bit is set to 1 counter X5 1 The 16 bit counter is controlled by X5 0 Disables the CX pin to control the set to 1 when this bit is set to 1 Note X4 and X5 can not be set to 1 at the same time 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx Function AC Ry Rx Description The content of Rx is loaded to AC and the working register specified by Ry MRW HL Rx 105 tenx technology inc Rev 1 2 2003 7 31 Function Description TM8705 Users Manual AC R HL Rx The content of data memory specified by Rx is loaded to AC and data memory specified by HL MRW HL Rx Function Description MWR Rx Ry Function Description MWR Rx HL Function Description AC R HL Rx HL HL 1 The content of data memory specified by Rx is loaded to AC and data memory specified by HL The content of index register HL will be increment automatically after executing this instruction AC Rx lt Ry The content of working register specified by Ry is loaded to AC and data memory specified by Rx AC Rx R HL The content of data memory specified by HL is loaded to AC and data memory specified by Rx MWR Rx HL Function Description SRO Rx Function
109. in status register 4 STS4 83 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 28h SRF 0h SRF control Enable counter CX Content of PONE the counter o X1X 2X3 NH me EI ETEIETETET HALT released request L Counter starts Counter stops to count caused by the 2nd rising edge This figure shows the timing of the counter controlled by the CX pin Example SCC Oh Select the base clock of the frequency generator that comes from PHO XT clock FRQX 1 5 set the frequency generator to FREQ PH0 3 5 the setting value of the frequency generator is 5 and FREQ has 1 8 duty waveform SHE 40h enable the halt release caused by 16 bit counter SRF 28h enable the counter controlled by the CX signal HALT PLC 40h halt release is caused by the 2 rising edge on CX pin and then clear the halt release request flag MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 9 Key Matrix Scanning TM8705 shared the timing of LCD waveform to scan the key matrix circuitry and these scanning output pins are SEG1 16 for easy to understand named these pins as K1 K16 The time sharing of LCD waveform will not affect the display of LCD panel The input port of key matrix circuitry is composed by KI1 KI4 pins these pins are muxed with SEG32 SEG
110. ion Backup flag flag 3 flag 2 flag 1 BCF SCF3 SCF2 SCF 1 Halt release Halt release caused Halt release The backup caused by the by SCF4 5 6 7 8 9 caused by the mode status in IOD port IOC port TM8705 MSC Rx Function AC Rx SCF4 SCF5 SCF7 PH15 Description The SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag The content of 15th Start condition flag 122 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual SCF7 SCE5 Halt release Halt release Halt release caused by caused by TM1 caused by INT pin predivider overflow underflow MCX Rx Function AC Rx e SCF8 SCF6 SCF9 Description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition NA Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 Halt release NA Halt release Halt release caused by RFC caused by TM2 caused by the counter overflow underflow signal change to L applied on Kl1 4 in scanning interval MSD Rx Function Rx AC e WDF CSF RFOVF Description The watchdog flag system clock status and overflow flag of RFC counter are loaded to data memory specified by Rx and AC The content of AC and meaning of bit after e
111. kup flag must be reset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD2 at the off state of SW1 is used as an intermediate voltage level for the LCD driver 2 1 2 3 1 3 BIAS AT LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in inverter size At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD at the off state of SW1 is used as an intermediate voltage level for LCD driver 15 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 1 3 EXTV POWER SUPPLY Operating voltage range 3 6V 5 4V For different LCD bias application the connection diagrams are shown below 2 1 3 1 NO BIAS AT EXT V BATTERY POWER SUPPLY N C N C Internal EXTV 1 MASK OPTION table Mask Option name Selected it
112. l reset cycle BCF flag status BCF 1 hardware controlled hardware controlled BCF 1 BCF 0 Previous state BCF 1 hardware controlled BCF 1 53 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual PBF BCF 1 32 768KHz Crystal Oscillator Small driver Voltage on BAK pin VDD1 VDD2 Internal operating voltage VDD1 VDD2 Ext V power mode STOP mode BCF 1 hardware controlled Br o C Note For power saving reason it is recommend to reset BCF flag to 0 when back up mode is not used 54 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Chapter 3 Control Function 3 1 INTERRUPT FUNCTION There are 7 interrupt resources 3 external interrupt factors and 4 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine specified by a fix address in the program memory ROM is called The following table shows the flag and service of each interrupt Table 3 5 Interrupt information source IOD port underflow divider matrix counter wor underflow Scanning overflow vector Interrupt IEF2 IEFO IEF1 ied IEF4 IEF5 IEF6 enable flag Interrupt m 5 5 j j Interrupt dius doa uio iis ics d request flag The following figure shows the Interrupt Control Circuit 55 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual
113. ld be selected by mask option MASK OPTION table PHO lt gt BCLK FOR FAST ONLY 2 PHO BCLK 4 PHO lt gt BCLK FOR FAST ONLY 3 PHO BCLK 8 PHO lt gt BCLK FOR FAST ONLY 4 PHO BCLK 16 24 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 2 5 System Clock Generator For the system clock the clock switch circuit permits the different clocks input from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator SGC The basic system clock is shown below k Machine Cycle Instruction N Cycle 25 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 3 PROGRAM COUNTER PC This is a 12 bit counter which addresses the program memory ROM up to 3072 addresses The MSB of program counter PC11 is a page register Only CALL and JMP instructions could address to the whole address range 000h BFFh the rest jump relative instructions could address to either page 0 000h 7ffh or page 1 800h BFFh The program counter PC is normally increased by one 1 with every instruction execution PC PC 1 When executing JMP instruction subroutine call instruction CALL interrupt service routine or reset occurs the program counter PC loads the specified address corresponding to table 2 1 PC specified address shows in Table 2 1 When executing a jump instruction except JMP and CALL the p
114. ll be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry 76 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Interrupt request ALT released request chattering prevention LC 1 Interrupt accept SC intruction SCA intruction Note The default prevention clock is PH10 This figure shows the organization of chattering prevention circuitry This chattering prevention function works when the signal at the applicable pin ex IOD1 is changed from L level to H level or from H level to L level and the remaining pins ex IOD2 to IOD4 are held at L level When the signal changes at the input pins of IOD port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH1 0 cycles the control circuit at the input pins will deliver the halt release request signal SCF3 At that time the chattering prevention clock will stop due to the delivery of SCF3 The SCF3 will be reset to 0 by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF3 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOD interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOD1 to IODA the input data
115. loaded to AC and working register Ry D 0H FH AC lt Ry D D represents the immediate data The contents of Ry and D are binary OREd the result is loaded to AC D 2 0H FH AC Ry Ry D D represents the immediate data The contents of Ry and D are binary OREd the result is loaded to AC and working register Ry D 0H FH 5 4 LOAD STORE INSTRUCTIONS STA Rx Function Description STA HL Function Description STA HL Function Description LDS Rx D Function Description LDA Rx Function Description Rx AC The content of AC is loaded to data memory specified by Rx HL AC The content of AC is loaded to data memory specified by HL HL indicates an index address of data memory HL AC HL HL 1 The content of AC is loaded to data memory specified by HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Rx D Immediate data D is loaded to the AC and data memory specified by Rx D 0H FH AC lt Rx The content of Rx is loaded to AC 118 tenx technology inc Rev 1 2 2003 7 31 LDA HL Function Description LDA HL Function Description LDH Rx HL Function Description LDH Rx HL Function Description LDL Rx HL Function Description LDL Rx HL Function Description
116. mum Storage Temperature 25 to 125 C POWER CONSUMPTION at Ta 20 C to 70 C GND OV HALT mode l Only 32 768KHz Crystal oscillator 2 uA operating without loading Ag mode VDD1 1 5V BCF 0 7 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual IHa_t2 Only 32 768KHz Crystal oscillator operating without loading Li mode VDD2 3 0V BCF 0 STOP mode Note When RC oscillator function is operating the current consumption will depend on the frequency of oscillation ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND OV Symb Condition Min Ma Unit 525 VV 24 525 V Voltage Crystal Mode 2 vons Voltage VDDB Crystal Mode W VDD1 165 iti Max upply Voltage VDD1 upply Voltage VDD2 EXT V LiMode 24 52 nput H Voltage nput L Voltage i nput H Voltage nput L Voltage nput H Voltage OSCIN at Ag Battery nput L Voltage Mode 0 02xVDDi nput H Voltage OSCIN at Li Battery nput L Voltage Mode 0 02xVDD2 5 5 5 51 51 515151 5 0 o O O QO D en Oo Ke o lt S S lt 65 0p c D D a e 9p 5 C g Oo VDDB nput H Voltage CFIN at Li Battery or 0 8xVDD2 nput L Voltage EXT V Mode 02xVDD 2 nput H Voltage nput L Voltage O KHz INTERNAL RC FREQUENCY RANGE Option Mode 250KHz O o D _ ae
117. n Table 3 1 The back up flag status in different conditions 50 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 1 Agoptio Lioption EXT V option BCF 1 BCF 1 BCF 0 After reset cycle BCF 1 BCF 1 BCF 0 SF 2 executed BCF 1 BCF 1 BCF 1 RF 2 executed BCF 0 BCF 0 BCF 0 For low power consumption application reset BCF to 0 is necessary the 32 768KHz Crystal oscillator operates with a normal buffer only so switch the internal power BAK to VDD1 Li power option only In this condition only peripheral circuitry operates under VDD voltage range the other functions will operate under 1 2 VDD voltage range In Ag and EXT V power options the internal power BAK will not be affected by the setting of BCF With Li power option it is necessary to connect a 0 1uf capacitor from BAK power pin to GND for the backup mode application When the heavy load function is performed the current dissipation will increase Table 3 2 Ag power option ee ee SIOP mode KA A2 Lom co oq C Internal logic MEN VDD logic Table 3 3 Li power option Initial reset After reset Stop mode SF2 RF2 BCF f J f f 1 0 Peripheral VDD VDD VDD VDD VDD logic Table 3 4 EXT V power option Initial reset After reset Stop mode SF2 RF2 1 1 Internal logic VDD VDD VDD VDD logic Note When the program enters the stop mode the BCF w
118. n a signal chip 1 2 FEATURE 1 Low power dissipation 2 Powerful instruction set 178 instructions eBinary addition subtraction BCD adjust logical operation in direct and index addressing mode eSingle bit manipulation set reset decision for branch e Various conditional branch 16 working registers and manipulation eTable look up el CD driver data transfer 3 Memory capacity e ROM capacity 3072 x 16 bits RAM capacity 384 x4bits 4 LCD driver output 96 common outputs and 40 segment outputs up to drive 240 LCD segments 1 2 Duty 1 3 Duty 1 4 Duty 1 5 Duty or 1 6Duty is selected by MASK option 1 2 Bias or 1 3 Bias is selected by MASK option Single instruction to turn off all segments eCOM5 6 SEG1 40 could be defined as CMOS or open drain type output by mask option 5 Input output ports ePort IOA 4 pins with internal pull low muxed with SEG24 SEG27 e Port IOB 4 pins with internal pull low muxed with SEG28 SEG31 Port IOC 4 pins with internal pull low low level hold muxed with SEG32 SEG35 IOC port had built in the input signal chattering prevention circuitry Port IOD 4 pins with internal pull low muxed with SEG36 SEG39 IOD port had built in the input signal chattering prevention circuitry 8 level subroutine nesting Interrupt function eExternal factors 4 INT pin Port IOC IOD amp KI input lnternal factors 4 Pre Divider Timer1 Timer2 amp RFC 8 Built in E
119. n of the 16 bit counter Each mode will be described in the following sections 3 8 2 Enable Disable the Counter by Software The clock input of the 16 bit counter comes from the CX pin and is enabled disabled by the S W When SRF 8h instruction is executed the counter will be enabled and will start to count the signals on the CX pin The counter will be disabled when SRF 0 instruction is executed Executing MRF1 4 instructions may load the result of the counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically 81 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Example If you intend to count the clock input from the CX pin for a specified time period you can enable the counter by executing SRF 8 instruction and setting timer1 to control the time period Check the overflow flag RFOVF of this counter when the time period elapses If the overflow flag is not set to 1 read the content of the counter if the overflow flag has been set to 1 you must reduce the time period and repeat the previous procedure again In this example use the RR network to generate the clock source Timer 1 is used to enable disable the counter LDS 0 0 Set the TMR1 clock source PH9 LDS 1 3 initiate TMR1 setting value to 3F LDS 2 OFh SHE 2 enable halt release by TMR1 RE ONT LDA 0 OR 1 combine the TMR1 setting value TMS e enable the TMR1 SR
120. nts specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz Lz 00 1FH Ry 0 FH 98 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Table 4 2 The mapping table of LCD latches with the contents of AG and Ry DBUSA DBUSC DBUSG T HLO T HL1 T HL2 T HL3 T HL4 T HL5 T HL6 T HL7 LCD Lz HL Function Description LCT Lz HL Function Description LCB Lz HL Function Description LCP Lz HL Function Description LCDX D Function Description LCD latch Lz TAB HL HL indicates an index address of table ROM The contents of table ROM specified by HL are loaded to the LCD latch specified by Lz directly Refer to Table 4 2 Lz 00 1FH LCD latch Lz data decoder HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 4 2 Lz 00 1FH LCD latch Lz data decoder HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder Refer to Table 4 2 If the content of HL is 0 the outputs of the data decoder are all 0 Lz 00 1FH LCD latch Lz HL AC The contents of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz Refer to Table 4 2 Lz 00 1FH Mullti LCD latches Lz s TAB HL HL indicates an index addre
121. o O or not 60 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual MASK OPTION table Mask Option name RESET PIN TYPE 2 PULSE The following table shows the initial condition of TM8705 in reset cycle Program counter PC Address 000H Start condition flags 1 to 7 SCF1 7 C Ag Li version Backup tag aid EXTV version Stop release enable flags SRF3 4 5 7 A N Switch enable flags 4 SEF3 4 Halt release request flag HRF 0 6 Halt release enable flags 1 HEF1 6 to3 Interrupt enable flags 0 to 3 IEFO 6 Alarm output ALARM Pull down flags in I OC I OD 1 with pull down port resistor Input output ports l OA I OB PORT I OA I OB OC OD P Eu VOC VOD port chattering Cch clock EL panel driver pumping clock source and duty cycle EL panel driver clearing clock Celc source and duty cycle i Frequency generator clock Cia source and duty cycle output is inactive Resistor frequency converter RFC en LCD driver output All lighted mask option Timer 1 2 Watchdog timer WDT Reset mode WDF 0 XT clock slow speed Clock source BCLK clock in dual clock option Notes PH3 the 3rd output of predivider PH10 the 10th output of predivider Mask option can unlighted all of the LCD output J O 61 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 3 2 3 IOC Port Key Matrix RESET Key reset function is selected by mask option When IOC port or key
122. oaded to AC HL amp AC The contents of HL and AC are binary ANDed the result is loaded to AC HL indicates an index address of data memory AC e HL amp AC HL HL 1 The contents of HL and AC are binary ANDed the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC Rx Rx amp AC The contents of Rx and AC are binary ANDed the result is loaded to AC and data memory Rx GHL HL amp AC 113 tenx technology inc Rev 1 2 2003 7 31 Description AND Function Description EOR Rx Function Description EOR HL Function Description EOR HL Function Description EOR Rx Function Description EOR HL Function Description EOR Function Description TM8705 Users Manual The contents of HL and AC are binary ANDed the result is loaded to AC and data memory HL HL indicates an index address of data memory AC HL HL amp AC HL HL 1 The contents of HL and AC are binary ANDed the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory AC e Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC AC e HL 6
123. ogrammable Duty Cycle a Frequency output Divider Generator FREQ SCC x FRQ D Rx BCLK PH0 AC1 AC0 Rx3 Rx0 SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencies and duty cycles corresponding to the presetting data of FRQ related instructions The FRQ related instructions preset a letter N into the programming divider and letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz X 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of data memory and accumulator AC or the table ROM data or operand data specified in the FRQX instruction The following table shows the bit pattern of the combination The following table shows the bit pattern of the preset letter N The bit pattern of preset letter N Programmi bit ng divider le it7 P D HL Notes 1 TO T7 represents the data of table ROM 2 X7 represents the data specified in operand X Poe ons s j me os so Had i ba Ld ld d The following table shows the bit pattern of the preset letter D Preset Letter D Duty Cycle DO 0 l 4duy 0 t 2duy The following diagram shows the output waveform for different duty cycles 0 64 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manu
124. only or DUAL clock operation The usage of 3 58MHz ceramic resonator oscillator or external R type oscillator is defined by mask option XIN XOUT CFIN CFOUT P let beasined as CONS or Open Drain type output COM5 6 could be defined as COMS or Open Drain type output SEG1 40 O Output pins for driving the LCD panel segment 1 1 Input Output port A muxed with SEG24 27 Input Output port B muxed with SEG28 31 Output port C muxed with SEG32 35 OD 4 1 0 Input Output port D muxed with SEG36 39 1 Input Output port D muxed with SEG36 39 port D muxed with SEG36 39 ct 1 input pin and 3 output pins for RFC application muxed with SEG24 27 E ELC ELP O Output port for El panel driver muxed with SEG28 29 BZB BZ O Output port for alarm clock or single tone melody generator muxed with SEG30 31 Ki 16 O Output port for key matrix scanning Shared with SEG1 SEG16 Kl 4 I Input port for key matrix scanning Muxed with SEG32 SEG35 xU GND P Negative supply voltage 1 8 Characteristics ABSOLOUTE MAXIMUM RATINGS GND VDDi 93155 V Maximum Supply Voltage VDD2 0355 V VDD3 0 30085 V Maximum Input Voltage Vin OStoVDDi 2403 V er aA Vou2 O3toVDD3 03 V Maximum Operating Temperature Topg 20to 70 Maxi
125. ontents of Ry D ard CF are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D CF D represents the immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry Ry D CF D represents the immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC lt Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC The carry flag CF will be affected D 0H FH AC Ry Ry D D represents the immediate data The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH AC e Ry D 1 D represents the immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected 116 tenx technology inc Rev 1 2 2003 7 31 SUBI Ry D Function Description ADNI Ry D Function Description ADNI Ry D Function Description ANDI Ry D Function Description ANDI Ry D Function Description EORI Ry D Function
126. op mode to be released STOP Enter the stop mode TRE STOP release MSC 10h Check the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC that causes the stop mode to be released MCX 12h Check the signal change at KI1 4 pins that causes the stop mode to be released 49 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM8705 when LCD is operating During the halt mode the program memory ROM is not in operation and only the oscillator circuit pre divider circuit sound circuit I O port chattering prevention circuit and LCD driver output circuit are in operation If the timer has started operating the timer counter still operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters the halt mode The following 3 conditions are available to release the halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When the halt mode is released and an interrupt is accepted the halt release signal is reset automatically 2 The signal change specified by the SCA instruction is applied to port IOC SCF1
127. or SCG is used Executing SLOW instruction will change the clock source BCLK of the system clock generator SCG to the slow speed oscillator XT clock and the system clock selection flag CSF is reset to 0 Executing FAST instruction will change the clock source BCLK of the system clock generator SCG to the fast speed oscillator CF clock and the system clock selection flag CSF is set to 1 For the operation 4 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual of the system clock generator refer to 3 3 2 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF indicates the operating status of the watchdog timer 3 Overflow flag of 16 bit counter of RFC RFOVF The overflow flag of 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of RFC occurs The flag will reset to 0 when this counter is initiated by executing SRF instruction The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 Bit 3 Bit 2 Bit 1 Bit 0 of 16 bit counter of Enable flag WDF selection flag RFC RFVOF CSF 2 14 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF11 will be set to 1 in STOP mode when the following conditions are met A high level signal comes from the OR ed output of the pins defined as input mode in IOC p
128. ort which causes the stop release flag of IOC port CSR to output and stop release enable flag 4 SRF4 is set beforehand A high level signal comes from the OR ed output of the pins defined as input mode in IOD port which causes the stop release flag of IOD port DSR to output and stop release enable flag 3 SRF3 is set beforehand A high level signal comes from the OR ed output of the signals latch for Kl1 4 which causes the stop release flag of Key Scanning SKI to output and stop release enable flag 4 SRF7 is set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output and the stop release enable flag 5 SRF5 is set beforehand The following figure shows the organization of start condition flag 11 SCF 11 HRF2 scF11 Stop release SRF7 request SRF4 45 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The stop release flags SKI CSR DSR HRF2 were specified by the stop release enable flags SRFx and these flags should be clear before the chip enters the stop mode All of the pins in IOA and IOC port had to be defined as the input mode and keep in 0 state before the chip enters the STOP mode or the program can not enter the STOP mode Instruction SRE is used to set or reset the stop release enable flags SRF4 5 7 The following table shows the stop release request flags The OR ed The OR ed input The rising or latched signals for mode pins of falling
129. ote 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 12 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 2 1 1 2 1 2 BIAS amp STATIC AT AG BATTERY POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 1 3 1 3 BIAS AT AG BATTERY POWER SUPPLY Internal logic MASK OPTION table Mask Option name POWER SOURCE 3 1 5V BATTERY BIAS 3 1 3 BIAS Note 1 The input output ports operate between GND and VDD1 13 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes la
130. output the data to those output latches This will prevent the chattering signal when the IOC pins change to output mode 72 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual bit0 Initial clear SPG Control 1 Data Bus Control 2 IPC OPC This figure shows the organization of IOC port Note If the input level is in the floating state a large current straightthrough current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state IOC port may select the pull low device or low level hold device for each pin by mask option or enable disable this device by program setting When the pull low device and low level hold device are both enabled by mask option the reset will enable the pull low device and disable the low level hold device Executing SPC 10h instruction may also enable the pull low device and disable the low level hold device and executing SPC Oh may disable the pull low device and enable the low level hold device When the IOC pin has been defined as the output mode both the pull low and low level hold devices will be disabled 73 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual MASK OPTION table Pull low function option Mask Option name IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE The low level hold function will not be available when pull low function is not ac
131. requency generator D X Description Loads the data X X7 X0 and D D1 DO to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern preset letter N Programming divider Note X0 X7 represents the data specified in operand X Preset Letter D Duty Cycle Dt 0 1 4 duty x O 1 3 duty L1 1 2 dut 1 1 duty 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D HL The content of table ROM specified by HL as preset data N 3 FROX D X The data of operand in the instruction assigned as preset data N TMS Rx Function Select timer 1 clock source and preset timer 1 Description The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Presetting value of timer 1 E TMS Rx The clock source selection for timer 1 ofo PH Co Ps O J ME NI 1 1 utput of frequency enerator FREQ 129 tenx technology inc Rev 1 2 2003 7 31 TMS HL Function Description TMSXX Function Description TM8705 Users Manual Select timer 1 clock source and preset timer 1 The content of table ROM specified by HI is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Sele
132. rge in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 2 LIBATTERY POWER SUPPLY Operating voltage range 2 4V 3 6V For different LCD bias application the connection diagrams are shown below 2 1 2 1 NO BIAS AT LI BATTERY POWER SUPPLY Application circuit Og ITI z z n BH H x lt B A 8B lt 2 5 5 S S S co U Oo TM8706 MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 1 NO BIAS Note 1 The input output ports operate between GND and VDD2 2 1 2 2 1 2 BIAS AT LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF 14 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size At the backup flag set mode the operating current is increased Therefore the bac
133. ring prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to 0 by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOC interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOC1 to IOCA the input data at the port IOC must be read into the RAM immediately after the halt mode is released 74 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 3 5 4 IOD PORT IOD1 IOD4 pins are MUXed with SEG36 SEG37 SEG38 and SEG39 pins respectively by mask option MASK OPTION table Mask Option name Selected item After the reset cycle the IOD port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPD instruction Executed OPD instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IP D instructions may store the signals applied to the IOD pins in the specified data memory When the IOD pins are defined as the output executing IP D instruction will save the data stored in the output latches in the specified data memory Before executing SPD instruction to define the
134. river pin s set X X7 0 to specify the key matrix scanning output state for each SEGn pin in scanning interval Xe 0 when HEF5 is set to 1 the HALT released request HRF5 Will be set to 1 after the key depressed on the key matrix and then set SCF7 to 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle no matter the key is depressed or not and then set SCF7 to 1 X7X5X4 000 in this setting each scanning cycle only check one specified column K1 K16 on key matrix The specified column is defined by the setting of X3 Xo X3 Xo 0000 active K1 column Xo 0001 active K2 column 102 tenx technology inc Rev 1 2 2003 7 31 SPK Rx Function Description TM8705 Users Manual X3 Xo 1110 active K15 column X3 Xo 1111 active K16 column X7X5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle X5 Xo don t care X7X5X4 010 in this setting the key matrix scanning function will be disable Xs Xo don t care X7X5X4 10X in this setting each scanning cycle check 8 specified columns on key matrix The specified column is defined by the setting of Xs 0 active K1 K8 columns simultaneously 1 active K9 K16 columns simultaneously X2 Xo don t care X7X5X4 110 in this setting each scanning cycle check four specified columns on key matrix
135. rogram counter PC loads the specified address in the operand of instruction All of these jump relative instructions could only address to current page That means when the current page is in page 0 PC1 120 only the range 000h 7FFh is reachable when the current page is in page 1 PC11 1 only the range 800h FFFh is reachable PC current page PC11 specified address in operand e Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 Table 2 1 eo EE ojo cO U co NJN N Initial reset Interrupt 2 INT pin Interrupt 0 input port C or D Interrupt 1 timer 1 interrupt Interrupt 3 pre divider interrupt Interrupt 4 timer 2 interrupt Interrupt 5 Key Scanning interrupt Interrupt 6 RFC counter interrupt Jump instruction Subroutine call P10 to PO Low order 11 bits of instruction operand P6 PS P4 P3 P2 P1 PO P6 P5 P4 P3 P2 P1 PO P11 page register 26 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual When executing the subroutine call instruction or interrupt service routine the contents of the program counter PC are automatically saved to the stack register STACK 2 4 PROGRAM TABLE MEMORY The built in mask ROM is organized with 3072 x 16 bits There are 2 pages memory space in this mask ROM Page 0 covered the address range from 000h to 7FFh and page 1 Page 0
136. s with NOP instruction Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted Instruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are reset to 0 and the corresponding HRF flag will be cleared the interrupt enable flags IEF must be set again in the interrupt service routine as required 3 2 RESET FUNCTION TM8705 contains four reset sources power on reset RESET pin reset IOC port reset and watchdog timer reset When reset signal is accepted TM8705 will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by mask option the one is PH15 2 and the other is PH12 2 Reset signal JUUUUUL IU UU YUU UU UU D DL System clock t Hold 16384 or 2048 clocks for Normal operation internal reset cycle 59 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Internal reset cycle time is PH15 2 MASK OPTION table Mask Option name RESET TIME 1 PH15 2 In this option the reset cycle time will be extended 16384 clocks clock source comes form pre divider long at least Internal reset cycle time is PH12 2 MASK OPTION table Mask Option name Selected item RESET TIME
137. shows the organization of the buzzer output 3 4 1 BASIC BUZZER OUTPUT 66 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output pin or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output in any combination of one signal of FREQ PH3 1024Hz PH4 2048Hz PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz PH12 8Hz PH13 4Hz PH14 2Hz PH15 1Hz The ALM instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope of the modulation output Note 1 The high frequency clock source should only be one of PH3 PH4 PH5 or FREQ and the lower frequency may be any all of the combinations from PH10 PH15 2 The frequencies in corresponding to the input clock of the pre divider PHO is 32768Hz 3 The BZ and BZB pins will output DCO after the initial reset Example Buzzer output generates a waveform with 1KHz carrier and PH15 PH14 envelope LDS 20h OAh ALM 70h Output the waveform In this example the BZ and BZB pins will generate the waveform as shown in the following figure 6 C 1l _ PH14 2Hz P six ra EHE m BZ E l Kass MN Gg DONE ee PH5 1KHZ 3 4 2
138. ss of data memory AC e HL AC HL HL 1 The contents of HL and AC are binary added the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory AC Rx Rx AC 112 tenx technology inc Rev 1 2 2003 7 31 Description ADN HL Function Description ADN Function Description AND Rx Function Description AND HL Function Description AND HL Function Description AND Rx Function Description AND HL Function TM8705 Users Manual The contents of Rx and AC are binary added the result is loaded to AC and data memory Rx The result will not affect the carry flag CF AC HL HL AC The contents of HL and AC are binary added the result is loaded to AC and data memory HL The result will not affect the carry flag CF HL indicates an index address of data memory AC HL HL AC HL HL 1 The contents of HL and AC are binary added the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory AC Rx amp AC The contents of Rx and AC are binary ANDed the result is l
139. ss of table ROM The content of table ROM specified by HL are loaded to several LCD latches Lz simultaneously Refer to Table 4 2 The range of multi Lz is specified by data D D 0 1 Table 4 2 LCTX D Function The range of multi Lz latches D 0 Multi Lz 00H 0FH D 1 Multi Lz 10H 1FH Mullti LCD latch Lz data decoder HL 99 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Description The contents of index RAM specified by HL are loaded to several LCD latches Lz simultaneously The range of multi Lz is specified by data D Refer to Tabel 4 3 D 0 1 LCBX D Function Mullti LCD latch 12 data decoder HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder The range of multi Lz is specified by data D Refer to Table 4 3 D 0 1 LCPX D Function Mullti LCD latch Lz HL AC Description The contents of index RAM specified by HL and the contents of AC are loaded to several LCD latches Lz simultaneously Refer to Table 4 2 The range of multi Lz is specified by data D Refer to Table 4 3 0 1 SPA X Function Defines the input output mode of each pin for port and enables disables the pull low device Description Sets the I O mode and turns on off the pull low device The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Setting
140. ter is reset X8 1 The last 5 bits of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 simultaneously Appendix A TM8705 Instruction Table Instruction Ty gt g O Machine Code 0000 0000 0000 w0 Nooran CSP 0000 001Z ZZZ YYYY 0000 ZZZZ YYYY oxoonzzzzvwv z FP 000 1o0z zzz x eH 0000 z zzzwoi z eose Rony j 0000 1007 ZZZ 0010 0000 1002 ZZZZ 0011 0000 100D 0000 0100 Multi Lz R HL D 0 Multi Lz 00H OFH D 1 Multi Lz 10H 1FH 0000 100D 0000 0101 Muli Lz 7SEG R HL 0000 10000000 0111 Muli Lz R HL AC lt lt C z Ry z HL Z HL Z HL Z HL D B B 0000 1000 0000 0110 SEG lt ROHL 0000 1010 XOX l i OA Rx Pe 0000 1011 DXX XOX 284 e Rx0 Rx1 D Pulse 0000 1100 OOK OB fe RY 0000 1101 OMOWK OO fe RY 0000 1110 Xx fOO fe RY FREQ Rx amp AC m mM 1 3 Duty 1 2 Duty 1 1 Duty 1 1101 OX XOX 1 1110 OX XOX Po 10 0000 0XO XK 133 tenx technology inc Rev 1 2 2003 7 31 J 1 002D OXXX I s 222 gt x x 8 1 010D 0000 0000 1 10DD XXX 1 1100 OXXX XXXX TM8705 Users Manual Machine Code Function Flag Remark ADC HL 10 0000 1000 000 AC e R HL AC CF ADC 0010 0000 1100 0000 AC lt
141. terrupt caused by the IOC port and interrupt service is concluded SIE 24h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter and IOC port Interrupt caused by the INT pin and interrupt service is concluded SIE 20h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter IOC port and INT Interrupt caused by the Key matrix Scanning and interrupt service is concluded All interrupt requests have been processed 58 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service address is executed automatically Refer to Table 3 1 In this case the CPU performs the following services automatically 1 As for the return address of the interrupt service routine the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and the interrupt enable flags are all reset When the interrupt occurs the TM8705 will follow the procedure below Instruction 1 In this instruction interrupt is accepted NOP TM8705 stores the program counter data into the STACK At this time no instruction will be executed a
142. the OPB instruction must be executed to output the data to the output latches This will prevent the chattering signal on the I O pin when the I O mode changed IOB port had built in pull down resistor The pull low device for each pin is selected by mask option and executing SPB instruction to enable disable this device Pull low function option Mask Option name IOB PULL LOW RESISTOR 1 USE IOB PULL LOW RESISTOR 2 NO USE 71 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 3 5 3 IOC PORT IOC1 IOC4 pins are MUXed with KI1 SEG32 KI2 SEG33 KI3 SEG34 and KI4 SEG35 pins respectively by mask option MASK OPTION table EG32 IOC1 KH 2 IOC1 EG33 IOC2 Kl2 2 IOC2 EG34 IOC3 KI3 2 3 EG35 IOCA Kl4 2 IOC4 After the reset cycle the IOC port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPC instruction Executed OPC instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IP C instructions may store the signals applied to the IOC pins in the specified data memory When the IOC pins are defined as the output executing IPC instruction will save the data stored in the output latches in the specified data memory Before executing SPC instruction to define the IOC pins as output the OPC instruction must be executed to
143. tived Low level hold function option Mask Option name C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to IOC4 pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOC port are defined as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPC 1 SPC 2 SPC 4 SPC 8 Interrupt request IOC1 IOC2 IOC3 IOC4 ALT released request chattering prevention PLC 1 Interrupt accept SCC intruction SCA intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex 2 to 4 are held at L level When the signal changes at the input pins of IOC port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF1 At that time the chatte
144. ut When PHO is changed from H level to L level the content of this counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or at the initial reset mode The pre divider delivers the signal to the halver tripler circuit alternating frequency for LCD display system clock sound generator and halt release request signal I O port chattering prevention clock Frequency Interrupt request E HEF3 Halt mode BCLK Initial SCF7 SLOW instruction T1 T2 T3 T4 Sclk PLC 8H R FAST instruction Interrupt HALT release Clock System Falledge HRF3 request flag vue EK switch clock detector circuit generator MSC instruction L Data bus 2 oc CFOSC steh EE To timer circuit circuit ee eee PLC 100H initial EEE ELLE PPE Dual clock option PH1 PHB 5 PH7 PH9 PHi1 PHi3 5 P PH6 PH8 PHi2 PH14 NAE To sound circuit tribler circuit This figure shows the Pre divider and its Peripherals The PH14 delivers the halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of pre divider is PHO and 4 kinds of frequency of PHO cou
145. utput L ol 1uUA 1 2 Voltage ol 1uA 3 Output H oh 10uA 1 2 Voltage oh 10uA 3 ollh 10uA 1 2 Voltage ol h 10UA 3 ollh 10uA 1 2 Voltage i loV h 1 0UA 3 Vol12i llol 10uA 1 2 Voltage Vol3i lol210uA 23 lt 3 N N eiii lt 3 N e lt 10 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual 1 9 TYPICAL APPLICATION CIRCUIT This application circuit is simply an example and is not guaranteed to work LCD Pand 3 58MHz 3h Crysta COM1 6 SEG1 40 olu E q EL Plant IOA IOB IOC IOD Choke Buze 8 1 4 Key Scanning Key Marix Ag power mode 1 3 Bias 1 6 Duy 11 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Chapter 2 TM8705 Internal System Architecture 2 1 Power Supply TM8705 could operate at Ag Li and EXTV 3 types supply voltage all of these operating types are defined by mask option The power supply circuitry also generated the necessary voltage level to drive the LCD panel with different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias and no bias application 2 1 1 Ag BATTERY POWER SUPPLY Operating voltage range 1 2V 1 8V For different LCD bias application the connection diagrams are shown below 2 1 1 1 NO LCD BIAS NEED AT Ag BATTERY POWER SUPPLY Application circuit IIT ug TM8705 MASK OPTION table Mask Option name POWER SOURCE 3 1 5V BATTERY BIAS 1 NO BIAS N
146. x Ek m PSTB1Ah 1AH Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD outputs could be turned off without changing the segment data Executed SF2 4h instruction could turn off the display simultaneously and executed RF2 4h could turn on the display with the patterns before turned off These two instructions will not affect the content stored in the latch circuitry When the LCD is turned off by executing RF2 4h instruction the program could still execute LCT LCB LCP and LCD instructions to update the content in the latch circuitry and the new content will be outputted to the LCD while the display is turned on again In stop state all COM and SEG outputs of LCD driver will automatically switch to the GND state to avoid the DC voltage bias on the LCD panel 4 3 2 Relative Instructions 1 LCT Lz Ry 94 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 2 LCB Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUSA to DBUSH are all 0 when the input data of the data decoder is 0 3 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA to DBUSH without passing throug
147. xecution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Reserved The overflow flag Watchdog timer System clock of 16 bit counter of enable flag WDF selection flag RFC RFOVF CSF 5 6 INDEX ADDRESS INSTRUCTIONS MVU Rx Function U Rx AC Description Loads content of Rx to index address buffer U U3 Rx 3 U2 Rx 2 U1 Rx 1 U0 Rx 0 MVH Rx Function H Rx AC Description Loads content of Rx to index address buffer H 123 tenx technology inc Rev 1 2 2003 7 31 TM8705 Users Manual H3 Rx 3 H2 Rx 2 H1 Rx 1 MVL Rx Function L Rx Description Loads content of Rx to index address buffer L L3 Rx 3 L2 Rx 2 L1 Rx 1 L0 Rx 0 CPHL X Function If HL X force next instruction as NOP Description Compare the content of index register HL in lower 8 bits H and L with the immediate qata X Note In the duration of comparison the index address all the interrupt enable flags IEF has to be cleared to avoid malfunction If the compared result is equal the next executed instruction that behind CPHL instruction will be forced as NOP If the compared result is not equal the next executed instruction that behind CPHL instruction will operate normally The comparison bit pattern is shown below CPHLX X7 X5 x4 x3 x2 XO IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO 5 7 DECIMAL ARITHMET
148. y added the result is loaded to AC The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected AC Rx Rx AC The contents of Rx and AC are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected AC HL HL AC The contents of HL and AC are binary added the result is loaded to AC and data memory HL HL indicates an index address of data memory Carry flag CF will be affected AC HL HL AC HL HL 1 The contents of HL and AC are binary added the result is loaded to AC and data memory HL The content of index register HL will be increment automatically after executing this instruction HL indicates an index address of data memory Carry flag CF will be affected AC lt Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected AC HL AC B 1 The content of AC is binary subtracted from content of OHL the result is loaded to AC HL indicates an index address of data memory Carry flag CF will be affected AC e HL AC B 1 HL HL 1 The content of AC is binary subtracted from content of OHL the result is loaded to AC The content of index register HL will be increment automatically after executin

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