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CardS12

1. set up timing parameters for 125kbps bus speed and sample point at 87 5 complying with CANopen recommendations fOSC 16MHz prescaler 8 gt ltq 16MHz 8 1 0 5us tBIT tSYNCSEG tSEGI tSEG2 ltq 13tq 2tq 16tq 8ps BUS tBIT 1 125kbps CANOBTRO 0x07 sync jump width 1tq br prescaler 8 CANOBTRI Oxlc one sample point tSEG2 2tq tSEG1 13tq we are going to use four 16 bit acceptance filters CANOIDAC 0x10 set up acceptance filter and mask register 1 7 6 5 4 3 2 i Oo 7 6 5 4 3 2 1 0 ID10 ID9 ID8 ID7 ID6 ID5 IDA ID3 ID2 IDI IDO RTR IDE XXX XXX XXX we are going to detect data frames with standard identifier 11 bits only so bits RTR bit4 and IDE bit3 have to be clear CANOIDARO idar 8 top 8 of 11 bits CANOIDAR1 idar amp Oxe0 remaining 3 of 11 bits CANOIDMRO idmr gt gt 8 top 8 of 13 bits CANOIDMRI idmr amp Oxe0 0x07 remaining 3 bits RTR IDE set up acceptance filter and mask register 2 3 4 just as 1 25 CardS 12 CANOIDAR6 CANO CANOIDAR7 CANO CANOIDMR6 CANO CANOIDMR7 CANO CANOCTLO amp BM while CANOCTL1 CANOTBSEL BM T BOOL testCANO void IDAR4 CANOIDAR2 CANOIDARO IDARS CANOIDAR3 CANOIDARI IDMR4 CANOIDMR2 CANOIDMRO IDMR5 CANOIDMR3 CANOIDMRI INITRQ exit Init Mode amp BM INITAK 0 wait until Normal Mode is esta
2. BM_MSSL BM_TXRX back to transmit mode still master bval IBDR get received byte return bval The IIC Bus signals can be accessed at X5 47 48 CAN Interface The MC9S12D64 contains one CAN Module designated as CANO CANDO utilizes the port pins PMO and PM1 IC4 serves as a CAN physical bus interface It is a high speed interface chip commonly used in industry applications R9 determines the slope control setting must 24 User Manual be modified for high speed communication see datasheet R8 is a termination resistor which becomes necessary if the CardS12 is the last node in a CAN bus chain Close the connection between pins 1 and 2 of X2 in this case otherwise keep it open If CANO is not used BR9 can be opened to make the MCU pin PMO available as general purpose I O pin It can be accessed at X5 41 and PMI at X5 42 The following listing demonstrates some basic functions of CAN bus communication include datatypes h include lt mc9s12d64 h gt include s12 can h Defines Func initialize CAN Args Retn Note void initCANO UINT16 idar UINT16 idmr CANOCTLO BM INITRQ request Init Mode while CANOCTL1 amp BM INITAK 0 wait until Init Mode is established set CAN enable bit deactivate listen only mode and use Oscillator Clock 16MHz as clock source CANOCTLI BM CANE
3. CardS2 Hardware Version 1 00 User Manual April 11 2005 CardS12 Copyright C 2003 2005 by ELMICRO Computer GmbH amp Co KG Hohe Str 9 13 D 04107 Leipzig Germany Tel 49 0 341 9104810 Fax 49 0 341 9104818 Email leipzig 9 elmicro com Web http elmicro com This manual and the product described herein were designed carefully by the manufacturer We have made every effort to avoid mistakes but we cannot guarantee that it is 100 free of errors The manufacturer s entire liability and your exclusive remedy shall be at the manufacturer s option return of the price paid or repair or replacement of the product The manufacturer disclaims all other warranties either expressed or implied including but not limited to implied warranties of merchantability and fitness for a particular purpo se with respect to the product including accompanying written material hardware and firmware In no event shall the manufacturer or its supplier be liable for any damages whatsoever including without limitation damages for loss of business profits business interruption loss of business information or other pecuniary loss arising out of the use of or inability to use the product even if the manufacturer has been advised of the possibility of such damages The product is not designed intended or authorized for use in applications in which the failure of the product could create a situation where personal injury or dea
4. dc dc dc dc dc dc dc de dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc EU EET ELELEE ELEELELELELEELEEEELELELELEELEELEELELEELEELEELELEELELEELELELELELELELEELEELELELEELELEELEELELEELELELELELELELELE LL TP RAMTOP 189 TP RAMTOP 186 TP RAMTOP 183 TP RAMTOP 180 TP RAMTOP 177 TP RAMTOP 174 TP RAMTOP 171 TP RAMTOP 168 TP RAMTOP 165 TP RAMTOP 162 TP RAMTOP 159 TP RAMTOP 156 TP RAMTOP 153 TP RAMTOP 150 TP RAMTOP 147 TP RAMTOP 144 TP RAMTOP 141 TP RAMTOP 138 TP RAMTOP 135 TP RAMTOP 132 TP RAMTOP 129 TP RAMTOP 126 TP RAMTOP 123 TP RAMTOP 120 TP RAMTOP 117 TP RAMTOP 114 TP RAMTOP 111 TP RAMTOP 108 TP RAMTOP 105 TP RAMTOP 102 TP RAMTOP 99 TP RAMTOP 96 TP RAMTOP 93 TP RAMTOP 90 TP RAMTOP 87 TP RAMTOP 84 TP RAMTOP 81 TP RAMTOP 78 TP RAMTOP 75 TP RAMTOP 72 TP RAMTOP 69 TP RAMTOP 66 TP RAMTOP 63 TP RAMTOP 60 TP RAMTOP 57 TP RAMTOP 54 TP RAMTOP 51 TP RAMTOP 48 TP RAMTOP 45 TP RAMTOP 42 TP RAMTOP 39 TP RAMTOP 36 TP RAMTOP 33 TP RAMTOP 30 TP RAMTOP 27 TP RAMTOP 24 TP RAMTOP 21 TP RAMTOP 18 TP RAMTOP 15 TP RAMTOP 12 TP RAMTOP 9 TP RAMTOP 6 TP RAMTOP 3 main reserved reserved reserved reserved reserved reserved PWM Emergency Shutdown Port P CANA transmit CANA receive CANA errors CANA wake up CAN3 tr
5. access to the Inter IC Bus module IIC DC TC of the MC9S12D64 Since the IIC Bus is implemented as a hardware module an IIC software emulation is obsolete For the two IIC Bus signals SDA SCL pull up resistors are required They can be equipped on board R10 R11 or provided exter nally The following listing shows a simplified Master Mode implementa tion without interrupt usage File S12 IIC C V1 00 Func Simplified I2C Inter IC Bus Master Mode implementation using the IIC hardware module of the HCS12 Rem For a real world implementation an interrupt driven scheme should be preferred See AppNote AN2318 and accompanying software Hard External pull ups on SDA and SCL required Value should be 1k 5k depending on cap bus load Note Adjust IBFD value if ECLK is not 8MHz t222 a sasssesaseeceesessasssessssesssssssssssess include datatypes h include mc9s12d64 h include s12 iic h L 2 GOde AO Func Initialize IIC module Args Retn void initIIC void IBFD 0x18 100kHz IIC clock at 8MHz ECLK IBFD Oxlf 100kHz IIC clock at 24MHz ECLK IBCR BM IBEN enable IIC module still slave IBSR BM IBIF BM IBAL clear pending flags just in case Func Issue IIC Start Condition Args Retn void startIIC void while IBSR amp BM_IBB 0 wait if bus busy i CAUTION no loop time limit imp
6. automatically usually controlled by a PC based debugging program Integrated A D Converter The MC9S12Dxx contains two 10 bit Analog to Digital Converter modules Each module ATDO ATD1 provides eight multiplexed input channels VRH is the upper reference voltage for all A D channels On the CardS12 VRH is connected to VDDA 5V through solder bridge BRI After opening BRI it is possible to use an external reference voltage 16 User Manual The following example program shows the initialization sequence for the A D converter module ATDO and a single channel conversion routine The source file S12 ATD C also contains some additional functions for the integrated ATD module include datatypes h tinclude hcsl2dp256 h include s12 atd h Edo C CERT E DEN EE Func Initialize ATD module Args Retn void initATDO0 void enable ATD module ATDOCTL2 BM ADPU 10 bit resolution clock divider 12 allows ECLK 6 24MHz 2nd sample time 2 ATD clocks ATDOCTL4 BM PRS2 BM PRSO Func Perform single channel ATD conversion Args channel 0 7 Retn unsigned left justified 10 bit result UINT16 getATDO UINT8 channel select one conversion per sequence ATDOCTL3 BM S1C right justified unsigned data mode perform single sequence one out of 8 channels ATDOCTL5 BM DJM channel amp 0x07 wait until Sequence Complete Flag set CAUTIO
7. controller is to issue a stable reset condition if the power supply falls below the level required for proper MCU operation To prevent collisions with the bidirectional RESET pin of the MCU the LVI circuit IC2 has an open drain output In the inactive state it is pulled up high by the resistor R6 The detector treshold of IC2 is typically 4 6V which is slightly higher than the required minimum MCU operating voltage of 4 5V 13 CardS12 Furthermore IC2 is capable of stretching the reset output to filter out short pulses on the power supply effectively The duration of that delay can be selected using the capacitor C14 A value of 100nF results in a delay of approx 50 80ms It is important to note that this delay will only be applied during a power cycle event IC2 will not stretch pulses coming from the MCU s internal reset sources This is essentially important since otherwise the MCU would not be able to detect the source of a reset This would finally lead to a wrong reset vector fetch and could result in a system software crash Please be aware that also a capacitor on the reset line would cause the same fatal effect therefore external circuitry connected to the RESET pin of a HC12 HCS12 MCU should never include a large capacitance Clock Generation and PLL The on chip oscillator of the MC9S12Dxx can generate the primary clock OSCCLK using a quartz crystal Q1 connected between the EXTAL and XTAL pins The allowed
8. device connection to a PC etc 2 3 RS232 configured as host connection to a serial LCD etc BR8 LCD Power Supply SER1 open VCC not available on RS232 port SERT standard Sub D connector layout closed VCC available on RS232 port SERI at Pin 9 of the Sub D connector BR9 RXCANO open Port pin RXCANO PMO freely available closed RXCANO connected to CAN Transceiver ICA Factory Default Setting 10 User Manual 5 Mechanical Dimensions The following table summarizes the mechanical dimensions of the CardS 12 The values provide a basis for the design of carrier boards etc Please note Always check all mechanical dimensions using the real hardware module The reference point 0 0 is located at the south west corner of the PCB The PCB is orientated horizontally as shown in the Parts Location Diagram see above All data for holes drills B refer to the center of the hole drill connectors X are referenced by pin 1 kom Yin inch 11 CardS 12 6 Circuit Description In this section a number of details will be presented on how to work with the HCS12 in general and the CardS12 Controller Module in particular Please be aware that even if this manual can provide some specific hints it is impossible to cover all kinds of knowledge and techniques required to design a microcontroller application Please refer to the data sheets of the silicon vendors and to the manuals
9. frequency range is 0 5 to 16MHz As usual two load capacitors are part of the oscillator circuit C1 C2 However this circuit is modified compared to the standard Pierce oscillator that was widely used for the HC11 and HC12 and was added to newer HCS12 deriates as an oscillator configuration option On CardS12 the MC9S12Dxx uses a Colpitts oscillator with trans lated ground scheme The main advantage is a very low current consumption though the component selection is more critical The CardS 12 circuit uses a high quality 16MHz quartz crystal together with two load capacitors of only 3 9pF Furthermore special care was taken for the PCB design to introduce as little stray capacitance as possible in respect to XTAL and EXTAL With an OSCCLK of 16MHZz the internal bus speed ECLK becomes 8MHz by default To realize higher bus clock rates the PLL has to be engaged The MC9S12D64 can be operated with a bus speed of up to 25MHz though most designs use 24MHz because this value is a better basis to generate a wide range of SCI baud rates 14 User Manual A passive external loop filter must be placed on the XFC pin The filter R3 C3 C4 is a second order low pass filter to eliminate the VCO input ripple The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL If PLL usage is not required the XFC pin must be tied to VDDPLL The choice of fil
10. of your software tools to get additional information The software demos included in this paragraph are for demonstra tion puposes only Please note that we cannot guarantee for the correct ness and fitness for a particular purpose Schematic Diagram To ensure best visibility of all details the schematic diagram of the CardS 12 is provided as a separate document Controller Core Power Supply The nominal operating voltage of the MC9S12D64 is 5V This MCU IC1 has three supply pin pairs VDDR VSSR VDDX VSSX and VDDA VSSA Internally the MCU uses a core voltage of only 2 5V The necessary voltage regulator is already included in the chip as well as 5V I O buffers for all general purpose input output pins There fore the MCU behaves like a 5V device from an external point of view There is just one exception the signals for oscillator and PLL are based on the core voltage und must not be driven by 5V levels High level on the pin VREGEN is needed to enable the internal voltage regulator The three terminal pairs mentioned above must be decoupled carefully A ceramic capacitor of at least 100nF should be connected directly at each pair C15 C16 C17 It is recommended to add a 10uF electrolytic or tantalum capacitor per node especially if some MCU port pins are loaded heavily C5 C6 C7 Special care must be taken 12 User Manual with VDDA since this is the reference point VDDA 2 for the internal voltage regul
11. power supply e g here GND to X7 pin 2 5V to X7 pin 1 Check voltage and polarity before making the connection Once powered up the Monitor program will start display a message and await your commands We hope you will enjoy working with CardS121 CardS 12 3 Parts Location Diagram o000000000000000000000000 O SCEEEFEEEEEEEEEEEEEEEEREE x5 x1 o RIZ RI x2 Hlo o oj loo lo oo lool 000000000000 000000000000 0000 Ejsns BR4 BR2 BR3 BRSILI 0000000000000000000000000 O 0000000000000000000000000 Solder Bridges on the solder side of the PCB User Manual 4 Jumpers and Solder Bridges Jumpers There are no jumpers present on this board Solder Bridges On the solder side of the module the following solder bridges can be found BR1 VRH open external supply of VRH required closed VRH connected to VDDA VCC on board BR2 TIIN open Port pin TXDO PS1 freely available closed TXDO connected to RS232 Transceiver IC3 BR3 T2IN open Port pin TXDI PS3 freely available closed TXDI connected to RS232 Transceiver IC3 BRA RIOUT open Port pin RXDO PSO freely available closed RXDO connected to RS232 Transceiver IC3 BR5 R2OUT open Port pin RXDI PS2 freely available closed RXDI connected to RS232 Transceiver IC3 Factory Default Setting CardS 12 BR6 BR7 RS232 TxD RxD Select SER1 l 24 RS232 configured as
12. 12DP512 512KB Flash 4KB EEPROM e 14KB RAM 3x SPI four additional msCAN modules no drivers on board CardS 12 Package Contents Controller Module with MC9S12D64 CardS12 D64 or MC9S12DG256 CardS12 DG256 or MC9S12DP512 CardS12 DP512 TwinPEEKs Monitor in the MCU s Flash Memory RS232 cable Sub D9 two header connectors 2x25 pins each power connector User Manual this document Schematic Diagrams CD ROM contains assembler software data sheets CPU12 Reference Manual code examples C compiler evaluation version etc NIN ji jii in ezz J A 2 0 06 n y a 9 0 200000090 Controller Modul CardS12 D64 User Manual 2 Quick Start Nobody likes to read big manuals For that reason we will summa rize the most important things in the following section If you need additional information please refer to the more detailed sections of this manual Here is how you can start Please check the board for any damages due to transportation Connect the Controller Module via RS232 to a PC The connec tion between CardS 12 interface SERO connector X3 and PC is simply made using the flat ribbon cable which is in the box On the PC start a Terminal Program An easy to use Terminal Program is OC Console which is available at no charge from our Website Select a baudrate of 19200 Bd Disable all hardware or software protocols Connect a stabilized
13. By opening these solder bridges the controller signals can be used for other purposes The signals can be accessed at connector X6 X3 SCIO is used as the primary RS232 interface To connect the CardS 12 to a PC a 10 wire flat ribbon cable can be used The cable must have a 10 pin female header connector at the CardS12 side X3 and a female Sub D9 connector at the PC side The above is valid for X4 SCI1 as well provided that BR6 and BR7 are in position 1 2 In this case the PC serves as the host and CardS 12 is configured as device 20 User Manual The reverse configuration can be used to connect a serial LC display to X4 In this case the CardS12 is the host and the LCD is the device The required signal crossing is done by changing BR6 and BR7 to position 2 3 Additionally it might be useful to close BR8 in order to supply the LCD module via pin 9 of the Sub D9 connector Caution this is not conform with RS232 standard Serial alphanumeric LC Displays are offered by a number of manufacturers such as the Canadian company Matrix Orbital http www matrixorbital com The following code example shows how to use SCIO in polling mode include datatypes h include hcsl2dp256 h include s12 sci h Code void initSCIO UINT16 bauddiv SCIOBD bauddiv amp Oxlfff baudrate divider has 13 bits SCIOCRI 0 mode 8N1 S
14. CIOCR2 BM TEHBM RE Transmitter 4 Receiver enable UINT8 getSCIO void while SCIOSR1 amp BM RDRF 0 return SCIODRL void putSCIO UINT8 c while SCIOSR1 amp BM TDRE 0 SCIODRL c 21 CardS 12 SPI Bus The MC9S12D64 contains one SPI module SPIO which can be used for synchronous serial communication with external SPI chips SPIO consists of four individual signals MISO MOSI SCK and SS MCU port pins PS4 to PS7 These signals are not used on bord the CardS12 though they can be accessed through the header connec tors at the edges of the board The following listing demonstrates some basic functions initializa tion 8 bit data transfer for the SPI Port SPIO chip select signal handling not included finclude datatypes h include hcs12dp256 h include s12 spi h Code void initSPIO UINT8 bauddiv UINT8 cpol UINT8 cpha DDRS 0xe0 SS SCK MOSI Output SPIOBR bauddiv set SPI Rate enable SPI Master Mode select clock polarity phase SPIOCRI BM SPE BM MSTR cpol 7 BM CPOL 0 cpha 7 BM_CPHA 0 SPIOCR2 0 as default UINT8 xferSPIO UINT8 abyte SPIODR abyte start transfer while SPIOSR amp BM SPIF 0 wait until transfer finished return SPIODR read back data received 22 User Manual IIC Bus The port pins PJ6 and PJ7 grant
15. CTOR return 7 item no EETS START item no lt lt 2 return wrSectEETS UINT16 item no UINT16 item INT8 readItemEETS UINT16 item no void item if item no gt EETS MAX SECTOR return 7 item no EETS START item no lt lt 2 UINT16 item UINT16 item no UINT16 item 1 UINT16 item no 41 return 0 19 CardS 12 Indicator LED Port pin PH7 drives a single indicator LED D2 To control this LED some simple macros can be used as shown in the following C header file ifndef CARDS12 LED H define CARDS12 LED H Macros define initLED PORTH l 0x80 DDRH l 0x80 define offLED PORTH 0x80 define onLED PORTH amp 0x80 tdefine toggleLED PORTH 0x80 Function Prototypes module contains no code endif __CARDS12_LED_H 8 8 8 RS232 Interfaces The MC9S12Dxx provides two asynchronous serial interfaces SCIO SCI1 Each interface has one receive line and one transmit line RXDx TXDx Handshake lines are not provided by the SCI module they can be added by using general purpose I O port lines if required On CardS12 the signals of both SCIs are connected to an industry standard RS232 line transceiver circuit IC3 through solder bridges BR2 BR5 which are closed by default
16. F Control Registers 1KB of total 4KB EEPROM 0400 07FF the area below 0400 is hidden by control registers the top 2048 bytes by the RAM 14KB RAM 0800 S3FFF m PEEKs uses the top 512 bytes 4000 7FFF 16KB Flash equals Page 3E 16KB Flash page 20 8000 SBFFF anv Page 20 3F selectable by PPAGE 16KB Flash equals Page 3F 9E090 4SRFRE TwinPEEKs uses the top 4KB Note Due to a mask set erratum of the MC9S12DP512 Mask Set 4LO0M and earlier not only the monitor code in page 3F is write protected but also an additional area starting at B000 up to BFFF in page 3B Consequently the monitor can not download user code to this region However the whole Flash memory including the write protected areas can be programmed using a BDM tool at any desired time 36
17. N no loop time limit implemented while ATDOSTATO amp BM SCF 0 read result register return ATDODRO 17 CardS 12 Integrated EEPROM The internal EEPROM module of the MC9S12D64 contains IKB of memory It consists of 256 sectors with 4 bytes 32 bits per sector For erasure any single sector can be selected Programming is done by words 2 bytes Read accesses can be made to any word or byte After reset the EEPROM module of the MC9S12D64 is mapped both to address 0x0000 and at the same time to address 0x0400 However in the lower area 0x0000 0x03FF control registers take precedence over EEPROM The EEPROM module can be relocated to any 2KB boundary see INITEE control register In the following example the EEPROM module is left at it s default position The initialization sequence just takes care for setting up the EEPROM Clock Divider according to the quartz crystal frequen cy The write function wrSectEETS copies two words 4 bytes from source address src to EEPROM address dest dest must be identical to an EEPROM sector border aligned 32 bit value If the sector is not erased erased state OxEFFFFFFF the routine will perform a sector erase before writing to the sector The access functions readItemEETS and writeltemEETSO provide a more abstract way to deal with EEPROM contents Instead of using certain addresses which must be part of the EEPROM address range these routines use abstract
18. ansmit CAN3 receive CAN3 errors CAN3 wake up CAN2 transmit CAN2 receive CAN2 errors CAN2 wake up CANI transmit CANI receive CANI errors CANI wake up CANO transmit CANO receive CANO errors CANO wake up FLASH EEPROM SPI2 SPI1 LIG BDLC Self Clock Mode PLL Lock Pulse Accu B Overflow MDCU Port H Port J ATD1 ATDO SCIL SCIO SPIO Pulse Accu A Input Edge Pulse Accu A Overflow Timer Overflow TC7 TC6 TC5 TCA TC3 TC2 TCL TCO RTI IRQ XIRQ SWI Illegal Opcode COP Fail Clock Monitor Fail Reset 30 User Manual Usage A TwinPEEKs command is comprised by a single character follo wed by a number of arguments as required All numbers are hexadeci mal numbers without prefix or suffix Both upper and lower case letters are allowed The CPU s visible address range is 64KB therefore address arguments are not longer than 4 digits An end address always refers to the following not included address For example the command D 1000 1200 will display the address range from 1000 to including 11FF User input is handled by a line buffer Valid ASCII codes are in the range from 20 to 7E Backspace 08 will delete the character left of the cursor The lt ENTER gt key 0A is used to conclude the input The monitor prompt always displays the current program page i e the contents of the PPAGE register Monitor Commands Blank Check Syntax B Blank check whole Flash M
19. ator The internal core voltage appears at the pin pairs VDDI VSSI VDD2 VSS2 and VDDPLL VSSPLL which have to be decoupled as well C19 C20 C21 A static current draw from these terminals is not allowed This is especially true for VDDPLL which serves as the reference point for the external PLL loop filter combination R3 C3 C4 There are two MCU pins VRH VRL to define the upper and lower voltage limits for the internal analog to digital ATD converter While VRL is grounded VRH is connected to VDDA via solder bridge BRI C18 is used for decoupling VRH can be supplied externally after opening solder bridge BR1 This can be useful if the main supply is not in the desired tolerance band or if the ATD should work with a reference value lower than 5V VRH must not exceed VDDA regard less of the selected supply mode The TEST pin is used for factory testing only in an application circuit this pin always has to be grounded Reset Generation RESET is the MCU s active low bidirectional reset pin As an input it initializes the MCU asynchronously to a known start up state As an open drain output it indicates that a system reset internal to MCU has been triggered The HCS12 MCUs already contain on chip reset generation circuitry including power on reset COP watchdog timer and clock monitor It is however necessary to add an external Low Voltage Inhibit LVI circuit also referred to as reset controller The task of this reset
20. blished X0 use only TX buffer 0 Uf Ss l SS SS Ss a M RXF 0 return FALSE if CANORFLG amp B return TRUE UINT8 getCANO void UINT8 c while CANORFLG c CANORXFG 4 CANORFLG BM RX return c void putCANO UINT16 while CANOTFLG CANOTXFG 0 ki CANOTXFG 1 CANOTXFGHA Fl ll CANOTXFG 12 CANOTXFG 13 CANOTFLG BM_TX canid gt gt 8 amp BM RXF 0 Ji F canid UINT8 c amp BM TXEO Qy ue AL canid amp Oxe0 Gr 1 0 EO wait until CAN RX data pending save data clear RX flag wait until Tx buffer released destination address one byte data priority 0 highest initiate transfer 26 User Manual 7 Application Hints Behaviour after Reset As soon as the reset input of the microcontroller is released the MCU reads the Interrupt Vector at memory address FFFE F and then jumps to the address found there In the default delivery condition of the CardS12 the Flash module of the MCU contains the TwinPEEKs Monitor Program The reset vector points to the start of this Monitor Software As a result the monitor will start immediately after reset Startup Code Every Microcontroller firmware starts with a number of hardware initialization commands For the CardS12 only setting up the stack pointer is crucial While it was important for HC12 derivatives to disable the Watchdog the COP Watchdog
21. e word is missing TwinPEEKs will append an FF byte in this case so it is able to perform the word write The problem occurs if the byte stream continues with the follo wing S Record line The byte that was missing in the first attempt 28 User Manual would require a second write access to the same word address which is not allowed As a consequence a write error not erased will be issued To avoid this problem it is necessary to align all S Record data before programming This can be done using the freely available Freescale Tool SRECCVT SRECCVT m 0x00000 Oxfffff 32 o outfile lt infile gt A detailed description of this tool is contained in the SRECCVT Reference Guide PDF Please note that it is not possible to program or erase the part of Flash memory that contains the monitor code Also the last 16 bytes of the EEPROM block are reserved for system use Redirected Interrupt Vectors The interrupt vectors of the HCS12 are located at the end of the 64KB memory address range which falls within the protected monitor code space Therefore the application program can not modify the interrupt vectors directly To provide an alternative way the monitor redirects all vectors except the reset vector to RAM The procedure is similar to how the HC11 behaved in Special Bootstrap Mode The application program can set the required interrupt vectors during runtime before global interrupt enable by plac
22. emory ex monitor code space If Flash memory is not blank then display number of first page containing a byte not equal to FF Dump Memory Syntax D adr1 adr2 Display memory contents from address adr1 until address adr2 If end address adr2 is not given display the following 40 bytes Memory location adr1 will be highlighted in the listing 31 CardS 12 Edit Memory Syntax E addr byte Edit memory contents In the command line the start address addr can be followed by up to four data bytes byte thus allowing byte word and doubleword writes The write access will be performed immediately and then the function will return to the input prompt If the command line did not contain any data byte the interactive mode will be started The monitor is able to identify memory areas which can only be changed on a word by word basis Flash EEPROM In such cases the monitor always awaits and uses 16 bit data To exit the interactive mode simply type Q Additional commands are lt ENTER gt next address previous address same address exit like Q Fill Memory Syntax F adri adr2 byte Fill memory area starting at address adr1 and ending before adr2 with the value byte Goto Address Syntax G addr Call the application program at address addr Note there is no regular way for the application program to return to the monitor Help Syntax H Display a brief command overview 32 U
23. er Reset 0 0 eee 27 Stait p Code danna DR A Rr I RR Re EDU Re 6 27 Additional Information on the Web ss 27 CardS 12 B TwinPEEKSs Monitor Xmas ABAKA NAK debes 28 Serial Communication eee 28 Autostart Function 0 00 eee eee 28 Write Access to Flash and EEPROM sss 28 Redirected Interrupt Vectors L eee 29 Usage coisa cian PAP 31 Monitor Commands 0 0 0 cece eee eee eee es 31 9 Memory Map wax kwa ni i bI Ee RS REIR PES ie 35 User Manual l Overview CardS12 is an easy applicable credit card sized Controller Module based on the 16 bit microcontroller family HCS12 by Freescale formerly Motorola The CardS12 module provides an easy way to evaluate the microcontroller unit It is a versatile tool for rapid prototy ping and a very cost effective off the shelf solution for low and mid volume series applications The CardS12 is equipped with a MC9S12D64 microcontroller unit MCU It contains a 16 bit HCS12 CPU 64KB of Flash memory 4KB RAM IKB EEPROM and a large amount of peripheral function blocks such as SCI SPI CAN IIC Timer PNM ADC and General Purpose I Os The MC9S12D64 has full 16 bit data paths throughout An integrated PLL circuit allows adjusting performance Vs current consumption according to the needs of the user application There are two more versions of CardS 12 available CardS12 DG256 is equipped with a MC9S12DG256 m
24. icrocontroller and CardS12 DP512 uses a MC9S12DP512 For HCS12 microcontrollers a wide range of software tools monitors C compilers BDM debuggers is available to accelerate the development process CardS 12 Technical Data MCU MC9S12D64 with LQFP112 package SMD HCS12 16 bit CPU uses same programming model and command set as the HC12 16 MHz crystal clock up to 25 MHz bus clock using PLL 64KB Flash 1KB EEPROM 4KB RAM 2x SCI asynch serial interface e g RS232 LIN 1x SPI synch serial interface 1x IIC Inter IC Bus 1x msCAN Module CAN 2 0A B compatible one channel equipped with on board high speed physical interface driver 8x 16 Bit Timer Input Capture Output Compare 8x PWM Pulse Width Modulator 16 channel 10 bit A D Converter BDM Background Debug Mode Interface std 6 pin connector Special LVI circuit reset controller two serial interfaces with RS232 transceiver e g for PC connection 2nd serial port can directly drive a serial LC display unit Indicator LED Reset Button up to 87 free general purpose I Os all I O signals signals brought out on header connectors SV operating voltage current consumption 50 mA typ Mech Dimensions 2 1 x 3 4 User Manual Extended Features of CardS12 DG256 e MCU MC9S12DG256 e 256KB Flash 4KB EEPROM e 12KB RAM 3x SPI additional msCAN module busdriver circuit not included Extended Features of CardS12 DP5 12 MCU MC9S
25. ing a jump instruction into the RAM pseudo vector The following example shows the steps to utilizy the IRQ interrupt ldaa i4 06 JMP opcode to staa 3FEE IRQ pseudo vector ldd fisrFunc ISR address to std S3FEF IRQ pseudo vector 1 For a C program the following sequence could be used install IRQ pseudo vector in RAM if running with TwinPEEKs monitor unsigned char 0x3fee 0x06 JMP opcode void void Ox3fef isrFunc 29 CardS 12 The following assembly listing is part of the monitor program It shows the original vector addresses 1st column from the left as well as the redirected addresses in RAM 2nd column FF80 FF82 FF84 FF86 FF88 FF8A FF8C FF8E FF90 FF92 FF94 FF96 FF98 FF9A FF9C FF9E FFAO FFA2 FFAA FFA6 FFA8 FFAA FFAC FFAE FFBO FFB2 FFB4 FFB6 FFB8 FFBA FFBC FFBE FFCO FFC2 FFC4 FFC6 FFC8 FFCA FFCC FFCE FFDO FFD2 FFD4 FFD6 FFD8 FFDA FFDC FFDE FFEO FFE2 FFEA FFE6 FFE8 FFEA FFEC FFEE FFFO FFF2 FFFA FFF6 FFF8 FFFA FFFC FFFE 3F43 3F46 3F49 3F4C 3F4F 3F52 3F55 3F58 3F5B 3F5E 3F61 3F64 3F67 3F6A 3F6D 3F70 3F73 3F76 3F79 3F7C SEITE 3F82 3F85 3F88 3F8B 3F8E 3F91 3F94 3F97 3F9A 3F9D 3FA0 3FA3 3FA6 3FA9 3FAC 3FAF 3FB2 3FB5 3FB8 3FBB 3FBE SECI 3FC4 3FC7 3FCA 3FCD 3FDO 3FD3 3FD6 3FD9 3FDC 3FDF 3FE2 3FE5 3FE8 3FEB 3FEE SEFI 3FF4 3FF7 3FFA 3FFD F000 dc dc dc dc dc dc
26. item numbers with each item consi sting of a variable amount of data 1 to 4 bytes 18 User Manual S12 EETS Includes include datatypes h include hcsl2dp256 h include s12 eets h NEE EA a e See ee ese ess aasee void initEETS void ECLKDIV EETS_ECLKDIV set EEPROM Clock Divider Register HL INT8 wrSectEETS UINT16 dest UINT16 src check addr must be aligned 32 bit if UINT16 dest amp 0x0003 return 1 check if ECLKDIV was written if ECLKDIV amp BM EDIVLD 0 return 2 make sure error flags are reset ESTAT BM PVIOL BM ACCERR check if command buffer is ready if ESTAT amp BM CBEIF 0 return 3 check if sector is erased if dest l Oxffff dest 1 l Oxffff no go erase sector dest src ECMD EETS CMD SERASE ESTAT BM CBEIF if ESTAT amp BM PVIOL BM ACCERR return 4 while ESTAT amp BM CBEIF 0 program 1st word dest src ECMD EETS_CMD_PROGRAM ESTAT BM_CBEIF if ESTAT amp BM PVIOL BM ACCERR return 5 while ESTAT amp BM CBEIF 0 program 2nd word x destt1 src 1 ECMD EETS CMD PROGRAM ESTAT BM CBEIF if ESTAT amp BM PVIOL BM ACCERR return 6 while ESTAT amp BM CCIF 0 return 0 INT8 writeltemEETS UINT16 item no void item if item no gt EETS MAX SE
27. lash memory If page is not specified the whole Flash memory ex monitor code space will be erased after user confirmation To remove erase the monitor code a BDM tool such as ComPOD 12 StarProg is required Erase EEPROM Syntax Y sadr Erase one sector double word 4 byte of EEPROM memory The sector is specified by it s starting address sadr bits O and 1 of sadr are don t care If sadr is not specified the whole EEPROM will be erased after user confirmation 34 User Manual 9 Memory Map The memory map of the microcontroller is initialized by the TwinPEEKs monitor as follows Note partly different from reset default values CardS12 D64 Begin Em fRessowes 0000 03FF Control Registers 1KB EEPROM od poddili the top 16 bvtes are alwavs reservedi 4KB RAM reset default 0000 0FFF 33000 PPRT TWinPEEKS uses the top 512 Were equis Page 9 CardS12 DG256 Begin End Resource o y 0000 03FF Control Registers 3KB of total 4KB EEPROM 0400 the area below 0400 is hidden by control registers the top 16 bytes are always reserved 12KB RAM 1000 53FFF TwinPEEKs uses the top 512 bytes 4000 7FFF 16KB Flash equals Page 3E 16KB Flash page 30 30000 SBEFE any Page 30 3F selectable by PPAGE 16KB Flash equals Page 3F SEUDO Spe TwinPEEKs uses the top 4KB 35 CardS 12 CardS12 DP512 Begin End Ressources o o 0000 03F
28. lemented IBCR BM_IBEN BM_MSSL BM_TXRX transmit mode master issue START cond while IBSR amp BM_IBB 0 wait for busy state i CAUTION no loop time limit implemented Func Issue IIC Restart Condition Args Retn void restartIIC void 23 CardS 12 IBCR BM RSTA issue RESTART condition Func Issue IIC Stop Condition Args Retn void stopIIC void IBCR BM IBEN back to slave mode issue STOP cond Func Transmit byte via IIC Args bval data byte to transmit Retn if stat 0 then IIC ACK else IIC NOACK UINT8 sendIIC UINT8 bval UINT8 stat IBCR BM IBEN BM MSSL BM TXRX still transmit mode still master IBDR bval transmit bvte while IBSR amp BM IBIF 0 wait for transfer done i CAUTION no loop time limit implemented stat IBSR amp BM_RXAK mask ACK status 0 ACK IBSR BM_IBIF clear IB Intr Flag return stat Func Receive byte from IIC Args ack IIC ACK IIC NOACK Retn byte received UINT8 receiveIIC UINT8 ack UINT8 bval IBCR BM IBEN BM MSSL receive mode still master if ack l IIC ACK IBCR BM TXAK set TXAK to respond with NOACK bval IBDR dummy read initiates transfer while IBSR amp BM IBIF O0 wait for transfer done i CAUTION no loop time limit implemented IBSR BM_IBIF clear IB Intr Flag IBCR BM_IBEN
29. of HCS12 devices is already disabled out of reset Additional Information on the Web Additional information about the CardS12 Controller Module will be published on our Website as it becomes available http elmicro com cards12 html 27 CardS12 8 TwinPEEKs Monitor Software Version 2 3 Serial Communication TwinPEEKs communicates over the first RS232 interface SERO X3 at 19200 Baud Settings are 8N1 no hardware or software hand shake no protocol Autostart Function After reset the TwinPEEKs monitor checks whether port pins PH6 and PH7 are connected If this is the case the monitor immediately jumps to address 8000 This feature allows to start an application program automatically without modifying the reset vector which is located in the protected Flash Boot Block Write Access to Flash and EEPROM The CPU can read every single byte of the microcontroller s resour ces the type of memory does not matter However for write accesses some rules have to be followed Flash and EEPROM have to be erased before any write attempt Programming is done by writing words two bytes at a time to aligned addresses To form such aligned words two subsequent bytes have to be combined TwinPEEKs is aware of this but the following problem can not be avoided by the monitor The monitor is processing each S Record line seperately If the last address of such an S Record is even the 2nd byte to form a complet
30. r the MC9S 12Dxx if the internal oscillator and PLL are disabled by applying 15 CardS 12 a low level to the XCLKS pin during reset Since this option is not used by default on the CardS12 Controller Module XCLKS must be tied to high level which is realized by a MCU internal pull up resistor Please note that other HCS12 derivatives may have different features associated with the XCLKS pin Operating Modes BDM Support Three pins of the HCS12 are used to select the MCU operating mode MODA MODB and BKGD MODC While MODA and MODB are pulled low R1 R2 to select Single Chip Mode BKGD is pulled high R7 by default As a consequence the MCU will start in Normal Single Chip Mode which is the most common operating mode for application code running on the HCS12 The HCS12 operating mode used for download and debugging is called Background Debug Mode BDM BDM is active immediately out of reset if the mode pins MODA MODB BKOD are configured for Special Single Chip Mode This is done by pulling the BKGD pin low during reset while MODA and MODB are pulled down as well Because only the BKGD level is different for the two modes it is quite easy to change over However there is no need to switch the BKGD line manually via a jumper or solder bridge because this can be done by a BDM Pod such as ComPOD12 attached to connector X1 A BDM Pod is required for BDM based download and or debugging anyway so it can handle this task
31. ser Manual System Info Syntax I Display system information This includes address range of register block RAM EEPROM and Flash and the MCU identifier PARTID Load Syntax L Load an S Record file into memory Data records of type S1 16 bit MCU addresses and S2 linear 24 bit addresses can be processed SO Records comment lines will be skipped S8 and S9 Records are recognized as end of file mark S2 Records use linear adresses according to Freescale guidelines The valid address range for the MC9S12D64 starts at OXF0000 0x3C 16KB and ends at OXFFFFF 0x40 16 KB 1 Before loading into non volatile memory EEPROM Flash this kind of memory must always be erased Also only word writes can be used in this case It may be required to prepare S Record data accor dingly before it can be downloaded see instructions above The sending terminal program such as OC Console must wait for the acknowledge byte before starting the transmission of another line This way the transmission speed of both sides PC and MCU are synchronized Move Memory Syntax M adr1 adr2 adr3 Copy a memory block starting at address adr1 and ending at adr2 not included to the area starting at address adr3 33 CardS 12 Select PPAGE Syntax P page Select a program page PPAGE This page will become visible in the 16KB page window from 8000 to BFFF Erase Flash Syntax X page Erase one page 16K B of F
32. ter component values is always a compromise over lock time and stability of the loop 5 to 10kHz loop bandwidth and a damping factor of 0 9 are a good starting point for the calculations With a quartz frequency of 16MHz and a desired bus clock of 24MHz a possible choice is R3 4 7k and C3 22nF C4 should be approxi mately 1 20 1 10 x C3 e g 2 2nF in our case These values are suitable for a reference frequency of 1MHz Note to be defined in example file S12 CRG H The according reference divider register value is REFDV 15 and the synthesizer register setting becomes SXNR 23 Please refer to the chapter XFC Component Selection in the MC9S12DP256B Device User Guide for detailed description of how to calculate values for other system configurations The following source listing shows the steps required to initialize the PLL include hcsl2dp256 h include s12 crg h void initPLL void CLKSEL amp BM_PLLSEL make sure PLL is not in use PLLCTL BM_PLLON BM_AUTO enable PLL module Auto Mode REFDV S12 REFDV set up Reference Divider SYNR S12_SYNR set up Synthesizer Multiplier the following dummy write has no effect except consuming some cycles this is a workaround for erratum MUCTS00174 mask set OK36N only CRGFIG 0 while CRGFLG amp BM_LOCK 0 wait until PLL is locked CLKSEL BM_PLLSEL switch over to PLL clock An alternative external clock source can be used fo
33. th may occur Should you use the product for any such unintended or unauthorized application you shall indemnify and hold the manufacturer and its suppliers harmless against all claims even if such claim alleges that the manufacturer was negli gent regarding the design or implementation of the product Product features and prices may change without notice All trademarks are property of their respective holders User Manual Contents 1 Overview APAPAP AP 3 Technical Data V LLL eee 4 Package Contents 0 sirasi risi karatia 6 EHE SIT ei oa ewer ew eee et eeu dn Bean Gees 7 3 Parts Location Diagram sssi e isjametja tisbita a widen 8 4 Jumpers and Solder Bridges 9 JUMPETS REC PLC 9 Solder Bridges 2 9 5 Mechanical Dimensions s sese 11 6 Circuit Description 2p eek EROR EORR RUR Rae e ee 12 Schematic Diagram 00 eee 12 Controller Core Power Supply LL 12 Reset Generation 0 0 ccc eee eens 13 Clock Generation and PLL 1 ees 14 Operating Modes BDM Support 000 eee 16 Integrated A D Converter ccc cee eens 16 Integrated EEPROM 2 2 0200 18 Indicator LED i suere ee be RR tm e nie 20 RS232 nterfaces rss spen Re Er C e eed 20 SPI BUS iine ru c AW PANG REA bed eee PNE cs 22 NG BUS rcc 23 CAN Interface 2 maba bake naa km Mer ede ee ata E 25 7 Application Hints a ba kaa dscns et Y Rr Kakasa 27 Behaviour aft

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