User`s Manual Template
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1. User s Manual Page 6 2 6 0 Configuration Files E aE aE FE FE FE FE FE a a aE FE E a a a a FE a FE E aaa aaa a aaa aa a PinList Definition TEE FE a a aE FE E a a a a FE E E a a aa a FE E a aa aaa aaa aaa aa aa PINLIST ANALOG VDD default IO ANALOG VDD CVDD default IO CVDD HOLDn default IO HOLDn NOVEA RVDD default IO NOVEA RVDD RVDD default IO RVDD WPn default IO WPn anapadext data n default IO anapadext data n 6 2 Understanding the Configuration File Structure e A Configuration File is an ASCII text file with a simple human readable format e The main elements ate Control Definitions which define particular aspects of the conversion and program generation process and comments which begin with the symbol and continue to the end of the line e Control Definitions can be categorized into one of two forms single line or multi line single line definition begins with a keyword includes one or more parameters and continues to the end of the line or to the beginning of a comment The following PERIOD definition is an example of a single line Control definition PERIOD 5 000ns default Note that the keyword is PERIOD and that the two parameters are 5 000ns the value of the target period for cyclization and default the name given to this particular target period or Click Dom2. 6 0 Configuration Files 6 5 Create or Edit the Pinlist e The PINLIST block allows you to define per pin the D10 tester channel assigned and any alternate versions of that name used in the simulation or ATE conversion soutce The tester channel information that can be specified includes Resource Type DPIN96 DPS16 VIS16 DIBU or default The word default selects DPIN96 Pin Type I IO CLK REF POW A NC or See Vedoaty CAE User s Guide for more information on these types Slot number Channel number The alternate pin names known as Aliases You can specify as many Aliases on a pin line separated by whitespace as you need Velocity uses Aliases to match simulation or ATE pin names that are different from the target D10 pin name e The following is an example of a PINLIST definition HEHEHE EERE EE EEE HE EEE EEE EEE EEE HEHEHE EEE HEE EE EEE HEE HEE EEE HF EH EE FH PinList Definition HEHEHE EERE HE EGE EEE EE HEE EH EGE EE EEE HEE HEE EEE HEE EEE EH FE HE HE FF PINLIST ANALOG VDD DPS16 POW 0 2 HOLDn DPIN96 I 1 17 hold n holdn WPn DPIN96 1 8 anapadext data VIS16 ANA 0 3 END PINLIST Note that pin ANALOG VDD uses channel 2 of a DPS16 card in slot 0 It is defined as a pin type of POW meaning a Power pin Also note that pin HOLDn the pin name to be used in the target D10 test program has aliases of hold n a
3. 3 2 3 3 Create Tester Setup tete be mettons eie 2 3 2 3 4 Cr ate LEN M 2 4 2 3 5 Compilen isse er eee ee RR TR Ee Te EH ERN RC EU Te Yee E oe A eene 2 4 2 36 Normalize Timing oo e Diti ete orae e 2 4 DBT Append sco ee Epi EEUU ptit ovs re tot vrbe E be oS 2 4 3 0 VELOCITY CAE CONVERTERS COMMAND LINE 3 1 3 1 Running the WGL Converter eee ceres eee e esee ette eene netta setenta nest en asse osse ense sena 3 1 Xl Gonfiguration File europe Gt EU AR ER ine P ERREUR ERSTE 3 1 3 1 2 WGL Conversion nere enne nennt erret E eren ener erret 3 1 3 1 3 Runnng WGE CONnVersiOns cscs toto Re EO IE I OE REI Re UU RO Eee te 3 1 3 2 Running the VCD Converter eere ecce ee eee eee ee enne eren seen ose tease enano tasses enses 3 2 32eb Configuration File Settings E ERROR RENS 3 2 322 VCD Convetsion Options 5 nint tcc ein men dada bete indeed cad ee 3 2 3 2 3 Running VOD et RE RE RUE ee REI b e EG ERE dots 3 3 3 2 4 Verifying Correct Cyclization Using the Cycled VCD sse eee 3 4 3 3 Running the ee eese esee eite ee 3 4 3 3 1 Configuration File Settings espe RE RAE RN EGER RE Nr EI
4. CONTENTS Page NO IGE iua ii FECIT cp ii 1 0 GENERAL INFORMATION i eire toten Ie exe PEU VE do 1 1 1 1 Wliat is Velocity CAE icsssscscscestsssesdsecascceusesconsconsesssnseccvassosesseeusecceccdocanseenssocenseedseesensonsenses 1 1 1 2 Running Velocity 07 d dem 1 1 1 2 What are the tools and components that make up Velocity CAE 1 1 1 3 What Simulation to Test Tools are available eee eee eene tenete tenent enne 1 2 1 4 What Tester to Tester Tools are available eee 1 2 1 5 What kinds of files do Velocity CAE converters 5 1 4 2 0 RUNNING VELOCITY CAE COMMAND LINE ecce esee eene eren neenon neta aseo 2 1 2 1 Using Configuration eene eroi treat eroe noe ao sdovanssesaedsaseonsvosebacsecncse 2 1 2 2 Running a Simulation to Test Converter 4 eee eee e etes eee eee ee enne eren netta netos sse 2 1 2 3 Simulation to Test Conversion Options eee e esee teen seen nest 2 3 2 3 1 Optimize Output eee eese vede e eee ie de eee i ie 2 3 2 32 Write ete oe eria E IER ETE 2
5. you can name multiple VCD files for conversion listed after the required Configuration file name User s Manual Page 3 3 3 0 Velocity CAE Converters Command Line 3 2 4 Verifying Correct Cyclization Using the Cycled VCD Output For each input VCD file the VCDtoD10 Converter generates an output VCD file at the end of conversion that contains any modifications to events that may have been caused by the cyclization process For example if Snap to Timing is enabled and an edge from the original VCD file is moved by the Snap process the output VCD file will contain the moved edge Design Engineers can feed this cycled VCD file back into the simulation to verify that the modified waveforms will still work for the device Each output VCD file will be named with the same base filename as the input VCD file but with Cycled appended For example if the input VCD file is named myPattern ved the output VCD file will be named myPattern_Cycled vcd 3 3 Running the VCT Converters Information on how to configure and run V CItoD10 and VCDIAVTC BACKGROUND This section focuses on Velocity settings specific to the VCTtoD10 and VCDtoAVC Converter For more information on the use of Velocity Simulation to Test Converters and their common settings refer to the previous section of this guide called Using Velocity Simulation to Test Tools 3 3 1 Configuration File Settings There are no Configuration file settings specific to the VC
6. 0 Running Velocity CAE Command Line 2 0 RUNNING VELOCITY CAE COMMAND LINE User s Manual 2 0 Running Velocity CAE Command Line 2 0 RUNNING VELOCITY CAE COMMAND LINE Information on how to configure and start up Velocity CAE Simulation to Test Tools and how to set common execution options 2 4 Using Configuration Files All Velocity CAE tools require a configuration file which is a human readable ASCII text file that you create This file will customize the Core Analyzer Engine for specific conversions For more information on understanding creating and editing Velocity configuration files refer to the section in this guide called Configuration Files or for more details see the Velocity CAE Configuration Guide To start a new conversion without customization you can run Velocity CAE with a blank configuration file 2 2 Running a Simulation to Test Converter At a command line prompt in a terminal window type the name of the Converter followed by any required command line options and input filenames and press ENTER The following example shows typical command line syntax for executing the WGLtoD10 Converter bin ConfigFile cfg myPatterns wgl The following example shows typical command line syntax for executing the WGLtoAVC Converter COUNT anceATHNbDEn velocityvexe WGLEOAVC TO EDD ConfigFile cfg myPatterns wgl Note the four options o s t and
7. 008 User s Manual Page 4 2 4 0 Running Velocity CAE GUI Based To select the WGLtoD10 Converter first load an appropriate configuration file For help on creating this file please see the section 6 0 Configuration Files ot refer to the Velocity CAE Configuration Guide Select WGL on your Source Port Drag down Select Credence Diamond on the Target Port Configuration C AllianceaTE samples weL deviceD deviceD_withCustomizatic 57 EDIT g BULD COMPILE r Build Source Port wa v Target Port Credence Diamond v Selected Outputs Write Pattern Timing etc Create Tester Setup Files Create C Source if applicable Now you can click on the Source Icon to load your source file WGL and press Build Sometimes the Select Orignal Source File Look in deviceD gt fv sjc abist p2002 sdca comp p22 wgl k My Recent Documents E Desktop My Documents a My Computer My Network Places File name o 0 0 0 0 0 0 0 0 Files of type Valid Shell Source Files adr xmlL atp WGL w Cancel Please see the next section in this guide Simulation to Test Conversion Options for more information on the meaning and usage of the various User s Manual Page 4 3 4 0 Running Velocity CAE GUI Based 4 3 Simulation to Test Conversion Options All Velocity tools including the Simulation t
8. 2 Conversion Options There are no conversion options specific to the VCTtoD10 Converter You can use any of the common options described in the section of this guide called Simulation to Test Conversion Options or in the Velocity Program Generator User s Guide User s Manual 5 0 Velocity CAE Converters GUI Based 5 3 3 Running Converter Select VCD EVCD under Source Port and Credence Diamond under Target Port Load the appropriate Configuration and Source Files Press Build Configuration c AllianceATE samples WwGL deviceD deviceD_withCustomizatic 2 NEW 57 EDIT BUILD COMPILE r Build Source Port vcb evcp D Target Port Credence Diamond Selected Outputs V write Pattern Timing etc v Create Tester Setup Files v Create Source if applicable Create Verilog Files Compile Output Files for Target Append Mode Debug Mode User s Manual 6 0 Configuration Files 6 0 CONFIGURATION FILES User s Manual Page 5 1 6 0 Configuration Files 6 0 CONFIGURATION FILES A brief tutorial on creating basic Configuration File BACKGROUND Velocity requires a Configuration file for every pattern conversion or program generation process The Configuration file allows you to specify key aspects of the test program creation process in a simple format including pin mapping levels timing tests and test flow TIP It is r
9. At a command line prompt in a terminal window type velocity followed by any required command line options and input filenames and press ENTER The following are examples of WGLtoD10 and WGLtoAVC command line syntax CPA NOntobiU Ton ConfigFile cfg myPatterns wgl myPatterns2 wgl Gr AllpanceatE binevelocrty MGLEOAVC to s ConfigFile cfg myPatterns wgl myPatterns2 wgl These examples illustrate that you can name multiple WGL files for conversion listed after the required Configuration file name User s Manual Page 3 1 3 0 Velocity CAE Converters Command Line 3 2 Running the VCD EVCD Converters Information on how to configure and run V CDfoD10 and V CDto AV C BACKGROUND This section focuses on Velocity settings specific to the VCDtoD10 and VCDtoAVC Converters For more information on the use of Velocity Simulation to Test Converters and their common settings refer to the previous section of this guide called Using Velocity Simulation to Test Tools 3 2 1 Configuration File Settings There are two Configuration file settings specific to the VCD Converters PERIOD and EDGES The PERIOD Control definition is used to specify a target tester period to be applied to the VCD pattern in order to cyclize the stream of events The EDGES definition specifies the maximum number of timing edges to expect within a period By default this value is 1 However an
10. ND All TIMING blocks in a particular Configuration file must use the same PERIOD value This ensures that the D10 will be able to use the resulting STIL file TIP In order to use TIMING blocks with different PERIOD values in your test program use separate Configuration files for each of the different periods and run separate conversions with each User s Manual Page 6 8 6 0 Configuration Files On subsequent lines use the following keywords followed either by a time value or a percentage OFFSET Time delay of first edge for a pin of type CLK RISE Time delay of second edge for a pin of type CLK if a rising edge FALL Time delay of second edge for a pin of type CLK if a falling edge DUTY Duty cycle for a pin of type CLK expressed only as a percentage DRIVE Time delay of a drive edge for a pin of type I or IO RECEIVE Time delay of a compare edge for a pin of type O or IO BACKGROUND If you specify a timing parameter as a percentage Velocity interprets it as a percentage of the PERIOD time This provides a convenient way to scale edge delays with a sequencer period For the last line use the keywords END TIMING e following is an example of a Timing definition TIMING default ERIOD 100ns FFSET Ons UTY 50 RIVE 25 ECEIVE 90 ULSE 5 END TIMING uvVAUUO N 6 8 Customizing Patterns BACKGROUND If your Velocity package includes Optimization options Vel
11. NNING VELOCITY CAE GUI BASED Information on how to configure and start up Velocity CAE Simutation to Test Tools and how to set common execution option through the Graphical User Interface 5 File View Test Help Configuration Options Configuration File Location Optimization Level Partial Optimization No Compression v B 8 Normalize Timing AC specs track with periods Build Enable Parallel Scan Mode Source Port Shell No Patterns y bowe Data BitRate i Target Port choose Only Selected Outputs Edges Per Data 2 Enable Snapping Write Pattern Timing etc Create Tester Setup Files Target Program Files Create C Source if applicable Create Verilog Files Compile Output Files for Target Append Debug Mode Alliance ATE liance ATE Consulting Inc Release V5 3 June 10 2008 4 1 Using Configuration Files All Velocity CAE tools require a configuration file which is a human readable ASCII text file that you create This file will customize the Core Analyzer Engine for specific conversions For more information on understanding creating and editing Velocity configuration files refer to the section in this guide called The Velocity CAE Configuration File or for more details see the Velocity CAE Configuration Guide To start a new conversion witho
12. RE Fe iiie ad 3 4 3 32 VET Conversion Options s sco ned a p eo iet re inm duties 3 4 3 3 3 TAREA ea du reset te E E RESO 3 4 4 0 RUNNING VELOCITY CAE GUI Based e eeee ee eee eee ee eee eene enne etas etna setas setas eto nose tanen 4 1 User s Manual Page iii 4 1 Using Configuration Files scccscscsscsssscccscsscsesscccessscccssccsescessssceesccssescccssscessssssssoesees 4 1 4 2 Running a Simulation to Test Converter 4 eee ee esee etes seen esee 4 2 4 3 Simulation to Test Conversion Options tasses seta 4 4 4371 Op nmuze Outputs eee eq 4 4 430 Writ Pattem Timing ete dee tei en e E GE ger E TR ERE ES dH 4 4 4 3 3 Create Tester Setup Files iso e UE drei na n Up d a oe GR TINTO 4 4 4 3 4 Create C EE 4 4 43 5 teste e RED nee A qe HERR 4 4 43 6 Normalize Timing iet e eiie 4 4 4 Append seo pee e eh ea Rn tI dept d e e ete d 4 5 5 0 VELOCITY CAE CONVERTERS GUI BASED eee stone sen 5 1 5 1 Running the WGL Converter eere ecce esee e eese e ette eene neon seta seta ns seen sese 5 1 51 Configuration File Settings ooo
13. RZ or R1 formatted signal would require 2 edges TIP A reliable method for ensuring that your PERIOD and EDGES configuration file settings are appropriate for your VCD conversion soutce is to automatically generate an initial configuration file from the VCD source Then you can edit other settings in the configuration file as required Before auto generating the configuration file be sure to set the Snap Resolution option in the GUI to the desired value of EDGES For more information on how to automatically generate a configuration file refer to the section in this guide called Creating a Configuration File For more information on these Configuration settings or any of the common settings refer to the section of this guide called Creating a Configuration File or to the Ve ocity Program Generator User s Guide 3 2 2 VCDtoD10 and VCDtoAVC Conversion Options There are two conversion options specific to the VCD Converters Edge Count and Snap Enable The Edge Count option is used for specifying the number of edges to be used per tester period in the converted patterns and timing On the command line the edge count option is eN where N is the number of databits per period User s Manual Page 3 2 3 0 Velocity CAE Converters Command Line To set the XMode from the GUI enter a number in the Edges Per Data field The Snap Enable option is used for correcting imperfect simulation data in which an edge placement w
14. T Converters You can use any of the common settings described in the section of this guide called Creating a Configuration File or in the Velocity Program Generator User s Guide However you should note that since VCT is a cyclized format the PERIOD and EDGES Control definitions are not required in the Configuration file 3 3 2 VCTtoD10 and VCDtoAVC Conversion Options There are no conversion options specific to the VCTtoD10 Converter You can use any of the common options described in the section of this guide called Simulation to Test Conversion Options or in the Velocity Program Generator User s Guide 3 3 3 Running VCTtoD10 and VCDtoAVC At a command line prompt in a terminal window type velocity followed by any required command line options and input filenames and press ENTER User s Manual Page 3 4 3 0 Velocity CAE Converters Command Line The following is an example of VCTtoD10 and VCTtoAVCcommand line syntax Ce ELE ConfigFile cfg myTiming rconfig m yPattern vct FS Ha ConfigFile cfg myTiming rconfig m yPattern vct Note in this example that immediately after the name of the configuration file is the name of the rconfig file followed by the name of the vct file User s Manual Page 3 5 4 0 Running Velocity CAE GUI Based 4 0 RUNNING VELOCITY CAE GUI BASED User s Manual 4 0 Running Velocity CAE GUI Based 4 0 RU
15. TERS COMMAND LINE User s Manual 3 0 Velocity CAE Converters Command Line 3 0 VELOCITY CAE CONVERTERS COMMAND LINE Velocity CAE comes with independent converters for each translation this way multiple processes can be ran at once These converters are ran through the Windows Command Line 3 1 Running the WGL Converters Information on bow to configure and run WGLZoD10 and BACKGROUND This section focuses on Velocity settings specific to the WGLtoD10 and WGLtoAVC Converters For more information on the use of Velocity Simulation to Test Converters and their common settings refer to the previous section of this guide called Using Velocity Simulation to Test Tools 3 1 1 Configuration File Settings There are no Configuration file settings specific to the WGL Converters You can use any of the common settings described in the section of this guide called Creating a Configuration File or in the Velocity Program Generator User s Guide However you should note that since WGL is a cyclized format the PERIOD and EDGES Control definitions are not required in the Configuration file 3 1 2 WGLtoD10 and WGLtoAVC Conversion Options There are no conversion options specific to the WGL Converters You can use any of the common options described in the section of this guide called Simulation to Test Conversion Options or in the Velocity Program Generator User s Guide 3 1 3 Running WGLtoD10 and WGLtoAVC
16. Timing ce ATE IP INC niliil Allian History User s Manual Page 4 5 5 0 Velocity CAE Converters GUI Based 5 0 VELOCITY CAE CONVERTERS GUI BASED User s Manual 5 0 Velocity CAE Converters GUI Based 5 0 VELOCITY CAE CONVERTERS GUI BASED Velocity CAE comes with independent converters for each translation this way multiple processes can be ran at once These converters are run through the Windows GUI Based Application m veiocity cr Eile View Test Help Configuration 1 Options C AlianceATE samples WGL deviceD deviceD_withCustomizatic optimization Level Partial Optimization No Compression New v y suno 9 Normalize Timing AC specs track with periods Enable Parallel Scan Mode p Build SourcePort wa v em Data BitRate i TargetPort Credence Diamond SEONG Edges Data 2 Enable Snapping V Write Pattern Timing etc IV Create Tester Setup Files amp Target Program Files V Create C Source if applicable Create Verilog Files Compile Output Files for Target Append Debug Mode Alliance ATE Alliance ATE Consulting Inc Release V5 3 June 10 2008 5 1 Running the WGL Converter Information on how to configure and run WGL conversion BACKGROUND This section focuses on Velocity
17. VELOC TY CAE TESTING AT THE SPEED OF LIGHT Velocity CAE Program Generator For Simulation to ATE and ATE to ATE Conwersion Release 53 Quick Start Guide Velocity CAE Program Generator Simulation to Test Tools Quick Start Guide COPYRIGHT NOTICE Copyright 2008 Alliance ATE Consulting Group Inc Alliance ATEX All rights reserved Documentation version 2 0 Any technical documentation that is made available by Alliance ATE Consulting Group is the copyrighted work of Alliance ATE Consulting Group and is owned by Alliance ATE Consulting Group NO WARRANTY The technical documentation is being delivered to you AS IS and Alliance ATE Consulting Group makes no warranty as to its accuracy or use Any use of the technical documentation ot the information contained therein is at the risk of the user Documentation may contain technical or other inaccuracies or typographical errors Alliance ATE Consulting Group Inc reserves the right to make change without prior notice No part of this publication may be copied without the express written permission of Alliance ATE Consulting Group 3080 Olcott St Suite 110C Santa Clara CA 95054 TRADEMARKS Velocity CAE Program Generator D10Shell and ShellConstructor are trademarks of Alliance ATE Consulting Group Diamond D10 and ITE are trademarks of Credence Systems Corporation SmarTest 93000 and 93K are trademarks of Verigy User s Manual Page ii QUICK START GUIDE TABLE OF
18. ain A multi line definition also called a block consists of a starting line zero or more sub parameter lines and an ending line The starting line begins with a keyword and includes zero or more parameters The ending line consists of the keyword END and the starting line keyword The following PINLIST block definition is an example of a multi line Control definition PINLIST ANALOG VDD default IO ANALOG VDD CVDD default CVDD HOLDn default HOLDn END PINLIST Note that the block begins with the keyword PINLIST and ends with END PINLIST In between are lines that begin with a pin name and consist of several parameters that define properties of the pin User s Manual Page 6 3 6 0 Configuration Files The following sections describe how to create and edit the most common Control Definitions in a Configuration File 6 3 Create or Edit the Program Path e The first thing that you should define in the Configuration file is the location of the target test program files e Velocity divides the test program location into three parts base path Points to the directory typically used as the parent directory of all D10 test programs Device name Appended to the base path Categorizes test programs by device Program name Appended to the base path Device name combination Contains all the files that make up a specific D10 test program e Define the base path using the keyw
19. anual 5 0 Velocity CAE Converters GUI Based TIP Although not specific to the VCD Converters another useful option for converting VCD files is Debug This option enables a shortened conversion run allowing you to examine the initial results for problems before proceeding with the full conversion To select the Debug option click on to put a checkmark in the Debug checkbox in the GUI You can use any of the common options described in the section of this guide called Simulation to Test Conversion Options or in the Velocity Program Generator User s Guide 5 2 3 Running VCD Conversion Select VCD EVCD under Source Port and choose Target Port For the example below the Credence Diamond Target is chosen To Load the appropriate Configuration and Source Files Press Build Configuration C AllianceATE samples WGL deviceD deviceD withCustomizatic w NEW EDIT BUILD COMPILE r Build Source Port vcb evcp Target Port Credence Diarnond Selected Outputs write Pattern Timing etc v Create Tester Setup Files v Create C Source if applicable create Verilog Files Compile Output Files for Target Append Mode Debug Mode 5 2 4 Verifying Correct Cyclization Using the Cycled VCD Output For each input VCD file the VCDtoD10 Converter generates an output VCD file at the end of conversion that contains any modifications to events tha
20. cyclization process by specifying one or more target tester periods in the Configuration File Velocity will attempt to divide the VCD event stream into the specified period or periods and determine the resulting drive tri state and compare edge delays within the period e Define a target period using the keyword PERIOD followed by a time value The Period definition also specifies what is known in Velocity as a Clock Domain Optionally each Period Clock Domain definition can take a name as a second parameter This name can be used elsewhere in the Configuration File to reference the Clock Domain The following is an example of a PERIOD definition PERIOD 1608ps domain622 Note that the time value parameter can include units immediately after the number no whitespace in between Units can include all the common scaling letters such as n for nano u for micro m for milli etc Also note that the name domain622 has been assigned to the Clock Domain e Use the EDGES Control definition if your VCD pattern contains waveforms that can be translated as RZ or R1 formats on the D10 The EDGES definition specifies the maximum number of timing edges to expect within a period An RZ or R1 formatted signal would require 2 edges Define the number of timing edges per Period using the keyword EDGES followed by an integer value as in the following example EDGES 2 User s Manual Page 6 5
21. e eR ers uere 5 1 5 127 WGE Conversion Options atte ERR eed Rg RO dis 5 2 52123 Running WGL Conversions sosca naear eet Riese hist Bai 5 2 5 2 Running the VCD Converter eeeee eerie eee e esee ette eene eee en netta stone setas eee ta sets s setas sse ense etes 5 2 52 1 Configuration File Set n9s 5 3 5 2 2 VCD Conversion Options iie esee eee e e e ERE He HH iii 5 3 5 2 3 Running VCD Conversions ee eg I t esc RE 5 4 5 2 4 Verifying Correct Cyclization Using the Cycled VCD Output sese 5 4 5 3 Running the Converter eere eee ee eee e esee ette ee enne 5 5 5 3 1 Configuration File Settings nen nnne rene rennen nene uipi 5 5 5 32 Conversion ptoms ee e ber iei ere epe RE AR REI Rudd 5 5 5 3 3 Running VCT Conversions esee ne e RIDERE EIU r ee 5 6 6 0 CONFIGURATION FILES 6 2 6 1 Optional Automatically Generate an Initial Configuration File eres 6 2 6 2 Understanding the Configuration File Structure eere eee eese cette eren eren nnn 6 3 6 3 Create or Edit the Program Path 4 eerie eee ee eerte eren eese te setas tnos etas etna sto 6 4 6 4 Create or Edi
22. ecommended that at a minimum your Configuration file contain a program PATH name specification and a PINLIST definition 6 1 Optional Automatically Generate an Initial Configuration File To automatically generate an initial configuration file press the New Icon under the configuration box Enter a desired filename into the file selection window and press save This will generate a initial Velocity CAE Configuration File Configuration c AllianceATE samples WGL deviceD deviceD withCustomizatic nor y NEW EDIT BUILD COMPILE Build Source Port Target Port Credence Diamond Selected Outputs ross Below 15 the first part of an example Configuration file automatically generated by Velocity from the Samplel vcd file listed in the previous File Selection window HEHEHE EH HEH HE EE EE EE EE EEE EE EE HH TE FE FE EE EE EE EE EEE EH HE EE EE EE EE EE EEE EF Device and Path Information HEHEHE EH HEH HE HHH EEE EE EE EE EE HEHE EE E TE FE FE EE EE EE EE EEE EE EE EE EE EE EE EE EE EE EE EEE EH PATH Documents and Settings Phil My Documents Alliance ATE Velocity Velocity V3 2 1 Windows Samples DEVICE VCD PROGRAM test PERIOD 5 000ns default EDGES 1 HEHE HEHE HE HH EEE HEHE EEE EE EEE EEE FE AE FE EEE EE EE HE EEE EEE EE EE EE RE Group Definitions E aE aE aE AE AE aE a aaa aaa
23. his will be the master power supply voltage level On subsequent lines use the following keywords followed either by a voltage value or a percentage VIH Input voltage for a logic high VIL Input voltage for a logic low Output threshold voltage for a logic high VOL Output threshold voltage for a logic low BACKGROUND If you specify a level as a percentage Velocity interprets it as a percentage of the POWER level This provides a convenient way to scale levels with a device power supply voltage For the last line use the keywords END LEVELS User s Manual Page 6 7 6 0 Configuration Files The following is an example of a Levels definition LEVELS default POWER 3 0V VIL 0 8V VIH 2 0V VOL 30 VOH 50 END LEVELS 6 7 Create or Edit Custom Timing BACKGROUND Although Velocity will create appropriate Time Sets for your D10 program based on the simulation or ATE files used as source for the conversion you can create your own custom timing to apply to tests To define custom timing for a group of pins create the following Control definition block On the first line use the keyword TIMING followed by a pin or group name Optionally you can use the word default for the pin specification to indicate all pins On the next line use the keyword PERIOD followed by a time value This will be the period of the tester s pattern sequencer BACKGROU
24. iming etc v Create Tester Setup Files Create C Source if applicable Create Verilog Files Compile Output Files for Target Append Mode Debug Mode 5 2 Running the VCD EVCD Converter Information on how to configure and run VCD conversions BACKGROUND This section focuses on Velocity settings specific to the VCD Converters For more information on the use of Velocity Simulation to Test Converters and their common settings refer to the previous section of this guide called Using Velocity Simulation to Test Tools User s Manual 5 0 Velocity CAE Converters GUI Based 5 2 1 Configuration File Settings There are two Configuration file settings specific to the VCD Converters PERIOD and EDGES The PERIOD Control definition is used to specify a target tester period to be applied to the VCD pattern in order to cyclize the stream of events The EDGES definition specifies the maximum number of timing edges to expect within a period By default this value is 1 However an RZ or R1 formatted signal would require 2 edges TIP A reliable method for ensuring that your PERIOD and EDGES configuration file settings are appropriate for your VCD conversion soutce is to automatically generate an initial configuration file from the VCD source Then you can edit other settings in the configuration file as required Before auto generating the configuration file be sure to set the Snap Resolution o
25. ithin the tester period might vaty from petiod to period The option does so by specifying a number of equal size snap windows with which to divide the tester period A raw edge from the simulation file that falls within a particular snap window will be automatically moved to a specific time within the window On the command line the Snap Enable option is s To set the Snap Enable option from the GUI check the snap enable box TIP Although not specific to the VCD Converters another useful option for converting VCD files is Debug This option enables a shortened conversion run allowing you to examine the initial results for problems before proceeding with the full conversion To select the Debug option click on to put a checkmark in the Debug checkbox in the GUI You can use any of the common options described in the section of this guide called Simulation to Test Conversion Options or in the Velocity Program Generator User s Guide 3 2 3 Running VCDtoD10 and VCDtoAVC At a command line prompt in a terminal window type velocity followed by any required command line options and input filenames and press ENTER The following is an example of VCDtoD10 and VCDtoAVC command line syntax a rE Ha ConfigFile cfg Patternl evcd Pattern2 evcd ance ih bid Ge oer ConfigFile cfg Patternl evcd Pattern2 evcd This example illustrates that
26. les needed for Verigy s ASCII translator FLEXtoAVC Converts patterns and timing from Teradyne UltraFlex files to Verigy s AVC and DVC format along with files needed for Verigy s ASCII translator AVCtoD10 Converts patterns and timing from Verigy AVC files to D10 STIL pattern and timing files STILtoD10 Converts patterns from non Diamond comliant STIL to proper diamond compliant STIL STILtoAVC Converts any STIL based pattern representation into Verigy s AVC and DVC format along with files needed for Verigy s ASCII translator User s Manual Page 1 3 1 0 General Information 1 5 What kinds of files do Velocity CAE converters create Depending on the options you select for the conversion and the targeted output format Velocity converters can create all the setup C source and pattern files required to build and run a fully functional test program These generated files include For the Verigy 93000 Setup Files gt pin gt tim gt binl gt pmfl gt aic Pattern Files gt avc gt dvc For the Credence Diamond Setup Files job make res sig bindef binmap C Source Files 3333153 gt gt h Pattern Files Levels stil Signals stil Specs stil Timing stil Mactos stil Pattern stil Contains patternExecs patternBursts and overall usage Vectors stil defines the vector data 313315333 User s Manual Page 1 4 2
27. make lighting fast conversions without the pain of customizing each run However the command line will give power users the ability to customize and batch run their translations For Running Velocity CAE from the Command Line see 20 Running Velocity CAE Command Line ot fot running Velocity CAE from a GUI see 4 0 Running Velocity CAE GUI 1 2 What are the tools and components that make up Velocity CAE Velocity CAE consists of the following major components Component Description ShellConstructor Automatically generates all initial source and setup files for a skeleton D10 program GUI The graphical interface to all Velocity CAE functionality Core Engine Analyzer Central processing hub of Velocity CAE Required for all Simulation to Test and Tester to Tester conversion tools Simulation to Test Tools Convert simulation output to tester patterns and timing User s Manual Page 1 1 1 0 General Information Tester to Tester Tools Convert pattern and timing data from one test platform to another 1 3 What Simulation to Test Tools are available Velocity CAE offers the following Simulation to Test Tools Tool Description WGLtoD10 Converts patterns and timing from WGL Waveform Generation Language files to D10 STIL pattern and timing files VCDtoD10 Converts patterns and timing from VCD Verilog Change Dump files to D10 STIL pattern and timing files Automa
28. nd holdn meaning that it can take its data from simulation or ATE conversion sources that use either of those alias names Finally note that pin anapadext data n is defined as pin type ANA meaning an Analog pin User s Manual Page 6 6 6 0 Configuration Files The GROUP Control definition allows you to assign a name to a group of pins for easier reference elsewhere in the Configuration file e define a Group use the keyword GROUP followed by a Group name followed by an equals sign and a comma separated list of pin names enclosed in double quotes The following is an example of a Group definition GROUP DBUS DO D1 D2 D4 D5 D7 6 6 Create or Edit the DC Levels BACKGROUND Simulation output files and even STIL files do not typically define DC levels for the signals However using configuration file structures Velocity provides you with a way to include levels information with your auto generated D10 test program The LEVELS block allows you to define for any pin or group of pins power supply levels input drive levels and output threshold levels To define levels for a group of pins create the following Control definition block On the first line use the keyword LEVELS followed by a pin or group name Optionally you can use the word default for the pin specification to indicate all pins On the next line use the keyword POWER followed by a voltage value T
29. o Test Converters support a set of execution options Most of the options are common to all of the tools The following section lists all of the common options 4 3 1 Optimize Output Enables the performance of various optimizations on the conversion output If this option is turned on Velocity will at a minimum remove any unreferenced timing and levels blocks that were defined in the source files It will also enable the use of other optimization options that can be individually turned on or off Those additional optimization options are described later in this guide especially the XMode and Snap Resolution options that are specific to conversions from VCD EVCD format 4 3 2 Write Pattern Timing etc Enables the converter to create new STIL files for the D10 program if Credence Diamond Target is chosen Enables the converter to create and DVC files if the Verigy 93000 Target is chosen 4 3 3 Create Tester Setup Files Enables the converter to create new test setup files for the D10 program such as JOB SIG MAKE etc For the 93000 this will enable the export of the 93K Pin Configuration file the AIC file and the other files required to run the ASCII translator ATT amp AIV 4 3 4 Create Source Enables the converter to create new test program source files for the D10 program namely cpp and h files There are no source files created for the 93000 targets to this option would be ignored for all exp
30. ocity can automatically search for compression opportunities when converting patterns and create appropriate repeats and loops in your D10 STIL patterns However even without Optimization you can manually customize your pattern files using Configuration file control With this capability you can specify explicitly not only repeats and loops but also selective output masking pin by pin and cycle by cycle User s Manual Page 6 9 6 0 Configuration Files The following section describes how you can define some of the most common pattern customizations in the Configuration file However there is much more that you can do with this control structure For more information refer to the CAE Program Generator User s Guide e To modify an existing pattern use a Pattern block with the following structure On the first line use the keyword PATTERN followed by a new pattern name For the last line of the block use the keywords END PATTERN e Inside a Pattern block you can define output masking and vector loops or repeats e To define an output mask for a particular pin or group of pins and for a particular vector range use the keyword PINS followed by a comma separated no spaces pin group list followed by a vector range as in the following example PATTERN func pat masked PINS Q0 01 02 03 55 83 END PATTERN Note the use of the hyphen for the vector range specifier indicating that the masking occurs from
31. ord PATH followed by a directory path specifier For example PATH home D10programs e Define the device name using the keyword DEVICE followed by a device name For example DEVICE coolChip e Define the program name using the keyword PROGRAM followed by the test program name For example PROGRAM finalTest e In the above example Velocity would create test program files for the D10 Build in the directory home D10programs coolChip finalTest User s Manual Page 6 4 6 0 Configuration Files 6 4 Create or Edit the Cyclization Timing BACKGROUND ATE test systems such as the Credence D10 output functional stimulus to the device in the form of a vector sequence The vectors are presented at a particular rate defined by the cycle time Many simulation and test data formats such as WGL and STIL also have a concept of vectors and cycle times which can be translated directly to D10 format However the VCD Verilog Change Dump format is non cyclized That is signal patterns are represented as a continuous stream of events where an event is a change of state at a particular point in time relative to the beginning of the pattern For VCD Velocity will analyze the spacing of timing events for each signal and determine a best fit tester cycle time and edge delays for your D10 test program The cycle time is also known as the period e For VCD files you can assist Velocity s
32. orts 4 3 5 Compile Enables Velocity to automatically run a build on the source files and STIL files if the Credence Diamond Target is chosen Enables Velocity to automatically run the Verigy ASCII translator AIT amp AIV is the Verigy 93000 Target is chosen 4 3 6 Normalize Timing User s Manual Page 4 4 4 0 Running Velocity CAE GUI Based Enables Velocity to automatically create a period scaled timing set 4 3 7 Append Enables the converter to add new patterns timing etc to an existing program instead of overwriting the existing data Velocity CAE File View Test Help Configuration Options 4 3 1 Optimize Output C AllianceATE samples WGL deviceD deviceD _withCustomizatic m Optimization Level Partial Optimization No Compression Y d CERE S ao Normalize Timing AC specs track with periods Build Enable Parallel Scan Made 4 3 6 Normalize Source Port wet is Data BitRate Timing Target Port Credence Diarnond YCD Only Selected Outputs Edges Per Data 2 Enable Snapping Write Pattern Timing etc 4 3 2 Write Pattern Timing etc Create Tester Setup Files 4 3 3 Create Tester Setup Files Target Program Files ILI Create C Source if applicable 4 3 4 Create C Source Create Verilog Files Compile Output Files for Target 4 3 5 Compile Append Debug Mode 4 3 6 Normalize
33. p immediately after the Converter name Velocity tool command line options always begin with a to indicate the setting of the option or with a to indicate the unsetting of the option Please see the section in this guide called Simulation to Test Conversion Options for more information on the meaning and usage of the various options User s Manual Page 2 1 2 0 Running Velocity CAE Command Line Also note the use of a configuration file name on the command line myConfigFile cfg in this example As stated previously all Velocity tools require a configuration file User s Manual Page 2 2 2 0 Running Velocity CAE Command Line 2 3 Simulation to Test Conversion Options All Velocity tools including the Simulation to Test Converters support a set of execution options Most of the options are common to all of the tools The following section lists all of the common options 2 3 1 Optimize Output Enables the performance of vatious optimizations on the conversion output If this option is turned on Velocity will at a minimum remove any unreferenced timing and levels blocks that were defined in the source files It will also enable the use of other optimization options that can be individually turned on or off Those additional optimization options are described later in this guide especially the XMode and Snap Resolution options that are specific to conversions from VCD EVCD format Command line o Tum op
34. ption in the GUI to the desired value of EDGES For more information on how to automatically generate a configuration file refer to the section in this guide called Creating a Configuration File For more information on these Configuration settings or any of the common settings refer to the section of this guide called Creating a Configuration File or to the Ve ocity Program Generator User s Guide 5 2 2 VCD Conversion Options There are two conversion options specific to the VCD Converter Edge Count and Snap Enable The Edge Count option is used for specifying the number of databits to be used per tester period in the converted patterns and timing On the command line the Edge Count option is eN where N is the number of databits per period To set the Snap Enable from the GUI check the snap enable box The Snap Resolution option is used for correcting imperfect simulation data in which an edge placement within the tester period might vary from period to period The option does so by specifying a number of equal size snap windows with which to divide the tester period A raw edge from the simulation file that falls within a particular snap window will be automatically moved to a specific time within the window On the command line the Edge Count option is eN where is the number of edges to use per tester period To set the Edge Count from the GUI enter a number in the Edges Per Data field User s M
35. settings specific to the WGL Converters For more information on the use of Velocity Simulation to Test Converters and their common settings refer to the previous section of this guide called Using Velocity Simulation to Test Tools 5 1 1 Configuration File Settings There are no Configuration file settings specific to the WGL Converters You can use any of the common settings described in the section of this guide called Creating a Configuration File or in the Velocity Program Generator User s Guide However you should note that since WGL is a cyclized format the PERIOD and EDGES Control definitions are not required in the Configuration file User s Manual 5 0 Velocity CAE Converters GUI Based 5 1 2 WGL Conversion Options There no conversion options specific to the WGLtoD10 Converter You can use any of the common options described in the section of this guide called Simulation to Test Conversion Options or in the Velocity Program Generator User s Guide 5 1 3 Running WGL Conversion Select WGL under Source Port and choose a Target Port For this example the Credence Diamond is chosen To Load the appropriate Configuration and Source Files Press Build Configuration c AllianceATE samples wGL deviceD deviceD_withCustomizatic amp NEW 57 EDIT z BUILD 3 COMPILE Build Source Port wet Target Port Credence Diamond r Selected Outputs v write Pattern T
36. t the Cyclization Timing cues eese ceres eere ee netta sets ast tn osea aee 6 5 6 5 Create or Edit the Pinlist 1 4 eer ront euer erkennen tane ooa prone oaa 6 6 6 6 Create or Edit the DC Le vels euet ne eene oe uei ro e oen po euo aoa so 6 7 6 7 Create or Edit Custom Timing renes ette nette seen ose etn setas etos seen aee 6 8 6 8 Customizing Patterns RR 6 9 User s Manual Page iv 1 0 General Information 1 0 GENERAL INFORMATION User s Manual 1 0 General Information 1 0 GENERAL INFORMATION A brief look at the various elements and capabilities of the Velocity CAE Program Generator and Velocity CAE Simulation to Test Tools 1 4 Whatis Velocity CAE Velocity CAE Computer Aided Engineering is a suite of software tools for automatically generating Credence D10 patterns timing and other test program files from either a simulation output or files from other ATE platforms The following sections of this Overview will introduce all the various components of Velocity CAE while the rest of this manual will be focused on the Velocity CAE s Simulation to Test Tools 1 2 Running Velocity CAE Velocity CAE can be run from both the command line and or a Windows Linux based GUI interface The GUI interface makes it extremely easy to
37. t may have been caused by the cyclization process For example if Snap to Timing is enabled and an edge from the original VCD file is moved by the Snap process the output VCD file will contain the moved edge Design Engineers can feed this cycled VCD file back into the simulation to verify that the modified waveforms will still work for the device User s Manual 5 0 Velocity CAE Converters GUI Based Each output VCD file will be named with the same base filename as the input VCD file but with Cycled appended For example if the input VCD file is named myPattern ved the output VCD file will be named myPattern_Cycled ved 5 3 Running the VCT Converter Information on how to configure and run VCT converters BACKGROUND This section focuses on Velocity settings specific to the Converters For mote information on the use of Velocity Simulation to Test Converters and their common settings refer to the previous section of this guide called Using Velocity Simulation to Test Tools 5 3 1 Configuration File Settings There ate no Configuration file settings specific to the VCTtoD10 Converter You can use any of the common settings described in the section of this guide called Creating a Configuration File or in the Velocity Program Generator User s Guide However you should note that since is a cyclized format the PERIOD and EDGES Control definitions are not required in the Configuration file 5 3
38. tically cyclizes stream of events in VCD into D10 vectors with timing sets VCTtoD10 Converts cycled patterns from Verilog vct output files and timing from RCONFIG files to D10 STIL pattern and timing files WGLtoAVC Converts patterns and timing from WGL Waveform Generation Language files to Verigys AVC and DVC format along with files needed for Verigy s ASCH translator VCDtoAVC Converts patterns and timing from VCD Verilog Change Dump files to Verigys AVC and DVC format along with files needed for Verigy s ASCII translator VCTtoAVC Converts patterns and timing from WGL Waveform Generation Language files to Verigys AVC and format along with files needed for Verigy s ASCII translator 1 4 What Tester to Tester Tools are available User s Manual Page 1 2 1 0 General Information Velocity CAE offers the following Tester to Tester Tools Tool Description J750toD10 Converts patterns and timing from Teradyne J750 files to D10 STIL pattern files along with all test flow and programming information FLEXtoD10 Converts patterns and timing from Teradyne UltraFlex files to D10 STIL pattern files along with all test flow and programming information J973toD10 Converts patterns and timing from Teradyne J973 files to D10 STIL pattern and timing files J750t0AVC Converts patterns and timing from Teradyne J750 files to Verigy s AVC and DVC format along with fi
39. timization on O Turn optimization off 2 3 2 Write Pattern Timing etc Enables the converter to create new STIL files for the D10 program Command line s Turn STIL file creation on S Turn STIL file creation off 2 3 3 Create Tester Setup Files Enables the converter to create new test setup files for the D10 program such as JOB SIG MAKE etc Command line t Turn tester setup file creation on t Turn tester setup file creation off User s Manual Page 2 3 2 0 Running Velocity CAE Command Line 2 3 4 Create C Source Enables the converter to create new test program source files for the D10 program namely cpp and h files Command line p Tum test program source file creation on p Tum test program source file creation off 2 3 5 Compile Enables Velocity to automatically bring up the Credence ITE at the end of conversion and run a build on the soutce files Command line Tum automatic test program compilation c Turn automatic test program compilation off 2 3 6 Normalize Timing Enables Velocity to automatically create a period scaled timing set Command line n Turn auto normalization on n Turn auto normalization off 2 3 7 Append Enables the converter to add new patterns timing etc to an existing program instead of overwriting the existing data Command line a Tum appending on User s Manual Page 2 4 3 0 Velocity CAE Converters Command Line 3 0 VELOCITY CAE CONVER
40. ut customization you can run Velocity CAE with a blank configuration file User s Manual Page 4 1 4 0 Running Velocity CAE GUI Based 42 Running a Simulation to Test Converter All of the Simulation to Test Converters can be accessed with options through the GUI The following example demonstrates the selection of the WGLtoD10 Converter First you can start up velocty exe from the desktop if a desktop icon was chosen or from the C AllianceATE bin folder MAKE SURE YOU HAVE A LICENSE FILE BEFORE STARTING THE PROGRAM Having an incorrect license file can cause errors to occur in your program If a correct license file was used you should see the following screen loxi Eile View Test Help Configuration Options Configuration File Location En Optimization Level Partial Optimization No Compression hd NEW EDIT y BUILD Normalize Timing AC specs track with periods ME Enable Parallel Scan Made Source Port shell No Patterns y Data BitRate i Target Port Choose Only Selected Outputs Edges Per Data 2 Enable Snapping V Write Pattern Timing etc V Create Tester Setup Files Target Program Files Create C Source if applicable Create Verilog Files Compile Output Files for Target Append Mode Debug Mode Alliance ATE liance ATE Consulting Inc Release V5 3 June 10 2
41. vector 55 through vector 83 In this example the output pins to be masked Q1 Q2 Q3 and Q4 e When defining any loops or repeats in a Pattern block you must also include an indication of the base pattern to which the loops or repeats apply To indicate the name of the base pattern use the keywotd BASE followed by the base pattern name e To define a loop on an existing pattern sequence use the keyword LOOP followed by comma separated start and stop vector numbers followed by an optional loop count The following example adds a loop to the previous pin masking example PATTERN func pat compressed PINS 00 01 02 03 55 83 BASE func pat LOOP 100 131 1000 END PATTERN Note that the start vector number of the loop is 100 the stop vector is 131 and that the vector block is looped on 1000 times User s Manual Page 6 10
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