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VINETIC

1. Ethernet 10 100bT UC IF POTS lines t r gic a VINETIC Td Ur a SLIC 2CPE VINETIC Figure 7 Cable Modem Settop Box SMTA EMTA The VINETIC chip set fulfills all requirements for packetized voice over cable see Figure 7 The voice data is transferred in RTP packets allowing the network processor an easy packetization for transmitting it via VoIP over the cable network The VINETIC system is conform to PacketCable specification Fax relay T 38 is also supported by the VINETIC chip set No additional DSP for voice processing or fax termination is needed in the system Preliminary Product Overview 24 Rev 2 0 2004 05 11 _ Infineon technologies VINETIC Family Overview 8 xx POTS lines ix JA aic t parallel pC IF ha n d VINETIC Ly t Ga 4x A Ga Suc amp L r Z s VINETIC c MINETIC Network ATM IP letworl lt Processor UY Wr ON Sa T VINETIC ES a SUC I r or E ia suc Je te VINETIC Aa T p PCM VINETIC vinetic NextG Acc Figure 8 Next Generation Access Network Linecard Next generation
2. 17 1 3 P LBGA 176 3 Pin Diagram 18 1 4 PG LBGA 144 Pin Diagram 4 channel devices 19 1 5 PG LBGA 144 Pin Diagram 2 channel devices 20 1 6 Logic Symbol VINETIC 4x 2 1 7 Typical Applications 22 2 VINETIC Host Interface Description 26 241 VINETIC Host Interface Configurations 26 3 Codec SLIC Features BORSCHT Functions 28 3 1 BORSCHT functions 28 3 2 Advanced Integrated Test and Diagnostic Functions AITDF 29 3 2 1 Moon aca PETITS 29 3 2 2 VINETIC Line Testing wi aaa 29 3 2 3 Board and Production Testing 30 4 Signalprocessing Capabilities of the VINETIC 3i 5 Programming of the VINETIC 33 5 1 Command Data Structure in Downstream Direction 33 5 2 Command Data Structure in Upstream Direction 35 5 3 First Command Word 36 5 4 Second Command Word 36 5 4 1 Second Command Word in Case of SOP COP and IOP 36 5 4 2 Second Command Word in Case of EOP EVT and VOP 37 5 5 Data Words chimes
3. Cc gt Er 0 10 05 21 5 ail a c 0 08 0 22 095 2 19 08 WIA BIDIC Tex 26 _ 5 02 A BIDI 76x 240 lt 102 A BIDIH 4x 4444 i e NE aw zi E N E Cw Ad B Qe Index Marking E T6 5 E 1 Je ELA HIER E IN 1 Does not include plastic or metal protrusion of 0 25 max per side 2 Does not include dambar protrusion of 0 08 max per side GPP09451 Figure 24 VINETIC 4x PEB33x4HL VINETIC 2VIP PEB 3322HL and VINETIC 0 PEB3320HL You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products SMD Surface Mounted Device Dimensions in mm Preliminary Product Overview 78 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Package Outlines P LBGA 176 3 Plastic Low Profile Pitch Ball Grid Array Package 4 1 14 415 Index Marking Al x x Y RS 0 28 C 9 z UUUIUUUUUUUUUUU z
4. 905101 5025 HISA 8 i e Index Marking 17 toa B gpa09450 Figure 25 VINETIC 4x PEB33x4E VINETIC 2VIP PEB 3322E and VINETIC 0 PEB3320E You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products SMD Surface Mounted Device Dimensions in mm Preliminary Product Overview 79 Rev 2 0 2004 05 11 lt e C Infineon VINETIC technologies Package Outlines PG LBGA 144 Plastic Low Profile Pitch Ball Grid Array Package Tx1 n n Index Marking nx12 f AY RE gt 144x gt C a 90 6 01 e 50 25 GAIB t S g 2 Q bs Index Marking 18 01 B Figure 26 VINETIC 2CPE PEB 3332 VINETIC 4M PEB 3314 VINETIC 4C PEB 3394 VINETIC 4S PEB 3304 You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products SMD Surface Mounted Device Dimensions in mm Preliminary Product Overview 80 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Terminology 11 Terminology A A D Analog to digital AAL2 ATM Adaption Layer 2 AC Alternative Current ADC Analog Digital Converter AITDF Advanced Integrated Test and Diagnostic Functions ATD Answering Tone Detector ATM Asynch
5. however internally offers the possibility of accurate line and board testing thus avoiding the need for external test unit and relays Programmability One of the main advantages of VINETIC is that all SLIC and codec functions are programmable through software The configuration software VINETICOS can be used to program at each port indepenently the following functions DC battery feed characteristics AC impedance matching Transmit gain Receive gain Hybrid balance Frequency response in transmit and receive direction e Ring frequency and amplitude waveform sinusoidal trapezoidal crest factor Hook thresholds TTX modes 3 2 Advanced Integrated Test and Diagnostic Functions AITDF 3 2 1 Introduction Subscriber loops are affected by a variety of failures and thus must be monitored This requires access to the subscriber loop as well as specific test equipment The tests involve measurements of resistance capacitance leakage and any interfering currents and voltages Traditionally up to 2 relays and a test unit was necessary to perform such tests VINETIC9 integrates both the generation and detection of the test signals as well as the functionality of the relays 3 2 2 VINETIC Line Testing The VINETIC chip set uses its Advanced Integrated Test and Diagnostic Functions AITDF to perform all tests necessary for monitoring the local loop The measurements can be accomplished not only on a channel speci
6. A ring burst is executed with a programmed cadence including the transmission of Caller ID Automactic Teletax Metering The Teletax signal stops automatically after a programmable period 1 more automatic modes are in preparation 2 only availabe from v2 1 onwards 3 only available from v2 1 onwards Preliminary Product Overview 41 Rev 2 0 2004 05 11 _ e Infineon VINETIC technologies Firmware Architecture 7 Firmware Architecture 7 1 Module Concept The VINETIC 4x has a modular firmware architecture which is based on four different firmware module types lt PCM Interface module lt Analog Line Interface module Coder module Signaling module These modules contain the functional blocks necessary for the implementation of typical voice over packet applications as well as standard TDM applications The Figure 9 illustrates the module concept The multiple arrows show the data path to the hardware the single arrows symbolize signals which can be connected together via a signal array o 5g PE Interface aos E Module lt 4 channels i 8 16 channels Packet Mailbox PH X SIG OutB 7 Any Signal X SIG OutB 0 Any Signal Signaling Module 4 channels Vinetic 1000 FW Architecture Figure 9 Module Concept Preliminary Product Overview 42 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firm
7. Each ALM Module channel supports the following features Conferencing ADDER Submodule Gain e LEC far end near end with NLP ALM Interface Module Any Signals Analog Line ear En Module Far End LEC Vinetic 1002 ALM Module Figure 11 Analog Line Module ALM The Gain submodules allow a gain adjustment of the transmit and receive path Preliminary Product Overview 45 Rev 2 0 2004 05 11 _ Infineon technologies 7 4 VINETIC Signaling Module Firmware Architecture The Signaling Module supports up to 4 channels Each channel supports the following features DTMF Receiver 2 ATD Answering Tone and DIS Detection 2 UTD Universal Tone and V 18 A Detection DTMF AT Generation CPT Detector CID Receiver CID Caller ID Sender DTMF AT Generation Universal Tone Generator UTG Event Transmit Unit Figure 12 shows one channel of the signaling module Signaling Channel gt E CID Receiver Event E RTP gt Event Transmit Salus Unit y QE CID ae gt Satus gt Sender em 8 Sn E 2885 Event i a y J UTD T 1 EB E gt Satus gt Signal DTMF AT m i DIME Reose Any 1 Auto Suppression Signals i E SIGata SIGO4B 2 B A 12 e 82 gt Status Information reflected in Status Registers SRE1 SRE2 Event Transmission if enabled ET 1
8. Features CPE e e e e e Power optimized architecture with power management capability integrated battery switches e e e e e Part of ADSL IVD and IPVD solution e e e e e Direct connection of Clare Litelink Ill device Interface Features e e e e e e POCM pC interface selectable 1 2 2 2 2 POM interface number of highways e e e e e e Parallel Host interface Intel Motorola compatible e e e e e e Serial control interface SCI Infineon compatible SPI compatible e e e e e SLIC interface compatible with DuSLIC SLICs e e e e e e JTAG interface for boundary scan e e e e e e P LQFP 176 9 e e e e e P LBGA 176 PG LBGA 144 Additional Features e e e e e e SW compatible between different VINETIC devices e e e e e HW compatible between different VINETIC devices e e e e e e Driver and API for Linux and VxWorks 1 8 channel devices in preparation 2 In preparation 3 All VINETIC devices un to version v1 4 include RAM for download 4 in preparation 5 Green Packaaes in preparation contact local sales for details 6 only available for production from v2 1 onwards Preliminary Product Overview 15 Rev 2 0 2004 05 11 VINETIC technologies Family Overview VINETIC 4x 32 MHz PLL ee Clock Control 128 MHz serial parallel interface
9. KK PCM Bus PHI G 726 Linear Vinetic 1001 PCM Module Figure 10 PCM Interface Module The G 711 G 726 Linear submodule performs either A u Law ADPCM coding decoding or can be switched to 16 bit linear data two consecutive PCM time slots The LEC submodule can be used to cancel a near or far end echo A near end echo is generated via a local hybrid a far end echo via a complete network The RBS robbed bit signaling submodule suppresses signaling information It replaces the signaling information with a V 90 friendly pattern The RBS module modifies the received PCM values and herefore it has to be in front of the PCM decoder The Gain submodules allow a gain adjustment of the transmit and receive path The HP submodule filters the DC part of the signal 1 in preparation Preliminary Product Overview 44 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Firmware Architecture 7 3 Analog Line Module ALM The VINETIC 4x contains as many ALM modules as analog ports are specified for the corresponding device The ALM module has a granularity of 2 as the hardware blocks are also the same granularity Channel one and two are within the Analog Line Module 1 HW Module and channel three and four for the 4 channel devices are within the Analog Line Module 2 HW Module Data is transferred from the SLIC devices via the Analog Line Module to the Signal Array and vice versa
10. Signa Module Figure 12 Signaling Module Preliminary Product Overview Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firmware Architecture The DTMF Receiver submodule is responsible for detection of DTMF signals If a valid DTMF key is detected status bits are set and an interrupt is generated The DTMF Receiver submodule has an early detection mode This mode can be used to suppress DTMF signals auto suppression to avoid double sending of DTMF signals in packet networks The DTMF Receiver submodule also provides event transmission support for RTP and the AAL2 protocols The answering tone detection submodules ATD1 and ATD2 have two different modes They can detect the answering tone or the signal level The signal level detec tion mode is needed for implementing the holding characteristic according to the G 164 specification Event transmission support is available for the RTP protocol The universal tone detection submodules UTD1 UTD2 supports two different modes They can detect a sine tone or the signal level The signal level detection mode mode is needed for implementing the holding characteristic according to the G 164 specification Event transmission support is not available for the UTD submodule The DTMF AT Generator submodule can generate DTMF signals alert tones or any other dual tone frequencies The host can decide if it wants to program both frequen cies independently or to prog
11. e e e Text phone support V 18 Codec SLIC Features e e e e e Worldwide programmability for AC and DC parameters e e e e e Specification in accordance with ITU T Recommendation Q 552 for interface Z e e e e Specification in accordance with ITU T Recommendation G 712 and applicable LSSGR GR 506 507 etc GR 57 EIA TIA 464 and other applicable worldwide standards e e e e e Integrated balanced unbalanced ringing capability fully software programmable up to 85 Vrms ringing voltage Crest factor selection between 1 2 and 1 6 frequency range between 15 and 75Hz e e e e External ringing support e e e e Programmable 12 16 kHz teletax generation metering and integrated notch filtering e e e e e Programmable battery feeding with capability for driving longer loops e e e e e Ground loop start signaling e e e e Ground key detection e e e e e Polarity reversal e e e e e Message Waiting Indication e e e e e Automatic modes for POTS signaling and Power Management e e e e e Advanced Integrated Test and Diagnostic Functions AITDF for local loop monitoring including GR 909 and board production test capabilities e e e e e On hook transmission Preliminary Product Overview 14 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Family Overview Table 3 VINETIC Features cont d VIP 2 M C eS 0 VINETIC
12. G 728 Annex Packet Loss Concealment Automatic Gain Control AGC Coder 0 7 8 T 38 Coder typ 10 4 1 not all algorithms functions are supported with all devices 2 Refer to Chapter 7 for the definition of the modules 3 See Table 3 on Page 13 for details available showing the exact number of resources available per version Using the integrated ALM tone generators doesn t allocate EDSP ressources not all devices and all firmware versions support all the given number of resources A firmware status sheet is DTMF generation can be realized by using EDSP ressources or by using the integrated ALM tone generators Numbers for block packet based coder channels include Voice Play Out reordering jitter buffer clock synchronization and Packetization AAL2 or RTP RTCP At the Coder Module different coders can be activated in receive and transmit direction In this case the max of MCycle s of both coders has to be taken into account The Far End Line Echo Cancellation has shared ressources with the low bitrate coders Therefore each activated Far End LEC channel will reduce the available number of coder channels by one Preliminary Product Overview 32 Rev 2 0 2004 05 11 C a ere VINETIC technologies Programming of the VINETIC 5 Programming of the VINETIC This chapter gives an overview on the command data structure of the VINETIC chip devices For further informat
13. Output current limit TR max SLIC E E2 IT mazi Active Modes 80 105 130 mA SLIC S S2 Active Modes 75 95 115 mA SLIC P Version 1 2 Active Modes HIT HIR C3 L 45 60 75 mA SLIC P Version 1 2 Active Modes ROR ROT C3 H 70 loo 110 mA Loop current gain 3 Yo accuracy Loop current offset 0 75 0 75 mA error Loop open resistance Ra Power Down Mode 5 kQ TIP to BGND lh 2mA 74 25 C Loop open resistance Power Down Mode 5 kQ RING to VBAT IR 2 mA Ty 25 C Ring trip DC voltage SLIC E E2 S S2 0 30 Vdc SLIC P balanced 0 30 Vdc SLIC P unbalanced VgArR 2 Vdc Ring trip detection Standard ring trip 2 cycle time delay detection DC AC RTR FAST 0 Fast ring trip detection 0 5 cycle RTR FAST 1 Ring off time delay 2 cycle 1 Current limitation controlled at SLIC P pin C3 by the VINETIC pin IOO 2 Preliminary Product Overview Can be reduced with current offset error compensation 64 Rev 2 0 2004 05 11 VINETIC technologies Application Circuits 9 Application Circuits 9 1 Internal Ringing Balanced Unbalanced Internal balanced ringing is supported up to 85 Vrms for systems with SLIC E E2 P and up to 45 Vrms for systems with SLIC S SLIC P also allows internal unbalanced ringing up to 50 Vrms without any additional external components 9 1 1 Appli
14. Vi DD18 DD18 V Vi Vi DD18 M DD18 0033 0033 0033 1 1 1 1 1 1 4 AGND AGND AGND AGND AGND AGND AGND V DD18A M Vu Mona V Venne ACPA ACNA DCPA DCNA C1A C2A Rstas 301 TIPA 7 6 STAB TSLIC E A TSLIC S 3 Channel A B BGND only channel A connected for this example gt Csras RINGA ILA R STAB 301 VCMSA PEB 4365 PEB 4364 POND AGND CEXTA Cea BGND AGND AGND DD184B A4 V Vina 0018 Vopise V DD33A Vona Interface Parallel or VINETIC x serial Interface only channel A and SUC interface pins connected for this example 8 6800 GPIO7 gt VCMAB 100A IO4A lt gt VREFAB Cree mH CREFAB PEB 33xy GNDAB GND Le GND GNDP AGND AGND AGND AGND ezm14042V_T_ES Figure 15 Preliminary Product Overview 66 Application Circuit Internal Ringing balanced for TSLIC E S Rev 2 0 2004 05 11 VINETIC technologies Application Circuits Vonis Vopis Voois Vonis Vooss Vooss Voss 1 1 1 1 1 T T Diodes are shared AGND AGND AGND AGND AGND AGND AGND for 2 channels 0018 Vonia Vpote Vopiep Vopssa Manga Von ACPA i ACNA DCPA DCNA 3 Channel Overvoltage Protection CIA i A 62 Rogo
15. Access Networks DLCs are using ATM or IP networks to transmit data and voice VINETIC is highly scalable and allows to install as many codecs in parallel as required by the linecard design The integrated line testing ring generation and small footprint SLIC chips makes VINETIC an optimum fit for these high density applications Both RTP and AAL2 are supported by VINETIC enabling the network processor to have either an IP or an ATM backbone Preliminary Product Overview Rev 2 0 2004 05 11 _ Infineon VINETIC technologies VINETIC Host Interface Description 2 VINETIC Host Interface Description The host interface of the VINETIC is operated by a programmable host interface controller PHI which allows a flexible and easy adaption to various interface types For programming the VINETIC and performing data packet transfer from to VINETIC a parallel interface or a serial microcontroller interface can be used Additionally VINETIC has an interface to PCM data VINETIC 8 16 Bit Parallel Interfaces The parallel interface can be operated in Intel 8 16 bit mode multiplexed demultiplexed or in 8 16 bit Motorola mode Note VINETIC 2CPE and VINETIC devices with PG LBGA 144 package only support 8 bit interfaces VINETIC Serial Interfaces The VINETIC serial microcontroller interface uC interface SCI is compatible with Motorola SPI and is electrically compatible with DuSLIC The PCM interface
16. DC part is dimensioned to allow dynamic ring voltage tracking In Table 16 typical values of the external components are listed unregulated R1 asw D1 supply voltage o lt 9 20V EVA ae gs R2 R3 e L1 I 65 n in C4 C3 R4 R5 vs SWD PB 61 Re CVR VN 4 66 gt GNDA amp 2 COS 4 H Cr R7 3 2 I R8 GND 8 ROS 4 c8 v 8 VINETIC 8 SYNC M R9 DUSLIC EAN 610 69 R10 01 C1 EAO D e c2 c2 PEF 4268T vnEF SLIC DC KA naun dp dp y ps lt o gt UT a 7 7 ad 0 gt v CODEC Interface J 0 SLIC Interface 1 channel gt v gt 30 0 gt gt 2 AA T A Ee EE aaa E p ME Line Interface 0 VCMITA Figure 17 Application Circuit Internal Ringing with DC DC Table 16 Components for SLIC DC Application Circuit Symbol Function typ Unit Tolerance Rating Value 2 IR overcurrent limitation stability 20 Q 1 rel 2 IC EMC filtering 18 nF 5 rel 100 V 2 Hp overcurrent limitation EMC filtering 20 0 1 Yo rel 1
17. Interface Concept VINETIC chip set family For more VINETIC related documents please see our webpage at http www infineon com vinetic To simplify matters the following synonyms are used VINETIC x Synonym used for all codec versions VINETIC 4VIP VINETIC 2VIP VINETIC 2CPE VINETIC 4C VINETIC 4M VINETIC 4S VINETIC 8S and VINETIC9 8M VINETIC 4x Synonym used for 4 channel versions of the VINETIC family To simplify matters only the 4 channel versions are depicted in this document in most cases SLIC Synonym used for all SLIC versions SLIC S S2 TSLIC S SLIC E E2 TSLIC E SLIC P SLIC LCP and SLIC DC Attention The TSLIC S PEB 4364 and TSLIC E PEB 4365 chips are dual channel versions of the SLIC S PEB 4264 and SLIC E PEB 4265 with identical technical specifications for each channel Therefore whenever SLIC S or SLIC E are mentioned in the specification also TSLIC S and TSLIC E can be deployed Organization of this Document This Preliminary Product Overview is divided into 11 chapters It is organized as follows Chapter 1 Family Overview A general description of the chip set the key features and some typical applications Chapter 2 VINETIC Host Interface Description Connection information including the different interface types Chapter 3 Codec SLIC Features BORSCHT Functions The main functions of the chip set are presented with functional block diagrams Chapter
18. Limit Value Unit Test Condition Min Typ Max Supply pins VDD18 VDD18i 1 71 1 8 1 89 V referred to the corresp ground pins GND GNDi i A AB B C CD D P Supply pins VDD33 VDD33i 3 14 3 3 13 47 V referred to the corresp ground pins GND GNDi i A AB B C CD D Analog input pins 0 33 JV Vop33i 3 3 V 02 IO3x lO4x ILx ITx VCMITx ITACx referred to the corresp ground pins GNDx x 2 A B C D Analog output pins Vop33i 3 3 V DCPx DCNx 03 2 7 RLoag gt 900 Q ACPx ACNx 03 2 7 Rioad gt 9 KQ VREFy VCMy 1 3 1 7 l gag 4 mA C1x C2x 0 3 3 Toad lt 250 pA referred to the corresp ground pins GNDx GNDy x A B C D y AB CD Analog pins for passive Vpp33i 3 3 V devices CDCPx CDCNx 0 33 IV CREFy 05 07 09 IV referred to the corresp ground pins GNDx GNDy x A B C D y AB CD lt lt lt lt Preliminary Product Overview 52 Rev 2 0 2004 05 11 lt Infineon technologies VINETIC Electrical Characteristics Table 5 Operating Range VINETIC cont d Parameter Symbol Limit Value Unit Test Min Typ Max Condition Digital input output pins I O pins GPIO pins High level input voltage Vin 2 0 36 IV Vout gt Vou min Low level input voltage Vi 0 3 08 IV Vout lt VoL max High level outp
19. R t IT current voltage conv AC 510 Q 1 1 Rito IT current voltage conv DC 680 Q 1 1 A IL current voltage conv 3 3 ko 196 Preliminary Product Overview 69 Rev 2 0 2004 05 11 technologies VINETIC Application Circuits Table 16 Components for SLIC DC Application Circuit cont d Symbol Function typ Unit Tolerance Rating Value 1 Citac AC separation on IT 1 uF 10 10 V 1 C1 internal positive supply voltage filtering 47 nF 10 10V 1 C2 VS supply filtering 100 nF 10 100 V 1 C6 switching frequency setting 82 pF 5 96 1 QSW switching transistor pnp Zetex FZT 955 or equivalent 1 QOW alternative switching transistor PMOS Int Rectifier IRF 6216 or equivalent 1 R1 current limitation 220 mQ 5 96 0 5W 1 R2 base emitter discharging resistor 180 Q 5 1 R5 base current limitation 47 Q 5 1 R4V DC base current limitation 680 Q 5 1 c3 base current highpass filter 33 nF 10 96 1 R3 damping of overshoots 100 Q 5 1 with PMOS 1 C4 damping of overshoots 330 pF 10 1 L1 DC DC inductor 33 uH 10 Ipeak 2A 1 D1 DC DC diode 150V 1A e g MURS 120 1 C5 DC DC capacitance 1 uF 10 low ESR 1 R8 output voltage divider 715 ko 1 1 R10 output voltage divider 18 ko 1 1 R7 smoothing of VN transients 470 ko 5 C8 smoothing of VN transients 22 pF 10 1 R6 VN filtering 20 Q 5 96 1 C7 VN filtering 1 u
20. Supply voltage VS 9 40 V with PMOS switch 9 20 V with pnp switch Generated battery voltage VN 90 15 V Voltage at pins IT IL Vim Vit 0 4 3 5 V Input range Vpcp VpcN VACDC 0 3 3 V VACP VACN Ambient temperature Tamb 40 85 C Junction temperature Tj gt 125 eC 1 Operation up to Ty 150 C possible However a permanent junction temperature exceeding 125 C could degrade device reliability Preliminary Product Overview 60 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Electrical Characteristics 8 6 Operating Range SLIC LCP Table 12 Operating Range SLIC LCP Parameter Symbol Limit Values Unit Note Min Max Battery voltage L VBATL 65 15 V Referred to BGND Battery voltage H VBATH 70 20 V Referred to BGND Vpp supply voltage Vbp 4 5 5 5 V Referred to AGND Voltage at pins IT IL Vir Vit 0 4 3 5 V Referred to AGND Input range Vpcp Voen Vacpc 0 3 3 V Referred to AGND Vacp VACN Ambient temperature Tamb 40 85 C Junction temperature Tj gt 1252 6 1 If the battery switch is not used pins VgAr and Vgaty should be connected externally In this case the full voltage range of 15 V to 70 V can be used 2 Operation up to Tj 150 C possible However a permanent junction temperature exceeding 125 C could degrade device reliability Preliminary Product Overview 61 Rev 2
21. and RAM for voice processing into the codec SLIC chip set thereby offering a unique set of features for voice over packet Cost and Boardspace Reduction codec DSP and RAM are integrated into one small package providing significant cost and boardspace advantages Scalability VINETIC supports each voice channel with the necessary amount of DSP performance due to the encapsulation of codec and DSP Flexibility the VINETIC family offers 2 to 8 analog ports and various level of DSP performance while remaining pin and software compatible lt World Wide Usage The VINETIC can be adapted to different country requirements without a hardware change AC and DC path ringing metering etc are programmable Future Proof the integrated RAM for downloading advanced codecs or Infineon DSP software VINETIC P LQFP 176 2 P LBGA 176 3 and PG LBA 144 1 E SLIC pium X T i ET ELI lx P DSO 20 5 P VQFN 48 4 lt A P DSO 24 1 3 P TQFP 48 1 guarantees that for future remote updates the system will remain state of the art technology TSLIC Designed for Voice over Packet VoIP VoDSL Cable c atm VoATM ra P DSO 36 15 Type Package PEB 3324 PEB 3322 PEB 3332 P LQFP 176 2 P LBGA 176 3 PEB 3320 PEB 3314 PEB 3394 PG LBGA 144 PEB 3304 PEB 4364 PEB 4365 P DSO 36 15 PEB 4264 2 PEB 4265 2 PEB 4266 P DSO 20 5 P VQFN 48 4 PEF 4268 P DSO 24 1 3 P TQFP 4
22. any attached conducting part can be hazardous It must be electrically insulated from other parts or board connections You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products SMD Surface Mounted Device Dimensions in mm Preliminary Product Overview 73 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Package Outlines P VQFN 48 4 Plastic Very Thin Profile Quad Flat Non Leaded 0 9 MAX EMI Tl x 0 5 5 5 55 008 o B B u b q te p 48x E 0 08 n x P H uu C z J vov X Vi Index Marking Op view id 9 gt 02 NA 0 05 MAK STANDOFF gvq09350 Figure 20 SLIC S S2 SLIC E E2 SLIC P PEB426x SLIC LCP PEB 4262 Note The P VQFN 48 4 package is only available with heatsink on bottom Attention The exposed die pad and die pad edges are connected to VBATH VBATR via the chip substrate Due to the high voltage of up to 150 V between VHR and VBATH VBATR and BGND touching of the die pad or any attached conducting part can be hazardous It must be electrically insulated from other parts or board conn
23. has 2 PCM highways and can be operated together with the serial uC interface or the parallel interface Note VINETIC 2CPE only supports one PCM interface 2 1 VINETIC Host Interface Configurations The VINETIC host interface can be set into one of the following modes 8 bit INTEL multiplexed mode PCM interface 2 PCM highways 8 bit INTEL demultiplexed mode PCM interface 2 PCM highways 16 bit INTEL multiplexed mode PCM interface 2 PCM highways 16 bit INTEL demultiplexed mode PCM interface 2 PCM highways 8 bit MOTOROLA mode PCM interface 2 PCM highways 16 bit MOTOROLA mode PCM interface 2 PCM highways VINETIC serial uC interface compatible with Motorola SPI and DuSLIC PCM interface 2 PCM highways Note VINETIC 2CPE only supports 8 bit and serial interfaces with only one PCM highway Note VINETIC devices with PG LBGA 144 package only support 8 bit interfaces Data transfers to and from the VINETIC are either performed via a mailbox system and via the controller interface or via PacketOverPCM The VINETIC supports the widely used microcontrollers e g ADM 5120 MPC850 MPC860 MPC8260 C165UTAH ARM and MIPS based processors etc Preliminary Product Overview 26 Rev 2 0 2004 05 11 Infineon VINETIC technologies VINETIC Host Interface Description All parallel and serial interfaces host interfaces use the same multiplexed pins The desi
24. is mainly used to drive extreme long lines As battery voltages for driving the line the delta between VHR minus VBATH for SLIC P VBTR is used Current Limitation For above active modes the SLIC P and the SLIC LCP offer a selectable current limitation The SLIC P can be selected for either 60 or 90 mA The SLIC LCP between 75 and 110 mA Lower limitation is mainly used to limit the current flowing in fault cases and during ring trip off hook transitions Active with Metering For above active modes all VINETIC devices support 12 and 16 kHz metering signals Active with Metering switches the generation of such frequencies on Ringing Modes Ringing Active Boost In this state the VINETIC9 generates a ringing signal according to the settings made for frequency voltage DC offset and crest factor and the SLIC applies it as balanced ringing onto tip and ring wire Ring trip is supported with programmable ring trip levels Ringing on Ring Tip with Tip Ring to Ground SLIC P only The SLIC P offers in addition to balanced ringing also integrated unbalanced ringing In this mode the ring voltage is only applied to either Ring or Tip wire the other wire is pulled to ground Ring Pause Modes Ring Pause is the default state for the time between two ring bursts Off hook detection is supported with programmable threshold values This is the preferred state for the time between two rings Ground Start Modes In this mode grou
25. voice protocol unit block is responsible for adding upstream direction or deleting downstream direction a header containing the timestamp the packet time PTE and the coder configuration to the voice data The Voice Play Out unit is responsible for packet reordering to estimate the optimum jitter buffer size to readjust the jitter buffer size for clock synchronization and determines the play out times for the received packets A fixed and an adaptive jitter buffer is implemented The maximum supported jitter buffer size is 200 msec the granularity for packets is 5 msec Preliminary Product Overview 50 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firmware Architecture 7 6 Test Features The following test features have been implemented a peak detector test loops a MIPS meter and a version register The peak detector can be connected with any signal from the global Signal Array and any memory location It allows the search for maximum or minimum values since the last read access from the peak value register The version register contains the actual hardware and firmware version Preliminary Product Overview 51 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Electrical Characteristics 8 Electrical Characteristics 8 1 Operating Range VINETIC Venda YGNDB VaNpc YGNDD YGNDAB Vennen YGNDD Venpp 0 V Table 5 Operating Range VINETIC Parameter Symbol
26. will read one packet and one command from the packet and command in box COP SOP and IOP commands will be distributed to the corresponding units COP and SOP Analog Line Module IOP PHI VOP EVT and EOP commands will be processed by the EDSP In upstream direction the packet data sent from the VINETIC to the host is stored in a 256 word out buffer packet out box The responses to read commands are stored a 32 word out buffer command out box If the EDSP wants to send data VOP or EVT operations to the host it checks the free memory space in the packet out box before writing the data If there is not enough memory in the packet out box the EDSP discards the data and sets the box overflow flag in the Mailbox Status Register2 BXSR2 The communcation between host and VINETIC can either be done by interrupt handling maskable interrupt bits one interrupt line from VINETIC to the host or by polling host polls VINETIC interupt and status registers Preliminary Product Overview 38 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Operating Modes 6 Operating Modes 6 1 Overview of all VINETIC Operating Modes VINETIC provides full control over the analog line status by a comprehensive set of modes that can be clustered into 7 groups Sleep Modes Sleep Power Down Resistive The VINETIC is completely powered down The SLIC feeds via an internal resistor the VBATH battery voltage onto the a
27. 0 2004 05 11 Infineon VINETIC technologies Electrical Characteristics 8 7 AC Transmission VINETIC The AC and DC parameters in Table 13 and Table 14 are valid for a chip set of a VINETIC9 x codec and X single channel x 2 dual channel SLIC chips Table 13 AC Transmission Parameter Symbol Conditions Limit Values Unit Min Typ Max Transmission Performance 2 wire Return loss HL 200 3600 Hz 26 dB Frequency Response according to ITU T Q 552 G 712 and Telcordia TGR 57 requirements Idle Channel Noise according to ITU T Q 552 G 712 and Telcordia GR 57 requirements Distortion according to ITU T Q 552 G 712 and Telcordia GR 57 requirements Sinusoidal Test Method Longitudinal Balance according to ITU T 0 9 Longitudinal L T 300 1000 Hz conversion loss SLIC S E P 53 58 l dB SLIC S2 E2 60 65 dB 3400 Hz SLIC S E P 52 55 dB SLIC S2 E2 56 59 dB Input longitudinal L 4 300 1000 Hz interference loss SLIC S E P 53 58 dB SLIC S2 E2 60 65 dB 3400 Hz SLIC S E P 52 55 dB SLIC S2 E2 56 59 dB TTX Signal Generation TTX signal at 200 Q gt 2 5 Vrms Preliminary Product Overview 62 Rev 2 0 2004 05 11 _ Infineon technologies VINETIC Table 13 AC Transmission cont d Electrical Characteristics Paramete
28. 201 Rsras oa 1 lt TIP fuseable resistor 301 PCM TIP Bent ee Cotas Tip CDCP i machi VINETICX lt U1 serial Interface BGND only channel A and SLIC interface pins n connected Ring E for this example Coras L3 4 ILA RING Rpror 201 Rsras GPIOO 97 7 gt fuseable resistor 301 5 VOMAS 1004 104A gt VCMS VREFAB PEB 33xy CREFAB PEB 4266 GNDAB BGND AGND CEXT m GND GNDP C A ExT BGND AGND AGND AGND AGND AGND AGND ezm14042V_P Figure 16 Application Circuit Internal Ringing bal amp unbal for SLIC P As Figure 16 shows balanced and unbalanced internal ringing use the same line circuit Preliminary Product Overview 67 Rev 2 0 2004 05 11 VINETIC technologies Application Circuits 9 1 2 Bill of Materials Table 15 shows the external passive components needed for a complete four channel solution with protection consisting of one VINETIC 4x and four SLIC E E2 S P or two TSLIC E TSLIC S devices Table 15 External Components in Application Circuit for 4 Channels No Symbol Value Unit Tol Rating SLIC E S TSLIC E S SLIC P Systems Systems Systems 4 Rm 510 0 1 X X X 4 Rite 680 Q 1 X X X 4 IRL 1 6 KO 1 8 Rstap 30 Q 1 X X X 8 Rpror 20 Q 196 seed x X X 8 Cstap 15 typ nF 10 see x X x 4 Cpc 220 nF 10 10V
29. 6 Operating Modes A brief description of the operating modes and the integrated test and diagnostic functions Chapter 4 Signalprocessing Capabilities of the VINETIC A short overview of DSP performance necessary for different algorithms Chapter 5 Programming of the VINETIC A general description of the VINETIC x command structure Chapter 7 Firmware Architecture A general description of the VINETIC x software system Preliminary Product Overview 4 Rev 2 0 2004 05 11 Infineon VINETIC technologies Chapter 8 Electrical Characteristics Parameters symbols and limit values are provided for the chip set Chapter 9 Application Circuits External components are identified Illustrations of balanced ringing unbalanced ringing and protection circuits are included Chapter 10 Package Outlines Illustrations and dimensions of the package outlines Chapter 11 Terminology List of abbreviations and descriptions of symbols Chapter 12 Index Attention This document is a pre release version of the VINE TIC product overview Related Documentation in preparation Preliminary Product Overview 5 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Table of Contents Page 1 Family Overview 10 1 1 Pin Diagram VINETIC 4x 17 1 2 P LQFP 176 2 PinDiagram
30. 726 Packetized Voice Protocol Unit which supports the RTP RTCP and AAL2 protocol Voice Play Out unit reordering fixed and adaptive jitter buffer clock synchronization AGC Automatic Gain Control Clock synchronization between packet sender and receiver Multi party conferencing Gain lt DC HP LEC far end with NLP for cancelling echoes originating from the packet network Decoder controlling via voice packet header Status Output Fax Datapump V 17 V 19 V 27ter V 29 for T 38 fax relay Preliminary Product Overview 49 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firmware Architecture Packetized G 7xx Voice Encoder Protocol Unit VAD RTP TCP IP AAL2 ATM DSL Data Depacketized Clock G 7xx Voice Synchro Decoder Protocol Unit nization CNG BFM RTP TCP IP AAL2 ATMI DSL Vinetic 1003 Coder Module Figure 13 Coder Channel Module The AGC can be used to gain and to limit the level of the input signal The limitation should prevent clipping of the signal especially to be used with low bitrate encoders The HP in the decoder direction filters the DC part of the signal The far end LEC can be used to cancel the echo which occurs via the packet connection A global timer for the coder module automatically generates the timestamps for the voice and event packets for all coder and signaling channels The packetized
31. 8 1 Preliminary Product Overview 11 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Family Overview Table 1 VINETIC x Versions Chip Set VINETIC VINETIC VINETIC VINETIC VINETIC VINETIC VINETIC 4VIP 2VIP 2CPE 0 4M 8M 4C 4S 8S Product ID PEB 3324 PEB 3322 PEB 3332 PEB 3320 PEB 3314 PEB 3394 PEB 3304 PEB 3318 PEB 3308 Analog Channels 4 2 2 0 4 8 4 4 8 Echo Cancellation G 165 up to up to up to up to up to 16 ms up to 16 ms No G 168 128 ms 128 ms 16 ms 128 ms ADPCM G 726 Yes Yes Yes Yes Yes Yes No Complex Voice Codecs Yes Yes Yes Yes No No No G 723 G 728 G 729 Fax Relay T 38 Yes Yes Yes Yes No No No Signal processing functions Yes Yes Yes Yes Yes Yes No AAL2 RTP packetization Yes Yes RTP only Yes Yes No No Jitter Buffer Integrated Code RAM for Yes Yes Yes Yes Yes No9 No 9 Firmware Download Line testing AITDF Yes Yes GR909 only Yes Yes Yes Yes World wide programmability of Yes Yes Yes Yes Yes Yes analog BORSCHT functions 1 All 4 2 and O channel devices are pin and software compatible except the VINETIC 2CPE that is optimized for CPE market for 8 channel codecs contact local sales Patent indemnification available e g DTMF generation and detection Caller ID CLIP generation FSK Universal Tone Detection UTD Answering Tone Detection ATD Calle
32. B 3314 VINETIC9 4C PEB 3394 VINETIC 4S PEB 3904 80 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies List of Tables Page Table 1 VINETIC KN ISIS um ved debe rm ced qd Ka ka A d Eua S a 12 Table 2 SLIG VEISIONS esta ace ue c Rex Roe e Ros acp oh ed Rcs end chee d die 12 Table 3 v sse rire aci ot oes eror d cone a 13 Table 4 Provided Algorithms for VINETIS cca os marmor coa d ed Does 31 Table 5 Operating Range VINETIC M 52 Table 6 Power Consumption 24 44 44 ae ween 54 Table 7 Power Up Sequence VINET RETE 55 Table 8 Operating Range SLIC S S2 57 Table 9 Operating Range SLIC E E2 58 Table 10 Operating Range SLIC P 59 Table 11 Operating Range SLIC DC 60 Table 12 Operating Range SLIC LCP 61 Table 13 AC Transmission 62 Table 14 DC Characteristics 63 Table 15 External Components in Application Circuit for 4 Channels 68 Table 16 Components for SLIC DC Application Circuit 69 Table 17 External Components 71 Preliminary Product Overview 9 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Family Overview 1 Fa
33. CDCPA DCPA ACNA ACPA ACPB ACNB DCPB CDCPB 1O2B IO1B 9 6 9 9 9 Vinetic 0000a 2CPE LBGA 144 pinning diagram Preliminary Product Overview 20 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Family Overview 1 6 Logic Symbol VINETIC 4x E AUX ITx Line 7g ITACx TDRSQ current g gt ILx E VCMITx TDI TMO JTAG TMS TM1 interface 4 TCK TM2 testmode DC 1 7 DCPx lop 4 DCNx TDO TM3 eja select CDCPx IFSELO 3 e lt gt CDCNx MCLK TC1Q TC2Q PCM DRI DX1 gt DR2 DX2 gt lt VCMAB lt VCMCD VREFAB lt VREFCD interface AC 17 ACPx PCL loop ACNx FSC Logic lt 7 C1x INTC control C2x IFC6 serial interface 4 IFC so IO0x IFADO lt z gt 101x IFAD1 gt I O s 1 gt 102x IFAD2 oO 103x IFAD3 lt 104x IFAD4 IFAD5 lt CREFAB ES as CREFCD pad IFAD8 Intel cod IFAD9 Motorola VDD33x IFAD10 interface gt GNDx IFAD11 3 VDD18x IFAD12 VDD33AB IFAD13 IFAD14 VDD33CD IFAD15 VDD18AB IFCO Power VDD18CD IFC1 supply GNDAB IFC2 G
34. DCNC VDD33A C2D VDD18A VOMITD VCMITC TCK TM2 DR2 e 008 O VCMITA ILA C2A ILB 9 O O ITACA VDD33A VDD18A VDD33A ACPA O RESETQ VCMITB ITACB CDCNB ACPB DCPB CDCPB O DCPA ACNA ACNB Vinetic_0000a_HDLC_LBGA_144_pinning_diagram_21 Preliminary Product Overview 19 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Family Overview 1 5 PG LBGA 144 Pin Diagram 2 channel devices L CB C D E CF LG H LK t dnc dnc dnc dc dnc dnc dnc dnc dnc dnc dnc dnc e 9 eO 9 9 6 6 9 e dnc dnc dnc ITACD dnc VDD18A VDD RA ITACC dnc dnc dnc e eo e e e 9 9 dnc ITD dnc VCMITD ILD dnc dnc ILC VCMITC dnc ITC dnc e 6 9 9 9 9 e TDRSQ TDI TMO TMS TM1 TEST dnc dnc dnc dnc TDO TMV3 INTQ GNDP VDD18P O eO O VDD83 VDD18 dnc TCK TM2 DRI GNDA GNDA IFC8 PCL IFADA IFAD VDD83 e O O O O DRI DX1 FSC DX1 dnc GND GND IFC7 IFC IFAD6 IFAD5 VDD18 e e 9 6 e GPIOO GPIO1 GPIO2 GPIO3 GPIO4 GND GND GPIO7 IFCO IFAD2 IFADG VDD18 e 0 033 VDD18 GPIO6 RSYNC AUX GNDA GNDA GPIO5 IFC2 IFADO IFAD1 VDD83 e e 6 e e IFSEL2 IFSELO IFSEL1 RESETQ CREFAB VOMAB IO0B IFC3 IFC1 IFC5 IFO6 e 9 9 6 6 6 6 CIA ITA DCNA VOMITA ILA C2A VREFAB ILB VOMITB DCNB ITB C1B e 6 e 9 o o 6 6 6 IO4A 03 CDCNA ITACA VDD33A VDD18A C2B VDD33A ITACB CDCONB 103B 1048 e 6 6 6 6 eO IO1A IO2A
35. F 10 1 R9 error amplifier loop filter 470 ko 5 1 C9 error amplifier loop filter 120 pF 10 96 1 C10 error amplifier loop filter 82 pF 10 96 1 with pnp type switch only Preliminary Product Overview 70 Rev 2 0 2004 05 11 777 9 C Infineon VINETIC technologies Application Circuits 9 2 External Ringing With SLIC E E2 P external ringing is supported however for US market with external ringing the SLIC LCP is the most suitable device as it also provides an automatic longitudinal balance adaptation This reduces BOM cost while maintaining a very good longitudinal balance Figure 18 shows a typical line interface with SLIC LCP An electronic switch LCAS e g Clare CPC 75xx serves as the ring relay The external components are listed in Table 17 for details on overvoltage protection please refer to the respective Application Note Note For stability reasons PCB must be designed with minimum parasitic capacitances at the TIP S and RING S pins values below 10 pF are recommended Table 17 External Components Quant Symbol Function Typ Unit Tolerance Rating Value Matching Rs stability overcurrent limitation 30 Q 1 Yo 2 Rep longitudinal balance feedback 200 ko 5 e g MELF resistors 2 C EMC filtering 10 nF 10 100 V 2 Ret Ring trip voltage divider 750 ko 1 1 Rsense Rring current sense resistor 330 Q 1 Yo 1 Riri IT current voltage co
36. IP for four channels takes care of all the functionality that is voice related All jitter buffering RTP packetization tone generation and detection including event handling and voice processing compression G 72x T 38 fax relay modem modulations line echo cancellation is handled within the DSP of the VINETIC No external memory or other components is needed All the analog functionality is covered at the same time including ringing feeding line testing and supervision The number of POTS lines can easily be increased by adding more VINETIC devices if desired For an FXO operation to connect to the PSTN network the VINETIC devices allow direct connection to DAAs and provide all necessary signal processing functionality like Caller ID detection Preliminary Product Overview 22 Rev 2 0 2004 05 11 777 T Infineon VINETIC technologies Family Overview 8 2 S parallel gic m rud Network Processor E i kl SHDSL Socrates U Sif Sif Par Host Interface vinetic_IAD_POTS_ISDN Figure 6 IAD serving POTS and ISDN European Version Figure 6 shows an highly integrated G SHDSL Integrated Access Device IAD The application consists of four major blocks the SHDSL transceiver the network controller the ISDN S transceiver the I
37. NDCD i IFC3 gt VDD33 64 72 gt VDD18 IFC5 7 GND IFC8 VDD18P 8 E GNDP GPlOn gt RESETQ x synonym for channel A B C D RSYNC n synonym for O 7 Vinetic 0018 logic symbol Figure 4 Logic Symbol VINETIC 4x Preliminary Product Overview 21 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Family Overview 1 7 Typical Applications The following applications are only a small part of the numerous possibilities when using the VINETIC chip set Wireless Mini PCI i Network 10 1006T z e LAN connection Processor Ethernet POTS lines Parallel pC IF tr aic YA m DSP 3 Ur suc VINETIC 2CPE 4VIP E optional suc VINETIC Clare optional DAA p PSIN vinetic residential gateway Figure 5 Residential Gateway ATA VoIP Router Figure 5 shows a residential gateway that allows to extend the home network by introducing VolP and a wireless data connection to it The existing Ethernet connection is terminated by a network processor that enables additional functionality like firewalling routing and other data services as well as the voice call control To keep the network as optimized as possible the VINETIC9 2CPE for two voice channels or the VINETIC 4V
38. PHI ANALOG LINE MODULE lt 2 channels HOST Programmable Host Interface SLIC SLIC ANALOG LINE MODULE lt 2 channels Extended DSP EDSP SLIC SLIC ROM RAM Vinetic_0001_Vinetic_Blockdiagram Figure 1 Block Diagram VINETIC 4x Figure 1 shows the typical block diagram of a VINETIC 4 channel device Preliminary Product Overview 16 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Family Overview 1 1 Pin Diagram VINETIC 4x 1 2 P LQFP 176 2 Pin Diagram Vinetic 0000 pinning diagram Figure 2 P LQFP 176 2 Pin Diagram Preliminary Product Overview 17 Rev 2 0 2004 05 11 lt Infineon technologies 1 3 VINETIC P LBGA 176 3 Pin Diagram Family Overview CAD L3 GNDCD 666 VDD33 TMS TM1 VDD18D VCMITD VDD18CD CREFCD VCMCD VDD33CD VCMITC 9 9 IFSEL3 IFSELO VCMITA ACPA VDD334B ITACA ACNA CREFAB e ILA VDD18B e e GNDB e DCNB 038 Vinetic_0000a_LBGA_pinning_diagram Figure 3 Preliminary Product Overview P LBGA 176 3 Pin Diagram Rev 2 0 2004 05 11 lt Infineon technologies 1 4 Family Overview PG LBGA 144 Pin Diagram 4 channel devices CDCPD TDI TMO DX1 O GPIO1 SCDI IFSEL1 O CD CE CF Ce CA DCPD ACND ACPD ACPC 2016 O ITACD C
39. Preliminary Product Overview Rev 2 0 May 2004 VINETIC Voice and Internet Enhanced Telephony Interface Concept PEB 3324 PEB 3322 PEB 3332 PEB 3320 PEB 3314 PEB 3394 PEB 3304 PEB 4264 2 PEB 4364 PEB 4265 2 PEB 4365 PEB 4266 PEB 4262 PEB 4268 Wireline Communications Infineon Never stop thinking ABM ACE AOP ARCOFI ASM ASP DigiTape DuSLIC EPIC ELIC FALC GEMINAX IDEC INCA IOM IPAT 2 ISAC ITAC IWE IWORX MUSAC MuSLIC OCTAT OptiPort POTSWIRE QUAT QuadFALC SCOUT SICAT SICOFI SIDEC SLICOFI SMINT SOCRATES VINETIC 10BaseV 10BaseVX are registered trademarks of Infineon Technologies AG 10BaseS EasyPort VDSLite are trademarks of Infineon Technologies AG Microsoft is a registered trademark of Microsoft Corporation Linux is a registered trademark of Linus Torvalds The information in this document is subject to change without notice Edition 2004 05 11 Published by Infineon Technologies AG St Martin Strasse 53 81669 M nchen Germany 0 Infineon Technologies AG 5 14 04 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement r
40. SAC SX devices are an option for european IADs and the POTS part including voice processing VINETIC Analog signals from the POTS telephones are terminated within the VINETIC chip set and then digitized In a next step these signals are packetized and sent via tha microprocessor interfaces to the host controller All necessary fucntions for AAL2 or RTP packetization including jitter buffer and compression are executed within the VINETICS Additionally voice and tone processing like DTMF CLIP and line echo cancellation LEC is also performed within the VINETIC chip set When using the optional ISDN transceivers it is also possible to apply the LEC and compression features of the VINETIC chip set to the ISDN channels Voice from the ISAC SX is transferred via PCM to the DSP of the VINETICS where the voice processing is performed The VINETIC is able to handle both voice compression G 723 1 G 728 or G 729 and Near End LEC for up to 4 channels simultaneously or G 726 and LEC for up to 8 channels In the application above all voice channels could be operated with ADPCM compression and line echo cancellation with a single VINETIC chip set without external memory Preliminary Product Overview 23 Rev 2 0 2004 05 11 777 T Infineon technologies VINETIC Family Overview Network Processor Cable Modem Transceiver Cable
41. Short Commands 34 Signaling 12 28 Rev 2 0 2004 05 11 _ Infineon technologies VINETIC Supervision 12 28 T Technology 13 Teletax Metering 12 Testing 29 Transmission Performance 62 Transmit gain 29 TTX 29 TTX Signal Generation 62 U Universal Tone Detection 12 13 31 V V 90 13 Voice Activity Detection 14 Voice Compression 12 VoIP PBX PBX 25 Preliminary Product Overview 85 Index Rev 2 0 2004 05 11 http www infineon com Published by Infineon Technologies AG
42. TIC waa waa 62 8 8 DC Characteristics 63 9 Application Circuits 65 9 1 Internal Ringing Balanced Unbalanced 65 9 1 1 Application Circuits for Internal Ringing 65 9 1 2 Bill of Materials 68 9 1 3 Application Circuits for Internal Ringing with DC DC 69 9 2 External Ringing 71 10 Package Outlines 73 11 Terminology 81 12 TT 84 Preliminary Product Overview 7 Rev 2 0 2004 05 11 lt Infineon technologies List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Preliminary Product Overview 8 VINETIC Page Block Diagram VINETIC 4x 16 P LQFP 176 2 Pin Diagram uuu acu arduus EUER C rd Ren en 17 F LBGA 176 3 Pin Diagram 18 Logic Symbol VINETIC 4x 2 Residential Gateway ATA VoIP Router 22 IAD serving POTS a
43. X X X 4 Crac 1 uF 10 10V X X X 2 CREF 68 nF 20 10 x X x 4 Cext 470 nF 20 10V X X X 4 Cpre 18 nF 5 10V X X X 20 Cis typ 100 nF 10 see x x 21 Ciy typ 1009 nF 10 10V x x x 12 D BAS21 X x 10 ID BAS21 x 4 Overvoltage X X X Element 1 Matching tolerance dependent on longitudinal balance requirements for details see the Application Note External Components For protection see the Application Note Protection of DuSLIC VINETIC Linecard Chip Sets against Overvoltages and Overcurrents 3 Exact value depends on system requirements e g coordination with primary protector According to the highest used battery voltage lVgarnRI for SLIC P and IVyp l or for SLIC E E2 S 9 Depends on layout considerations Voltage rating according to the battery voltage Vig Viatu VBATH VBATR only needed when VBATH and VBATL are different voltages the diodes ensure that Vgat is more positive than Veaty and in case of SLIC P Vata is more positive than VBATR Preliminary Product Overview 68 Rev 2 0 2004 05 11 VINETIC technologies Application Circuits 9 1 3 Application Circuits for Internal Ringing with DC DC Figure 17 shows an example for a typical low cost application of SLIC DC in the P DSO 24 package with a pnp type switching transistor By using a PMOS switch efficiency could be slightly improved The DC
44. XAR E ERR IER ead ac ROS EC d dua ERR e 37 5 6 Data Handling douce dC d ara ER a REOR E c ead 39374 o oou 37 6 Operating Modes 39 6 1 Overview of all VINETIC Operating Modes 39 6 2 Automatic Modes for POTS Signaling and Power Management 41 7 Firmware Architecture 42 7 1 Module Concept 42 7 2 PCM Interface Module 44 7 3 Analog Line Module ALM 45 7 4 Signaling Module eres 46 7 5 Coder Module 49 7 6 Walia AH AA YA as Ew BRR ee aaa 5 8 Electrical Characteristics 52 8 1 Operating Range uz e 52 Preliminary Product Overview 6 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Table of Contents Page 8 1 1 Power Consumption Ilse T 54 8 1 2 Power Up Sequence Va IA 55 8 2 Operating Range SLIC S S2 57 8 3 Operating Range SLIC E E2 58 8 4 Operating Range SLIC P 59 8 5 Operating Range SLIC DC 60 8 6 Operating Range SLIC LCP 61 8 7 AC Transmission VINE
45. art Power Power Power Power Power Power Power Power Power 1 For broadband SLICs for the Infineon ADSL combo solution Integrated Voice and Data IVD GEMINAX S PEB 4561 and GEMINAX S MAX PEF 55801 please contact local sales 2 Chin marked as PEB 4264 3 Chip marked as PEB 4265 Table 3 VINETIC Features VIP M C S 0 VINETIC Features CPE Common Features 2 4 2 4 8 4 4 8 0 Number of fully programmable codecs with enhanced signal processing capabilities e e e e e Pin compatible and software compatible e e e e e Glueless interface to Infineon SLICs family SLIC S S2 TSLIC S SLIC E E2 TSLIC E and SLIC P SLIC LCP and SLIC DC GEMINAX S GEMINAX S MAX Integrated DSP e e e e with RAM for VoIP VoDSL VoATM and software download capability e e e e e for enhanced signal processing e e e e RTP packetization amp jitter buffer adaptive and fixed 200ms e e e e RTCP support e e e AAL2 cell generation amp jitter buffer adaptive and fixed 200ms e e e Compatible with ITU T 1 366 2 e e e e Compatible with RFC 1889 specification e e e e Compatible with Packet Cable specification e e e PacketOverPCM functionality e e e e e e Integrated DTMF generator e e e e e Integrated DTMF decoder e e e e e Integrated Caller ID FSK generator according to Bellcore 202 and V 23 e e e e e Integr
46. ast message to all channels on the VINETIC only SOP COP EOP and short commands CMD 4 0 Command bits defining the type of command SOP COP IOP VOP EVT EOP SUBCMDJ 3 0 Only valid in case of a short command SC 1 and directly sets the operating mode or gives fast register accesse e g the reading of the interrupt register IR CHAN 3 0 Channel identifier 5 4 Second Command Word 5 4 1 Second Command Word in Case of SOP COP and IOP Note The second command word only exists if in the first command word bit SC 0 Bt 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 OFFSET 7 0 LENGTH 7 0 OFFSET 7 0 The second command word specifies the internal offset for the subsequent data words It is possible to send a variable number of data words with one command Preliminary Product Overview 36 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Programming of the VINETIC LENGTH 7 0 Number of following data words binary coded in case of write command or number of data words to be read in case of read commands respectively 5 4 2 Second Command Word in Case of EOP EVT and VOP Note The second command word only exists if in the first command word bit SC 0 For definition of the second command word in case of EOP EVT and VOP see the Preliminary User s Manual Software Description 5 5 Data Words Words following the first and second command words denote data For the data format
47. ated Caller ID FSK detector according to Bellcore 202 and V 23 e e e e e Integrated fax modem detection by Universal Tone Detection unit UTD In band tone detection e e e e e Integrated Universal Tone Generator UTG including holwer tone and japanese tone generation e e e e e Call Progress Tone CPT Detector e e e e Optimized filter structure for modem transmission enhanced modem performance for improvement of V 90 transmission Preliminary Product Overview 13 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Family Overview Table 3 VINETIC Features cont d VIP 2 M C S 0 VINETIC Features CPE e e e e e Multi party conferencing e e e e 3 Party conferencing via packet network e e e e e e G 711 e e e e G 711 Annex I Packet Loss Concealment G 711 Annex II VAD CNG e e e e e G 726 ADPCM e e e G 729 A B e e e G 723 1 e e e G 728 G 728 Annex Packet Loss Concealment e e e 20 e o e iLBc e e e e Voice Activity Detection VAD e e e e Comfort Noise Generation CNG Algorithms for Line Echo Cancellation exceeding G 165 G 168 G 168 2000 G 168 2002 e e upto 128 ms tail length e e e e e upto 16 ms tail length e e e e Voice Play Out reordering fixed and adaptive jitter buffer clock synchronization e e e s Fax Relay Support including all required datapump algorithms V 17 V 21 V 27ter
48. cation Circuits for Internal Ringing All application circuits show only one channel A for the VINETIC SLIC interface and for the ring tip lines Vonis Vonis 1 Vopis Vots 5 Vooss Vobss AM DD33 AGND AGND AGND AGND AGND AGND AGND Vopiea Vopieas Vonis Vpo18e Manasa Vons Vood Overvoltage Protection Channel A gt Roror 200 Rs bos ROT 8 Interface TIP f ist 30 s useable resis or M Mm VINETIC Tip x Parallel or IT serial Interface sdo SLIC S S2 only channel A and SLIC interface pins connected ing for this example Csrab C H L 1 RING IL RING Rogoy 201 Ris fuseable resistor 301 GPIOO GPIO7 gt VCMS IOOA 02 gt PEB 4265 2 PEB 4264 2 PEB 33xy BGND AGND CEXT GND GNDP Co BGND AGND AGND AGND AGND AGND AGND ezm14042V_ES Figure 14 Application Circuit Internal Ringing balanced for SLIC E S Preliminary Product Overview 65 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Application Circuits Overvoltage Protection Rpror 201 TIPfuseable resistor Tip Ring RING Roror 201 fuseable resistor V
49. e feed current Measurement of supply voltage Vpp of the VINETIC 4x Measurement of transversal and longitudinal current Noise Measurement 3 2 3 Board and Production Testing The VINETIC chip set has a set of signal generators and features implemented to accomplish a variety of diagnostic functions that can be used in production tests Various test loops and measurement features are completing this tool suite Preliminary Product Overview 30 Rev 2 0 2004 05 11 Infineon technologies 4 Signalprocessing Capabilities of the VINETIC The VINETIC VIP M and C versions are equiped with an EDSP module Enhanced Digital Signal Processor module to perform voice and tone processing functions The maximum available signal processing capability of the EDSP is limited by the 128 MCycles s and the internal RAM Table 4 gives an overview on the performance demands of the different algorithms functions available and how many resources of them can be activated As each FW version offers a different subset a document is available that lists the available resources per firmware version For further description of the functions refer to VINETIC Signalprocessing Capabilities of the VINETIC Chapter 7 or the VINETIC documentation available Table 4 Provided Algorithms for VINETIC9 Algorithm Function Module MCycle s max of ressources available Operating System typ 15 1 Base load
50. e types of read write commands depending on the HW module to be addressed that differ in the CMD bits of the first command word a status operation SOP commands provide access to configuration and status register of the Analog Line Modules b coefficient operation COP commands enable the configuration of the coefficent registers of the Analog Line Modules c Interface operation IOP commands are needed to set all registers related to the Programmable Host Interface PHI The first command word contains read write bit 15 broadcast bit 13 and channel Preliminary Product Overview 33 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Programming of the VINETIC information The second command word includes the offset of the register address and the number of the following data words Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st word R W 0 BC SOP COP IOP reserved channel 0 2nd word address offset length n x data data only write commands 3 Read Write Commands for EDSP Operation EDSP operations are indicated by an EDSP operation command identifier EOP within the CMD bits of the first command word The first command word contains read write bit 15 broadcast bit 13 and channel information The second command word includes information about the SW module which should be addressed the command and the length of the following data B
51. ections You can find all of our packages sorts of packing and others in our Infineon Internet Page Products http www infineon com products SMD Surface Mounted Device Dimensions in mm Preliminary Product Overview 74 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Package Outlines P DSO 36 15 Plastic Dual Small Outline 6 3 1 74 o al oes Fessi eoc H Mo 0 25 073 oe m gt 0 95 0 5 gt 610 25 WA BC 03 14 2 10 2518 19 38 2 g 3 8 o o n Top View q Index Marking eatslug 1x45 a S o o Metal 1 Does not include plastic or metal protrusion of 0 15 max per side gps09181 Figure 21 TSLIC S PEB 4364 TSLIC E PEB 4365 Note The P DSO 36 15 package is available with heatsink on bottom Attention The heatslug is connected to VBATH via the chip substrate Due to the high voltages of up to 150 V between VHRA VHRB and VBATH touching of the heatslug or any attached conducting part can be hazardous It must be electrically insulated from other parts or board connections You can find all of our packages sorts of packing and others in our Infineon Internet Page Pr
52. efore value must not be exceeded supply tolerances have to be taken into account For impact on overvoltage protection see the Application Note Protection for SLIC S S2 PEB 4264 2 against Over Voltages and Over Currents Operation up to Tj 150 C possible However a permanent junction temperature exceeding 125 C could degrade device reliability 2 Preliminary Product Overview 57 Rev 2 0 2004 05 11 _ Infineon technologies VINETIC Electrical Characteristics 8 3 Operating Range SLIC E E2 Table 9 Operating Range SLIC E E2 Parameter Symbol Limit Values Unit Note Min Max Battery voltage L VBATL 80 15 V Referred to BGND Battery voltage H 1 VBATH 85 20 V Referred to BGND Auxiliary supply voltage Vun 5 85 V Referred to BGND Total battery supply Vur VBATH 150 V voltage Vpp supply voltage Vpp 4 75 525 V Referred to AGND Ground voltage 0 4 0 4 V difference BGND AGND Voltage at pins IT IL Vit Vi 0 4 3 5 V Referred to AGND Input range Vpcp VpcN Vacpc 0 3 3 V Referred to AGND VacP VACN Ambient temperature Tamb 40 85 C Junction temperature T x 1252 6 j 1 If the battery switch is not used pins Viatu and Vpaty should be connected externally In this case the full voltage range of 15 V to 85 V can be used 2 degrade device reliability Preliminary Product Overview 58 Operation up to T
53. egarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail itis reasonable to assume that the health of the user or other persons may be endangered Preliminary Product Overview Revision History 2004 05 11 Rev 2 0 Previous Version none Page Subjects major changes since last revision VINETIC 2CPE added Featurelist updated gm 6 Infineon VINETIC technologies Preface This Preliminary Product Overview describes the Voice and Internet Enhanced Telephony
54. especially in case of packet based information VOP and EVT see the Preliminary User s Manual Software Description Bt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 15 0 5 6 Data Handling The VINETIC includes an interface controller Programmable Host Interface PHI which handles the communication between the host and the VINETIC 4x internal units via a SW state machine The VINETIC handles packet data VOP EVT commands command data COP SOP IOP EOP commands and short commands SC bit of first command word is set as well as a direct memory access of the interrupt register DIA for SW handshake RDYQ bit in the DIA In downstream direction packet data sent by the host to the VINETIC or PHI respectively is stored in a in buffer packet in box and command data is stored in another in buffer command in box Subsequently these data are transferred to the EDSP of the VINETIC In upstream direction packet command data are transferred from the EDSP to internal out buffers packet out box command out box and the VINETIC notifies the host controller via status registers and interrupt that data is ready for reading The host can read the packet or command out box via short commands rPOBX read packet out box rCOBX read command out box Because of varying command recovery times the VINETIC supports HW and SW handshake for speed optimization of the data transfer The HW handshake is done via t
55. fic basis but also concurrently on all channels This allows a strong reduction of the testing time compared to conventional test methods Thus VINETIC helps to increase quality of service and to reduce costs The VINETIC line testing supports GR 909 line testing requirements Preliminary Product Overview 29 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Codec SLIC Features BORSCHT Functions Line Test Capabilities The line test comprises the following functions Loop resistance measurement The DC loop resistance can be determined by supplying a constant DC voltage Vin pc to the Ring and Tip line and measuring the DC loop current via the IT pin Leakage current Leakage current Tip Ring Leakage current Tip GND Leakage current Ring GND Ringer Line capacitance Capacitance measurements can be performed by using the integrated ramp generator function Loading a capacitor CMeasure with a constant voltage ramp results in a constant current which is proportional to Cyeasure Line capacitance Tip GND Line capacitance Ring GND Foreign voltage measurement Three analog input pins per voice channel can be used for direct and differential measurement of external voltages Foreign voltage measurement Tip GND Foreign voltage measurement Ring GND Foreign voltage measurement Tip Ring Supervision of Battery voltages Measurement of ringing voltage Measurement of lin
56. he RDYQ line of the VINETIC and the SW handshake is done via the RDYQ bit in the Preliminary Product Overview 37 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Programming of the VINETIC DIA register To enable a fast access to the DIA register the DIA register can be addressed directly via the DIA command All other registers as well as the command and packet in and out box can t be addressed directly For this the PHI handles the data transfer by address auto incrementation Short commands are treated seperately and with higher priority than packet and command data and are not handled via the command mailbox To optimize the data transfer during download and or for packet transmission the size of the in boxes command packet can be changed with the short commands wMAXCBX Maximize command in box size Command in box size 255 Packet in box size 31 and wMINCBX Minimize command in box size Command in box size 31 Packet in box size 255 The size of the out boxes cannot be changed Before the host writes data to the VINETICS it has to make sure that there is enough free memory space in the desired packet and or command in box This is done by reading the FIBXMS free in box memory space register via the short command rFIBXMS As long as there is enough free memory space in the in boxes packets commands the host is allowed to send data Every 125 us the VINETIC internal EDSP
57. ion see the User Manual Software Description VINETIC uses a flexible command structure which can be used with parallel and serial interfaces Note In the following chapters downstream indicates the direction from the host controller to the VINETIC upstream the direction from VINETIC to the host controller 5 1 Command Data Structure in Downstream Direction Each command consists either of one single command word or of two command words followed by data The first command word contains information about the read write status the type of the command mode and the VINETIC channel addressed The second command word defines length and destination or source respectively for control data or in case of packet data only the length information Four different command types can be distinguished 1 Packets Packets are indicated by a voice packet operation identifier VOP or a packet based event transmission operation identifier EVT within the CMD bits of the first command word The first command word contains read write bit 15 and channel information also The second command word includes the number of following data words and the information if there is an even or odd number of bytes in the packet Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 istword R W 0 0 VOP EVT reserved channel 0 2nd word reserved ODD reserved length n x data data 2 Read Write Commands for Register Access There are thre
58. it 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st word RW 0 BC EOP reserved channel 0 2nd word SW module extended command length n x data data only write commands 4 Short Commands Short commands consist of the first command The first command word contains read write bit 15 broadcast bit 13 and channel information also Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st word RW 1 BC command or operational state channel 0 Preliminary Product Overview 34 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Programming of the VINETIC 5 2 Command Data Structure in Upstream Direction In upstream direction four different data types can be distinguished 1 Packets Packets in upstream direction have the same command structure as packets in downstream direction but the R W bit of the first command word is set The SC bit is always cleared the CMD bits indicate a voice packet operation VOP or a packet based event transmission operation EVT and the CHAN bits specify the corresponding channel The second word includes the number of following data words and an indication whether there is an even or odd number of bytes in the packet Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st word R W 0 0 VOP EVT reserved channel 1 2nd word reserved ODD reserved length n x data data 2 Responses to Read Commands for Register Access Responses to read com
59. j 150 C possible However a permanent junction temperature exceeding 125 C could Rev 2 0 2004 05 11 lt Infineon technologies VINETIC Electrical Characteristics 8 4 Operating Range SLIC P Table 10 Operating Range SLIC P Parameter Symbol Limit Values Unit Test Condition Min Max Battery voltage L Vaart 140 15 V Referred to BAND Battery voltage H Vaart 145 20 V Referred to BAND Battery voltage R VBATR 150 25 V Referred to BAND Total battery supply Vpp VeatrR 155 V voltage Vpp supply voltage Vpp 3 1 5 5 V Referred to AGND Ground voltage VBaGND gt 0 4 0 4 V difference VAGND Voltage at pins IT IL Vir Vi 0 4 3 5 V Referred to AGND Input range Vpocp Vacpc 0 3 3 V Referred to AGND Voen Vacp VACN Ambient temperature Tamb 40 85 C Junction temperature T 1252 jec 1 if only two battery voltages are used pins VBATL and VBATH should be connected externally 2 Operation up to Tj 150 C possible However a permanent junction temperature exceeding 125 C could degrade device reliability Preliminary Product Overview 59 Rev 2 0 2004 05 11 lt Infineon technologies VINETIC 8 5 Operating Range SLIC DC Table 11 Operating Range SLIC DC Electrical Characteristics Parameter Symbol Limit Values Unit Note Min Max
60. j VD fpu D18P 0 ms i A AB B C CD D Preliminary Product Overview 55 Rev 2 0 2004 05 11 Infineon VINETIC technologies Electrical Characteristics Note No voltage is to be applied to any input or output pin before the VDD33 voltages are applied Preliminary Product Overview 56 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Electrical Characteristics 8 2 Operating Range SLIC S S2 Table 8 Operating Range SLIC S S2 Parameter Symbol Limit Values Unit Notes Min Max Battery voltage L VBATL 60 15 V Referred to BAND Battery voltage H 1 VBATH 65 20 V Referred to BGND Auxiliary supply voltage Vun 3 1 45 V Referred to BGND Total battery supply Vun 902 V i voltage VBATH Vpp supply voltage Vbpp referred to AGND 4 75 5 25 V SLIC S V 1 1 3 1 5 5 V SLIC S V 1 2 Ground voltage 0 4 0 4 V difference BGND AGND Voltage at pins IT IL Vito Vy 0 4 Vpp V Referred to AGND Input range Vpcp VpcN Vacpc 0 3 3 V Referred to AGND VacP VACN Ambient temperature Tamb 40 85 C j Junction temperature T 1259 C j 1 If the battery switch is not used pins VBATL and VBATH should be connected externally In this case the full voltage range of 15 V to 65 V can be used Y This value is identical with the maximum rating value ther
61. mands for register access starts with the copy of the corresponding read command first and second command word sent by the host followed by the requested data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st word RAW 0 BC SOP COP IOP reserved channel gt 2nd word address offset length n x data data 3 Responses to Read Commands for EDSP Operation Responses to read commands for EDSP operation EOP start with the copy of the corresponding read command first and second command word sent by the host followed by the requested data Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1st word RW 0 BC EOP reserved channel 1 2nd word SW module extended command length n x data data Preliminary Product Overview 35 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Programming of the VINETIC 4 Responses to Short Commands Responses to short commands do not repeat the command header because they will be provided within a given command recovery time Therefore only the requested data will be returned 5 3 First Command Word Bt 15 14 13 12 11109 8 7 6 5 4 3 2 10 R W SC BC CMD 4 0 reserved CHAN 3 0 SUBCMD 3 0 R W Read Write bit for defining a read or write command SC Short Command bit defining the short commands for a fast register access to VINETIC or operating mode change BC Broadcast bit defining a broadc
62. mily Overview The VINETIC is a family of devices for analog telephone line provision VINETIC devices are available in different granularity 0 2 4 and 8 analog voice channels and also with different levels of DSP performance VIP CPE M C S The seamless connection to a broad range of SLICs provides the most effective solution for a wide range of applications from high density CO DLC PBX linecards to low cost CPE applications Significant boardspace reduction can be achieved through the integrated DSP for voice processing and packetization The VINETIC provides system solutions for the following applications Access Network Central Office TDM Digital Loop Carrier TDM VoATM VoIP FTTH TDM VoATM VoIP WLL TDM VoIP PBX Analog Linecard TDM VoIP Customer Premises Equipment Residential Gateway Home Gateway Internet Telephony Gateway ITG VoIP Integrated Access Device IAD VoIP VoATM Cable Modems Media Terminal Adapter MTA VoIP Analog Telephony Adapter ATA VoIP To cover these applications the VINETIC devices are pin and software compatible allowing the maximum flexibility while offering the optimized feature set per application Preliminary Product Overview 10 Rev 2 0 2004 05 11 lt Infineon technologies Voice and Internet Enhanced Telephony Interface Concept VINETIC Executive Summary The VINETIC family integrates the DSP
63. nF LCAS ove H VBATH u pi acres napas R C 10 nF P FB RING S T e Rs RING 1 CEXT p n CDCNA RING OCP 309 Vring CT T d ir AGND porn sa 10 kQ INyest INGinging gm a a Rar 1 200 Q R 330 0 750 ka 1 RTN 4 750 196 i VRNG La Voe RD16 T Me VOMS LVREFAB RD IC1A T a mE Logic c2 5624 A d I 101 RDG mur CREFAB VERTI VBATL VDD AGND BGND aco E CNDAB Ga DAL DA Coan ri H Figure 18 Application Circuit External Ringing for SLIC LCP Preliminary Product Overview 72 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Package Outlines 10 Package Outlines P DSO 20 5 Plastic Dual Small Outline 0 95 t 0 15 14 2 03 5025 WB Yo E m Top View TEBEH EEEH Heatsink 0 15 9035 Index Marking 1 Does not include plastic or metal protrusion of 0 15 max per side Gps05755 Figure 19 SLIC S S2 SLIC E E2 SLIC P PEB 426x Note The P DSO 20 5 package is designed with heatsink on top The pin counting for this package is clockwise top view Attention The heatsink is connected to VBATH VBATR via the chip substrate Due to the high voltage of up to 150 V between VHR and VBATH BGND and VBATR touching of the heatsink or
64. nalog line SLIC P offers in addition the option of feeding the VBATR voltage On off hook an comparator in the SLIC wakes the VINETIC No debouncing of spikes is performed in this case Power Down Modes Power Down High Impedance The selected channel of the VINETIC is powered down with internal clocks and deglitching logic running but no voice signals are processed The SLIC is high impedance on the analog line This is the preferred state for a fault condition or an inactive line Power Down Resistive The selected channel of the VINETIC is powered down with internal clocks and deglitching logic running but no voice signals are processed The SLIC feeds via an internal resistor the VBATH battery voltage SLIC P offers in addition the option of feeding the VBATR voltage onto the analog line Off hook detection is supported with programmable threshold values and a debounce timer This is the preferred state for an on hook telephone Active Modes Active Low and Active High In active mode the complete voice path of the VINETIC is active and also the SLIC is feeding the line In active low the VBATL battery supply and in active high the VBATH battery supply is used This is the preferred state for off hook telephone conversation and for on hook transmission Active Boost Preliminary Product Overview 39 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Operating Modes This special active mode
65. nd ISDN European Version 23 Cable Modem Settop Box SMTA EMTA 24 Next Generation Access Network Linecard 25 Module Concept 42 PCM Interface Module 44 Analog Line Module ALM 45 Signaling Module 46 Coder Channel Module 50 Application Circuit Internal Ringing balanced for SLIC E S 65 Application Circuit Internal Ringing balanced for TSLIC E S 66 Application Circuit Internal Ringing bal amp unbal for SLIC P 67 Application Circuit Internal Ringing with DC DC 69 Application Circuit External Ringing for SLIC LCP 72 SLIC S S2 SLIC E E2 SLIC P PEB 426x 73 SLIC S S2 SLIC E E2 SLIC P PEB426x SLIC LCP PEB 4262 74 TSLIC S PEB 4364 TSLIC E PEB 4365 75 SLIC DC PEB 4268 76 SLIC DC PEB 4268 77 VINETIC 4x PEB33x4HL VINETIC 2VIP PEB 3322HL and VINETIC9 0 PEB3320HL 78 VINETIC 4x PEB33x4E VINETIC 2VIP PEB 3322E and VINETIC9 0 PEB3320E 79 VINETIC 2CPE PEB 3332 VINETIC 4M PE
66. nd start is supported Testing Modes Testing modes are extensions of the active modes using various SLIC settings Ring or the Tip wire can be set to high impedance all SLICs or GND only SLIC P Ring and Tip wire can be set both to High Impedance and all SLICs or in addition to have some impedance for testing purposes only SLIC E v1 2 and Preliminary Product Overview 40 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Operating Modes GEMINAX S MAX All these modes are intended for line testing and diagnosis functions 6 2 Automatic Modes for POTS Signaling and Power Management The following automatic modes can be switched on off by the user AUTOMOD Automatic Mode Register 1 Automatic mode Off hook detection Auto Off hook Automatic switching to Active Mode after off hook was detected Power Down PDRH PDRR Ringing Ring Pause Active Automatic switching to the current mode set by the host indicated by MODE SRC bits in register OPMOD SRO after on hook was detected Active gt host mode Automatic mode Battery Switching for Power Management Auto Battery change from ACTH to ACTL A change will take place only once after off hook was detected A further change will not result in a mode change Automatic mode Power Down Over Temperature Automatic switching to Power Down High Impedance mode when the SLIC detects overtemperature Automatic Ring Cadencing2
67. ng In addition the SLIC DC integrates a DC DC converter and simplifies CPE applications significantly while reducing BOM cost at the same time e Signaling Supervision VINETIC detects off hook in both non ringing hook switch detection and ringing modes ring trip detection The thresholds for ring trip detection within VINETIC 4x can be programmed without changes to external components Coding VINETIC 4x encodes an analog input signal to a digital PCM signal and decodes a PCM signal to an analog signal Both A law and p law coding is supported and can be selected via software Some members of the VINETIC family also add ADPCM coding and low bitrate vocoders Hybrid for 2 4 wire Conversion The subscriber equipment is connected to a 2 wire interface Tip and Ring where information is transmitted bidirectionally For digital transmission through the switching PSTN network the information must be split into separate transmit and receive paths 4 wires To avoid generating echoes the hybrid function requires a balanced network Preliminary Product Overview 28 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Codec SLIC Features BORSCHT Functions matched to the line impedance Hybrid balancing can be programmed in the VINETIC device without any external components Testing In conventional solutions testing of local loop and linecard requires a remote test unit and test relays VINETIC
68. nnel Popactt 1 8 V 110 mW VINETIC 4S Power Down PDH other channels 120 mW VINETIC 4C 130 mW VINETIC 4M 150 130 mW VINETIC 4VIP 4002 Pppacti 3 3 V 90 mW al Preliminary Product Overview 54 Rev 2 0 2004 05 11 _ Infineon technologies VINETIC Electrical Characteristics Table 6 Power Consumption VINETIC cont d Parameter Symbol Limit Values Unit Test Condition Min Typ Max Remark Active one channel Popacti 1 gv 120 mW VINETIC 4S Power Down Resistive other 1302 mW VINETIC 4C channels 140 mW VINETIC 4M 160 140 mW VINETIC 4VIP 4002 Pppacti 3 3 V 120 mW Jall Active 4 channels Popacta 1 8 V 140 mW VINETIC9 4S 170 mW VINETIC 4C 200 mW VINETIC 4M 2802 200 mW VINETIC 4VIP 4002 PppAct 3 3 V 280 mW jall 1 In Active modes the values of both supply rails 3 3 V and 1 8 V have to be added The power values represent the latest generation For details on power consumption per version refer to version specific device datasheet 2 8 1 2 Depends on used EDSP load representing the enabled features Power Up Sequence VINETIC The 3 3V supply has to be applied before the 1 8V supply Table 7 Power Up Sequence VINETIC Parameter Symbol Limit Value Unit Test Min Typ Max Condition Time between power up of VDD33 VDD33i and VDD18 VDD18
69. nv AC 510 Q 1 1 Rite IT current voltage conv 680 Q 1 1 Ry IL current voltage conv AC 1 6 ko 1 1 Cext Common mode output 470 nF 20 10 V voltage filtering 1 Chat Supply voltage blocking 100 nF 20 100 V CBATH 1 Citac AC separation on IT 1 UF 110 10 V 1 CpRE IT lowpass only necessary 18 nF 5 10V with 12 16 kHz metering 1 Cpc DC lowpass filtering 220 nF 10 10V 1 CREF 68 nF 20 10 V 3 D1 D2 Substrate overvoltage BAS21 D3 protection 1 LCAS Linecard Access Switch e g CPC 75xx electronic ring relay Preliminary Product Overview 71 Rev 2 0 2004 05 11 VINETIC technologies Application Circuits Table 17 External Components Quant Symbol Function Typ Unit Tolerance Rating Value Matching 1 OVP Overvoltage Protection e g gate triggered thyristorintegrated in LCAS 2 OCP Overcurrent Protection e g LFR fuse PTC 1 depending on overvoltage requirements 2 depending on overvoltage requirements SLIC LCP PME VI N ETI C X l e g CPC75xx T TIP T n 34 RSYNC TIP OCP Rs oe T ACT T T Ace er 4 o 1 ACN E 1 ACMA Res WA n nh 200 k d NN C T 10
70. oduct Overview 82 Rev 2 0 2004 05 11 Infineon VINETIC technologies Terminology VoIP Voice over IP X xDSL all flavors of Digital Subscriber Line Preliminary Product Overview 83 Rev 2 0 2004 05 11 _ Infineon technologies VINETIC 12 A Advanced Integrated Test and Diagnostic Functions 29 Index B Balanced ringing 65 Battery Feed 28 Broadcast bit 36 C Caller ID 12 13 31 Channel or resource number 36 Coding 28 Comfort Noise Generation 14 Command bits 36 D Distortion 62 DTMF 12 31 E EDSP 31 External ringing 14 F Fax Relay Support 14 First Command Word 33 36 Frequency response 29 62 G G 711 31 G 723 32 G 726 32 G 728 32 Group Delay 63 H Hybrid 12 28 Hybrid balance 29 Preliminary Product Overview Index Idle Channel Noise 62 Impedance matching 29 Integrated Access Device 23 Internal Ringing 12 ITU T G 728 14 L Line Echo Cancellation 14 31 Line Termination Tip Ring 63 Longitudinal Balance 62 Message Waiting 14 Multi party conferencing 14 0 On hook transmission 14 Operating Modes 39 Overvoltage protection 28 P Parallel Host Interface PHI 15 PCM uC Interface 15 Polarity Reversal 14 R Read Commands for EDSP Operation 35 for Register Access 35 Read Write bit 36 Receive gain 29 Responses to short commands 36 Ringing 12 28 S Second Command Word 33 Serial control interface 15 Short Command bit 36
71. oducts http www infineon com products SMD Surface Mounted Device Dimensions in mm Preliminary Product Overview 75 Rev 2 0 2004 05 11 Ya 9 Infineon VINETIC technologies Package Outlines 0 35 x 45 P DSO 24 1 3 Plastic Dual Small Outline 2 65 MAX 1 27 Si 110 2 24x Index Marking Does not include plastic or metal protrusion of 0 15 max per side Lead width can be 0 61 max in dambar area Figure 22 SLIC DC PEB 4268 Preliminary Product Overview 76 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Package Outlines P TQFP 48 1 Plastic Low Profile Quad Flat 0 12 0 05 71 lt 2 0 2 A B D 48x Index Marking Does not include plastic or metal protrusion of 0 25 max per side Figure 23 SLIC DC PEB 4268 Preliminary Product Overview 77 Rev 2 0 2004 05 11 _ e Infineon VINETIC technologies Package Outlines P LQFP 176 2 Plastic Low Profile Quad Flat Package 03 0 08 0 7 MAX H 1 4 0 05 cC Cn B
72. of internal control Command Mailbox handling DTMF Receiver Signaling 1 0 4 Caller ID Transmission Signaling 1 5 4 Universal Tone Detection UTD V 18 Signaling 1 2 4 ATD 2 1 KHz Modem Tone Detection with Signaling 1 3 4 Phaseshift phase reversal amplitude modulation DIS DTMF generation Signaling 1 8 4 Near End Line Echo Cancellation LEC PCM ALM 4 G 165 G 168 NLP included Coder LEC 8 ms 4 4 LEC 16 ms 5 4 Far End Line Echo Cancellation G 168 NLP PCM ALM 4 incl Coder LEC 32 ms 11 0 LEC 64 ms 17 0 LEC 128 ms 29 0 G 711 block based b 5ms Coder 5 09 8 G 711 G 711 Annex I BFI G 711 Annex VAD CNG jitter buffer protocol handling G 711 sample based PCM 0 6 16 Preliminary Product Overview 31 Rev 2 0 2004 05 11 Infineon technologies VINETIC Signalprocessing Capabilities of the VINETIC Table 4 Provided Algorithms for VINETIC9 cont d Algorithm Function Module MCycle s max of ressources available G 711 Annex BFM Coder 0 6 8 G 711 Annex VAD CNG Coder 0 7 8 G 726 for Coder Module block based 11ms Coder 11 49 8 G 726 for PCM Module sample based PCM 5 5 G 723 1 packet size 30 ms Coder 12 49 4 G 729 A B packet size 10 20 ms Coder 10 79 4 G 729 A B E packet size 10 20 ms Coder 20 9 4 G 728 packet size 5 10 15 20 ms incl Coder 19 59 4
73. r Symbol Conditions Limit Values Min Typ Max Unit Group Delay please refer to Preliminary User s Manual System Reference 1 SLIC version used in the chip set system Also TSLIC S and TSLIC E possible 8 8 DC Characteristics TA gt 40 C to 85 C unless otherwise stated Table 14 DC Characteristics Parameter Symbol Conditions Limit Values Unit Min Typ Max Line Termination Tip Ring Sinusoidal Ringing Max ringing voltage VmNao Vur Veat 150 V 85 Vrms Voc 20 V for ring trip SLIC E E2 VBATR 150 V 85 Vrms Voc 20 V for ring trip SLIC P Vur lt VBATH 85 V 45 Vrms Voc 15 V for ring trip SLIC S S2 Trapezoidal Ringing Max ringing voltage Vpngo Vur Veat 150 V 1100 Vrms Crest factor 1 2 Voc 20 V for ring trip SLIC E E2 VBATR 150 V 100 Vrms Voc 20 V for ring trip SLIC P VHR VBATH 85 V 52 Vrms Voc 15 V for ring trip SLIC S S2 Preliminary Product Overview 63 Rev 2 0 2004 05 11 lt Infineon technologies VINETIC Electrical Characteristics Table 14 DC Characteristics cont d Parameter Symbol Conditions Limit Values Unit Min Typ Max Output impedance Rout SLIC output buffer and 61 Q RSTAB Harmonic distortion THD 5 96
74. r ID detection Universal Tone Generator coverina Japanese Tones Call Proaress Tone detector Advanced Intearated Test and Diaanosis Functions Battery feed Ringing Signaling supervision Coding Hybrid for 2 4 wire conversion Testing Hook thresholds Teletax metering Versions up to v1 4 provide also RAM for firmware download Table 2 SLIC Versions Marketing SLIC S TSLIC S SLIC S2 SLIC E TSLIC E SLIC E2 SLIC P SLIC LCP SLIC DC Name Product ID PEB 4264 PEB 4364 E 4264 PEB 4265 PEB 4365 4265 PEB 4266 PEB 4262 PEB 4268 2 2 Channels 1 2 1 1 2 1 1 1 1 Internal 45 Vrms 45 Vrms 45 Vrms 85 Vrms 85 Vrms 85 Vrms 85 Vrms external DC DC Ringing balanced balanced balanced balanced balanced balanced bal ringing generator 50 Vrms included unbal 60Vrms Longitudinal 53 dB 53 dB 60 dB 53 dB 53 dB 60 dB 53 dB 6008 with 48 dB Balance adaption to external compon ents Maximum 32 mA 32 mA 50 mA 32 mA 32 mA 50 mA 32 mA 50 mA 32 mA DC feeding Neg Battery 2 2 2 2 2 2 2 3 2 0 Voltages Preliminary Product Overview 12 Rev 2 0 2004 05 11 9 Infineon technologies VINETIC Family Overview Table 2 SLIC Versions cont d Add positive 1 1 1 1 1 1 0 0 1 Voltages unreg 12 35V Technology 90V 90 V 90 V 170 170 170 V 170 V 170 V 170 Smart Smart Smart Smart Smart Smart Smart Smart Sm
75. ram only a short coding for the DTMF and the AT frequen cies In the latter case the generator uses predefined frequencies The host can select between two modes It can control the whole timing by itself or it can use an automatic mode In case of an automatic mode the host only has to set the frequencies and the generator controls the timing of the tones automatically The generator supports event transmission also For event transmission the generator provides two special modes which are optimized for the RTP and AAL2 support For the CID Sender submodule no event transmission support is available The host can use the sender to send CID information according to V 23 or Bell 202 to an analog phone The sender is configurable to cover all country specifications The CID Receiver can be used for FXO applications and detects FSK signals accord ing to V 23 or Bell 202 standard The Universal Tone Generator UTG can generate a wide variety of tones allowing also modulated multitones This is required for howler tone generation and meeting the japanese tone specification The Call Progress Tone Detector CPT tracks in band notification signals busy hang up and notifies the host accordingly Event processing is completely handled by the Event Transmit and the Event Play Out Preliminary Product Overview 47 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firmware Architecture units The Event Transmit Uni
76. red interface type is selected by means of pin strapping Preliminary Product Overview 27 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Codec SLIC Features BORSCHT Functions 3 Codec SLIC Features BORSCHT Functions 3 1 BORSCHT functions Battery Feed The DC battery feed for the subscriber equipment has to be adapted to different applications and country specific requirements With the VINETIC chip set the feed characteristic is programmable in a wide range without any hardware change Overvoltage Protection Overvoltage protection is indispensable to prevent damage to the line circuit if the system is exposed to high voltages that can result from power lines crossing or lightning strikes The robust high voltage SLIC technology together with low cost external protection components form a reliable overvoltage protection solution for the SLIC against overvoltages from the Tip and Ring lines e Ringing The VINETIC9 chip set integrates the ringing generator thus reducing the BOM by obsoleting the ring relay and ring generator VINETIC supports unbalanced and balanced ringing up to 85 Vans With balanced ringing the ringing voltage is applied differentially to the Tip and Ring lines With unbalanced ringing the ringing voltage is applied single ended to either the Tip or Ring line Balanced ringing is generated by SLIC E E2 and SLIC S while SLIC P can generate both balanced and unbalanced ringi
77. ronous Transfer Mode C CAS Channel Associated Signaling CNG Comfort Noise Generation Codec Coder Decoder CPE Customer Premises Equipment D DAC Digital Analog Converter DC Direct Current DSP Digital Signal Processor DTMF Dual Tone Multi Frequency E EDSP Enhanced Digital Signal Processor F FSK Frequency Shift Keying G GPIO General Purpose Input Output H HW Hardware l IAD Integrated Access Device ITU International Telecommunication Union IP Internet Protocol Preliminary Product Overview 81 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies ISDN JTAG LSSGR NG DLC NT PBX PCM POTS RAM RBS RTCP RTP SLIC T TG TS TTX U UTD V VAD VINETIC VINETICOS VoATM VoDSL Terminology Integrated Services Digital Network Joint Test Action Group Local area transport access Switching System Generic Requirements Next Generation Digital Loop Carrier Network Terminal Private Branch eXchange Pulse Code Modulation Plain Old Telephone Service Random Access Memory Robbed Bit Signaling Real time Transport Control Protocol Real time Transport Protocol Subscriber Line Interface Circuit Tone Generator Time Slot Teletax Universal Tone Detection Voice Activity Detection Voice and Internet Enhanced Telephony Interface Concept Voice and Internet Enhanced Telephony Interface Concept Coefficients Software Voice over ATM Voice over DSL Preliminary Pr
78. t receives the events from the DTMF Receiver ATD1 and ATD2 adds the event header and forwards the event to the packet out box The Event Play Out Unit reorders the received events and synchronize them with the play out time of the corresponding coder channel decoder path The status information of all submodules are written into the status registers Preliminary Product Overview 48 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firmware Architecture 7 5 Coder Module The coder module supports up to 8 channels and has two different interfaces The interface for the sample based side is the signal array decoder output and encoder input and the packet based interface is the packet mailbox That means for example that in receive direction a G 723 decoder and in transmit direction a G 729 encoder can be activated Each Encoder supports a Voice Activity Detection VAD For the VAD either a part of the standard solution or an Infineon proprietary solution can be used Each decoder supports comfort noise generation CNG and packet loss concealment PLC Each channel supports the following features G 723 1 A G 726 ADPCM G 728 G 729 A B E e G 711 Annex packet loss concealment II VAD CNG format encoder and decoder VAD CNG for G 711 G 726 VINETIC provides a proprietary VAD CNG and signal power estimation Packet Loss Concealment as described in G 711 Annex for G 711 and G
79. ut voltage Vou 2 4 V lop 5 mA Low level output voltage VoL 04 Io 5 mA Input leakage current Iy uA Vpp33 3 3 V VaNpD 20 V all other pins are floating Vin O0V Output leakage current loz 1 uA Vpp33 3 3 V 0 V Vout 9 Input capacitance at digital 5 pF signal pins except lOOx lO1x IO2x lO3x lO4x x A B C D Input transition rise or fall time 0 5 ns at digital signal pins except 00 101x 102x IO3x 104x x A B C D Ambient temperature under TA 40 85 C bias 0 85 0 VINETIC 2CPE Preliminary Product Overview 53 Rev 2 0 2004 05 11 lt Infineon VINETIC technologies Electrical Characteristics 8 1 1 Power Consumption VINETIC TA 40 C to 85 C unless otherwise stated Voois VppisA VppisAB VppiseB Vppisec Vppiscp Vppisp VppieP 18V 5 Vppas VppasA Vpp33AB Vppssa Vppsasc Vppsscp Vppssp 3 3 V 5 Yo VaNpA YGNDAB YGNDB YGNDG Vennen YGNDD Vanpp 0 V Table 6 Power Consumption VINETIC Parameter Symbol Limit Values Unit Test Condition Min Typ Max Remark Power consumption in operation modes Deep Sleep PppDsSleep 60 mw Sleep all channels Pppsieep 1 8 v 70 mW MCLK PCLK PppSleep 3 3 V 50 mW 2 Mrz Power down PDH Poppp 1 8 v 70 mW all channels PppppH 33 V 25 mW Power Down PDDPDRH 100 mW PDRH all 18V channels PpDPDRH 80 mW 33V Active one cha
80. ware Architecture Each module contains 4 8 or 16 channels Each channel of each module can be connected with any channel of any module via the Signal Array The global signal array contains the output values of each channel from every module Each channel input signal of each module can be connected with any signal in the signal array With the concept of the global Signal Array the applied module functions can be adapted very easily and flexible to the needs of different applications Typical module configurations will be provided by Infineon Note Different firmware versions will provide subsets of the firmware modules described in this chapter Note Check Firmware Status Sheet documentation for the exact number of supported modules and features within the modules Preliminary Product Overview 43 Rev 2 0 2004 05 11 _ Infineon VINETIC technologies Firmware Architecture 7 2 PCM Interface Module The PCM Interface module supports up to 16 channels Each channel can be activated separately and supports the following features Decoder and encoder G 726 G 711 without annex and ll without CNG and VAD RBS CAS filtering for enhanced modem performance 1 e Conferencing via ADDER submodule e Gain lt DC HP DC high pass e LEC far end near end with NLP Figure 10 shows one channel of the PCM Interface module PCM Interface Module Any G 711 ed ue Signal Array 7

VINETIC

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