CHAPTER 1 - Electro Systems Associates
Contents
1. CMD53 EQU 83H CMD5 EQU 91H DAT5 EQU 90H ADDRESS OPCODE LABLE MNOMONIC COMMENTS ORG 8000H 8000 11 0A 00 LXI D 000AH TIMER O for 9600 BAUD 8003 3E 36 MVI A 36H TIMER O IN MODE 3 8005 D3 83 OUT CMD53 8007 7B MOV A E LOAD LSB VALUE 8008 D3 80 OUT 80H 800A 7A MOV A D LOAD MSB VALUE 800B D3 80 OUT 80H 800D AF XRA A DUMMY MODE 800E D3 9 OUT CMD51 WRITE DUMMY word 8010 D3 91 OUT CMD51 IN MODE reg 8012 D3 91 OUT CMD51 8014 D3 91 OUT CMD51 8016 3E 40 MVI A 40H RESET 8251 8118 D3 91 OUT CMD51 801A 3E CE MVI SET 8251 FOR 801C D3 91 OUT CMD51 ASYNCHRONOUS 16 16X baud 2 STOP 5 8 data bits No parity 801E 3E 27 MVI A 27H WRITE COMMAND Word 8020 D3 91 OUT CMD51 8022 21 00 90 LXI H 9000H MEMORY TO STORE the character 8025 06 33 MVI B 33H CHARACTER 8027 DB 9 STATUS IN CMD51 GET USART Status 8029 E6 8 ANI 81H RECEIVER READY 802B FE 81 CPI 81K NO WAIT 802D C2 27 80 JNZ STATUS GET CHARACTER FROM USART 8030 7E MOV A M 22 HAD User s Manual for 8251 8253 study card 41 35 54 20 44 TA BLE OUT INX DCR H B DAT51 JNZ STATUS ORG 9000H WELCOM TO ESA 8251 STUDY CARD K K K K K K K K K K K K K K K K K K K K K K Sample programs for MPS 85 3 and ESA 85 2 trainer2. 34 HAD User s Manual for 8251 8253 study card 74 08 12 11 Al 79 FF 7A FF DA FE D9 FA 80 D5 LH MOV A 08H 6 0 Demonstration programs for 8086 series kits EXAMPLE PROGRAMS FOR ESA 86 88 3 AND 86 88 2 TRAINERS LCALL 11AEH MOV R1 FFH X2 MOV R2 FFH X1 DJNZ R2 X1 DJNZ R1 X2 SJMP BACK 1 PROGRAM TO DISPLAY WELCOME TO ESA STUDY CARD FOR 9600 BAUD EXECUTE THE PROGRAM FROM 2000H ADDR 0000 3000 0000 3002 0000 3005 0000 3006 0000 3009 0000 300B 0000 300C 0000 300E 0000 300F 0000 3012 0000 3015 0000 3016 0000 3017 0000 3018 0000 3019 0000 301C 0000 30 1E 0000 30 1F 0000 3022 0000 3024 0000 3025 0000 3028 0000 302A 0000 302B 0000 302E 0000 3031 0000 3034 CONTROL REGISTER 8253 0080H DATA PORT 8251 0090H COMMAND PORT 8251 0092H OPCODE BO 36 BA 86 00 EE BA 80 00 BOOA EE BO 00 EE BC 00 30 BA 92 00 EE EE EE EE E8 2E 00 BO 40 EE E8 28 00 BO CE EE E8 22 00 BO 27 EE E8 1C 00 BE 00 31 BA 92 00 EC ORG 2000H MNEMONIC MOV AL 36 MOV DX 0086 OUT Dx AL MOV DX 0080 MOV AL OA OUT DX AL MOV AL 00 OUT DX AL MOV 5 3000 MOV DX 0092 OUT DX AL OUT DX AL OUT Dx AL OUT DX AL CALL 304A MOV ALAO OUT DX AL CALL 304A MOV AL CE OUT DX AL CALL 304A MOV ALJ27 OUT DX AL CALL 304A MOV SL3100 MOV DX 0092 IN AL DX COMMENTS Timer 0 in mode 3 Initialize
3. R A MOV DPTR 9000H MOV R1 00H MOV DPTR 0F191H MOVX A DPTR ANL A 81H A 01H STATUS POP DPL POP DPH A 00H MOVC LUMP PUSH DPH PUSH DPL A A DPTR A 00H CONT 0 MOV DPTR F190H MOVX DPTR A POP DPL POP DPH INC DPTR SJMP STATUS ORG 9000H D Initialize USART 8251 Get USART Status OAH OAH OAH OAH OAH 20H 20H 20H 20H 20H D Di D B B OAH OAH OAH B B 20H 20H 20H DB DEMO PROGRAM FOR 110 BAUD O DH 00H HAD User s Manual for 8251 8253 study card 30 EXAMPLE PROGRAMS FOR ESA 31 51 TRAINERS 4 Program to Display DEMO PROGRAM FOR ASYNCHRONOUS COMMUNICATION IN INTERRUPT MODE by using interrupt driven method Execute the Program at 8000H CONTROL REGISTER F183 DATA PORT F190 COMMAND PORT F191 ADDRESS OPCODE LABLE MNOMONIC COMMENTS ORG 8000H 8000 74 36 IOV A 36H 8002 90 F1 83 OV DPTR F183H TIMER 0 CMD 8005 FO OVX DPTR A 8006 90 Fl 80 OV DPTR F180H TIMER 0 DATA 8009 74 0 IOV 0AH 800B FO OVX DPTR A 800C 74 00 MOV A 400H 800E FO OVX DPTR A 800F 90 F1 91 OV DPTR F191H Initialize 8012 FO OVX QDPTR A USART 8013 FO OVX DPTR A 8
4. 0000 2064 Example 3 C3 RET This program initializes the 8253 timer in Mode 3 Square wave Generator and displays the count on the console Press RESET to exit from the program Execute this program from 0 2000H location in Serial Mode M53 TM2 TMO ODT Fi LH FI ADDRESS OP CODES LABELS 0000 2000 0000 2000 0000 2000 0000 2000 BO 76 0000 2002 BA C6 FF 0000 2005 EE 0000 2006 BO FF 0000 2008 BA C2 FF 0000 200B EF 0000 200C EE 0000 200D BO 96 0000 200F BA C6 FF 0000 2012 EE 0000 2013 BO FF 0000 2015 BA C4 FF 0000 2018 EE 0000 2019 9A 31 00 00 0000 201E BE 60 20 0000 2021 9A AF 01 00 0000 2026 BO 86 0000 2028 BA C6 FF 0000 202B EE 0000 202C BA C4 FF 0000 202F EC 0000 2030 3c 00 0000 2032 74 El 0000 2034 B4 00 0000 2036 9A 52 00 00 0000 203B BO 08 0000 203D 9A 00 00 00 0000 2042 9A 00 00 00 0000 2047 B9 00 04 0000 204A E2 FE 0000 204C EB D8 0000 2060 54 49 4D 45 52 MNEMONICS COMMENTS EQU OFFC6 EQU OFFC4 EQU OFFCO 1OVB AL 76 Initialize TIMER 1 MOVW DX M53 for Mode 3 operation OUTB DX AL OVB AL OFF OVW 1 Load TIMER 1 data OUTB DX
5. The output will go high on the terminal count If a new count value is loaded while the output is low it will not affect the duration of the one shot pulse until the succeeding trigger The current count can be read at any time without affecting the one shot pulse The one shot is retriggerable hence the output will remain low for the full count after any rising edge of the gate input MODE 2 Rate Generator Divide by N counter The output will be low for one period of the input clock The period from the output pulse to the next equals the number of input counts in the count register If the count register is reloaded between output pulses the present period will not be affected but the subsequent period will reflect the new value The gate input when low will force the output high When the gate input goes high the counter will start from the initial count Thus the gate input can be used to synchronize the counter When this mode is set the output will remain high until after the counter register is loaded The output then can also synchronized by software Mode 3 Square Wave Rate Generator Similar to MODE 2 except that the output will remain high until one half the count has been completed for even numbers and go low for the other half of the count This is accomplished by decrementing the counter by two on the falling edge of each clock pulse When the counter reaches terminal count the state of the output is changed and the c
6. OVR DLY NB AL DX ready ANDB 81 DSR active AL 81 No wait till it JNE STS becomes active MOVB AL ST If yes transmit INCW SI stored character CMPB AL 00 JE OVER MOVW DX V51 OUTB DX AL JMP STS INT 3 MOVW CX 2 LOOP 204E RET ORG 2100 Display look up table EMO PROGRAM FOR 110 BAUD ASC DI 47 Users Manual for 8251 8253 study card User s Manual for 8251 8253 study card 48
7. A DPTR F182H DPTR F183H MOV 00H 019 Latch CMD word LATCH COMMAND WORD Initialize Timer 1 and display the count on Data field of the Execute the program at 8000H The program is in continuous loop press RESET Key to come out of the loop 83 81 83 82 83 82 CONTROL REG STER DATA PORT COMMAND PORT LABLE ODT BACK MNOMONIC ORG 8000H MOV A 176H D JOVX td H FFH OVX OV A OV D IOVX MOV A FFH DPTI lt Q lt c rtJ 96 rJ OV A 86H MOV R F1 DPTR A TR F1 R DPTR H DPTR F1 IOVX DPTR A DPTR F1 OVX DPTR DPTR F182H LUE ER A A 183 190 191 TR F183H DPTR 82H 83H COMMENTS Timer 1 in mode 3 Timer I data Load mode word Data to counter 2 Latch CMD word ADDRESS OPCODE 8000 74 76 8002 90 F1 8005 FO 8006 74 FF 8008 90 F1 800B FO 800C FO 800D 74 96 800F 90 F1 8012 FO 8013 74 FF 8015 90 F1 8018 FO 8019 74 86 801B 90 F1 801E FO 801F 90 F1 Lan NULLI User s Manual for 8251 8253 study card 33 8022 EO IOVX A DPTR 8023 B4 00 02 A 00H NEXT 8026 80 ED SJMP ODT 8028 F5 60 NEXT MOV 71H A 802A 75 FO 00 MOV OFOH 00H 802D 12 01 9B LCALL 13D2H 80
8. CS P d Read Write Control c D hx Control Register WR q Logic RR 16 Bit RD RESET CLK INTERNAL DATA BUS Status Register RECEIVER FIGURE 2 The 8251A Expanded Block Diagram of Control Logic and Registers e WR Write When this signal goes low the MPU either writes in the control register or sends output to the data buffer This is connected to IOW or MEMW e RD Read When this signal goes low the MPU either reads a status register or accepts input data from the data buffer This is connected to either IOR or MEMR RESET Reset A high on this input resets the 8251 and forces it into the idle mode e CLK Clock This is the clock input usually connected to the system clock This clock does not control either the transmission or the reception rate The clock is necessary for communication with the microprocessor HAD User s Manual for 8251 8253 study card Control Register This 16 bit register for a control word consists of two independent bytes the first byte is called the mode instruction word and the second byte is called command instruction word This register can be accessed as an output port when the C D pin is high Status Register This input register checks the ready status of a peripheral This register is addressed as an input port when the C D pin is high it has the same port address as the control register Data Buffer This bi directional register c
9. This is an output signal It goes high when the USART has a character in the buffer register and is ready to transfer into the MPU This line can be used either to indicate the status or to interrupt the MPU HAD User s Manual for 8251 8253 study card INITIALIZING THE 8251A To implement serial communication the MPU must inform the 8251A of all details such as mode baud stop bits parity etc Therefore prior to data transfer a set of control words must be loaded into the 8 bit control register of the 8251A In addition the MPU must check the readiness of the peripheral by reading the status register The control words are divided into two formats mode words and command words The mode word specifies the general characteristics of operation such as baud parity number of stop bits the command word enable data transmission and or reception and the status word provides the information concerning register status and transmission errors Figure 4 shows the definition of these words To initialize the 8251A in the asynchronous mode a certain sequence of control words must be followed After a Reset operation system Reset or through instruction a mode word must be written in the control register followed by a command word Any control word written in the control register immediately after a word will be interpreted as a command word that means a command word can be changed any time during the operation However the 8251A should
10. 0 Read Load most significant byte only 0 1 Read Load least significant byte only 1 1 Read Load least significant byte first then most significant byte M_ MODE M2 MI 0 0 0 0 Mode 0 0 0 1 Mode 1 X 1 0 Mode 2 X 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 15 HAD User s Manual for 8251 8253 study card BCD Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades Counter Loading The count register is not loaded until the count value is written one or two bytes depending on the mode selected by the RL bits followed by a rising edge and a falling edge of the clock Any read of the counter prior to that falling clock edge may yield invalid data Mode Definition MODE 0 Interrupt on Terminal count The output will be initially low after the mode set operation After the count is loaded into the selected count register the output will remain low and the counter will count When the terminal count is reached the output will go high and remain high until the selected count register is reloaded with the mode or a new count is loaded The counter continues to decrement after terminal count has been reached Rewriting a counter register during counting result in the following 1 Write 1 byte stops the current counting 2 Write 2 byte start the new count MODE 1 Programmable One Shot The output will go low on the count following the rising edge of the gate input
11. 0A 0A DB 0A 0A DB 20 20 DB 20 20 DB 20 20 DB 20 20 ASC DEMO PROGRAM FOR ASYNCHRONOUS ASC COMMUNICATION IN INTERRUPT MODE OS k k k Me R kk k k AS ak k AS R R AS HS AS SEA R k ak ak ak K 3K SAS AS k ak AS aK K AS ACES AS US AS ACES AS K K AS k ak AS UIS GE CES SS GR 41 HAD User s Manual for 8251 8253 study card DEMONSTRATION EXAMPLES FOR 86E Trainer 8251 amp 8253 REGISTER ADDRESSES The addresses for the 8253 registers on this card for use with ESA 86 88E Trainer are follows Timer 0 FFCOH Timer 1 FFC2H Timer 2 FFC4H Command Register addresses for the 8251 registers this card for use with ESA 86 88E Trainer are follows Command Status Register FFCAH Data Register FFC8H Example 1 This program initializes the 8251 for 9600 baud and displays the message WELCOME TO ESA 8251 53 STUDY CARD on the console Enter and execute th program from 0 2000H location ADDRESS OP CODES LABELS MNEMONICS COMMENTS 0000 2000 M53 EQU OFFC6 0000 2000 EQU OFFCO 0000 2000 M5 EQU OFFCA 0000 2000 V5 EQU OFFC8 0000 2000 BO 36 OVB AL 36 Initialize TIMER 0 0000 2002 BA C6 FF IOVW DX M53 for Mode 3 operation 0000 2005 OUTB DX AL 0000 2006 BA CO FF MOVW DX TMO 0000 2009 BO 0A IOVB AL OA 0000 200B EE OUTB DX AL Lo
12. 0F191H IOVX DPT OVX DPT MOVX DPT IOVX DPT IOV A 40 OVX DPT OV 80H gy p FID d oZ A D me MOVX DPT OV A 01H OVX DPTR A DPTR 9000H R1 00H PUSH DPH S gt PUSH MOV MOVX DPL DPTR 0F191H A DPTR A 81H DPL DPH D HU C lt lt 2 rg tt rg Fl A 00H A A DPTR A 00H CONT 0 Q aquooc E 01 STATUS Program at 8000H COMMENTS TimerO for 9600 baud in mode3 USART Reset 8251 Get USART otatus L NULLI User s Manual for 8251 8253 study card 27 OO BBP UJ p DPTR 0F190H H OAH OAH OAH OAH DB OAH OAH OAH H 20H 20H 20H 20H H 20H 20H DB WELCOME TO ESA STUDY CARD ODH 00H CO 83 CONT PUSH DPH CO 82 PUSH DPL 90 1 90 MOV FO MOVX DPTR A DO 82 POP DPL DO 83 POP DPH A3 INC DPTR 80 D7 SJMP STATUS ORG 9000H OA OA OA OA OA TABLE DB OA OA OA OA 20 20 20 20 20 DB 20 20 20 20 DB 20 57 45 4C 43 4F 4D 45 20 5 F 20 45 53 41 20 53 54 55 59 20 43 41 52 44 OD 00 EXAMPLE PROGRAMS FOR ESA 31 51 TRAINERS 2 Program to receive characters from the USART and display it on Console as well as stored it in memory from 9000h The program is in a c
13. 2 Program to receive characters from the USART and display it on console as well as stored it in memory from 8500H The program is in a continuous loop Press ESC to come out of the loop CMD53 EQU 83H CMD51 EQU 91H DAT51 EQU 90H ADDRESS OPCODE LABLE MNEMONIC COMMENTS ORG 8000H 8000 11 0 00 LXI D 000AH TIMER 0 for 9600 BAUD 8003 36 MVI 36 TIMERO IN MODE 3 8005 D3 83 OUT CMD53 8007 7B MOV A E LOAD LSB VALUE 8008 D3 80 OUT 80H 800A 7A MOV A D LOAD MSB VALUE 800B D3 80 OUT 80H 800D AF XRA A DUMMY MODE 800E D3 91 OUT CMD51 WRITE DUMMY WORD 8010 D3 91 OUT CMD51 IN MODE REGISTER 8012 D3 91 OUT CMD51 8014 D3 91 OUT CMD51 23 HAD User s Manual for 8251 8253 study card gt gt 801E 8020 8022 8025 8028 8029 802B 8031 8032 8C33 8036 8037 gt uS BBW UJ o gt N P o p DJ E Co EH J CU C gt Ww Co tz 27 91 00 NU rH 37 J 11 36 42 25 O r 1 IJ r QO QO gt U gt Ed OQ O UO O ti 1 UJ xo J p 0 nj WON ens WO 85 80 80 60 80 80 80 DOWN RS ETCH IN CMD51 SOUTPT MVI A 40H OUT CMD51 M
14. Mhz clock is given to CLK1 JP4 1 2 is given to CLK2 2 3 CLK2 is derived externally JP5 OPEN CLKO is left unconnected CLOSED 1 5Mhz clock is given to CLKO JP6 OPEN RxD and TxD are not shorted CLOSED RxD and TxD are shorted JP7 OPEN CTS and RTS are not shorted CLOSED CTS and RTS are shorted JP8 OPEN 8251 chip select derived from decoder CLOSED 8251 chip select derived externally HAD User s Manual for 8251 8253 study card 3 0 INSTALLATION Please refer the below table for connection procedure for various trainer kits SI No Model No Studycard Connection Procedure Adapter 1 MPS 85 3 No Adapter Connect 26 pin FRC cables between J3 J4 of study card with J3 J4 of the trainer kit respectively 2 ESA 85 2 No Adapter Connect 50 pin FRC cable between of study card with P1 of the trainer kit 3 ESA 86 88 Study card adapter Connect 50 pin FRC cables between J1 J2 of the adapter 2 for ESA 86 2 3 with J1 J2 of the trainer kit trainer Connect 26 pin FRC cables between J3 J4 of the adapter with J3 J4 of the study card respectively 4 ESA 86 88 Study card adapter Connect 50 pin FRC cables between J1 J2 of the adapter 3 for ESA 86 2 3 with J1 J2 of the trainer kit trainer Connect 26 pin FRC cables between J3 J4 of the adapter with J3 J4 of the study card respectively 5 ESA 86E No Adapter Connect 26 pin FRC cables between J3 J4 of study card with 16 77 of
15. be sent to the same counter Read Operation Chart Al AO RD 0 0 0 Read Counter No 0 0 1 0 Read Counter No 1 1 0 0 Read Counter No 2 1 1 0 Illegal Reading While Counting The order for the programmer to read the contents of any counter without effecting or disturbing the counting operation the 8253 has special internal logic that can be accessed using simple WR commands to the MODE register Basically in the programmer wishes to read the contents of a selected counter on the fly he loads the MODE register with a special code which lathes MODE Register for Latching count 1 11 07 D5 D4 D3 D2 D1 DO 5 SCO 0 0 X X X X SCI SCO Specify counter to be latched D5 D4 D0 designates counter latching operation X don t care The same limitation applies to this mode of reading the counter as the previous method That is it is mandatory to complete the entire read operation as programmed This command has no effect on the counter s mode 21 HAD User s Manual for 8251 8253 study card 4 0 Demonstration programs for 8085 Series kits Sample programs for MPS 85 3 and ESA 85 2 trainer 1 Program to display WELCOME TO ESA 8251 STUDY CARD for 9600 baud by initializing 8251 Execute the program from 8000H
16. receives serial bits from a peripheral converts them into a parallel word and transfers it to MPU The 8251A is a complex device capable of performing various functions For the sake of clarity this chapter focuses only on the asynchronous mode of serial I O and excludes any discussion of the synchronous mode and the modem control The asynchronous mode is often used for the data communication between the MPU and serial peripherals such as terminals and floppy disks HAD User s Manual for 8251 8253 study card Figure 2 shows an expanded version of the 8251A block diagram The block diagram shows all the elements of a programmable chip It includes the interfacing signals the control register and the status register The functions of the various blocks are described below READ WRITE CONTROL LOGIC AND REGISTERS This section includes R W control logic six input signals control logic and three buffer registers data register control register and status register The input signals to the control logic are as follows Input signals CS chip select When this signal goes low the 8251A is selected by the MPU for communication This is usually connected to a decoded address bus C D control data when this signal is high the control register the status register is addressed The control register and the status register are differentiated by WR and RD signals respectively Buffer Register TRANSMITTER
17. selected The CS input has no effect upon the actual operation of the counters INTERNAL BUS CONTROL WORD REGISTE R COUNTER 0 COUNTER 1 COUNTER 2 GATEI CLK2 GATE2 OUT2 CS RD WR Al AO 0 1 0 0 0 Load Counter No 0 0 1 0 0 1 Load Counter No 1 0 1 0 1 0 Load Counter No 2 0 1 0 1 1 Write Mode Word 0 0 1 0 0 Read Counter No 0 0 0 1 0 1 Read Counter No 1 0 0 1 1 0 Read Counter No 2 0 0 1 1 1 No operation 3 state 1 X X X X Disable 3 state 0 1 1 X X No operation 3 state HAD User s Manual for 8251 8253 study card 13 Control Word Register The control word register is selected when 0 1 are 11 It then accepts information from the data bus buffer and stores it in a register The information stored in this register controls the operational MODE of each counter selection of binary or BCD counting and the loading of each count register The Control Word Register can only be written into no read operation of its contents is available Counter 0 counter 1 counter 2 These three function blacks are identical in operation so only a single counter will be described Each Counter consists of a single 16 pre settable DOWN counter The counter can operate in either binary or BCD and its input gate and output are configured by the selection of MODES stored in the Control Word Register The counters are f
18. signal is reset when a data byte is loaded into the buffer TxE Transmitter Empty This is an output signal Logic 1 on this indicates the output register is empty This signal is reset when a byte is transferred from the buffer to the output register HAD User s Manual for 8251 8253 study card Transmitt er Buffer Register Register Receiver Buffer register INTERNAL DATA BUS FIGURE 3 The 8251A Expanded Block Diagram of Transmitter and Receiver Section RECEIVER SECTION The receiver accept serial data on the RxD line from a peripheral and converts them into parallel data The section has two registers the receiver input register and the buffer register figure 3 When the RxD line goes low the control logic assumes it is a START bit waits for half a bit time and sample the line again If the line is still low the input register accepts the following bits form a character and load it into the buffer register Subsequently the parallel byte is transferred to the MPU when requested In the asynchronous mode two input signal and one output signal are necessary as described below RxD Receive Data Bits are received serially on this line and converted into a parallel byte in the receiver input register RxC Receiver clock This is a clock signal that controls the rate at which bits are received by the USART In the asynchronous mode the clock can be set to 1 16 or 64 times the baud RxRDY Receiver Ready
19. yes transmit Stored character Display msg TBL E TO ESA STUDY CARD Example 2 Program to receive characters from the USART and display it on the console as well as store it in memory location from Press Esc to stop receiving characters 0 2100H location onwards and exit from the loop ADDRESS 0000 0000 0000 0000 0000 0000 0000 2000 2000 2000 2000 2000 2002 2005 operation 0000 2006 0000 2009 OP CODES LABELS BO 36 BO OA BA 6 FF BA CO FF M53 TMO M5 MNEMONICS EQU EQU EQU V5 EQU OVB OUTB MOVW MOVB OVW OFFC6 OFFCO OFFCA OFFC8 AL 36 DX M53 DX AL DX TMO AL OA COMMENTS Initialize TIMER 0 for Mode 3 Load TIMER 0 count L NU Users Manual for 8251 8253 study card 43 0000 200 EE OUTB DX AL for 9600 baud 0000 200C BO 00 MOVB AL 00 0000 200 OUTB DX AL 0000 200F BC 00 30 5 3000 0000 2012 BA CA FF MOVW DX M51 Reset 8251 0000 20
20. 014 FO IOVX DPTR A 8015 FO OVX DPTR A 8016 74 40 OV A 40H 8018 FO IOVX DPTR A 8019 74 CE OV A CEH 801B FO OVX DPTR A 801C 74 27 OV A 27H 801E FO IOVX QDPTR A 801F 90 81 50 DPTR 8150H 8022 75 8 85 EN OV IE 85H Enable INT ORG FFF3H FFF3 02 90 00 LJMP STATUS ORG 9000H 9000 CO DO STATUS PUSH PSW 9002 74 00 BACK MOV A 400H 9004 93 MOVC A A DPTR 9005 B4 00 03 CJNE A 00H NEXT 9008 02 00 00 LUMP 0 900B CO 83 NEXT PUSH DPH 900D CO 82 PUSH DPL 900F 90 F1 92 MOV DPTR F192H 9012 FO MOVX DPTR A 9013 DO 82 POP DPL 9015 DO 83 POP DPH 31 User s Manual for 8251 8253 study card 9017 A3 9018 DO DO 901A 32 8150 OD OA OA OA OA 8155 OA OA OA OA 8159 20 20 20 20 20 815E 20 20 20 8161 5 4D 4F 20 8166 50 52 4F 47 52 816B 1 4D 20 46 4F 8170 52 20 41 53 59 8175 E 43 48 52 817A E 4F 55 53 20 817F 3 4 4D 4D 55 8184 49 43 41 5 189 9 4 4E 20 49 818 4 20 49 4E 5 8193 45 52 52 55 50 8196 54 20 AF 819D 45 819E OD 00 INC DPTR POP PSW RET ORG 8150H DB OD 0A 20 H OAH OAH OAH OAH OAH H OAH OAH H 20H 20H 20H 20H 20 B DB DB DB DB H 20H 20H D EMO PROGRAM FOR J EXAMPLE PROGRAM FOR ESA 31 TRAINER 5a Initialize Timer 1 and Display the count on Data field of the trainer Display
21. 1 31 30 20 42 41 55 44 00 DB 00 38 HAD User s Manual for 8251 8253 study card 4 PROGRAM TO INITIALIZE AND DISPLAY THE COUNT ON THE SERIAL MODE EXECUTE THE PROGRAM FROM 2000H THE PROGRAM IS IN CONTINUOUS LOOP PRESS RESET KEY TO COME OUT OF THE LOOP CONTROL REGISTER 8253 0080H DATA PORT 82153 0090H COMMAND PORT 8251 0092H ORG 2000H ADDR OPCODE MNEMONIC COMMENTS 0000 2000 BO 76 MOV AL 76 Timer 1 CMD 0000 2002 BA 86 00 MOV DX 0086 0000 2005 EE OUT DX AL 0000 2006 B0 FF MOV AL FF 0000 2008 BA 82 00 MOV DX 0082 Timer 1 DATA 0000 200B EE OUT DX AL 0000 200C EE OUT DX AL 0000 200D BO 96 MOV AL 96 Timer 2 CMD 0000 200F BA 86 00 MOV DX 0086 0000 2012 EE OUT DX AL 0000 2013 B0 FF MOV AL FF 0000 2015 BA 84 00 ODT MOV DX 0084 Latch command word 0000 2018 EE OUT DX AL 0000 2019 B8 0021 MOV 2100 0000 201C 9A 31 00 00 FB CALLS FB00 0031 0000 2021 9A 13 00 00 FB CALLS FB00 0013 0000 2026 BO 86 BACK MOV AL 86 0000 2028 BA 86 00 MOV DX 0086 0000 202B EE OUT DX AL 0000 202C BA 84 00 MOV DX 0084 0000 202F EC IN AL DX 0000 2030 3C 00 AL 00 0000 2032 74 El JE ODT 0000 2034 B4 00 MOV 00 0000 2036 9A 52 00 00 FB CALLS FB00 0052 0000 203B B9 FF FF MOV CX FFFF 0000 203E E2 FE LOOP 203E 0000 2040 BO 08 MOV AL 08 0000 2042 9A 00 00 00 FB CALLS FB00 0000 0000 2047 9A 00 00 00 FB CALLS FB00 0000 0000 204C E9 D7 FF JMP BACK 0000 2100 ORG 2100 0000 2100 43 4F 55 4E 54 20 ASC COUNT VALUE 0000 2106 5
22. 13 D3 82 8015 3E 86 8017 D3 83 8019 DB 82 801B 32 801E FE 80 8020 CA 3F 8023 06 00 8025 CD 4C 8028 CD 2E 802B O35 802E 16 FF 8030 1E 33 8032 1D 8033 00 8034 00 8035 00 8036 00 8037 C2 32 803A 15 803B C2 30 803E C9 803F 3E 70 8041 C313 Sample programs for MPS 85 3 and ESA 85 2 trainer DAT51 FF 8F 80 04 80 80 80 80 LABLE ODT DLY 1 LP NDT ORG LX1 O G O c lt lt H lt Hi Hi C 3 uc OUT IN 82H EQU 90H MNEMONIC 8000H H OFFFFH 96H MD53 OFFH 82H I 86 CMD53 STA 8FF1H CPI 80H NDT MV B OOH CALL 044C CALL DLY JMP IVI ODT 2 D OFFH F 33H NOP NOP NOP NOP JNZ NZ ET 20 DCR 1 y D LP 70 ODT COMMENTS TIAL SE 1 JES MS 7 LO R LH B OF T MER 1 B D OF T MER 2 E MOD E WORD LATCH COMMAND WORD 4 Program to display DEMO PROGRAM FOR AYSNCHRONOUS COMMUNICATION IN INTERRUPT MODE by using interrupt driven Execute the program from 8000H ADDRESS OPCODE 8000 11 0A 8003 3E 36 00 LABLE MNOMONIC ORG LXI MVI 8000H D 000AH A 36H COMMENTS TIME
23. 15 OUTB DX AL 0000 2016 OUTB DX AL 0000 2017 OUTB DX AL 0000 2018 OUTB DX AL 0000 2019 E 43 00 CALL DLY 0000 201C BO 40 MOVB AL 40 Initialize 8251 for asynchronous 0000 201E EE OUTB DX AL 16x baud 8 data 0000 201 E8 00 CALL DLY bits no parity 0000 2022 BO CE MOVB AL 0000 2024 EE OUTB DX AL 0000 2025 E8 37 00 CALL DLY 0000 2028 B0 27 MOVB AL 27 0000 202A EE OUTB DX AL 0000 202B E8 31 00 CALL DLY 0000 202E BE 00 21 MOVW SI 2100 P Initialize Memory to 0000 2031 BA CA FF GCH MOVW DX M51 store character 0000 2034 EC NB AL DX Get USART status 0000 2035 24 02 ANDB AL 02 Receiver ready 0000 2037 74 F8 JZ GCH wait 0000 2039 BA C8 FF MOVW DX V51 Yes Get Character 0000 203C EC NB AL DX from USART 0000 203D 3C 1B CMPB AL 27 If char Esc 0000 203F 8A D8 MOVB BL AL PExit 0000 2041 7 B JE OVR 0000 2043 BA CA FF OPT MOVW DX M51 0000 2046 EC NB AL DX Get USART status 0000 2047 24 8 ANDB AL 8 Transmitter Ready 0000 2049 3C 8 CMPB AL 81 0000 204B 75 R6 JNE OPT No Wait 0000 204D 8A C3 MOVB AL BL Send same character 0000 204F BA C8 FF MOVW DX V51 to USART 0000 2052 EE OUTB DX AL 0000 2053 88 04 MOVB SI AL 0000 2055 46 INCW SI 0000 2056 E9 D8 FF JMP 0000 2059 EE OUTB DX AL 0000 205A 46 INCW SI 0000 205B E9 E5 FE JMP OPT 0000 205E CC OVR TINTS 23 0000 205F 9 02 00 DLY MOVW CX 2 0000 2062 E2 FE LOOP 2062 44 HAD User s Manual for 8251 8253 study card
24. 30 79 FF MOV R1 FFH 8032 7A FF X2 MOV R2 FFH 8034 DA FE XI DJN2 R2 X1 8036 D9 FA DJNZ R1 X2 8038 80 DF SJMP BACK KKKKKKKKKKKKK ck k k ck lt ck ck k k lt lt ck ck k k ck lt ck ck k k ck ck ck ck k ck ck ck ck ck k k ck ck ck ck k k ck ck k k k k ck k k k kk EXAMPLE PROGRAM FORS51E TRAINER 5c Initialize Timer 1 and display the count on the console Execute The program at 8000H The program is in continuous loop Press RESET Key to come out of the loop CONTROL REGISTER F183H DATA PORT F190H COMMAND PORT F191H ADDRESS OPCODE LABLE MNOMONIC COMMENTS ORG 8000H 8000 74 76 MOV A 76H Timer 1 in mode 3 8002 90 F1 83 OV DPTR F183H 8005 FO MOVX DPTR A 8006 74 FF MOV A FFH 8008 90 81 MOV DPTR F181H Timer 1 data 800B FO MOVX DPTR A 800C FO MOVX DPTR A 800D 74 96 MOV A 96H Load mode word 800F 90 1 83 MOV DPTR F183H 8012 FO OVX DPTR A 8013 74 FF OV A FFH Data to counter 2 8015 90 1 82 ODT MOV DPTR F182H Latch CMD word 8018 FO MOVX DPTR A 8019 74 86 BACK MOV A 86H 801B 90 F1 83 MOV DPTR F183H 801 FO DPTR A 801F 90 F1 82 MOV DPTR F182H 8022 FO OVX A DPTR 8023 B4 00 02 A 00H NEXT 8026 80 ED SJMP ODT 8028 5 71 NEXT MOV 71H A 802A 75 FO 00 MOV OFOH 00H 802D 12 13 9 LCALL 139 8030 74 08 MOV 08 8032 12 11 LCALL 11
25. 6 41 4C 55 45 3A 0000 210C 20 HAD User s Manual for 8251 8253 study card 39 0000 210D 00 DB 00 5 PROGRAM TO DISPLAY DEMO PROGRAM FOR ASYNCHRONOUS COMMUNICATION IN INTERRUPT MODE BY USING INTERRUPT METHOD EXECUTE PROGRAM FROM 2000H ADDR 0000 2000 0000 2003 0000 2005 0000 2007 0000 200A 0000 200D 0000 200E 0000 2014 0000 2015 0000 201B 0000 201E 0000 2020 0000 2021 0000 2024 0000 2026 0000 2027 0000 2029 0000 202A 0000 202C 0000 202D 0000 202E 0000 2030 0000 2033 0000 2034 0000 2037 0000 2039 0000 203A 0000 203C 0000 203D 0000 2040 0000 2041 0000 2042 0000 2043 0000 2044 0000 2047 0000 2049 0000 204A CONTROL REGISTER 8253 0080H DATA PORT 8251 0090H COMMAND PORT 8251 0092H ORG OPCODE B8 00 00 8E C8 8E CO BC 00 30 BE 50 21 26 C7 06 24 01 00 21 26 C7 06 26 01 00 00 BA F4 FF BO 13 EE BA F6 FF BO 48 EE BO 03 EE BO FD EE FB BO 36 BA 86 00 EE BA 80 00 BOOA EE E8 1D 00 BO 40 EE 8 17 00 2000 MNEMONIC COMMENTS INIT MOV 0000 Timer 0 in mode MOV 5 ES AX MOV SP 3000 MOV 51 2150 ES MOVW 0124 2100 ES MOVW 0126 0000 MOV DX FFF4 MOV AL 13 OUT DX AL MOV DX FFF6 MOV ALAS OUT DX AL MOV AL 03 OUT DX AL MOV AL FD OUT DX AL STI MOV AL 36 MOV DX 0086 Timer 0 cmd OUT DX AL MOV DX 0080 Timer 0 data MOV 0 OUT DX AL MOV AL 00 OUT DX AL MOV DX 0092 Initialization USAR
26. 8251 AND 8253 PROGRAMMABLE COMMUNICATION INTERFACE AND PROGRAMMABLE INTERVAL TIMER 1 INTRODUCTION Electro System Associates Private Limited ESA manufactures trainers for most of the popular microprocessors like 8085 Z 80 8031 8086 88 68000 and 80196 ESA offers a variety of modules which can be interfaced to these trainers These modules can be effectively used for teaching training in the laboratories The 8251 and 8253 study card incorporates Intel s 8251 and 8253 The interface is designed to explain all the facilities available in 8251 and 8253 Functional description of 8251 and 8253 implementation of the circuit and some simple software are presented in this manual 2 DESCRIPTION OF THE CIRCUIT The study card provides 8251 as well as timer section The interface has got 4 connectors J3 J4 and P1 used for various trainer kits J2 10 pin FRC right angle male connector is used for connecting RS232C cable to the COM port of the system 10 RED LEDs are provided to indicate the important signals 6 144MHz crystal is provided to drive 1 5 MHz clock The following table describes the various hardware configurations for 8251 and 8253 using jumper settings Jumper Position Description 1 2 is connected externally 2 3 is connected to VCC JP2 1 2 GATE2 is connected externally 2 3 GATE2 is connected to VCC JP3 1 2 CLK1 is derived externally 2 3 1 5
27. 8253 study card ADDR 0000 2000 0000 2002 0000 2005 0000 2006 0000 2009 0000 200C 0000 200D 0000 200F 0000 2010 0000 2012 0000 2015 0000 2016 0000 2017 0000 2018 0000 2019 0000 201B 0000 201C 0000 201E 0000 201F 0000 2021 0000 2022 0000 2025 0000 2028 0000 2029 0000 202B 0000 202D 0000 202F 0000 2031 0000 2033 0000 2035 0000 2038 0000 2039 0000 203A 0000 203C 0000 2100 0000 2100 0000 2102 0000 2104 0000 2106 0000 2108 0000 210A 0000 210C 0000 210E 0000 2110 0000 2116 0000 21 1C 0000 2122 0000 2128 0000 2129 ORG 2000H OPCODE MNEMONIC COMMENTS BO 36 MOV AL 36 BA 86 00 MOV DX 0086 TimerO in mode 3 EE OUT DX AL BA 80 00 MOV DX 0080 B8 69 03 MOV AX 0369 EE OUT DX AL 8A C4 MOV AL AH EE OUT DX AL BO 00 MOV 00 BA 92 00 MOV Dx 0092 Initialization USART EE OUT DX AL EE OUT DX AL EE OUT DX AL EE OUT DX AL BO 40 MOV AL 40 Reset 8251 EE OUT DX AL BO CE AL CE EE OUT DX AL B027 MOV AL 27 EE OUT DX AL BE 0021 MOV SL2100 BA 92 00 STATUS MOV DX 0092 Get USART status EC IN AL DX 24 81 AND AL 81 3C 81 AL 81 75 F6 JNE 2025 8A 04 MOV ALJSI 3C 00 AL 00 74 08 203D 90 00 MOV Dx 0090 EE OUT DX AL 46 INC SI EB E9 JMP 2025 CC OVER INT 03 ORG 2100 0A 0A DB 0A 0A 0A 0A DB 0A 0A 0A 0A DB 0A 0A 0A 0A DB 0A 0A 20 20 DB 20 20 20 20 DB 20 20 20 20 DB 20 20 20 20 DB 20 20 44 45 4D 4F 20 50 ASC DEMO PROGRAM FOR 110 BAUD 52 4F 47 52 41 4D 20 46 AF 52 203
28. 900A 50 52 4F 47 52 ASYNCHRONOUS 900F 1 4D 20 46 4F COMMUNICATION IN 9014 52 20 41 53 59 NTERUPT MODE 9019 E 43 48 52 4F 901E 4F 55 53 20 9023 3 AF 4D 55 9028 E 49 43 41 5 902D 9 4F 4E 20 49 9032 4E 20 49 4E 5 9037 45 52 52 55 50 26 HAD User s Manual for 8251 8253 study card 903C 54 20 4D 4F 44 9041 45 2E OA 00 8FB3 C3 32 80 ORG 8FB3H JMP STATUS KKKKKKKKKKKKKKK KK lt ck ck ck k ck lt ck ck k k ck ck ck ck ck k ck ck ck ck k k ck ck ck ck ck k ck ck ck ck ck ck lt ck ck ck ck ck lt k X KKK 5 0 Demonstration programs for 8051 Series kits EXAMPLE PROGRAMS FOR ESA 31 51 TRAINERS l Program to display WELCOME TO ESA 8251 STUDY CARD for 9600 baud by initializing 8251 Execute the ADDRESS OPCODE 8000 74 36 8002 90 F1 83 8005 FO 8006 90 F1 80 8009 74 0A 800B FO 800C 74 00 800E FO 800F 90 F1 91 8012 FO 8013 FO 8014 FO 8015 FO 8016 74 40 8018 FO 8019 74 CE 801B FO 801C 74 01 801E FO 801F 90 90 00 8022 79 00 8024 CO 83 8026 CO 82 8028 90 F1 91 802 0 802 54 81 802 DO 82 8030 DO 83 8032 4 01 8035 74 00 8037 93 8038 B4 00 03 803B 02 00 00 CONTROL R EG STER F183 DATA PORT F190 COMMAND PORT F191 LABLE STATUS MNEMONIC ORG 8000H OV A 36H MOV DPTR 0F183H OVX DPTR A DPTR 0F1 IOV A OAH OVX DPTR A MOV A 00H MOVX DPTR A IOV DPTR
29. AL LSB first OUTB DX AL Load MSB MOVB AL 96 P Initialize TIMER 2 MOVW DX M53 OUTB DX AL MOVB AL OFF MOVW TM2 Load TIMER 2 Data OUTB DX AL CALLS OFE00 0031 Display message 51 2060 Timer Count CALLS OFE00 01AF on console MOVB AL 86 MOVW DX M53 Latch Command Word OUTB DX AL OVW DX TM2 Read count NB AL DX CMPB AL 00 JE ODT OVB AH 00 CALLS O0FE00 0052 Display count value MOVB AL 08 on console CALLS 0 00 0000 CALLS 0 00 0000 MOVW CX 0400 LOOP 204A JMP BCK Repeat continuously ORG 2060 User s Manual for 8251 8253 study card 45 0000 2065 20 43 4F 55 4E 0000 206A 54 20 00 ASC TIMER COUNT DB 00 Example 4 This program initializes the 8251 for 110 baud and displays the following message on the console Enter and execute the program from 0 2000H location ESA 8251 53 STUDY CARD DEMONSTRATION PROGRAM FOR 110 BAUD Note Set receiving terminal to receive data at 110 baud ADDRESS OP CODES LABELS MNEMONICS COMMENTS 0000 2000 M53 EQU OFFC6 0000 2000 EQU OFFCO 0000 2000 M5 EQU OFFCA 0000 2000 V5 EQU OFFC8 0000 2000 BO 36 MOVB AL 36 0000 2002 BA C6 FF OVW DX M53 Initializ
30. Execute the Program at 8000H The program is in a continuous Loop press RESET key to come COMMUN ASYNCHRONOUS CATION MODE NT B ODH 00H out of the loop CONTROL REGISTER F183 DATA PORT F190 COMMAND PORT F191 ADDRESS OPCODE LABLE MNEMONIC COMMENTS ORG 8000K 8000 74 76 A 76H TIMER1 mode3 8002 90 Fl 83 OV DPTR F183H 8005 FO IOVX DPTR A 8006 74 FF IOV A FFH 8008 90 F1 81 OV DPTR F181H TIMER 1 DATA 800B FO MOVX DPTR A 800C FO IOVX DPTR A 800D 74 96 A 96H Load mode word 800F 90 Fl 83 OV DPTR F183H 8012 FO AOVX DPTR A 8013 74 FF MOV A FFH Data to counter2 User s Manual for 8251 8253 study card 32 8015 90 8018 FO 8019 74 801B 90 801E FO 801F 90 8022 0 8023 B4 8026 80 8028 5 802 75 802D 12 8030 79 8032 7A 8034 DA 8036 D9 8038 80 Fl 86 Fl 00 ED 60 FO 01 EE FE FA DF 82 83 1 82 02 ODT BACK NEXT EXAMPLE PROGRAM FOR51E TRAINER 5b trainer display A 86 IOV MOVX MOV IOVX A CJNE SJMP ODT IOV 60H A LCALL DJUNZ DJUNZ SJMP R2 X1 R1 X2 BACK OVX DPTR A H DPTR DPTR F182H DPTR A 00H NEXT R1 FFH R2 FFH
31. R O for 9600 baud TIMER 0 IN HAD User s Manual for 8251 8253 study card 25 MODE 3 8005 D3 83 OUT CMD53 8007 7B MOV A E LOAD LSB VALUE 8008 D3 80 OUT 80H 800A 7A MOV A D LOAD MSB VALUE 800B D3 80 OUT 80H 800D AF XRA A DUMMY MODE 800E D3 91 OUT CMD5 WRITE DUMMY WORD 8010 D3 91 OUT CMD51 IN MODE REGISTER 8012 D3 91 OUT CMD51 8014 D3 91 OUT CMD51 8016 3E 40 MVI A 40H RESET 8251 8018 D3 91 OUT CMD51 801A 3E CE MVI 0 SET 8251 FOR 801C D3 91 OUT CMD51 ASYNCHRONOUS 16XBAUD 2 STOP BITS 8 DATA BITS NO PARITY 801 27 MVI A 27H WRITE COMMAND WORD 8020 D3 91 OUT CMD51 8022 21 00 90 LXI H 9000H MEMORY TO STORE THE 8025 06 45 MVI B 45H CHARACTER 8027 3E OE MVI A 0EH ENABLE RST 5 5 8029 30 SIM 802A FB E 802B 78 LOOP MOV A B 802C 6 00 ORI 0 802 C2 2B 80 JNZ LOOP 8031 EF RST 5 8032 F5 STATUS PUSH PSW 8033 7E MOV A M 8034 D3 90 OUT DAT51 8036 23 INX H 8037 05 DCR B 8038 F1 POP PSW 8039 FB E 803A C9 RET 9000 OA OA 20 20 20 TABLE ORG 9000H 9005 4 45 4D 4F 20 DEMO PROGRAM FOR
32. RIPTION General The complete functional definition of the 8253 is programmed by the systems software A set of control words must be sent out by the CPU to initialize each counter of the 8253 with the desired MODE and quantity information Prior to initialize the MODE count and output of all counters is undefined These control words program the MODE Loading sequence and selection of binary or BCD counting Once programmed the 8253 is ready to perform whatever timing tasks it is assigned to accomplish The actual counting operation of each counter is completely independent and additional logic is provided on chip so that the usual problems associated with efficient monitoring and management of external asynchronous events or rates to the microcomputer system have been eliminated Programming the 8253 All of the MODES for each counter are programmed by the system software by simple I O operations Each counter of the 8253 is individually programmed by writing a control word in to the control word register AO 1 11 Control Word Format D7 D6 D5 D4 D3 D2 DI DO SCI SCO RLO M2 0 BCD Definition of Control SC Select Counter SCI SCO 0 0 Select Counter 0 0 1 Select Counter 1 1 0 Select Counter 2 1 1 Illegal RL Read Load RLO 0 0 Counter latching operation see READ WRITE procedure section 1
33. T OUT DX AL OUT DX AL 36 HAD User s Manual for 8251 8253 study card 0000 2017 EE OUT Dx AL 0000 2018 EE OUT DX AL 0000 2019 E8 43 00 CALL 205F 0000 201C BO 40 MOV AL 40 Reset 8251 0000 201E EE OUT DX AL 0000 201F E8 3D 00 CALL 205F 0000 2022 BO CE MOV AL CE 0000 2024 EE OUT DX AL 0000 2025 E8 37 00 CALL 205F 0000 2028 BO 27 MOV AL 27 0000 202A EE OUT DX AL 0000 202B E8 31 00 CALL 205F 0000 202E BE 00 21 MOV 9L2100 0000 2031 92 00 MOV DX 0092 0000 2034 EC IN AL DX Get USART status 0000 2035 24 02 AND AL 02 Receiver Ready 0000 2037 74 F8 JE 2031 0000 2039 BA 90 00 MOV DX 0090 Get character from 0000 203C EC IN AL DX USART 0000 203D 3C 1B AL 1B 0000 203F 8A D8 MOV BL AL 0000 2041 74 1B JE 205E 0000 2043 BA 92 00 MOV DX 0092 0000 2046 EC IN AL DX 0000 2047 24 81 AND AL 81 0000 2049 81 AL 81 0000 204B 75 F6 JNE 2043 0000 204D 8A C3 MOV AL BL 0000 204F BA 90 00 MOV DX 0090 0000 2052 EE OUT DX AL 0000 2052 EE OUT DX AL 0000 2053 88 04 MOV SI AL 0000 2055 46 INC SI 0000 2056 E9 D8 FF JMP 2031 0000 2059 EE OUT DX AL 0000 205A 46 INC SI 0000 205B E9 E5 FF JMP 2043 0000 205E CC INT 03 0000 205F B9 02 00 MOV CX 0002 0000 2062 E2 FE LOOP 2062 0000 2064 C3 RET 3 PROGRAM TO DISPLAY DEMO PROGRAM FOR 110 BAUD EXECUTE PROGRAM FROM 2000H CONTROL REGISTER 8253 0080H DATA PORT 8253 0090H COMMAND PORT 8253 0092H 37 HAD User s Manual for 8251
34. T OUT DX AL OUT DX AL OUT DX AL OUT DX AL CALL 2064 MOV AL 40 Reset 8251 OUT DX AL CALL 2064 40 HAD User s Manual for 8251 8253 study card 0000 204D 0000 204F 0000 2050 0000 2053 0000 2055 0000 2056 0000 2058 0000 205A 0000 205C 0000 205F 0000 2060 0000 2061 0000 2062 0000 2063 0000 2064 0000 2067 0000 2069 0000 2100 0000 2100 0000 2101 0000 2103 0000 2104 0000 2107 0000 2108 0000 2109 0000 210A 0000 2150 0000 2150 0000 2152 0000 2154 0000 2156 0000 2158 0000 215A 0000 215C 0000 215E 0000 2160 0000 2166 0000 216C 0000 2172 0000 2178 0000 217E 0000 2184 0000 218A 0000 2190 0000 2196 0000 219C 0000 219D CE EE E8 11 00 BO 27 EE 8A 04 3C 00 75 FA BA 92 00 EE EE EE EE CC B9 02 00 E2 FE C3 9C 8A 04 46 BA 90 00 EE 9D FB CF OD 0A 0A 0A 0A 0A 0A 0A 20 20 20 20 20 20 20 20 44 45 4D 4F 20 50 52 AF 47 52 41 4D 20 46 4F 52 2041 53 59 4E 43 48 52 4E 4F 55 53 20 43 4A 4D 4D 55 4E 49 43 41 54 49 4F 4E 20 49 4E 20 49 4E 54 45 52 52 55 50 54 20 4D 4F 44 45 00 DB 00 BACK DLY STATUS OVER MOV AL CE OUT Dx AL CALL 2064 MOV AL 27 OUT DX AL MOV AL SI AL 00 JNE BACK MOV DX 0092 Get USART status OUT DX AL OUT DX AL OUT DX AL OUT DX AL INT 03 MOV CX 0002 LOOP 2067 RET ORG 2100 PUSHF MOV AL SI INC SI MOV DX 0090 OUT DX AL POPF STI IRET ORG 2150 DB 0D 0A DB 0A 0A DB
35. USART Reset 8251 USART status HAD User s Manual for 8251 8253 study card 35 0000 3035 0000 3037 0000 3039 0000 303B 0000 303D 0000 303E 0000 3040 0000 3042 0000 3045 0000 3046 0000 3049 0000 2100 0000 2102 0000 2104 0000 2106 0000 2108 0000 210A 0000 210C 0000 210E 0000 2110 0000 2116 0000 211C 0000 2122 0000 2128 24 81 3C 81 75 F6 8A 04 46 3C 00 74 07 BA 90 00 EE E9 E8 FF CC 0A 0A 0A 0A 0A 0A 0A 0A 20 20 20 20 20 20 20 20 57 45 4C 43 AF 4D 45 20 54 4F 20 45 53 41 20 53 54 55 44 59 20 43 41 52 44 00 AND AL 81 ALI JNE 3031 MOV ALJSI INC SI CMP AL 00 JE 3049 MOV DX 0090 OUT DX AL JMP 3031 INT 03 ORG 2100H DB 0A 0A DB 0A 0A DB 0A 0A DB 0A 0A DB 20 20 DB 20 20 DB 20 20 DB 20 20 ASC WELCOME TO ESA STUDY CARD 2 PROGRAM TO RECEIVE CHARACTERS FROM THE USART AND DISPLAY IT ON CONSOLE PROGRAM EXECUTED FROM 2000H ADDR 0000 2000 0000 2002 0000 2005 0000 2006 0000 2009 0000 200B 0000 200C 0000 200E 0000 200F 0000 2012 0000 2015 0000 2016 CONTROL REGISTER 8253 0080H DATA PORT 8251 0090H COMMAND PORT 8251 0092H ORG OPCODE B0 36 BA 86 00 EE BA 80 00 B00A EE BO 00 EE BC 00 30 BA 92 00 EE EE 2000H MNEMONIC COMMENTS MOV AL 36 MOV DX 0086 Timer 0 in mode 0 OUT DX AL MOV DX 0080 MOV AL 0A Timer 0 DATA OUT DX AL MOV AL 00 OUT DX AL MOV SP 3000 MOV DX 0092 Initialize USAR
36. UTPT LJMP 3 2 OV DPTR OF191H OVX A DPTR Get USART Status ANL A 01H Receiver ready CJNE A 01H STATUS MOV 0 OV DPTR 0F190H OVX DPTR A POP DPL POP DPH OVX DPTR A INC DPTR SJMP GETCH EXAMPLE PROGRAMS FOR ESA 31 51 TRAINERS 3 Program to Display DEMO PROGRAM FOR 110 BAUD Execute the Program at 8000H ADDRESS 8000 8002 8005 OPCODE 74 36 90 F1 FO 83 CONTROL DATA PORT COMMAN LABLE REGISTER F183 190 Il nj D PORT F191 MNEMONIC COMMENTS ORG 8000H MOV 36H MOV DPTR 0F183H MOVX DPTR A Timer 0 in mode 3 29 HAD User s Manual for 8251 8253 study card 8006 8009 800B 800C 800F OO FJ O1 gt WN 9029 F1 69 03 F1 80 91 00 91 D7 OA OA 20 OA OA 20 OA 20 STATUS CONT 20 20 B 50 1 5 52 20 OD 2 nj w N ONOUN 0 7 6 1 31 55 TA BLE F MOV A 69 MOVX DPT MOV A 03 MOVX QDPTI MOVX MOVX MOVX MOVX A 40 MOVX QDPTi MOV A 0 OVX QDPTI MOV A 01 DPT DPT DPT DPT on MOV DPTR 0F180H H R A H R A MOV DPTR 0F191H gs ps m D BAMA d 2 OG A 2 4 D MOVX DPT PUSH DPH PUSH DPL
37. VI A OCEH OUT CMD51 MVI A 27H OUT CMD51 LXI H 8500H BACK CALL GETCH MOV A C CRI 27 JZ DOWN CALL SOUTPT MOV M C INX H JMP BACK LOH D O g z z z O ZN in H lt 02H GETCH DAT51 V C A C J Z SOUTPT A C T 51 T Doe om c PR 9 ES ET 825 8251 FOR ASYNCHRONOUS 16XBAUD 2 STOP BITS DATA B T TW r L 5 PARI R TE COMMAN p D Hj m odit ORD ORY TO ST ARACTER TO ORY USART EIVER REA CHARACTI 1 USART LH 8 TY D ORI LH DY KKKKKKKKKKKKK ck k k ck ck ck ck k k ck ck ck ck k k ck lt ck ck k k ck lt ck ck ck k ck ck ck ck ck k ck ck ck ck k k ck ck ck ck ck k lt lt X kk Sample programs for MPS 85 3 and ESA 85 2 trainer 3 Initialize Timer 1 and display the count on Data field of the trainer display Execute the program from 8000H The program is in a continuous loop press RESET key to come out of the loop CM CM D53 D51 EQU 83H EQU 91H User s Manual for 8251 8253 study card 24 ADDRESS OPCODE 8000 2L EE 8003 3E 76 8005 D3 83 8007 7D 8008 D3 81 800A 7C 800B D3 81 800D 3E 96 800F D3 83 8011 3E FF 80
38. ad TIMER O0 count 0000 200C BO 00 MOVB AL 00 for 9600 baud 0000 200E EE OUTB DX AL 0000 200F BC 00 30 OVW SP 3000 0000 2012 BA CA FF OVW DX M51 0000 2015 EE OUTB DX AL Reset 8251 0000 2016 EE OUTB DX AL 0000 2017 EE OUTB DX AL 0000 2018 EE OUTB DX AL 0000 2019 E8 2E 00 CALL DLY HAD User s Manual for 8251 8253 study card 42 201 0 40 201 EE 201F E8 28 00 2022 BO CE 2024 EE 2025 E8 22 00 2028 BO 27 202A EE 202 8 1 00 202 00 21 2031 FF 2034 2035 24 8 22037 3C 81 22039 75 F6 203B 8A 04 203D 46 203E 3c 00 2040 74 07 2042 BA C8 FF 2045 EE 2046 E9 E8 FE 2049 GE 204A 9 02 00 204D E2 FE 204F G3 2100 OD OA 20 20 2106 4C 43 4F 4D 210C 54 4F 20 45 2412 20 53 54 55 2118 20 43 41 52 STS OVR ASC WEL 00 lt lt Ww L H L 00 D gt lt QOxoo H lt ww gt lt set UJ lt O O va COE t Dagan PONOOBOOROD lt O YQ lt s UJ Ot lt Z OZ lt CO mee ot Initialize 8251 for asynchronous 16x baud 8 data bits no parity Get USART status for Transmitter ready amp DSR active If
39. an be addressed as an input port and output port when the C D pin is low Table 1 summarizes all the interfacing and control signals CS C D RD WR Function 0 1 1 0 MPU writes instructions in the control register 0 1 0 1 MPU reads status from the status register 0 0 1 0 MPU outputs data to the Data Buffer 0 0 0 0 MPU accepts data from the Data Buffer 1 X X X USART is not selected TRANSMITTER SECTION The transmitter accepts parallel data from the MPU and converts them into serial data It has two registers a buffer register to hold eight bits and an output register to convert eight bits into steam of serial bits figure 3 the MPU writes a byte in the buffer register whenever the output register is empty the contents of the buffer register are transferred to the output register This section transmits data on TxD pin with the appropriate framing bits START and STOP Three output signals and one input signal are associated with the transmitter section TxD Transmit Data Serial bits are transmitted on this line TxC Transmitter Clock This input signal controls the rate at which the bits are transmitted by the USART The clock frequency can be 1 16 or 64 times the baud TxRDY transmitter Ready This is the output signal When it is high it indicates the buffer register is empty and USART is ready to accept a byte It can be used either to interrupt the MPU or to indicate the status This
40. be reset prior to writing a new mode word and it can be reset by using the Internal Reset bit D6 in the command word HAD User s Manual for 8251 8253 study card 00 SYN Mode 01 ASYN X 1 10 ASYN X 16 11 ASYN X 64 Character length 0 No parity 01 Odd parity 11 Even parity 00 Not Valid 01 1 stop bit 10 1 stop bit ASYN D1D0 X 11 2 stop Bits D Ds Ds Ds D D D Do Transmit Enable 1 enable 0 Disable Bits for Sync format Receive enable 1 enable Error Reset 0 Disable 1 Reset All Error Internal reset flags 1 resets 8251 to mode Modem signals Note indicates active low signal FIGURE 4 Mode Word Format A Command Word Format B and Status word Format C Han User s Manual for 8251 8253 study card DSR SYNDET FE RxRDY TxRDY BRKDET Data set ready indicates that the DSR 1s at a zero level NOTEI ame definition as L O Pin Parity Error The PE flag is set when a parity Error 1s detected It is reset by the ER bit of the command instruction PE does not inhibit operation of the 8251A Overrun Error The OE flag is set when the CPU does not read a character before the next one becomes available It is reset by the ER bit of the command instruction OE does not inhibit operation of the 8251A however the previously overrun character is lost Framing Erro
41. d in order All counters are down counters Thus the value loaded in to the count register will actually be decremented Loading all zeroes in to a count register will result in the maximum count 219 for binary or 10 for BCD In MODE 0 the new count will not restart until the load has been completed It will accept one of two bytes depending on how the MODE control words RLO RL1 are programmed Then proceed with the restart operation MODE Control Word Counter n LSB Count Register byte Counter n MSB Count Register byte Counter n Note Format shown is a simple example of loading the 8253 and does not reply imply that it is the only format that can be used No 1 MODE control Word 1 1 Counter 0 19 HAD User s Manual for 8251 8253 study card No 2 MODE control Word 1 1 Counter 1 No 3 MODE control Word 1 1 Counter 2 No 4 LSB Count Register Byte Counter 0 1 1 5 MSB Count Register Byte Counter 0 1 1 6 LSB Count Register Byte Counter 1 0 2 7 MSB Count Register Byte Counter 1 0 2 8 LSB Count Register Byte Counter 0 0 0 No 9 MSB Count Register Byte Counter 0 0 0 Note The exclusive addresses of each counter s count register make the task of programming the 8253 a very simple matter and maximum effective use of the device will result if this feature is fully utilized Figure 9 Alternat
42. e timer 0 0000 2005 OUTB DX AL For mode 3 operation 0000 2006 BA CO FF OVW DX TMO 0000 2009 BO 69 IOVB AL 69 Load TMER 0 Count 0000 200B EE OUTB DX AL for 110 baud 0000 200C BO 03 OVB AL 03 0000 200E ERE OUTB DX AL 0000 200F BC 00 30 IOVW SP 3000 0000 2012 BO 00 OVB AL 00 0000 2014 BA CA FF OVW DX M51 Reset USART 0000 2017 OUTB DX AL 0000 2018 OUTB DX AL 0000 2019 OUTB DX AL 0000 201A OUTB DX AL 0000 201B E8 2E 00 CALL DLY 0000 201E BO 40 OVB AL 40 0000 2020 OUTB DX AL 0000 2021 8 28 00 CALL DLY 0000 2024 BO CE AOVB AL OCE 0000 2026 FE OUTB DX AL 0000 2027 8 22 00 CALL DLY 0000 202A BO 27 AOVB AL 27 0000 202C OUTB DX AL 0000 2020 E8 00 CALL DLY 0000 2030 00 21 OW 51 2100 0000 2033 FF STS MOVW DX M51 Get USART status for transmitter 46 HAD User s Manual for 8251 8253 study card 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 2036 2037 24 81 2039 3 81 203 75 6 2030 8A 04 204 46 2040 3C 00 2042 74 06 2044 BA C8 FF 2047 2048 EB E9 204A CC 204 9 02 00 204E E2 FE 2050 C3 2100 1 45 4D 2104 20 50 52 4F 2108 47 52 D 210C 20 46 4F 52 210 20 3l 345 30 2114 20 42 55 2115 44 OD 00
43. iggered Strobe 4 6 Wee 4 OUTPUT in 4 GATE OUTPUT In 4 Figure 7 8253 Timing Diagrams 8253 READ WRITE PROCEDURE ao User s Manual for 8251 8253 study card 18 Write Operations The system software must program each counter of the 8253 with the mode and quantity desired The programmer must write out to the 8253 a MODE control word and the programmed number of count register bytes 1 or 2 prior to actually using the selected counter The actual order of the programming is quite flexible Writing out of the MODE control word can be in any sequence of counter section e g counter 2 last Each counter s MODE control word register has a separate address so that its loading is completely sequence independent SCO SC1 The loading of the count register with the actual count value however must be done in exactly the sequence programmed in the MODE control word RLO RL1 This loading of the counter s count register is still sequence independent like the MODE control word loading but when a selected count register is to be loaded it must be loaded with the number of bytes programmed in the MODE control word RLO RL1 The one or two bytes to be loaded in the count register do not have to follow the associated MODE control word They can be programmed at any time following the MODE control word loading as long as the correct number of bytes is loade
44. inary or BCD Single 5V Supply 24 Pin dual In line Package The Intel 8253 is a programmable counter timer chip designed for use as an Intel microcomputer peripheral It uses nMOS technology with a single 5V supply and is packaged in a 24 pin plastic DIP It is organized as 3 independent 16 bit counters each with a count rate of up to 2 Mhz All modes of operation are software programmable PIN CONFIGURATION w N m 4 5 6 7 8 9 11 HAD User s Manual for 8251 8253 study card FUNCTIONAL DESCRIPTION General The 8253 is a programmable interval timer counter specifically designed for use with the Intel microcomputer systems Its function is that of a general purpose multi timing element that can be treated as an array of I O ports in the system software The 8253 solves one of the most common problems in the microcomputer system the generation of accurate time delays under software control Instead of setting up timing loops in system software the programmer configures the 8253 to match his requirements initialize one of the counter of 8253 with the desired quantity then upon command the 8253 will count out the delay and interrupt the CPU when it has completed its tasks it is easy to easy to see that the software overhead is minimal and that multiple delays can easily be maintained by assignment of priority levels Other counter timer functions that are non delay in nature but also common to most microco
45. ing Programming Formats Read operations In most counter applications it becomes necessary to read the value of the count in progress and make a computational decision based on this quantity Event counters are probably the most common application that uses this function The 8253 contains logic that will allow the programmer to easily read the contents of any of three counters without disturbing the actual count in progress There are two methods that the programmer can use to read the value of the counters The first method involves the use of simple I O read operations of the selected counter By controlling the AO Al inputs to the 8253 the programmer can select the counter to be read remember that no read operation of the mode register is allowed AO 1 11 The only requirement with this method is that in order to assure a stable count reading the actual operation of the selected counter must be inhibited either by controlling the Gate input or by external logic that inhibits the clock input The contents of the counter selected will be available as follows First I O Read contains the least significant byte LSB Second I O Read contains the most significant byte MSB 20 HAD User s Manual for 8251 8253 study card Due to the internal logic of the 8253 it is absolutely necessary to complete the entire reading procedure If two bytes are programmed to be read then two bytes must be read before any loading WR commands can
46. mputers can be implemented with the 8253 Programmable Rate Generator Event Counter Binary rate multiplier Real Time Clock Digital One shot Complex Motor controller Data Bus Buffer This 3 state bi directional 8 bit buffer is used to interface the 8253 to the system data bus Data is transmitted or received by the buffer upon execution of IN put or OUT put CPU instructions The Data Bus Buffer has three basic functions 1 Programming the MODES of the 8253 2 Loading the count registers 3 Reading the count values Read Write Logic The Read Write Logic accepts inputs from the system bus and in turn generates control signals for overall device operation It is enabled or disabled by CS so that no operation can occur to change the function unless the device has been selected by the system logic RD Read A low on this input informs the 8253 that the CPU is inputting the data in the form of a counter value WR Write A low on this input informs the 8253 that the CPU is outputting the data in the form of mode information or loading counters 12 HAD User s Manual for 8251 8253 study card AO 1 These inputs are normally connected to the address bus Their function is to select one of the three counters to be operated on and to address the control word register for mode selection CS Chip Select A low on this input informs the 8253 No reading or writing will occur unless the device is
47. ontinuous loop press ESC to come out from the loop Execute the Program at 8000H ADDRESS OPCODE LABLE MNEMONIC COMMENTS ORG 8000H 8000 74 36 OV A 136H 8002 90 Fl OV DPTR 0F183H TIMER 0 CMD 8005 FO OVX DPTR A 006 90 Fl 80 DPTR 0F180H 8009 74 OA TIMER ODATA 800B FO OVX QDPTR A 800C 74 00 OV A 00H 800E FO MOVX DPTR A 800F 90 Fl 91 OV DPTR 0F191H Initialize USART 8012 FO OVX DPTR A 8013 FO OVX DPTR A 28 User s Manual for 8251 8253 study card FJ O UJ OO e nj 8022 8024 8026 8029 802A 802C 8031 8032 8034 8037 803A 803D 803E CD I e Sop PBB H O UJ o 74 40 74 25 90 90 CO 83 CO 82 90 Fl 54 02 60 F8 90 EE F5 FO 02 00 E5 F0 90 FO DO 82 DO 83 FO A3 80 D1 FE 00 91 90 03 91 FA 90 GETCH SOUTPT STATUS IOVX MOVX OV A 40H IOVX DPTR IOV A CEH OVX DPTR R DPTR DFTR gt G D D OV A 425 DPTR OV DPTR 9 HU o A 000H Memory to store the PUSH DPH Character PUSH DPL MOV DPTR 0F191H OVX A DPTR ANL A 02H JZ GETCH IOV DPTR 0F190H MOVX A DPTR OV OFOH A CJNE A 1BH SO
48. ounter is reloaded with the full count and the whole process is repeated If the count is odd and the output is high the first clock pulse after the count is loaded decrements the count by 1 Subsequent clock pulses decrement the clock by 2 After timeout the output goes low and the full count 16 HAD User s Manual for 8251 8253 study card is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by 2 until the timeout Then the whole process is repeated in this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts MODE 4 Software Triggered Strobe After the mode is set the output will be high When the count is loaded The counter will begin counting On terminal count the output will go low for one input clock period and then will go high again If the count register is reloaded between output pulses the present period will not be affected but the subsequent period will reflect the new value The count will be inhibited while the gate input is low Reloading the counter register will restart counting beginning with new number MODE 5 Hardware Triggered strobe The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached The counter is retriggerable The output will not go low until the full count after the rising edge of an
49. r Async only The FE flag 1s set when a valid stop bit 15 not detected at the end of every character It 15 reset by the ER bit of the command Instruction FE does not inhibit the operation of the 8251A NOTE1 TxRDY status bit has different meanings from the TxRDY output pin The former 15 not conditioned by CTS And TxEN the latter is conditioned by both CTS and TxEN ie TXRDY status bit DB buffer empty TxRDY pin out DB buffer empty CTS 0 TxEN 1 C D User s Manual for 8251 8253 study card Pin Configuration 1 2 3 4 5 6 7 8 9 SYNDET BD TxRDY Data Bus 8 bits Control or Data is to be Written or Read Read Data Command Write Data or Control Command Chip Enable Clock Pulse TTL Reset Transmitter Clock Transmitter Data Receiver Clock Receiver Data Receiver Ready Transmitter Ready Data Set Ready Data Terminal Ready sync detect break detect Request to send data clear to send data transnutter empty 5 vnlt amnlv D User s Manual for 8251 8253 study card Block Diagram Transmit Buffer Transmit control Receive Buffer S P Receive Control Data bus FIGURE 1 The 8251 A Block Diagram Pin Configuration and Description User s Manual for 8251 8253 study card 8253 8253 5 PROGRAMMABLE INTERVAL TIMER MCS 85 Compatible 8253 5 3 Independent 16 Bit Counter DC to 2 MHz Programmable Counter Modes Count B
50. the trainer kit respectively 6 ESA 31 Study Card adapter Connect 50 pin FRC cable between J1 of adapter with J5 of ESA 31 51 Trainer the trainer kit Connect 26 pin FRC cables between J3 J4 of adapter with J3 J4 of the study card respectively 7 ESA 51 Study Card adapter Connect 50 pin FRC cable between J1 of adapter with J1 of ESA 31 51 Trainer the trainer kit Connect 26 pin FRC cables between J3 J4 of adapter with J3 J4 of the study card respectively 8 ESA 51E ESA SIE Study Connect 50 pin FRC cable between P3 of adapter with P1 of card adapter study card Connect 26 pin FRC cables between J3 J4 of adapter with J4 J6 of the trainer kit respectively The 8251A programmable communication interface The 8251A is a programmable chip designed for synchronous and a synchronous serial data communication packaged in a 28 pin DIP The 8251A is the enhanced version of its predecessor the 8251 and it is compatible with the 8251 Figurel shows the block diagram of the 8251A It includes 5 sections Read Write Control Logic Transmitter Receiver Data Bus Buffer and Modem Control The control logic interfaces the chip with the MPU determines the function of the chip according to the control word in its register to be explained below and monitors the data flow The transmitter section converts a parallel word received from the MPU into serial bits and transmits them over the TxD line to a peripheral The receiver section
51. ully independent and each can have separate Mode configuration and counting operation binary or BCD Also there are special features in the control word that handle the loading of the count value so that software overhead can be minimized for these functions The reading of the contents of each counter is available to the programmer with simple READ operations for event counting applications and special commands and logic are included in the 8253 so that the contents of each counter can read on the fly without having to inhibit the clock input 8253 SYSTEM INTERFACE The 8253 is a component of the Intel microcomputer systems and interfaces in the same manner as all other peripherals of the family It is treated by the system software as an array of peripheral I O ports three are counters and the fourth is a control register for MODE programming Basically the select inputs AO A1 connect to the A0 A1 address bus signals of the CPU The CS be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger systems ADDRESS BUS 16 CONTROT RUS LOR Vow DATA BUS 8 Al 0 D0 D7 WR 8253 COU RO COUNTERI COUNTERS OUT GATE CLK OUT GATE CLK OUT GATE CLK Figure 4 Block Diagram Showing Control Word Register and Counter Functions 14 HAD User s Manual for 8251 8253 study card OPERATIONAL DESC
52. y trigger Modes Signa Low Or going low Rising High 1 Status 0 Disables counting Enables counting 1 1 Initiates counting 2 Resets output after next clock 2 1 Disables 1 Reloads counter Enables counting counting 2 Initiates counting 2 Sets output immediately high 3 1 Disables Initiates counting Enables counting counting 2 Sets output immediately high 4 Disables counting Enables counting 5 Initiates counting Figure 6 Gate Pin Operations Summary HAD User s Manual for 8251 8253 study card 17 MODE 0 interrupt on Terminal Count ma 5 OUTPUT nNTERAUPTI im 5 MODE 1 Programmable One Shot secx_JrLTLFLFLTUTLLTLFLTLTLLTL a TAIOOER 229 1 y 5o IA TAGGER rr i 4 4v CE CM irai MODE 2 Rate Generator SN Wi a 31 4 32 1 OMS 3 1 0200132 o gt 1 1 2 1 gt 3 2 3 wre vL 27 MODE 3 Square Wave Generator eec Tiriririnnn nnnnr Ru he RR Din at Da md 2 0 812 2 OUTPUT in e fi cec 512 MODE 4 Software Triggered Sirobe ma fon 2 24 9 gj 582 Rp CUTPUT Les TL _ 4 QUNE ae te ee ee MODE 5 Hardware Tr
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