Home

R8C/1A, R8C/1B Group Hardware Manual

1. Rev 1 30 Dec 08 2006 Page 21 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 4 Special Function Registers SFRs Table 4 3 SFR Information 3 1 Address Register Symbol After reset 0080h Timer Z Mode Register TZMR 00h 008Th 0082h 0083h 0084h Timer Z Waveform Output Control Register PUM 00h 0085h Prescaler Z Register PREZ FFR 0086h Timer Z Secondary Register TZSC FFh 0087h Timer Z Primary Register TZPR FER 0088h 0089h 008Ah Timer Z Output Control Register TZOC 00h 008Bh Timer X Mode Register TXMR ooh 008Ch Prescaler X Register PREX FFh 008Dh Timer X Register TX FFR DUGER Timer Count Source Setting Register TCSS 00h 008Fh 0090h Timer C Register TC 00h 0091h 00h 0092h 0093h 0094h 0095h 0096h External Input Enable Register INTEN 00h 0097h 0098h Key Input Enable Register KIEN 00h 0099h 009Ah Timer C Control Register 0 TCCO 00h 009Bh Timer C Control Register 1 TCC1 00h 009Ch Capture Compare 0 Register TMO 0000h 2 009Dh FFFFh 3 009Eh Compare 1 Register TM1 EEN 009Fh FFh OOA0h UARTO Transmit Receive Mode Register UOMR 00h OOATh UARTO Bit Rate Generator UOBRG XXh 00A2h UARTO Transmit Buffer R
2. TXOCNT bit NEE Write to TX register Bits TXMOD1 to TXMODO 01b TXMODO to TXMOD1 ROEDG TXS TXOCNT Bits in TXMR register TXCKO to TXCK1 Bits in TCSS register CNTRSEL Bit in UCON register Figure 14 1 Block Diagram of Timer X Rev 1 30 Dec 08 2006 Page 109 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 b1 bO Address After Reset 008Bh 00h TXMODO Timer mode or pulse period measurement mode Pulse output mode TXMOD1 Event counter mode Pulse w idth measurement mode ROEDG INT1 CNTRO signal Function varies depending on operating mode polarity sw itch bit Timer X count start flag e Stops counting Starts counting TXOCNT P3_7 CNTRO select bit Function varies depending on operating mode Operating mode select bit 2 0 Other than pulse period measurement mode 1 Pulse period measurement mode Active edge judgment flag Function varies depending on operating mode TXUND Timer X underflow flag Function varies depending on operating mode NOTES 1 The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources 2 Refer to 14 1 6 Notes on Timer X for precautions regarding the TXS bit Figure 14 2 TXMR Register Rev 1 30 Dec 08 2006 Page 1100f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14
3. 1 Overview Package type SP PLSP0020JB A DD PRDP0020BA A NP PWQN0028KA B ROM number Classification D Operating ambient temperature 40 C to 85 C No Symbol Operating ambient temperature 20 C to 85 C Y Operating ambient temperature 20 C to 105 C Note ROM capacity 1 4 KB 2 8KB 3 12 KB 4 16 KB R8C 1A Group R8C Tiny Series Memory type F Flash memory version Renesas MCU Renesas semiconductors NOTE Please contact Renesas Technology sales offices for the Y version Figure 1 2 Type Number Memory Size and Package of R8C 1A Group Rev 1 30 Dec 08 2006 Page6of315 stENESAS REJ09B0252 0130 Table 1 4 Type No R8C 1A Group R8C 1B Group ROM Capacity Program ROM Data Flash Product Information for R8C 1B Group RAM Capacity 1 Overview Current of December 2006 Package Type Remarks R5F211B1SP 4 Kbytes Kbyte x 2 384 bytes PLSP0020JB A R5F211B2SP 8 Kbytes Kbyte x 2 512 bytes PLSP0020JB A R5F211B3SP 12 Kbytes Kbyte x 2 768 bytes PLSP0020JB A R5F211B4SP 16 Kbytes Kbyte x 2 1 Kbyte PLSP0020JB A R5F211B1DSP 4 Kbytes Kbyte x 2 384 bytes PLSP0020JB A R5F211B2DSP 8 Kbytes Kbyte x 2 512 bytes PLSP0020JB A R5F211B3DSP 12 Kbytes Kbyte x 2 768 bytes PLSP0020JB A R5F211B4DSP 16 Kbytes Kbyte x 2 1 Kbyte PLSP0020JB A D version
4. n 2008 UJ fg 91D Counter d 10b Timer X underflow o PREZ register f2 1b o NTO C D Digital filter Input polarity selected to be one edge or both edges INTOPL INTOEN TZMOD1 to TZMODO 01b 10b 11b Counter Timer Z interrupt TZMOD1 to TZMODO 10b 11b p gt INTO interrupt INOSEG TZOPL 1 OD Toggle TZOCNT 0 TZOUT O A ec o P1_3 bit in P1 register TZOCNT 1 TZMODO to TZMOD1 TZS Bits in TZMR register TZOS TZOCNT Bits in TZOC register TZOPL INOSTG Bits in PUM register TZCKO to TZCK1 Bits in TCSS register flip flop CK CLR TZOPL 0 Write to TZMR register TZMOD1 to TZMODO 01b 10b 11b INTOEN INTOPL Bits in INTEN register Figure 14 11 Block Diagram of Timer Z Rev 1 30 Dec 08 2006 Page 123 0f315 speeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0080h 00h SE Reserved bits Set to 0 b3 b0 Timer Z operating mode Jeng D RW 0 0 Timer mode RW 0 1 Programmable w aveform generation mode W 1 0 Programmable one shot generation mode 1 1 Programmable w ait one shot generation mode Timer Z write control bit Functions varies depending on operating mode Timer Z count start flag 0 Stops counting NOTE 1 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS
5. CO Ni o O1 BY GC PO CNTROO CNTRO1 CMP0_1 CMPO0_0 TCIN CMP1_0 CMP1_1 CMP1_2 CNTRO Rev 1 30 Dec 08 2006 Page 14 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 2 Central Processing Unit CPU 2 Central Processing Unit CPU Figure 2 1 shows the CPU Registers The CPU contains 13 registers RO R1 R2 R3 AO A1 and FB configure a register bank There are two sets of register bank b15 b8b7 bO ROH high order of RO ROL low order of RO R1H high order of R1 R1L low order of R1 gt Data registers LD 0 gt Address registers A FB Framebase register b19 b15 INTBH INTBL Interrupt table register The 4 high order bits of INTB are INTBH and the 16 low bits of INTB are INTBL b19 Program counter User stack pointer Interrupt stack pointer Static base register Flag register b0 O B S Z DIC Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE 1 These registers comprise a register bank There are two register banks Figure 2 1 CPU Register Rev 1 30 Dec 08 2006 Page 15 of 315 2tENESAS REJ09B0252 0130 R8C 1A
6. ICDRT register ICDRS register Processing 3 Data write to ICDRT 6 Generate stop condition and by program register set TEND bit to 0 7 Set to slave receive mode Figure 16 34 Operating Timing in Master Transmit Mode I2C bus Interface Mode 2 Rev 1 30 Dec 08 2006 Page 213 0f 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 3 3 Master Receive Operation In master receive mode the master device outputs the receive clock receives data from the slave device and returns an acknowledge signal Figures 16 35 and 16 36 show the Operating Timing in Master Receive Mode I2C bus Interface Mode The receive procedure and operation in master receive mode are shown below 1 After setting the TEND bit in the ICSR register to 0 switch from master transmit mode to master receive mode by setting the TRS bit in the ICCR1 register to 0 Also set the TDRE bit in the ICSR register to 0 2 When performing the dummy read of the ICDRR register and starting the receive operation the receive clock is output in synchronization with the internal clock and data is received The master device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the 9th clock cycle of the receive clock 3 The 1 frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the 9th clock cycle At this time when reading the ICDRR
7. Transfer bit count n 1 to 8 gt Transfer frame count m from 1 b EC bus format when start condition is retransmitted FS 0 RW DATA s R W a DATA KSE EE Upper Transfer bit count n1 n2 1 to 8 Lower Transfer frame count m1 m2 1 or more H CITT CH sot B freh fA SA her SA SA her fol fof E Explanation of symbols S Start condition The master device changes the SDA signal from H to L while the SCL signal is held H SLA Slave address Indicates the direction of data transmit receive DATA R W value is 0 Acknowledge The receive device sets the SDA signal to L Transmit receive data Stop condition The master device changes the SDA signal from L to H while the SCL signal is held H Data is transmitted from the slave device to the master device when RW value is 1 and from the master device to the slave device when Figure 16 32 12C bus Format and Bus Timing Rev 1 30 Dec 08 2006 Page 211 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 3 2 Master Transmit Operation In master transmit mode the master device outputs the transmit clock and data and the slave device returns an acknowledge signal Figures 16 33 and 16 34 show the Operating Timing in Master Transmit Mode ZC bus Interface Mode The transmit procedure and operation in master
8. IOH peak Peak output H current IOH avg Average output H current lOL sum Peak sum output Sum of all pins L currents lOL peak IOL peak Peak output L Except P1_0 to P1_3 currents P1_0to P1_3 Drive capacity HIGH Drive capacity LOW lOL avg Average output Except P1_0 to P1_3 L current P1_0 to P13 Drive capacity HIGH Drive capacity LOW Main clock input oscillation frequency 3 0 V lt Vcc lt 5 5 V 2 7 V lt Vcc lt 3 0 V NOTES OCD2 0 Main clock selected System clock 3 0 V lt Vcc lt 5 5 V 2 7 V lt Vcc lt 3 0 V OCD2 1 On chip oscillator clock selected HRA01 0 Low speed on chip oscillator clock selected HRAO1 1 High speed on chip oscillator clock selected 1 Vcc 2 7 to 5 5 V at Topr 20 to 85 C 40 to 85 C unless otherwise specified 2 Typical values when average output current is 100 ms Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 276 of 315 stENESAS R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 3 A D Converter Characteristics Standard Parameter Conditions Resolution Vref Voc Absolute 10 bit mode AD 10 MHZ Vref Vcc 5 0 V accuracy 8 bit mode AD 10 MHZ Vret Vcc 5 0 V 10 bit mode AD 10 MHz Vret Vcc 3 3 V63 8 bit mode AD 10 MHz Vret Vcc 3 3 V63 Rladder Resistor la
9. 12 1 2 Software Interrupts A software interrupt is generated when an instruction is executed Software interrupts are non maskable 12 1 2 1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed 12 1 2 2 Overflow Interrupt The overflow interrupt is generated when the O flag is set to 1 arithmetic operation overflow and the INTO instruction is executed Instructions that set the O flag are ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA and SUB 12 1 2 3 BRK Interrupt A BRK interrupt is generated when the BRK instruction is executed 12 1 2 4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed The INT instruction can select software interrupt numbers 0 to 63 Software interrupt numbers 4 to 31 are assigned to the peripheral function interrupt Therefore the MCU executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt is generated For software interrupt numbers 0 to 31 the U flag is saved to the stack during instruction execution and the U flag is set to 0 ISP selected before the interrupt sequence is executed The U flag is restored from the stack when returning from the interrupt routine For software interrupt numbers 32 to 63 the U flag does not change state during instruction execution and the selected SP is used Rev 1 30 Dec 08
10. CMOS I O ports Each port has an I O select direction register allowing each pin in the port to be directed for input or output individually Any port set to input can be set to use a pull up resistor or not by a program P1_0 to P1_3 also function as LED drive ports P4_2 P4_6 P4_7 Input only ports I Input O Output I O Input and output Rev 1 30 Dec 08 2006 Page 120f315 sENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview Table 1 6 Pin Name Information by Pin Number of PLSP0020JB A PRDP0020BA A Packages I O Pin Functions for Peripheral Modules Clock Serial Synchronous 12C bus A D Interface Serial I O with Interface Converter Chip Select CMP1_2 SSCK SCL CNTRO SSO Pin Control Number Pin Interrupt Timer RESET XOUT VSS AVSS XIN VCC AVCC MODE CO NI o Ei Oj PO H CNTROO CNTRO1 TZOUT CMP0O_2 CMPO_1 CMPO 0 TCIN CMP1_0 CMP1_1 Rev 1 30 Dec 08 2006 Page 13 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview Table 1 7 Pin Name Information by Pin Number of PWQN0028KA B Package I O Pin Functions for Peripheral Modules Clock Serial Synchronous 12C bus A D Interface Serial I O with Interface Converter Chip Select Pin Control Number Pin Interrupt Timer NC XOUT VSS AVSS NC NC XIN NC VCC AVCC MODE
11. Master slave device select bit 0 Operates as slave device 1 Operates as master device Receive single stop bit 0 Maintains receive operation after receiving 1 byte of data 1 Completes receive operation after receiving 1 byte of data Nothing is assigned If necessary set to 0 b7 When read the content is 0 NOTES The set clock is used when the internal clock is selected The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 operates as master device The MSS bit is set to 0 operates as slave device when the CE bit in the SSSR register is set to 1 conflict error occurs The RSSTP bit is disabled w hen the MSS bit is set to 0 operates as slave device Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial I O with Chip Select for more information Figure 16 2 SSCRH Register Rev 1 30 Dec 08 2006 Page 1720f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Control Register L b7 b6 b5 b4 b3 b2 bi bO Address After Reset 01111101b SE Nothing is assigned If necessary set to 0 When read the content is 1 Ei Clock synchronous When this bit is set to 1 the clock synchronous serial serial VO with chip VO with chip select control block and SSTRSR register select control part are reset SRES reset bit The values of the registers in the clock synchronous serial VO with chip
12. Full status check Block erase completed NOTES 1 In EWO mode the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area 2 td SR SUS is needed until the interrupt request is acknowledged after it is generated The interrupt to enter suspend should be in interrupt enabled status 3 When no interrupt is used the instruction to enable interrupts is not needed Figure 18 15 Block Erase Command When Erase Suspend Function Enabled Rev 1 30 Dec 08 2006 Page 265 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 4 Status Register The status register indicates the operating status of the flash memory and whether an erase or program operation has completed normally or in error Status of the status register can be read by bits FMROO FMRO6 and FMRO7 in the FMRO register Table 18 5 lists the Status Register Bits In EWO mode the status register can be read in the following cases e When a given address in the user ROM area is read after writing the read status register command e When a given address in the user ROM area is read after executing program or block erase command but before executing the read array command 18 4 4 1 Sequencer Status Bits SR7 and FMROO The sequencer status bits indicate the operating status of the flash memory SR7 is set to 0 busy during auto programming and auto erasure and is set to ready at the
13. Main clock off High speed on chip oscillator off Low speed on chip oscillator on 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 VCA26 0 Stop mode Main clock off Topr 25 C High speed on chip oscillator off Low speed on chip oscillator off CM10 1 Peripheral clock off VCA27 VCA26 0 Rev 1 30 Dec 08 2006 Page 289 of 315 speRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Timing Requirements Unless otherwise specified Vcc 5 V Vss 0 V at Ta 25 C Vcc 5 V Table 19 16 XIN Input Standard Min Symbol Parameter te XIN XIN input cycle time 50 tWH XIN XIN input H width 25 tWL XIN XIN input L width 25 WH XIN XIN input TWL XIN Figure 19 8 XIN Input Timing Diagram when Vcc 5 V Table 19 17 CNTRO Input CNTR1 Input INT1 Input Standard Symbol Parameter Min Max Unit te CNTRO CNTRO input cycle time 100 ns tWH CNTRO CNTRO input H width 40 ns tWL CNTRO CNTRO input L width 40 ns CNTRO input tWL CNTRO Figure 19 9 CNTRO Input CNTR1 Input INT1 Input Timing Diagram when Vcc 5 V Table 19 18 TCIN Input INT3 Input Standard Min Symbol Parameter tc TCIN TCIN input cycle time 400 1 tWH TCIN TCIN input H width 200 2 tWL TCIN TCIN input
14. TCOUT3 CMP output enable 0 Disables CMP output from CMP1_0 1 Enables CMP output from CMP1_0 RW RW RW RW RW RW RW WW Figure 14 29 TCOUT Register Rev 1 30 Dec 08 2006 Page 146 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 3 1 Input Capture Mode Rev 1 30 REJ09B0252 0130 In input capture mode the edge of the TCIN pin input signal or the fRING128 clock is used as a trigger to latch the timer value and generate an interrupt request The TCIN input contains a digital filter and this prevents errors caused by noise or the like from occurring Table 14 11 shows the Input Capture Mode Specifications Figure 14 30 shows an Operating Example in Input Capture Mode Table 14 11 Item Input Capture Mode Specifications Specification Count sources f1 f8 82 fRING fast Count operations e Increment e Transfer the value in the TC register to the TMO register at the active edge of the measured pulse e The value in the TC register is set to 0000h when the count stops Count start condition The TCCO0 bit in the TCCO register is set to 1 count starts Count stop condition The TCCOO bit in the TCCO register is set to 0 count stops Interrupt request generation timing e When the active edge of the measured pulse is input INT3 interrupt 1 e When timer C overflows timer C interrupt INT3 TCIN pin function Programmable I O port or the me
15. 1 to the TXS bit gt Q count stops can be read after the TXS bit is set to 1 revised 20 3 2 Precautions on Timer Z When writing 1 count starts to writing 1 to the TZS bit gt Q count stops can be read after the TZS bit is set to 1 revised 20 5 1 2 Selecting SSI Signal Pin added 21 Precautions on On Chip Debugger 1 added C 3 REVISION HISTORY R8C 1A Group R8C 1B Group Hardware Manual R D Description ev ate Summa 1 10 Mar 17 2006 Products of PWQN0028KA B package included or SDIP gt SDIP or a 28 pin plastic molded HWQFN Table 1 1 Table 1 2 28 pin molded plastic HWQFN added Table 1 3 Table 1 4 Type No added deleted Figure 1 6 added Table 1 7 added Figure 3 1 Figure 3 2 Part Number added deleted 6 2 When a capacitor is connected to pin 0 8VCC or more added Figure 10 1 revised Table 10 2 CM1 Register CM17 CM16 revised Figure 13 2 Option Function Select Register NOTE 1 revised NOTE 2 revised Watchdog Timer Control Register NOTE 1 deleted Table 14 3 NOTE 1 added Figure 14 25 revised Table 14 12 NOTE 1 revised Figure 15 3 NOTE 3 added Figure 15 5 NOTE 1 added Table 16 1 revised Table 16 2 NOTE 1 deleted Figure 16 8 SS Transmit Data Register The last NOTE 1 deleted 16 2 5 2 16 2 5 4 16 2 6 2 When setting the microcomputer to continuous transmit is enabled
16. Count source input ONT interrupt input CNTRO pin function Programmable I O port Read from timer The count value can be read out by reading registers TX and PREX Write to timer e When registers TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each reload register of registers TX and PREX at the following count source input the data is transferred to the counter at the second count source input and the count re starts at the third count source input Select functions e INT1 CNTPO signal polarity switch function The ROEDG bit can select the active edge of the count source e Count source input pin select function The CNTRSEL bit in the UCON register can select the CNTROO or CNTRO1 pin Timer X Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset een Sch mema aee o e TXMODO Operating mode select bits 0 1 b1 bO TED 1 0 Event counter mode o r Rising edge NT1 CNTRO signal ROEDG E polarity sw itch bit Falling edge be Timer X count start flag GG Stops counting Starts counting NOTES 1 The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources 2 Refer to 14 1 6 Notes on Timer X for precautions regarding the TXS bit Figure 14 6
17. Input Input Output 1 Input Output Input Input Input 1 Output 1 Output Output Input Output Output 4 wire bus bidirectional communication mode 2 NOTES 1 This pin can be used as a programmable I O port 1 Input Input 1 Output Input Input Output Ol O O O O O 1 1 1 Output 2 Do not set both bits TE and RE to 1 in 4 wire bus bidirectional communication mode SSUMS and BIDE Bits in SSMR2 register MSS Bit in SSCRH register TE and RE Bits in SSER register Rev 1 30 Dec 08 2006 Page 183 0f 315 pRENESAS REJ09B0252 0130 Output R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 5 Clock Synchronous Communication Mode 16 2 5 1 Initialization in Clock Synchronous Communication Mode Figure 16 12 shows Initialization in Clock Synchronous Communication Mode To initialize set the TE bit in the SSER register to 0 transmit disabled and the RE bit to 0 receive disabled before data transmission or reception Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format Setting the RE bit to 0 does not change the contents of flags RDRF and ORER and the contents of the SSRDR register Start SSER register RE bit lt 0 TE bit 0 SSMR2 register SSUMS bit lt 0 SSMR registe
18. L width 200 2 NOTES 1 When using timer C input capture mode adjust the cycle time to 1 timer C count source frequency x 3 or above 2 When using timer C input capture mode adjust the pulse width to 1 timer C count source frequency x 1 5 or above TCIN input Figure 19 10 TCIN Input INT3 Input Timing Diagram when Vcc 5 V Rev 1 30 Dec 08 2006 Page 290 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 19 Serial Interface Standard Min Max tc CK CLKi input cycle time 200 tw CKH CLKi input H width 100 tw CKL CLKi input L width 100 ta C Q TXDi output delay time th C Q TXDi hold time 0 tsu D C RXDi input setup time 50 th C D RXDi input hold time 90 i Oor1 Symbol Parameter Figure 19 11 Serial Interface Timing Diagram when Vcc 5 V Table 19 20 External Interrupt INTO Input Standard Min INTO input H width 250 1 INTO input L width 250 2 Parameter NOTES 1 When selecting the digital filter by the INTO input filter select bit use an INTO input HIGH width of either 1 digital filter clock frequency x 3 or the minimum value of standard whichever is greater ___ 2 When selecting the digital filter by the INTO input filter select bit use an INTO input LOW width of either 1 digital filter clock frequency x 3 or the minimum value
19. R8C 1A Group R8C 1B Group 5 Programmable UO Ports Table 5 7 Register Port P1_3 KI3 AN11 TZOUT ADCONO TZMR TZOC Bit CH2 CH1 CHO ADGSELO TZMOD1 TZMODO Function TZOCNT Setting Value X 0or 1 Table 5 8 Register XXXXb 00b Input port not pulled up XXXXb 00b Input port pulled up XXXXb 00b KI3 input 1111b 00b A D converter input AN11 XXXXb 00b Output port Output port high drive Output port Output port high drive TZOUT output UOMR Bit SMD2 SMD1 SMDO TZOUT output Function Setting Value X 0or1 Table 5 9 Register 000b Input port not pulled up 000b Input port pulled up 000b Output port 001b 100b 101b 110b TXDO output CMOS output 001b 100b 101b 110b UCON TXMR Bit CNTRSEL TXMOD1 TXMODO TXDO output N channel open output Function Setting Value X XXb Input port not pulled up X XXb Input port pulled up X Other than 01b RXDO input Other than 01b CNTRO1 INT11 input Other than 01b Output port Other than 01b CNTRO1 output Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 33 of 315 2tENESAS R8C 1A Group R8C 1B Group 5 Programmable UO Ports Table 5 10 Port P1_6 CLKO SSI01
20. Set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode 2 When the slave address matches at the Ist frame after detecting the start condition the slave device outputs the level set in the ACKBT bit in the ICTER register to the SDA pin at the rise of the 9th clock cycle Since the RDRF bit in the ICSR register is set to 1 simultaneously perform the dummy read the read data is unnecessary because if indicates the slave address and R W 3 Read the ICDRR register every time the RDRF bit is set to 1 If the 8th clock cycle falls while the RDRF bit is set to 1 the SCL signal is fixed L until the ICDRR register is read The setting change of the acknowledge signal returned to the master device before reading the ICDRR register takes affect from the following transfer frame 4 Reading the last byte is performed by reading the ICDRR register in like manner Rev 1 30 Dec 08 2006 Page 220 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SCL master output SDA master output SCL slave output SDA slave output RDRF bit in 1 ICSR register ws me i om ICDRR register Processing 2 Dummy read of ICDRR register 2 Read ICDRR register by program Figure 16 39 Operating Timing in Slave Receive Mode GC bus Interface Mode 1 SCL master output 9 1 2 3 4 5 6 T 8 9 SDA raster oumu E EE
21. The peripheral functions clocked by external signals continue operating Table 10 4 lists Interrupts to Exit Stop Mode and Usage Conditions Table 10 4 Interrupts to Exit Stop Mode and Usage Conditions Interrupt Usage Conditions Key input interrupt INTO to INT interrupts INTO can be used if there is no filter INT3 interrupt No filter Interrupt request is generated at INT3 input TCCO6 bit in TCCO register is set to 1 Timer X interrupt When external pulse is counted in event counter mode Serial interface interrupt When external clock is selected Voltage monitor 2 interrupt Usable in digital filter disabled mode VW2C1 bit in VW2C register is set to 1 10 4 3 1 Entering Stop Mode The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 all clocks stop At the same time the CM06 bit in the CMO register is set to 1 divide by 8 mode and the CM15 bit in the CM10 register is set to 1 main clock oscillator circuit drive capability high When using stop mode set bits OCD1 to OCDO to 00b oscillation stop detection function disabled before entering stop mode 10 4 3 2 Pin Status in Stop Mode The status before wait mode was entered is maintained However when the CM13 bit in the CM1 register is set to 1 XIN XOUT pins the XOUT P4_7 pin is held H When the CM13 bit is set to O input ports P4_6 and P4_7 the P4_7 XOUT pin is held in input status 10 4 3 3 Exiting Stop Mod
22. 200 ns 2 signal Watchdog timer block Voltage detection 2 signal is held H when VCA27 bit is set to 0 disabled VW2F1 to VW2F0 00b 01b VW2C2 bit is set to 0 not detected by writing 0 by a program When VCA27 bit is set to 0 voltage detection 2 circuit disabled VW2C2 bit is set to 0 a Watchdog timer underflow signal Watchdog timer interrupt signal oltage monitor 2 interrupt signal Oscillation stop detection interrupt signal Non maskable interrupt signal Voltage e monitor 2 This bit is set to 0 not detected by writing 0 by a program J VW2C0 to VW2C3 VW2F2 VW2F1 VW2C6 VW2C7 Bits in VW2C register VCA13 Bit in VCA1 register VCA27 Bit in VCA2 register Figure 7 3 Block Diagram of Voltage Monitor 2 Interrupt Reset Generation Circuit Rev 1 30 Dec 08 2006 Page 460f315 stENESAS REJ09B0252 0130 reset signal R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit Voltage Detection Register 1 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset as h 00001 anes Bit Symbol Ca Reserved bits Set to 0 b2 b b0 Voltage detection 2 signal monitor 0 VCC lt Vdet2 VCA13 ia 1 VCC gt Vdet2 or voltage detection 2 circuit disabled Reserved bits Set to 0 The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 voltage detection 2
23. 6 bits 110 7 bits 111 8 bits Clock synchronous serial format w hen read the remaining transfer bit count and w hen written 000b b2 b1 b0 0 00 8 bits 001 1 bit 0 10 2 bits 0 11 3 bits 100 4 bits 101 5 bits 110 6 bits 111 7 bits BC write protect bit When rewriting bits BCO to BC2 write 0 simultaneously 24 When read the contentis 1 Nothing is assigned If necessary set to 0 When read the content is 1 0 No wait Transfer data and acknow ledge bit consecutively 1 Wait After the clock falls for the final data bit L period is extended for two transfer clocks cycles NOTES Rew rite betw een transfer frames When writing values other than 000b write when the SCL signal is L When writing to bits BCO to BC2 write 0 to the BCWP bit using the MOV instruction After data including the acknow ledge bit is transferred these bits are automatically set to 000b When the start condition is detected these bits are automatically set to 000b Do not rewrite when the clock synchronous serial format is used The setting value is enabled in master mode of the PC bus format It is disabled in slave mode of the PC bus format or when the clock synchronous serial format is used Set to 0 when the PC bus format is used Refer to 16 3 8 1 Accessing of Registers Associated with DC bus Interface for more information Figure 16 26 ICMR Register Rev 1 30 Dec 08 2006 Page 204 of 315 pRENESAS REJ09B0252
24. Count source protect mode disabled after reset bit NOTES 1 The OFS register is on the flash memory Write to the OFS register w ith a program 2 if the block including the OFS register is erased FFh is set to the OFS register Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 bi bd Address After Reset 000Fh 00X11111b SE High order bits of w atchdog timer b4 b0 Reserved bit Set to 0 When read the content is undefined RW b5 Reserved bit Set to 0 Prescaler select bit 0 Divided by 16 Figure 13 2 Registers OFS and WDC Rev 1 30 Dec 08 2006 Page 104 0f 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 13 Watchdog Timer Watchdog Timer Reset Register Address After Reset 000Dh Undefined Function When 00h is written before w riting FER the watchdog timer is reset The default value of the w atchdog timer is 7FFFh when count source protection mode is disabled and OFFFh when count source protection mode is enabled NOTES 1 Do not generate an interrupt betw een when 00h and FFh are written 2 When the CSPRO bit in the CSPR register is set to 1 count source protection mode enabled OFFFh is set in the watchdog timer Watchdog Timer Start Register b7 Address After Reset 000Eh Undefined Function The w atchdog timer starts counting after a w rite instruction to this register Count Source Protection Mode Register b7 b6 b5 b4 b3 b2 bi b Address After Reset 00
25. H w hen the timer is stopped INOSTG INTO pin one shot trigger 0 INTO pin one shot trigger disabled RW control bit 1 INTO pin one shot trigger enabled INTO pin one shot trigger 0 Falling edge trigger ie RW ES polarity select bit 1 Rising edge trigger NOTES 1 Set the INOSTG bit to 1 after the INTOEN bit in the INTEN register and the INOSEG bit in the PUM register are set When setting the INOSTG bit to 1 INTO pin one shot trigger enabled set the INTOFO to INTOF1 bits in the INTOF register Set the INOSTG bit to 0 INTO pin one shot trigger disabled after the TZS bit in the TZMR register is set to 0 count stops 2 The INOSEG bit is enabled only when the INTOPL bit in the INTEN register is set to 0 one edge Figure 14 19 Registers TZMR and PUM in Programmable One Shot Generation Mode Rev 1 30 Dec 08 2006 Page 134 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Set to 1 by program TZS bit in TZMR register g H Set to 0 when Set to 1 by INTO pin Set to 1 by program counting ends input trigger We TZOS bit in TZOC register Count source Prescaler Z underflow signal INTO pin input E II Timer Z Count Timer Z primary Starts primary reloads i reloads Contents of timer Z Set to 0 when interrupt request i s acknowledged or set to 0 by rogram i IR bit in TZIC l register Set to 0 by program TZOPL bit in PUM register
26. Nom Max D 4 9 5 0 5 1 E 4 9 50 5 1 A2 0 75 A 08 Au 0 0 0 05 Detail F bp 0 15 0 2 0 25 e 0 5 Lp 0 5 0 6 0 7 x Bo y 0 08 D2 2 0 Ei 2 0 Rev 1 30 Dec 08 2006 Page 311 of 315 sptENESAS REJ09B0252 0130 R8C 1A Group R8C 1B GroupAppendix 2 Connection Examples between Serial Writer and On Chip Debugging Appendix 2 Connection Examples between Serial Writer and On Chip Debugging Emulator Appendix Figure 2 1 shows a Connection Example with M16C Flash Starter M3A 0806 and Appendix Figure 2 2 shows a Connection Example with E8 Emulator ROEQOOO80KCE00 O Connect oscillation circuit dnoi5 gL 9884 VL O8HY 10 TXD 7 VSS O OO OO OO OO A M16C flash starter M3A 0806 1 VCC NOTES 1 An oscillation circuit must be connected even when operating with the on chip oscillator clock 2 Connect an external reset circuit Appendix Figure 2 1 Connection Example with M16C Flash Starter M3A 0806 User reset signal Connect oscillation circuit 4 9884 vg E8 emulator NOTE ROEQOOO80KCE00 1 It is not necessary to connect an oscillation circuit when operating with the on chip oscillator clock Appendix Figure 2 2 Connection Example with E8 Emulator ROEQQOO80KCE00 Rev 1 30 Dec 08 2006 Page 312 0f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Appendix 3
27. PAR j me nEmA enabled VART UART 9 bits synchronous PRYE 1 type UART 8 bits UART 9 bits L D7 D6 Dei D4 D3 D2 D1 DO Jup register MSB LSB conversion circuit Data bus high order bits Data bus low order bits MSB LSB conversion circuit D7 D6 Det D2 D1 DO ue register UART 8 bits UART 9 bits Clock PRYE 1 RT 9 bi synchronous Steg UART type III UART 7 bits UART 7 bits UARTI transmit register UART 8 bits PRYE 0 type i 0or1 lock SP Stop bit synchronous type PAR Parity bit Note Clock synchronous type is implemented in UARTO only Figure 15 2 UARTi Transmit Receive Unit Rev 1 30 Dec 08 2006 Page 153 0f 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface UARTI Transmit Buffer Register i 0 or 1 2 Address After Reset OOA3h 00A2h Undefined OOABh 00AAh Undefined Bit Symbol Function Transmit data eo e o E eros imen reza e comen s orete O T b15 b9 When read the content is undefined NOTES 1 When the transfer data length is 9 bits write data to high byte first then low byte 2 Use the MOV instruction to write to this register UARTi Receive Buffer Register i 0 or 1 b15 b8 b7 bO b7 bo Symbol Address After Reset UORB 00A7h 00A6h Undefined
28. R5F211B1DD 4 Kbytes Kbyte x 2 384 bytes PRDP0020BA A R5F211B2DD 8 Kbytes Kbyte x 2 512 bytes PRDP0020BA A R5F211B3DD 12 Kbytes Kbyte x 2 768 bytes PRDP0020BA A R5F211B4DD 16 Kbytes Kbyte x 2 1 Kbyte PRDPOO20BA A R5F211B2NP 8 Kbytes Kbyte x 2 512 bytes PWQN0028KA B R5F211B3NP 12 Kbytes Kbyte x 2 768 bytes PWQN0028KA B R5F211B4NP 16 Kbytes Kbyte x 2 1 Kbyte PWQN0028KA B R5F211B1XXXSP 4 Kbytes Kbyte x 2 384 bytes PLSP0020JB A R5F211B2XXXSP 8 Kbytes Kbyte x 2 512 bytes PLSP0020JB A R5F211B3XXXSP 12 Kbytes Kbyte x 2 768 bytes PLSP0020JB A R5F211B4XXXSP 16 Kbytes Kbyte x 2 1 Kbyte PLSP0020JB A R5F211B1DXXXSP 4 Kbytes Kbyte x 2 384 bytes PLSP0020JB A R5F211B2DXXXSP 8 Kbytes Kbyte x 2 512 bytes PLSP0020JB A R5F211B3DXXXSP 12 Kbytes Kbyte x 2 768 bytes PLSP0020JB A R5F211B4DXXXSP 16 Kbytes Kbyte x 2 1 Kbyte PLSP0020JB A Factory programming product 1 D version R5F211B1XXXDD 4 Kbytes Kbyte x 2 384 bytes PRDP0020BA A R5F211B2XXXDD 8 Kbytes Kbyte x 2 512 bytes PRDP0020BA A R5F211B3XXXDD 12 Kbytes Kbyte x 2 768 bytes PRDP0020BA A R5F211B4XXXDD 16 Kbytes Kbyte x 2 1 Kbyte PRDP0020BA A R5F211B2XXXNP 8 Kbytes Kbyte x 2 512 bytes PWQN0
29. R8C 1A Group R8C 1B Group 17 A D Converter A D conversion rate selection CKSO 1 fRING fast O Resistor ladder Successive conversion register ADCAP 0 Software trigger ADCONO o Trigger SR Timer Z O interrupt request ADCAP 1 AD register Decoder I Comparator ADGSELO 0 ADGSELO 1 CH2 to CHO 100b CH2 to CHO 101b CH2 to CHO 110b CH2 to CHO 111b P1_0 AN8 P1_1 AN9 P1_2 AN10 O P1_3 AN11 CHO to CH2 CKSO Bits in ADCONO register CKS1 VCUT Bits in ADCON1 register Figure 17 1 Block Diagram of A D Converter Rev 1 30 Dec 08 2006 Page 233 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset OOD6h 00000XXXb Analog input pin select b2 b1 b bits 100 AN8 101 AN9 110 AN10 RW 111 AN11 CH2 Other than above Do not set R W A D operating mode select 0 One shot mode A D input group select bit 0 Disabled ADCAP A D conversion automatic 0 Starts at softw are trigger ADST bit RW start bit 1 Starts at capture timer Z interrupt request A D conversion start flag 0 Disabes A D conversion ADST A Starts A D conversion Frequency select bit 0 When CKS1 in ADCON1 register 0 0 Selects f4 1 Selects f2 When CKS1 in ADCON1 register 1 0 Selects f1 1 fRING fast NOTE f the ADCONO register is
30. SSU Refer to Table 16 4 Association Register UOMR between Communication Modes and UO Pins Function Bit Soe iat SSI Output Control SSI Input Control SSISEL Other than 0X10b 0 X Input port not pulled up Other than 0X10b 0 X Input port pulled up XXX1b 0 X CLKO external clock input Setting Other than 0X10b 0 X Output port Value re a vies clock xX xX XXXXb 0 1 1 SSI01 input X X XXXXb 1 0 1 SSI01 output X 0or1 Table 5 11 Port P1_7 CNTROO INT10 Register TXMR UCON Bit TXMOD1 TXMODO CNTRSEL Other than 01b Input port not pulled up Function Other than 01b Input port pulled up Other than 01b CNTROO INT10 input Other than 01b Output port Other than 01b CNTROO output Setting Value X 0or 1 Table 5 12 Port P3_3 TCIN INT3 SSI00 CMP1_0 SSU Refer to Table 16 4 Association between Communication Modes and I O Pins Function SSI Output SSI Input Control Control 0 Register TCOUT3 U E oo Input port not pulled up Input port pulled up SSI100 input Output port 0 0 X 0 Setting Value 1 Output port CMP1_0 output SSI00 output TGIN input INT3 x XxX o XxX XxX x x ojx x XxX o x S X 0 or 1 Rev 1 30 Dec 08 2006 Page 24 oi 218 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable I O Ports Table 5 13 Port
31. disable w hen the VCA26 bit is set to 0 voltage detection 1 circuit disabled Figure 7 5 VW1C Register Rev 1 30 Dec 08 2006 Page 48 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit Voltage Monitor 2 Circuit Control Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0037h 00h Bi Symbol Voltage monitor 2 interrupt 0 Disable reset enable DE 1 1 Enable Voltage monitor 2 digital filter 0 Digital filter enabled mode disabled mode select Dn digital filter circuit enabled 1 Digital filter disabled mode digital filter circuit disabled Voltage change detection 0 Not detected flag 48 1 Vdet2 crossing detected WDT detection flag 0 Not detected an RW RW RW 1 Detected P Sampling clock select bits b5 b4 0 0 fRING S divided by 1 RW 0 1 fRING S divided by 2 1 0 fRING S divided by 4 RW 1 1 fRING S divided by 8 RW W VW2C6 Voltage monitor 2 circuit mode 0 Voltage monitor 2 interrupt mode select DI 1 Voltage monitor 2 reset mode Voltage monitor 2 interrupt 0 When VCC reaches Vdet2 or above reset generation condition 1 When VCC reaches Vdet2 or below R select bit NOTES iP Set the PRC bit in the PRCR register to 1 rewrite enable before writing to this register When rewriting the VW2C register the VW2C2 bit may be set to 1 Set the VW2C2 bit to 0 after rew riting the VW2C register When the voltage monitor 2 inter
32. e When flash memory access resulted in an error while erasing or programming in EWO mode FMROO bit not reset to 1 ready e When entering on chip oscillator mode main clock stops Figure 18 11 shows a flowchart of the steps to be followed before and after entering on chip oscillator mode main clock stop Note that when going to stop or wait mode while the CPU rewrite mode is disabled the FMRO register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode 18 4 2 5 FMRO0O6 Bit This is a read only bit indicating the status of an auto program operation The bit is set to 1 when a program error occurs otherwise it is set to 0 For details refer to the description in 18 4 5 Full Status Check 18 4 2 6 FMRO7 Bit This is a read only bit indicating the status of an auto erase operation The bit is set to 1 when an erase error occurs otherwise it is set to 0 Refer to 18 4 5 Full Status Check for details 18 4 2 7 FMR11 Bit Setting this bit to 1 EW1 mode places the MCU in EW1 mode 18 4 2 8 FMR15 Bit When the FMRO2 bit is set to 1 rewrite enabled and the FMR15 bit is set to 0 rewrite enabled block 0 accepts program and block erase commands 18 4 2 9 FMR16 Bit When the FMRO2 bit is set to 1 rewrite enabled and the FMR16 bit is set to 0 rewrite enabled block 1 accepts program and block erase commands Rev 1 30 De
33. lt 1 000 times Block erase time 0 3 s Program erase endurance gt 1 000 times td SR SUS Time Delay from suspend request until 97 CPUclock us suspend x 6 cycles Interval from erase start restart until 650 us following suspend request Interval from program start restart until 0 ns following suspend request Time from suspend until program erase 3 CPU clock us restart x 4 cycles Program erase voltage 2 7 5 5 V Read voltage 2 7 5 5 V Program erase temperature 20 8 85 C Data hold time 9 Ambient temperature 55 C 20 year NOTES 1 Vcc 2 7 to 5 5 V at Topr 20 to 85 C 40 to 85 C unless otherwise specified 2 Definition of programming erasure endurance The programming and erasure endurance is defined on a per block basis If the programming and erasure endurance is n n 100 or 10 000 each block can be erased n times For example if 1 024 1 byte writes are performed to block A a 1 Kbyte block and then the block is erased the programming erasure endurance still stands at one However the same address must not be programmed more than once per erase operation overwriting prohibited 3 Endurance to guarantee all electrical characteristics after program and erase 1 to Min value can be guaranteed 4 If emergency processing is required a suspend request can be generated independent of this characteristic In that case the normal
34. receive mode receive mode receive device in transmit mode is set to 0 receive device in transmit mode is set to 1 and continuous transfer is performed continuous transfer is halted request request arbitration lost overrun error interrupt request arbitration lost overrun error interrupt request error interrupt request error interrupt request R 3 Refer to 16 3 8 1 Accessing of Registers Associated with I C bus Interface for more information ICIER Register Dec 08 2006 Page 205 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface IC bus Status Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 00BCh 0000X000b SE General call address When the general call address is detected this flag ADZ A ES RW recognition flag is setto 1 Slave address recognition This flag is set to 1 when the first frame follow ing start condition matches bits SVAO to SVA6 in the SAR register in slave receive mode Detect the slave address and generate call address AAS Arbitration lost flag When the DC bus format is used this flag indicates overrun error flag that arbitration has been lost in master mode In the follow ing cases this flag is set to 1 e When the internal SDA signal and SDA pin level do not match at the rise of the SCL signal in master transmit mode e When the start condition is detected and the SDA pin is held H
35. the transfer is not possible yet the SCL signal goes L and the interface stands by Support for direct drive of pins SCL and SDA NMOS open drain output e Clock synchronous serial format Continuous transmit receive operation Because the shift register transmit data register and receive data register are independent I O pins SCL I O Serial clock I O pin SDA I O Serial data I O pin Transfer clock e When the MST bit in the ICCR1 register is set to 0 The external clock input from the SCL pin e When the MST bit in the ICCR1 register is set to 1 The internal clock selected by bits CKSO to CKS3 in the ICCR1 register output from the SCL pin Receive error detection e Overrun error detection clock synchronous serial format Indicates an overrun error during reception When the last bit of the next data item is received while the RDRF bit in the ICSR register is set to 1 data in the ICDRR register the AL bit is set to 1 Interrupt sources e EC bus format 6 sources 1 Transmit data empty including when slave address matches transmit ends receive data full including when slave address matches arbitration lost NACK detection and stop condition detection e Clock synchronous serial format 4 sources 1 Transmit data empty transmit ends receive data full and overrun error Select functions NOTE e 2C bus format Selectable output level for acknowledge signal during recep
36. transmission starts When the TIE bit in the SSER register is set to 1 the TXI interrupt request is generated When one frame of data is transferred while the TDRE bit is set to 0 data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started If the 8th bit is transmitted while the TDRE bit is set to 1 the TEND bit in the SSSR register is set to 1 the TDRE bit is set to 1 when the last bit of the transmit data is transmitted and the state is retained The TEI interrupt request is generated when the TEIE bit in the SSER register is set to 1 transmit end interrupt request enabled The SSCK pin is fixed H after transmit end Transmission cannot be performed while the ORER bit in the SSSR register is set to overrun error Confirm that the ORER bit is set to 0 before transmission Figure 16 14 shows a Sample Flowchart of Data Transmission Clock Synchronous Communication Mode e When SSUMS 0 clock synchronous communication mode CPHS 0 data change at odd numbers and CPOS 0 CH when clock stops sx Ode 1 frame 1 frame generation lt lt j N ee TDRE bit in nn peers SSSR register K TEI interrupt request TEND bit in TXI interrupt request generation SSSR register Processing by program Write data to SSTDR register Figure 16 13 Example of Clock Synchronous Serial I O with Chip Select Operation for Data Transmission Clock Synchronous Communication Mode Rev 1 30 Dec
37. 0049h 004Ah 004Bh 004Ch 004Dh Key Input Interrupt Control Register KUPIC XXXXX000D 004Eh A D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh SSU IIC Interrupt Control Register 2 SSUAIC IIC2AIC XXXXX000b 0050h Compare 1 Interrupt Control Register CMPTIC XXXXX000D 0051h UARTO Transmit Interrupt Control Register SOTIC XXXXX000b 0052h UARTO Receive Interrupt Control Register SORIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UARTT Receive Interrupt Control Register STRIC XXXXX000Dti C COd 0055h 0056h Timer X Interrupt Control Register TXIC XXXXX000D 0057h 0058h Timer Z Interrupt Control Register TZIC XXXXX000B ti C _COdS 0059h INT1 Interrupt Control Register INT1IC XXXXX000b 005Ah INT3 Interrupt Control Register INT3IC XXXXX000b 005Bh Timer C Interrupt Control Register TCIC XXXXX000b 005Ch Compare 0 Interrupt Control Register CMPOIC XXXXX000b ti CS Cd 005Dh INTO Interrupt Control Register INTOIC XX00X000b DOSEN 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h O006An 006Bh 006Ch 006Dh DOEN 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007An 007Bh 007Ch 007Dh DO ZER 007Fh X Undefined NOTES 1 The blank regions are reserved Do not access locations in these regions 2 Selected by the IICSEL bit in the PMR register
38. 08 2006 Page 185 0f315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Initialization Read TDRE bit in SSSR register Write transmit data to SSTDR register Data transmission continues Read TEND bit in SSSR register SSSR register TEND bit lt 0 SSER register TE bit lt 0 NOTE 1 Write 0 after reading 1 to set the TEND bit to 0 16 Clock Synchronous Serial Interface 1 After reading the SSSR register and confirming that the TDRE bit is set to 1 write the transmit data to the SSTDR register When the transmit data is written to the SSTDR register the TDRE bit is automatically set to 0 2 Determine whether data transmission continues 3 When data transmission is completed the TEND bit is set to 1 Set the TEND bit to 0 and the TE bit to 0 and complete transmit mode Figure 16 14 Sample Flowchart of Data Transmission Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 186 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 5 3 Data Reception Figure 16 15 shows an Example of Clock Synchronous Serial I O with Chip Select Operation for Data Reception Clock Synchronous Communication Mode During data reception clock synchronous serial I O with chip select operates as described below When clock synchronous serial I O with chip select is set as the master device it outputs a synchronous clock and inputs d
39. 1 Circuit Control Register VW1C 48 0079h 0037h Voltage Monitor 2 Circuit Control Register VW2C 49 007Ah 0038h 007Bh 0039h 007Ch 003Ah 007Dh 003Bh 007EN 003Ch 007Fh 003Dh 003Eh 003Fh NOTE 1 The blank regions are reserved Do not access locations in these regions Address Register Symbol Page 0080h Timer Z Mode Register TZMR 124 g 0081h Address Register Symbol Page 0082h 00COh A D Register AD 235 er DOC 0084h Timer Z Waveform Output Control Register PUM 126 90C2h 0085h Prescaler Z Register PREZ 125 00C3h 0086h Timer Z Secondary Register TZSC 125 00C4h 0087h Timer Z Primary Register TZPR 125 WOCH 0088h O00C6h nee DOC 008Ah Timer Z Output Control Register TZOC 126 90C8h 008Bh Timer X Mode Register TXMR T0 00C9h 008Ch Prescaler X Register PREX TH OOCAh 008Dh Timer X Register TX mm OOCBh DOSEN Timer Count Source Setting Register TCSS 111 127 00CCh 008Fh DCD 0090h Timer C Register TC 143 O0CEh SCT OOCFh 0092h KRIER 0093h 00Dih So 00D2h 0095h KRIER 0096h External I
40. 110 AN10 111 AN11 C Other than above Do not set H2 i 1 R A D input group select bit 0 Disabled ADGSELO 1 Enabled ANS to AN11 RW ADCAP A D conversion automatic 0 Starts at softw are trigger ADST bit RW start bit 1 Starts at capture requests timer Z interrupt A D conversion start flag 0 Disables A D conversion ADST fe Starts A D conversion Frequency select bit 0 When CKS1 in ADCON1 register 0 0 Selects f4 1 Selects f2 ES When CKS1 in ADCONt register 1 RW 0 Selects f1 1 fRING fast NOTES If the ADCONO register is rew ritten during A D conversion the conversion result is undefined Bits CHO to CH2 are enabled w hen the ADGSELO bit is set to 1 After changing the A D operating mode select the analog input pin again Set AD frequency to 10 MHz or below A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 00D7h 00h Bit Sybol Reserved bits Set to 0 Ces Frequency select bit 1 Refer to the description of the CKSO bit in the ADCONO register function Vref connect bit 1 Vref connected Reserved bits Set to 0 R b6 b7 f the ADCON1 register is rew ritten during A D conversion the conversion result is undefined Set the BITS bit to 0 8 bit mode in repeat mode When the VCUT bit is set to 1 connected from 0 not connected w ait for 1 us or more before starting A D conversion bi R I CSS BTS 8 10 bit mode select bit 0 8 bit mode an
41. 2006 Page 790f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 3 Special Interrupts Special interrupts are non maskable 12 1 3 1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer Reset the watchdog timer after the watchdog timer interrupt is generated For details refer to 13 Watchdog Timer 12 1 3 2 Oscillation Stop Detection Interrupt The oscillation stop detection interrupt is generated by the oscillation stop detection function For details of the oscillation stop detection function refer to 10 Clock Generation Circuit 12 1 3 3 Voltage Monitor 2 Interrupt The voltage monitor 2 interrupt is generated by the voltage detection circuit For details of the voltage detection circuit refer to 7 Voltage Detection Circuit 12 1 3 4 Single Step Interrupt and Address Break Interrupt Do not use these interrupts They are for use by development tools only 12 1 3 5 Address Match Interrupt The address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMADO to RMAD1 when the AIERO or AJER1 bit in the ATER register is set to 1 address match interrupt enable For details of the address match interrupt refer to 12 4 Address Match Interrupt 12 1 4 Peripheral Function Interrupt The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maska
42. 3 Functions to Prevent Rewriting of Flash Memory Rev 1 30 Dec 08 2006 Page 273 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 7 Notes on Flash Memory 18 7 1 CPU Rewrite Mode 18 7 1 1 Operating Speed Before entering CPU rewrite mode EWO mode select 5 MHz or below for the CPU clock using the CM06 bit in the CMO register and bits CM16 to CM17 in the CM1 register This does not apply to EW1 mode 18 7 1 2 Prohibited Instructions The following instructions cannot be used in EWO mode because they reference data in the flash memory UND INTO and BRK 18 7 1 3 Interrupts Table 18 9 lists the EWO Mode Interrupts and Table 18 10 lists the EW1 Mode Interrupts Table 18 9 EW Mode Interrupts When Watchdog Timer Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request is Acknowledged During auto erasure Any interrupt can be used Once an interrupt request is acknowledged by allocating a vector in auto programming or auto erasure is RAM forcibly stopped immediately and the flash memory is reset Interrupt handling starts after the fixed period and the flash memory restarts Since the block during auto erasure or the address during auto programming is forcibly stopped the Auto programming normal value may not be read Execute auto erasure again and ensure it completes normally Since the watchdog timer does not stop during the command operation interrupt requests may be
43. Address After Reset OOBOh 00h Bit Symbol UOIRS UARTO transmit interrupt 0 Transmit buffer empty TI 1 source select bit 1 Transmit completed TXEPT 1 ups UART1 transmit interrupt 0 Transmit buffer empty TI 1 RW source select bit 1 Transmit completed TXEPT 1 UORRM UARTO continuous receive 0 Disables continuous receive mode mode enable bit 1 Enables continuous receive mode Reserved bit Set to 0 b3 UART1 pin P3_7 TXD1 b5 b4 D RW RW RW P4_5 RXD1 select bits P3_7 P4_ W 0 1 P3_7 RXD1 10 Do not set 1 1 TXD1 RXD1 RW W RW R R Reserved bit Set to 0 b6 CNTPO signal pin select bit 0 P1_5 RXDO P1_7 CNTROO INT10 1 P1_5 RXDO CNTRO1 INT11 P1_7 NOTE 1 The CNTRSEL bit selects the input pin of the CNTRO INTI signal When the CNTRO signal is output it is output from the CNTROO pin regardless of the CNTRSEL bit setting Figure 15 6 Registers U0C1 to U1C1 and UCON Rev 1 30 Dec 08 2006 Page 157 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface 15 1 Clock Synchronous Serial UO Mode In clock synchronous serial I O mode data is transmitted and received using a transfer clock Table 15 1 lists the Clock Synchronous Serial I O Mode Specifications Table 15 2 lists the Registers Used and Settings in Clock Synchronous Serial I O Modell Table 15 1 Clock Synchronous Serial UO Mode Specifications Item Specification Transfer d
44. An example of waiting four cycles or more Program example BCLR 4 00BBh Disable transmission JMP B NEXT NEXT BSET 3 00BBh Enable reception 20 5 1 2 Selecting SSI Signal Pin Set the SOOS bit in the SSMR2 register to 0 CMOS output in the following settings e SSUMS bit in SSMR2 register 1 4 wire bus communication mode e BIDE bit in SSMR2 register 0 standard mode e MSS bit in SSCRH register 0 operate as slave device e SSISEL bit in PMR register 1 use P1_6 pin for SSIO1 pin Do not use the SSIO1 pin with NMOS open drain output for the above settings Rev 1 30 Dec 08 2006 Page 303 of 315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 5 2 Notes on I2C bus Interface Set the IICSEL bit in the PMR register to 1 select I2C bus interface function to use the DC bus interface 20 5 2 1 Accessing of Registers Associated with 12C bus Interface Wait for three instructions or more or four cycles or more after writing to the same register among the registers associated with the DC bus Interface 00B8h to OOBFh before reading it e An example of waiting three instructions or more Program example MOV B 00h 00BBh _ Set ICIER register to 00h NOP NOP NOP MOV B OOBBh ROL e An example of waiting four cycles or more Program example BCLR 6 00BBh Disable transmit end interrupt request JMP B NEXT NEXT BSET 7 00BBh Enable transmit data empty interrupt request Rev 1 30 Dec 08 2006 P
45. D Register b15 b7 Address After Reset 00C1h 00COh Undefined When BITS bit in ADCON1 register is set to 1 When BITS bit in ADCON1 register is set to 0 10 bit mode 8 bit mode 8 low order bits in A D conversion result A D conversion result ml 2 high order bits in A D conversion result When read the content is undefined ml Nothing is assigned If necessary set to 0 When read the content is 0 Figure 17 3 Registers ADCON2 and AD Rev 1 30 Dec 08 2006 Page 235 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 1 One Shot Mode 17 A D Converter In one shot mode the input voltage of one selected pin is A D converted once Table 17 2 lists the One Shot Mode Specifications Figure 17 4 shows Registers ADCONO and ADCONT in One shot Mode Table 17 2 One Shot Mode Specifications Specification Function The input voltage of one pin selected by bits CH2 to CHO is A D converted once Start conditions e When the ADCAP bit is set to 0 software trigger set the ADST bit to 1 A D conversion starts e When the ADCAP bit is set to 1 capture timer Z interrupt request is generated while the ADST bit is set to 1 Stop conditions e A D conversion completes when the ADCAP bit is set to 0 software trigger ADST bit is set to 0 e Set the ADST bit to 0 Interrupt request generation timing A D conversion completes Input pin Select one of AN8 to AN11 Reading
46. Group R8C 1B Group 2 Central Processing Unit CPU 2 1 Data Registers RO R1 R2 and R3 RO is a 16 bit register for transfer arithmetic and logic operations The same applies to R1 to R3 RO can be split into high order bits ROH and low order bits ROL to be used separately as 8 bit data registers R1H and R1L are analogous to ROH and ROL R2 can be combined with RO and used as a 32 bit data register R2RO R3R1 is analogous to R2R0 2 2 Address Registers A0 and A1 AO is a 16 bit register for address register indirect addressing and address register relative addressing It is also used for transfer and arithmetic and logic operations A1 is analogous to AO A1 can be combined with AO and used as a 32 bit address register A1A0 2 3 Frame Base Register FB FB is a 16 bit register for FB relative addressing 2 4 Interrupt Table Register INTB INTB is a 20 bit register that indicates the start address of an interrupt vector table 2 5 Program Counter PC PC is 20 bits wide indicates the address of the next instruction to be executed 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP The stack pointer SP USP and ISP are each 16 bits wide The U flag of FLG is used to switch between USP and ISP 2 7 Static Base Register SB SB is a 16 bit register for SB relative addressing 2 8 Flag Register FLG FLG is an 11 bit register indicating the CPU state 2 8 1 Carry Flag C The C flag reta
47. INTO interrupt is generated by an INTO input When using the INTO interrupt the INTOEN bit in the INTEN register is set to 1 enable The edge polarity is selected using the INTOPL bit in the INTEN register and the POL bit in the INTOIC register Inputs can be passed through a digital filter with three different sampling clocks The INTO pin is shared with the external trigger input pin of timer Z Figure 12 11 shows Registers INTEN and INTOF External Input Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Address After Reset 0096h 00h Bi Symbol INTO input enable bit o Disable INTO input polarity select bit 2 Ong edge Reserved bits Set to 0 NOTES Set the INTOEN bit while the INOSTG bit in the PUM register is set to 0 one shot trigger disabled When setting the INTOPL bit to 1 both edges set the POL bit in the INTOIC register to 0 selects falling edge The IR bit in the INTOIC register may be set to 1 requests interrupt when the INTOPL bit is rewritten Refer to 12 5 5 Changing Interrupt Sources INTO Input Filter Select Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 001Eh 00h No filter Filter with f1 sampling Filter w ith f8 sampling Filter w ith 82 sampling Reserved bit Set to 0 Nothing is assigned If necessary set to 0 b7 b3 When read the content is 0 Figure 12 11 Registers INTEN and INTOF Rev 1 30 Dec 08 2006 Page910f315 RENESAS REJ09B0252 0130 R8C
48. P4_6 P4_7 P4_6 and P4_7 can be used as input ports 5 When entering stop mode from high or medium speed mode the CMO6 bit is set to 1 divide by 8 mode Figure 10 2 CMO Register Rev 1 30 Dec 08 2006 Page 60 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit System Clock Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0007h 20h Bi Syro M1 All clock stop control DI 78 0 Clock operates RW 1 Stops all clocks stop mode Reserved bit Set to 0 b1 Reserved bit Set to 0 b2 8 M Port XIN XOUT sw itch bit 0 Input port P4_6 P4_7 Gils 1 XIN XOUT Pin CM14 Low speed on chip oscillation stop 0 Low speed on chip oscillator on DIS 1 Low speed on chip oscillator off i i it Io earls XIN XOUT drive capacity select bit SE an System clock division select bits 1 b7 b6 CM16 0 0 No division mode pone 0 1 Divide by 2 mode 1 0 Divide by 4 mode 1 1 Divide by 16 mode NOTES Set the PRCO bit in the PRCR register to 1 w rite enable before rew riting the CM1 register When entering stop mode from high or medium speed mode this bit is set to 1 drive capacity high When the CM06 bit is set to 0 bits CM16 CM17 enabled bits CM16 to CM17 are enabled _ If the CM10 bit is set to 1 stop mode the on chip feedback resistor is disabled When the OCD2 bit is set to 0 main clock selected the CM14 bit is set to 1 low s
49. PM1 register to 1 The watchdog timer is reset when watchdog timer underflows e The following conditions apply in count source protection mode Writing to the CM10 bit in the CM1 register is disabled It remains unchanged even if it is set to 1 The MCU does not enter stop mode Writing to the CM14 bit in the CM1 register is disabled It remains unchanged even if it is set to 1 The low speed on chip oscillator does not stop NOTES 1 The WDTON bit cannot be changed by a program To set the WDTON bit write 0 to bit 0 of address OFFFFh with a flash programmer 2 Even if 0 is written to the CSPROINI bit in the OFS register the CSPRO bit is set to 1 The CSPROINI bit cannot be changed by a program To set the CSPROINI bit write 0 to bit 7 of address OFFFFh with a flash programmer Rev 1 30 Dec 08 2006 Page 107 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 Timers The MCU has two 8 bit timers with 8 bit prescalers and a 16 bit timer The two 8 bit timers with 8 bit prescalers are timer X and timer Z These timers contain a reload register to store the default value of the counter The 16 bit timer is timer C and has input capture and output compare functions All the timers operate independently The count source for each timer is the operating clock that regulates the timing of timer operations such as counting and reloading Table 14 1 lists Functional Comparison of Timers Ta
50. RW RW RW RW W Figure 17 5 Registers ADCONO and ADCON1 in Repeat Mode Rev 1 30 Dec 08 2006 Page 239 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter 17 3 Sample and Hold When the SMP bit in the ADCON2 register is set to 1 sample and hold function enabled the A D conversion rate per pin increases to 28 AD cycles for 8 bit resolution or 33 AD cycles for 10 bit resolution The sample and hold function is available in all operating modes Start A D conversion after selecting whether the sample and hold circuit is to be used or not When performing A D conversion charge the comparator capacitor in the MCU during the sampling time Figure 17 6 shows a Timing Diagram of A D Conversion Sample and Hold disabled Conversion time of 1st bit 2nd bit Sampling time Comparison Sampling time Comparison Sampling time Comparison 4 AD cycles time 2 50 AD cycles time 2 59 AD cycles time d Repeat until conversion ends Sample and Hold enabled Conversion time of 1st bit Sampling time Comparison Comparison Comparison Comparison 4 AD cycles time time time l gt L Figure 17 6 Timing Diagram of A D Conversion 17 4 A D Conversion Cycles Figure 17 7 shows the A D Conversion Cycles Conversion time 2nd and End of following bits qbrocessing t Conversion Sampling Comparison Sampling Comparison End AD Conversion Moge Time Time Time Processing Conversion
51. Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office
52. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document including but not limited to product data diagrams charts programs algorithms and application circuit examples You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use When exporting the products or technology described herein you should follow the applicable export control laws and regulations and procedures required by such laws and regulations All information included in this document such as product data diagrams charts programs algorithms and application circuit examples is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas products listed in this document please confirm the latest product information with a Renesas sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website http www renesas com Renesas has used reasonable care in compiling the information included in this document but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the inf
53. TCC04 TCC06 or TCCO7 bit is rewritten Refer to 12 5 5 Changing Interrupt Sources When the TCC13 bit is set to 1 output compare mode and INTS interrupt is input regardless of the setting value of the TCC06 bit an interrupt request is generated When using the INTS filter the INTS interrupt is generated in synchronization w ith the clock for the digital filter Figure 14 27 TCCO Register Rev 1 30 Dec 08 2006 Page 144 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer C Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 009Bh 00h No filter Filter with f1 sampling Filter w ith f8 sampling Filter w ith 32 sampling Timer C counter reload select 0 No reload bit Set TC register to 0000h when compare 1 is matched Compare 0 capture select Selects capture input capture mode bit Selects compare 0 output output compare mode Compare 0 output mode select bits CMP output remains unchanged even w hen compare 0 is matched CMP output is inverted w hen compare 0 signal is matched CMP output is set to L w hen compare 0 signal is matched CMP output is set to H when compare 0 signal is matched Compare 1 output mode select bits CMP output remains unchanged even when compare 1 is matched CMP output is inverted w hen compare 1 signal is matched CMP output is set to L when compare 1 signal is matched CMP
54. TXMR Register in Event Counter Mode Rev 1 30 Dec 08 2006 Page 1150f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 1 4 Pulse Width Measurement Mode In pulse width measurement mode the pulse width of an external signal input to the INT1 CNTRO pin is measured refer to Table 14 5 Pulse Width Measurement Mode Specifications Figure 14 7 shows the TXMR Register in Pulse Width Measurement Mode Figure 14 8 shows an Operating Example in Pulse Width Measurement Mode Table 14 5 Item Pulse Width Measurement Mode Specifications Specification Count sources f1 f2 8 fRING Count operations e Decrement e Continuously counts the selected signal only when the measured pulse is H level or conversely only L level e When the timer underflows the contents of the reload register are reloaded and the count is continued Count start condition 1 count starts is written to the TXS bit in the TXMR register Count stop condition 0 count stops is written to the TXS bit in the TXMR register Interrupt request generation timing e When timer X underflows timer X interrupt e Rising or falling of the CNTRO input end of measurement period INT1 interrupt INT10 CNTROO INT11 CNTRO1 pin functions Measured pulse input INT1 interrupt input CNTRO pin function Programmable I O port Read from timer The count value can be read out by reading re
55. Table 19 25 TCIN Input INT3 Input Symbol Parameter Standard Min tc TCIN TCIN input cycle time 1 20001 tWH TCIN TCIN input H width 600 2 tWL TCIN NOTES TCIN input L width 600 2 1 When using the timer C input capture mode adjust the cycle time to 1 timer C count source frequency x 3 or above 2 When using the timer C input capture mode adjust the width to 1 timer C count source frequency x 1 5 or above TCIN input Figure 19 15 TCIN Input INT3 Input Timing Diagram when Vcc 3 V Rev 1 30 Dec 08 2006 Page 294 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 26 Serial Interface Standard Min Max tc CK CLKi input cycle time 300 tw CKH CLKi input H width 150 tw CKL CLKi input L width 150 ta C Q TXDi output delay time th C Q TXDi hold time 0 tsu D C RXDi input setup time 70 th C D RXDi input hold time 90 i Oor1 Symbol Parameter Figure 19 16 Serial Interface Timing Diagram when Vcc 3 V Table 19 27 External Interrupt INTO Input Standard l P t Unit Symbo arameter Min Max tW INH INTO input H width 3801 ns WOU INTO input L width 380 2 ns NOTES 1 When selecting the digital filter by the INTO input filter select bit use an INTO input HIGH width of either 1 di
56. Timers Prescaler X Register b7 Address After Reset 008Ch Counts internal count source 00h to FFh Pulse output mode Counts internal count source 00h to FFh Counts input pul f I clock Measures pulse w idth of input pulses from Pulse width external clock counts internal count measurement mode source Measures pulse period of input pulses from external clock counts internal count source Pulse period measurement mode Timer X Register Address After Reset 008Dh FFh Function Setting Range Counts underflow of prescaler X 00h to EEN Timer Count Source Setting Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 008Eh 00h RW 11 f2 Reserved bits Set to 0 KE RW 1 Do not switch count sources during a count operation Stop the timer count before switching count sources Figure 14 3 Registers PREX TX and TCSS Rev 1 30 Dec 08 2006 Page 111 0f315 pLeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 1 1 14 Timers Timer Mode In timer mode the timer counts an internally generated count source refer to Table 14 2 Timer Mode Specifications Figure 14 4 shows the TXMR Register in Timer Mode Table 14 2 Item Timer Mode Specifications Specification Count sources f1 f2 f8 fRING Count operations e Decrement e When the timer underflows the contents of the reload register are reloaded and the count is continued 1 n 1 m 1 n value set
57. U1RB 00A Fh 00A Eh Undefined SE Function Receive data D7 to DO b7 t b0 el See 8 sl Nothing is assigned If necessary set to 0 b11 b9 When read the content is undefined Overrun error flag 8 No overrun error Overrun error Framing error flag i No framing error Framing error oan Parity error flag 0 No parity error ml 1 Parity error Error sum flag 0 No error NOTES 1 Read out the UiRB register in 16 bit units 2 Bits SUM PER FER and OER are set to 0 no error when bits SMD2 to SMDO in the UiMR register are set to 000b serial interface disabled or the RE bit in the UiC1 register is set to 0 receive disabled The SUM bit is set to 0 no error when bits PER FER and OER are set to 0 no error Bits PER and FER are set to 0 even when the higher byte of the UIRB register is read out Also bits PER and FER are set to 0 when reading the high order byte of the UiRB register UARTIi Bit Rate Register i 0 or 1 2 3 b7 b0 Address After Reset 00A 1h Undefined 00A9h Undefined Assuming the set value is n UIBRG divides the count source by n 1 00h to FFh NOTES 1 Write to this register while the serial VO is neither transmitting nor receiving 2 Use the MOV instruction to write to this register 3 After setting the CLKO to CLK1 bits of the UiCO register write to the UiBRG register Figure 15 3 Registers UOTB to U1TB UORB to U1RB and UOBRG to U1BRG Rev 1 30 Dec 08 2006 Pag
58. V to the VSS pin RESET Reset input Reset input pin P4_6 XIN P4_6 input clock input Connect a ceramic resonator or crystal oscillator between pins XIN and XOUT P4_7 XOUT P4_7 input clock output AVCC AVSS Analog power supply input Connect AVSS to VSS and AVCC to VCC respectively P1_0 to P1_7 Input port P1 Input H or L level signal or leave the pin open P3_3 to P3_5 Input port P3 Input H or L level signal or leave the pin open P4_2 VREF Input port P4 Input H or L level signal or leave the pin open MODE MODE Input L P3_7 TXD output Serial data output pin P45 RXD input Serial data input pin Rev 1 30 Dec 08 2006 Page 269 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Table 18 8 Pin 18 Flash Memory Pin Functions Flash Memory Standard Serial I O Mode 3 Name Description VCC VSS Power input Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin RESET Reset input Reset input pin P4_6 XIN P4_6 input clock input P4_7 XOUT P4_7 input clock output Connect a ceramic resonator or crystal oscillator between pins XIN and XOUT when connecting external oscillator Apply H and L or leave the pin open when using as input port AVCC AVSS Analog power supply input Connect AVSS to VSS and AVCC to VCC respectively P1
59. bit Figure 14 12 TZMR Register Rev 1 30 Dec 08 2006 Page 124 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Prescaler Z Register Symbol Address After Reset PREZ 0085h de FFh Setting Range Counts internal count source or timer X 00h to FFh RW underflow s Programmable w aveform Counts internal count source or timer X 00h to FFh RW generation mode underflow s Programmable one shot Counts internal count source or timer X 00h to FFh RW generation mode underflow s Programmable w ait one shot Counts internal count source or timer X 00h to FFh RW generation mode underflow s Timer Z Secondary Register Timer mo Address After Reset 0086h FFh C we J o e Disabled Programmable waveform Counts underflow of prescaler Z 00h to FFh woe generation mode Programmable one shot Disabled generation mode Programmable w ait one shot Counts underflow of prescaler Z counts one 00h to FEN wo generation mode shot w idth NOTES 1 Each value in the TZPR register and TZSC register is reloaded to the counter alternately and counted 2 The count value can be read out by reading the TZPR register even w hen the secondary period is being counted Timer Z Primary Register b7 A Address After Reset 0087h FFh Seting Range Counts underflow s of prescaler Z 00h to EEN Programmable waveform Counts underflow s of prescaler Zu 00h to FFh RW generation mode Programmable on
60. bit in ICSR register No Yes Read ICDRR register OCH register RCVD bit 0 ICCR1 register MST bit lt 0 End NOTES 1 Do not generate the interrupt while processing steps 1 to 3 2 When receiving 1 byte skip steps 2 to 6 after 1 and jump to process of step 7 Processing step 8 is dummy read of the ICDRR register Figure 16 47 Example of Register Setting in Master Receive Mode ZC bus Interface Mode Rev 1 30 Dec 08 2006 Page 228 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group IESSE ICSR register AAS bit 0 Write transmit data to ICDRT register f Read TDRE bit in ICSR register Yes Y es Write transmit data to ICDRT register Read TEND bit in ICSR register ICSR register TEND bit lt 0 ICCR1 register TRS bit lt 0 Dummy read in ICDRR register ICSR register TDRE bit lt 0 16 Clock Synchronous Serial Interface 1 Set the AAS bit to 0 2 Set the transmit data except the last byte 3 Wait until the ICRDT register is empty 4 Set the transmit data of the last byte 5 Wait until the last byte is transmitted 6 Set the TEND bit to 0 7 Set to slave receive mode 8 Dummy read the ICDRR register to release the SCL signal 9 Set the TDRE bit to 0 Figure 16 48 Example of Register Setting in Slave Transmit Mode ZC bus Interface Mode Rev 1 30 Dec 08 2006 Page 229 of 315 spRENESAS REJ09B0252 0
61. bit in the INTEN register is set to 0 one edge Figure 14 21 Registers TZMR and PUM in Programmable Wait One Shot Generation Mode Rev 1 30 Dec 08 2006 Page 138 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Set to 1 by program D eg TZS bit in TZMR register Set to 1 by program or set to 1 by INTO pin Set to 0 when input trigger counting ends TZOS bit in TZOC 1 register 0 A Count source Prescaler Z underflow toa signal SE INTO pin input E Timer Z secondar Timer Z primar Count s starts I p e reloads enge CECR ENER E Set to 0 when interrupt Ee is accepted or set by program IR bit in TZIC register i i Set to 0 by program TZOPLbitinPUM 4 l i register 0 i Wait starts Waveform output starts Waveform output ends Y TZOUT pin output a The above applies under the following conditions PREZ 01h TZPR 01h TZSC 02h PUM register TZOPL bit 0 INOSTG bit 1 INTO one shot trigger enabled INOSEG bit 1 edge trigger at rising edge Figure 14 22 Operating Example in Programmable Wait One Shot Generation Mode Rev 1 30 Dec 08 2006 Page 139 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 2 5 Notes on Timer Z e Timer Z stops counting after a reset Set the values in the timer and prescaler before the count starts e Even if the prescaler and timer are read out in 16 bit units these registe
62. chip oscillator varies depending on the supply voltage and the operating ambient temperature Application products must be designed with sufficient margin to allow for the frequency changes 10 2 2 High Speed On Chip Oscillator Clock The clock generated by the high speed on chip oscillator is used as the clock source for the CPU clock peripheral function clock fRING fRING128 and fRING1 fast After reset the on chip oscillator clock generated by the high speed on chip oscillator stops Oscillation is started by setting the HRAOO bit in the HRAO register to 1 high speed on chip oscillator on The frequency can be adjusted by registers HRA1 and HRA2 Since there are differences in delay among the bits in the HRAI register make adjustments by changing the settings of individual bits The high speed on chip oscillator frequency may be changed in flash memory CPU rewrite mode during auto program operation or auto erase operation Refer to 10 6 5 High Speed On Chip Oscillator Clock for details Rev 1 30 Dec 08 2006 Page 66 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 3 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions Refer to Figure 10 1 Clock Generation Circuit 10 3 1 System Clock The system clock is the clock source for the CPU and peripheral function clocks Either the main clock
63. communication mode e BIDE bit in SSMR2 register 0 standard mode e MSS bit in SSCRH register 0 operate as slave device e SSISEL bit in PMR register 1 use PI pin for SSIO1 pin Do not use the SSIO1 pin with NMOS open drain output for the above settings Rev 1 30 Dec 08 2006 Page 198 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 12C bus Interface The I C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips DC bus Table 16 5 lists the IC bus interface Specifications Figure 16 22 shows a Block Diagram of DC bus interface and Figure 16 23 shows the External Circuit Connection Example of Pins SCL and SDA Figures 16 24 to 16 31 show the registers associated with the I2C bus interface DC bus is a trademark of Koninklijke Philips Electronics N V Table 16 5 12C bus interface Specifications Hem Specification Communication formats e 12C bus format Selectable as master slave device Continuous transmit receive operation Because the shift register transmit data register and receive data register are independent Start stop conditions are automatically generated in master mode Automatic loading of acknowledge bit during transmission Bit synchronization wait function In master mode the state of the SCL signal is monitored per bit and the timing is synchronized automatically If
64. count source input and the count re starts at the third count source input When the TZWC bit is set to 1 writing to only the reload register the value is written to each reload register of registers TZPR and PREZ the data is transferred to the counter at the following reload NOTE 1 The IR bit in the TZIC register is set to 1 interrupt requested when writing to the TZPR or PREZ register while both of the following conditions are met e TZWC bit in TZMR register is set to 0 write to reload register and counter simultaneously e TZS bit in TZMR register is set to 1 count starts Disable interrupts before writing to the TZPR or PREZ register in the above state Rev 1 30 Dec 08 2006 Page 128 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0080h 00h SE Reserved bits Set to 0 bis i S Hiem Le bits 00 Timer mode PW Timer Z write control bit 0 Write to reload register and counter TZWG dl Write to reload register only Timer Z count start flag 0 Stops counting TZS 1 Starts counting RW NOTES 1 When the TZS bit is set to 1 count starts the setting value in the TZWC bit is enabled When the TZWC bit is set to 0 timer Z count value is written to both reload register and counter Timer Z count value is written to the reload register only when the TZWC bit is set t
65. enable before rew riting to this register The OCD2 bit is automatically set to 1 on chip oscillator clock selected if a main clock oscillation stop is detected while bits OCD1 to OCDO are set to 11b oscillation stop detection function enabled If the OCDS bit is set to 1 main clock stops the OCD2 bit remains unchanged even when set to 0 main clock selected The OCD3 bit is enabled w hen bits OCD1 to OCDO are set to 11b oscillation stop detection function enabled Set bits OCD1 to OCDO to 00b oscillation stop detection function disabled before entering stop or on chip oscillator mode main clock stops The OCD3 bit remains 0 main clock oscillates if bits OCD1 to OCDO are set to 00b The CM14 bit is set to 0 low speed on chip oscillator on if the OCD2 bit is set to 1 on chip oscillator clock selected Refer to Figure 10 8 Switching Clock Source from Low speed On Chip Oscillator to Main Clock for the switching procedure w hen the main clock re oscillates after detecting an oscillation stop Figure 10 4 OCD Register Rev 1 30 Dec 08 2006 Page 620f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit High Speed On Chip Oscillator Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0020h 00h Bit Symbol HRAOO High speed on chip oscillator enable H High speed on chip oscillator off bit High speed on chip oscillator on HRAO1 High speed on c
66. equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under c
67. erase command during program suspend Figure 18 14 shows the Block Erase Command When Erase Suspend Function Disabled Figure 18 15 shows the Block Erase Command When Erase Suspend Function Enabled In EW1 mode do not execute this command for any address to which a rewrite control program is allocated In EWO mode the MCU enters read status register mode at the same time auto erasure starts and the status register can be read The status register bit 7 SR7 is set to 0 at the same time auto erasure starts and set back to 1 when auto erasure completes In this case the MCU remains in read status register mode until the next read array command is written Write the command code 20h Write DOh to a given block address Full status check Block erase completed Figure 18 14 Block Erase Command When Erase Suspend Function Disabled Rev 1 30 Dec 08 2006 Page 264 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Maskable interrupt 2 1 enable interrupt i FMR40 1 Yes FMR46 0 e Write the command code 20h Yes i Write DOh to any block address Access flash memory Access flash memory FMR41 0 Full status check Maskable interrupt 1 enable interrupt Access flash memory d FMR40 1 Write the command code 20h Write DOh to any block address FMR41 0
68. external clock uoco CLK1 to CLKO Select the count source in the UOBRG register TXEPT Transmit register empty flag NCH Select TXDO pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first TE Set this bit to 1 to enable transmission reception TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag NOTE UOIRS Select the UARTO transmit interrupt source UORRM Set this bit to 1 to use continuous receive mode CNTRSEL Set this bit to 1 to select P1_5 RXDO CNTRO1 INT11 1 Set bits which are not in this table to 0 when writing to the above registers in clock synchronous serial I O mode Table 15 3 lists the I O Pin Functions in Clock Synchronous Serial I O Mode The TXDO pin outputs H level between the operating mode selection of UARTO and transfer start If the NCH bit is set to 1 N channel open drain output this pin is in a high impedance state Table 15 3 Pin Name UO Pin Functions in Clock Synchronous Serial UO Mode Function Selection Method TXDO P1_4 Output serial data Outputs dummy data when performing reception only RXDO P1_5 Input serial data PD1_5 bit in PD1 register 0 P1_5 can be used as an input port when performing transmission only CLKO P1_6 Output transfer clock CKDIR bit in
69. functions using these clocks continue operating 10 4 2 1 Peripheral Function Clock Stop Function If the CMO2 bit is set to 1 peripheral function clock stops in wait mode the f1 f2 f4 f8 and 32 clocks stop in wait mode This reduces power consumption 10 4 2 2 Entering Wait Mode The MCU enters wait mode when the WAIT instruction is executed 10 4 2 3 Pin Status in Wait Mode The status before wait mode was entered is maintained Rev 1 30 Dec 08 2006 Page 69 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 4 2 4 Exiting Wait Mode The MCU exits wait mode by a hardware reset or a peripheral function interrupt To use a hardware reset to exit wait mode set bits ILVL2 to ILVLO for the peripheral function interrupts to 000b interrupts disabled before executing the WAIT instruction 10 Clock Generation Circuit The peripheral function interrupts are affected by the CM02 bit When the CM02 bit is set to 0 peripheral function clock does not stop in wait mode all peripheral function interrupts can be used to exit wait mode When the CMO02 bit is set to 1 peripheral function clock stops in wait mode the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals can be used to exit wait mode Table 10 3 lists Interrupts to Exit Wait Mode and Usage Conditions Table 10 3 Interrupt CMO02 0 Interrupts to Exit Wait Mode a
70. generated Reset the watchdog timer regularly When Maskable Interrupt Request is Acknowledged Status NOTES 1 Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 Rev 1 30 Dec 08 2006 Page 274 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Status Table 18 10 EW1 Mode Interrupts When Maskable Interrupt Request is Acknowledged 18 Flash Memory When Watchdog Timer Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request is Acknowledged During auto erasure erase Suspend function enabled Auto erasure is suspended after td SR SUS and interrupt handling is executed Auto erasure can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after interrupt handling completes During auto erasure erase suspend function disabled Auto erasure has priority and the interrupt request acknowledgement is put on standby Interrupt handling is executed after auto erasure completes During auto programming program suspend function enabled Auto programming is suspended after td SR SUS and interrupt handling is executed Auto programming can be restarted by setting the FMR42 bit in the FMR4 register to 0
71. hen the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources This bit is used to select the polarity of INT interrupt in timer mode Refer to 14 1 6 Notes on Timer X for precautions regarding the TXS bit Figure 14 4 TXMR Register in Timer Mode Rev 1 30 Dec 08 2006 Page 1120f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 1 2 Pulse Output Mode In pulse output mode the internally generated count source is counted and a pulse with inverted polarity is output from the CNTRO pin each time the timer underflows refer to Table 14 3 Pulse Output Mode Specifications Figure 14 5 shows the TXMR Register in Pulse Output Mode Table 14 3 Item Pulse Output Mode Specifications Specification Count sources f1 f2 f8 fRING Count operations e Decrement e When the timer underflows the contents of the reload register are reloaded and the count is continued Divide ratio 1 n 1 m 1 n value set in PREX register m value set in TX register Count start condition 1 count starts is written to the TXS bit in the TXMR register Count stop condition 0 count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows timer X interrupt INT10 CNTROO pin function Pulse output CNTRO pin function Programmable I O port or inverted output of CNTRO Read from timer The c
72. in SSSR register 4 When the data transmission is completed the Yes SSSR register TEND bit lt 0 5 Set the TEND bit to 0 6 and bits RE and TE in the SSER register to 0 before ending transmit receive mode SSER register RE bit 0 TE bit lt lt 0 NOTE 1 Write 0 after reading 1 to set the TEND bit to 0 Figure 16 17 Sample Flowchart of Data Transmission Reception Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 190 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 6 Operation in 4 Wire Bus Communication Mode In 4 wire bus communication mode a 4 wire bus consisting of a clock line a data input line a data output line and a chip select line is used for communication This mode includes bidirectional mode in which the data input line and data output line function as a single pin The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the BIDE bit in the SSMR2 register For details refer to 16 2 2 1 Association between Data I O Pins and SS Shift Register In this mode clock polarity phase and data settings are performed by bits CPOS and CPHS in the SSMR register For details refer to 16 2 1 1 Association between Transfer Clock Polarity Phase and Data When this MCU is set as the master device the chip select line controls output When clock synchronous serial T O with chip selec
73. is set to 1 the INT11 pin becomes the INT 1 input pin The INT 10 pin is shared with the CNTROO pin and the INT11 pin is shared with the CNTRO1 pin Figure 12 14 shows the TXMR Register when INT Interrupt is Used Timer X Mode Register b7 b6 b5 b4 b3 b2 b1 bO Address After Reset 008Bh 00h b1 b0 0 0 Timer mode or pulse period measurement mode 1 Do not set 1 0 Event count mode 1 Pulse w idth measurement mode e 1 CNTRO polarity sw itch Si d i edge veer X count start flag 0 oa counting 1 Starts counting TXOCNT P3_7 CNTRO select bit Function varies depending on operating mode Operating mode select 0 Other than pulse period measurement mode TXMOD2_ bit 2 1 Pulse period measurement mode Active edge reception flag Function varies depending on operating mode ND Timer X underflow flag Function varies depending on operating mode NOTES 1 When using INT interrupt select modes other than pulse output mode 2 The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources 3 Refer to 14 1 6 Notes on Timer X for precautions regarding the TXS bit Figure 12 14 TXMR Register when INT1 Interrupt is Used Rev 1 30 Dec 08 2006 Page 93 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 2 4 INT3 Interrupt The INT3 interrupt is generated by an INT3 input Set the TCCO7 bit in the
74. of standard whichever is greater Figure 19 12 External Interrupt INTO Input Timing Diagram when Vcc 5 V Rev 1 30 Dec 08 2006 Page 291 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Table 19 21 Parameter Electrical Characteristics 3 Vcc 3V Condition 19 Electrical Characteristics Standard Min Typ Output H voltage Except Sou lOH 1 mA Vcc 0 5 XOUT Drive capacity HIGH loH 0 1 mA Vcc 0 5 Drive capacity LOW loH 50 pA Vcc 0 5 Output L voltage Except P1_0 to P1_3 XouT lo 1mA P1_0toP1_3 Drive capacity HIGH loL 2 mA Drive capacity LOW loL 1 mA Drive capacity HIGH Jo 0 1 mA Drive capacity LOW o 50 pA Hysteresis INTO INTI INTS KIO KI1 KI2 KI3 CNTRO CNTR1 TCIN RXDO RESET IIH Input H current liL Input L current RPULLUP Pull up resistance Dro Feedback resistance XIN fRING S Low speed on c hip oscillator frequency VRAM NOTE RAM hold voltage During stop mode 1 Vcc 2 7 to 3 3 V at Topr 20 to 85 C 40 to 85 C f XIN 10 MHz unless otherwise specified Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 292 of 315 stENESAS R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 22 Electrical Characterist
75. of the next data Select functions e CLK polarity selection Transfer data input output can be selected to occur synchronously with the rising or the falling edge of the transfer clock e LSB first MSB first selection Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected e Continuous receive mode selection Receive is enabled immediately by reading the UORB register NOTES 1 If an external clock is selected ensure that the external clock is H when the CKPOL bit in the U0CO register is set to 0 transmit data output at falling edge and receive data input at rising edge of transfer clock and that the external clock is L when the CKPOL bit is set to 1 transmit data output at rising edge and receive data input at falling edge of transfer clock 2 If an overrun error occurs the receive data b0 to b8 of the UORB register will be undefined The IR bit in the SORIC register remains unchanged Rev 1 30 Dec 08 2006 Page 158 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface Table 15 2 Register Bit Registers Used and Settings in Clock Synchronous Serial I O Mode Function UOTB 0to7 Set data transmission UORB O0to7 Data reception can be read OER Overrun error flag UOBRG O0to7 Set bit rate UOMR SMD2 to SMDO Set to 001b CKDIR Select the internal clock or
76. or auto erasure is forcibly stopped immediately and the flash memory is reset Interrupt handling starts after the fixed period and the flash memory restarts Since the block during auto erasure or the address during auto programming is forcibly stopped the normal value may not be read Execute auto erasure again and ensure it completes normally Since the watchdog timer does not stop during the command operation interrupt requests may be generated Reset the watchdog timer regularly using the erase suspend function NOTES 1 Do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 20 7 1 4 How to Access Write 0 before writing 1 when setting the FMRO1 FMRO2 or FMR11 bit to 1 Do not generate an interrupt between writing 0 and 1 20 7 1 5 Rewriting User ROM Area In EWO Mode if the supply voltage drops while rewriting any block in which a rewrite control program is stored it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly In this case use standard serial I O mode 20 7 1 6 Program Do not write additions to the already programmed address 20 7 1 7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase suspend
77. oscillator on fRING and fRING128 can be used as timers X and C When the HRAO0 bit is set to 1 fRING fast can be used as timer C When the CM 14 bit is set to 0 low speed on chip oscillator on fRING S can be used for the watchdog timer and voltage detection circuit 10 4 1 2 Medium Speed Mode The main clock divided by 2 4 8 or 16 provides the CPU clock If the CM14 bit is set to 0 low speed on chip oscillator on or the HRAOO bit in the HRAO register is set to 1 high speed on chip oscillator on fRING and fRING128 can be used as timers X and C When the HRAOO bit is set to 1 fRING fast can be used as timer C When the CM14 bit is set to 0 low speed on chip oscillator on fRING S can be used for the watchdog timer and voltage detection circuit 10 4 1 3 High Speed and Low Speed On Chip Oscillator Modes The on chip oscillator clock divided by 1 no division 2 4 8 or 16 provides the CPU clock The on chip oscillator clock is also the clock source for the peripheral function clocks When the HRAOO bit is set to 1 fRING fast can be used as timer C When the CM14 bit is set to 0 low speed on chip oscillator on fRING S can be used for the watchdog timer and voltage detection circuit 10 4 2 Wait Mode Since the CPU clock stops in wait mode the CPU which operates using the CPU clock and the watchdog timer when count source protection mode is disabled stop The main clock and on chip oscillator clock do not stop and the peripheral
78. output is set to H when compare 1 signal is matched NOTES 1 When the same value is sampled from the INT3 pin three times continuously the input is determined 2 When the TCCOO bit in the TCCO register is set to 0 count stops rewrite the TCC13 bit 3 When the TCC13 bit is set to 0 input capture mode set bits TCC12 and TCC14 to TCC17 to 0 Figure 14 28 TCC1 Register Rev 1 30 Dec 08 2006 Page 145 0f 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer C Output Control Register b7 b6 b5 b4 b3 b2 b1 bO Address After Reset OOFFh 00h Bit Symbol TCOUTO CMP output enable bit 0 0 Disables CMP output from CMP0_0 1 Enables CMP output from CMP0_0 TCOUTI CMP output enable bit 1 0 Disables CMP output from CMPO0_1 1 Enables CMP output from CMP0_1 TCOUT2 CMP output enable bit 2 0 Disables CMP output from CMP0_2 Enables CMP output from CMP0_2 bit 3 S TCOUT4 CMP output enable bit 4 0 Disables CMP output from CMP1_1 1 Enables CMP output from CMP1_1 TCOUTS CMP output enable bit 5 0 Disables CMP output from CMP1_2 1 Enables CMP output from CMP1_2 CMP output invert bit 0 0 Does not invert CMP output from CMP0_0 to TCOUT6 CMP0_2 1 Inverts CMP output from CMP0_0 to CMP0_2 CMP output invert bit 1 0 Does not invert CMP output from CMP1_0 to TCOUT7 CMP1_2 R 1 Inverts CMP output from CMP1_0 to CMP1_2 NOTE 1 Set the bits w hich are not used for CMP output to 0
79. port when performing reception only RXDO P1_5 Input serial data PD1_5 bit in PD1 register 0 P1_5 can be used as an input port when performing transmission only CLKO P1_6 Programmable I O Port CKDIR bit in UOMR register 0 Input transfer clock CKDIR bit in UOMR register 1 PD1_6 bit in PD1 register 0 TXD1 P3_7 Output serial data Bits U1SEL1 to U1SELO in UCON register 11b P3_7 can be used as a port when bits U1SEL1 to U1SELO 01b and performing reception only RXD1 P4_5 _ Input serial data PD4_5 bit in PD4 register 0 Bits U1SEL1 to U1SELO in UCON register 01b or 11b Cannot be used as a port when performing transmission only Rev 1 30 Dec 08 2006 Page 164 0f 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface Transmit timing when transfer data is 8 bits long parity enabled 1 stop bit TC poe Transfer clock register giste Write data to UiTB register j d TI bit in UiC1 1 ra H register 0 d Om T d TE bit in UiC1 H ransfer from UiTB register to UARTi transmit register Stop pulsing i because the TE bit is set to 0 Parity Stop H 1 i bit bit H Z i O ISP st do D1 TXEPT bit in UiCO register IR bit SITIC register eee e a Set to 0 when interrupt request is a
80. program restart after interrupt handling completes During auto programming program suspend function disabled Auto programming has priority and the interrupt request acknowledgement is put on standby Interrupt handling is executed after auto programming completes Once an interrupt request is acknowledged auto programming or auto erasure is forcibly stopped immediately and the flash memory is reset Interrupt handling starts after the fixed period and the flash memory restarts Since the block during auto erasure or the address during auto programming is forcibly stopped the normal value may not be read Execute auto erasure again and ensure it completes normally Since the watchdog timer does not stop during the command operation interrupt requests may be generated Reset the watchdog timer regularly using the erase suspend function NOTES 1 Do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 18 7 1 4 Howto Access Write 0 before writing 1 when setting the FMRO1 FMRO2 or FMR11 bit to 1 Do not generate an interrupt between writing 0 and 1 18 7 1 5 Rewriting User ROM Area In EWO Mode if the supply voltage drops while rewriting any block in which a rewrite control program is
81. read by reading the TZS bit until the count stops after writing 0 to the TZS bit After writing 0 to the TZS bit do not access registers associated with timer Z except for the TZS bit until 0 can be read from the TZS bit Rev 1 30 Dec 08 2006 Page 140 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 3 TimerC Timer C is a 16 bit timer Figure 14 23 shows a Block Diagram of Timer C Figure 14 24 shows a Block Diagram of CMP Waveform Generation Unit Figure 14 25 shows a Block Diagram of CMP Waveform Output Unit Timer C has two modes input capture mode and output compare mode Figures 14 26 to 14 29 show the Timer C associated registers TCC11 to TCC10 f 01b mz 10b O 11b Other than D o SC E i INTS interrupt 00b _ detection fRING128 Sampling clock Transfer signal 1a PP Higher 8 bits Lower 8 bits Capture and compare 0 register TMO register Compare circuit 0 Compare 0 interrupt 2 2 ao z ai OH TCCO02 to TCC01 00b IW Higher 8 bits Lower 8 bits fg 91b5No 9 B Timer C interrupt 10b Counter 32 abe fRING fast UD TYC0O TCC12 lt 1 Compare 1 interrupt Higher 8 bits Lower 8 bits Compare register 1 TM1 register TCCO1 to TCC02 TCCO7 Bits in TCCO register TCC10 to TCC12 Bits in TCC1 register Figure 14 23 Block Diagram of Timer C Rev 1 30 Dec 08 2006 Page 141 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group
82. rew ritten during A D conversion the conversion result is undefined Bits CHO to CH2 are enabled w hen the ADGSELO bit is set to 1 After changing the A D operating mode select the analog input pin again Set AD frequency to 10 MHz or below A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address After Reset ADCON1 00D7h 00h SE Reserved bits Set to 0 8 10 bit mode select bit 0 8 bit mode Coen Frequency select bit 1 Refer to the description of the CKSO bit in the RW ADCONDO register function Vref connect bit 0 Vref not connected Reserved bits Set to 0 NOTES If the ADCON1 register is rew ritten during A D conversion the conversion result is undefined Set the BITS bit to 0 8 bit mode in repeat mode When the VCUT bit is set to 1 connected from 0 not connected w ait for 1 us or more before starting A D conversion Figure 17 2 Registers ADCONO and ADCON1 Rev 1 30 Dec 08 2006 Page 234 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter A D Control Register 2 b7 b6 b5 b4 b3 b2 bi bO Address After Reset oop 00h Bit Symbol Function A D conversion method select bit Without sample and hold With sample and hold Reserved bits Set to 0 b3 t b1 Nothing is assigned If necessary set to 0 b7 b4 When read the content is 0 NOTE 1 When the ADCON2 register is rew ritten during A D conversion the conversion result is undefined A
83. select register are maintained Nothing is assigned If necessary set to 0 b3 b2 When read the content is 1 SOL write protect bit The output level can be changed by the SOL bit w hen SOLP this bit is set to 0 RW Cannot write to this bit When read the content is 1 Serial data output value When read setting bit 0 The serial data output is set to L 1 The serial data output is set to H SOL When written 9 0 The data output is L after the serial data output 1 The data output is H after the serial data output Nothing is assigned If necessary set to 0 b6 When read the contentis 1 Nothing is assigned If necessary set to 0 b7 When read the content is 0 NOTES 1 Registers SSCRH SSCRL SSMR SSER SSSR SSMR2 SSTDR and SSRDR 2 The data output after serial data is output can be changed by writing to the SOL bit before or after transfer When writing to the SOL bit set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction Do not write to the SOL bit during data transfer Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial I O with Chip Select for more information Figure 16 3 SSCRL Register Rev 1 30 Dec 08 2006 Page 173 0f315 speeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Mode Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset OOBAh 0
84. time delay to suspend can be applied to the request However we recommend that a suspend request with an interval of less than 650 ps is only used once because if the suspend state continues erasure cannot operate and the incidence of erasure error rises 5 In a system that executes multiple programming operations the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation For example when programming groups of 16 bytes the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number 6 If an error occurs during block erase attempt to execute the clear status register command then execute the block erase command at least three times until the erase error does not occur 7 Customers desiring programming erasure failure rate information should contact their Renesas technical support representative 8 40 C for D version 9 The data hold time includes time that the power supply is off or the clock is not supplied Rev 1 30 Dec 08 2006 Page 279 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Suspend request maskable interrupt request FMR46 Clock U U Fixed time 97 us 1 dependent
85. time of 1st bit With sample and hold 8bits 286AD 4bAD 2 5pAD 0 0 AD 2 5AD 4 0bAD With sample and hold 10bits 336AD 4bAD 2 5pAD 0 0 AD 2 5AD 4 0bAD Figure 17 7 A D Conversion Cycles Rev 1 30 Dec 08 2006 Page 240 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter 17 5 Internal Equivalent Circuit of Analog Input Block Figure 17 8 shows the Internal Equivalent Circuit of Analog Input Block VCC VSS ee U Parasitic diod ON resistor arasitic diode EN KG Wiring resistor SPPFOx 0 6 ka ANS approx 0 2 kQ a Parasitic diode control signal U U U i Sampling U I UH iladder type i ladder type r switches wiring resistors O opper type i i f amplifier ON resistor tapprox 2 kQ Wiring resistor 1 approx 0 2 KQ oO A D successive Reference conversion register control signal Comparison Resistor voltage ON resistor geet approx 0 6 k f A D conversion interrupt request Comparison reference voltage Vref generator Sampling Comparison e SW1 conducts only to the ports selected for analog input Correct toO Se SW2 and SW3 are open when A D conversion is not in progress Control signal for SW2 their status varies as shown by the waveforms in the diagrams at left SW4 conducts only when A D conversion is not in progress Control signal for SW3 NOTE 1 Use this data only as a guideline for circuit design Mass p
86. to 0 by writing 0 to these bits by a program However these bits remain unchanged if 1 is written When using the READ MODIFY WRITE instruction for the TXMR register the TXEDG or TXUND bit may be set to 0 although these bits are set to 1 while the instruction is being executed In this case write 1 to the TXEDG or TXUND bit which is not supposed to be set to 0 with the MOV instruction e When changing to pulse period measurement mode from another mode the contents of bits TXEDG and TXUND are undefined Write 0 to bits TXEDG and TXUND before the count starts e The TXEDG bit may be set to by the prescaler X underflow generated after the count starts e When using the pulse period measurement mode leave two or more periods of the prescaler X immediately after the count starts then set the TXEDG bit to 0 e The TXS bit in the TXMR register has a function to instruct timer X to start or stop counting and a function to indicate that the count has started or stopped 0 count stops can be read until the following count source is applied after 1 count starts is written to the TXS bit while the count is being stopped If the following count source is applied 1 can be read from the TXS bit After writing 1 to the TXS bit do not access registers associated with timer X registers TXMR PREX TX TCSS and TXIC except for the TXS bit until 1 can be read from the TXS bit The count starts at the following count source after the TXS bit is set to 1
87. to ICDRT register gt Read TEND bit in ICSR register No Yes Read ACKBR bit in ICIER register No Set the STOP bit in the ICSR register to 0 Set the IICSEL bit in the PMR register to 1 1 Judge the state of the SCL and SDA lines 2 Set to master transmit mode 3 Generate the start condition 4 Set the transmit data of the 1st byte slave address R W 5 Wait for 1 byte to be transmitted 6 Judge the ACKBR bit from the specified slave device 7 Set the transmit data after 2nd byte except the last byte 8 Wait until the ICRDT register is empty 9 Set the transmit data of the last byte 10 Wait for end of transmission of the last byte 11 Set the TEND bit to 0 12 Set the STOP bit to 0 13 Generate the stop condition 14 Wait until the stop condition is generated 15 Set to slave receive mode Set the TDRE bit to 0 Master receive Yes mode Write transmit data to ICDRT register ER ii Read TDRE bit in ICSR register Write transmit data to ICDRT register Read TEND bit in ICSR register ICSR register TEND bit 0 ICSR register STOP bit lt 0 ICCR2 register SCP bit lt 0 BBSY bit 0 Read STOP bit in ICSR register Yes ICCR1 register TRS bit 0 MST bit lt 0 ICSR register TDRE bit lt 0 End Fi
88. when clock stops High a LPL LPL DES Co ee CH 1 frame 1 frame SSCK SSI RDFF bit in SSSR register RXI interrupt request RXI interrupt request RSSTP bit in SSCRH register is generated is generated RXI interrupt request is generated Processing Dummy read in Data read in SSRDR Set RSSTP Data read in SSRDR by program SSRDR register register bit to 1 register CPHS and CPOS Bit in SSMR register Figure 16 20 Example of Clock Synchronous Serial I O with Chip Select Operation during Data Reception 4 Wire Bus Communication Mode Rev 1 30 Dec 08 2006 Page 196 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 7 SCS Pin Control and Arbitration When setting the SSUMS bit in the SSMR2 register to 1 4 wire bus communication mode and the CSS1 bit in the SSMR2 register to 1 functions as SCS output pin set the MSS bit in the SSCRH register to 1 operates as the master device and check the arbitration of the SCS pin before starting serial transfer If clock synchronous serial I O with chip select detects that the synchronized internal SCS signal is held L in this period the CE bit in the SSSR register is set to 1 conflict error and the MSS bit is automatically set to 0 operates as a slave device Figure 16 21 shows the Arbitration Check Timing Future transmit operations are not performed while the CE bit is set to 1 Set the CE
89. when the prescale X underflows for the second time The TX register should be read before the next active edge is input after the TXEDG bit is set to 1 active edge found The contents in the read out buffer are retained until the TX register is read If the TX register is not read before the next active edge is input the measured result of the previous period is retained To set to 0 by a program use a MOV instruction to write 0 to the TXEDG in the TXMR register At the same time write 1 to the TXUND bit To set to 0 by a program use a MOV instruction to write 0 to the TXUND in the TXMR register At the same time write 1 to the TXEDG bit Bits TXUND and TXEDG are both set to 1 if timer X underflows and reloads on an active edge simultaneously Figure 14 10 Operating Example in Pulse Period Measurement Mode Rev 1 30 Dec 08 2006 Page 121 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 1 6 Notes on Timer X e Timer X stops counting after a reset Set the values in the timer and prescaler before the count starts e Even if the prescaler and timer are read out in 16 bit units these registers are read 1 byte at a time by the MCU Consequently the timer value may be updated during the period when these two registers are being read e Do not rewrite bits TXMODO to TXMOD1 and bits TXMOD2 and TXS simultaneously In pulse period measurement mode bits TXEDG and TXUND in the TXMR register can be set
90. writing programs in assembly language and C Renesas Product specifications updates on documents technical update etc 2 Notation of Numbers and Symbols The notation conventions for register names bit names numbers and symbols used in this manual are described below 1 Register Names Bit Names and Pin Names Registers bits and pins are referred to in the text by symbols The symbol is accompanied by the word register bit or pin to distinguish the three categories Examples the PMO3 bit in the PMO register P3_5 pin VCC pin 2 Notation of Numbers The indication b is appended to numeric values given in binary format However nothing is appended to the values of single bits The indication h is appended to numeric values given in hexadecimal format Nothing is appended to numeric values given in decimal format Examples Binary 11b Hexadecimal EFAOh Decimal 1234 3 The symbols and terms used in register diagrams are described below Register Notation 2 3 4 XXX Register 4 b7 b6 b5 b4 b3 b2 bi b Symbol Address After Reset XXX XXX 00h Bit Symbol D 7 b1 bO XXX0 XXX bits 10 XXX n 0 1 XXX 1 0 Do not set XXX1 11 XXX RW get Nothing is assigned If necessary set to 0 b2 When read the content is undefined cs ee b3 Reserved bits Set to 0 XXXA XXX bits Function varies according to the op
91. 0 5 0 7 JEITA Package Code RENESAS Code Previous Code MASS Typ P SDIP20 6 3x19 1 78 PRDPO0020BA A 20P4B 1 0g Seefe S S i z SISISISLSISISISRS NOTE 1 DIMENSIONS 1 AND 2 2 DO NOT INCLUDE MOLD FLASH D 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET y p Reference Dimension in Millimeters H U l Symbol Min Nom Max e1 732 762 7 92 4 z D 18 8 19 0 19 2 I E eis 6 3 6 45 U U U A SE 4 5 a e Au 0 51 e bs 5 Az 3 3 SEATING PLANE bp 0 38 0 48 0 58 bs 0 9 1 0 1 3 c 0 22 0 27 0 34 Tote e 1 528 1 778 2 028 L 3 0 Rev 1 30 Dec 08 2006 Page 310 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ P HWQFN28 5x5 0 50 PWQN0028KA B 28PJW B 0 05g KM EZ D GEM 21 15 a 22 14 14 CH 22 CA ca ram we ech a 4 CS CS 28 8 SE 28 d a f UI Rer 0 aa DIMENSIONS 1 AND 2 1 7 7 el DO NOT INCLUDE MOLD FLASH e0 Reference Dimension in Millimeters Symbol Min
92. 0 6 5 High Speed On Chip Oscillator Clock for notes on high speed on chip oscillator clock 3 The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to OOh Table 19 11 Power Supply Circuit Timing Characteristics Standard Parameter Condition Max Time for internal power supply stabilization during 2000 power on 2 STOP exit time s 150 NOTES 1 The measurement condition is Vcc 2 7 to 5 5 V and Topr 25 C 2 Waiting time until the internal power supply generation circuit stabilizes during power on 3 Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode Rev 1 30 Dec 08 2006 Page 282 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 12 Timing Requirements of Clock Synchronous Serial UO with Chip Select Standard Parameter Conditions Min SSCK clock cycle time 4 SSCK clock H width 0 4 SSCK clock L width 0 4 SSCK clock rising time Master Slave SSCK clock falling time Master Slave SSO SSI data input setup time 100 SSO SSI data input hold time 1 SCS setup time 1tcyc 50 SCS hold time Itcyc 50 SSO SSI data output delay time 1 SSI slave access time 1 5tcyc 100 SSI slave out open time 1 5tcyc 100 1 Vcc 2 7 to 5 5V Vss OV at Ta 2
93. 0 to 85 C 40 to 85 C unless otherwise specified 2 1tcyc 1 f1 s Rev 1 30 Dec 08 2006 Page 283 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics 4 Wire Bus Communication Mode Master CPHS 1 Vum or VOH SCS output VI or VOH tHI SSCK output CPOS 1 SSCK output CPOS 0 SSO output SSI input tH _tsucye X 4 Wire Bus Communication Mode Master CPHS 0 VIH or VOH SCS output VIH or VOH SSCK output CPOS 1 SSCK output CPOS 0 SSO output y d SSI input X CPHS CPOS Bits in SSMR register tsucYc Figure 19 4 UO Timing of Clock Synchronous Serial I O with Chip Select Master Rev 1 30 Dec 08 2006 Page 284 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics 4 Wire Bus Communication Mode Slave CPHS 1 ViH or VOH SCS input VIH or VOH tLEAD SSCK input CPOS 1 SSCK input CPOS 0 SSO input SSI output 4 Wire Bus Communication Mode Slave CPHS 0 SCS input VIH or VOH VIH or VOH tLEAD tHI SSCK input CPOS 1 SSCK input CPOS 0 tSUCYC SSO input SSI output CPHS CPOS Bits in SSMR register Figure 19 5 UO Timing of Clock S
94. 000Xb 01B6h 01B7h Flash Memory Control Register 0 FMRO 00000001b OFFFFh Optional Function Select Register OFS 2 X Undefined NOTES 1 Blank regions 0100h to 01B2h and 01B8h to 02FFh are all reserved Do not access locations in these regions 2 The OFS register cannot be changed by a user program Use a flash programmer to write to it Rev 1 30 Dec 08 2006 Page 23 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports 5 Programmable UO Ports There are 13 programmable Input Output ports I O ports P1 P3_3 to P3_5 P3_7 and P4_5 4_2 can be used as an input only port Also P4_6 and P4_7 can be used as input only ports if the main clock oscillation circuit is not used Table 5 1 lists an Overview of Programmable I O Ports Table 5 1 Overview of Programmable I O Ports Internal Pull Up Drive Capacity Type of Output I O Setting Resistor Selection P1 CMOSS state Set per bit Set every 4 bits 1 Set every bit 2 of P1_0 to P1_3 P3_3 P4_5 CMOS3 state Set per bit Set every bit 1 None P3_4 P3_5 P3_7 CMOS3 state Set per bit Set every 3 bits 1 None P4_2 P4_6 P4_7 8 No output function None None None NOTES 1 In input mode whether an internal pull up resistor is connected or not can be selected by registers PURO and PURI 2 These ports can be used as the LED drive port by setting the DRR register to 1 high 3 When the ma
95. 0011000b SE Bit counter 2 to 0 8 bits left 1 bit left 2 bits left 3 bits left 4 bits left 5 bits left p 6 bits left 7 bits left Reserved bit Set to 1 RW b3 When read the content is 1 Nothing is assigned If necessary set to 0 b4 When read the content is 1 SSCK clock phase select bit 0 Change data at odd edge Dow nload data at even edge 1 Change data at even edge Dow nload data at odd edge SSCK clock polarity select bit 0 H when clock stops RW 1 L when clock stops MSB first LSB first select bit 0 Transfers data MSB first RW 1 Transfers data LSB first NOTES 1 Refer to 16 2 1 1 Association between Transfer Clock Polarity Phase and Data for the settings of bits CPHS and CPOS Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial I O with Chip Select for more information CPHS RW CPOS MLS Figure 16 4 SSMR Register Rev 1 30 Dec 08 2006 Page 1740f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Enable Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset E 00h Bit Symbol Panton mees eener L I CEIE Conflict error interrupt enable bit A Disables conflict error interrupt request Enables conflict error interrupt request Nothing is assigned If necessary set to 0 b2 bt When read the content is 0 Receive enable bit S Disables receive Enables receive Transm
96. 0130 R8C 1A Group R8C 1B Group IIC bus Interrupt Enable Register b7 b6 b5 b4 b3 b2 bi b0 Address OOBBh 16 Clock Synchronous Serial Interface After Reset 00h Bi Symbol Transmit acknow ledge select bit Receive acknow ledge bit Acknow ledge bit judgment select bit Stop condition detection interrupt enable bit NACK receive interrupt enable bit Receive interrupt enable bit Transmit end interrupt enable bit Transmit interrupt enable bit NOTES 1 An overrun error interrupt request is generated w hen the clock synchronous format is used 2 Set the STIE bit to 1 enable stop condition detection interrupt request w hen the STOP bit in the ICSR register is set Figure 16 27 Rev 1 30 to 0 0 0 is transmitted as acknow ledge bit in 1 1 is transmitted as acknow ledge bit in Acknow ledge bit received from Acknow ledge bit received from Value of receive acknow ledge bit is ignored When receive acknow ledge bit is set to 1 Disables stop condition detection interrupt Enables stop condition detection interrupt Disables NACK receive interrupt request and Enables NACK receive interrupt request and Disables receive data full and overrun Enables receive data full and overrun Disables transmit end interrupt request Enables transmit end interrupt request Disables transmit data empty interrupt request Enables transmit data empty interrupt request
97. 028KA B R5F211B3XXXNP 12 Kbytes Kbyte x 2 768 bytes PWQN0028KA B R5F211B4XXXNP NOTE 16 Kbytes i i i i f i f l i i l i i l I i S I i i i f i l j i f l J i Kbyte x 2 1 Kbyte 1 The user ROM is programmed before shipment PWQN0028KA B Factory programming product 1 Rev 1 30 Dec 08 2006 Page 7 of315 REJ09B0252 0130 2tENESAS R8C 1A Group R8C 1B Group 1 Overview Type No R5F 211B 4D XXX SP E Package type SP PLSP0020JB A DD PRDP0020BA A NP PWQN0028KA B ROM number Classification D Operating ambient temperature 40 C to 85 C No Symbol Operating ambient temperature 20 C to 85 C Y Operating ambient temperature 20 C to 105 C Note ROM capacity 1 4 KB 2 8 KB 3 12 KB 4 16 KB R8C 1B Group R8C Tiny Series Memory Type F Flash memory version Renesas MCU Renesas semiconductors NOTE Please contact Renesas Technology sales offices for the Y version Figure 1 3 Type Number Memory Size and Package of R8C 1B Group Rev 1 30 Dec 08 2006 Page8o0f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview 1 5 Pin Assignments Figure 1 4 shows Pin Assignments for PLSPO0020JB A Package Top View Figure 1 5 shows Pin Assignments for PRDPOO20BA A Package Top View and Figure 1 6 shows Pin Assignments for PWQN0028KA B Package Top View PIN assi
98. 0h NOP i NOP FSET I Enable interrupts Example 2 Use dummy read to delay FSET instruction INT_SWITCH2 FCLR I Disable interrupts AND PB 00H 0056H Set TXIC register to 00h MOV W MEM RO Dummy read FSET I Enable interrupts Example 3 Use POPC instruction to change I flag INT_SWITCH3 PUSHC FLG FCLR I Disable interrupts AND PB 00H 0056H Set TXIC register to 00h POPC FLG Enable interrupts Rev 1 30 Dec 08 2006 Page 102 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 13 Watchdog Timer 13 Watchdog Timer The watchdog timer is a function that detects when a program is out of control Use of the watchdog timer is recommended to improve the reliability of the system The watchdog timer contains a 15 bit counter and allows selection of count source protection mode enable or disable Table 13 1 lists information on the Count Source Protection Mode Refer to 6 5 Watchdog Timer Reset for details on the watchdog timer reset Figure 13 1 shows the Block Diagram of Watchdog Timer and Figures 13 2 to 13 3 show Registers OFS WDC WDTR WDTS and CSPR Table 13 1 Count Source Protection Mode Count Source Protection Mode Count Source Protection Mode Disabled Enabled Count source CPU clock Low speed on chip oscillator clock Item Count operation Decrement Reset condition of watchdog e Reset timer e Write 00h to the WDTR register before writing FFh e underflow Count start condition Eit
99. 0h to 0O2BFFh The internal RAM is allocated higher addresses beginning with address 00400h For example a 1 Kbyte internal RAM area is allocated addresses 00400h to 007FFh The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged Special function registers SFRs are allocated addresses 00000h to 002FFh The peripheral function control registers are allocated here All addresses within the SFR which have nothing allocated are reserved for future use and cannot be accessed by users 00000h SFR See 4 Special Function Registers SFRs 002FFh 00400h Internal RAM OXXXXh 02400h Internal ROM OFFDCh data Flash K E Undefined instruction Overflow BRK instruction Address match K Single step OYYYYh Pa Watchdog timer oscillation stop detection voltage monitor 2 Internal ROM o Address break 02BFFh program ROM Reserved OFFFFh OFFFFh Expanded area FFFFFh NOTES 1 Data flash block A 1 Kbyte and B 1 Kbyte are shown 2 The blank regions are reserved Do not access locations in these regions Internal ROM Internal RAM OYYYYh OXXXXh R5F211B4SP R5F211B4DSP R5F211B4DD R5F211B4NP R5F211B4XXXSP R5F211B4DXXXSP R5F211B4XXXDD 16 Kbytes 0C000h 1 Kbyte 007FFh R5F211B4XXXNP R5F211B3SP R5F211B3DSP R5F211B3DD R5F211B3NP R5F211B3XXXSP R5F211B3DXXXSP R5F211B3XXXDD 12 Kbytes 0D000h 768 bytes OO6FFh R5F
100. 1 lists Bus Cycles by Access Space of the R8C 1A Group and Table 9 2 lists Bus Cycles by Access Space of the R8C 1B Group ROM RAM and SFR are connected to the CPU by an 8 bit bus When accessing in word 16 bit units these areas are accessed twice in 8 bit units Table 9 3 lists Access Units and Bus Operations Table 9 1 Bus Cycles by Access Space of the R8C 1A Group Access Area Bus Cycle SFR 2 cycles of CPU clock ROM RAM 1 cycle of CPU clock Table 9 2 Bus Cycles by Access Space of the R8C 1B Group Access Area Bus Cycle SFR data flash 2 cycles of CPU clock Program ROM RAM 1 cycle of CPU clock Table 9 3 Access Units and Bus Operations Area SFR data flash ROM program ROM RAM Even address Byte access CPU clock LTI LT CPU clock LTI LT Address Address Odd address CPU clock LOT L Tr E cpuclock TL TI T Address EN Data Data Even address Lr Ly CH EH nr Word access CPU clock CPU clock Address Address Data Data Odd address CPU clock CPU clock LOTS lL r Word access Address X Odd X Odd 1 Address X__Odd _X_Odd 1 Data X Data X V Data Y Data Y Data X Rev 1 30 Dec 08 2006 Page 57 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 Clock Generation Circuit The clock generation circuit has Rev 1 30 REJ09B0252 0130 e Main clock oscillation circuit e On chip oscillator oscillation stop detection function Table 10 1 lists
101. 13 bit in TCC1 register 1 Compare 0 output selected TCC15 to TCC 14 bits in TCC1 register 11b CMP output level is set to high at compare 0 match occurrence TCC17 to TCC16 bits in TCC1 register 10b CMP output level is set to low at compare 1 match occurrence TCOUTE bit in TCOUT register 0 not inverted TCOUT7 bit in TCOUT register 1 inverted TCOUTO bit in TCOUT register 1 CMP0_0 output enabled TCOUTS bit in TCOUT register 1 CMP1_0 output enabled P1_0 bit in P1 register 1 high P3_0 bit in P3 register 1 high Figure 14 31 Operating Example in Output Compare Mode Rev 1 30 Dec 08 2006 Page 150 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 3 3 Notes on Timer C Access registers TC TMO and TM1 in 16 bit units The TC register can be read in 16 bit units This prevents the timer value from being updated between when the low order bytes and high order bytes are being read Example of reading timer C MOV W 0090H RO Read out timer C Rev 1 30 Dec 08 2006 Page 151 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface 15 Serial Interface The serial interface consists of two channels UARTO and UART1 Each UARTi i 0 or 1 has an exclusive timer to generate the transfer clock and operates independently Figure 15 1 shows a UARTi i 0 or 1 Block Diagram Figure 15 2 shows a UARTi Transmit Receive Unit UARTO has two modes clock syn
102. 130 R8C 1A Group R8C 1B Group Sieve evsive mode ICSR register AAS bit 0 ICIER register ACKBT bit lt 0 Dummy read in ICDRR register Read RDRF bit in ICSR register Last receive 1 No Read ICDRR register ICIER register ACKBT bit lt 1 Read ICDRR register Read RDRF bit in ICSR register Yes Read ICDRR register NOTE 16 Clock Synchronous Serial Interface 1 Set the AAS bit to 0 2 Set the ACKBT bit to the transmit device 3 Dummy read the ICDRR register 4 Wait until 1 byte is received 5 Judge last receive 1 6 Read the receive data 7 Set the ACKBT bit of the last byte 8 Read the receive data of last byte 1 9 Wait until the last byte is received 10 Read the receive data of the last byte 1 When receiving 1 byte skip steps 2 to 6 after 1 and jump to processing step 7 Processing step 8 is dummy read of the ICDRR register Figure 16 49 Example of Register Setting in Slave Receive Mode I2C bus Interface Mode Rev 1 30 Dec 08 2006 Page 230 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 8 Notes on I2C bus Interface Set the IICSEL bit in the PMR register to 1 select I2C bus interface function to use the DC bus interface 16 3 8 1 Accessing of Registers Associated with I2C bus Interface Wait for three instructions or more or four cycles or more after writing to the
103. 15 peeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface e Example of receive timing when transfer data is 8 bits long parity disabled one stop bit UiBRG output UiC1 register RE bit Stop bit RXDi Transfer clock Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTIi receive register to UiRB register UiC1 register RI bit none SS d SiRIC register IR bit GE SE 8 Set to 0 when interrupt request is accepted or set by a program The above timing diagram applies when the register bits are set as follows e PRYE bit in UIMR register 0 parity disabled STPS bit in UIMR register 0 1 stop bit i Oor1 Figure 15 11 Receive Timing in UART Mode 15 2 1 CNTRO Pin Select Function The CNTRSEL bit in the UCON register selects whether P1_7 is used as the CNTROO INT 10 input pin or P1_5 is used as the CNTROI INT11 input pin When the CNTRSEL bit is set to 0 P1_7 is used as the CNTROO INT 10 pin and when the CNTRSEL bit is set to 1 P1_5 is used as the CNTROI INT11 pin Rev 1 30 Dec 08 2006 Page 166 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface 15 2 2 Bit Rate In UART mode the bit rate is the frequency divided by the UiBRG i 0 or 1 register UART Mode e Internal clock selected fi Bit Rate x 16 UiBRG register setting value Fj Count source frequency o
104. 1A Group R8C 1B Group 12 Interrupts 12 2 2 INTO Input Filter The INTO input contains a digital filter The sampling clock is selected by bits INTOF1 to INTOFO in the INTOF register The INTO level is sampled every sampling clock cycle and if the sampled input level matches three times the IR bit in the INTOIC register is set to 1 interrupt requested Figure 12 12 shows the Configuration of INTO Input Filter Figure 12 13 shows an Operating Example of INTO Input Filter INTOF1 to INTOFO Sampling clock INTOEN Other than INTOF1 to INTOFO Digital filter L 202 TO interrupt input level Port P4_5 matches 3x direction register Both edges detection circuit NTOPL 1 INTOFO INTOF1 Bits in INTOF register INTOEN INTOPL Bits in INTEN register Figure 12 12 Configuration of INTO Input Filter GW IR bit in INTOIC register Set to 0 by a program This is an operating example in which bits INTOF1 to INTOFO in the INTOF register are set to 01b 10b or 11b digital filter enabled Figure 12 13 Operating Example of INTO Input Filter Rev 1 30 Dec 08 2006 Page 92 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 2 3 INT1 Interrupt The INT interrupt is generated by an INT input The edge polarity is selected by the ROEDG bit in the TXMR register When the CNTRSEL bit in the UCON register is set to 0 the INT10 pin becomes the INTI input pin When the CNTRSEL bit
105. 1Ch 00h SE Reserved bits Set to 0 o e TT ml select bit 1 Count source protection mode enabled NOTES 1 When 0 is w itten to the CSPROINI bit in the OFS register the value after reset is 10000000b 2 Write 0 before writing 1 to set the CSPRO bit to 1 0 cannot be set by a program Figure 13 3 Registers WDTR WDTS and CSPR Rev 1 30 Dec 08 2006 Page 105 of 315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 13 Watchdog Timer 13 1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled Table 13 2 lists the Watchdog Timer Specifications with Count Source Protection Mode Disabled Table 13 2 Watchdog Timer Specifications with Count Source Protection Mode Disabled Item Specification Count source CPU clock Count operation Decrement Period Division ratio of prescaler n x count value of watchdog timer 32768 1 CPU clock n 16 or 128 selected by WDC7 bit in WDC register Example When the CPU clock frequency is 16 MHz and prescaler divides by 16 the period is approximately 32 8 ms Count start conditions The WDTON bit 2 in the OFS register OFFFFh selects the operation of the watchdog timer after a reset e When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to e When the W
106. 2006 Page 83 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts INTO Interrupt Control Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 005Dh XX00X000b Level 0 interrupt disable Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 OR Ee es Jr 1 Requests interrupt e Reserved bit Set to 0 e Pee Te Nothing is assigned if necessary set to 0 i b7 b6 When read the content is undefined NOTES Only 0 can be written to the IR bit Do not write 1 Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated Refer to 12 5 6 Changing Interrupt Control Registers If the INTOPL bit in the INTEN register is set to 1 both edges set the POL bit to 0 selects falling edge The IR bit may be set to 1 requests interrupt w hen the POL bit is rewritten Refer to 12 5 5 Changing Interrupt Sources Figure 12 4 INTOIC Register Rev 1 30 Dec 08 2006 Page 84 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 1 I Flag The I flag enables or disables maskable interrupts Setting the I flag to 1 enabled enables maskable interrupts Setting the I flag to 0 disabled disables all maskable interrupts 12 1 6 2 IR Bit The IR bit is set to interrupt requested when an interrupt request is generated Then when the interrupt request is acknowledged and the CPU bran
107. 211B3XXXNP R5F211B2SP R5F211B2DSP R5F211B2DD R5F211B2NP R5F211B2XXXSP R5F211B2DXXXSP R5F211B2XXXDD 8 Kbytes OE000h 512 bytes OOSFFh R5F211B2XXXNP R5F211B1SP RS5F211B1DSP R5F211B1DD Fees Dap Greg Bee R5F211B1XXXSP R5F211B1DXXXSP R5F211B1XXXDD y y Figure 3 2 Memory Map of R8C 1B Group Rev 1 30 Dec 08 2006 Page 19 of 315 v EN SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 4 Special Function Registers SFRs 4 Special Function Registers SFRs An SFR special function register is a control register for a peripheral function Tables 4 1 to 4 4 list the special function registers Table 4 1 SFR Information 1 Address Register Symbol After reset 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PMO 00h 0005h Processor Mode Register 1 PM1 00h 0006h System Clock Control Register 0 CMO 01101000b 0007h System Clock Control Register 1 CM1 00100000b 0008h 0009h Address Match Interrupt Enable Register AIER 00h O00Ah Protect Register PRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh OOOEh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register WDC 00X11111b 0010h Address Match Interrupt Register 0 RMADO 00h 0011h 00h 0012h XOh 0013h 0014h Address Match Interrupt Register 1 RMAD1 00h 0015h 00h 0016h XOh 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protection Mode Register CSPR 00h 001Dh OOTEH INT
108. 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit 7 3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 7 3 lists the Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bits Figure 7 9 shows an Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset To use voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode set the VW2C1 bit in the VW2C register to 1 digital filter disabled Table 7 3 Setting Procedure of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Associated Bits When Using Digital Filter When Not Using Digital Filter Voltage Monitor 2 Voltage Monitor 2 Interrupt Reset Voltage Monitor 2 Voltage Monitor 2 Interrupt Reset Set the VCA27 bit in the VCA2 register to 1 voltage detection 2 circuit enabled Wait for td E A Select the sampling clock of the digital filter by bits VW2F0 to VW2F 1 in the VW2C register Select the timing of the interrupt and reset request by the VW2C7 bit in the VW2C register 1 Set the VW2C1 bit in the VW2C register to 0 digital filter enabled Set the VW2C1 bit in the VW2C register to 1 digital filter disabled Set the VW2CE6 bit in Set the VW2CE6 bit in the VW2C register to the VW2C register to 0 voltage monitor 2 1 voltage monitor 2 interrupt mode reset mode Set the VW2CE6 bit in Set
109. 47 1 Wait mode Main clock off High speed on chip oscillator off Low speed on chip oscillator on 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 VCA26 0 Wait mode Main clock off High speed on chip oscillator off Low speed on chip oscillator on 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 VCA26 0 Stop mode Main clock off Topr 25 C High speed on chip oscillator off Low speed on chip oscillator off CM10 1 Peripheral clock off VCA27 VCA26 0 Rev 1 30 Dec 08 2006 Page 293 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Timing requirements Unless Otherwise Specified Vcc 3 V Vss 0 V at Ta 25 C Vcc 3 V Table 19 23 XIN Input Symbol Parameter Standard Min tc XIN XIN input cycle time 100 TWH XIN XIN input H width 40 TWL XIN XIN input Figure 19 13 XIN Input Timing Diagram when Vcc 3 V Table 19 24 CNTRO Input CNTR1 Input INT1 Input Symbol XIN input L width Parameter 40 Standard Min tc CNTRO CNTRO input cycle time 300 tWH CNTRO CNTRO input H width tWL CNTRO CNTRO input CNTRO input L width tWL CNTRO gt Figure 19 14 CNTRO Input CNTR1 Input INT1 Input Timing Diagram when Vcc 3 V
110. 6 bit is set to 1 read enabled before accessing the user ROM area The auto program operation can be restarted by setting the FMR42 bit to 0 program restarts 18 4 2 EW1 Mode The MCU is switched to EW1 mode by setting the FMR11 bit to 1 EW1 mode after setting the FMRO1 bit to 1 CPU rewrite mode enabled The FMRO register can be used to determine when program and erase operations complete Do not execute software commands that use the read status register in EW1 mode To enable the erase suspend function during auto erasure execute the block erase command after setting the FMR4O0 bit to 1 erase suspend enabled The interrupt to enter erase suspend should be in interrupt enabled status After waiting for td SR SUS after the block erase command is executed the interrupt request is acknowledged When an interrupt request is generated the FMR41 bit is automatically set to 1 requests erase suspend and the auto erase operation suspends If an auto erase operation does not complete FMROO0 bit is 0 after an interrupt process completes the auto erase operation restarts by setting the FMR41 bit to 0 erase restarts To enable the program suspend function during auto programming execute the program command after setting the FMR40 bit to 1 suspend enabled The interrupt to enter a program suspend should be in interrupt enabled status After waiting for td SR SUS after the program command is executed an interrupt request is acknowledged
111. 62 5 kHz 78 1 kHz 125 kHz 156 kHz 1 56 89 3 kHz 143 kHz 179 kHz 286 kHz 357 kHz 1 80 62 5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 96 52 1 kHz 83 3 kHz 104 kHz 167 kHz 208 kHz f1 128 39 1 kHz 62 5 kHz 78 1 kHz 125 kHz 156 kHz f1 160 31 3 kHz 50 0kHz 62 5 kHz 100 kHz 125 kHz f1 200 25 0 kHz 40 0 kHz 50 0 kHz 80 0 kHz 100 kHz 11 224 22 3 kHz 35 7 kHz 44 6 kHz 71 4 kHz 89 3 kHz f1 256 19 5 kHz 31 3kHz 39 1 kHz 62 5 kHz 78 1 kHz O O O o Oo El El Rev 1 30 Dec 08 2006 Page 209 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 2 Interrupt Requests The DC bus interface has six interrupt requests when the DC bus format is used and four when the clock synchronous serial format is used Table 16 7 lists the Interrupt Requests of I C bus Interface Since these interrupt requests are allocated at the UC bus interface interrupt vector table determining the factor by each bit is necessary Table 16 7 Interrupt Requests of 12C bus Interface Interrupt Request Generation Condition Format 12C bus Clock Synchronous Serial Transmit data empty TIE 1 and TDRE 1 Enabled Enabled Transmit ends TEIE 1 and TEND 1 Enabled Enabled Receive data full RIE 1 and RDRF 1 Enabled Enabled Stop condition detection STIE 1 and STOP 1 Enabled Di
112. AS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 CPU Rewrite Mode In CPU rewrite mode the user ROM area can be rewritten by executing software commands from the CPU Therefore the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer Execute the program and block erase commands only to blocks in the user ROM area The flash module has an erase suspend function when an interrupt request is generated during an erase operation in CPU rewrite mode It performs an interrupt process after the erase operation is halted temporarily During erase suspend the user ROM area can be read by a program In case an interrupt request is generated during an auto program operation in CPU rewrite mode the flash module has a program suspend function which performs the interrupt process after the auto program operation During program suspend the user ROM area can be read by a program CPU rewrite mode has an erase write 0 mode EWO mode and an erase write 1 mode EW1 mode Table 18 3 lists the Differences between EWO Mode and EW1 Mode Table 18 3 Differences between EWO Mode and EW1 Mode Item EWO Mode EW1 Mode Operating mode Single chip mode Single chip mode Areas in which a rewrite control program can be located User ROM area User ROM area Areas in which a rewrite control program can be Necessary to transfer to any area other than the flas
113. After the TDRE bit is set to 1 data is transferred from registers SSTDR to SSTRSR transmission starts When the TIE bit in the SSER register is set to 1 a TXI interrupt request is generated After 1 frame of data is transferred while the TDRE bit is set to 0 the data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started If the 8th bit is transmitted while TDRE is set to 1 TEND in the SSSR register is set to 1 when the last bit of the transmit data is transmitted the TDRE bit is set to 1 and the state is retained If the TEIE bit in the SSER register is set to 1 transmit end interrupt requests enabled a TEI interrupt request is generated The SSCK pin remains H after transmit end and the SCS pin is held H When transmitting continuously while the SCS pin is held L write the next transmit data to the SSTDR register before transmitting the 8th bit Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 overrun error Confirm that the ORER bit is set to 0 before transmission In contrast to the clock synchronous communication mode the SSO pin is placed in high impedance state while the SCS pin is placed in high impedance state when operating as a master device and the SSI pin is placed in high impedance state while the SCS pin is placed in H input state when operating as a slave device The sample flowchart is the same as that for the clock synchronous c
114. Also after writing 0 count stops to the TXS bit during the count timer X stops counting at the following count source 1 count starts can be read by reading the TXS bit until the count stops after writing 0 to the TXS bit After writing 0 to the TXS bit do not access registers associated with timer X except for the TXS bit until 0 can be read from the TXS bit Rev 1 30 Dec 08 2006 Page 122 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 2 Timer Z Timer Z is an 8 bit timer with an 8 bit prescaler The prescaler and timer each consist of a reload register and counter The reload register and counter are allocated at the same address Refer to the Tables 14 7 to 14 10 for the Specifications of Each Mode Timer Z contains timer Z primary and timer Z secondary reload registers Figure 14 11 shows a Block Diagram of Timer Z Figures 14 12 to 14 15 show registers TZMR PREZ TZSC TZPR TZOC PUM and TCSS Timer Z has the following four operating modes e Timer mode e Programmable waveform generation mode e Programmable one shot generation mode e Programmable wait one shot generation mode The timer counts an internal count source or timer X underflows The timer outputs pulses of a given width successively The timer outputs a one shot pulse The timer outputs a delayed one shot pulse TZSC register TZCK1 to TZCKO Reload register Reload register l Reload register 00b
115. Ambient Temperature 20 to 85 C 40 to 85 C D version 20 to 105 C Y version 2 Package 20 pin molded plastic LSSOP 20 pin molded plastic SDIP 28 pin molded plastic HWQFN NOTE 1 12C bus is a trademark of Koninklijke Philips Electronics N V 2 Please contact Renesas Technology sales offices for the Y version Rev 1 30 Dec 08 2006 Page 2of 315 2RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview Table 1 2 Functions and Specifications for R8C 1B Group Item Specification Number of fundamental 89 instructions instructions Minimum instruction execution 50 ns f XIN 20 MHz VCC 3 0 to 5 5 V time 100 ns f XIN 10 MHz VCC 2 7 to 5 5 V Operating mode Single chip Address space 1 Mbyte Memory capacity See Table 1 4 Product Information for R8C 1B Group Peripheral Ports I O ports 13 pins including LED drive port Functions Input port 3 pins LED drive ports I O ports 4 pins Timers Timer X 8 bits x 1 channel timer Z 8 bits x 1 channel Each timer equipped with 8 bit prescaler Timer C 16 bits x 1 channel Input capture and output compare circuits Serial interfaces 1 channel Clock synchronous serial I O UART 1 channel UART Clock synchronous serial interface 1 channel 12C bus Interface 1 Clock synchronous serial I O with chip select SSU A D converter 10 bit A D converter 1 circuit 4 channels Watchdog timer 15
116. D1 and OCDO Figure 10 1 Clock Generation Circuit Rev 1 30 Dec 08 2006 Page 59 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit System Clock Control Register 0 b7 b6 b5 b4 b3 b2 b1 b Address After Reset 0006h 68h Bi Symbol Reserved bits Set to 0 b1 b0 WATT peripheral function clock stop 0 Peripheral function clock does not stop bit in w ait mode CM02 1 Peripheral function clock stops in w ait mode Reserved bit Set to 1 a RW RW RW RW RW RW W Reserved bit Set to 0 Main clock XIN XOUT 0 Main clock oscillates stop bit 4 1 Main clock stops System clock division select bit 0 0 CM16 CM17 enabled 1 Divide by 8 mode Reserved bit Set to 0 NOTES 1 Set the PRCO bit in the PRCR register to 1 write enable before rew riting the CMO register 2 The CMO05 bit stops the main clock w hen the on chip oscillator mode is selected Do not use this bit to detect w hether the main clock is stopped To stop the main clock set the bits in the follow ing order a Set bits OCD1 and OCDO in the OCD register to 00b oscillation stop detection function disabled b Set the OCD2 bit to 1 selects on chip oscillator clock To input an external clock set the CMO5 bit to 1 main clock stops and the CM13 bit in the CM1 register to 1 XIN XOUT pin When the CM05 bit is set to 1 main clock stops and the CM13 bit in the CM1 register is set to 0
117. DTON bit is set to 0 watchdog timer starts automatically after exiting The watchdog timer and prescaler start counting automatically after reset Reset condition of watchdog Reset timer e Write 00h to the WDTR register before writing FFh e Underflow Count stop condition Stop and wait modes inherit the count from the held value after exiting modes Operation at time of underflow When the PM12 bit in the PM1 register is set to 0 Watchdog timer interrupt When the PM12 bit in the PM1 register is set to 1 Watchdog timer reset Refer to 6 5 Watchdog Timer Reset NOTES 1 The watchdog timer is reset when OOh is witten to the WDTR register before FFh The prescaler is reset after the MCU is reset Some errors in the period of the watchdog timer may be caused by the prescaler 2 The WDTON bit cannot be changed by a program To set the WDTON bit write 0 to bit 0 of address OFFFFh with a flash programmer Rev 1 30 Dec 08 2006 Page 106 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 13 Watchdog Timer 13 2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low speed on chip oscillator clock when count source protection mode is enabled If the CPU clock stops when a program is out of control the clock can still be supplied to the watchdog timer Table 13 3 lists the Watchdog Timer Specifications with Count Source Protection Mode Enabled Tabl
118. EE ee SCL slave output SDA A slave output RDRF bit in ICSR register Za Processing 3 Set ACKBT bit to 1 3 Read ICDRR register 4 Read ICDRR register by program Figure 16 40 Operating Timing in Slave Receive Mode I2C bus Interface Mode 2 Rev 1 30 Dec 08 2006 Page 221 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 4 Clock Synchronous Serial Mode 16 3 4 1 Clock Synchronous Serial Format Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication Figure 16 41 shows the Transfer Format of Clock Synchronous Serial Format When the MST bit in the ICCR1 register is set to 1 the transfer clock is output from the SCL pin and when the MST bit is set to 0 the external clock is input The transfer data is output between successive falling edges of the SCL clock and data is determined at the rising edge of the SCL clock MSB first or LSB first can be selected as the order of the data transfer by setting the MLS bit in the ICMR register The SDA output level can be changed by the SDAO bit in the ICCR2 register during transfer standby NAN Ans SDA Figure 16 41 Transfer Format of Clock Synchronous Serial Format Rev 1 30 Dec 08 2006 Page 222 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 4 2 Transmit Operation In trans
119. EW1 mode it is automatically set to 1 if a maskable interrupt is generated during an erase operation w hile the FMR40 bit is set to 1 Do not set this bit to 1 by a program 0 can be written The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 enable and programming to the FMR42 bit is enabled until auto programming ends after a program command is generated This bit is set to 0 during periods other than the above In EWO mode 0 or 1 can be programmed to the FMR42 bit by a program In EW1 mode the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto programming when the FMR40 bit is set to 1 1 cannot be written to the FMR42 bit by a program RW RW RW W 4 Use this mode only in low speed on chip oscillator mode Figure 18 7 FMR4 Register Rev 1 30 Dec 08 2006 Page 257 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Figure 18 8 shows the Timing of Suspend Operation Erasure Erasure Programming Programming Programming Programming Erasure Erasure starts suspends starts suspends restarts restarts ends During erasure During i i During erasure U U DH 1 FMROO bit in Remains 0 during suspend FMRO register XS i i FMR46 bit in FMR4 register FMR44 bit in FMR4 register 1 1 H H FMR43 bit in H 1 FMR4 register Remains 1 during suspend t t Check that the Check that the Check the status Check the status FMR43 bit is se
120. Example of Oscillation Evaluation Circuit Appendix 3 Example of Oscillation Evaluation Circuit Appendix Figure 3 1 shows an Example of Oscillation Evaluation Circuit Connect oscillation circuit H z Ka D u NOTE 1 Write a program to perform the evaluation Appendix Figure 3 1 Example of Oscillation Evaluation Circuit Rev 1 30 Dec 08 2006 Page 313 0f 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Register Index Register Index A K Ee 235 KIEN deed 97 ADCONO osioissa 234 KUPIC ccccccssssecsccsessesssssescssecsesvesncsessesseeeees 83 PG ONG WEE 234 ENEE reet 235 o EE 83 PRUE Reds geesde big 99 eeh EE 62 ei EE 104 250 C P e EE 60 GOUT 61 E O E A E A T 29 CMPOIC nassssssansesssanrsessnnresssnnrssssnrnesnnnnneeens 83 ENEE 29 CMP TG nassssssssssssssnrsessnnressssnrssnnnrresennnneeens 83 CHE 30 SPR onsssansssssanressssnrssssnnrereennnnnennnnneennnnene 105 POl e 29 EIERE 29 D PD4 EE 29 PMO beienee 55 EE te 31 CC KEE 56 PMR EE 30 178 208 F PACE egiertteetueeneeen te 77 PREX aa eee eT 111 EMpn D 255 PREZ hee 125 a edu AR EE Ae 256 PUM EEN 126 NA Ae sec ct cee teh ne at 257 PURO seis eege ge 31 PUR a 31 H R RE 63 BER siencetstaaorssteaai te tinnwisc eis bocesiusas tele 64 RMADO E 99 TT 64 MAD 1 en 99 S ICCRA MO 202 SORIG E 83 eier gt ee ee ae ee ER 203 CIR Re 83 ODRA 208 SIRIG EN 83 CDpRS 208 LC UE 83 IESEL 207 SAR EG 207 EIERE ee 205 SSGRH see ENEE 172 Ca
121. Group R8C 1B Group 18 Flash Memory 18 2 Memory Map The flash memory contains a user ROM area and a boot ROM area reserved area Figure 18 1 shows a Flash Memory Block Diagram for R8C 1A Group Figure 18 2 shows a Flash Memory Block Diagram for R8C 1B Group The user ROM area of the R8C 1B Group contains an area program ROM which stores MCU operating programs and the blocks A and B data flash each 1 Kbyte in size The user ROM area is divided into several blocks The user ROM area can be rewritten in CPU rewrite mode and standard serial I O and parallel I O modes When rewriting blocks O and 1 in CPU rewrite mode set the FMRO2 bit in the FMRO register to 1 rewrite enabled When the FMR15 bit in the FMRI register to is set to 0 rewrite enabled block 0 is rewritable When the FMR 16 bit to is set 0 rewrite enabled block 1 is rewritable The rewrite control program for standard serial I O mode is stored in the boot ROM area before shipment The boot ROM area and the user ROM area share the same address but have separate memory areas 8 Kbyte ROM product f i 4 Kbyte ROM product Block 0 8 Kbytes Program ROM Block 0 4 Kbytes User ROM area User ROM area 16 Kbyte ROM product Block 1 8 Kbytes 12 Kbyte ROM product Program ROM Block 1 4 Kbytes Block 0 8 Kbytes Block 0 8 Kbytes 8 Kbytes OE000h OFFFFh User ROM area User ROM area Boot ROM area reserved area NOTES 1 When the FM
122. I O with Chip Select SSU 16 3 12C bus Interface Compare 1 64 to 67 0040h to 0043h 16 14 3 Timer C UARTO transmit 68 to 71 0044h to 0047h 17 UARTO receive 18 UART1 transmit 76 to 79 004Ch to 004Fh 19 UART1 receive 72 to 75 0048h to 004Bh 80 to 83 0050h to 0053h 20 15 Serial Interface Reserved 21 Timer X 88 to 91 0058h to 005Bh 22 14 1 Timer X Reserved 23 Timer Z 96 to 99 0060h to 0063h 24 14 2 Timer Z INT1 100 to 103 0064h to 0067h 25 INT3 104 to 107 0068h to 006Bh 26 12 2 INT interrupt Timer C 108 to 111 006Ch to 006Fh 27 Compare 0 112 to 115 0070h to 0073h 28 14 3 Timer C INTO 116 to 119 0074h to 0077h 29 12 2 INT interrupt Reserved 30 Reserved 31 Software interrupt NOTES 128 to 131 0080h to 0083h to 252 to 255 00FCh to 00FFh 32 to 63 1 These addresses are relative to those in the INTB register 2 The flag does not disable these interrupts 3 The IICSEL bit in the PMR register switches functions Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 82 of 315 2tENESAS R8C Tiny Series Software Manual R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 Interrupt Control The following describes enabling and disabling the maskable interrupts and set
123. ING fast is generated by the high speed on chip oscillator and supplied by setting the HRAO0 bit to 1 When the WAIT instruction is executed the clock fRING fast does not stop 10 3 6 fRING S fRING S is an operating clock for the watchdog timer and voltage detection circuit fRING S is supplied by setting the CM14 bit to 0 low speed on chip oscillator on and uses the clock generated by the low speed on chip oscillator When the WAIT instruction is executed or in count source protect mode of the watchdog timer fRING S does not stop Rev 1 30 Dec 08 2006 Page 67 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 4 Power Control There are three power control modes All modes other than wait mode and stop mode are referred to as standard operating mode 10 4 1 Standard Operating Mode Standard operating mode is further separated into four modes In standard operating mode the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks Power consumption control is enabled by controlling the CPU clock frequency The higher the CPU clock frequency the more processing power increases The lower the CPU clock frequency the more power consumption decreases When unnecessary oscillator circuits stop power consumption is further reduced Before the clock sources for the CPU clock can be switched over the new clock source needs to be oscillat
124. Interrupt Register 0 RMADO 99 0050h Compare 1 Interrupt Control Register CMP1IC 83 0011h 0051h UARTO Transmit Interrupt Control Register SOTIC 83 0012h 0052h UARTO Receive Interrupt Control Register SORIC 83 0013h 0053h UART1 Transmit Interrupt Control Register S1TIC 83 0014h Address Match Interrupt Register 1 RMAD1 99 0054h UART1 Receive Interrupt Control Register S1RIC 83 0015h 0055h 0016h 0056h Timer X Interrupt Control Register TXIC 83 0017h 0057h 0018h 0058h Timer Z Interrupt Control Register TZIC 83 0019h 0059h INT1 Interrupt Control Register INTIIG 83 001Ah 005Ah INT3 Interrupt Control Register INT3IC 83 001Bh 005Bh Timer C Interrupt Control Register TCIC 83 001Ch Count Source Protection Mode Register CSPR 105 005Ch Compare 0 Interrupt Control Register CMPOIC 83 001Dh 005Dh INTO Interrupt Control Register INTOIC 84 OO1Eh INTO Input Filter Select Register INTOR 91 O05Eh DOEN 005Fh 0020h High Speed On Chip Oscillator Control HRAO 63 0060h Register 0 0061h 0021h High Speed On Chip Oscillator Control HRA1 64 0062h Register 1 0063h 0022h High Speed On Chip Oscillator Control HRA2 64 0064h Register 2 0065h 0023h 0066h 0024h 0067h 0025h 0068h 0026h 0069h 0027h 006Ah 0028h 006Bh 0029h 006Ch 002Ah 006Dh 002Bh DOEN 002Ch DOSEN 002Dh 0070h 002Eh 0071h 002Fh 0072h 0030h 0073h 0031h Voltage Detection Register 1 VCA1 47 0074h 0032h Voltage Detection Register 2 VCA2 47 0075h 0033h 0076h 0034h 0077h 0035h 0078h 0036h Voltage Monitor
125. Interrupt response time a Period between interrupt request generation and the completion of execution of an instruction The length of time varies depending on the instruction being executed The DIVX instruction requires the longest time 30 cycles assuming no wait states and that a register is set as the divisor b 21 cycles for address match and single step interrupts Figure 12 6 Interrupt Response Time 12 1 6 6 IPL Change when Interrupt Request is Acknowledged When an interrupt request of a maskable interrupt is acknowledged the interrupt priority level of the acknowledged interrupt is set in the IPL When a software interrupt or special interrupt request is acknowledged the level listed in Table 12 5 is set in the IPL Table 12 5 lists the IPL Value When a Software or Special Interrupt Is Acknowledged Table 12 5 IPL Value When a Software or Special Interrupt Is Acknowledged Interrupt Source Value Set in IPL Watchdog timer oscillation stop detection voltage monitor 2 7 Software address match single step address break Not changed Rev 1 30 Dec 08 2006 Page 87 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 7 Saving a Register In the interrupt sequence the FLG register and PC are saved to the stack After an extended 16 bits 4 high order bits in the PC and 4 high order IPL and 8 low order bits in the FLG register are saved to the stack the 16 low order bits i
126. Mode Specifications The TZSC register is not used in timer mode Figure 14 16 shows Registers TZMR and PUM in Timer Mode Table 14 7 Timer Mode Specifications Item Specification Count sources f1 f2 f8 Timer X underflow Count operations e Decrement e When the timer underflows it reloads the reload register contents before the count continues When timer Z underflows the contents of timer Z primary reload register is reloaded Divide ratio 1 n 1 m 1 fi Count source frequency n Value set in PREZ register m value set in TZPR register Count start condition 1 count starts is written to the TZS bit in the TZMR register Count stop condition 0 count stops is written to the TZS bit in the TZMR register Interrupt request e When timer Z underflows timer Z interrupt generation timing TZOUT pin function Programmable I O port INTO pin function Programmable I O port or INTO interrupt input Read from timer The count value can be read out by reading registers TZPR and PREZ Write to timer e When registers TZPR and PREZ are written while the count is stopped values are written to both the reload register and counter e When registers TZPR and PREZ are written during the count while the TZWC bit is set to 0 writing to the reload register and counter simultaneously the value is written to each reload register of registers TZPR and PREZ at the following count source input the data is transferred to the counter at the second
127. NOSTG bit in the PUM register is set to 0 INTO one shot trigger disabled programmable I O port or INTO interrupt input e When the INOSTG bit in the PUM register is set to 1 INTO one shot trigger enabled external trigger INTO interrupt input Read from timer The count value can be read out by reading registers TZPR and PREZ Write to timer The value written to registers TZPR and PREZ is written to the reload register only 3 Select functions NOTES e Output level latch select function The output level of the one shot pulse waveform is selected by the TZOPL bit e INTO pin one shot trigger control function and polarity select function Trigger input from the INTO pin can be set to active or inactive by the INOSTG bit Also the active trigger s polarity can be selected by the INOSEG bit 1 The TZS bit in the TZMR register must be set to 1 start counting 2 The TZS bit must be set to 1 start counting the INTOEN bit in the INTEN register to 1 enabling INTO input and the INOSTG bit in the PUM register to 1 enabling INTO one shot trigger A trigger which is input during the count cannot be acknowledged however an INTO interrupt request is generated 3 The set values are reflected at the following one shot pulse after writing to the TZPR register Dec 08 2006 Page 137 of 315 stENESAS R8C 1A Group R8C 1B Group 14 Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Res
128. O Input Filter Select Register INTOF ooh 001Fh 0020h High Speed On Chip Oscillator Control Register 0 HRAO 00h 0021h High Speed On Chip Oscillator Control Register 1 HRA1 When shipping 0022h High Speed On Chip Oscillator Control Register 2 HRA2 00h 0023h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h Voltage Detection Register 1 2 VCAT 00001000b 0032h Voltage Detection Register 2 2 VCA2 ooh 8 01000000b 4 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register 2 VWic 0000X000b 3 0100X001b 4 0037h Voltage Monitor 2 Circuit Control Register 5 VW2C 00h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh X Undefined NOTES 1 The blank regions are reserved Do not access locations in these regions Software reset watchdog timer reset and voltage monitor 2 reset do not affect this register After hardware reset After power on reset or voltage monitor 1 reset Software reset watchdog timer reset and voltage monitor 2 reset do not affect b2 and b3 IPN Rev 1 30 Dec 08 2006 Page 200f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 4 Special Function Registers SFRs Table 4 2 SFR Information 2 Address Register Symbol After reset 0040h 0041A 0042h 0043h 0044h 0045h 0046h 0047 0048h
129. O to TCOUT5 in the TCOUT register are set to 1 enables CMP output 2 Waveform output stop condition Bits TCOUTO to TCOUT5 in the TCOUT register are set to 0 disables CMP output Interrupt request generation timing e When a match occurs in compare circuit 0 compare 0 interrupt e When a match occurs in compare circuit 1 compare 1 interrupt e When time C overflows timer C interrupt INT3 TCIN pin function Programmable I O port or INT3 interrupt input P1_0 to P1_2 pins and P3_3 to P3_5 pins functions Programmable I O port or CMP output Counter value reset timing When the TCCO0 bit in the TCCO register is set to 0 count stops Read from timer 2 e The value in the compare register can be read out by reading registers TMO and TM1 e The count value can be read out by reading the TC register Write to timer 2 e Write to the TC register is disabled e The values written to registers TMO and TM1 are stored in the compare register in the following timings When registers TMO and TM1 are written to if the TCCOO bit is set to 0 count stops When the counter overflows if the TCCOO bit is set to 1 during counting and the TCC12 bit in the TCC1 register is set to 0 free run When the compare 1 matches a counter if the TCCOO bit is set to 1 and the TCC12 bit is set to 1 the TC register is set to 0000h at compare 1 match Select functions NOTES e Timer C count
130. O0F4h 00B7h OOFSh 00B8h SS Control Register H IIC bus Control SSCRH ICCRI 172 202 HEEN Register 1 00F7h 00B9h SS Control Register L IIC bus Control SSCRL ICCR2 173 203 OOF8h__ Port Mode Register PMR 30 178 208 Register 2 OOF9h OOBAh SS Mode Register IIC bus Mode Register SSMR ICMR 174 204 OOFAh OOBBh SS Enable Register IIC bus Interrupt SSER ICIER 175 205 OOFBh Enable Register OOFCh Pull Up Control Register 0 PURO 31 00BCh SS Status Register IIC bus Status Register SSSR ICSR 176 206 00FDh Pull Up Control Register 1 PUR1 31 OOBDh_ SS Mode Register 2 Slave Address SSMR2 SAR 177 207 OOFEh Port P1 Drive Capacity Control Register DRR 31 Register OOFFh Timer C Output Control Register TCOUT 146 OOBEh SS Transmit Data Register IIC bus SSTDR ICDRT 178 207 Transmit Data Register 01B3h Flash Memory Control Register 4 FMR4 257 OOBFh SS Receive Data Register IIC bus Receive SSRDR ICDRR 178 208 01B4h Data Register O1B5h Flash Memory Control Register 1 FMRI 256 NOTE 01B6h 1 The blank regions 0100h to 01B2h and 01C0h to 02FFh EE SE 259 are reserved OFFFFh Optional Function Select Register OFS 104 250 Do not access locations in these regions 2tENESAS R8C 1A Group R8C 1B Group REJ09B0252 0130 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Rev 1 30 Dec 08 2006 1 Overview These MCUs are fabricated using the high performance silicon gate CMOS process embedding the R8C Tiny Series CPU co
131. ORER bit is set to 0 before restarting receive Figure 16 16 shows a Sample Flowchart of Data Reception MSS 1 Clock Synchronous Communication Mode e SSUMS 0 clock synchronous communication mode CPHS 0 data download at even edges and CPOS bit 0 H when clock stops ssok gUUlg UU lg O 1 frame RDFF bit in 1 SSSR register 0 D RXI interrupt request RXI interrupt request RSSTP bit in 1 generation generation SSCRH register 0 K RXI interrupt request generation Processing Dummy read in Read data in SSRDR Set RSSTP bit to 1 Read data in by program SSRDR register register SSRDR register Figure 16 15 Example of Clock Synchronous Serial I O with Chip Select Operation for Data Reception Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 187 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Start Initialization Dummy read of SSRDR register 1 After setting each register in the clock synchronous serial UO with chip select register a dummy read of the SSRDR register is performed and the receive operation is started Last data received 2 Determine whether it is the last 1 byte of data to be received If so set to stop after the data is received Read ORER bit in SSSR register 3 If a receive error occurs perform error 6 Processing after reading the ORER bit Then set the ORER bit to 0 Transmission reception c
132. P3_4 SCS SDA CMP1_1 SSU Refer to Table 16 4 Association between Communication Modes and I O Pins Function SCS Output SCS Input Control Control Register TCOUT4 0 Input port not pulled up Input port pulled up SCS input SDA input output Setting Value Output port Output port CMP1_1 output 1 SCS output 0 0 0 0 0 0 X 0or1 Table 5 14 Port P3_5 SSCK SCL CMP1_2 SSU Refer to Table 16 4 Association between Communication Modes and I O Pins Function SSCK Output SSCK Input Control Control Register 0 0 Input port not pulled up Input port pulled up SSCK input Setting SCL input output Value Output port Output port CMP1_2 output SSCK output X 0or1 Rev 1 30 Dec 08 2006 Page 350f315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports Table 5 15 Port P3_7 CNTRO SSO TXD1 SSU Refer to Table 16 4 Pag cin eee ete ucon and UO Pins Function BEEN Cer capes JEE Zeg 000b 0 0 OXb Input port not pulled up 000b 0 0 OXb Input port pulled up 000b 0 0 OXb Output port 001b E eg TXD1 output pin 110b 000b CNTRO output pin XXXb SSO input pin XXXb SSO output pin X 0 or 1 Table 5 16 Port XIN P4_6 XOUT P4_7 Reg
133. POS 1 L when clock stops SSO SSI CPHS and CPOS Bits in SSMR register SSUMS Bits in SSMR2 register Figure 16 10 Association between Transfer Clock Polarity Phase and Transfer Data Rev 1 30 Dec 08 2006 Page 180 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 2 SS Shift Register SSTRSR The SSTRSR register is a shift register for transmitting and receiving serial data When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to 0 MSB first the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register When the MLS bit is set to 1 LSB first bit 7 in the SSTDR register is transferred to bit 0 in the SSTRSR register 16 2 2 1 Association between Data I O Pins and SS Shift Register The connection between the data I O pins and SSTRSR register SS shift register changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register The connection also changes according to the BIDE bit in the SSMR2 register Figure 16 11 shows the Association between Data I O Pins and SSTRSR Register e SSUMS 0 e SSUMS 1 4 wire bus communication mode and clock synchronous communication mode BIDE 0 standard mode and MSS 1 operates as master device SSTRSR register SSTRSR register e SSUMS 1 4 wire bus communication mo
134. R bit is set to 1 overrun error while the TDRE bit is set to 1 data is transferred from registers SSTDR to SSTRSR the transmit receive operation is stopped When switching from transmit mode TE 1 or receive mode RE 1 to transmit receive mode Te RE 1 set the TE bit to 0 and RE bit to 0 before switching After confirming that the TEND bit is set to 0 the TDRE bit is set to 0 when the last bit of the transmit data is transmitted the RDRF bit is set to 0 no data in the SSRDR register and the ORER bit is set to 0 no overrun error set bits TE and RE to 1 Figure 16 17 shows a Sample Flowchart of Data Transmission Reception Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 189 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Initialization Read TDRE bit in SSSR register 1 After reading the SSSR register and confirming that the TDRE bit is set to 1 write the transmit data to the SSTDR register When the transmit data is written to the SSTDR register the TDRE bit is automatically set to 0 Yes Write transmit data to SSTDR register Read RDRPF bit in SSSR register bit is set to 1 read the receive data in the SSRDR register When the SSRDR register is read the RDRF bit is automatically set to 0 Yes Read receive data in SSRDR register Data transmission 3 Determine whether data transmission continues continues Read TEND bit
135. R8C 1B Group 14 Timers TCC14 TCC15 Compare 0 interrupt signal Compare 1 interrupt signal TCC16 TCC17 TCC17 to TCC16 11b CMP output internal signal Reverse Reverse TCC14 to TCC17 Bits in TCC1 register Figure 14 24 Block Diagram of CMP Waveform Generation Unit CMP output TCOUT6 0 PD1_0 Internal signal Q TCOUTO 1 TCOUTO O TCOUTO 0 Register TCOUT TCOUT CMP0_0 Output Bit TCOUTO J TCOUT6 SZ Setting Value 0 CMP0_0 waveform output CMPO D reversed waveform output oat GER This diagram is a block diagram of the CMP0_0 waveform output unit The CMP0_1 to CMP0_2 and CMP1_0 to CMP1_2 waveform output units have the same configuration Figure 14 25 Block Diagram of CMP Waveform Output Unit Rev 1 30 Dec 08 2006 Page 142 0f 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer C Register b15 b8 b7 b0 b7 Address After Reset 0091h 0090h 0000h Counts internal count source 0000h can be read when the TCCO0O bit is set to 0 count stops Count value can be read when the TCCO0 bit is set to 1 count starts Capture and Compare 0 Register b15 b8 b7 b0 b7 Address After Reset 009Dh 009Ch 0000h fs Function CER i d E the active edge of the measured Kee is input store RER the value in the TC register Function OS Setting Range Range Output compare a a a the value compared with timer C 0000h to FFFFh GER NOTES 1 When
136. RO2 bit in the FMRO register is set to 1 rewrite enabled and the FMR15 bit in the FMR1 register to 0 rewrite enabled block 0 is rewritable When the FMR16 bit is set to 0 rewrite enabled block 1 is rewritable only for CPU rewrite mode 2 This area is for storing the boot program provided by Renesas Technology Figure 18 1 Flash Memory Block Diagram for R8C 1A Group Rev 1 30 Dec 08 2006 Page 247 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 8 Kbyte ROM product 4 Kbyte ROM product Block A 1 Kbyte Block A 1 Kbyte Block B 1 Kbyte Block B 1 Kbyte 02BFFh Block 0 8 Kbytes Block 0 4 Kbytes User ROM area User ROM area 16 Kbyte ROM product 12 Kbyte ROM product 024008 Block A 1 Kbyte Block A 1 Kbyte Block B 1 Kbyte Block B 1 Kbyte Block 1 8 Kbytes Block 1 4 Kbytes Block 0 8 Kbytes Block 0 8 Kbytes User ROM area User ROM area NOTES 18 Flash Memory Data flash Program ROM Data flash Program ROM OE000h 8 Kbytes OFFFFh Boot ROM area reserved area 1 When the FMRO2 bit in the FMRO register is set to 1 rewrite enabled and the FMR15 bit in the FMR1 register to 0 rewrite enabled block 0 is rewritable When the FMR16 bit is set to 0 rewrite enabled block 1 is rewritable only for CPU rewrite mode 2 This area is for storing the boot program provided by Renesas Technology Figure 18 2 Flash Memory Block Diagram f
137. Rev 1 30 Dec 08 2006 Page 307 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 8 Notes on Noise 20 8 1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch Up Connect a bypass capacitor at least 0 1 uF using the shortest and thickest wire possible 20 8 2 Countermeasures against Noise Error of Port Control Registers During rigorous noise testing or the like external noise mainly power supply system noise can exceed the capacity of the MCU s internal noise control circuitry In such cases the contents of the port related registers may be changed As a firmware countermeasure it is recommended that the port registers port direction registers and pull up control registers will be reset periodically However examine the control processing fully before introducing the reset routine as conflicts may be created between the reset routine and interrupt routines Rev 1 30 Dec 08 2006 Page 308 of 315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 21 Notes on On Chip Debugger 21 Notes on On Chip Debugger When using on chip debugger to develop and debug programs for the R8C 1A Group and R8C 1B Group take note of the following 1 Do not access the related UART1 registers 2 Some of the user flash memory and RAM areas are used by the on ship debugger These areas cannot be accessed by the user Refer to the on chip debugger manual for which ar
138. Selects PC bus function Figure 5 8 PMR Register Rev 1 30 Dec 08 2006 Page 300f315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports Pull Up Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOFCh 00XX0000b Bit Symbol W b1 b0 Reserved bits Set to 0 P1_0 to P1_3 pull up 0 Not pulled up P1_4 to P1_7 pull up 1 Pulled up Nothing is assigned If necessary set to 0 b5 b4 When read the content is undefined P3_3 pull up 0 Not pulled up 3 4 to P3 5 and P3_7 pll up S ulled up 1 When this bit is set to 1 pulled up the pin w hose direction bit is set to 0 input mode is pulled up Pull Up Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOFDh XXXXXX0Xb Bit Symbol Nothing is assigned If necessary set to 0 b0 When read the content is undefined P4_5 pull up 0 Not pulled up Nothing is assigned If necessary set to 0 b7 b2 When read the content is undefined NOTE 1 When the PU11 bit is set to 1 pulled up and the PD4_5 bit is set to 0 input mode the P4_5 pin is pulled up Figure 5 9 Registers PURO and PUR1 Port P1 Drive Capacity Control Register b7 b6 b5 b4 b3 b2 b1 bO Address After Reset OOFEh Dm Pi Zare capacity Figure 5 10 DRR Register Rev 1 30 Dec 08 2006 Page 310f315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports 5 4 Port Setti
139. Specifications of Clock Generation Circuit Figure 10 1 shows a Clock Generation Circuit Figures 9 2 to 10 5 show clock associated registers Table 10 1 Hem Main Clock Oscillation Circuit Specifications of Clock Generation Circuit On Chip Oscillator High Speed On Chip Oscillator Low Speed On Chip Oscillator Applications e CPU clock source e Peripheral function clock source e CPU clock source e Peripheral function clock source e CPU and peripheral function clock sources when main clock stops oscillating e CPU clock source e Peripheral function clock source e CPU and peripheral function clock sources when main clock stops oscillating Clock frequency 0 to 20 MHz Approx 8 MHz Approx 125 kHz Connectable oscillator e Ceramic resonator e Crystal oscillator Oscillator connect pins XIN XOUT Note 1 Note 1 Oscillation stop restart function Usable Usable Usable Oscillator status after reset Stop Stop Oscillate Others NOTE Externally generated clock can be input 1 These pins can be used as P4_6 or P4_7 when using the on chip oscillator clock as the CPU clock while the main clock oscillation circuit is not used Dec 08 2006 Page 580f315 stENESAS R8C 1A Group R8C 1B Group 10 Clock Generation Circuit HRA register HRA2 register On chip oscillator clock Frequency adjustable R HRA00 Watc
140. TCCO register to 0 INT3 When the TCC06 bit in the TCCO register is set to 0 an INT3 interrupt request is generated in synchronization with the count source of timer C If the TCC06 bit is set to 1 the INT3 interrupt request is generated when an INT3 input occurs The INT3 input contains a digital filter The INT3 level is sampled every sampling clock cycle and if the sampled input level matches three times the IR bit in the INT3IC register is set to 1 interrupt requested The sampling clock is selected by bits TCC11 to TCC10 in the TCC1 register If filter is selected the interrupt request is generated in synchronization with the sampling clock even if the TCC06 bit is set to 1 The P3_3 bit in the P3 register indicates the value before filtering regardless of the contents set in bits TCC11 to TCC10 The INT3 pin is used with the TCIN pin If the TCCO7 bit is set to 1 RING128 the INT3 interrupt is generated by the fRING128 clock The IR bit in the INT3IC register is set to 1 interrupt requested every fRING128 clock cycle or every half fRING128 clock cycle Figure 12 15 shows the TCCO Register and Figure 12 16 shows the TCC1 Register Timer C Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 009Ah 00h SECH Timer C count start bit 0 Stops counting 1 Starts counting Timer C count source select bits TCCO1 0 f1 f8 f32 FRING fast D RW RW RW RW RW INT3 interrupt and capture Rising edg
141. TEE 204 SSORL unsere ENEE 173 Ier EE 206 SSER ees eeeeesseteeeeeeeeeetsenneeeeetenneeteeeenans 175 INTOF een 91 SSMR EE 174 INTOIG egene Eet 84 SSMR2 E 177 INT dE 83 SSRDR ooeeessseessseeesseeeeseeeesneeeenneensnateennaes 178 INT3IC ebben 83 SSSR E 176 IEN 91 SSTDR sseeeesseteeeeesseteteesennneeeteeenneneeessnans 178 Rev 1 30 Dec 08 2006 Page 314 0f 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Register Index T TG pakistani dined 143 TOGO EE 144 Ree 145 NCIC a E A GEN 83 Ree NEE 146 TOSS EE 111 127 TMO ET 143 UCNE 143 REG 111 RAL 83 TAM EE 110 EA 83 TZM EE 124 EE 126 El EE 125 EE 125 U HORN 2 ietuebtteeudegsesiueeetseie eege 154 BEE eege eege 156 VOG Iisa easiness asenaan 157 VOMR ona e a S 155 VORB EE 154 WOT B resita cernteivatannt 154 UTBRG perotis aaeeea 154 WIC WE 156 UN Le 157 WAM fs etsscte nition rnnr eared eeng 155 UTRB cunnairt 154 WIT Bsa E E eege eege 154 HCON eet Seree ged deeg eeeEeE EEN 157 V M ie ege ge SE 47 VIS 47 VAN 48 VAN 49 W NEIE sorene 104 WTR wesc tevrercestestitl cenenetiuiastebents 105 KOLBET 105 Rev 1 30 Dec 08 2006 Page 3150f315 stENESAS REJ09B0252 0130 REVISION HISTORY R8C 1A Group R8C 1B Group Hardware Manual Description Summary Table 1 2 Performance Outline of the R8C 1B Group Flash Memory Data area Data flash Program area Program ROM revised Figure 1 1 Block Diagram Peripheral Function added Syste
142. Table 5 13 Port P3_4 SCS SDA CMP1_1 Setting SCS gt SCS Table 5 14 Port P3_5 SSCK SCL CMP1_2 Setting SSK gt SSCK REVISION HISTORY R8C 1A Group R8C 1B Group Hardware Manual Description Summary 1 00 Sep 09 2005 Table 5 18 Unassigned Pin Handling Figure 5 11 Unassigned Pin Handling Port P4_2 P4_6 P4_7 gt Port P4_6 P4_7 VREF Port P4_2 VREF revised Table 9 2 Bus Cycles for Access Space of the R8C 1B Group added Table 9 3 Access Unit and Bus Operation SFR gt SFR Data flash ROM RAM Program ROM ROM RAM revised 10 2 1 Low speed On Chip Oscillator Clock The application products to accommodate the frequency range gt The application products for the frequency change revised 10 2 2 High Speed On Chip Oscillator Clock The high speed on chip oscillator frequency for details added 10 5 1 How to Use Oscillation Stop Detection Function This function cannot is 2 MHz or below gt This function cannot be is below 2 MHz revised Figure 10 9 Procedure of Switching Clock Source From Low Speed On Chip Oscillator to Main Clock revised 10 6 2 Oscillation Stop Detection Function Since the oscillation frequency is 2MHz or below gt Since the oscillation frequency is below 2MHz revised 10 6 4 High Speed On Ship Oscillator Clock added Figure 12 10 Judgement Circu
143. Timer X for precautions regarding the TXS bit Figure 14 9 TXMR Register in Pulse Period Measurement Mode Rev 1 30 Dec 08 2006 Page 1200f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Underflow signal of prescaler X Set to 1 by program TXS bit in TXMR register Starts counting CNTROi pin input Timer X reloads Timer X reloads H H 1 H H 1 1 1 H 1 1 1 H 1 1 H H 1 1 1 H Contents of timer X OFh OEh ODh OFh OE ODh OCh OBh OA 09h OFh OEh ODh Retained Retained Contents of read out buffer1 09h ODh OBh OAh Gen X read Timer X read 2 TXEDG bit in TXMR register Timer X reloads ae aer Set to 0 by program TXUND bit in TXMR register Set to 0 by program IR bit in TXIC register Set to 0 when interrupt request is acknowledged or set by program IR bit in INT1IC register Gs Set to 0 when interrupt request is acknowledged or set by program J Conditions The period from one rising edge to the next rising edge of the measured pulse is measured ROEDG 0 with the default value of the TX register as OFh i Oto1 NOTES The contents of the read out buffer can be read by reading the TX register in pulse period measurement mode After an active edge of the measured pulse is input the TXEDG bit in the TXMR register is set to 1 active edge found
144. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 17 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry w N E SAS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is gran
145. UOMR register 0 Input transfer clock CKDIR bit in UOMR register 1 PD1_6 bit in PD1 register 0 Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 159 of 315 stENESAS R8C 1A Group R8C 1B Group 15 Serial Interface Example of transmit timing when internal clock is selected TC e wennen UU UUU r e a Ir Sea K Transfer from UOTB register to UARTO transmit register TCLK Pulse stops because the TE bit is set to 0 gt La r i i i i H DO D1 D2 D3 D4 D5 D6 D7 DO D1 D2 D3 4 osf oey TXEPT bit in UOC0 register i i i i IR bit in SOTIC j register Ee Set to 0 when interrupt request is acknowledged or set by a program TC TCLK 2 n 1 fi fi Frequency of UOBRG count source f1 f8 f32 The above applies under the following settings n Setting value to UOBRG register CKDIR bit in UOMR register 0 internal clock CKPOL bit in UOCO register 0 output transmit data at the falling edge and input receive data at the rising edge of the transfer clock UOIRS bit in UCON register 0 an interrupt request is generated when the transmit buffer is empty Example of receive timing when external clock is selected RE bitin UOC1 4 register TE bit in UOC1 register Write dummy data to UOTB register TI bit in UOC1 registe
146. Vdet2 gt Vdett Rev 1 30 Dec 08 2006 Page 280 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 8 Reset Circuit Electrical Characteristics When Using Voltage Monitor 1 Reset Symbol Parameter Condition Standard Vpor2 Power on reset valid voltage 20 C lt Topr lt 85 C tw Vpor2 Vdet1 Supply voltage rising time when power on reset is 20 C lt Topr lt 85 C deasserted tw por2 gt Del NOTES 1 This condition is not applicable when using with Vcc 1 0 V 2 When turning power on after the time to hold the external power below effective voltage Vpor1 exceeds10 s refer to Table 19 9 Reset Circuit Electrical Characteristics When Not Using Voltage Monitor 1 Reset 3 tw por2 is the time to hold the external power below effective voltage Vpor2 Table 19 9 Reset Circuit Electrical Characteristics When Not Using Voltage Monitor 1 Reset Symbol Parameter Condition Standard Typ Vport Power on reset valid voltage 20 C lt Topr lt 85 C tw Vpor Supply voltage rising time when power on reset is 0 C lt Topr lt 85 C deasserted tw port gt 10 s tw Vpor Supply voltage rising time when power on reset is 20 C lt Topr lt 0 C deasserted tw port gt 30 s 2 tw Vpor Supply voltage rising time when power on reset is 20 C lt Topr lt 0 C deasserted tw port gt 10 s 2 tw Vpor Supply voltage rising time wh
147. Waveform Waveform Wavefo rm Waveform output starts output ends output starts output ends TZOUT pin input The above applies under the following conditions PREZ 01h TZPR 01h TZOPL bit in PUM register 0 INOSTG bit 1 INTO one shot trigger enabled INOSEG bit 1 rising edge trigger Figure 14 20 Operating Example in Programmable One Shot Generation Mode Rev 1 30 Dec 08 2006 Page 135 0f 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 2 4 Programmable Wait One Shot Generation Mode In programmable wait one shot generation mode a one shot pulse is output from the TZOUT pin by a program or an external trigger input input to the INTO pin refer to Table 14 10 Programmable Wait One Shot Generation Mode Specifications When a trigger is generated from that point the timer outputs a pulse only once for a given length of time equal to the setting value in the TZSC register after waiting for a given length of time equal to the value set in the TZPR register Figure 14 21 shows Registers TZMR and PUM in Programmable Wait One Shot Generation Mode Figure 14 22 shows an Operating Example in Programmable Wait One Shot Generation Mode Rev 1 30 Dec 08 2006 Page 136 of 315 pRENESAS REJ09B0252 0130 Rev 1 30 REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Table 14 10 Programmable Wait One Shot Generation Mode Specifications Hem Specification Count sources f1 f2 f8 Tim
148. When an interrupt request is generated the FMR42 bit is automatically set to 1 request program suspend and the auto program operation suspends When the auto program operation does not complete FMRO0 bit is 0 after the interrupt process completes the auto program operation can be restarted by setting the FMR42 bit to 0 programming restarts Rev 1 30 Dec 08 2006 Page 252 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Figure 18 5 shows the FMRO Register Figure 18 7 shows the FMR4 Register 18 4 2 1 FMROO Bit This bit indicates the operating status of the flash memory The bits value is 0 during programming or erasure suspend term included otherwise it is 1 18 4 2 2 FMRO01 Bit The MCU is made ready to accept commands by setting the FMRO1 bit to 1 CPU rewrite mode 18 4 2 3 FMRO2 Bit Rewriting of blocks 1 and 0 does not accept the program or block erase commands if the FMRO2 bit is set to 0 rewrite disabled Rewriting of blocks 0 and 1 is controlled by bits FMR15 and FMR16 if the FMRO2 bit is set to 1 rewrite enabled 18 4 2 4 FMSTP Bit This bit is used to initialize the flash memory control circuits and also to reduce the amount of current consumed by the flash memory Access to the flash memory is disabled by setting the FMSTP bit to 1 Therefore the FMSTP bit must be written to by a program located outside of the flash memory In the following cases set the FMSTP bit to 1
149. _0 to P1_7 Input port P1 Input H or L level signal or leave the pin open P3_3 to P3_5 P3_7 Input port P3 Input H or L level signal or leave the pin open P4_2 VREF P4_5 Input port P4 Input H or L level signal or leave the pin open MODE MODE Serial data I O pin Connect to flash programmer Rev 1 30 Dec 08 2006 Page 270 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Connect oscillator circuit CHE Gl O8y VL 98H Package PLSP0020JB A NOTE 1 It is not necessary to connect an oscillating circuit Mode Setting when operating with the on chip oscillator clock Value Voltage from programmer VSS gt VCC Figure 18 17 Pin Connections for Standard Serial UO Mode 3 Rev 1 30 Dec 08 2006 Page 271 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 5 1 1 Example of Circuit Application in Standard Serial UO Mode Figure 18 18 shows an example of Pin Processing in Standard Serial I O Mode 2 and Figure 18 19 shows Pin Processing in Standard Serial I O Mode 3 Since the controlled pins vary depending on the programmer refer to the manual of your serial programmer for details Data Output Data input NOTES 1 In this example modes are switched between single chip mode and standard serial I O mode by controlling the MODE i
150. acknowledgement VW2C6 0 ra Set to 0 by a program VW2C2 bit Set to 0 by interrupt a set to 1 digital filter Voltage monitor 2 a request acknowledgement disabled and the interrupt request VW2C7 bit is set to 1 VW2C6 0 When the VW2C1 bit is Vdet2 or below Internal reset signal VW2C6 1 VCA13 Bit in VCA1 register VW2C1 VW2C2 VW2C6 VW2C7 Bit in VW2C register The above applies under the following conditions VCA27 bit in VCA2 register 1 voltage detection 2 circuit enabled VW2C0 bit in VW2C register 1 voltage monitor 2 interrupt and voltage monitor 2 reset enabled NOTE 1 If voltage monitor 1 reset is not used set the power supply to VCC gt 2 7 Figure 7 9 Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Rev 1 30 Dec 08 2006 Page 54 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 8 Processor Mode 8 Processor Mode 8 1 Processor Modes Single chip mode can be selected as the processor mode Table 8 1 lists Features of Processor Mode Figure 8 1 shows the PMO Register and Figure 8 2 shows the PM1 Register Table 8 1 Features of Processor Mode Processor Mode Accessible Areas Pins Assignable as I O Port Pins Single chip mode SFR internal RAM internal ROM All pins are I O ports or peripheral function I O pins Processor Mode Register 0 b7 b6 b5 b4 b3 b2 bi bd Address After Reset 0004h 00h SE Reserved bits S
151. age 304 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 6 Notes on A D Converter e Write to each bit other than bit 6 in the ADCONO register each bit in the ADCON I register or the SMP bit in the ADCON2 register when A D conversion is stopped before a trigger occurs e When the VCUT bit in the ADCONI register is changed from 0 VREF not connected to 1 VREF connected wait for at least 1 us before starting A D conversion e After changing the A D operating mode select an analog input pin again e When using the one shot mode ensure that A D conversion is completed before reading the AD register The IR bit in the ADIC register or the ADST bit in the ADCONDO register can be used to determine whether A D conversion is completed e When using the repeat mode use the undivided main clock as the CPU clock e If the ADST bit in the ADCONDO register is set to 0 A D conversion stops by a program and A D conversion is forcibly terminated during an A D conversion operation the conversion result of the A D converter will be undefined If the ADST bit is set to 0 by a program do not use the value of the AD register Rev 1 30 Dec 08 2006 Page 305 of 315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 7 Notes on Flash Memory 20 7 1 CPU Rewrite Mode 20 7 1 1 Operating Speed Before entering CPU rewrite mode EWO mode select 5 MHz or below for the CPU clock using the CM06
152. annot No be restarted while the ORER bit is set to 1 Read RDRF bit in SSSR register 4 Confirm that the RDRF bit is set to 1 If the RDRF bit is set to 1 read the receive data in the SSRDR register When the SSRDR register is read the RDRF bit is automatically set to 0 Yes Read receive data in SSRDR register SSCRH register RSSTP bit lt 1 5 Before the last 1 byte of data is received set the RSSTP bit to 1 and stop after the data is received Read ORER bit in SSSR register Yes No Read RDRF in SSSR register 7 Confirm that the RDRF bit is set to 1 When the receive operation is completed set the RSSTP bit to 0 and the RE bit to 0 before reading the last 1 byte of data If the SSRDR register is read before setting the RE bit to 0 the receive operation is restarted SSCRH register RSSTP bit lt 0 again Overrun SSER register RE bit lt 0 error processing Read receive data in SSRDR register Figure 16 16 Sample Flowchart of Data Reception MSS 1 Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 188 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 5 4 Data Transmission Reception Data transmission reception is an operation combining data transmission and reception which were described earlier Transmission reception is started by writing data to the SSTDR register When the 8th clock rises or the ORE
153. any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in
154. arity select bit 0 Falling edge 1 Rising edge KIB input enable bit 0 Disable 1 Enable KD input polarity select bit 0 Falling edge Gei H 1 Rising edge NOTE 1 The IR bit in the KUPIC register may be set to 1 requests interrupt w hen the KIEN register is rew ritten Refer to 12 5 5 Changing Interrupt Sources RW RW RW RW RW RW RW W Figure 12 18 KIEN Register Rev 1 30 Dec 08 2006 Page 970f315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register i 0 1 This interrupt is used as a break function by the debugger When using the on chip debugger do not set an address match interrupt registers of AIER RMADO and RMAD1 and fixed vector tables in a user system Set the starting address of any instruction in the RMADi register Bits ATERO and AIER1 in the AIERO register can be used to select enable or disable of the interrupt The I flag and IPL do not affect the address match interrupt The value of the PC Refer to 12 1 6 7 Saving a Register for the value of the PC which is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMADi register The appropriate return address is not saved on the stack When returning from the address match inter
155. asured pulse input INT3 interrupt input Di Oto P1 2 P3 3to P3_5 pin functions Programmable I O port Counter value reset timing When the TCCO0 bit in the TCCO register is set to 0 count stops Read from timer 2 e The count value can be read out by reading the TC register e The count value at the measured pulse active edge input can be read out by reading the TMO register Write to timer Write to the TC and TMO registers is disabled Select functions NOTES e INT3 TGIN polarity select function Bits TCC03 to TCC04 can select the active edge of the measured pulse e Digital filter function Bits TCC11 to TCC10 can select the digital filter sampling frequency e Trigger select function The TCCO7 bit can select the TCIN input or the fRING128 1 The INT3 interrupt includes a digital filter delay and one count source max delay 2 Read registers TC and TMO in 16 bit unit Dec 08 2006 Page 147 of 315 stENESAS R8C 1A Group R8C 1B Group 14 Timers Overflow Count starts rer Counter contents hex Measurement lt H T lt Measurement value value3 Set to 0 by Time Set to 1 by program program TCCO0 bit in f f TCCO register The delay caused by digital filter and one count source cycle delay max N Transmit Cl Transmit l Transmit CR SE measured value 1 value 2 value 3 Transmit timing from ye Va timer C counter to TMO register Measured
156. ata When clock synchronous serial I O with chip select is set as a slave device it inputs data synchronized with the input clock When clock synchronous serial I O with chip select is set as a master device it outputs a receive clock and starts receiving by performing dummy read of the SSRDR register After 8 bits of data are received the RDRF bit in the SSSR register is set to 1 data in the SSRDR register and receive data is stored in the SSRDR register When the RIE bit in the SSER register is set to 1 RXI and OEI interrupt requests enabled the RXI interrupt request is generated If the SSDR register is read the RDRF bit is automatically set to 0 no data in the SSRDR register Read the receive data after setting the RSSTP bit in the SSCRH register to 1 after receiving 1 byte of data the receive operation is completed Clock synchronous serial I O with chip select outputs a clock for receiving 8 bits of data and stops After that set the RE bit in the SSER register to 0 receive disabled and the RSSTP bit to O receive operation is continued after receiving the 1 byte of data and read the receive data If the SSRDR register is read while the RE bit is set to 1 receive enabled a receive clock is output again When the 8th clock rises while the RDRF bit is set to 1 the ORER bit in the SSSR register is set to 1 overrun error OED and the operation is stopped When the ORER bit is set to 1 receive cannot be performed Confirm that the
157. ata format e Transfer data length 8 bits Transfer clocks e CKDIR bit in UOMR register is set to 0 internal clock fi 2 n 1 fi f1 f8 f32 n value set in UOBRG register 00h to FFh e The CKDIR bit is set to 1 external clock input from CLKO pin Transmit start conditions e Before transmission starts the following requirements must be met 1 The TE bit in the U0C1 register is set to 1 transmission enabled The TI bit in the UOC1 register is set to 0 data in the UOTB register Receive start conditions e Before reception starts the following requirements must be met 1 The RE bit in the UOC1 register is set to 1 reception enabled The TE bit in the UOC1 register is set to 1 transmission enabled The TI bit in the UOC1 register is set to O data in the UOTB register Interrupt request e When transmitting one of the following conditions can be selected generation timing The UOIRS bit is set to 0 transmit buffer empty When transferring data from the UOTB register to UARTO transmit register when transmission starts The UOIRS bit is set to 1 transmission completes When completing data transmission from UARTi transmit register e When receiving When data transfer from the UARTO receive register to the UORB register when reception completes Error detection e Overrun error 2 This error occurs if the serial interface starts receiving the next data item before reading the UORB register and receives the 7th bit
158. ated Registers Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIERO RMADO Address match interrupt 1 AIER1 RMAD1 Rev 1 30 Dec 08 2006 Page 98 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0009h 00h Bit Symbol AIERO Address match interrupt 0 enable bit 0 Disable RW 1 Enable Address match interrupt 1 enable bit 0 Disable Nothing is assigned If necessary set to 0 b7 b2 When read the content is 0 Address Match Interrupt Register i i 0 1 b23 b19 b16 b15 b8 b7 b3 b0 bi b0 b7 Address After Reset 0012h 0010h X00000h 0016h 0014h X00000h A ddress setting register for address match interrupt 00000h to FFFFFh Nothing is assigned If necessary set to 0 b7 b4 When read the content is undefined Figure 12 19 Registers AIER and RMADO to RMAD1 Rev 1 30 Dec 08 2006 Page990f315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 5 Notes on Interrupts 12 5 1 Reading Address 00000h Do not read address 00000h by a program When a maskable interrupt request is acknowledged the CPU reads interrupt information interrupt number and interrupt request level from 00000h in the interrupt sequence At this time the acknowledged interrupt IR bit is set to 0 If a
159. bit in the CMO register and bits CM16 to CM17 in the CM1 register This does not apply to EW1 mode 20 7 1 2 Prohibited Instructions The following instructions cannot be used in EWO mode because they reference data in the flash memory UND INTO and BRK 20 7 1 3 Interrupts Table 20 1 lists the EWO Mode Interrupts and Table 20 2 lists the EW1 Mode Interrupts Table 20 1 EWO Mode Interrupts When Watchdog Timer Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request is Acknowledged During auto erasure Any interrupt can be used Once an interrupt request is acknowledged by allocating a vector in auto programming or auto erasure is RAM forcibly stopped immediately and the flash memory is reset Interrupt handling starts after the fixed period and the flash memory restarts Since the block during auto erasure or the address during auto programming is forcibly stopped the Auto programming normal value may not be read Execute auto erasure again and ensure it completes normally Since the watchdog timer does not stop during the command operation interrupt requests may be generated Reset the watchdog timer regularly When Maskable Interrupt Status Request is Acknowledged NOTES 1 Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM 2 Do not use a non maskable interrupt while block 0 is being automaticall
160. bit to 0 no conflict error before starting transmission SCS input Internal SCS synchronization MSS bit in SSCRH register Transfer start ata write to STDR register Maximum time of SCS internal synchronization During arbitration detection Figure 16 21 Arbitration Check Timing Rev 1 30 Dec 08 2006 Page 197 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 8 Notes on Clock Synchronous Serial I O with Chip Select Set the ITCSEL bit in the PMR register to 0 select clock synchronous serial I O with chip select function to use the clock synchronous serial I O with chip select function 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial UO with Chip Select After waiting three instructions or more after writing to the registers associated with clock synchronous serial I O with chip select QOB8h to OOBFh or four cycles or more after writing to them read the registers e An example of waiting three instructions or more Program example MOV B 00h 00BBh Set the SSER register to 00h NOP NOP NOP MOV B OOBBh ROL e An example of waiting four cycles or more Program example BCLR 4 00BBh Disable transmission JMP B NEXT NEXT BSET 3 00BBh Enable reception 16 2 8 2 Selecting SSI Signal Pin Set the SOOS bit in the SSMR2 register to 0 CMOS output in the following settings SSUMS bit in SSMR2 register 1 4 wire bus
161. bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode When the slave address matches at the Ist frame after detecting the start condition the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock cycle At this time if the 8th bit of data R W is 1 bits TRS and TDRE in the ICSR register are set to 1 and the mode is switched to slave transmit mode automatically Continuous transmission is enabled by writing transmit data to the ICDRT register every time the TDRE bit is set to 1 When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT register wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1 When the TEND bit is set to 1 set the TEND bit to 0 The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR register to end the process Set the TDRE bit to 0 Dec 08 2006 Page 217 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Slave receive mode nl Slave transmit mode SCL master output SDA master output SCL slave output SDA slave output TDRE bit i ICSR regis TEND bit i ICSR regis TRS bi ICCR1 regis ICDRT regis ICDRS regis ICDRR regis 2 Data write to ICDRT register data 3 Pr
162. bits x 1 channel timer Z 8 bits x 1 channel Each timer equipped with 8 bit prescaler Timer C 16 bits x 1 channel Input capture and output compare circuits Serial interfaces 1 channel Clock synchronous serial I O UART 1 channel UART Clock synchronous serial interface 1 channel 12C bus Interface Clock synchronous serial I O with chip select SSU A D converter 10 bit A D converter 1 circuit 4 channels Watchdog timer 15 bits x 1 channel with prescaler Reset start selectable count source protection mode Interrupts Internal 11 sources External 4 sources Software 4 sources Priority levels 7 levels Clock generation circuits 2 circuits e Main clock oscillation circuit with on chip feedback resistor e On chip oscillator high speed low speed High speed on chip oscillator has a frequency adjustment function Oscillation stop detection function Main clock oscillation stop detection function Voltage detection circuit On chip Power on reset circuit On chip Electric Supply voltage VCC 3 0 to 5 5 V f XIN 20 MHz Characteristics VCC 2 7 to 5 5 V f XIN 10 MHz Current consumption Typ 9 mA VCC 5 0 V f XIN 20 MHz A D converter stopped Typ 5 mA VCC 3 0 V f XIN 10 MHz A D converter stopped Typ 35 pA VCC 3 0 V wait mode peripheral clock off Typ 0 7 uA VCC 3 0 V stop mode Flash Memory Programming and erasure voltage VCC 2 7 to 5 5 V Programming and erasure 100 times endurance Operating
163. bits x 1 channel with prescaler Reset start selectable count source protection mode Interrupts Internal 11 sources External 4 sources Software 4 sources Priority levels 7 levels Clock generation circuits 2 circuits e Main clock generation circuit with on chip feedback resistor e On chip oscillator high speed low speed High speed on chip oscillator has a frequency adjustment function Oscillation stop detection function Main clock oscillation stop detection function Voltage detection circuit On chip Power on reset circuit On chip Electric Supply voltage VCC 3 0 to 5 5 V f XIN 20 MHz Characteristics VCC 2 7 to 5 5 V f XIN 10 MHz Current consumption Typ 9 mA VCC 5 0 V f XIN 20 MHz A D converter stopped Typ 5 mA VCC 3 0 V f XIN 10 MHz A D converter stopped Typ 35 pA VCC 3 0 V wait mode peripheral clock off Typ 0 7 pA VCC 3 0 V stop mode Flash Memory Programming and erasure voltage VCC 2 7 to 5 5 V Programming and erasure 10 000 times data flash endurance 1 000 times program ROM Operating Ambient Temperature 20 to 85 C 40 to 85 C D version 20 to 105 C Y version 2 Package 20 pin molded plastic LSSOP 20 pin molded plastic SDIP 28 pin molded plastic HWQFN NOTE 1 12C bus is a trademark of Koninklijke Philips Electronics N V 2 Please contact Renesas Technology sales offices
164. ble interrupt Refer to Table 12 2 Relocatable Vector Tables for sources of the peripheral function interrupt For details of peripheral functions refer to the descriptions of individual peripheral functions Rev 1 30 Dec 08 2006 Page 80 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 5 Interrupts and Interrupt Vectors There are 4 bytes in each vector Set the starting address of an interrupt routine in each interrupt vector When an interrupt request is acknowledged the CPU branches to the address set in the corresponding interrupt vector Figure 12 2 shows an Interrupt Vector Vector address L Mid address Vector address H Figure 12 2 12 1 5 1 High address Interrupt Vector Fixed Vector Tables The fixed vector tables are allocated addresses OFFDCh to OFFFFh Table 12 1 lists the Fixed Vector Tables The vector addresses H of fixed vectors are used by the ID code check function For details refer to 18 3 Functions to Prevent Rewriting of Flash Memory Table 12 1 Interrupt Source Undefined instruction Overflow Fixed Vector Tables Vector Addresses Address L to H Remarks Reference OFFDCh to OFFDFh OFFEOh to OFFE3h Interrupt on UND instruction Interrupt on INTO instruction BRK instruction OFFE4h to OFFE7h If the content of address OFFE7h is FFh program execution starts from the address shown by the vector in the rel
165. ble 14 1 Functional Comparison of Timers Timer X Timer Z Timer C Configuration 8 bit timer with 8 bit prescaler with reload register 8 bit timer with 8 bit prescaler with reload register 16 bit free run timer with input capture and output compare Count Decrement Decrement Increment Count sources Ma We WG e IRING ft Wi f8 e Timer X underflow Wa WG e f32 e fRING fast Timer mode Provided Provided Not provided Pulse output mode Provided Not provided Not provided Event counter mode Provided Not provided Not provided Pulse width measurement mode Provided Not provided Not provided Pulse period measurement mode Provided Not provided Not provided Programmable waveform generation mode Not provided Provided Not provided Programmable one shot generation mode Not provided Provided Not provided Programmable wait one shot generation mode Not provided Provided Not provided Input capture mode Not provided Not provided Provided Output compare mode Not provided Not provided Provided Input pin CNTRO INTO TCIN Output pin CNTRO CNTRO TZOUT CMP0_0 to CMPO_2 CMP1_0to CMP1_2 Related interrupt Timer X interrupt INT1 interrupt Timer Z interrupt INTO interrupt Timer C interrupt INTS interrupt Compare 0 interrupt Com
166. ble and interrupt routine for interrupts to be used should be allocated to the RAM area 2 td SR SUS is needed until the interrupt request is acknowledged after it is generated The interrupt to enter suspend should be in interrupt enabled status 3 When no interrupt is used the instruction to enable interrupts is not needed Figure 18 13 Program Command When Suspend Function Enabled Rev 1 30 Dec 08 2006 Page 263 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 3 5 Block Erase When 20h is written in the first bus cycle and DOh is written to a given address of a block in the second bus cycle an auto erase operation erase and verify of the specified block starts The FMROO0 bit in the FMRO register can be used to determine whether auto erasure has completed The FMRO0 bit is set to 0 during auto erasure and set to 1 when auto erasure completes The FMR07 bit in the FMRO register can be used to determine the result of auto erasure after auto erasure has completed Refer to 18 4 5 Full Status Check When the FMRO2 bit in the FMRO register is set to 0 rewriting disabled or the FMRO2 bit is set to 1 rewriting enabled and the FMR15 bit in the FMRI register is set to 1 rewriting disabled the block erase commands targeting block 0 are not acknowledged When the FMR 16 bit is set to 1 rewriting disabled the block erase commands targeting block 1 are not acknowledged Do not use the block
167. bles w riting 1 Enables writing Reserved bits Set to 0 b5 b4 Reserved bits When read the content is 0 b7 b6 Figure 11 1 PRCR Register ee bit Set to 0 z Rev 1 30 Dec 08 2006 Page 77 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 Interrupts 12 1 Interrupt Overview 12 1 1 Types of Interrupts Figure 12 1 shows the types of Interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction Software non maskable interrupt Interrupt lt Watchdog timer Oscillation stop detection Special lt __ Voltage monitor 2 non maskable interrupt Single step Hardware Address match Peripheral function maskable interrupt NOTES 1 Peripheral function interrupts in the MCU are used to generate peripheral interrupts 2 Do not use this interrupt This is for use with development tools only Figure 12 1 Interrupts e Maskable interrupts The interrupt enable flag I flag enables or disables these interrupts The interrupt priority order can be changed based on the interrupt priority level e Non maskable interrupts The interrupt enable flag I flag does not enable or disable interrupts The interrupt priority order cannot be changed based on interrupt priority level Rev 1 30 Dec 08 2006 Page 78 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts
168. block as possible is used up before performing an erase operation For example when programming groups of 16 bytes the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation In addition averaging the number of erase operations between block A and block B can further reduce the effective number of rewrites It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number If an error occurs during block erase attempt to execute the clear status register command then execute the block erase command at least three times until the erase error does not occur Customers desiring programming erasure failure rate information should contact their Renesas technical support representative The data hold time includes time that the power supply is off or the clock is not supplied Dec 08 2006 Page 278 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 5 Flash Memory Data flash Block A Block B Electrical Characteristics Standard Symbol Parameter Conditions Min Typ Max Unit Program erase endurance 2 10 000 3 times Byte program time 50 400 us Program erase endurance lt 1 000 times Byte program time 65 8 us Program erase endurance gt 1 000 times Block erase time 0 2 9 s Program erase endurance
169. c 08 2006 Page 253 of 315 seRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 2 10 FMR40 Bit The suspend function is enabled by setting the FMR40 bit to 1 enable 18 4 2 11 FMR41 Bit In EWO mode the MCU enters erase suspend mode when the FMR41 bit is set to 1 by a program The FMR41 bit is automatically set to 1 request erase suspend when an interrupt request of an enabled interrupt is generated in EW1 mode and then the MCU enters erase suspend mode Set the FMR41 bit to 0 erase restarts when the auto erase operation restarts 18 4 2 12 FMR42 Bit In EWO mode the MCU enters program suspend mode when the FMR42 bit is set to 1 by a program The FMR42 bit is automatically set to 1 request program suspend when an interrupt request of an enabled interrupt is generated in EW1 mode and then the MCU enters program suspend mode Set the FMR42 bit to 0 program restart when the auto program operation restarts 18 4 2 13 FMR43 Bit When the auto erase operation starts the FMR43 bit is set to 1 erase execution in progress The FMR43 bit remains set to 1 erase execution in progress during erase suspend operation When the auto erase operation ends the FMR43 bit is set to 0 erase not executed 18 4 2 14 FMR44 Bit When the auto program operation starts the FMR44 bit is set to 1 program execution in progress The FMR44 bit remains set to 1 program execution in progress during program suspend operatio
170. ce Condition 1 1 Command sequence error When a command is not written correctly e When invalid data other than that which can be written in the second bus cycle of the block erase command is written e other than DOh or FFh 1 e When the program command or block erase command is executed while rewriting is disabled by the FMR0O2 bit in the FMRO register or the FMR15 or FMR16 bit in the FMR1 register e When an address not allocated in flash memory is input during erase command input When attempting to erase the block for which rewriting is disabled during erase command input When an address not allocated in flash memory is input during write command input e When attempting to write the block for which rewriting is disabled during write command input Erase error e When the block erase command is executed but auto erasure does not complete correctly NOTE Program error When the program command is executed but not auto programming does not complete correctly 1 The MCU enters read array mode when FFh is written in the second bus cycle of these commands At the same time the command code written in the first bus cycle is disabled Rev 1 30 Dec 08 2006 Page 267 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Command sequence error Execute the clear status register command set these status flags to 0 Full status check Command seq
171. ce e nl Nsloat ce 1 1 2 Performance Chverview AEN 2 1 3 Block DD RACE EE 4 1 4 dal TTT OP MAUI DEE 5 1 5 aile lr EE 9 1 6 Pen FeCl ei 12 2 Central Processing Unit CPU 15 2 1 Data Registers RO R1 R2 and Reeg 16 2 2 Address K rrech eege EENG 16 2 3 Frame Base Register EB 16 2 4 Interrupt Table Register INTB cccececceeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeeeeees 16 25 Program Counter PG NEE 16 2 6 User Stack Pointer USP and Interrupt Stack Pointer SP 16 2 7 Static Base Register SB E 16 2 8 Flag R gister PG EE 16 2 8 1 Cathy Eeer 16 28 2 Debug RIA EAR EE 16 28 3 LOMO Flag BE cit ca ic sep reson via ees EEN ec adie ee ceded 16 2 8 4 SigA SL E EE 16 2 8 5 Register Bank Select Flag EE 16 2 8 6 Overflow Flag RL EE 16 2 8 7 Interrupt Enable Flag O osechrtru egEEESEEEKEEESESEEEEEEEEEEEEEEEEEEEUN uERSEEEEN 17 2 8 8 Stack Pointer Select Flag UI 17 2 8 9 Processor Interrupt Priority Level IPL EE 17 2 8 10 Reserved BEE 17 3 Memory 18 3 1 FBGA GlOUD E 18 3 2 PBC e EE 19 4 Special Function Registers SFRs 20 5 Programmable I O Ports 24 5 1 Functions of Programmable I O Porte 24 5 2 Effect on Peripheral Functions EE 24 5 3 Pins Other than Programmable I O Portes 24 5 4 Por Settings ee 32 5 5 Unassigned Pin Rangliste g ere tt 37 6 Resets 38 6 1 Hardware Reset E 40 6 1 1 When Power Supply is Stable AEN 40 E RE mn eee aa Eaa E dare ee et ca E Se AEA 40 6 2 Power On Reset Eupe
172. ce to 0 by a clock synchronous serial I O with chip select interrupt routine However the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and the RDRF bit is automatically set to 0 by reading the SSRDR register In particular the TDRE bit is set to 1 data transmitted from registers SSTDR to SSTRSR at the same time transmit data is written to the SSTDR register Setting the TDRE bit to 0 data not transmitted from registers SSTDR to SSTRSR can cause an additional byte of data to be transmitted Rev 1 30 Dec 08 2006 Page 182 0f315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 2 4 Communication Modes and Pin Functions 16 Clock Synchronous Serial Interface Clock synchronous serial I O with chip select switches the functions of the I O pins in each communication mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register Table 16 4 shows the Association between Communication Modes and I O Pins Table 16 4 Association between Communication Modes and I O Pins Bit Setting Pin State Communication Mode BIDE MSS SSI SSO SSCK Clock synchronous communication mode Disabled 0 Input 1 Input 1 Output Input Input Output Input Input 1 Output 1 Output Output Input Output Output 4 wire bus communication mode 1
173. cease Auch ege 14 2 2 Programmable Waveform Generation Mode 14 2 3 Programmable One shot Generation Mode 14 2 4 Programmable Wait One Shot Generation Mode 14 2 5 Notes on BR lr E GC Ge Ni EEN 14 3 1 Input Capture Mode Ae 14 3 2 Output Compare Mode eneee 14 3 3 Notes on Timer EE 15 Serial Interface 15 1 Clock Synchronous Serial I O Mode 0088 15 1 1 Polarity Select Funchon 15 1 2 LSB First MSB First Select Function 15 1 3 Continuous Receive Mode ccccccececcececnecceccececeeccecceeeceeeateeseeeaees 162 15 2 Clock Asynchronous Serial I O UART Mode 163 15 2 1 CONTRO Pin Select Funchon ENEE 166 15 224 Bit EE 167 15 3 Notes on Spraken 168 16 Clock Synchronous Serial Interface 169 16 1 Ee E 169 16 2 Clock Synchronous Serial I O with Chip Select GU 170 16 2 1 Reie EE 179 16 2 2 SS Shift Register SSTRSR cccccecceecesseeeeeesseeeeesseeeeeesseeeeees 181 16 2 3 Interrupt Requests ANE 182 16 2 4 Communication Modes and Pin Functions sssssseeeeeeeeeeseeeeeeeenne 183 16 2 5 Clock Synchronous Communication Mode 184 16 2 6 Operation in 4 Wire Bus Communication Mode ssssssssseesseeneeeeeenne 191 16 2 7 SCS Pin Control and Arbitration 197 16 2 8 Notes on Clock Synchronous Serial I O with Chip Select 198 16 3 120 TER 199 16 3 1 Transfer ee 209 16 32 Interrupt EE 210 16 3 3 12C bus Interface Mee eege etbtete gn
174. ch a rewrite control program is allocated In EWO mode the MCU enters read status register mode at the same time auto programming starts and the status register can be read The status register bit 7 SR7 is set to 0 at the same time auto programming starts and set back to 1 when auto programming completes In this case the MCU remains in read status register mode until the next read array command is written The status register can be read to determine the result of auto programming after auto programming has completed Write the command code 40h to the write address Write data to the write address Full status check Program completed Figure 18 12 Program Command When Suspend Function Disabled Rev 1 30 Dec 08 2006 Page 262 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Maskable interrupt 2 1 enable interrupt A FMR40 1 Yes FMR46 0 e Write the command code 40h Y es FMR42 1 Write data to the write address FMR44 0 BS Access flash memory Yes Access flash memory Full status check Program completed EW1 Mode Maskable interrupt 1 enable interrupt Access flash memory y FMR40 1 REIT Write the command code 40h Write data to the write address FMR44 0 Full status check Program completed NOTES 1 ln EWO mode the interrupt vector ta
175. ches to the corresponding interrupt vector the IR bit is set to 0 interrupt not requested The IR bit can be set to 0 by a program Do not write 1 to this bit 12 1 6 3 Bits ILVL2 to ILVLO and IPL Interrupt priority levels can be set using bits ILVL2 to ILVLO Table 12 3 lists the Settings of Interrupt Priority Levels and Table 12 4 lists the Interrupt Priority Levels Enabled by IPL The following are conditions under which an interrupt is acknowledged eI flag 1 e IR bit 1 e Interrupt priority level gt IPL The I flag IR bit bits ILVL2 to ILVLO and IPL are independent of each other They do not affect one another Table 12 3 Seitings of Interrupt Priority Table 12 4 Interrupt Priority Levels Enabled by Levels IPL ILVL2 to ILVLO Interrupt Priority Level Priority Order Enabled Interrupt Priority Levels Bits Interrupt level 1 and above 000b Level 0 interrupt disabled Interrupt level 2 and above 001b Level 1 Interrupt level 3 and above 010b Level 2 Interrupt level 4 and above 011b Level 3 Interrupt level 5 and above 100b Level 4 Interrupt level 6 and above 101b Level 5 Interrupt level 7 and above 110b Level 6 All maskable interrupts are disabled 111b Level 7 Rev 1 30 Dec 08 2006 Page 85 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 4 Interrupt Sequence An interrupt sequence is performed between an interrupt requ
176. chronous serial I O mode and clock asynchronous serial I O mode UART mode UART1 has only clock asynchronous serial I O mode UART mode Figures 15 3 to 15 6 show the Registers Associated with UARTi UARTO RXDO UART reception Receive CLK1 to CLKO 00b CKDIR 0 Internal fl 18 ES register oa 10b o 1 n0 1 Clock Reception control 1 circuit synchronous type o UART transmission fie External CKDIR 1 Clock i 1 KW o_ Transmission control circuit synchronous type rO 1 2 Clock synchronous type when internal clock is selected a CKDIR 0 clock Transmit clock Transmit receive unit Clock synchronous type when external clock is selected CKDIR 1 Clock synchronous type when internal clock is selected polarity reversing circuit UART reception Reception Receive clock control circuit CLK1 to CLKO 00b fl TAS 01b Internal f8 O t32 10b_ Transmit receive unit U1BRG register 1 n1 1 UART transmission Transmission Transmit clock control circuit Figure 15 1 UARTI i 0 or 1 Block Diagram Rev 1 30 Dec 08 2006 Page 152 0f315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface Clock synchronous type PRYE 0 AR UART 7 bits P disabled t UART 8 oe oOo UART 7 bits UARTI receive register
177. circuit enabled The VCA13 bit is set to 1 VCC gt Vdet 2 when the VCA27 bit in the VCA2 register is set to 0 voltage detection 2 circuit disabled The software reset watchdog timer reset and voltage monitor 2 reset do not affect this register Voltage Detection Register 2 b7 b6 b5 b4 b3 b2 b1 b0 After Reset Address Hardw are reset 00h 0032h Pow er on reset voltage monitor 1 reset 01000000b Bi Symbol Reserved bits Set to 0 b5 b0 VCA26 Voltage detection 1 enable bit 0 Voltage detection 1 circuit disabled 1 Voltage detection 1 circuit enabled Voltage detection 2 enable bit 0 Voltage detection 2 circuit disabled VCA27 R 1 Voltage detection 2 circuit enabled NOTES Set the PRC3 bit in the PRCR register to 1 write enable before writing to this register To use the voltage monitor 1 reset set the VCA26 bit to 1 After the VCA26 bit is set to 1 from 0 the voltage detection circuit w aits for td E A to elapse before starting operation To use the voltage monitor 2 interrupt reset or the VCA13 bit in the VCA1 register set the VCA27 bit to 1 After the VCA27 bit is set to 1 from 0 the voltage detection circuit w aits for td E A to elapse before starting operation Softw are reset w atchdog timer reset and voltage monitor 2 reset do not affect this register Figure 7 4 Registers VCA1 and VCA2 Rev 1 30 Dec 08 2006 Page 47 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Gro
178. cknowledged or set by a program The above timing diagram applies under the following conditions TC 16 n 1 fj or 16 n 1 fEXT PRYE bit in UiMR register 1 parity enabled fj Frequency of UiBRG count source f1 f8 32 STPS bit in UiMR register 0 1 stop bit fEXT Frequency of UiBRG count source external clock UIIRS bit in UiC1 register 1 an interrupt request is generated when transmit completes n Setting value to UiBRG register i Oor1 Transmit timing when transfer data is 9 bits long parity disabled 2 stop bits Transfer clock 8 8 TE bitin UiC1 1 register 0 i Write data to UiTB register Tl bitin UiC1 1 M l register 0 Transfer from UiTB register to UARTi transmit register Start bit TXEPT bit in UiCO register 0 IRbitinSiTIC 1 register 0 T Set to 0 when interrupt request is acknowledged or set by a program The above timing diagram applies under the following conditions 8 e lg Fe trequency of UISRG count source 118 132 it in UIMR register 1 2 stop bits S 10 UIIRS bit in UiC1 register 0 an interrupt request is generated when transmit buffer is empty fEXT Frequency of UIBRG count source external clock n Setting value to UIBRG register i Oor1 Figure 15 10 Transmit Timing in UART Mode Rev 1 30 Dec 08 2006 Page 1650f3
179. clock e When the CKPOL bit in the UOCO register 1 output transmit data at the rising edge and input receive data at the falling edge of the transfer clock RXDO NOTES 1 When not transferring the CLKO pin level is H 2 When not transferring the CLKO pin level is L Figure 15 8 Transfer Clock Polarity 15 1 2 LSB First MSB First Select Function Figure 15 9 shows the Transfer Format Use the UFORM bit in the UOCO register to select the transfer format e When UFORM bit in UOCO register 0 LSB first CLKO RXDO DO e When UFORM bit in UOCO register 1 MSB first ee TLL no Xe Ke Xe Re ae ce EREECHEN NOTE 1 The above applies when the CKPOL bit in the UOCO register is set to 0 output transmit data at the falling edge and input receive data at the rising edge of the transfer clock Figure 15 9 Transfer Format Rev 1 30 Dec 08 2006 Page 161 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface 15 1 3 Continuous Receive Mode Continuous receive mode is selected by setting the UORRM bit in the UCON register to 1 enables continuous receive mode In this mode reading the UORB register sets the TI bit in the UOC1 register to 0 data in the UOTB register When the UORRM bit is set to 1 do not write dummy data to the UOTB register by a program Rev 1 30 Dec 08 2006 Page 162 0f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B G
180. clock synchronous serial interface has four modes Table 16 1lists the Mode Selections Refer to 16 2 Clock Synchronous Serial I O with Chip Select SSU and the sections that follow for details of each mode Table 16 1 Mode Selection IICSEL Bit in Bit 7 in OOB8h PMR Register ICE Bit in ICCR1 Register SSUMS Bit in SSMR2 Register FS Bit in SAR Bit 0 in OOBDh Register Function 0 0 Clock synchronous Clock synchronous serial UO with chip communication mode select 4 wire bus communication mode 12C bus interface 12C bus interface mode Clock synchronous serial mode Rev 1 30 Dec 08 2006 Page 169 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 Clock Synchronous Serial I O with Chip Select SSU Clock synchronous serial I O with chip select supports clock synchronous serial data communication Table 16 2 shows a Clock Synchronous Serial I O with Chip Select Specifications and Figure 16 1 shows a Block Diagram of Clock Synchronous Serial I O with Chip Select Figures 16 2 to 16 9 show Clock Synchronous Serial T O with Chip Select Associated Registers Table 16 2 Clock Synchronous Serial UO with Chip Select Specifications Hem Specification Transfer data format e Transfer data length 8 bits Continuous transmission and reception of serial data are supported since both transmitter and receiver have buffer st
181. d bits CM16 to CM17 in the CM1 register 2 To set the FMR01 bit to 1 write 0 to the FMR01 bit before writing 1 Do not generate an interrupt between writing 0 and 1 3 Disable the CPU rewrite mode after executing the read array command Figure 18 9 How to Set and Exit EWO Mode EW1 Mode Operating Procedure Program in ROM Write 0 to the FMRO1 bit before writing 1 CPU rewrite mode enabled Write 0 to the FMR11 bit before writing 1 Execute software commands Write 0 to the FMR01 bit CPU rewrite mode disabled NOTE 1 To set the FMR01 bit to 1 write 0 to the FMR01 bit before writing 1 Do not generate an interrupt between writing 0 and 1 Figure 18 10 How to Set and Exit EW1 Mode Rev 1 30 Dec 08 2006 Page 259 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Transfer an on chip oscillator mode main clock stops program to an area other than the flash memory Jump to the on chip oscillator mode main clock stops program which has been transferred to an area other than the flash memory The subsequent processing is executed by the program in an area other than the flash memory NOTES 18 Flash Memory On chip oscillator mode main clock stops program Write 0 to the FMRO1 bit before writing 1 CPU rewrite mode enabled Write 1 to the FMSTP bit flash memory stops low power consumption mode Switch the clock source for the CPU clock Turn XIN off Process in o
182. d with Clock Synchronous Serial I O with Chip Select for more information Figure 16 6 SSSR Register Rev 1 30 Dec 08 2006 Page 176 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Mode Register 27 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 00BDh 00h SE Clock synchronous serial VO w ith 0 Clock synchronous communication mode chip select mode select bit 1 Four wire bus communication mode SCS pin open drain output select 0 CMOS output RW Serial data open drain output 0 CMOS output SooS select bit 1 NMOS open drain output RW SSCK pin open drain output 0 CMOS output b5 b4 SCS pin select bits 0 0 Functions as port 0 1 Functions as SCS input pin 1 e Functions as SCS output pin Functions as SCS output pin be SCKS EEN pin select bit J TH as port Functions as serial clock pin Bidirectional mode enable bit 3 0 Standard mode communication using 2 pins of data input and data output 1 Bidirectional mode communication using 1 pin of data input and data output NOTES Refer to 16 2 2 1 Relationship between Data I O Pin and SS Shift Register for information on combinations of data VO pins The SCS pin functions as a port regardless of the values of bits CSSO and CSS1 when the SSUMS bit is set to 0 clock synchronous communication mode This bit functions as the SCS input pin before starting transfer The BIDE b
183. dder Vref Voc teonv Conversion time 10 bit mode AD 10 MHZ Vref Vcc 5 0 V 8 bit mode AD 10 MHZ Vret Vcc 5 0 V Vref Reference voltage VIa Analog input voltage 4 A D operating Without sample and clock hold frequency 2 With sample and hold NOTES 1 Vcc AVcc 2 7 to 5 5 V at Topr 20 to 85 C 40 to 85 C unless otherwise specified 2 If f1 exceeds 10 MHz divide f1 and ensure the A D operating clock frequency AD is 10 MHz or below 3 If AVcc is less than 4 2 V divide f1 and ensure the A D operating clock frequency AD is f1 2 or below 4 When the analog input voltage is over the reference voltage the A D conversion result will be 3FFh in 10 bit mode and FFh in 8 bit mode Figure 19 1 Port P1 P3 and P4 Measurement Circuit Rev 1 30 Dec 08 2006 Page 277 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Table 19 4 Flash Memory Program ROM Electrical Characteristics Standard Typ Parameter Conditions Program erase endurance R8C 1A Group 19 Electrical Characteristics R8C 1B Group Byte program time 50 Block erase time 0 4 9 Time delay from suspend request until 97 CPUclock suspend x 6 cycles Interval from erase start restart until following suspend request Interval from program start restart until following suspend request Time from suspend unt
184. ddress 00000h is read by a program the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 12 5 2 SP Setting Set any value in the SP before an interrupt is acknowledged The SP is set to 0000h after reset Therefore if an interrupt is acknowledged before setting a value in the SP the program may run out of control 12 5 3 External Interrupt and Key Input Interrupt Either L level or H level of at least 250 ns width is necessary for the signal input to pins INTO to INT3 and pins KIO to KT3 regardless of the CPU clock 12 5 4 Watchdog Timer Interrupt Reset the watchdog timer after a watchdog timer interrupt is generated Rev 1 30 Dec 08 2006 Page 100 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 5 5 Changing Interrupt Sources The IR bit in the interrupt control register may be set to interrupt requested when the interrupt source changes When using an interrupt set the IR bit to 0 no interrupt requested after changing the interrupt source In addition changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers polarities and timing Therefore if a mode change of a peripheral function involves interrupt sources edge polarities and timing set the IR bit to 0 no interru
185. de and e SSUMS 1 4 wire bus communication mode and BIDE 0 standard mode and MSS 0 operates BIDE 1 bidirectional mode as slave device I SSTRSR register SSTRSR register Figure 16 11 Association between Data I O Pins and SSTRSR Register Rev 1 30 Dec 08 2006 Page 181 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 3 Interrupt Requests Clock synchronous serial I O with chip select has five interrupt requests transmit data empty transmit end receive data full overrun error and conflict error Since these interrupt requests are assigned to the clock synchronous serial I O with chip select interrupt vector table determining interrupt sources by flags is required Table 16 3 shows the Clock Synchronous Serial I O with Chip Select Interrupt Requests Table 16 3 Clock Synchronous Serial I O with Chip Select Interrupt Requests Interrupt Request Abbreviation Generation Condition Transmit data empty TXI TIE 1 TDRE 1 Transmit end TEI TEIE 1 TEND 1 Receive data full RXI RIE 1 RDRF 1 Overrun error OEI RIE 1 ORER 1 Conflict error CEI CEIE 1 CE 1 CEIE RIE TEIE and TIE Bits in SSER register ORER RDRF TEND and TDRE Bits in SSSR register If the generation conditions in Table 16 3 are met a clock synchronous serial I O with chip select interrupt request is generated Set each interrupt sour
186. deleted Figure 16 14 NOTE 2 deleted Table 17 3 revised 17 7 added 18 3 2 To disable ROM code protect revised Figure 18 4 NOTE 1 revised NOTE 2 added Figure 18 5 NOTE 6 added Table 18 5 Value after Reset revised Figure 18 15 revised Table 19 4 Topr gt Ambient temperature Conditions Vcc 5 0 V at Topr 25 C deleted NOTE 8 added Table 19 5 Topr Ambient temperature Conditions Vcc 5 0 V at Topr 25 C deleted NOTE 9 added Table 19 10 NOTE 3 added Table 19 12 Standard of tSA and toR revised NOTE 1 vcc 2 2 to gt 2 7 to REVISION HISTORY R8C 1A Group R8C 1B Group Hardware Manual Description Summary Mar 17 2006 Table 19 13 NOTE 1 Vcc 2 2 to 2 7 to Table 19 15 Table 19 22 The title revised Condition of Stop Mode Topr 25 C added Table 19 19 Table 19 26 Standard of td C Q and tsu D C revised Package Dimensions revised added Appendix Figure 2 1 revised Appendix Figure 3 1 revised Oct 03 2006 Y version added Factory programming product added Table 1 1 Table 1 2 Specification Interrupts Internal 9 sources gt Internal 11 sources Table 5 12 Setting Value revised Table 6 2 Pin Functions after Reset gt Pin Functions while RESET Pin Level is L Figure 10 6 HRA1 NOTE 2 added HRA2 NOTE 5 added 10 6 1 revised 10 6 2 added Figure 13 2 WDC After Reset When read the content is
187. descriptions of the CPU system control functions peripheral functions and electrical characteristics and usage notes Particular attention should be paid to the precautionary notes when using the manual These notes occur within the body of the text at the end of each section and in the Usage Notes section The revision history summarizes the locations of revisions and additions It does not list all revisions Refer to the text of the manual for details The following documents apply to the R8C 1A Group R8C 1B Group Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the Renesas Technology Web Site Document Type Description Document Title Document No Datasheet Hardware overview and electrical characteristics R8C 1A Group REJ03B0144 R8C 1B Group Datasheet Hardware manual Hardware specifications pin assignments R8C 1A Group This hardware memory maps peripheral function R8C 1B Group manual specifications electrical characteristics timing Hardware Manual charts and operation description Note Refer to the application notes for details on using peripheral functions Software manual Description of CPU instruction set R8C Tiny Series REJO9B0001 Software Manual Application note Information on using peripheral functions and Available from Renesas application examples Technology Web site Sample programs Information on
188. e Falling edge Both edges Do not set Reserved bit Set to 0 INTS interrupt request generation 0 INT3 interrupt is generated timing select bit in synchronization w ith timer C count 1 INTS interrupt is generated w hen INTS interrupt is input TCCO7 me interrupt and capture input 0 INT3 RW sw itch bi 3 1 fRING128 NOTES Change this bit w hen the TCCOO bit is set to 0 count stops The IR bit in the INTSIC register may be set to 1 requests interrupt w hen the TCC03 TCC04 TCC06 or TCCO7 bit is rewritten Refer to 12 5 5 Changing Interrupt Sources polarity select bits TCCO6 When the TCC13 bit is set to 1 output compare mode and an INTS interrupt is input regardless of the setting value of the TCCO6 bit an interrupt request is generated When using the INTS filter the INT3 interrupt is generated in synchronization w ith the clock for the digital filter Figure 12 15 TCCO Register Rev 1 30 Dec 08 2006 Page 94 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts Timer C Control Register 1 b7 b6 b5 b4 b3 b2 bi DO Address After Reset 009Bh 00h INTS filter select bits No filter Filter with f1 sampling Filter with f8 sampling Filter with 32 sampling Timer C counter reload select 0 No reload bite 3 1 Set TC register to 0000h w hen compare 1 is matched Compare 0 capture select bit 0 Capture select input capture mode Com
189. e The MCU exits stop mode by a hardware reset or peripheral function interrupt Figure 10 9 shows the Time from Stop Mode to Interrupt Routine Execution When using a hardware reset to exit stop mode set bits ILVL2 to ILVLO for the peripheral function interrupts to 000b interrupts disabled before setting the CM10 bit to 1 When using a peripheral function interrupt to exit stop mode set up the following before setting the CM10 bit to 1 1 Set the interrupt priority level in bits ILVL2 to ILVLO of the peripheral function interrupts to be used for exiting stop mode Set bits ILVL2 to ILVLO of the peripheral function interrupts that are not to be used for exiting stop mode to 000b interrupt disabled 2 Set the I flag to 1 3 Operate the peripheral function to be used for exiting stop mode When exiting by a peripheral function interrupt the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started The CPU clock when exiting stop mode by a peripheral function interrupt is the divide by 8 of the clock which was used before stop mode was entered Rev 1 30 Dec 08 2006 Page 72 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit FMRO Register Time until Flash Memory Time until CPU Clock Time for Interrupt Remarks FMSTP Bit is Activated T2 is Supplied T3 Sequence T4 Period of system clock Period of CPU clock Period of CPU clock F
190. e 13 3 Watchdog Timer Specifications with Count Source Protection Mode Enabled Item Specification Count source Low speed on chip oscillator clock Count operation Decrement Period Count value of watchdog timer 4096 Low speed on chip oscillator clock Example Period is approximately 32 8 ms when the low speed on chip oscillator clock frequency is 125 kHz Count start conditions The WDTON bit in the OFS register OFFFFh selects the operation of the watchdog timer after a reset e When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to When the WDTON bit is set to 0 watchdog timer starts automatically after reset The watchdog timer and prescaler start counting automatically after a reset Reset condition of watchdog e Reset timer e Write 00h to the WDTR register before writing FFh e Underflow Count stop condition None The count does not stop in wait mode after the count starts The MCU does not enter stop mode Operation at time of Watchdog timer reset Refer to 6 5 Watchdog Timer Reset underflow Registers bits e When setting the CSPPRO bit in the CSPR register to 1 count source protection mode is enabled 2 the following are set automatically Set OFFFh to the watchdog timer Set the CM14 bit in the CM1 register to 0 low speed on chip oscillator on Set the PM12 bit in the
191. e 154 0f 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface UARTIi Transmit Receive Mode Register i 0 or 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 00A0h 00h OOA8h 00h Serial interface disabled Clock synchronous serial YO mode UART mode transfer data 7 bits long UART mode transfer data 8 bits long UART mode transfer data 9 bits long Other than above Do not set Stop bit length select bit 0 1 stop bit ai 1 2 stop bits Odd even parity select bit Enabled w hen PRYE 1 0 Odd parity 1 Even parity Parity enable bit 0 Parity disabled Reserved bit Set to 0 R b7 NOTES 1 Set the PD1_6 bit in the PD1 register to O input 2 Do not set bits SMD2 to SMDO in the U1MR register to any values other than 000b 100b 101b and 110b 3 Set the CKDIR bit in UART1 to 0 internal clock KDIR Internal external clock select 0 Internal clock ci bn 1 External clock RW RW RW RW RW RW RW W Figure 15 4 Registers UOMR to U1MR Rev 1 30 Dec 08 2006 Page 155 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface UARTIi Transmit Receive Control Register 0 i 0 or 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 00A4h 08h DOACH 08h BRG count source select moto 00 Selects f1 0 1 Selects f8 10 Selects f32 11 Do not set Reserved bit Set to 0 Transmit register empty 0 Data in transmit regi
192. e Ee Ee 76 10 6 3 Oscillation Stop Detection Funchon 76 10 6 4 Oscillation Circuit Ee Ee eege saad enn Aye esiateis 76 10 6 5 High Speed On Chip Oscillator Clock sssssnnnseesennnnnneeenrnnnnneeerreenn 76 11 Protection Wi 12 Interrupts 78 12 1 Interrupt E WEEN a aaae a Sek oak aea aa eea N E aa Sate 78 12 1 1 Types of lnterupts EE 78 n De ne 79 121 3 Ee Ne 80 12 1 4 Peripheral Function Interupt 80 12 1 5 Interrupts and Interrupt Vechors 81 T2216 interrupt COMO EE 83 12 2 Or 91 122A INTO NET 91 1222 ONTO Minuit Fe ME snra O 92 12 23 INTI Interrupt eon E erst oS E 93 EK MAT 94 12 3 Key Ree 96 12 4 Address Match Interupt 12 5 Notes on Blend EEN 12 5 1 Reading Address 00000h ceeeeeeeeeeeeees 12 95 24 Gu Le D 12 5 3 External Interrupt and Key Input Interrupt 12 5 4 Watchdog Timer Intern 12 5 5 Changing Interrupt Sources 12 5 6 Changing Interrupt Control Register Contents 13 Watchdog Timer 13 1 Count Source Protection Mode Disabled 13 2 Count Source Protection Mode Enabled 14 Timers Tol STASI EEN 14 1 1 Timer Mode ssaooononnnnnnnnnnnnnnnnnnnnennnnnnneeeeeennnnnnnnna 14 1 2 Pulse Output Mode AA 14 1 3 Event Counter Mode 14 1 4 Pulse Width Measurement Mode nnnnsasnnneen 14 1 5 Pulse Period Measurement Mode 14 1 6 Notes On Tmerx er Ni E atic ts tae hs Maat iin ian Gina ahah oes is 14 2 1 Der Mode eieiei b ie de
193. e P3 register are unavailable on this MCU If itis necessary to set bits P3_0 to P3_2 and P3_6 set to 0 L level When read the content is 0 Figure 5 6 Registers P1 and P3 Rev 1 30 Dec 08 2006 Page 29 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports Port P4 Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOE8h Undefined P4 Nothing is assigned If necessary set to 0 L level b1 b0 When read the content is 0 Port P4_2 bit The level of the pin can be read by reading the bit P42 0 L level 1 H level Nothing is assigned If necessary set to 0 L level b4 b3 When read the content is 0 Port P4_5 bit The pin level of any VO port w hich is set to input mode can be read by reading the corresponding bit in this register The pin level of any VO port w hich is set to P4 5 output mode can be controlled by w riting to the 8 corresponding bit in this register 0 L level 1 H level Port P4_6 bit The level of the pin can be read by reading the bit 0 L level Port P4_7 bit 1 H level Figure 5 7 P4 Register Port Mode Register Address After Reset OOF8h 00h Bi Symbol Reserved bits Set to 0 W SSI signal pin select bit 0 P3_3 pin is used for SSI00 pin Seer eee a P1_6 pin is used for SSI01 pin R Reserved bits Set to 0 SSU PC bus switch bit 0 Selects SSU function dee 1
194. e RDRF bit is set to 1 the ORER bit in the SSSR register is set to 1 overrun error OEI and the operation is stopped When the ORER bit is set to 1 reception cannot be performed Confirm that the ORER bit is set to 0 before restarting reception The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the SSMR register Figure 16 20 shows when bits RDRF and ORER are set to 1 When the CPHS bit is set to 1 data download at the odd edges bits RDRF and ORER are set to at some point during the frame The sample flowchart is the same as that for the clock synchronous communication mode Refer to Figure 16 16 Sample Flowchart of Data Reception MSS 1 Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 195 0f315 pReENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface CPHS bit 0 data download at even edges and CPOS bit 0 H when clock stops SCS High impedance output Ss o d ie Pig LI LI ly 1 Ke 3 steen if 1 frame 1 frame RDPF bit in SSSR register amp amp RSSTP bit in RXI interrupt request RXI interrupt request is generated is generated RXI interrupt request SSCRH register as K is generated Processing Dummy read in Data read in SSRDR Set RSSTP Data read in SSRDR by program SSRDR register register bit to 1 register e CPHS bit 1 data download at odd edges and CPOS bit 0 CH
195. e shot Counts underflow s of prescaler Z 00h to FFh RW generation mode counts one shot w idth Programmable w ait one shot Counts underflow s of prescaler Z 00h to FFh RW generation mode counts w ait period NOTE 1 Each value in registers TZPR and TZSC is reloaded to the counter alternately and counted Figure 14 13 Registers PREZ TZSC and TZPR Rev 1 30 Dec 08 2006 Page 1250f315 speeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer Z Output Control Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 008Ah 00h Bi Symbol Function Car Timer Z one shot start DI g One shot stops RW One shot starts SR Reserved bit Set to 0 be TZOCNT Timer Z programmable w aveform K Outputs programmable w aveform generation output sw itch bit Outputs value in P1_3 port register Nothing is assigned If necessary set to 0 b7 b3 When read the content is 0 This bit is set to 0 when the output of a one shot w aveform is completed If the TZS bit in the TZMR register was set to 0 count stops to stop the w aveform output during one shot w aveform output set the TZOS bit to 0 This bit is enabled only when operating in programmable w aveform generation mode When executing an instruction w hich changes this register w hen the TZOS bit is set to 1 during count the TZOS bit is automatically set to 0 one shot stop if the count is completed w hile the instruction is being executed If th
196. e time if the 12C bus Interface monitors the SDA pin and the data which the 12C bus Interface transmits is different the AL flag is set to 1 and the bus is occupied by another master The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 when the receive acknowledge bit is set to 1 transfer is halted The RDRF bit is set to 0 when reading data from the ICDRR register Bits TEND and TDRE are set to 0 when writing data to the ICDRT register Refer to 16 3 8 1 Accessing of Registers Associated with DC bus Interface for more information Figure 16 28 ICSR Register Rev 1 30 Dec 08 2006 Page 206 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Slave Address Register b7 b6 b5 b4 b3 b2 bi b Address After Reset 00BDh 00h Bit Symbol FS Format select bit 0 PC bus format RW 1 Clock synchronous serial format Slave address 6 to 0 Set an address different from that of the other slave devices w hich are connected to the PC bus When the 7 high order bits of the first frame transmitted after the starting condition match bits SVAO to SVAG in slave mode of the PC bus format the MCU operates as a slave device NOTE 1 Refer to 16 3 8 1 Accessing of Registers Associated with PC bus Interface for more information IIC bus Transmit Data Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOBEh FFh Store transmit data When it is detected tha
197. eas are used 3 Do not set the address match interrupt registers AIER RMADO and RMAD1 and fixed vector tables in a user system 4 Do not use the BRK instruction in a user system Connecting and using the on chip debugger has some special restrictions Refer to the on chip debugger manual for on chip debugger details Rev 1 30 Dec 08 2006 Page 309 of 315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Appendix 1 Package Dimensions Appendix 1 Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the Packages section of the Renesas Technology website JEITA Package Code RENESAS Code Previous Code MASS Typ P LSSOP20 4 4x6 5 0 65 PLSP0020JB A 20P2F A 0 1g 20 11 LER HAE E Q ra 1 Index mark a0 He NOTE 1 DIMENSIONS 4 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET Ae A v i 7 lReference Dimension in Millimeters D Symbol Min Nom Max D 6 4 6 5 6 6 E 43 44 4 5 Az 1 15 g TI ID Jy A as Ki Au 0 0 1 0 2 at ap i betalF bp 0 17 0 22 0 32 c 0 13 0 15 0 2 H o 10 He 6 2 6 4 6 6 e 0 53 0 65 0 77 y 0 10 L 03
198. egister Rev 1 30 Dec 08 2006 Page 22 of 315 w N E SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 4 Special Function Registers SFRs Table 4 4 SFR Information 4 1 Address Register Symbol After reset 00COh A D Register AD XXh 00C1h XXh 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h DOC Ah OOCBh 00CCh 00CDh OOCEh OOCFh 00D0h 00Dth 00D2h 00D3h 00D4h A D Control Register 2 ADCON2 00h 00D5h 00D6h A D Control Register 0 ADCONO 00000XXXb 00D7h A D Control Register 1 ADCON1 00h 00D8h 00D9h OODAh OODBh 00DCh 00DDh OODEh OODFh OOEOh OOETh Port P1 Register P1 XXh 00E2h OOE3h Port P1 Direction Register PD1 00h 00E4h OOE5h Port P3 Register P3 XXh OOE6h 00E7h Port P3 Direction Register PD3 00h OOE8h Port P4 Register P4 XXh OOE9h OOEAR Port P4 Direction Register PD4 00h OOEBh OOECh OOEDh OOEEh OOEFh OOFOh OOF Th O00F2h OOF3h O00F4h OOF5h OOF6h OOF7h OOF8h Port Mode Register PMR 00h OOF9h OOFAh OOFBh OOFCh Pull Up Control Register 0 PURO 00XX0000b OOFDh Pull Up Control Register 1 PUR1 XXXXXXOXb OOFEh Port P1 Drive Capacity Control Register DRR 00h OOFFh Timer C Output Control Register TCOUT 00h 01B3h Flash Memory Control Register 4 FMR4 01000000b 01B4h 01B5h Flash Memory Control Register 1 FMR1 1000
199. egister the TXEDG or TXUND bit may be set to 0 although these bits are set to 1 while the instruction is being executed In this case write 1 to the TXEDG or TXUND bit which is not supposed to be set to 0 with the MOV instruction e When changing to pulse period measurement mode from another mode the contents of bits TXEDG and TXUND are undefined Write 0 to bits TXEDG and TXUND before the count starts e The TXEDG bit may be set to 1 by the prescaler X underflow generated after the count starts e When using the pulse period measurement mode leave two or more periods of the prescaler X immediately after the count starts then set the TXEDG bit to 0 e The TXS bit in the TXMR register has a function to instruct timer X to start or stop counting and a function to indicate that the count has started or stopped 0 count stops can be read until the following count source is applied after 1 count starts is written to the TXS bit while the count is being stopped If the following count source is applied 1 can be read from the TXS bit After writing 1 to the TXS bit do not access registers associated with timer X registers TXMR PREX TX TCSS and TXIC except for the TXS bit until 1 can be read from the TXS bit The count starts at the following count source after the TXS bit is set to 1 Also after writing 0 count stops to the TXS bit during the count timer X stops counting at the following count source 1 count starts can be read by read
200. egister U0TB XXh OOA3h XXh 00A4h UARTO Transmit Receive Control Register 0 U0CO 00001000b OOA5h UARTO Transmit Receive Control Register 1 U0C1 00000010b OOA6h UARTO Receive Buffer Register UORB XXh 00A7h XXh 00A8h UART1 Transmit Receive Mode Register U1MR 00h OOA9h UART1 Bit Rate Generator UTBRG XXh OOAAh UART1 Transmit Buffer Register U1TB XXh OOABh XXh OO0ACh UART1 Transmit Receive Control Register 0 U1CO 00001000b OOADh UART1 Transmit Receive Control Register 1 UiC1 00000010b OOAEh UART1 Receive Buffer Register U1RB XXh OOAFh XXh OOBOh UART Transmit Receive Control Register 2 UCON 00h OOBTh 00B2h 00B3h 00B4h DOD h OOB6h 00B7h 00B8h SS Control Register H IIC bus Control Register 19 SSCRH ICCR1 00h OOB9h SS Control Register L IIC bus Control Register 2 4 SSCRL 1ICCR2 01111101b OOBAh SS Mode Register IIC bus Mode Register 4 SSMR ICMR 00011000b OOBBh SS Enable Register IIC bus Interrupt Enable Register 4 SSER ICIER 00h OOBCh SS Status Register IIC bus Status Register 4 SSSR ICSR 00h 7 0000X000b 0OBDh SS Mode Register 2 Slave Address Register 4 SSMR27SAR 00h OOBEh SS Transmit Data Register IIC bus Transmit Data Register SSTDR ICDRT FFh OOBFh SS Receive Data Register IIC bus Receive Data Register 4 SSRDR ICDRR FFh X Undefined NOTES 1 The blank regions are reserved Do not access locations in these regions 2 In input capture mode 3 In output compare mode 4 Selected by the IICSEL bit in the PMR r
201. en VCC reaches Vdet2 or below Figure 7 6 VW2C Register Rev 1 30 Dec 08 2006 Page 490f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit 7 1 VCC Input Voltage 7 1 1 Monitoring Vdet1 Vdet1 cannot be monitored 7 1 2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 voltage detection 2 circuit enabled After td E A has elapsed refer to 19 Electrical Characteristics Vdet2 can be monitored by the VCA13 bit in the VCA1 register 7 1 3 Digital Filter A digital filter can be used for monitoring the VCC input voltage When the VW1C1 bit in the VWIC register is set to O digital filter enabled for the voltage monitor 1 circuit and the VW2C1 bit in the VW2C register is set to 0 digital filter enabled for the voltage monitor 2 circuit the digital filter circuit is enabled fRING S divided by 1 2 4 or 8 may be selected as a sampling clock The level of VCC input voltage is sampled every sampling clock cycle and when the sampled input level matches two times the internal reset signal changes to L or a voltage monitor 2 interrupt request is generated Rev 1 30 Dec 08 2006 Page 50 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit Voltage monitor 1 reset VCC Vdet1 n 2 Ze ZE Irtrrrrt Internal reset signal Sampling clock of digital filter x 4 cycles Operation when the VW1C1 bit in the VW1C register i
202. en power on reset is 0 C lt Topr lt 85 C deasserted tw por1 gt 1 s 2 NOTES 1 When not using voltage monitor 1 use with Vece 2 7 V 2 tw port is the time to hold the external power below effective voltage Vport Vaett Vaett 3 EE Le EE Sampling time 2 tw por2 tw Vpor2 Vdet Internal reset signal CL valid x32 Ig fRING S fRING S NOTES 1 Hold the voltage inside the MCU operation voltage range Vccmin or above within the sampling time 2 The sampling clock can be selected Refer to 7 Voltage Detection Circuit for details 3 Vdet1 indicates the voltage detection level of the voltage detection 1 circuit Refer to 7 Voltage Detection Circuit for details Figure 19 3 Reset Circuit Electrical Characteristics Rev 1 30 Dec 08 2006 Page 281 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 10 High Speed On Chip Oscillator Circuit Electrical Characteristics Standard Min Typ High speed on chip oscillator frequency when the Vcc 5 0 V Topr 25 C 8 reset is deasserted High speed on chip oscillator frequency 0 to 60 C 5 V 5 I3 temperature e supply voltage dependence 2 20 to 85 C 2 7 to 5 5 V 3 40 to 85 C 2 7 to 5 5 VIS Parameter Condition NOTES 1 The measurement condition is Vcc 5 0 V and Topr 25 C 2 Refer to 1
203. er X underflow Count operations e Decrement the value set in Timer Z primary When the count of TZPR register underflows the timer reloads the contents of the TZSC register before the count is continued e When the count of the TZSC register underflows the timer reloads the contents of the TZPR register before the count completes and the TZOS bit is set to 0 When the count stops the timer reloads the contents of the reload register before it stops Wait time n 1 m 1 fi fi Count source frequency n Value set in PREZ register m value set in TZPR register One shot pulse output time n 1 p 1 fi fi Count source frequency n Value set in PREZ register p value set in TZSC register Count start conditions e Set the TZOS bit in the TZOC register to 1 one shot starts 1 e Input active trigger to the INTO pin 2 Count stop conditions When reloading completes after timer Z underflows during secondary period When the TZS bit in the TZMR register is set to 0 count stops e When the TZOS bit in the TZOC register is set to 0 one shot stops Interrupt request generation timing In half a cycle of the count source after timer Z underflows during secondary period complete at the same time as waveform output from the TZOUT pin timer Z interrupt TZOUT pin function Pulse output To use this pin as a programmable UO port select timer mode INTO pin function e When the I
204. er reload select function The TCC12 bit in the TCC1 register can select whether the counter value in the TC register is set to 0000h when the compare circuit 1 matches e Bits TCC 14 to TCC15 in the TCC1 register can be used to select the output level when compare circuit 0 matches Bits TCC16 to TCC17 in the TCC1 register can be used to select the output level when compare circuit 1 matches e Bits TCOUT6 to TCOUT7 in the TCOUT register can select whether the output is inverted or not 1 When the corresponding port data is 1 the waveform is output depending on the setting of the registers TCC1 and TCOUT When the corresponding port data is 0 the fixed level is output refer to Figure 14 25 Block Diagram of CMP Waveform Output Unit 2 Access registers TC TMO and TM1 in 16 bit units Dec 08 2006 Page 149 of 315 stENESAS R8C 1A Group R8C 1B Group 14 Timers Value set in TM1 register Count starts rer Match Value set in TMO register Counter content hex l l Set to 1 by program l i l l TCCOO bit in TCCO register l l l Set to 0 when interrupt request is acknowledged or set by program l l IR bit in CMPOIC a 1 D register 1 Set to 0 when interrupt request is acknowledged or set by program IR bit in CMP1IC register CMPO 0 output CMP1_0 output The above applies to the following conditions TCC12 bit in TCC1 register 1 TC register is set to 0000h at compare 1 match occurrence TCC
205. erating mode XXX5 L_ XXX bit 0 XXX Blank Set to 0 or 1 according to the application 0 Set to 0 1 Set to 1 X Nothing is assigned Fosse RW Read and write RO Read only WO Write only Nothing is assigned e Reserved bit Reserved bit Set to specified value e Nothing is assigned Nothing is assigned to the bit As the bit may be used for future functions if necessary set to 0 e Do not set to a value Operation is not guaranteed when a value is set e Function varies according to the operating mode The function of the bit varies with the peripheral function mode Refer to the register diagram for information on the individual modes 4 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi Z High Impedance Inter Equipment bus Input Output Infrared Data Association Least Significant Bit Most Significant Bit Non Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver Transmitter Voltage Controlled Oscillator Table of Contents SFR Page Reference EEN 1 Overview 1 1 1 Applications ness eee a tts ann nS anes abe aee en
206. ertain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electro
207. esistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by the manufacturer of the oscillator When the oscillation drive capacity is set to low check that oscillation is stable Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added to the chip externally insert a feedback resistor between XIN and XOUT following the instructions Figure 10 7 Examples of Main Clock Connection Circuit Rev 1 30 Dec 08 2006 Page 65 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 2 On Chip Oscillator Clocks These clocks are supplied by the on chip oscillators high speed on chip oscillator and a low speed on chip oscillator The on chip oscillator clock is selected by the HRAO1 bit in the HRAO register 10 2 1 Low Speed On Chip Oscillator Clock The clock generated by the low speed on chip oscillator is used as the clock source for the CPU clock peripheral function clock fRING fRING128 and fRING S After reset the on chip oscillator clock generated by the low speed on chip oscillator divided by 8 is selected as the CPU clock If the main clock stops oscillating when bits OCD1 to OCDO in the OCD register are set to 11b oscillation stop detection function enabled the low speed on chip oscillator automatically starts operating supplying the necessary clock for the MCU The frequency of the low speed on
208. est acknowledgement and interrupt routine execution When an interrupt request is generated while an instruction is being executed the CPU determines its interrupt priority level after the instruction is completed The CPU starts the interrupt sequence from the following cycle However for the SMOVB SMOVF SSTR or RMPA instruction if an interrupt request is generated while the instruction is being executed the MCU suspends the instruction to start the interrupt sequence The interrupt sequence is performed as indicated below Figure 12 5 shows the Time Required for Executing Interrupt Sequence 1 The CPU gets interrupt information interrupt number and interrupt request level by reading address 00000h The IR bit for the corresponding interrupt is set to O interrupt not requested 2 The FLG register is saved to a temporary register in the CPU immediately before entering the interrupt sequence 3 The I D and U flags in the FLG register are set as follows The I flag is set to 0 interrupts disabled The D flag is set to 0 single step interrupt disabled The U flag is set to 0 ISP selected However the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed 4 The CPU s internal temporary register is saved to the stack 5 The PC is saved to the stack 6 The interrupt priority level of the acknowledged interrupt is set in the IPL 7 The starting address of the interrupt rout
209. et 0080h 00h SECH Reserved bits Set to 0 Timer Z operating mode b5 b4 bits 1 1 Programmable w ait one shot generation mode TE Timer Z write control bit Set to 1 in programmable w ait one shot generation mode D Timer Z count start flag 0 Stops counting ee SG eae counting ie NOTES 1 When the TZS bit is set to 1 count starts the count value is written to the reload register only When the TZS bit is set to 0 count stops the count value is written to both reload register and counter 2 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit Timer Z Waveform Output Control Register b7 b6 b5 b4 b3 b2 bi bd Address After Reset 0084h 00h SECH Reserved bits Set to 0 Timer Z output level latch 0 Outputs one shot pulse H Outputs L w hen the timer is stopped TZOPL RW 1 Outputs one shot pulse L Outputs H w hen the timer is stopped control bit 1 INTO pin one shot trigger enabled INTO pin one shot trigger 0 Falling edge trigger NOTES 1 Set the INOSTG bit to 1 after the INTOEN bit in the INTEN register and the INOSEG bit in the PUM register are set When setting the INOSTG bit to 1 INTO pin one shot trigger enabled set the INTOFO to INTOF1 bits in the INTOF register Set the INOSTG bit to 0 INTO pin one shot trigger disabled after the TZS bit in the TZMR register is set to 0 count stops 2 The INOSEG bit is enabled only when the INTOPL
210. et the TZS bit to 1 count starts the INTOEN bit in the INTEN register to 1 enables INTO input and the INOSTG bit in the PUM register to 1 INTO one shot trigger enabled A trigger which is input during the count cannot be acknowledged however an INTO interrupt request is generated 3 The set value is reflected at the following one shot pulse after writing to the TZPR register Rev 1 30 Dec 08 2006 Page 133 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0080h 00h SE Reserved bits Set to 0 Timer Z operating mode bit bs ba RW TZMOD1 1 0 Programmable one shot generation mode TZWC Timer Z w rite control bit Set to 1 in programmable one shot generation RW mode Timer Z count start flag 0 Stops counting TZS 1 Starts counting GA NOTES 1 When the TZS bit is set to 1 count starts the count value is written to the reload register only When the TZS bit is set to 0 count stops the count value is written to both reload register and counter 2 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit Timer Z Waveform Output Control Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0084h 00h PUM SE Reserved bits Set to 0 Timer Z output level latch 0 Outputs one shot pulse H Outputs L w hen the timer is stopped TZOPL 1 Outputs one shot pulse L Outputs
211. et to 0 Softw are reset bit The MCU is reset w hen this bit is set to 1 When read the content is 0 PMO03 RW Nothing is assigned If necessary set to 0 b7 b4 When read the content is 0 1 Set the PRC1 bit in the PRCR register to 1 write enable before rew riting the PMO register NOTE Figure 8 1 PMO Register Rev 1 30 Dec 08 2006 Page 55 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 8 Processor Mode Processor Mode Register 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0005h 00h Bi Syirbol Nothing is assigned If necessary set to 0 b0 When read the content is undefined Reserved bit Set to 0 b1 PM12 WDT interrupt reset sw itch bit 0 Watchdog timer interrupt 1 Watchdog timer reset Nothing is assigned If necessary set to 0 b6 b3 When read the content is 0 Reserved bit Set to 0 R b7 NOTES 1 Set the PRC1 bit in the PRCR register to 1 write enable before rew riting the PM1 register 2 The PM12 bit is set to 1 by a program and remains unchanged even if 0 is written to it When the CSPRO bit in the CSPR register is set to 1 count source protect mode enabled the PM12 bit is automatically set to 1 RW RW W Figure 8 2 PM1 Register Rev 1 30 Dec 08 2006 Page 56 of 315 v EN SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 9 Bus 9 Bus The bus cycles differ when accessing ROM RAM and when accessing SFR Table 9
212. etting TDRE bits to 0 Figure 16 35 Operating Timing in Master Receive Mode 12C bus Interface Mode 1 Rev 1 30 Dec 08 2006 Page 2150f315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SCL master output 9 1 2 3 4 5 6 7 8 9 SDA master output faa ie NESE EE E ESE RDRF bit in ICSR register RCVD bit in ICCR1 register ICDRS register Data n 1 BE ICDRR register A 6 Stop condition i Processing 5 Set RCVD bit to 1 before generation 7 Read ICDRR register before by program reading ICDRR register setting RCVD bit to 0 8 Set to slave receive mode Figure 16 36 Operating Timing in Master Receive Mode GC bus Interface Mode 2 Rev 1 30 Dec 08 2006 Page 216 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 3 4 Slave Transmit Operation In slave transmit mode the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal Figures 16 37 and 16 38 show the Operating Timing in Slave Transmit Mode I C bus Interface Mode Rev 1 30 The transmit procedure and operation in slave transmit mode are as follows 1 2 3 4 5 Set the ICE bit in the ICCR1 register to 1 transfer operation enabled Set bits WAIT and MLS in the ICMR register and bits CKSO to CKS3 in the ICCR1 register initial setting Set
213. external pull up resistor RW When writing to the BBSY bit write 0 simultaneously When read the content is 1 Writing 1 is invalid When read 0 Bus is in released state SDA signal changes from L to H while SCL signal is in H state 1 Bus is in occupied state SDA signal changes from H to L while SCL signal is in H state When written 0 Generates stop condition 1 Generates start condition RW When writing to the SDAO bit write 0 to the SDAOP bit using the MOV instruction simultaneously Do not write during a transfer operation This bit is enabled in master mode When writing to the BBSY bit w rite 0 to the SCP bit using the MOV instruction simultaneously Execute the same w ay when the start condition is regenerating This bit is disabled w hen the clock synchronous serial format is used Refer to 16 3 8 1 Accessing of Registers Associated with DC bus Interface for more information Figure 16 25 ICCR2 Register Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 203 of 315 stENESAS R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface IC bus Mode Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset OOBAh 00011000b Bit Symbol i Function Bit counter 2 to 0 PC bus format remaining transfer bit count w hen read out and data bit count of next transfer when written 2 b2 bt b0 000 9bits 001 2bits 0 10 3 bits 0 11 4 bits 100 5 bits 101
214. f the UiBRG register f1 f8 or 32 e External clock selected UiBRG register setting value i EE 1 Bit Rate x 16 fEXT Count source frequency of the UiBRG register external clock Figure 15 12 Calculation Formula of UiBRG i 0 or 1 Register Setting Value Table 15 7 Bit Rate Setting Example in UART Mode Internal Clock Selected BRG System Clock 20 MHz System Clock 8 MHz ae Count UiBRG Actual Time Error Gees Actual H g Time bps Source Setting Value bps Error 1200 129 81h 1201 92 0 16 1201 92 0 16 2400 64 40h 2403 85 0 16 2403 85 0 16 4800 32 20h 4734 85 1 36 4807 69 0 16 9600 129 81h 9615 38 0 16 9615 38 0 16 14400 14367 82 0 22 14285 71 0 79 19200 19230 77 0 16 19230 77 0 16 28800 29069 77 0 94 29411 76 2 12 31250 31250 00 0 00 31250 00 0 00 38400 37878 79 1 36 38461 54 0 16 51200 52083 33 1 73 50000 00 2 34 i Oor1 Rev 1 30 Dec 08 2006 Page 167 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface 15 3 Notes on Serial Interface e When reading data from the UiRB register either in the clock asynchronous serial I O mode or in the clock synchronous serial I O mode Ensure the data is read in 16 bit units When the high order byte of the UiRB register is read bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0 To check receive errors read the UiRB reg
215. f transmit data Transmit data empty 5 0 Data is not transferred from registers SSTDR to SSTRSR 1 Data is transferred from registers SSTDR to SSTRSR NOTES 1 Writing 1 to CE OPER RDRF TEND or TDRE bit is invalid To set any of these bits to 0 first read 1 then write 0 2 When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 four wire bus communication mode and the MSS bit in the SSCRH register is set to 1 operates as master device the CE bit is set to 1 if L is applied to the SCS pin input When the SSUMS bit in the SSMR2 register is set to 1 four w ire bus communication mode the MSS bit in the SSCRH register is set to 0 operates as slave device and the SCS pin input changes the level from L to H during transfer the CE bit is set to 1 Indicates w hen overrun errors occur and receive completes by error reception If the next serial data receive operation is completed w hile the RDRF bit is set to 1 data in the SSRDR register the ORER bit is set to 1 After the ORER bit is set to 1 overrun error transmit and receive operations are disabled w hile the bit remains 1 The RDFF bit is set to 0 when reading out the data from the SSRDR register Bits TEND and TDRE are set to 0 when writing data to the SSTDR register The TDRE bit is set to 1 when the TE bit in the SSER register is set to 1 transmit enabled Refer to 16 2 8 1 Accessing Registers Associate
216. for the Y version Rev 1 30 Dec 08 2006 Page3o0f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview 1 3 Block Diagram Figure 1 1 shows a Block Diagram I O ports Peripheral Functions Timers Timer X 8 bits Timer Z 8 bits Timer C 16 bits A D converter 10 bits x 4 channels UART or clock synchronous serial I O 8 bits x 1 channel UART 8 bits x 1 channel System clock generator XIN XOUT High speed on chip oscillator Low speed on chip oscillator SSU 8 bits x 1 channel or PC bus Watchdog timer 15 bits R8C Tiny Series CPU core ae Memory es we Figure 1 1 Block Diagram NOTES 1 ROM size varies with MCU type 2 RAM size varies with MCU type Rev 1 30 Dec 08 2006 Page 4of315 REJ09B0252 0130 2tENESAS R8C 1A Group R8C 1B Group 1 Overview 1 4 Product Information Table 1 3 lists Product Information for R8C 1A Group and Table 1 4 lists Product Information for R8C 1B Group Table 1 3 Product Information for R8C 1A Group Current of December 2006 RAM Capacity R5F211A1SP 4 Kbytes 384 bytes PLSP0020JB A R5F211A2SP 8 Kbytes 512 bytes PLSP0020JB A R5F211A3SP 12 Kbytes 768 bytes PLSP0020JB A R5F211A4SP 16 Kbytes 1 Kbyte PLSP0020JB A R5F211A1DSP 4 Kbytes 384 bytes PLSP0020JB A D version R5F211A2DSP 8 Kbytes 512 bytes PLSP0020JB A R5F211A3DSP 12 Kbytes 768 bytes PLSP0020JB A R5F211A4DSP 16 Kbytes 1 Kb
217. fter Reset OOB8h 00h Bi Sy Transmit clock select bits 3 to 53621 b0 1 28 1 40 1 48 1 64 1 80 1 100 f1 112 f1 128 1 56 1 80 1 96 f1 128 Transfer receive select DIS 3 bs b4 0 0 Slave receive mode 0 1 Slave transmit mode Master slave select bit 1 0 Master receive mode 1 1 Master transmit mode Receive disable bit After reading the ICDRR register w hile the TRS bit is set to 0 0 Maintains the next receive operation 1 Disables the next receive operation f1 160 1 200 1 224 1 256 RW RW RW RW RW RW RW W IC bus interface enable bit 0 This module is halted Pins SCL and SDA are set to port function 1 This module is enabled for transfer R operations Pins SCL and SDA are bus drive state NOTES Set according to the necessary transfer rate in master mode Refer to Table 16 6 Transfer Rate Examples for the transfer rate This bit is used for maintaining of the setup time in transmit mode of slave mode The time is 10Tcyc when the CKS3 bit is set to and 20Tcyc when the CKS3 bit is set to 1 1Tcyc 1 f1 s Rew rite the TRS bit betw een transfer frames When the first 7 bits after the start condition in slave receive mode match with the slave address set in the SAR register and the 8th bit is set to 1 the TRS bit is set to 1 In master mode w ith the PC bus format when arbitration is lost bits MST and TRS are set to 0 and the IIC enters slave receive mode When an overrun err
218. g amplifier Analog input voltage 0 V to AVCC Operating clock AD 4 2V lt AVCC lt 5 5 V f1 f2 f4 2 7 V lt AVCC lt 4 2 V f2 f4 Resolution 8 bits or 10 bits selectable Absolute accuracy AVCC Vref 5 V e 8 bit resolution 2 LSB e 10 bit resolution 3 LSB AVCC Vref 3 3 V e 8 bit resolution 2 LSB e 10 bit resolution 5 LSB Operating mode One shot and repeats Analog input pin 4 pins AN8 to AN11 A D conversion start conditions e Software trigger Set the ADST bit in the ADCONO register to 1 A D conversion starts e Capture Timer Z interrupt request is generated while the ADST bit is set to 1 Conversion rate per pin NOTES e Without sample and hold function 8 bit resolution 49AD cycles 10 bit resolution 59dAD cycles e With sample and hold function 8 bit resolution 28oAD cycles 10 bit resolution 33 AD cycles 1 The analog input voltage does not depend on use of a sample and hold function When the analog input voltage is over the reference voltage the A D conversion result will be 3FFh in 10 bit mode and FFh in 8 bit mode 2 The frequency of AD must be 10 MHz or below Without a sample and hold function the AD frequency should be 250 kHz or above With a sample and hold function the AD frequency should be 1 MHz or above 3 In repeat mode only 8 bit mode can be used Rev 1 30 Dec 08 2006 Page 232 of 315 spRENESAS REJ09B0252 0130
219. gisters TX and PREX Write to timer When registers TX and PREX are written while the count is stopped values are written to both the reload register and counter e When registers TX and PREX are written during the count the value is written to each reload register of registers TX and PREX at the following count source input the data is transferred to the counter at the second count source input and the count re starts at the third count source input Select functions e INT1 CNTRO signal polarity switch function The ROEDG bit can select H or L level period for the input pulse width measurement e Measured pulse input pin select function The CNTRSEL bit in the UCON register can select the CNTROO or CNTRO1 pin Rev 1 30 Dec 08 2006 Page 1160f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 008Bh 00h Bi Syro Function Operating mode select bits 0 1 b1 bo RW TXMOD1 11 Pulse width measurement mode INT1 CNTRO signal CNTRO ROEDG polarity switch bit 0 Measures L level w idth 1 Measures H level w idth NTI RW 0 Rising edge 1 Falling edge W Timer X count start flag 0 Stops counting NOTES 1 The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources 2 Refer to 14 1 6 Notes on Time
220. gital filter clock frequency x 3 or the minimum value of standard whichever is greater 2 When selecting the digital filter by the INTO input filter select bit use an INTO input LOW width of either 1 digital filter clock frequency x 3 or the minimum value of standard whichever is greater Figure 19 17 External Interrupt INTO Input Timing Diagram when Vcc 3 V Rev 1 30 Dec 08 2006 Page 295 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 Usage Notes 20 1 Notes on Clock Generation Circuit 20 1 1 Stop Mode When entering stop mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled and the CM 10 bit in the CM1 register to 1 stop mode An instruction queue pre reads 4 bytes from the instruction which sets the CM10 bit to 1 stop mode and the program stops Insert at least 4 NOP instructions following the JMP B instruction after the instruction which sets the CM10 bit to 1 e Program example to enter stop mode BCLR 1 FMRO CPU rewrite mode disabled BSET 0 PRCR Protect disabled FSET I Enable interrupt BSET 0 CM1 Stop mode JMP B LABEL_001 LABEL_001 NOP NOP NOP NOP 20 1 2 Wait Mode When entering wait mode set the FMRO1 bit in the FMRO register to O CPU rewrite mode disabled and execute the WAIT instruction An instruction queue pre reads 4 bytes from the WAIT instruction and the program stops Insert at least 4 NOP instructions after the WAIT instructio
221. gnments top view P3_5 SSCK SCL CMP1_ 2 lt gt gt P3_4 SCS SDA CMP1_1 P3_7 CNTRO SSO TXD1 lt gt lt gt P3_3 TCIN INT3 SSI00 CMP1_0 RESET gt a gt P1_0 KIO AN8S CMPO_0 XOUT P4_70 lt gt a k P1_1 KIT AN9 CMPO_1 VSS AVSS gt a P4_2 VREF XIN P4_6 gt 6 lt gt P1_2 KI2 AN10 CMPO_2 VCC AVCG gt ak P1_3 KIG AN11 TZOUT lt gt P1_4 TXDO P4_S INTO RXD1 9 a gt P1_5 RXDO CNTRO1 INTTT P1_7 CNTROO INT10 lt gt lt gt P1_6 CLKO SSI01 DD SL w gt 27 oO o S E oO NOTE 1 P4_7 is an input only port Package PLSP0020JB A 20P2F A Figure 1 4 Pin Assignments for PLSP0020JB A Package Top View Rev 1 30 Dec 08 2006 Page9o0f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview PIN assignments top view C P3_5 SSCK SCL CMP1_2 lt gt 1 lt 4 P3_4 SCS SDA CMP1_1 P3_7 CNTRO SSO TXD1 lt gt 2 lt P3_3 TCIN INT3 SSI00 CMP1_0 RESET gt 3 lt gt P1_0 KIO AN8 CMP0_0 XOUT P4_7 1 lt gt 4 lt gt P1_1 KI1 AN9 CMPO_1 VSS AVSS gt 5 lt t P4_2 VREF XIN P4_6 gt 6 lt gt P1_2 KI2 AN10 CMPO_2 dno19 g1 O8y dno V1 O8u VCC AVCC 7 lt 4 P1_3 KI3 AN11 TZOUT MODE 8 lt P1_4 TXDO P4_5 INTO RXD1 lt gt 9 lt gt P1_5 RXDO CNTRO1 INT11 P1_7 CNTROO INT10 gt gt 10 lt lt P1_6 CLKO SSI01 NOTE 1 P4_7 is an input only port Package PRDP0020BA A 20P4B Figure 1 5 Pin Assignments fo
222. gt Vdet2 when digital filter is disabled Digital filter Switch enabled disabled Available Available Sampling time Divide by n of fRING S x4 n 1 2 4 and 8 Divide by n of fRING S x4 n 1 2 4 and 8 Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 440f315 stENESAS R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit Voltage detection 2 Noise filter signal Internal E reference voltage F VCA1 register VCA13 bit Voltage detection 1 signal gt Vdet1 Figure 7 1 Block Diagram of Voltage Detection Circuit Voltage monitor 1 reset generation circuit VW1F1 to VW1F0 00b 01b Voltage detection 1 circuit fRING S VCC Digital Internal Voltage filter reference detection 1 signal voltage gt Voltage detection 1 signal is held H when VCA26 bit is set to 0 disabled Voltage monitor 1 reset signal VW1CO to VW1C1 VW1F0 to VW1F1 VW1C6 VW1C7 Bits in VW1C register VCA26 Bit in VCA2 register Figure 7 2 Block Diagram of Voltage Monitor 1 Reset Generation Circuit Rev 1 30 Dec 08 2006 Page 45 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Voltage detection 2 circuit 7 Voltage Detection Circuit Voltage monitor 2 interrupt reset generation circuit fRING S VCC Internal Noise filter Voltage detection reference voltage Filter width
223. gure 16 46 Example of Register Setting in Master Transmit Mode I2C bus Interface Mode Rev 1 30 Dec 08 2006 Page 227 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Master receive mode ICSR register TEND bit lt 0 ICCR1 register TRS bit 0 1 Set the TEND bit to 0 and set to master receive mode Set the TDRE bit to 0 2 2 Set the ACKBT bit to the transmit device ICSR register TDRE bit lt 0 3 Dummy read the ICDRR register ICIER register ACKBT bit 9 4 Wait for 1 byte to be received l 5 Judge last receive 1 Dumny read in ICDRR register 6 Read the receive data 7 Set the ACKBT bit of the last byte and set to disable the Read RDRF bit in ICSR register continuous receive operation RCVD 1 8 Read the receive data of last byte 1 9 Wait until the last byte is received 10 Set the STOP bit to 0 11 Generate the stop condition Last receive 1 12 Wait until the stop condition is generated 13 Read the receive data of the last byte Read ICDRR register I 14 Set the RCVD bit to 0 ICIER register ACKBT Bit 1 15 Set to slave receive mode ICCR1 register RCVD Bit 1 Read ICDRR register Read RDRF bit in ICSR register Yes ICSR register STOP bit lt 0 ICCR2 register SCP bit lt 0 BBSY bit 0 Read STOP
224. h memory e g RAM before Executing directly in user ROM area is possible executed executing Areas which can be User ROM area User ROM area rewritten However blocks which contain a rewrite control program are excluded 1 Software command restrictions None e Program and block erase commands e Cannot be run on any block which contains a rewrite control program e Read status register command cannot be executed Modes after program or erase Read status register mode Read array mode Modes after read status register Read status register mode Do not execute this command CPU status during auto write and auto erase Operating Hold state I O ports hold state before the command is executed Flash memory status detection e Read bits FMROO FMRO6 and FMRO7 in the FMRO register by a program e Execute the read status register command and read bits SR7 SR5 and SR4 in the status register Read bits FMROO FMRO06 and FMR07 in the FMRO register by a program Conditions for transition to erase suspend Set bits FMR40 and FMR41 in the FMR4 register to 1 by a program The FMR40 bit in the FMR4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated Conditions for transitions to program suspend Set bits FMR40 and FMR42 in the FMR4 register to 1 by a program The FMR40 bit in the FMR4 register is set to 1 and the interrupt reque
225. hdog timer fRING128 A HRAO1 1 amen timed AD imer imer HRAO1 0 Converter A AA Low speed on chip Power on oscillator reset circuit Voltage detection circuit CM10 1 Stop mode ze d Power on reset Oscillation Software reset I stop Interrupt request detection Main clock wAlT 4 instruction CM13 Divider A CPU clock i System clock CM06 0 CM17 to CM16 11b CM02 CM05 CMO Bits in CMO register CMo6 0 CM10 CM13 CM14 CM16 CM17 Bits in CM1 register CM17 to CM16 10b OCDO OCD1 OCD2 Bits in OCD register HRAOO HRA01 Bits in HRAO register CMOG 0 M17 to CM16 01b CMO06 0 CM17 to CM16 00b Detail of divider Oscillation Stop Detection Circuit Forcible discharge when OCDO 0 Pulse generation i circuit for clock Charge Main clock edge detection and discharge Oscillation Stop Detection charge discharge circuit Interrupt Generation control circuit Circuit Detection Oscillation stop ocp1 Watchdog detection Timer Interrupt Watchdog timer Voltage Watch Voltage monitor 2 2 Interrupt E interrupt OCD2 bit switch signal NOTE CM14 bit switch signal 1 Set the same value in bits OC
226. he VCC pin reaches the Vdet1 level or above the low speed on chip oscillator clock starts counting When the low speed on chip oscillator clock count reaches 32 the internal reset signal is held H and the MCU enters the reset sequence refer to Figure 6 3 The low speed on chip oscillator clock divide by 8 is automatically selected as the CPU after reset Refer to 4 Special Function Registers SFRs for the status of the SFR after power on reset The voltage monitor reset is enabled after power on reset Figure 6 6 shows an Example of Power On Reset Circuit and Operation 0 1 V to 2 7 V gt 0 8 VCC or above i lt _ within td P R Vecemin Vpor2 a timalt 2 tw Vpor1 Vdett Sampling time tw por2 tw Vpor2 Vdet1 Internal reset signal active L EE EE fRING S fRING S NOTES 1 The supply voltage must be held within the MCU s operating voltage range Vccmin or above over the sampling time 2 A sampling clock can be selected Refer to 7 Voltage Detection Circuit for details 3 Vdet1 indicates voltage detection level for the voltage detection 1 circuit Refer to 7 Voltage Detection Circuit for details 4 Refer to 19 Electrical Characteristics Figure 6 6 Example of Power On Reset Circuit and Operation Rev 1 30 Dec 08 2006 Page 42 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 6 Resets 6 3 Voltage Monitor 1 Reset A reset is applied using the on chip v
227. he terminal is assumed to be 4 5 pF Figure 17 11 Analog Input Pin and External Sensor Equivalent Circuit Rev 1 30 Dec 08 2006 Page 243 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter 17 8 Notes on A D Converter e Write to each bit other than bit 6 in the ADCONO register each bit in the ADCON register or the SMP bit in the ADCON2 register when A D conversion is stopped before a trigger occurs e When the VCUT bit in the ADCONI register is changed from 0 VREF not connected to 1 VREF connected wait for at least 1 us before starting A D conversion e After changing the A D operating mode select an analog input pin again e When using the one shot mode ensure that A D conversion is completed before reading the AD register The IR bit in the ADIC register or the ADST bit in the ADCONDO register can be used to determine whether A D conversion is completed e When using the repeat mode use the undivided main clock as the CPU clock e If the ADST bit in the ADCONDO register is set to 0 A D conversion stops by a program and A D conversion is forcibly terminated during an A D conversion operation the conversion result of the A D converter will be undefined If the ADST bit is set to 0 by a program do not use the value of the AD register Rev 1 30 Dec 08 2006 Page 244 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 Flash Memory 18 1 Overview I
228. her of the following can be selected e After reset count starts automatically e Count starts by writing to WDTS register Count stop condition Stop mode wait mode None Operation at time of underflow Watchdog timer interrupt or Watchdog timer reset watchdog timer reset Prescaler r PM12 0 Watchdog timer interrupt request CPU clock Watchdog timer O gt PM12 1 Watchdog CSPRO 1 timer reset Write to WDTR register Internal reset signal CSPRO Bit in CSPR register WDC7 Bit in WDC register PM12 Bit in PM1 register NOTE 1 When the CSPRO bit is set to 1 count source protection mode enabled OFFFh is set Figure 13 1 Block Diagram of Watchdog Timer Rev 1 30 Dec 08 2006 Page 103 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 13 Watchdog Timer Option Function Select Register b7 b6 b5 b4 b3 b2 b1 b Address Before Shipment OFFFFh FFh Bi Symbol Funcion Watchdog timer start 0 Starts w atchdog timer automatically after reset select bit 1 Watchdog timer is inactive after reset Reserved bit Set to 1 ROM code protect 0 ROM code protect disabled ROMCR disabled bit 1 ROMCP1 enabled E ROM code protect bit 0 ROM code protect enabled ROMGPI oo 1 ROM code protect disabled Reserved bits Set to 1 b6 b4 Count source protection 0 Count source protect mode enabled after reset CSPROINI mode after reset select 1
229. hip oscillator select 0 Selects low speed on chip oscillator Di 1 Selects high speed on chip oscillator NOTES Set the PRCO bit in the PRCR register to 1 write enable before rewriting the HRAO register Change the HRA01 bit under the follow ing conditions e HRAOO 1 high speed on chip oscillation e The CM14 bit in the CM1 register 0 low speed on chip oscillator on When setting the HRA01 bit to 0 low speed on chip oscillator selected do not set the HRAOO bit to 0 high speed on chip oscillator off at the same time Set the HRAOO bit to 0 after setting the HRA01 bit to 0 Figure 10 5 HRAO Register Rev 1 30 Dec 08 2006 Page 63 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit High Speed On Chip Oscillator Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 0021h When Shipping Function The frequency of the high speed on chip oscillator is adjusted w ith bits 0 to 7 High speed on chip oscillator frequency 8 MHz HRA1 register value when shipping fRING fast mode 0 Setting the HRA1 register to a low er value minimum value 00h results in a higher frequency Setting the HRA1 register to a higher value maximum value FFh results in a low er frequency NOTE 1 Set the PRCO bit in the PRCR register to 1 write enable before rewriting the HRA1 register 2 Adjust the HRA1 register so that the frequency of the high speed on chip oscillat
230. hronous Serial Interface 16 3 6 Bit Synchronization Circuit When setting the UC bus interface to master mode the high level period may become shorter in the following two cases e If the SCL signal is driven L level by a slave device e If the rise speed of the SCL signal is reduced by a load load capacity or pull up resistor on the SCL line Therefore the SCL signal is monitored and communication is synchronized bit by bit Figure 16 45 shows the Timing of Bit Synchronization Circuit and Table 16 8 lists the Time between Changing SCL Signal from L Output to High Impedance and Monitoring of SCL Signal Basis clock of SCL monitor timing SCL Internal SCL Figure 16 45 Timing of Bit Synchronization Circuit Table 16 8 Time between Changing SCL Signal from L Output to High Impedance and Monitoring of SCL Signal ICCR1 Register Time for Monitoring SCL CKS3 CKS2 7 51cyc 19 5Tcyc 17 5Tcyc 41 5Tcyc 1Tcyc 1 f1 s Rev 1 30 Dec 08 2006 Page 226 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 3 7 Examples of Register Setting 16 Clock Synchronous Serial Interface Figures 16 46 to 16 49 show Examples of Register Setting When Using DC bus interface Start Initial setting Read BBSY bit in ICCR2 register Yes ICCR1 register TRS bit lt 1 MST bit lt 1 ICCR2 register SCP bit 0 BBSY bit 1 Write transmit data
231. ial Mode Rev 1 30 Dec 08 2006 Page 223 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 4 3 Receive Operation In receive mode data is latched at the rising edge of the transfer clock The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0 Figure 16 43 shows the Operating Timing in Receive Mode Clock Synchronous Serial Mode The receive procedure and operation in receive mode are as follows 1 Set the ICE bit in the ICCR1 register to 1 transfer operation enabled Set bits CKSO to CKS3 in the ICCR1 register and set the MST bit initial setting 2 The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being output 3 Data is transferred from registers CDRS to ICDRR and the RDRF bit in the ICSR register is set to 1 when the receive operation is completed Since the next byte of data is enabled when the MST bit is set to 1 the clock is output continuously Continuous reception is enabled by reading the ICDRR register every time the RDRF bit is set to 1 An overrun is detected at the rise of the 8th clock cycle while the RDRF bit is set to 1 and the AL bit in the ICSR register is set to 1 At this time the last receive data is retained in the ICDRR register 4 When the MST bit is set to 1 set the RCVD bit in the ICCR1 register to 1 disables the next receive opera
232. ics 4 Vcc 3 V Topr 40 to 85 C unless otherwise specified Parameter Condition Standard Typ Power supply current Vcc 2 7 to 3 3 V Single chip mode output pins are open other pins are Vss A D converter is stopped High speed mode XIN 20 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz No division 8 XIN 16 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz No division XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz No division Medium speed mode XIN 20 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 XIN 16 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 High speed on chip oscillator mode Main clock off High speed on chip oscillator on 8 MHz Low speed on chip oscillator on 125 kHz No division Main clock off High speed on chip oscillator on 8 MHz Low speed on chip oscillator on 125 kHz Divide by 8 Low speed on chip oscillator mode Main clock off High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 FMR
233. ietegrkietZebege eg eneen 211 16 3 4 Clock Synchronous Serial Mode ceeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeees 222 162325 Ee 225 16 3 6 Bit Synchronization Cireut 226 16 3 7 Examples of Register Setting e 227 16 3 8 Notes on I2C bus Interface ce eeeececccceeeeseeeseeecseeeeeeeeseeeeteeseeeses 231 17 A D Converter 232 17 1 nee 236 17 2 Repeat ee 238 Z3 Sample ne Be EE 240 17 4 A D Conversion CyCles cccccceeeceeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 240 17 5 Internal Equivalent Circuit of Analog Input Block eeeeeeeeeeeeeeees 241 17 6 Inflow Current Bypass CirCuit cccececececceeeeeeeeeeceeeeeeeeeeeeeeeeeeeeeeeeees 242 17 7 Output Impedance of Sensor under A D Conversion ssssssssssssssrneeese 243 17 8 NOLES om A D CONVGRG eet 244 18 Flash Memory TA e EE 18 2 Memory Map E 18 3 Functions to Prevent Rewriting of Flash Memonm 18 3 1 ID Code Check HENGEL ee tege geed tvvenssatamecitosdcs 18 3 2 ROM Code Protect Function 0 ccccccccceeeeeeeeeeeeeeeeeees 18 4 CPU Rewrite Modew icccniaicciieaiaviainaianiaianiiaiean 18 41 EW ON MOA EE 18 4 2 EW TMOG EEN 18 4 3 Software Commande nnne 18 4 4 Status Register sieicecctccceesstetetotesestteiecenddecidiylectttieteeed ites 18 4 5 Full Status e 18 5 Standard Serial WO Mode 18 5 1 ID Code Check Function cccccccccccccccecceeeeeeeeeeeeeeeeeees 18 6 Parallel WO MMO i aere ee eege 18 6 1 ROM Code Pro
234. ignal is held L until data is available and the stop condition is generated Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1 When writing the number of bytes to be transmitted to the ICDRT register wait until the TEND bit is set to 1 while the TDRE bit is set to 1 Or wait for NACK the NACKF bit in the ICSR register is set to 1 from the receive device while the ACKE bit in the ICIER register is set to 1 when the receive acknowledge bit is set to 1 transfer is halted Then generate the stop condition before setting bits TEND and NACKF to 0 When the STOP bit in the ICSR register is set to 1 return to slave receive mode Rev 1 30 Dec 08 2006 Page 212 0f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SCL master output 1 2 3 4 5 6 7 SDA master output Slave address SDA slave output TDRE bit in ICSR register TEND bit in ICSR register ICDRT register Address R W ICDRS register Address RW Processing 2 Instruction of 3 Data write to ICDRT 4 Data write to ICDRT 5 Data write to ICDRT by program start condition register 1st byte register 2nd byte register 3rd byte generation Figure 16 33 Operating Timing in Master Transmit Mode I2C bus Interface Mode 1 SCL master output SDA master output SDA slave output TDRE bit in ICSR register TEND bit in ICSR register
235. igure 14 18 Operating Example of Timer Z in Programmable Waveform Generation Mode Rev 1 30 Dec 08 2006 Page 132 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 2 3 Programmable One shot Generation Mode In programmable one shot generation mode one shot pulse is output from the TZOUT pin by a program or an external trigger input input to the INTO pin refer to Table 14 9 Programmable One Shot Generation Mode Specifications When a trigger is generated the timer starts operating from the point only once for a given period equal to the set value in the TZPR register The TZSC register is not used in this mode Figure 14 19 shows Registers TZMR and PUM in Programmable One Shot Generation Mode Figure 14 20 shows an Operating Example in Programmable One Shot Generation Mode Table 14 9 Programmable One Shot Generation Mode Specifications Item Specification Count sources f1 f2 f8 Timer X underflow Count operations e Decrement the value set in the TZPR register e When the timer underflows it reloads the contents of the reload register before the count completes and the TZOS bit is set to 0 one shot stops e When the count stops the timer reloads the contents of the reload register before it stops One shot pulse n 1 m 1 fi output time fi Count source frequency n value set in PREZ register m value set in TZPR register Count start conditions Set the TZOS bit in the TZOC register to 1 o
236. il program erase 3 CPU clock restart x 4 cycles Program erase voltage 5 5 Read voltage 5 5 Program erase temperature 60 Data hold time 8 Ambient temperature 55 C NOTES Rev 1 30 Vcc 2 7 to 5 5 V at Topr 0 to 60 C unless otherwise specified Definition of programming erasure endurance The programming and erasure endurance is defined on a per block basis If the programming and erasure endurance is n n 100 or 10 000 each block can be erased n times For example if 1 024 1 byte writes are performed to block A a 1 Kbyte block and then the block is erased the programming erasure endurance still stands at one However the same address must not be programmed more than once per erase operation overwriting prohibited Endurance to guarantee all electrical characteristics after program and erase 1 to Min value can be guaranteed If emergency processing is required a suspend request can be generated independent of this characteristic In that case the normal time delay to suspend can be applied to the request However we recommend that a suspend request with an interval of less than 650 us is only used once because if the suspend state continues erasure cannot operate and the incidence of erasure error rises In a system that executes multiple programming operations the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the
237. imer Z Waveform Output Control Register b7 b6 b5 b4 b3 b2 bi bd Symbol Address After Reset 0084h 00h PUM SE Reserved bits Set to 0 b4 b0 Timer Z output level latch 0 Outputs H for primary period Outputs L for secondary period Outputs L w hen the timer is stopped TZOPL Outputs L for primary period Outputs H for secondary period Outputs H when the timer is stopped INTO pin one shot trigger Set to 0 in programmable w aveform generation INOSTG control bit mode INTO pin one shot trigger Set to 0 in programmable w aveform generation INOSEG R polarity select bit mode Figure 14 17 Registers TZMR and PUM in Programmable Waveform Generation Mode RW RW RW W Rev 1 30 Dec 08 2006 Page 131 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Set to 1 by program TZS bit in TZMR register s UUW UUU UU UU UU ee NUD RREE Timer Z Timer Z secondary primary H reloads reloads i i y i Set to 0 when interrupt request is acknowledged or set by program ra H Set to 0 by program TZOPL bit in PUM register i i i IR bit in TZIC register i H Waveform Waveform Waveform output starts output inverted output inverted SC Yy y i TZOUT pin output Primary period Secondary period Primary period The above applies under the following conditions PREZ 01h TZPR 01h TZSC 02h TZOC register TZOCNT bit 0 F
238. in PREX register m value set in TX register 1 count starts is written to the TXS bit in the TXMR register 0 count stops is written to the TXS bit in the TXMR register When timer X underflows timer X interrupt Divide ratio Count start condition Count stop condition Interrupt request generation timing INT10 CNTROO INT11 CNTRO1 pin functions CNTRO pin function Read from timer Write to timer Programmable I O port or INT1 interrupt input Programmable I O port The count value can be read out by reading registers TX and PREX e When registers TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each reload register of registers TX and PREX at the following count source input the data is transferred to the counter at the second count source input and the count re starts at the third count source input Timer X Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 008Bh 00h EE Operating mode select bits 0 1 je bo RW 0 0 Timer mode or pulse period measurement mm i INT1 CNTRO signal Si Rising edge ROEDG polarity sw itch bit 2 Falling edge Timer X count start flag 0 Stops counting 1 Starts counting al Set to Qi in timer mode NOTES The IR bit in the INT1IC register may be set to 1 requests interrupt w
239. in clock oscillation circuit is not used P4_6 and P4_7 can be used as input only ports 5 1 Functions of Programmable UO Ports The PDi_j G 0 to 7 bit in the PDi i 1 3 and 4 register controls I O of ports P1 P3_3 to P3_5 P3_7 and P4_5 The Pi register consists of a port latch to hold output data and a circuit to read pin states Figures 5 1 to 5 3 show the Configurations of Programmable I O Ports Table 5 2 lists the Functions of Programmable I O Ports Also Figure 5 5 shows Registers PD1 PD3 and PD4 Figure 5 6 shows Registers P1 and P3 Figure 5 9 shows Registers PURO and PURI and Figure 5 10 shows the DRR Register Table 5 2 Functions of Programmable UO Ports Operation when Value of PDi_j Bit in PDi Register Accessing SES ES Pi Register When PDi_j Bit is Set to 0 Input Mode When PDi_j Bit is Set to 1 Output Mode Reading Read pin input level Read the port latch Writing Write to the port latch Write to the port latch The value written to the port latch is output from the pin NOTE 1 Nothing is assigned to bits PD3_0 to PD3_2 PD3_6 PD4_0 to PD4_4 PD4_6 and PD4_7 5 2 Effect on Peripheral Functions Programmable I O ports function as I O ports for peripheral functions Refer to Table 1 6 Pin Name Information by Pin Number of PLSP0020JB A PRDP0020BA A Packages Table 5 3 lists the Settings of PDi_j Bit when Functioning as I O Ports for Peripheral Functions Refer to the description of each function f
240. ine set in the interrupt vector is stored in the PC After the interrupt sequence is completed instructions are executed from the starting address of the interrupt routine NOTE 1 This register cannot be used by user CPU clock Si rt CT e ct E m ct rt ES mi 12 13 1 4 18 e ef Address bus Address Undefined SP 2 SP 1 SP 4 VEC VEC 1 VEC 2 PC EC VEC 1 VEC 2 Interrupt d SP 2 SP 1 SP 4 VI i i Undefined contents contents contents contents n The undefined state depends on the instruction queue buffer A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions Figure 12 5 Time Required for Executing Interrupt Sequence Rev 1 30 Dec 08 2006 Page 86 of 315 v EN SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 5 Interrupt Response Time Figure 12 6 shows the Interrupt Response Time The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine The interrupt response time includes the period between interrupt request generation and the completion of execution of the instruction refer to a in Figure 12 6 and the period required to perform the interrupt sequence 20 cycles see b in Figure 12 6 Interrupt request is generated Interrupt request is acknowledged A Instruction in Instruction Interrupt sequence interrupt routine 20 cycles b
241. ing and stable If the new clock source is the main clock allow sufficient wait time in a program until oscillation is stabilized before exiting Table 10 2 Settings and Modes of Clock Associated Bits OCD Register CM1 Register CMO Register OCD2 CM17 CM16 CM13 CMO06 CM05 Modes High speed mode CH CH 00b 1 Medium Divide by 2 speed mode Divide by 4 01b 10b Divide by 8 Divide by 16 11b High speed No division and low speed Divide by 2 on chip Divide by 4 oscillator Divide by 8 modes Divide by 16 00b 01b 10b i i O O G CH oO CO CO O O CO 11b NOTE 1 Rev 1 30 The low speed on chip oscillator is used as the on chip oscillator clock when the CM14 bit in the CM1 register is set to 0 low speed on chip oscillator on and the HRAO1 bit in the HRAO register is set to 0 The high speed on chip oscillator is used as the on chip oscillator clock when the HRAOO bit in the HRAO register is set to 1 high speed on chip oscillator A on and the HRA01 bit in the HRAO register is set to 1 Dec 08 2006 Page 680f315 sENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 4 1 1 High Speed Mode The main clock divided by 1 no division provides the CPU clock If the CM14 bit is set to 0 low speed on chip oscillator on or the HRAOO bit in the HRAO register is set to 1 high speed on chip
242. ing the TXS bit until the count stops after writing 0 to the TXS bit After writing 0 to the TXS bit do not access registers associated with timer X except for the TXS bit until 0 can be read from the TXS bit 20 3 2 Notes on Timer Z e Timer Z stops counting after a reset Set the values in the timer and prescaler before the count starts Even if the prescaler and timer are read out in 16 bit units these registers are read 1 byte at a time by the MCU Consequently the timer value may be updated during the period when these two registers are being read e Do not rewrite bits TZMOD0 to TZMOD1 and the TZS bit simultaneously In programmable one shot generation mode and programmable wait one shot generation mode when setting the TZS bit in the TZMR register to 0 stops counting or setting the TZOS bit in the TZOC register to 0 stops one shot the timer reloads the value of the reload register and stops Therefore in programmable one shot generation mode and programmable wait one shot generation mode read the timer count value before the timer stops The TZS bit in the TZMR register has a function to instruct timer Z to start or stop counting and a function to indicate that the count has started or stopped 0 count stops can be read until the following count source is applied after 1 count starts is written to the TZS bit while the count is being stopped If the following count source is applied 1 can be read from the TZS bit After writi
243. initial value of the SP when an interrupt request is acknowledged After registers are saved the SP content is SP minus 4 When executing software number 32 to 63 INT instructions this SP is specified by the U flag Otherwise it is ISP Figure 12 8 Register Saving Operation Rev 1 30 Dec 08 2006 Page 88 of 315 2RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine the FLG register and PC which have been saved to the stack are automatically restored The program that was running before the interrupt request was acknowledged starts running again Restore registers saved by a program in an interrupt routine using the POPM instruction or others before executing the REIT instruction 12 1 6 9 Interrupt Priority If two or more interrupt requests are generated while a single instruction is being executed the interrupt with the higher priority is acknowledged Set bits ILVL2 to ILVLO to select the desired priority level for maskable interrupts peripheral functions However if two or more maskable interrupts have the same priority level their interrupt priority is resolved by hardware and the higher priority interrupts acknowledged The priority levels of special interrupts such as reset reset has the highest priority and watchdog timer are set by hardware Figure 12 9 shows the Priority Level
244. ins The main clock oscillation circuit includes an on chip feedback resistor which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip The main clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin Figure 10 7 shows Examples of Main Clock Connection Circuit During reset and after reset the main clock stops The main clock starts oscillating when the CM05 bit in the CMO register is set to O main clock on after setting the CM13 bit in the CM1 register to 1 XIN XOUT pin To use the main clock for the CPU clock source set the OCD2 bit in the OCD register to 0 selects main clock after the main clock is oscillating stably The power consumption can be reduced by setting the CMOS bit in the CMO register to 1 main clock stops if the OCD bit is set to 1 select on chip oscillator clock When an external clock is input to the XIN pin the main clock does not stop if the CM05 bit is set to 1 If necessary use an external circuit to stop the clock In stop mode all clocks including the main clock stop Refer to 10 4 Power Control for details MCU MCU on chip feedback resistor on chip feedback resistor XIN XOUT XIN XOUT S SH Externally derived clock ees CIN COUT VCC a he VSS Ceramic resonator external circuit External clock input circuit NOTE 1 Insert a damping resistor if required The r
245. ins a carry borrow or shift out bits that have been generated by the arithmetic and logic unit 2 8 2 Debug Flag D The D flag is for debugging only Set it to 0 2 8 3 Zero Flag Z The Z flag is set to 1 when an arithmetic operation results in 0 otherwise to 0 2 8 4 Sign Flag S The S flag is set to 1 when an arithmetic operation results in a negative value otherwise to 0 2 8 5 Register Bank Select Flag B Register bank 0 is selected when the B flag is 0 Register bank 1 is selected when this flag is set to 1 2 8 6 Overflow Flag O The O flag is set to 1 when the operation results in an overflow otherwise to 0 Rev 1 30 Dec 08 2006 Page 16 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 2 Central Processing Unit CPU 2 8 7 Interrupt Enable Flag I The flag enables maskable interrupts Interrupts are disabled when the flag is set to 0 and are enabled when the flag is set to 1 The flag is set to 0 when an interrupt request is acknowledged 2 8 8 Stack Pointer Select Flag U ISP is selected when the U flag is set to 0 USP is selected when the U flag is set to 1 The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL is 3 bits wide assigns processor interrupt priority levels from level 0 to level 7 If a requested interrupt has higher
246. interrupt the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started The CPU clock when exiting wait mode by a peripheral function interrupt is the same clock as the CPU clock when the WAIT instruction is executed FMRO Register FMSTP Bit 0 flash memory operates Time until Flash Memory Time until CPU Clock 1 flash memory stops is Activated T1 Period of system clock x 12 cycles 30 us max Period of system clock x 12 cycles is Supplied T2 Period of CPU clock x 6 cycles Same as above Time for Interrupt Sequence T3 Period of CPU clock x 20 cycles Same as above Remarks Following total time is the time from wait mode until an interrupt routine is executed Wait mode plash memoty CPU clock restart sequence Interrupt sequence activation sequence Interrupt request generated Figure 10 8 Time from Wait Mode to Interrupt Routine Execution Rev 1 30 Dec 08 2006 Page 71 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 4 3 Stop Mode Since the oscillator circuits stop in stop mode the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating The least power required to operate the MCU is in stop mode If the voltage applied to the VCC pin is VRAM or more the contents of internal RAM is maintained
247. is causes problems execute an instruction which changes the contents of this register when the TZOS bit is set to 0 one shot stop Timer Z Waveform Output Control Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset pogan 00h S sg Function Reserved bits Set to 0 b4 b0 Timer Z output level latch Function varies depending on operating mode INOSTG INTO pin Ep trigger control 0 INTO pin one shot trigger disabled RW bit timer Z 1 INTO pin one shot trigger enabled INOSEG INTO pin one shot trigger polarity 0 i Falling edge trigger RW select bit timer Z 1 Rising edge trigger NOTES 1 The INOSEG bit is enabled only when the INTOPL bit in the INTEN register is set to 0 one edge 2 Set the INOSTG bit to 1 after setting the INTOEN bit in the INTEN register and the INOSEG bit in the PUM register Figure 14 14 Registers TZOC and PUM Rev 1 30 Dec 08 2006 Page 126 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer Count Source Setting Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 008Eh 1 Do not switch count sources during a count operation Stop the timer count before sw itching count sources Figure 14 15 TCSS Register Rev 1 30 Dec 08 2006 Page 127 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 2 1 Timer Mode In timer mode a count source which is internally generated or timer X underflow is counted refer to Table 14 7 Timer
248. ister Circuit Specification Bit Oscillation Feedback Function Buffer Resistance OFF OFF XIN XOUT oscillation stop Ge OFF ON eon Our on XIN pin H output Value OFF ON XIN XOUT oscillation stop ON ON XIN XOUT oscillation OFF Input port X Oor 1 Table 5 17 Port P4_5 INTO RXD1 Register UCON INTEN Bit U1SEL1 U1SELO INTOEN dere 00b 0 Input port not pulled up 00b 0 Input port pulled up 00b 1 INTO input not pulled up Go 00b INTO input pulled up 01b em RXD1 input 00b Output port X 0or1 Rev 1 30 Dec 08 2006 Page 36 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports 5 5 Unassigned Pin Handling Table 5 18 lists Unassigned Pin Handling Figure 5 11 shows Unassigned Pin Handling Table 5 18 Unassigned Pin Handling Pin Name Connection Ports P1 P3_3 to P3_5 e After setting to input mode connect each pin to VSS via a resistor pull P3_7 P4_5 down or connect each pin to VCC via a resistor pull up 2 e After setting to output mode leave these pins open ll 2 Ports P4_6 P4_7 Connect to VCC via a pull up resistor 2 Port P4_2 VREF Connect to VCC RESET 8 Connect to VCC via a pull up resistor 2 NOTES 1 If these ports are set to output mode and left open they remain in input mode until they are switched to output mode by a program The voltage level of these pins may be undefined and the power supply current may increase while the ports remain in input mode The content
249. ister and then use the read data Example when reading receive buffer register MOV W OOA6H RO Read the UORB register e When writing data to the UiTB register in the clock asynchronous serial I O mode with 9 bit transfer data length write data to the high order byte first then the low order byte in 8 bit units Example when reading transmit buffer register MOV B XXH 00A3H Write the high order byte of UOTB register MOV B XXH 00A2H Write the low order byte of UOTB register Rev 1 30 Dec 08 2006 Page 168 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows Clock synchronous serial interface Clock synchronous serial I O with chip select SSU Clock synchronous communication mode ___ 4 wire bus communication mode 12C bus interface mode 12C bus Interface L Clock synchronous serial mode The clock synchronous serial interface uses the registers at addresses OOB8h to OOBFh Registers bits symbols and functions vary even for the same addresses depending on the mode Refer to the register diagrams of each function for details Also the differences between clock synchronous communication mode and clock synchronous serial mode are the options of the transfer clock clock output format and data output format 16 1 Mode Selection The
250. it Watchdog timer Watchdog reset timer Software reset Voltage monitor 2 reset VCA13 Bit in VCA1 register VCA26 VCA27 Bits in VCA2 register SFRs bits VCA26 VW1C0 and VW1C6 SFRs bits VCA13 VCA27 VW1C1 VW1C2 VW1FO VW1F1 VW1C7 VW2C2 and VW2C3 Pin CPU and SFR bits other than those listed above VW1C0 to VW1C2 VW1F0 VW1F1 VW1C6 VW1C7 Bits in VW1C register VW2C2 VW2C3 Bits in VW2C register Figure 6 1 Block Diagram of Reset Circuit Rev 1 30 Dec 08 2006 Page 380f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 6 Resets Table 6 2 shows the Pin Functions while RESET Pin Level is L Figure 6 2 shows CPU Register Status after Reset and Figure 6 3 shows Reset Sequence Table 6 2 Pin Functions while RESET Pin Level is L Pin Name Pin Functions P1 Input port P3_3 to P3_5 P3 7 Input port P4 2 P4 5toP4 7 Input port Data register RO Data register R1 Data register R3 Data register R2 Address register A0 Address register A1 Frame base register FB b19 bo 00000h Interrupt table register INTB Content of addresses OFFFEh to OFFFCh Program counter PC User stack pointer USP Interrupt stack pointer ISP Static base register SB Flag register FLG OBSZDC Figure 6 2 CPU Register Status after Reset RINGS If LU ai 20 cycles or more are needed M Internal reset signal Flash memory acti
251. it enable bit Si Disables transmit Enables transmit Receive interrupt enable bit 0 Disables receive data full and overrun error interrupt request 1 Enables receive data full and overrun error interrupt request TEE Transmit end interrupt enable bit 0 Disables transmit end interrupt request RW 1 Enables transmit end interrupt request Transmit interrupt enable bit 0 Disables transmit data empty interrupt request 1 Enables transmit data empty interrupt request NOTE 1 Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial UO with Chip Select for more information Figure 16 5 SSER Register Rev 1 30 Dec 08 2006 Page 1750f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Status Register b7 b6 b5 b4 b3 b2 b1 bO Address After Reset 00BCh 00h Bi Sym Loe ee Conflict error flag No conflict errors ee Conflict errors generated Nothing is assigned If necessary set to 0 When read the content is 0 ORER Overrun error flag i No overrun errors generated Overrun errors generated Nothing is assigned If necessary set to 0 b4 b3 When read the content is 0 RDRF Receive data register full i No data in SSRDR register 1 4 Data in SSRDR register Transmit end 5 0 The TDRE bit is set to 0 when transmitting the last bit of transmit data 1 The TDRE bit is set to 1 when transmitting the last bit o
252. it in the TZOC register is set to 0 the output from the TZOUT pin is inverted synchronously when timer Z underflows When set to 1 the value in the P1_3 bit is output from the TZOUT pin 9 1 Even when counting the secondary period the TZPR register may be read 2 The value set in registers TZPR and TZSC are made effective by writing a value to the TZPR register The set values are reflected in the waveform output beginning with the following primary period after writing to the TZPR register 3 The TZOCNT bit is enabled by the following e When counting starts e When a timer Z interrupt request is generated The contents after the TZOCNT bit is changed are reflected from the output of the following primary period Dec 08 2006 Page 130 of 315 stENESAS R8C 1A Group R8C 1B Group 14 Timers Timer Z Mode Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0080h 00h SE Reserved bits Set to 0 Timer Z operating mode bits b5 b4 PRW TZMODI 0 1 Programmable w aveform generation mode Timer Z write control bit Set to 1 in programmable w aveform generation TZWC mode RW Timer Z count start flag 0 Stops counting NOTES 1 When the TZS bit is set to 1 count starts the count value is written to the reload register only When the TZS bit is set to 0 count stops the count value is written to both reload register and counter 2 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit T
253. it in the VW1C register to 0 Set the CM14 bit in the CM1 register toO low speed on chip oscillator on Wait for 4 cycles of the sampling clock of No wait time the digital filter Set the VW1CO bit in the VW1C register to 1 voltage monitor 1 reset enabled NOTE 1 When the VW1CO bit is set to 0 disabled steps 3 4 and 5 can be executed simultaneously with 1 instruction Vdet1 Typ 2 85V Sampling clock of digital filter x 4 cycles 4 I i me l i i When the VW1C1 bit is set A to 0 digital filter enabled Mternal reset signal SE HE E eeng 1 I When the VW1C1 bit is set to 1 digital filter disabled l I ignal and the VW1C7 bit is set vere TT to 1 VW1C1 and VW1C7 Bits in VW1C Register The above applies under the following conditions VCA26 bit in VCA2 register 1 voltage detection 1 circuit enabled VW1CO bit in VW1C register 1 voltage monitor 1 reset enabled VW1C6 bit in VW1C register 1 voltage monitor 1 reset mode When the internal reset signal is held L the pins CPU and SFR are reset The internal reset signal level changes from L to H and a program is executed beginning with the address indicated by the reset vector Refer to 4 Special Function Register SFR for the SFR status after reset Figure 7 8 Operating Example of Voltage Monitor 1 Reset Rev 1 30 Dec 08 2006 Page 52 of
254. it is disabled w hen the SSUMS bit is set to 0 clock synchronous communication mode Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial I O with Chip Select for more information Figure 16 7 SSMR2 Register Rev 1 30 Dec 08 2006 Page 177 of 315 speeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Transmit Data Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOBEh FFh Store the transmit data The stored transmit data is transferred to the SSTRSR register and transmission is started when it is detected that the SSTRSR register is empty When the next transmit data is w ritten to the SSTDR register during the data transmission from py the SSTRSR register the data can be transmitted continuously When the MLS bit in the SSMR register is set to 1 transfer data with LSB first the data in which MSB and LSB are reversed is read after writing to the SSTDR register NOTE 1 Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial I O with Chip Select for more information SS Receive Data Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset OOBFh FFh Store the receive data il The receive data is transferred to the SSRDR register and the receive operation is completed when 1 byte of data has been received by the SSTRSR register At this time the next receive operation is possible Continuous reception is possible using registe
255. it of Interrupts Priority Level Date NOTE2 deleted Figure 14 1 Block Diagram of Timer X Peripheral data bus Data Bus revised 14 1 6 Precautions on Timer X When writing 1 count starts to writing 1 to the TXS bit gt 0 count stops can be read after the TXS bit is set to 1 revised Figure 14 11 Block Diagram of Timer Z Peripheral Data Bus Data Bus revised 14 2 5 Precautions on Timer Z When writing 1 count starts to writing 1 to the TZS bit gt Q count stops can be read after the TZS bit is set to 1 revised Figure 15 3 UOTB to U1TB UORB to U1RB and UOBRG to U1BRG Registers UARTi Transmit Buffer Register i 0 to 1 and UARTi Receive Buffer Register i 0 to 1 revised Table 15 5 Registers to Be Used and Settings in UART Mode UiBRG gt 0 to 7 revised Table 16 1 Mode Selection RE and TE Bits in SSER Register added 16 2 8 2 Selecting SSI Signal Pin added REVISION HISTORY R8C 1A Group R8C 1B Group Hardware Manual SC 1 00 Sep 09 2005 Description Summary Figure 16 46 Example of Register Setting in Master Transmit Mode Clock Synchronous Serial Mode e Set the IICSEL bit in the PMR register to 1 added Table 17 1 Performance of A D Converter e Analog Input Voltage OV to Vref OV to AVCC revised e NOTE1 Whe
256. ite mode enabled bits FMR15 and FMR16 can be written to To set this bit to 0 set it to 0 immediately after setting it first to 1 To set this bit to 1 set it to 1 RW RW RW RW W Figure 18 6 FMR1 Register Rev 1 30 Dec 08 2006 Page 256 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Address After Reset 01B3h 01000000b SE Erase suspend function 0 Disable FMR40 enable bit 1 Enable Pw EMRA1 Erase suspend request bit 0 Erase restart 1 Erase suspend request DT Program suspend request bit 0 Program restart 1 Program suspend request FMR43 Erase command flag 0 Erase not executed 1 Erase execution in progress FMR44 Program command flag 0 Program not executed 1 Program execution in progress Reserved bits Set to 0 b5 Read status flag 0 Disables reading Ge Wee Ms Enables reading Low pow er consumption read 0 Disable FMR47 mode enable bit 4 1 Enable NOTES 1 To set this bit to 1 set it to 1 immediately after setting it first to 0 Do not generate an interrupt betw een setting the bit to 0 and setting it to 1 This bit is enabled w hen the FMR40 bit is set to 1 enable and it can be written to during the period betw een issuing an erase command and completing the erase This bit is set to 0 during the periods other than the above In EWO mode it can be set to 0 and 1 by a program In
257. its CKSO to CKS2 SSSR register ORER bit lt 0 SSCRH register Set RSSTP bit SSER register RE bit lt 1 receive TE bit lt 1 transmit Set bits eg TEIE and TIE NOTE 1 Write 0 after reading 1 to set the ORER bit to 0 16 Clock Synchronous Serial Interface 1 The MLS bit is set to 0 for MSB first transfer The clock polarity and phase are set by bits CPHS and CPOS 2 Set the BIDE bit to 1 in bidirectional mode and set the I O of the SCS pin by bits CSSO to CSS1 Figure 16 18 Initialization in 4 Wire Bus Communication Mode Rev 1 30 Dec 08 2006 Page 192 0f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 6 2 Data Transmission Figure 16 19 shows an Example of Clock Synchronous Serial I O with Chip Select Operation during Data Transmission 4 Wire Bus Communication Mode During the data transmit operation clock synchronous serial I O with chip select operates as described below When the MCU is set as the master device it outputs a synchronous clock and data When the MCU is set as a slave device it outputs data in synchronization with the input clock while the SCS pin is L When the transmit data is written to the SSTDR register after setting the TE bit to transmit enabled the TDRE bit is automatically set to 0 data has not been transferred from registers SSTDR to SSTRSR and the data is transferred from registers SSTDR to SSTRSR
258. m Clock Generation gt System Clock Generator revised Table 1 3 Product Information of R8C 1A Group D and D Under development deleted Table 1 4 Product Information of R8C 1B Group D and D Under development deleted ROM capacity Program area gt Program ROM Data area gt Data flash revised Table 1 5 Pin Description Power Supply Input VCC AVCC gt VCO VSS AVSS gt VSS revised Analog Power Supply Input added Figure 2 1 CPU Register Reserved Area gt Reserved Bit revised 2 8 10 Reserved Area Reserved Area Reserved Bit revised 3 2 R8C 1B Group Figure 3 2 Memory Map of R8C 1B Group Data area gt Data flash Program area Program ROM revised Table 4 2 SFR Information 2 004Fh SSU IIC Interrupt Control Register SSUAIC IIC2AIC XXXXX000b added NOTE2 added Table 4 3 SFR Information 3 0085h Prescaler Z Prescaler Z Register 0086h Timer Z Secondary gt Timer Z Secondary Register 0087h Timer Z Primary gt Timer Z Primary Register 008Ch Prescaler X Prescaler X Register 008Dh Timer X Timer X Register 0090h 0091h Timer C Timer C Register revised 20 to 39 5 Reset gt 5 Programmable I O Ports and 6 Programmable I O Ports 6 Reset revised 31
259. mand writes data to the flash memory in byte units By writing 40h in the first bus cycle and data to the write address in the second bus cycle an auto program operation data program and verify will start Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle The FMROO0 bit in the FMRO register can be used to determine whether auto programming has completed When suspend function disabled the FMROO bit is set to 0 during auto programming and set to 1 when autoprogramming completes When suspend function enabled the FMR44 bit is set to 1 during auto programming and set to when autoprogramming completes The FMRO6 bit in the FMRO register can be used to determine the result of auto programming after it has been finished Refer to 18 4 5 Full Status Check Do not write additions to the already programmed addresses When the FMRO2 bit in the FMRO register is set to 0 rewriting disabled or the FMRO2 bit is set to 1 rewrite enabled and the FMR15 bit in the FMR1 register is set to 1 rewriting disabled program commands targeting block 0 are not acknowledged When the FMR16 bit is set to 1 rewriting disabled program commands targeting block are not acknowledged Figure 18 12 shows Program Command When Suspend Function Disabled Figure 18 13 shows Program Command When Suspend Function Enabled In EW1 mode do not execute this command for any address whi
260. mer X underflow Count operations Decrement e When the timer underflows it reloads the contents of the primary reload and secondary reload registers alternately before the count is continued Width and period of output waveform Primary period n 1 m 1 fi Secondary period n 1 p 1 fi Period n 1 m 1 p 1 fi fi Count source frequency n Value set in PREZ register m value set in TZPR register p value set in TZSC register Count start condition 1 count starts is written to the TZS bit in the TZMR register Count stop condition O count stops is written to the TZS bit in the TZMR register Interrupt request generation timing In half a cycle of the count source after timer Z underflows during the secondary period at the same time as the TZout output change timer Z interrupt TZOUT pin function Pulse output To use this pin as a programmable I O port select timer mode INTO pin function Programmable I O port or INTO interrupt input Read from timer The count value can be read out by reading registers TZPR and PREZ Write to timer The value written to registers TZSC PREZ and TZPR is written to the reload register only 2 Select functions NOTES e Output level latch select function The TZOPL bit can select the output level during primary and secondary periods e Programmable waveform generation output switch function When the TZOCNT b
261. mined Table 10 6 lists Determining Interrupt Source for Oscillation Stop Detection Watchdog Timer and Voltage Monitor 2 Interrupts e When the main clock restarts after oscillation stop switch the main clock to the clock source of the CPU clock and peripheral functions by a program e Figure 10 11 shows the Procedure for Switching Clock Source from Low Speed On Chip Oscillator to Main Clock e To enter wait mode while using the oscillation stop detection function set the CM02 bit to O peripheral function clock does not stop in wait mode e Since the oscillation stop detection function is a function for cases where the main clock is stopped by an external cause set bits OCD1 to OCDO to 00b oscillation stop detection function disabled when the main clock stops or is started by a program stop mode is selected or the CMOS bit is changed e This function cannot be used when the main clock frequency is 2 MHz or below In this case set bits OCD 1 to OCDO to 00b oscillation stop detection function disabled e To use the low speed on chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop set the HRAOI bit in the HRAO register to 0 low speed on chip oscillator selected and bits OCD1 to OCDO to 11b oscillation stop detection function enabled To use the high speed on chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation s
262. mit mode transmit data is output from the SDA pin in synchronization with the falling edge of the transfer clock The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0 Figure 16 42 shows the Operating Timing in Transmit Mode Clock Synchronous Serial Mode The transmit procedure and operation in transmit mode are as follows 1 Set the ICE bit in the ICCR1 register to 1 transfer operation enabled Set bits CKSO to CKS3 in the ICCR1 register and set the MST bit initial setting 2 The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the ICCR1 register to 1 3 Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1 Continuous transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1 When switching from transmit to receive mode set the TRS bit to 0 while the TDRE bit is set to 1 Pel Pe E f f a MEER eee Lt TRS bit in ICCR1 register TDRE bit in ICSR register ICDRT register ICDRS register Processing 3 Data write to 3 Data write to 3 Data write to 3 Data write to by program ICDRT register ICDRT register ICDRT register ICDRT register 2 Set TRS bit to 1 Figure 16 42 Operating Timing in Transmit Mode Clock Synchronous Ser
263. n e Program example to execute the WAIT instruction BCLR 1 FMRO CPU rewrite mode disabled FSET I Enable interrupt WAIT Wait mode NOP NOP NOP NOP 20 1 3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the main clock frequency is below 2 MHz set bits OCD1 to OCD0 to 00b oscillation stop detection function disabled in this case 20 1 4 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system 20 1 5 High Speed On Chip Oscillator Clock The high speed on chip oscillator frequency may be changed up to 10 in flash memory CPU rewrite mode during auto program operation or auto erase operation The high speed on chip oscillator frequency after auto program operation ends or auto erase operation ends is held the state before the program command or block erase command is generated Also this note is not applicable when the read array command read status register command or clear status register command is generated The application products must be designed with careful considerations for the frequency change NOTE 1 Change ratio to 8 MHz frequency adjusted in shipping Rev 1 30 Dec 08 2006 Page 296 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 2 Notes on Interrupts 20 2 1 Reading Address 00000h Do not read address 00000h by a program When a maskable i
264. n L is input to the KD pin which sets the KIiPL bit to 0 falling edge input to the other pins K10 to K13 is not detected as interrupts Also when H is input to the KD pin which sets the KIiPL bit to 1 rising edge input to the other pins K10 to K13 is not detected as interrupts Figure 12 17 shows a Block Diagram of Key Input Interrupt L PU02 bit in PURO register KUPIC register transistor KISEN bit PD1_3 bit GQ KISPL 0 o O O O O KI3PL 1 KI2EN bit Pull up PD1_2 bit transistor Q Kl2PL 0 o Interrupt control Key input interrupt O ebe o request KI2PL 1 KIEN bit Pul up PD1_1 bit ransistor d d KIIPL 0 d O o O O O KI1PL 1 KIOEN bit KIOEN KI1EN KI2EN KIBEN Pull up PD1 Obit KIOPL KI1PL KI2PL KI3PL Bits in KIEN register transistor J L KIOPL 0 PD1_0 PD1_1 PD1_2 PD1_3 Bits in PD1 register O gt e O O KIOPL 1 Figure 12 17 Block Diagram of Key Input Interrupt Rev 1 30 Dec 08 2006 Page 96 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts Key Input Enable Register b7 b6 b5 b4 b3 b2 b1 bO Address After Reset 0098h 00h Bi Symbol KIO input enable bit 0 Disable 1 Enable KIO input polarity select bit 0 Falling edge 1 Rising edge KI input enable bit 0 Disable 1 Enable KI input polarity select bit 0 Falling edge 1 Rising edge KI2 input enable bit 0 Disable 1 Enable KD input pol
265. n When the auto program operation ends the FMR44 bit is set to 0 program not executed 18 4 2 15 FMR46 Bit The FMR46 bit is set to 0 reading disabled during auto erase execution and set to reading enabled in erase suspend mode Do not access the flash memory while this bit is set to 0 18 4 2 16 FMR47 Bit Power consumption when reading flash memory can be reduced by setting the FMR47 bit to enabled Rev 1 30 Dec 08 2006 Page 254 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 01B7h 00000001b SE RY BY status flag 0 Busy writing or erasing in progress SEH 1 Ready CPU rew rite mode select bit 0 CPU rewrite mode disabled Block 0 1 rewrite enable bit O Disables rew rite Flash memory stop bit 5 0 Enables flash memory operation 1 Stops flash memory enters low pow er consumption state and flash memory is reset Reserved bits Set to 0 b5 b4 FMRO6 Program status flag K Completed successfully Terminated by error Erase status flag 0 Completed successfully NOTES To set this bit to 1 set it to 1 immediately after setting it first to 0 Do not generate an interrupt betw een setting the bit to 0 and setting it to 1 Enter read array mode and set this bit to 0 Set this bit to 1 immediately after setting it first to O w hile the FMRO1 bit is set to 1 Do not gene
266. n ee e ege eECNeTR Een Eege E Eee egg 42 6 3 Voltage Monitor 1 Reset AEN 43 6 4 Voltage Monitor 2 EE 43 6 5 Watchdog Timer Heset Aen 43 6 6 Software Reset eiee a aa e ind ductor aai 43 7 Voltage Detection Circuit 44 7 1 VCC Input EE 50 7 1 1 MOMORING VOOUT EE 50 G SE Oe eegne Ee 50 Ce KC SE el 50 7 2 Voltage Monitor FOS E 52 7 3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset nnnnnnnnnnnnanana 53 8 Processor Mode 55 8 1 Processor lee EE 55 9 Bus 57 10 Clock Generation Circuit 58 TOM WW CIO CK otis esis arena oan eas a a a E abate eaaa alias it 65 10 2 On Chip Oscillator Clocks 00 cccccceccceeeeeeeceeeeeeeeeeeceeeeeeeeeeeaaeeeeeeteeeeeeaaees 66 10 2 1 Low Speed On Chip Oscillator Clock 66 10 2 2 High Speed On Chip Oscillator Clock ssssssesseessennennesesnnnnnnnerrrrrenn 66 103 CPU Clock and Peripheral Function Cock 67 Enn Kee 67 10 3 2 CPU Cloke e p e a a 67 10 3 3 Peripheral Function Clock f1 f2 f4 f8 D 67 10 3 4 TRING and EEN 67 10 3 5 FRING FaSt an a A ear a a AtA 67 10 3 0 ENEE 67 10 4 Power GOI EE 68 10 4 1 Standard Operating Mode 2 cii sie sues Se eet oe es 68 10 42 Wat Mode eege eege 69 RL StD MOUE EE 72 10 5 Oscillation Stop Detection Function cccceeeceeeeeeeeeeeeeeeteeeeeeeeeeeeenaeees 74 10 5 1 How to Use Oscillation Stop Detection Function 0 eeeeeeees 74 10 6 Notes on Clock Generation Creunt 76 10 6 1 ee Mode EE 76 106 2 Wat el
267. n chip oscillator mode main clock stops Turn main clock on gt wait until oscillation stabilizes switch the clock source for CPU clock Write 0 to the FMSTP bit flash memory operation Write 0 to the FMRO1 bit CPU rewrite mode disabled Wait until the flash memory circuit stabilizes 30 ps Jump to a specified address in the flash memory 1 Set the FMRO1 bit to 1 CPU rewrite mode before setting the FMSTP bit to 1 2 Before switching to a different clock source for the CPU make sure the designated clock is stable 3 Insert a 30 us wait time in a program Do not access the flash memory during this wait time Figure 18 11 Process to Reduce Power Consumption in On Chip Oscillator Mode Main Clock Stops Rev 1 30 Dec 08 2006 Page 260 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 3 Software Commands The software commands are described below Read or write commands and data in 8 bit units Table 18 4 Software Commands First Bus Cycle Second Bus Cycle Command Data Data Mode Address D7 to DO Mode Address D7 to DO Read array Write FFh Read status register Write 70h Read SRD Clear status register Write 50h Program Write 40h Write WD Block erase Write 20h Write SRD Status register data D7 to DO WA Write address ensure the address specified in the first bus cycle is the same address as the write address
268. n the PC are saved Figure 12 7 shows the Stack State Before and After Acknowledgement of Interrupt Request The other necessary registers are saved by a program at the beginning of the interrupt routine The PUSHM instruction can save several registers in the register bank being currently used with a single instruction NOTE 1 Selectable from registers RO R1 R2 R3 AO A1 SB and FB Address Address MSB MSB SP New SP value FLGH PCH SP Previous stack contents 4 high order bits of PC 8 middle order bits of PC 8 low order bits of PC Previous stack contents 4 high order bits of FLG Ce 8 low order bits of FLG Stack state before interrupt request Stack state after interrupt request is acknowledged is acknowledged NOTE 1 When executing software number 32 to 63 INT instructions this SP is specified by the U flag Otherwise it is ISP Figure 12 7 Stack State Before and After Acknowledgement of Interrupt Request The register saving operation which is performed as part of the interrupt sequence saved in 8 bits at a time in four steps Figure 12 8 shows the Register Saving Operation Address Sequence in which order registers are saved Saved 8 bits at a time 4 high order bits of PC 8 middle order bits of PC 8 low order bits of PC Completed saving 4 high order bits of FLG registers in four 8 low order bits of FLG operations 1 SP indicates the
269. n the analog input voltage FFh in 8 bit mode added Figure 17 1 Block Diagram of A D Converter Vref gt Vcom revised Table 18 1 Flash Memory Version Performance Program and Erase Endurance Program area Program ROM Data area Data flash revised 18 2 Memory Map The user ROM area Block A and B gt The user ROM area program ROM Block A and B data flash revised Figure 18 1 Flash Memory Block Diagram for R8C 1A Group revised Figure 18 2 Flash Memory Block Diagram for R8C 1B Group revised 18 4 3 5 Block Erase The block erase command cannot program suspend added Table 19 3 A D Converter Characteristics Vref and VIA Standard value NOTE4 revised Table 19 4 Flash Memory Program ROM Electrical Characteristics NOTES3 and 5 revised NOTES deleted Table 19 5 Flash Memory Data flash Block A Block B Electrical Characteristics NOTES1 and 3 revised Table 19 8 Reset Circuit Electrical Characteristics When Using Voltage Monitor 1 Reset NOTE2 revised Table 19 10 High speed On Chip Oscillator Circuit Electrical Characteristics High Speed On Chip Oscillator gt High Speed On Chip Oscillator Frequency revised NOTE2 added Table 19 15 Electrical Characteristics 2 Vcc 5V NOTE1 deleted Table 19 22 Electrical Characteristics 4 Vcc 3V NOTE1 deleted 20 3 1 Precautions on Timer X When writing 1 count starts to writing
270. n the flash memory rewrite operations to the flash memory can be performed in three modes CPU rewrite standard serial I O and parallel I O Table 18 1 lists the Flash Memory Performance refer to Table 1 1 Functions and Specifications for R8C 1A Group and Table 1 2 Functions and Specifications for R8C 1B Group for items not listed in Table 18 1 Table 18 1 Flash Memory Performance Item Specification Flash memory operating mode 3 modes CPU rewrite standard serial I O and parallel I O mode Division of erase block Refer to Figure 18 1 and Figure 18 2 Programming method Byte unit Erase method Block erase Programming and erasure Program and erase control by software command control method Rewrite control method Rewrite control for blocks 0 and 1 by FMRO2 bit in FMRO register Rewrite control for block 0 by FMR15 bit and block 1 by FMR16 bit in FMR1 register Number of commands 5 commands Programming Blocks 0 and 1 R8C 1A Group 100 times R8C 1B Group 1 000 times and erasure program ROM endurance Blocks A and B 10 000 times data flash 2 ID code check function Standard serial UO mode supported ROM code protect Parallel UO mode supported NOTES 1 Definition of programming and erasure endurance The programming and erasure endurance is defined on a per block basis If the programming and erasure endurance is n n 100 or 10 000 each block can be erased n times For example if 1 024 1 byte wri
271. nd ICDRS Port Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOF8h 00h BT Sb kt Kaes Reserved bits Set to 0 b2 b0 SSISEL SSI signal pin select bit o P3_3 pin is used for SSI00 pin P1_6 pin is used for SSI01 pin Reserved bits Set to 0 Eier EEN ICSEL SSU PC bus switch bit 0 Selects SSU function 1 Selects FC bus function Figure 16 31 PMR Register Rev 1 30 Dec 08 2006 Page 208 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 1 Transfer Clock When the MST bit in the ICCR1 register is set to 0 the transfer clock is the external clock input from the SCL pin When the MST bit in the ICCR1 register is set to 1 the transfer clock is the internal clock selected by bits CKSO to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin Table 16 6 lists the Transfer Rate Examples Table 16 6 Transfer Rate Examples ICCR1 Register Transfer Transfer Rate CKS3 CKS2 CKS1 CKSO Clock f1 5 MHz f1 8 MHz f1 10 MHz f1 16 MHz f1 20 MHz 0 0 0 0 f1 28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 64 78 1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 1 80 62 5 kHz 100 kHz 125 kHz 200 kHz 250 kHz f1 100 50 0 kHz 80 0 kHz 100 kHz 160 kHz 200 kHz f1 112 44 6 kHz 71 4kHz 89 3 kHz 143 kHz 179 kHz f1 128 39 1 kHz
272. nd Usage Conditions CM02 1 Serial interface interrupt Usable when operating with internal or external clock Usable when operating with external clock Key input interrupt Usable Usable A D conversion interrupt Usable in one shot mode Do not use Timer X interrupt Usable in all modes Usable in event counter mode Timer Z interrupt Usable in all modes Do not use Timer C interrupt Usable in all modes Do not use INT interrupt Usable Usable INTO and INT3 can be used if there is no filter Voltage monitor 2 interrupt Usable Usable Oscillation stop detection interrupt Rev 1 30 REJ09B0252 0130 Usable Dec 08 2006 Page 700f315 stENESAS Do not use R8C 1A Group R8C 1B Group 10 Clock Generation Circuit Figure 10 8 shows the Time from Wait Mode to Interrupt Routine Execution To use a peripheral function interrupt to exit wait mode set up the following before executing the WAIT instruction 1 Set the interrupt priority level in bits ILVL2 to ILVLO in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode Set bits ILVL2 to ILVLO of the peripheral function interrupts that are not to be used for exiting wait mode to 000b interrupt disabled Set the I flag to 1 Operate the peripheral function to be used for exiting wait mode 2 3 When exiting by a peripheral function
273. ne shot starts 1 Input active trigger to the INTO pin 2 Count stop conditions e When reloading completes after the count value is set to 00h e When the TZS bit in the TZMR register is set to 0 count stops When the TZOS bit in the TZOC register is set to 0 one shot stops Interrupt request In half a cycle of the count source after the timer underflows at the same time as generation timing the TZOUT output ends timer Z interrupt TZOUT pin function Pulse output To use this pin as a programmable UO port select timer mode INTO pin function When the INOSTG bit in the PUM register is set to 0 INTO one shot trigger disabled programmable UO port or INTO interrupt input When the INOSTG bit in the PUM register is set to 1 INTO one shot trigger enabled external trigger INTO interrupt input Read from timer The count value can be read out by reading registers TZPR and PREZ Write to timer The value written to registers TZPR and PREZ is written to the reload register only 3 Select functions e Output level latch select function The TZOPL bit can select the output level of the one shot pulse waveform e INTO pin one shot trigger control and polarity select functions The INOSTG bit can select the trigger as active or inactive from the INTO pin Also the INOSEG bit can select the active trigger polarity NOTES 1 Set the TZS bit in the TZMR register to 1 count starts 2 S
274. ng 1 to the TZS bit do not access registers associated with timer Z registers TZMR PREZ TZSC TZPR TZOC PUM TCSC and TZIC except for the TZS bit until 1 can be read from the TZS bit The count starts at the following count source after the TZS bit is set to 1 Also after writing 0 count stops to the TZS bit during the count timer Z stops counting at the following count source 1 count starts can be read by reading the TZS bit until the count stops after writing 0 to the TZS bit After writing 0 to the TZS bit do not access registers associated with timer Z except for the TZS bit until 0 can be read from the TZS bit Rev 1 30 Dec 08 2006 Page 300 of 315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 3 3 Notes on Timer C Access registers TC TMO and TM1 in 16 bit units The TC register can be read in 16 bit units This prevents the timer value from being updated between when the low order bytes and high order bytes are being read Example of reading timer C MOV W 0090H RO Read out timer C Rev 1 30 Dec 08 2006 Page 301 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 4 Notes on Serial Interface e When reading data from the UORB register either in the clock asynchronous serial I O mode or in the clock synchronous serial I O mode Ensure the data is read in 16 bit units When the high order byte of the UORB register is read bits PER and FER in the UORB
275. ng auto program operation or auto erase operation The high speed on chip oscillator frequency after auto program operation ends or auto erase operation ends is held the state before the program command or block erase command is generated Also this note is not applicable when the read array command read status register command or clear status register command is generated The application products must be designed with careful considerations for the frequency change NOTE 1 Change ratio to 8 MHz frequency adjusted in shipping Rev 1 30 Dec 08 2006 Page 760f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 11 Protection 11 Protection The protection function protects important registers from being easily overwritten when a program runs out of control Figure 11 1 shows the PRCR Register The registers protected by the PRCR register are listed below e Registers protected by PRCO bit Registers CM0 CM1 and OCD HRAO HRA1 and HRA2 e Registers protected by PRC1 bit Registers PMO and PM1 e Registers protected by PRC3 bit Registers VCA2 VWIC and VW2C Protect Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 000Ah 00h Bi Symbol Protect bit 0 Writing to registers CMO CM OCD HRAO HRA1 and HRA2 is enabled 0 Disables writing 1 Enables writing Protect bit 1 Writing to registers PMO and PM1 is enabled 0 Disables writing e E bit 3 Writing to registers VCA2 VW1C and VW2C is enabled 0 Disa
276. ngs Tables 5 4 to 5 17 list the port settings Table 5 4 Register Port P1_0 KIO AN8 CMPO_0 ADCONO TCOUT Bit CH2 CH1 CHO ADGSELO TCOUTO Function Setting Value XXXXb x Input port not pulled up XXXXb x Input port pulled up 0 1 XXXXb X KIO input 0 X 1001b X A D Converter input AN8 X X XXXXb X Output port X X XXXXb X Output port High drive X X 0 X XXXXb 0 Output port x X 1 X XXXXb 1 0 Output port High drive X X X X XXXXb 1 1 CMP0_0 output X 0or1 Table 5 5 Port P1_1 KI1 AN9 CMPO_1 Register ADCONO TCOUT i Bit CH2 CH1 CHO ADGSELO TCOUT1 E GE x x Input port not pulled up x x Input port pulled up X X KIT input x X A D converter input AN9 SE 0 X Output port 1 X Output port high drive 0 0 Output port 1 0 Output port high drive X 1 CMP0_1 output X 0 or 1 Table 5 6 Port P1_2 KI2 AN10 CMPO_2 Register ADCONO TCOUT P1 Bit CH2 CH1 CHO ADGSELO TCOUT2 P1_2 SE 0 X XXXXb X Input port not pulled up 1 X XXXXb X Input port pulled up 0 D XXXXb X KIZ input 0 X 1101b X A D converter input AN10 SE xX 0 XXXXb X Output port x 1 XXXXb x Output port high drive X 0 XXXXb 0 Output port x 1 XXXXb 0 Output port high drive X X XXXXb 1 CMPO 2 input X 0 or 1 Rev 1 30 Dec08 2006 Page 32 of 315 2tENESAS REJ09B0252 0130
277. nics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics tENESAS C 7 D me d lt D D R8C 1A Group R8C 1B Group Hardware Manual RENESAS 16 BIT SINGLE CHIP MICROCOMPUTER R8C FAMILY R8C 1x SERIES CO All information contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http Awww renesas com Renesas Electronics www renesas com Rev 1 30 2006 12 10 11 12 13 Notes regarding these materials This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document
278. nly be changed while no interrupt requests corresponding to that register are generated If interrupt requests may be generated disable interrupts before changing the interrupt control register contents b When changing the contents of an interrupt control register after disabling interrupts be careful to choose appropriate instructions Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction the IR bit may not be set to 1 interrupt requested and the interrupt request may be ignored If this causes a problem use the following instructions to change the register AND OR BCLR BSET Changing IR bit If the IR bit is set to 0 interrupt not requested it may not be set to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag as shown in the sample programs below Refer to b regarding changing the contents of interrupt control registers by the sample programs Sample programs to 3 are for preventing the I flag from being set to 1 interrupts enabled before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer Example 1 Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCHI1 FCLR I Disable interrupts AND PB 00H 0056H Set TXIC register to 0
279. nput Enable Register INTEN ER 90D4h_ A D Control Register 2 ADCON2 235 3097h O0D5h 0098h Key Input Enable Register KIEN 97 00D6h A D Control Register 0 ADCONO 234 0099h 00D7h A D Control Register 1 ADCONT 234 009Ah Timer C Control Register 0 TCCO 144 00D8h 009Bh Timer C Control Register 1 TC 145 O0D9h 009Ch Capture Compare 0 Register TMO 143 OODAh 009Dh 00DBh 009Eh Compare 1 Register TM1 143 00DCh DER 00DDh 00A0h UARTO Transmit Receive Mode Register UOMR 155 OODEh OOATh UARTO Bit Rate Register UOBRG 154 HEEN 00A2h UARTO Transmit Buffer Register U0TB 154 O0E0h 00A3h OOE1h Port P1 Register P1 29 00A4h UARTO Transmit Receive Control Register 0 UOCO 156 HEN pai l O0A5h UARTO Transmit Receive Control Register 1 UOCT 157 SOESh Ee ET Direction Register E 29 O0AGh UARTO Receive Buffer Register UORB 154 00E4h O0A7h OOE5h Port P3 Register P3 29 O0ABh UART1 Transmit Receive Mode Register UIMR 155 EE 00A9h UART1 Bit Rate Register UIBRG 154 O0E7h__ Port P3 Direction Register PD3 29 OOAAH UARTI Transmit Buffer Register rg 154 OOE8h Port P4 Register P4 30 SOEN OOE9h OOACh UART1 Transmit Receive Control Register 0 U1C0 156 QOEAh __ Port P4 Direction Register PD4 29 O0ADh UARTI Transmit Receive Control Register 1 U1C1 157 OOEBh OOAEh UART1 Receive Buffer Register UIRB 154 O0ECh SE O0EDA 00B0h UART Transmit Receive Control Register 2 UCON 157 HEN SOS OOEFh 00B2h OOFOh O0B3h OOF th 00B4h O0F2h DOEN O0F3h 00B6h
280. nput with a switch 2 Connecting an oscillator is necessary Set the main clock frequency to between 1 MHz and 20 MHz Refer to Appendix 2 1 Connection Examples with M16C Flash Starter M3A 0806 Figure 18 18 Pin Processing in Standard Serial UO Mode 2 MODE VO Reset input User reset signal NOTES 1 Controlled pins and external circuits vary depending on the programmer Refer to the programmer manual for details 2 In this example modes are switched between single chip mode and standard serial I O mode by connecting a programmer 3 When operating with the on chip oscillator clock it is not necessary to connect an oscillating circuit Figure 18 19 Pin Processing in Standard Serial UO Mode 3 Rev 1 30 Dec 08 2006 Page 272 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 6 Parallel UO Mode Parallel I O mode is used to input and output software commands addresses and data necessary to control read program and erase the on chip flash memory Use a parallel programmer which supports this MCU Contact the manufacturer of the parallel programmer for more information and refer to the user s manual of the parallel programmer for details on how to use it ROM areas shown in Figures 18 1 and 18 2 can be rewritten in parallel I O mode 18 6 1 ROM Code Protect Function The ROM code protect function disables the reading and rewriting of the flash memory Refer to the 18
281. ns are Vss A D converter is stopped High speed mode XIN 20 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz No division 9 XIN 16 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz No division XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz No division Medium speed mode XIN 20 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 XIN 16 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 High speed on chip oscillator mode Main clock off High speed on chip oscillator on 8 MHz Low speed on chip oscillator on 125 kHz No division Main clock off High speed on chip oscillator on 8 MHz Low speed on chip oscillator on 125 kHz Divide by 8 Low speed on chip oscillator mode Main clock off High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 FMR47 1 Wait mode Main clock off High speed on chip oscillator off Low speed on chip oscillator on 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 VCA26 0 Wait mode
282. ntermeasures against Noise Error of Port Control Registers 308 21 Notes on On Chip Debugger 309 Appendix 1 Package Dimensions 310 Appendix 2 Connection Examples between Serial Writer and On Chip Debugging Emulator 312 Appendix 3 Example of Oscillation Evaluation Circuit 313 Register Index 314 SFR Page Reference Address Register Symbol Page Address Register Symbol Page 0000h 0040h 0001h 0041h 0002h 0042h 0003h 0043h 0004h Processor Mode Register 0 PMO 55 0044h 0005h Processor Mode Register 1 PM1 56 0045h 0006h System Clock Control Register 0 CMO 60 0046h 0007h System Clock Control Register 1 CM1 61 0047h 0008h 0048h 0009h Address Match Interrupt Enable Register AIER 99 0049h 000Ah Protect Register PRCR 77 004Ah 000Bh 004Bh 000Ch Oscillation Stop Detection Register OCD 62 004Ch 000Dh Watchdog Timer Reset Register WDTR 105 004Dh Key Input Interrupt Control Register KUPIC 83 000Eh Watchdog Timer Start Register WDTS 105 004Eh A D Conversion Interrupt Control Register ADIC 83 000Fh Watchdog Timer Control Register WDC 104 004Fh SSU IIC Interrupt Control Register SSUAIC IIC2AIC 83 0010h Address Match
283. nterrupt request is acknowledged the CPU reads interrupt information interrupt number and interrupt request level from 00000h in the interrupt sequence At this time the acknowledged interrupt IR bit is set to 0 If address 00000h is read by a program the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 20 2 2 SP Setting Set any value in the SP before an interrupt is acknowledged The SP is set to 0000h after reset Therefore if an interrupt is acknowledged before setting a value in the SP the program may run out of control 20 2 3 External Interrupt and Key Input Interrupt Either L level or H level of at least 250 ns width is necessary for the signal input to pins INTO to INT3 and pins KIO to KT3 regardless of the CPU clock 20 2 4 Watchdog Timer Interrupt Reset the watchdog timer after a watchdog timer interrupt is generated Rev 1 30 Dec 08 2006 Page 297 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 2 5 Changing Interrupt Sources The IR bit in the interrupt control register may be set to interrupt requested when the interrupt source changes When using an interrupt set the IR bit to 0 no interrupt requested after changing the interrupt source In addition changes of interrupt sources include all factors that change the interrupt s
284. o 1 When the TZS bit is set to 0 count stops timer Z count value is written to both reload register and counter regardless of the setting value of the TZWC bit 2 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit Timer Z Waveform Output Control Register b7 b6 b5 b4 b3 b2 bi bd Address After Reset 0084h 00h PUM SE Reserved bits Set to 0 Timer Z output level latch Set to 0 in timer mode INOSTG INTO pin one shot trigger Get to 0 in timer mode RW control bit INOSEG INTO pin one shot trigger Set to 0 in timer mode ou polarity select bit Figure 14 16 Registers TZMR and PUM in Timer Mode Rev 1 30 Dec 08 2006 Page 129 0f 315 peENESAS REJ09B0252 0130 Rev 1 30 REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 2 2 Programmable Waveform Generation Mode In programmable waveform generation mode the signal output from the TZOUT pin is inverted each time the counter underflows while the values in registers TZPR and TZSC are counted alternately refer to Table 14 8 Programmable Waveform Generation Mode Specifications Counting starts by counting the value set in the TZPR register Figure 14 17 shows Registers TZMR and PUM in Programmable Waveform Generation Mode Figure 14 18 shows an Operating Example of Timer Z in Programmable Waveform Generation Mode Table 14 8 Item Programmable Waveform Generation Mode Specifications Specification Count sources f1 f2 f8 ti
285. ocatable vector table R8C Tiny Manual Series Software Address match OFFE8h to OFFEBh 12 4 Address Match Interrupt Single step 1 OFFECh to OFFEFh e Watchdog timer e Oscillation stop detection e Voltage monitor 2 OFFFOh to OFFF3h e 13 Watchdog Timer e 10 Clock Generation Circuit e 7 Voltage Detection Circuit Address break 1 OFFF4h to OFFF7h Reserved OFFF8h to OFFFBh Reset NOTE OFFFCh to OFFFFh 6 Resets 1 Do not use these interrupts They are for use by development support tools only Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 81 of 315 7tENESAS R8C 1A Group R8C 1B Group 12 Interrupts 12 1 5 2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register Table 12 2 lists the Relocatable Vector Tables Table 12 2 Interrupt Source Relocatable Vector Tables Vector Address 1 Address L to Address H Software Interrupt Number Reference BRK instruction 2 0 to 3 0000h to 0003h 0 Reserved 1to 12 R8C Tiny Series Software Manual Key input 52 to 55 0034h to 0037h 13 12 3 Key Input Interrupt A D conversion 56 to 59 0038h to 003Bh 14 17 A D Converter Clock synchronous serial I O with chip select 12C bus interface 3 60 to 63 003Ch to 003Fh 15 16 2 Clock Synchronous Serial
286. ocessing 1 Data write to ICDRT 2 Data write to ICDRT by program register data 1 register data 2 Figure 16 37 Operating Timing in Slave Transmit Mode GC bus Interface Mode 1 Rev 1 30 Dec 08 2006 Page 218 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Slave receive mode Slave transmit mode i gt wees LIST US fol fol fr UL SDA master outpu slave ou Weg E E E E E ER ER TDRE bit in ICSR register TEND bit in ICSR register A TRS bit in ICCR1 register 1 Processing 3 Set TEND bit to 0 4 Dummy read of ICDRR register by program after setting TRS bit to 0 5 Set TDRE bit to 0 Figure 16 38 Operating Timing in Slave Transmit Mode 12C bus Interface Mode 2 Rev 1 30 Dec 08 2006 Page 219 0f 315 v ENE SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 3 5 Slave Receive Operation In slave receive mode the master device outputs the transmit clock and data and the slave device returns an acknowledge signal Figures 16 39 and 16 40 show the Operating Timing in Slave Receive Mode ZC bus Interface Mode The receive procedure and operation in slave receive mode are as follows 1 Set the ICE bit in the ICCR1 register to 1 transfer operation enabled Set bits WAIT and MLS in the ICMR register and bits CKSO to CKS3 in the ICCR1 register initial setting
287. of A D conversion result Read AD register Rev 1 30 Dec 08 2006 Page 236 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset Doren a Analog input pin select b2 b1 b bits 100 AN8 101 AN9 110 AN10 111 AN11 Other than above Do not set A D operating mode select 0 One shot mode bit A D input group select bit Si Geer ADCAP A D conversion automatic SS Starts at Ze are _ ADST bit start bit Starts at capture timer Z interrupt ADST A D conversion start flag SE Disables A D conversion Starts A D conversion Frequency select bit 0 weg CKS1 in ADCON1 register 0 Selects f4 1 Selects f2 When CKS1 in ADCON1 register 1 0 Selects f1 1 fRING fast NOTES If the ADCONO register is rew ritten during A D conversion the conversion result is undefined Bits CHO to CH2 are enabled w hen the ADGSELO bit is set to 1 After changing the A D operating mode select the analog input pin again Set AD frequency to 10 MHz or below A D Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 00D7h on SEHR ess bits Set to 0 b2 b0 8 10 bit mode select bit 0 8 bit mode CKS1 Frequency select bit 1 Refer to the description of the CKSO bit in the RW ADCONO register function Vref connect bz 1 Vref connected Reserved bits Set to 0 NOTES 1 If the ADCON1 register is rew ri
288. of the direction registers may change due to noise or program runaway caused by noise In order to enhance program reliability the program should periodically repeat the setting of the direction registers 2 Connect these unassigned pins to the MCU using the shortest wire length 2 cm or less possible 3 When the power on reset function is in use Port P1 P3_3 to P3_7 Input mode Input mode Output mode Port P4_6 P4_7 RESET Port P4_2 VREF OTE 1 When the power on reset function is in use Figure 5 11 Unassigned Pin Handling Rev 1 30 Dec 08 2006 Page 37 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 6 Resets 6 Resets The following resets are implemented hardware reset power on reset voltage monitor 1 reset voltage monitor 2 reset watchdog timer reset and software reset Table 6 1 lists the Reset Names and Sources Table 6 1 Reset Names and Sources Reset Name Source Hardware reset Input voltage of RESET pin is held L VCC rises Power on reset Voltage monitor 1 reset VCC falls monitor voltage Vdet1 Voltage monitor 2 reset VCC falls monitor voltage Vdet2 Watchdog timer reset Underflow of watchdog timer Software reset Hardware reset RESET O Write 1 to PMO3 bit in PMO register Power on Power on reset reset circuit Voltage monitor 1 reset Voltage detection circu
289. ollowing total time is flash memory operates x a 2 cycles 20 Us max x 6 cycles x 20 cycles the time from stop eriod of system cloc mode until an interrupt flash memory stops x 12 cycles same as above handling is executed Oscillation time of Internal power CPU clock source Flash memory CPU clock restart stability time used immediately activation sequence sequence before stop mode AN 150 us Interrupt max request generated Interrupt sequence Figure 10 9 Time from Stop Mode to Interrupt Routine Execution Figure 10 10 shows the State Transitions in Power Control Low speed on chip oscillator mode OCD2 1 There are six power control modes High speed mode 1 Medium speed mode High speed on chip oscillator mode High speed mode Low speed on chip oscillator mode medium speed mode 0 Wait mode h 1 2 3 4 5 6 Stop mode gt lt a I 1 st OO HRAOO 1 HRAO1 1 High speed on chip CMOS Bit in CMO register oscillator mode CM10 CM13 CM14 Bit in CM1 register OCD2 1 OCD2 Bit in OCD register HRAO1 1 HRAOO HRAO1 Bit in HRAO register HRAOO 1 WAIT Interrupt CM10 1 Interrupt S instruction all oscillators stop Wait mode Stop mode Figure 10 10 State Transitions in Power Control Rev 1 30 Dec 08 2006 Page 73 of 315 2RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 5 Oscillati
290. oltage detection circuit The voltage detection circuit monitors the input voltage to the VCC pin The voltage to monitor is Vdet1 When the input voltage to the VCC pin reaches the Vdet level or below the pins CPU and SFR are reset When the input voltage to the VCC pin reaches the Vdet1 level or above the low speed on chip oscillator clock starts counting When the low speed on chip oscillator clock count reaches 32 the internal reset signal is held H and the MCU enters the reset sequence refer to Figure 6 3 The low speed on chip oscillator clock divided by 8 is automatically selected as the CPU after reset Refer to 4 Special Function Registers SFRs for the status of the SFR after voltage monitor 1 reset The internal RAM is not reset When the input voltage to the VCC pin reaches the Vdet1 level or below while writing to the internal RAM is in progress the contents of internal RAM are undefined Refer to 7 Voltage Detection Circuit for details of voltage monitor 1 reset 6 4 Voltage Monitor 2 Reset A reset is applied using the on chip voltage detection 2 circuit The voltage detection 2 circuit monitors the input voltage to the VCC pin The voltage to monitor is Vdet2 When the input voltage to the VCC pin reaches the Vdet2 level or below pins CPU and SFR are reset and the program beginning with the address indicated by the reset vector is executed After reset the low speed on chip oscillator clock divided by 8 is aut
291. omatically selected as the CPU clock The voltage monitor 2 does not reset some SFRs Refer to 4 Special Function Registers SFRs for details The internal RAM is not reset When the input voltage to the VCC pin reaches the Vdet2 level or below while writing to the internal RAM is in progress the contents of internal RAM are undefined Refer to 7 Voltage Detection Circuit for details of voltage monitor 2 reset 6 5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 reset when watchdog timer underflows the MCU resets its pins CPU and SFR if the watchdog timer underflows Then the program beginning with the address indicated by the reset vector is executed After reset the low speed on chip oscillator clock divided by 8 is automatically selected as the CPU clock The watchdog timer reset does not reset some SFRs Refer to 4 Special Function Registers SFRs for details The internal RAM is not reset When the watchdog timer underflows the contents of internal RAM are undefined Refer to 13 Watchdog Timer for details of the watchdog timer 6 6 Software Reset When the PMO3 bit in the PMO register is set to 1 MCU reset the MCU resets its pins CPU and SFR The program beginning with the address indicated by the reset vector is executed After reset the low speed on chip oscillator clock divided by 8 is automatically selected for the CPU clock The software reset does not reset some SFRs Refer to 4 Special Functi
292. ommunication mode Refer to Figure 16 14 Sample Flowchart of Data Transmission Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 193 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface e CPHS bit 0 data change at odd edges and CPOS bit 0 CH when clock stops High impedance SCS output eo 1 frame 1 frame tae trae FT TDRE bit in H SSSR register TEI interrupt request is generated TXI interrupt request is TXI interrupt request is TEND bit in generated generated SSSR register K Processing Data write to SSTDR register by program CPHS bit 1 data change at even edges and CPOS bit 0 H when clock stops High impedance SCS output e E 1 frame 1 frame TDRE bit in SSSR register TEI interrupt request is generated we TXI interrupt request is TXI interrupt request is TEND bit in generated generated SSSR register ___ _ K Processing Data write to SSTDR register by program CPHS CPOS Bits in SSMR register Figure 16 19 Example of Clock Synchronous Serial UO with Chip Select Operation during Data Transmission 4 Wire Bus Communication Mode Rev 1 30 Dec 08 2006 Page 194 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 6 3 Data Reception Figure 16 20 shows an example of clock synchronous serial I O with chip select operation 4 wi
293. on Registers SFRs for details The internal RAM is not reset Rev 1 30 Dec 08 2006 Page 430f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit 7 Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin This circuit can be used to monitor the VCC input voltage by a program Alternately voltage monitor 1 reset voltage monitor 2 interrupt and voltage monitor 2 reset can also be used Table 7 1 lists the Specifications of Voltage Detection Circuit and Figures 7 1 to 7 3 show the Block Diagrams Figures 7 4 to 7 6 show the Associated Registers Table 7 1 Hem Specifications of Voltage Detection Circuit Voltage Detection 1 Voltage Detection 2 VCC monitor Voltage to monitor Vdet1 Vdet2 Detection target Passing through Vdet1 by rising or falling Passing through Vdet2 by rising or falling Monitor None VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Process when voltage is detected Reset Voltage monitor 1 reset Voltage monitor 2 reset Reset at Vdet1 gt VCC restart CPU operation at VCC gt Vdet1 Reset at Vdet2 gt VCC restart CPU operation after a specified time Interrupt None Voltage monitor 2 interrupt Interrupt request at Vdet2 gt VCC and VCC gt Vdet2 when digital filter is enabled interrupt request at Vdet2 gt VCC or VCC
294. on Stop Detection Function The oscillation stop detection function detects the stop of the main clock oscillating circuit The oscillation stop detection function can be enabled and disabled by bits OCD1 to OCDO in the OCD register Table 10 5 lists the Specifications of Oscillation Stop Detection Function When the main clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b oscillation stop detection function enabled the system is placed in the following state if the main clock stops e OCD2 bit in OCD register 1 on chip oscillator clock selected e OCD3 bit in OCD register 1 main clock stops e CM14 bit in CM1 register 0 low speed on chip oscillator oscillates e Oscillation stop detection interrupt request is generated Table 10 5 Specifications of Oscillation Stop Detection Function Item Specification Oscillation stop detection clock and f XIN gt 2 MHz frequency bandwidth Enabled condition for oscillation stop Set bits OCD1 to OCDO to 11b oscillation stop detection detection function function enabled Operation at oscillation stop detection Oscillation stop detection interrupt is generated 10 5 1 How to Use Oscillation Stop Detection Function e The oscillation stop detection interrupt shares a vector with the voltage monitor 2 interrupt and the watchdog timer interrupt When using the oscillation stop detection interrupt and watchdog timer interrupt the interrupt source needs to be deter
295. or R8C 1B Group Rev 1 30 Dec 08 2006 Page 248 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 3 Functions to Prevent Rewriting of Flash Memory Standard serial I O mode has an ID code check function and parallel I O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily 18 3 1 ID Code Check Function This function is used in standard serial I O mode Unless the flash memory is blank the ID codes sent from the programmer and the ID codes written in the flash memory are checked to see if they match If the ID codes do not match the commands sent from the programmer are not acknowledged The ID codes consist of 8 bits of data each the areas of which beginning with the first byte are OOFFDFh OOFFE3h OOFFEBh OOFFEFh OOFFF3h OOFFF7h and OOFFFBh Write programs in which the ID codes are set at these addresses and write them to the flash memory OOFFDFh to OOFFDCh OOFFESh to OOFFEOh OOFFE7h to OOFFE4h OOFFEBh to OOFFE8h OOFFEFh to OOFFECh ID4 Single step vector Oscillation stop detection watch OOFFF3h to OOFFFOh IDS Weed Address i i SC f OOFFF7h to OOFFF4h ID6 Address break OOFFFBh to OOFFF8h ID7 1 Reserved OOFFFFh to OOFFFCh Note 1 Reset vector eege 4 bytes NOTE 1 The OFS register is assigned to OOFFFFh Refer to Figure 13 2 Registers OFS and WDC and Figure 13 3 Registers WDTR and WDTS for OFS
296. or information on how to set peripheral functions Table 5 3 Settings of PDi_j Bit when Functioning as I O Ports for Peripheral Functions UO of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions Input Set this bit to 0 input mode Output This bit can be set to either 0 or 1 output regardless of the port setting 5 3 Pins Other than Programmable UO Ports Figure 5 4 shows the Configuration of I O Pins Rev 1 30 Dec 08 2006 Page 24 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports P1_0to P1_3 Pull up selection Direction register Output from individual peripheral function Data bus Port latch Drive capacity selection Input to individual peripheral function Analog input Pull up selection Direction register Output from individual peripheral function Data bus Port latch O lt Pull up selection Direction register Data bus Port latch Input to individual peripheral function NOTE 1 NM symbolizes a parasitic diode Ensure the input voltage to each port will not exceed VCC Figure 5 1 Configuration of Programmable I O Ports 1 Rev 1 30 Dec 08 2006 Page 25 of 315 2CENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports P1_6 P1_7 Pull up selection Direction a register d Output from individual peripheral function Data bus j Port latch a lt Input to individ
297. or occurs in master receive mode of the clock synchronous serial format the MST bit is set to 0 and the IIC enters slave receive mode 6 Refer to 16 3 8 1 Accessing of Registers Associated with I C bus Interface for more information Figure 16 24 ICCR1 Register Rev 1 30 Dec 08 2006 Page 202 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group IC bus Control Register 2 b7 b6 b5 b4 b3 b2 bi b0 Address 00B9h 16 Clock Synchronous Serial Interface After Reset 01111101b Bi Syro IC control part reset bit ICRST Nothing is assigned If necessary set to 0 When read the content is 1 L itor fl SCLO SCL monitor flag SDA output value control When read bit Start stop condition generation disable bit Bus busy bit NOTES Nothing is assigned If necessary set to 0 b0 When read the content is 1 b2 DAOP SDAO write protect bit When rewrite to SDAO bit w rite 0 simultaneously SDAO When read the content is 1 When hang up occurs due to communication failure during PC bus interface operation w rite 1 to reset the control block of the PC bus interface w ithout setting ports or initializing registers 0 SCL pin is set to L 1 SCL pin is set to H RW O SDA pin output is held L 1 SDA pin output is held H When written 0 SDA pin output is changed to L 1 SDA pin output is changed to high impedance H output via
298. or the on chip oscillator clock can be selected 10 3 2 CPU Clock The CPU clock is an operating clock for the CPU and watchdog timer The system clock can be divided by 1 no division 2 4 8 or 16 to produce the CPU clock Use the CM06 bit in the CMO register and bits CM16 to CM17 in the CM1 register to select the value of the division After reset the low speed on chip oscillator clock divided by 8 provides the CPU clock When entering stop mode from high speed or medium speed mode the CM06 bit is set to 1 divide by 8 mode 10 3 3 Peripheral Function Clock f1 f2 f4 f8 32 The peripheral function clock is the operating clock for the peripheral functions The clock fi i 1 2 4 8 and 32 is generated by the system clock divided by i The clock fi is used for timers X Y Z and C the serial interface and the A D converter When the WAIT instruction is executed after setting the CM02 bit in the CMO register to 1 peripheral function clock stops in wait mode the clock fi stops 10 3 4 RING and fRING128 fRING and fRING128 are operating clocks for the peripheral functions fRING runs at the same frequency as the on chip oscillator clock and can be used as the source for timer X fRING128 is generated from fRING by dividing it by 128 and it can be used as timer C When the WAIT instruction is executed the clocks fRING and fRING128 do not stop 10 3 5 fRING fast fRING fast is used as the count source for timer C fR
299. or w ill be the maximum value or less of the system clock High Speed On Chip Oscillator Control Register 2 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0022h 00h Bit Symbol High speed on chip oscillator mode HRA20 select bits fRING fast mode 0 fRING fast mode 1 fRING fast mode 2 HRA 21 Do not set Reserved bits Set to 0 Nothing is assigned If necessary set to 0 b7 b5 When read the content is 0 NOTES Set the PRCO bit in the PRCR register to 1 write enable before rew riting the HRA2 register High speed on chip oscillator frequency 8 MHz HRA1 register value w hen shipping If fRING fast mode 0 is switched to fRING fast mode 1 the frequency is multiplied by 1 5 If fRING fast mode 0 is switched to fRING fast mode 2 the frequency is multiplied by 0 5 Set the HRA20 and HRA21 bits so that the frequency of the high speed on chip oscillator w ill be the maximum value or less of the system clock Figure 10 6 Registers HRA1 and HRA2 Rev 1 30 Dec 08 2006 Page 64 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit The clocks generated by the clock generation circuits are described below 10 1 Main Clock This clock is supplied by a main clock oscillation circuit This clock is used as the clock source for the CPU and peripheral function clocks The main clock oscillation circuit is configured by connecting a resonator between the XIN and XOUT p
300. ormation included in this document When using or otherwise relying on the information in this document you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application Renesas makes no representations warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products With the exception of products specified by Renesas as suitable for automobile applications Renesas products are not designed manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare in
301. ount value can be read out by reading registers TX and PREX Write to timer When registers TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each reload register of registers TX and PREX at the following count source input the data is transferred to the counter at the second count source input and the count re starts at the third count source input Select functions NOTE e INT1 CNTRO signal polarity switch function The ROEDG bit can select the polarity level when the pulse output starts 1 e Inverted pulse output function The pulse which inverts the polarity of the CNTRO output can be output from the CNTRO pin selected by TXOCNT bit 1 The level of the output pulse becomes the level when the pulse output starts when the TX register is written to Rev 1 30 Dec 08 2006 Page 1130f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 bi bO olofo fof Symbol Address After Reset TXMR 008Bh 00h Bi Sy Operating mode select bits 0 1 0 1 Pulse output mode a Ss m INT1 CNTRO signal 0 CNTRO signal output starts at H GEES polarity sw itch bit 1 CNTRO signal output starts at L vy XS Timer X count start flag 0 Stops counting 1 Starts counting CNTR i S 7 TXOCNT P3_7 0
302. ources assigned to individual software interrupt numbers polarities and timing Therefore if a mode change of a peripheral function involves interrupt sources edge polarities and timing set the IR bit to 0 no interrupt requested after the change Refer to the individual peripheral function for its related interrupts Figure 20 1 shows an Example of Procedure for Changing Interrupt Sources Interrupt source change Disable interrupts 2 Change interrupt source including mode of peripheral function Set the IR bit to 0 interrupt not requested using the MOV instruction Enable interrupts 3 Change completed IR bit The interrupt control register bit of an interrupt whose source is changed NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 Use the flag for the INTi i 0 to 3 interrupts To prevent interrupt requests from being generated when using peripheral function interrupts other than the INTI interrupt disable the peripheral function before changing the interrupt source In this case use the flag if all maskable interrupts can be disabled If all maskable interrupts cannot be disabled use bits ILVLO to ILVL2 of the interrupt whose source is changed 3 Refer to 12 5 6 Changing Interrupt Control Register for the instructions to be used and usage notes Figure 20 1 Example of Procedure for Changing Interrupt Sources Re
303. pare 0 output select output compare mode CMP output is reversed w hen compare 0 signal is matched CMP output is set to L when compare 0 signal is matched CMP output is set to H when compare 0 signal is matched Compare 1 output mode select bits CMP output remains unchanged even when compare 1 is matched CMP output is reversed w hen compare 1 signal is matched CMP output is set to L when compare 1 signal is matched CMP output is set to H when compare 1 signal is matched Compare 0 output mode select bits CMP output remains unchanged even when compare 0 is matched RW NOTES 1 When the same value from the INT3 pin is sampled three times continuously the input is determined 2 When the TCCOO bit in the TCCO register is set to 0 count stops rewrite the TCC13 bit 3 When the TCC13 bit is set to 0 input capture mode set bits TCC12 and TCC14 to TCC17 to 0 Figure 12 16 TCC1 Register Rev 1 30 Dec 08 2006 Page 95 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13 The key input interrupt can be used as a key on wake up function to exit wait or stop mode The KIiEN i 0 to 3 bit in the KIEN register can select whether or not the pins are used as KD input The KIiPL bit in the KIEN register can select the input polarity Whe
304. pare 1 interrupt Provided Provided Provided Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 108 of 315 stENESAS R8C 1A Group R8C 1B Group 14 Timers 14 1 Timer X Timer X is an 8 bit timer with an 8 bit prescaler The prescaler and timer each consist of a reload register and counter The reload register and counter are allocated at the same address and can be accessed when accessing registers PREX and TX refer to Tables 14 2 to 14 6 the Specifications of Each Mode Figure 14 1 shows a Block Diagram of Timer X Figures 14 2 and 14 3 show the registers associated with Timer X Timer X has the following five operating modes e Timer mode The timer counts the internal count source e Pulse output mode The timer counts the internal count source and outputs pulses which inverts the polarity by underflow of the timer e Event counter mode The timer counts external pulses e Pulse width measurement mode The timer measures the pulse width of an external pulse e Pulse period measurement mode The timer measures the pulse period of an external pulse Data Bus TACKY to TC raum to TXMODO U l U 00b or 01b Reload register Reload register n 00b 8 01b O RING o 1b b fo 11b O Counter Counter Timer X interrupt 10b o PREX register TX register CNTRSEL 1 TXS bit INT11 CNTRO1 O o INTT interrupt INTTO CNTROO Oe switching _ TXMOD1 to TXMODO CNTRSEL 0 Gs Otb ROEDG 1
305. pecified time Let output impedance of sensor equivalent circuit be RO internal resistance of microcomputer be R precision error of the A D converter be X and the resolution of A D converter be Y Y is 1024 in the 10 bit mode and 256 in the 8 bit mode 1 VC is generally VC vinji _ C RO R And whent T VC VIN VIN VIN 1 WEN rT e C R0 R X Y 1 Si X n C ROTR Y Hence RO T R Ce ine Y Figure 17 11 shows Analog Input Pin and External Sensor Equivalent Circuit When the difference between VIN and VC becomes 0 1LSB we find impedance RO when voltage between pins VC changes from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f XIN 10 MHz T 0 25 us in the A D conversion mode without sample amp hold Output impedance RO for sufficiently charging capacitor C within time T is determined as follows T 0 25 us R 2 8kO C 6 0 pF X 0 1 and Y 1024 Hence 0 25 x 107 6 0 x 107 e jn Hl 1024 RO 28x10 x 1 7x10 Thus the allowable output impedance of the sensor equivalent circuit making the precision error 0 1LSB or less is approximately 1 7 kQ maximum Sensor equivalent circuit R 2 8 kQ V i C 6 0 pF The 1 The capasity of t
306. peed on chip oscillator stopped When the OCD2 bit is set to 1 on chip oscillator clock selected the CM14 bit is set to 0 low speed on chip oscillator on And remains unchanged even if 1 is written to it RW RW RW RW RW RW RW When using the voltage detection interrupt set the CM14 bit to 0 low speed on chip oscillator on When the CM10 bit is set to 1 stop mode or the CMO5 bit in the CMO register to 1 main clock stops and the CM13 bit is set to 1 XIN XOUT pin the XOUT P4_7 pin becomes H When the CM13 bit is set to 0 input ports P4_6 P4_7 P4_7 XOUT enters input mode In count source protect mode refer to 13 2 Count Source Protect Mode the value remains unchanged even if bits CM10 and CM14 are set Figure 10 3 CM1 Register Rev 1 30 Dec 08 2006 Page 61 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit Oscillation Stop Detection Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 000Ch 04h Oscillation stop detection enable b1 bo 00 Oscillation stop detection function disabled 1 Do not set 10 Do not set 1 Oscillation stop detection function enabled System clock select bit g Selects main clock OCT Selects on chip oscillator clock 2 RW ocD3 oe monitor bit Main clock oscillates Main clock stops Reserved bits Set to 0 b7 b4 ese fev NOTES Set the PRCO bit in the PRCR register to 1 write
307. polarity switch function The ROEDG bit can select the measurement period for the input pulse e Measured pulse input pin select function The CNTRSEL bit in the UCON register can select the CNTROO or CNTRO1 pin 1 Input a pulse with a period longer than twice of the prescaler X period Input a pulse with a longer H and L width than the prescaler X period If a pulse with a shorter period is input to the CNTRO pin the input may be ignored Dec 08 2006 Page 1190f315 stENESAS R8C 1A Group R8C 1B Group 14 Timers Timer X Mode Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset 008Bh 00h 0 0 Timer mode or pulse period measurement mode signal CNTRO polarity sw itch bit 0 Measures measured pulse from one rising edge to next rising edge 1 Measures measured pulse from one falling edge to next falling edge NTT g Rising edge Falling edge e fT X count start flag e Stops counting Starts counting eal to 0 in pulse width measurement mode Beal La Operating mode select bit 2 1 Pulse period measurement mode Active edge judgment flag 0 Active edge not received 2 Timer X underflow flag 0 No underflow 2 NOTES The IR bit in the INT1IC register may be set to 1 requests interrupt when the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources This bit is set to 0 by writing 0 in a program It remains unchanged even if writing 1 Refer to 14 1 6 Notes on
308. priority than IPL the interrupt is enabled 2 8 10 Reserved Bit If necessary set to 0 When read the content is undefined Rev 1 30 Dec 08 2006 Page 17 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 3 Memory 3 Memory 3 1 R8C 1A Group Figure 3 1 is a Memory Map of R8C 1A Group The R8C 1A Group has 1 Mbyte of address space from addresses 00000h to FFFFFh The internal ROM is allocated lower addresses beginning with address OFFFFh For example a 16 Kbyte internal ROM area is allocated addresses 0CO000h to OFFFFh The fixed interrupt vector table is allocated addresses OFFDCh to OFFFFh They store the starting address of each interrupt routine The internal RAM is allocated higher addresses beginning with address 00400h For example a 1 Kbyte internal RAM area is allocated addresses 00400h to 007FFh The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged Special function registers SFRs are allocated addresses 00000h to 002FFh The peripheral function control registers are allocated here All addresses within the SFR which have nothing allocated are reserved for future use and cannot be accessed by users 00000h SFR See 4 Special Function Registers SFRs 002FFh 00400h Internal RAM OXXXXh Undefined instruction Overflow OYYYYh Fa Watchdog timersoscillation stop detection voltage monitor 2 eo Addres
309. pt requested after the change Refer to the individual peripheral function for its related interrupts Figure 12 20 shows an Example of Procedure for Changing Interrupt Sources Interrupt source change Disable interrupts 2 Change interrupt source including mode of peripheral function Set the IR bit to 0 interrupt not requested using the MOV instruction Enable interrupts 3 Change completed IR bit The interrupt control register bit of an interrupt whose source is changed NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 Use the flag for the INTi i 0 to 3 interrupts To prevent interrupt requests from being generated when using peripheral function interrupts other than the INTi interrupt disable the peripheral function before changing the interrupt source In this case use the flag if all maskable interrupts can be disabled If all maskable interrupts cannot be disabled use bits ILVLO to ILVL2 of the interrupt whose source is changed 3 Refer to 12 5 6 Changing Interrupt Control Register for the instructions to be used and usage notes Figure 12 20 Example of Procedure for Changing Interrupt Sources Rev 1 30 Dec 08 2006 Page 101 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 5 6 Changing Interrupt Control Register Contents a The contents of an interrupt control register can o
310. pulse TCIN pin input Indeterminate Indeterminate e Measured Measured TMO register Measured value 2 Set to 0 when interrupt request is acknowledged or set by program a d x IR bit in INT3IC register Set to 0 when interrupt request J is acknowledged or set by IR bit in TCIC program register The above applies under the following conditions TCCO register TCC04 to TCC03 bits 01b capture input polarity is set for falling edge TCC07 0 INT3 TCIN input as capture input trigger Figure 14 30 Operating Example in Input Capture Mode Rev 1 30 Dec 08 2006 Page 148 of 315 pRENESAS REJ09B0252 0130 Rev 1 30 REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 3 2 Output Compare Mode In output compare mode an interrupt request is generated when the value of the TC register matches the value of the TMO or TM1 register Table 14 12 shows the Output Compare Mode Specifications Figure 14 31 shows an Operating Example in Output Compare Mode Table 14 12 Output Compare Mode Specifications Hem Specification Count sources f1 f8 32 fFRING fast Count operations e Increment e The value in the TC register is set to 0000h when the count stops Count start condition The TCCOO bit in the TCCO register is set to 1 count starts Count stop condition The TCCOO0 bit in the TCCO register is set to 0 count stops Waveform output start condition Bits TCOUT
311. queue buffer Example 1 Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCHI1 FCLR I Disable interrupts AND PB 00H 0056H Set TXIC register to 00h NOP i NOP FSET I Enable interrupts Example 2 Use dummy read to delay FSET instruction INT_SWITCH2 FCLR I Disable interrupts AND PB 00H 0056H Set TXIC register to 00h MOV W MEM RO Dummy read FSET I Enable interrupts Example 3 Use POPC instruction to change I flag INT_SWITCH3 PUSHC FLG FCLR I Disable interrupts AND PB 00H 0056H Set TXIC register to 00h POPC FLG Enable interrupts Rev 1 30 Dec 08 2006 Page 299 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 3 Precautions on Timers 20 3 1 Notes on Timer X e Timer X stops counting after a reset Set the values in the timer and prescaler before the count starts e Even if the prescaler and timer are read out in 16 bit units these registers are read 1 byte at a time by the MCU Consequently the timer value may be updated during the period when these two registers are being read e Do not rewrite bits TXMODO to TXMOD1 and bits TXMOD2 and TXS simultaneously e In pulse period measurement mode bits TXEDG and TXUND in the TXMR register can be set to 0 by writing 0 to these bits by a program However these bits remain unchanged if 1 is written When using the READ MODIFY WRITE instruction for the TXMR r
312. r Transfer from UOTB register to UARTO transmit register 1 fEXT eg Tal LULL Receive data is taken in RXDO o0 o J c2V os bY os oa D7 vol 1 Tele va os Transfer from UARTO receive register to RI bit in UOC1 UORB register oh register IR bit in SORIC register val Set to 0 when interrupt request is acknowledged or set by a program Read out from UORB register 0 E The above applies under the following settings CKDIR bit in UOMR register 1 external clock CKPOL bit in UOCO register 0 output transmit data at the falling edge and input receive data at the rising edge of the transfer clock The following conditions are met when H is applied to the CLKO pin before receiving data TE bit in UOC1 register 1 enables transmit RE bit in UOC1 register 1 enables receive Write dummy data to the UOTB register fEXT Frequency of external clock Figure 15 7 Transmit and Receive Timing Example in Clock Synchronous Serial UO Mode Rev 1 30 Dec 08 2006 Page 160 0f 315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface 15 1 1 Polarity Select Function Figure 15 8 shows the Transfer Clock Polarity Use the CKPOL bit in the UOCO register to select the transfer clock polarity e When the CKPOL bit in the UOCO register 0 output transmit data at the falling edge and input the receive data at the rising edge of the transfer
313. r CPHS bit lt lt 0 CPOS bit lt 0 Set MLS bit SSCRH register Set MSS bit SSMR2 register SCKS bit lt 1 Set SOOS bit SSCRH register Set bits CKSO to CKS2 Set RSSTP bit SSSR register ORER bit 0 SSER register RE bit lt 1 receive TE bit lt 1 transmit Set bits RIE TEIE and TIE NOTE 1 Write 0 after reading 1 to set the ORER bit to 0 Figure 16 12 Initialization in Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 184 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 5 2 Data Transmission Figure 16 13 shows an Example of Clock Synchronous Serial I O with Chip Select Operation for Data Transmission Clock Synchronous Communication Mode During data transmission clock synchronous serial T O with chip select operates as described below When clock synchronous serial I O with chip select is set as a master device it outputs a synchronous clock and data When clock synchronous serial I O with chip select is set as a slave device it outputs data synchronized with the input clock When the TE bit is set to 1 transmit enabled before writing the transmit data to the SSTDR register the TDRE bit is automatically set to 0 data not transferred from registers SSTDR to SSTRSR and the data is transferred from registers SSTDR to SSTRSR After the TDRE bit is set to data transferred from registers SSTDR to SSTRSR
314. r PRDP0020BA A Package Top View Rev 1 30 Dec 08 2006 Page 10 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview PIN Assignment top view ak P1_2 AN10 KI2 CMP0_2 3 AN11 KI3 TZOUT a P4_2 VREF NC NC NC lt gt Di ba CH N be valhelfzlinellnsl P1_1 AN9 KIT CMPO_1 lt 22 14 P1_4 TXDO P1_0 AN8 KIO CMP0_0 lt gt 13 lt P1_5 RXDO CNTRO1 NTT1 P3_3 TCIN INT3 SSIO0 CMP1_0 lt gt 24 er P1_6 CLKO SSI01 R8C 1A Group P3_4 SCS SDA CMP1_1 gt 25 R8C 1B Group 11 a P1_7 CNTRO0 INTTO P3_5 SSCK SCL CMP1_2 lt gt 26 10 lt P4_5 INTO RXD1 P3_7 CNTRO SSO TXD1 lt 27 Q 8 lt VCC AVCC el al VSS AVSS gt XIN P4_6 gt XOUT P4_7 lt gt NOTES 1 P4_7 is a port for the input Package PWQNO0028KA B 28PJW B Figure 1 6 Pin Assignments for PWQNO0028KA B Package Top View Rev 1 30 Dec 08 2006 Page 11 of 315 7RENESAS REJ09B0252 0130 1 6 R8C 1A Group R8C 1B Group Pin Functions 1 Overview Table 1 5 lists Pin Functions Table 1 6 lists Pin Name Information by Pin Number of PLSPO020JB A PRDPOO20BA A Packages and Table 1 7 lists Pin Name Information by Pin Number of PWQNO0028KA B Package Table 1 5 Type Pin Functions Symbol UO Type Description Power Supply Input VCC VSS Apply 2 7 V to 5 5 V to the VCC pin Apply 0 V to the VSS pin Analog Power Supply Input AVCC AVSS Po
315. r X for precautions regarding the TXS bit Figure 14 7 TXMR Register in Pulse Width Measurement Mode Rev 1 30 Dec 08 2006 Page 1170f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers n high level the contents of TX register low level the contents of PREX register FFFFh Count start Underflow Count stop Counter contents hex Set to 1 by program i TXS bit in TXMR register Measured pulse CNTROi pin input Set to 0 when interrupt request is acknowledged or set by program IR bit in INT1IC register Set to 0 when interrupt request is acknowledged or set by program IR bit in TXIC register Conditions H level width of measured pulse is measured ROEDG 1 i Oto1 Figure 14 8 Operating Example in Pulse Width Measurement Mode Rev 1 30 Dec 08 2006 Page 1180f315 pLeENESAS REJ09B0252 0130 Rev 1 30 REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 1 5 Pulse Period Measurement Mode In pulse period measurement mode the pulse period of an external signal input to the INT1 CNTRO pin is measured refer to Table 14 6 Pulse Period Measurement Mode Specifications Figure 14 9 shows the TXMR Register in Pulse Period Measurement Mode Figure 14 10 shows an Operating Example in Pulse Period Measurement Mode Table 14 6 Hem Pulse Period Measurement Mode Specifications Specification Count sources f1 f2 f8 fRING Count opera
316. r in master transmit receive mode This flag indicates an overrun error when the clock synchronous format is used In the follow ing case this flag is set to 1 e When the last bit of the next data item is received w hile the RDRF bit is set to 1 STOP Stop condition detection When the stop condition is detected after the frame flag is transferred this flag is set to 1 RW NACKF No acknow ledge detection When no ACKnow ledge is detected from receive RW flag device after transmission this flag is set to 1 RDRF Receive data register When receive data is transferred from registers RW Tu ICDRS to ICDRR this flag is set to 1 Transmit end When the 9th clock cycle of the SCL signal in the PC bus format occurs while the TDRE bit is set to 1 this flag is set to 1 This flag is set to 1 when the final bit of the transmit frame is transmitted in the clock synchronous format Transmit data empty In the follow ing cases this flag is set to 1 e Data is transferred from registers ICDRT to ICDRS and the ICDRT register is empty e When setting the TRS bit in the ICCR1 register to 1 transmit mode e When generating the start condition including retransmit e When changing from slave receive mode to slave transmit mode NOTES Each bit is set to 0 by reading 1 before writing 0 This flag is enabled in slave receive mode of the IC bus format When two or more master devices attempt to occupy the bus at nearly the sam
317. r to 1 stop mode An instruction queue pre reads 4 bytes from the instruction which sets the CM10 bit to 1 stop mode and the program stops Insert at least 4 NOP instructions following the JMP B instruction after the instruction which sets the CM10 bit to 1 e Program example to enter stop mode BCLR 1 FMRO CPU rewrite mode disabled BSET 0 PRCR Protect disabled FSET I Enable interrupt BSET 0 CM1 Stop mode JMP B LABEL_001 LABEL_001 NOP NOP NOP NOP 10 6 2 Wait Mode When entering wait mode set the FMRO1 bit in the FMRO register to O CPU rewrite mode disabled and execute the WAIT instruction An instruction queue pre reads 4 bytes from the WAIT instruction and the program stops Insert at least 4 NOP instructions after the WAIT instruction e Program example to execute the WAIT instruction BCLR 1 FMRO CPU rewrite mode disabled FSET I Enable interrupt WAIT Wait mode NOP NOP NOP NOP 10 6 3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the main clock frequency is below 2 MHz set bits OCD1 to OCD0 to 00b oscillation stop detection function disabled in this case 10 6 4 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system 10 6 5 High Speed On Chip Oscillator Clock The high speed on chip oscillator frequency may be changed up to 10 in flash memory CPU rewrite mode duri
318. ransfer data is 8 bits long Set to 110b when transfer data is 9 bits long CKDIR Select the internal clock or external clock 2 STPS Select the stop bit PRY PRYE Select whether parity is included and whether odd or even UiCO CLKO CLK1 Select the count source for the UIBRG register TXEPT Transmit register empty flag NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selected when transfer data is 8 bits long Set to 0 when transfer data is 7 or 9 bits long UC TE Set to 1 to enable transmit TI Transmit buffer empty flag RE Set to 1 to enable receive RI Receive complete flag UCON UOIRS U1IRS Select the source of UARTO transmit interrupt UORRM Set to 0 CNTRSEL Set to 1 to select P1_5 RXDO CNTRO1 INT11 NOTES 1 The bits used for transmit receive data are as follows Bits 0 to 6 when transfer data is 7 bits long bits 0 to 7 when transfer data is 8 bits long bits 0 to 8 when transfer data is 9 bits long 2 An external clock can be selected in UARTO only Table 15 6 lists the I O Pin Functions in Clock Asynchronous Serial I O Mode The TXDi pin outputs H level between the operating mode selection of UARTi i 0 or 1 and transfer start If the NCH bit is set to 1 N channel open drain output this pin is in a high impedance state Table 15 6 UO Pin Functions in Clock Asynchronous Serial I O Mode Pin name Function Selection Method TXDO P1_4 Output serial data Cannot be used as a
319. rate an interrupt betw een setting the bit to 0 and setting it to 1 Set this bit by a program located in a space other than the flash memory This bit is set to 0 by executing the clear status command This bit is enabled when the FMR01 bit is set to 1 CPU rew rite mode When the FMRO01 bit is set to 0 writing 1 to the FMSTP bit causes the FMSTP bit to be set to 1 The flash memory does not enter low pow er consumption state nor is it reset When setting the FMRO1 bit to 0 CPU rewrite mode disabled the FMRO02 bit is set to 0 disables rewrite Figure 18 5 FMRO Register Rev 1 30 Dec 08 2006 Page 255 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset 01B5h 1000000Xb SE Reserved bit When read the content is undefined b0 EW1 mode select bit 2 0 EWO mode zer TT Vo Ei Reserved bits Set to 0 b4 b2 Block 0 rew rite disable bit 3 0 Enables rew rite Block 1 rew rite disable bit 3 0 Enables rew rite Reserved bit Set to 1 R b7 NOTES To set this bit to 1 set it to 1 immediately after setting it first to 0 w hile the FMRO1 bit is set to 1 CPU rew rite mode enable Do not generate an interrupt betw een setting the bit to 0 and setting it to 1 This bit is set to 0 by setting the FMRO01 bit to O CPU rewrite mode disabled When the FMR01 bit is set to 1 CPU rewr
320. re and is packaged in a 20 pin molded plastic LSSOP SDIP or a 28 pin plastic molded HWQEN It implements sophisticated instructions for a high level of instruction efficiency With 1 Mbyte of address space they are capable of executing instructions at high speed Furthermore the R8C 1B Group has on chip data flash ROM 1 KB x 2 blocks The difference between the R8C 1A Group and R8C 1B Group is only the presence or absence of data flash ROM Their peripheral functions are the same 1 1 Applications Electric household appliances office equipment housing equipment Sensors security systems portable equipment general industrial equipment audio equipment etc Rev 1 30 Dec 08 2006 Page1of315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 1 Overview 1 2 Performance Overview Table 1 1 outlines the Functions and Specifications for R8C 1A Group and Table 1 2 outlines the Functions and Specifications for R8C 1B Group Table 1 1 Functions and Specifications for R8C 1A Group Item Specification Number of fundamental 89 instructions instructions Minimum instruction execution 50 ns f XIN 20 MHz VCC 3 0 to 5 5 V time 100 ns f XIN 10 MHz VCC 2 7 to 5 5 V Operating mode Single chip Address space 1 Mbyte Memory capacity See Table 1 3 Product Information for R8C 1A Group Peripheral Ports I O ports 13 pins including LED drive port Functions Input port 3 pins LED drive ports I O ports 4 pins Timers Timer X 8
321. re bus communication mode for data reception During data reception clock synchronous serial I O with chip select operates as described below When the MCU is set as the master device it outputs a synchronous clock and inputs data When the MCU is set as a slave device it outputs data synchronized with the input clock while the SCS pin receives L input When the MCU is set as the master device it outputs a receive clock and starts receiving by performing a dummy read of the SSRDR register After 8 bits of data are received the RDRF bit in the SSSR register is set to 1 data in the SSRDR register and the receive data is stored in the SSRDR register When the RIE bit in the SSER register is set to 1 RXI and OEI interrupt request enabled an RXI interrupt request is generated When the SSRDR register is read the RDRF bit is automatically set to 0 no data in the SSRDR register Read the receive data after setting the RSSTP bit in the SSCRH register to 1 after receiving 1 byte data the receive operation is completed Clock synchronous serial I O with chip select outputs a clock for receiving 8 bits of data and stops After that set the RE bit in the SSER register to 0 receive disabled and the RSSTP bit to 0 receive operation is continued after receiving 1 byte data and read the receive data When the SSRDR register is read while the RE bit is set to 1 receive enabled a receive clock is output again When the 8th clock rises while th
322. register details Figure 18 3 Address for Stored ID Code Rev 1 30 Dec 08 2006 Page 249 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 3 2 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on chip flash memory by the OFS register in parallel I O mode Figure 18 4 shows the OFS Register The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit It disables reading or changing the contents of the on chip flash memory Once ROM code protect is enabled the content in the internal flash memory cannot be rewritten in parallel I O mode To disable ROM code protect erase the block including the OFS register with CPU rewrite mode or standard serial I O mode Option Function Select Register b7 b6 b5 b4 b3 b2 bi b Address Before Shipment OFFFFh FFh W ROM code protect bit 0 ROM code protect enabled ROMCP1 e 1 ROM code protect disabled Reserved bits Set to 1 b6 b4 Count source protect 0 Count source protect mode enabled after reset CSPROINI mode after reset select 1 Count source protect mode disabled after reset R bit NOTES 1 The OFS register is on the flash memory Write to the OFS register w ith a program 2 If the block including the OFS register is erased FFh is set to the OFS register Figure 18 4 OFS Register Rev 1 30 Dec 08 2006 Page 250 of 315 spRENES
323. register the received data can be read and the RDRF bit is set to 0 simultaneously 4 Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1 If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit is set to 1 the SCL signal is fixed L until the ICDRR register is read 5 Ifthe next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 disables the next receive operation before reading the ICDRR register stop condition generation is enabled after the next receive operation 6 When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock generate the stop condition 7 When the STOP bit in the ICSR register is set to 1 read the ICDRR register and set the RCVD bit to 0 maintain the following receive operation 8 Return to slave receive mode Rev 1 30 Dec 08 2006 Page 2140f315 peeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Master transmit mode lt 1 Master receive mode master output 9 1 2 3 4 5 AAA h SDA 7 slave outpu TDRE bit in ICSR register TEND bit in ICSR register TRS bit in ICCR1 register RDPF bit in ICSR register ICDRS register ICDRR register Processing 1 Set TEND and TRS bits to 0 before 2 Read ICDRR register 3 Read ICDRR register by program s
324. register and the RI bit in the UOC1 register are set to 0 To check receive errors read the UiRB register and then use the read data Example when reading receive buffer register MOV W OOA6H RO Read the UORB register e When writing data to the UOTB register in the clock asynchronous serial I O mode with 9 bit transfer data length write data to the high order byte first then the low order byte in 8 bit units Example when reading transmit buffer register MOV B XXH 00A3H Write the high order byte of UOTB register MOV B XXH 00A2H Write the low order byte of UOTB register Rev 1 30 Dec 08 2006 Page 302 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 5 Precautions on Clock Synchronous Serial Interface 20 5 1 Notes on Clock Synchronous Serial I O with Chip Select Set the ITCSEL bit in the PMR register to 0 select clock synchronous serial I O with chip select function to use the clock synchronous serial I O with chip select function 20 5 1 1 Accessing Registers Associated with Clock Synchronous Serial UO with Chip Select After waiting three instructions or more after writing to the registers associated with clock synchronous serial I O with chip select QOB8h to OOBFh or four cycles or more after writing to them read the registers e An example of waiting three instructions or more Program example MOV B 00h 00BBh Set the SSER register to 00h NOP NOP NOP MOV B OOBBh ROL e
325. release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different type numbers implement a system evaluation test for each of the products How to Use This Manual 1 Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU It is intended for users designing application systems incorporating the MCU A basic knowledge of electric circuits logical circuits and MCUs is necessary in order to use this manual The manual comprises an overview of the product
326. rial I O used to connect with a serial programmer e Standard serial I O mode 2 Clock asynchronous serial I O used to connect with a serial programmer e Standard serial I O mode 3 Special clock asynchronous serial I O used to connect with a serial programmer This MCU uses standard serial I O mode 2 and standard serial I O mode 3 Refer to Appendix 2 Connection Examples between Serial Writer and On Chip Debugging Emulator Contact the manufacturer of your serial programmer for additional information Refer to the user s manual of your serial programmer for details on how to use it Table 18 7 lists the Pin Functions Flash Memory Standard Serial I O Mode 2 Table 18 8 lists the Pin Functions Flash Memory Standard Serial I O Mode 3 Figure 18 17 shows Pin Connections for Standard Serial I O Mode 3 After processing the pins shown in Table 18 8 and rewriting the flash memory using a programmer apply H to the MODE pin and reset the hardware to run a program in the flash memory in single chip mode 18 5 1 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match refer to 18 3 Functions to Prevent Rewriting of Flash Memory Table 18 7 Pin Functions Flash Memory Standard Serial UO Mode 2 Pin Name Description VCC VSS Power input Apply the voltage guaranteed for programming and erasure to the VCC pin and 0
327. roduction may cause some changes in device characteristics Figure 17 8 Internal Equivalent Circuit of Analog Input Block Rev 1 30 Dec 08 2006 Page 241 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter 17 6 Inflow Current Bypass Circuit Figure 17 9 shows the Configuration of Inflow Current Bypass Circuit and Figure 17 10 shows an Example of Inflow Current Bypass Circuit where VCC or More is Applied Fixed to GND level Unselected channel ON To the internal logic yy of the A D Converter External input Selected latched into channel OFF Figure 17 9 Configuration of Inflow Current Bypass Circuit VCC or more Leakage current generated Unselected OFF Leaka ge current channel l generated Unaffected Ki T Gg by leakage y To the internal logic LS of the A D Converter Selected channel C Nw Sensor input Figure 17 10 Example of Inflow Current Bypass Circuit where VCC or More is Applied Rev 1 30 Dec 08 2006 Page 242 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter 17 7 Output Impedance of Sensor under A D Conversion To carry out A D conversion properly charging the internal capacitor C shown in Figure 17 11 has to be completed within a specified period of time T sampling time as the s
328. roup 15 Serial Interface 15 2 Clock Asynchronous Serial I O UART Mode The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format Table 15 4 lists the UART Mode Specifications Table 15 5 lists the Registers Used and Settings for UART Mode Table 15 4 UART Mode Specifications Hem Specification Transfer data format e Character bit transfer data Selectable among 7 8 or 9 bits e Start bit 1 bit e Parity bit Selectable among odd even or none e Stop bit Selectable among 1 or 2 bits Transfer clocks e CKDIR bit in UIMR register is set to 0 internal clock fj 16 n 1 fj f1 f8 f32 n value set in UIBRG register 00h to FFh e CKDIR bit is set to 1 external clock fEXT 16 n 1 TEST input from CLKi pin n setting value in UIBRG register 00h to FEN Transmit start conditions e Before transmission starts the following are required TE bit in UiC1 register is set to 1 transmission enabled TI bit in UiC1 register is set to O data in UiTB register Receive start conditions e Before reception starts the following are required RE bit in UiC1 register is set to 1 reception enabled Start bit detected Interrupt request generation timing e When transmitting one of the following conditions can be selected UIIRS bit is set to 0 transmit buffer empty When transferring data from the UiTB register to UARTi transmit regi
329. rs SSTRSR and SSRDR NOTES 1 The SSRDR register retains the data received before an overrun error occurs OPER bit in the SSSR register set to 1 overrun error When an overrun error occurs the receive data may contain errors and therefore should be discarded 2 Refer to 16 2 8 1 Accessing Registers Associated with Clock Synchronous Serial I O with Chip Select for more information Figure 16 8 Registers SSTDR and SSRDR Port Mode Register Address After Reset OOF8h 00h Bit Symbol Reserved bits Set to 0 b2 b0 SSI signal pin select bit 0 P3_3 pin is used for SSI00 pin SSISEL e P1_6 pin is used for SSI01 pin RW RW Reserved bits Set to 0 SSU PC bus switch bit 0 Selects SSU function ICSEL 1 Selects PC bus function Figure 16 9 PMR Register Rev 1 30 Dec 08 2006 Page 178 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 2 1 Transfer Clock The transfer clock can be selected among seven internal clocks f1 256 f1 128 f1 64 f1 32 f1 16 f1 8 and f1 4 and an external clock When using clock synchronous serial I O with chip select set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin When the MSS bit in the SSCRH register is set to 1 operates as master device an internal clock can be selected and the SSCK pin functions as output When transfer is started the SSCK pin outputs clocks of the
330. rs are read 1 byte at a time by the MCU Consequently the timer value may be updated during the period when these two registers are being read e Do not rewrite bits TZMODO to TZMOD1 and the TZS bit simultaneously e In programmable one shot generation mode and programmable wait one shot generation mode when setting the TZS bit in the TZMR register to 0 stops counting or setting the TZOS bit in the TZOC register to 0 stops one shot the timer reloads the value of the reload register and stops Therefore in programmable one shot generation mode and programmable wait one shot generation mode read the timer count value before the timer stops e The TZS bit in the TZMR register has a function to instruct timer Z to start or stop counting and a function to indicate that the count has started or stopped 0 count stops can be read until the following count source is applied after 1 count starts is written to the TZS bit while the count is being stopped If the following count source is applied 1 can be read from the TZS bit After writing 1 to the TZS bit do not access registers associated with timer Z registers TZMR PREZ TZSC TZPR TZOC PUM TCSC and TZIC except for the TZS bit until 1 can be read from the TZS bit The count starts at the following count source after the TZS bit is set to 1 Also after writing 0 count stops to the TZS bit during the count timer Z stops counting at the following count source 1 count starts can be
331. ructures Operating mode Clock synchronous communication mode e 4 wire bus communication mode including bidirectional communication Master slave device Selectable I O pins SSCK I O Clock I O pin SSI I O Data I O pin SSO I O Data I O pin SCS I O Chip select I O pin Transfer clock e When the MSS bit in the SSCRH register is set to 0 operates as slave device external clock is selected input from SSCK pin e When the MSS bit in the SSCRH register is set to 1 operates as master device internal clock selectable among f1 256 f1 128 f1 64 f1 32 f1 16 f1 8 and f1 4 output from SSCK pin is selected e Clock polarity and phase of SSCK can be selected Receive error detection e Overrun error Overrun error occurs during reception and completes in error While the RDRF bit in the SSSR register is set to 1 data in the SSRDR register and when the next serial data receive is completed the ORER bit is set to 1 Multimaster error detection e Conflict error When the SSUMS bit in the SSMR2 register is set to 1 4 wire bus communication mode and the MSS bit in the SSCRH register is set to 1 operates as master device and when starting a serial communication the CE bit in the SSSR register is set to 1 if L applies to the SCS pin input When the SSUMS bit in the SSMR2 register is set to 1 4 wire bus communication mode the MSS bit in the SSCRH register is set to 0 operates a
332. rupt return by one of the following means e Change the content of the stack and use the REIT instruction e Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged Then use a jump instruction Table 12 6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged Figure 12 19 shows Registers AIER and RMADO to RMAD1 Table 12 6 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged Address Indicated by RMADi Register i 0 1 PC Value Saved e Instruction with 2 byte operation code Address indicated by Instruction shown below among instruction with 1 byte operation code RMADi register 2 ADD B S IMM8 dest SUB B S IMM8 dest AND DS IMM8 dest OR B S IMM8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMM8 dest PUSHM src POPM dest JMPS IMM8 JSRS IMM8 MOV B S IMM dest however dest AO or A1 e Instructions other than the above Address indicated by RMADi register 1 NOTES 1 Refer to the 12 1 6 7 Saving a Register for the PC value saved 2 Operation code Refer for the R8C Tiny Series Software Manual REJ09B0001 Chapter 4 Instruction Code Number of Cycles contains diagrams showing operation code below each syntax Operation code is shown in the bold frame in the diagrams Table 12 7 Correspondence Between Address Match Interrupt Sources and Associ
333. rupt is used to exit stop mode and to return again write 0 to the VW2C1 bit before writing 1 This bit is enabled when the VCA27 bit in the VCA2 register is set to 1 voltage detection 2 circuit enabled Set this bit to 0 by a program When 0 is written by a program it is set to 0 and remains unchanged even if 1 is written to it This bit is enabled w hen the VW2CO0 bit is set to 1 voltage monitor 2 interrupt reset enabled The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 voltage detection 2 circuit enabled Set the VW2C0 bit to 0 disable w hen the VCA27 bit is set to 0 voltage detection 2 circuit disabled The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 digital filter disabled mode Bits VW2C2 and VW2C3 remain unchanged after a softw are reset w atchdog timer reset or voltage monitor 2 reset When the VW2CE6 bit is set to 1 voltage monitor 2 reset mode set the VW2C7 bit to 1 when VCC reaches Vdet2 or below Do not set to 0 Set the VW2CO bit to 0 disabled w hen the VCA13 bit in the VCA1 register is set to 1 VCC gt Vdet2 or voltage detection 2 circuit disabled the VW2C1 bit is set to 1 digital filter disabled mode and the VW2C7 bit is set to 0 when VCC reaches Vdet2 or above Set the VW2CO0 bit to 0 disabled w hen the VCA13 bit is set to 0 VCC lt Vdet2 the VW2C1 bit is set to 1 digital filter disabled mode and the VW2C7 bit is set to 1 wh
334. s 1 FRING S x 20 3 Apply H to the RESET pin 6 1 2 Power On 1 Apply L to the RESET pin 2 Let the supply voltage increase until it meets the recommended operating condition 3 Wait for td P R or more to allow the internal power supply to stabilize refer to 19 Electrical Characteristics 4 Wait for 500 us 1 FRING S x 20 5 Apply H to the RESET pin Rev 1 30 Dec 08 2006 Page 400f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 6 Resets 0 2 VCC or below GA steep H td P R 500 us or more NOTE 1 Refer to 19 Electrical Characteristics Figure 6 4 Example of Hardware Reset Circuit and Operation 5V Supply voltage detection circuit vec OV 5V H Ki Fa td P R 500 us or more Example when voc 5V NOTE 1 Refer to 19 Electrical Characteristics Figure 6 5 Example of Hardware Reset Circuit Usage Example of External Supply Voltage Detection Circuit and Operation Rev 1 30 Dec 08 2006 Page 41 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 6 Resets 6 2 Power On Reset Function When the RESET pin is connected to the VCC pin via a pull up resistor of about 5 kQ and the VCC pin voltage level rises the power on reset function is enabled and the MCU resets its pins CPU and SFR When a capacitor is connected to the RESET pin always keep the voltage to the RESET pin 0 8VCC or more When the input voltage to t
335. s break Internal ROM Reserved OFFDCh OFFFFh Expanded area FFFFFh NOTE 1 The blank regions are reserved Do not access locations in these regions Internal ROM Internal RAM Address Address OYYYYh OXXXXh Part Number R5F211A4SP R5F211A4DSP R5F211A4DD R5F211A4NP R5F211A4XXXSP R5F211A4DXXXSP R5F211A4XXXDD 16 Kbytes 0Co000h 1 Kbyte 007FFh R5F211A4XXXNP R5F211A3SP R5F211A3DSP R5F211A3DD R5F211A3NP R5F211A3XXXSP R5F211A3DXXXSP R5F211A3XXXDD 12 Kbytes 0D000h 768 bytes OO6FFh R5F211A3XXXNP R5F211A2SP R5F211A2DSP R5F211A2DD R5F211A2NP R5F211A2XXXSP R5F211A2DXXXSP R5F211A2XXXDD 8 Kbytes OE000h 512 bytes OOSFFh R5F211A2XXXNP R5F211A1SP R5F211A1DSP R5F211A1DD re on rae Se R5F211A1XXXSP R5F211A1DXXXSP R5F211A1XXXDD y y Figure 3 1 Memory Map of R8C 1A Group Rev 1 30 Dec 08 2006 Page 18 of 315 v EN SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 3 Memory 3 2 R8C 1B Group Figure 3 2 is a Memory Map of R8C 1B Group The R8C 1B Group has 1 Mbyte of address space from addresses 00000h to FFFFFh The internal ROM program ROM is allocated lower addresses beginning with address OFFFFh For example a 16 Kbyte internal ROM area is allocated addresses 0CO00h to OFFFFh The fixed interrupt vector table is allocated addresses OFFDCh to OFFFFN They store the starting address of each interrupt routine The internal ROM data flash is allocated addresses 0240
336. s of Hardware Interrupts The interrupt priority does not affect software interrupts The MCU jumps to the interrupt routine when the instruction is executed Address break Watchdog timer Oscillation stop detection Voltage monitor 2 Peripheral function Single step Address match Figure 12 9 Priority Levels of Hardware Interrupts Rev 1 30 Dec 08 2006 Page 89 of 315 7tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 12 Interrupts 12 1 6 10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt as shown in Figure 12 10 Figure 12 10 Rev 1 30 Dec 08 2006 Page 90 of 315 2tENESAS REJ09B0252 0130 Priority level of each interrupt Level 0 default value Compare 0 INTs Timer Z Timer X INT Timer C INTT UART1 receive UARTO receive Compare 1 A D conversion UART1 transmit UARTO transmit SSU IC bus Key input Address match Watchdog timer Oscillation stop detection Voltage monitor 2 TE 1 The IICSEL bit in the PMR register switches functions nterrupt Priority Level Judgement Circuit Highest Priority of peripheral function interrupts if priority levels are same Interrupt request level judgment output signal Interrupt request acknowledged R8C 1A Group R8C 1B Group 12 Interrupts 12 2 INT Interrupt 12 2 1 INTO Interrupt The
337. s set to 0 digital filter enabled Voltage monitor 2 interrupt VCC Vdet2 j ane ft tt VW2C2 bit in 1 VW2C register 0 Voltage monitor 2 interrupt request 0 Set to 0 by an interrupt request acknowledgment Operation when the VW2C1 bit in the VW2C register is set to 0 digital filter enabled and the VW2C6 bit is set to 0 voltage monitor 2 interrupt mode Figure 7 7 Operating Example of Digital Filter Rev 1 30 Dec 08 2006 Page 51 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit 7 2 Voltage Monitor 1 Reset Table 7 2 lists the Setting Procedure of Voltage Monitor 1 Reset Associated Bits and Figure 7 8 shows an Operating Example of Voltage Monitor 1 Reset To use voltage monitor 1 reset to exit stop mode set the VW1C1 bit in the VWIC register to 1 digital filter disabled Table 7 2 Setting Procedure of Voltage Monitor 1 Reset Associated Bits When Using Digital Filter When Not Using Digital Filter Set the VCA26 bit in the VCA2 register to 1 voltage detection 1 circuit enabled Wait for td E A Select the sampling clock of the digital filter Set the VW1C7 bit in the VW1C register to by bits VW1F0 to VW1F1 in the VW1C 1 register Set the VW1C1 bit in the VW1C register to Set the VW1C1 bit in the VW1C register to 0 digital filter enabled 1 digital filter disabled Set the VW1C6 bit in the VW1C register to 1 voltage monitor 1 reset mode Set the VW1C2 b
338. s slave device and the SCS pin input changes state from L to H the CE bit in the SSSR register is set to 1 Interrupt requests 5 interrupt requests transmit end transmit data empty receive data full overrun error and conflict error 1 Select functions NOTE e Data transfer direction Selects MSB first or LSB first e SSCK clock polarity Selects L or H level when clock stops SSCK clock phase Selects edge of data change and data download 1 Clock synchronous serial I O with chip select has only one interrupt vector table Rev 1 30 Dec 08 2006 Page 1700f315 peeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Internal clock f1 i Internal clock generation Multiplexer circuit ee SE I Data bus fy soc SSTRSR register Selector SSRDR register Interrupt requests TXI TEI RXI OEI and CEI i 4 8 16 32 64 128 or 256 Figure 16 1 Block Diagram of Clock Synchronous Serial I O with Chip Select Rev 1 30 Dec 08 2006 Page 171 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface SS Control Register H b7 b6 b5 b4 b3 b2 bi b Address After Reset OOB8h 00h Transfer clock rate select bits 1 256 1 128 f1 64 f1 32 f1 16 f1 8 21 4 Do not set Nothing is assigned If necessary set to 0 b4 b3 When read the content is 0
339. sabled NACK detection NAKIE 1 and AL 1 or Enabled Disabled Arbitration lost overrun error NAKIE 1 and NACKF 1 Enabled Enabled STIE NAKIE RIE TEIE TIE Bits in ICIER register AL STOP NACKF RDRF TEND TDRE Bits in ICSR register When the generation conditions listed in Table 16 7 are met an I C bus interface interrupt request is generated Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine However bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is automatically set to 0 by reading the ICDRR register When writing transmit data to the ICDRT register the TDRE bit is set to 0 When data is transferred from registers ICDRT to ICDRS the TDRE bit is set to 1 and by further setting the TDRE bit to 0 1 additional byte may be transmitted Set the STIE bit to 1 enable stop condition detection interrupt request when the STOP bit is set to 0 Rev 1 30 Dec 08 2006 Page 210 0f315 speeENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 3 12C bus Interface Mode 16 3 3 1 12C bus Format Setting the FS bit in the SAR register to 0 communicates in UC bus format Figure 16 32 shows the I2C bus Format and Bus Timing The Ist frame following the start condition consists of 8 bits 1 IC bus format a DC bus format FS 0 e SLA pw a 1 7 1
340. same register among the registers associated with the DC bus Interface 00B8h to OOBFh before reading it e An example of waiting three instructions or more Program example MOV B 00h 00BBh _ Set ICIER register to 00h NOP NOP NOP MOV B OOBBh ROL e An example of waiting four cycles or more Program example BCLR 6 00BBh Disable transmit end interrupt request JMP B NEXT NEXT BSET 7 00BBh Enable transmit data empty interrupt request Rev 1 30 Dec 08 2006 Page 231 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter 17 A D Converter The A D converter consists of one 10 bit successive approximation A D converter circuit with a capacitive coupling amplifier The analog input shares pins P1_0 to P1_3 Therefore when using these pins ensure that the corresponding port direction bits are set to 0 input mode When not using the A D converter set the VCUT bit in the ADCON register to 0 Vref unconnected so that no current will flow from the VREF pin into the resistor ladder This helps to reduce the power consumption of the chip The result of A D conversion is stored in the AD register Table 17 1 lists the Performance of A D Converter Figure 17 1 shows a Block Diagram of A D Converter Figures 17 2 and 17 3 show the A D Converter Associated Registers Table 17 1 Performance of A D Converter Hem Performance A D conversion method Successive approximation with capacitive couplin
341. same time the operation completes 18 4 4 2 Erase Status Bits SR5 and FMR07 Refer to 18 4 5 Full Status Check 18 4 4 3 Program Status Bits SR4 and FMRO6 Refer to 18 4 5 Full Status Check Table 18 5 Status Register Bits FMRO Status Name Description Register Bit Reserved Reserved Reserved Reserved Program status Completed Error normally Erase status Completed Error normally Reserved Sequencer Busy Ready status DO to D7 Indicate the data bus which is read when the read status register command is executed Bits FMRO7 SR5 to FMRO6 SR4 are set to 0 by executing the clear status register command When the FMR07 bit SR5 or FMRO6 bit SR4 is set to 1 the program and block erase commands cannot be accepted Rev 1 30 Dec 08 2006 Page 266 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 4 5 Full Status Check When an error occurs bits FMR06 to FMRO7 in the FMRO register are set to 1 indicating the occurrence of an error Therefore checking these status bits full status check can be used to determine the execution result Table 18 6 lists the Errors and FMRO Register Status Figure 18 16 shows the Full Status Check and Handling Procedure for Individual Errors 18 Flash Memory Table 18 6 Errors and FMRO Register Status FRMO Register Status Register Status FMRO07 SR5 FMRO6 SR4 Error Error Occurren
342. select bit 0 Port P3_ R 1 CNTRO output REESEN CD Setto Vin pulse oipo La REESEN NOTES 1 The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the ROEDG bit is rew ritten Refer to 12 5 5 Changing Interrupt Sources RW RW RW W 2 Refer to 14 1 6 Notes on Timer X for precautions regarding the TXS bit Figure 14 5 TXMR Register in Pulse Output Mode Rev 1 30 Dec 08 2006 Page 1140f315 peENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers 14 1 3 Event Counter Mode In event counter mode external signal inputs to the INT1 CNTRO pin are counted refer to Table 14 4 Event Counter Mode Specifications Figure 14 6 shows the TXMR Register in Event Counter Mode Table 14 4 Hem Event Counter Mode Specifications Specification Count source External signal which is input to CNTRO pin Active edge selectable by software Count operations e Decrement e When the timer underflows the contents of the reload register are reloaded and the count is continued Divide ratio 1 n 1 m 1 n value set in PREX register m value set in TX register Count start condition 1 count starts is written to the TXS bit in the TXMR register Count stop condition O count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows timer X interrupt INT10 CNTROO INT11 CNTRO1 pin functions
343. setting a value in the TMO register set the TCC13 bit in the TCC1 register to 1 compare 0 output selected When the TCC13 bit is set to 0 capture selected no value can be written 2 When the TCC13 bit in the TCC1 register is set to 1 the value is set to FFFFh Compare 1 Register b15 b8 b7 b0 b7 Address After Reset 009Fh 009Eh FFFFh Function OES Setting Range Range compare mode Store the value ee with timer C 0000h to FFFFh GER Figure 14 26 Registers TC TMO and TM1 Rev 1 30 Dec 08 2006 Page 143 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 14 Timers Timer C Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 009Ah 00h Bit Bit Symbol Pie Name function o O e se ty C count start bit 0 asa J counting 32 fRING fast Timer C count source select bits INTS interrupt capture polarity select bits 2 Rising edge Falling edge Both edges Do not set Reserved bit Set to 0 b5 INTS interrupt generation timing 0 INT3 Interrupt is generated in select bit 3 synchronization w ith timer C count source 1 INTS Interrupt is generated w hen INTS interrupt is input TCC07 N 93 imterrupt capture input 0 NT3 RW switch bitt 2 1 fRING128 NOTES Change this bit w hen the TCCOO bit is set to 0 count stops The IR bit in the INTSIC register may be set to 1 requests interrupt w hen the TCC03
344. specified in the second bus cycle WD Write data 8 bits BA Given block address x Any specified address in the user ROM area 18 4 3 1 Read Array Command The read array command reads the flash memory The MCU enters read array mode when FFh is written in the first bus cycle When the read address is entered in the following bus cycles the content of the specified address can be read in 8 bit units Since the MCU remains in read array mode until another command is written the contents of multiple addresses can be read continuously In addition the MCU enters read array mode after a reset 18 4 3 2 Read Status Register Command The read status register command is used to read the status register When 70h is written in the first bus cycle the status register can be read in the second bus cycle Refer to 18 4 4 Status Register When reading the status register specify an address in the user ROM area Do not execute this command in EW1 mode The MCU remains in read status register mode until the next read array command is written 18 4 3 3 Clear Status Register Command The clear status register command sets the status register to 0 When 50h is written in the first bus cycle bits FMR06 to FMRO7 in the FMRO register and SR4 to SRS in the status register are set to 0 Rev 1 30 Dec 08 2006 Page 261 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 3 4 Program Command The program com
345. st of the enabled maskable interrupt is generated CPU clock NOTE 5 MHz or below No restriction on clock frequency to be used 1 When the FMR02 bit in the FMRO register is set to 1 rewrite enabled rewriting block 0 is enabled by setting the FMR15 bit in the FMR1 register to 0 rewrite enabled and rewriting block 1 is enabled by setting the FMR16 bit to 0 rewrite enabled Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 251 of 315 stENESAS R8C 1A Group R8C 1B Group 18 Flash Memory 18 4 1 EWO Mode The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMRO1 bit in the FMRO register to 1 CPU rewrite mode enabled In this case since the FMR11 bit in the FMRI register is set to 0 EWO mode is selected Use software commands to control program and erase operations The FMRO register or the status register can be used to determine when program and erase operations complete During auto erasure set the FMR40 bit to 1 erase suspend enabled and the FMR41 bit to 1 request erase suspend Wait for td SR SUS and ensure that the FMR46 bit is set to 1 read enabled before accessing the user ROM area The auto erase operation can be restarted by setting the FMR41 bit to 0 erase restarts To enter program suspend during the auto program operation set the FMR40 bit to 1 suspend enabled and the FMR42 bit to 1 request program suspend Wait for td SR SUS and ensure that the FMR4
346. ster when transmit starts UIIRS bit is set to 1 transfer ends When serial interface completes transmitting data from the UARTi transmit register e When receiving When transferring data from the UARTIi receive register to UIRB register when receive ends Error detection i Oto1 NOTE e Overrun error 1 This error occurs if the serial interface starts receiving the next data item before reading the UiRB register and receives the bit preceding the final stop bit of the next data item e Framing error This error occurs when the set number of stop bits is not detected e Parity error This error occurs when parity is enabled and the number of 1 s in parity and character bits do not match the number of 1 s set e Error sum flag This flag is set is set to 1 when an overrun framing or parity error is generated 1 If an overrun error occurs the receive data b0 to b8 of the UIRB register will be undefined The IR bit in the SiIRIC register remains unchanged Rev 1 30 Dec 08 2006 Page 163 0f 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface Table 15 5 Registers Used and Settings for UART Mode Register Bit Function UiTB 0 to 8 Set transmit data UiRB 0to8 Receive data can be read 1 OER FER PER SUM Error flag UiBRG 0to7 Set a bit rate UiMR SMD2 to SMDO Set to 100b when transfer data is 7 bits long Set to 101b when t
347. ster during transmit TXEPT _ flag 1 No data in transmit register transmit completed Nothing is assigned If necessary set to 0 b4 When read the content is 0 NCH Data output select bit 0 TXDi pin is for CMOS output RW 1 TXDi pin is for N channel open drain output CLK polarity select bit 0 Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Transfer format select bit 0 LSB first NOTE 1 If the BRG count source is switched set the UiBRG register again Figure 15 5 Registers UOCO to U1CO Rev 1 30 Dec 08 2006 Page 156 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 15 Serial Interface UARTi Transmit Receive Control Register 1 i 0 or 1 b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOA5h 02h 00ADh 02h BI Symbol TE Transmit enable bit 0 Disables transmission Rw 1 Enables transmission TI Transmit buffer empty flag 0 Data in UiTB register 1 No data in UiTB register Receive enable bit 0 Disables reception Receive complete flag 0 No data in UiRB register 1 Data in UIRB register Nothing is assigned If necessary set to 0 b7 b4 When read the content is 0 The RI bit is set to 0 when the higher byte of the UIRB register is read out UART Transmit Receive Control Register 2 b7 b6 b5 b4 b3 b2 bi bd
348. stored it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly In this case use standard serial I O mode 18 7 1 6 Program Do not write additions to the already programmed address 18 7 1 7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase suspend Rev 1 30 Dec 08 2006 Page 275 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Please contact Renesas Technology sales offices for the electrical characteristics in the Y version Topr 20 C to 105 C 19 Electrical Characteristics Table 19 1 Absolute Maximum Ratings Symbol Parameter Condition Rated Value Unit Vcc Supply voltage Vcc AVcc 0 3 to 6 5 V AVcc Analog supply voltage Vcc AVcc 0 3 to 6 5 V Vi Input voltage 0 3 to Vcc 0 3 V Vo Output voltage 0 3 to Vcc 0 3 Vv Pd Power dissipation Topr 25 C 300 mW Topr Operating ambient temperature 20 to 85 40 to 85 D version C Tstg Storage temperature 65 to 150 C Table 19 2 Recommended Operating Conditions Symbol Parameter Conditions Standard Typ Vcc Supply voltage AVcc Analog supply voltage Vss Supply voltage AVss Analog supply voltage VIH Input H voltage VIL Input L voltage IOH sum Peak sum output Sum of all pins H current IOH peak
349. t is set as a slave device the chip select line controls input When it is set as the master device the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the CSS1 bit in the SSMR2 register When the MCU is set as a slave device the chip select line sets the SCS pin as an input pin by setting bits CSS1 and CSSO in the SSMR2 register to 01b In 4 wire bus communication mode the MLS bit in the SSMR register is set to 0 and communication is performed MSB first 16 2 6 1 Initialization in 4 Wire Bus Communication Mode Figure 16 18 shows Initialization in 4 Wire Bus Communication Mode Before the data transit receive operation set the TE bit in the SSER register to 0 transmit disabled the RE bit in the SSER register to 0 receive disabled and initialize the clock synchronous serial I O with chip select To change the communication mode or format set the TE bit to 0 and the RE bit to 0 before making the change Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR register Rev 1 30 Dec 08 2006 Page 191 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group SSER register RE bit lt lt 0 TE bit 0 SSMR2 register SSUMS bit 1 SSMR register Set bits CPHS and CPOS MLS bits lt 0 SSCRH register Set MSS bit SSMR2 register SCKS bit lt 1 Set bits SOOS CSS0 to CSS1 and BIDE SSCRH register Set b
350. t the ICDRS register is empty the stored transmit data item is transferred to the ICDRS register and data transmission starts When the next transmit data item is w ritten to the ICDRT register during transmission of the data in the ICDRS register continuous transmit is enabled When the MLS bit in the ICMR register is set to 1 data transferred LSB first and after the data is written to the ICDRT register the MSB LSB inverted data is read NOTE 1 Refer to 16 3 8 1 Accessing of Registers Associated with PC bus Interface for more information Figure 16 29 Registers SAR and ICDRT Rev 1 30 Dec 08 2006 Page 207 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface IC bus Receive Data Register b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOBFh FFh Store receive data When the ICDRS register receives 1 byte of data the receive data is transferred to the ICDRR register and the next receive operation is enabled NOTE 1 Refer to 16 3 8 1 Accessing of Registers Associated with DC bus Interface for more information IC bus Shift Register b7 b6 b5 b4 b3 b2 bi bO This register is used to transmit and receive data The transmit data is transferred from registers ICRDT to ICDRS and data is transmitted from the SDA pin w hen transmitting After 1 byte of data is received data is transferred from registers ICDRS to ICDRR w hile receiving Figure 16 30 Registers ICDRR a
351. t to 1 FMR44 bit is set to 1 and that the and that the during erase during program programming ends erasure ends execution and that execution and that normally normally the erase operation the program has not has not ended ended The above figure shows an example of the use of program suspend during programming following erase suspend NOTE 1 If program suspend is entered during erase suspend always restart programming Figure 18 8 Timing of Suspend Operation Rev 1 30 Dec 08 2006 Page 258 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Figure 18 9 shows How to Set and Exit EWO Mode Figure 18 10 shows How to Set and Exit EW1 Mode EWO Mode Operating Procedure Rewrite control program Write 0 to the FMR01 bit before writing 1 CPU rewrite mode enabled Set registers CMO and CM1 Execute software commands Transfer a rewrite control program which uses CPU rewrite mode to any area other than the flash memory Execute the read array command Write 0 to the FMRO1 bit Jump to the rewrite control program which has been CPU rewrite mode disabled transferred to any area other than the flash memory The subsequent process is executed by the rewrite control program in an area other than the flash memory Jump to a specified address in the flash memory NOTES 1 Select 5 MHz or below for the CPU clock by the CMO6 bit in the CMO register an
352. tect Function 0 cccccccceeeeeeeeeeeeeeeeeeees 18 7 Notes on Flash Memory cece Eed 18 7 1 CPU Rewrite Mode 19 Electrical Characteristics 20 Usage Notes 20 1 Notes on Clock Generation Circuit cceeeeeeeeeeeeeeeeeeeees DOME Stop MOOG EE 20 1 27 Wat MOOG cece uc uaa tale cede aes aed ictal seston 20 1 3 Oscillation Stop Detection Function cseseeeeeees 20 1 4 Oscillation Circuit CGonsiants eee 20 1 5 High Speed On Chip Oscillator Clock nnnnnnnnnaaaaaaaaaen 20 2 Notes on Interrupts een 20 2 1 Reading Address 00000 ee 20 2 2 SOP Setingan ces tance ER 20 2 3 External Interrupt and Key Input Interrupt esssssseeeeee 20 2 4 Watchdog Timer Irterupt eee 20 2 5 Changing Interrupt Gources 20 2 6 Changing Interrupt Control Register Contents 20 3 Precautions ON Tmers 20 3 1 Notesonfmerx 300 20 32 NOES ON UME Z eege EEN AE 300 20 3 3 Notes on Timer Ae eteetde ebe Eed et 301 20 4 Notes on Serial e EE 302 20 5 Precautions on Clock Synchronous Serial Interface eeeeeees 303 20 5 1 Notes on Clock Synchronous Serial I O with Chip Select 303 20 5 2 Netgen eene Ee 304 20 6 Notes on A D Converter 305 20 7 Notes on Flash eege Ee 306 20 7 1 CPU Rewrite de EE 306 20 8 Notes on Re 308 20 8 1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch Up ceeeeeeeeeeeeees 308 20 8 2 Cou
353. ted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but
354. teristics 1 Vcc 5 V Parameter Condition 19 Electrical Characteristics Standard Typ Output H voltage Except Sou lOH 5 mA loH 200 pA XOUT Drive capacity HIGH lOH 1 mA Drive capacity LOW loH 500 pA Output L voltage Except P1_0 to P1_3 XOUT loL 5 mA loL 200 pA P1_0 to P13 Drive capacity HIGH loL 15 mA Drive capacity LOW loL 5 mA Drive capacity LOW lo 200 pA Drive capacity HIGH loL 1 mA Drive capacity LOW loL 500 pA Hysteresis INTO INT1 INT3 KIO KI1 KI2 KI3 CNTRO CNTR1 TCIN RXDO RESET IIH Input H current liL Input L current RPULLUP Pull up resistance RtfXIN Feedback resistance XIN fRING S Low speed on chip oscillator frequency VRAM NOTE RAM hold voltage During stop mode 1 Vcc 4 2 to 5 5 V at Topr 20 to 85 C 40 to 85 C f XIN 20 MHz unless otherwise specified Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 288 of 315 stENESAS R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 15 Electrical Characteristics 2 Vcc 5 V Topr 40 to 85 C unless otherwise specified Parameter Condition Standard Typ Power supply current Vcc 3 3 to 5 5 V Single chip mode output pins are open other pi
355. tervention eg excision administration of medication etc 4 any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp its affiliated companies and their officers directors and employees against any and all damages arising out of such applications You should use the products described herein within the range specified by Renesas especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges Although Renesas endeavors to improve the quality and reliability of its products IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or
356. tes are performed to block A a 1 Kbyte block and then the block is erased the erase count stands at one When performing 100 or more rewrites the actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number 2 Blocks A and B are implemented only in the R8C 1B Group Rev 1 30 Dec 08 2006 Page 245 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory Table 18 2 Flash Memory Rewrite Modes Flash Memory Rewrite Mode Function User ROM area is rewritten by User ROM area is rewritten User ROM area is executing software commands Dy a dedicated serial rewritten by a from the CPU programmer dedicated parallel EWO mode Rewritable in any programmer area other than flash memory EW1 mode Rewritable in flash memory Areas which can User ROM area User ROM area User ROM area be rewritten Operating mode Single chip mode Boot mode Parallel UO mode ROM None Serial programmer Parallel programmer programmer CPU Rewrite Mode Standard Serial I O Mode Parallel I O Mode Rev 1 30 Dec 08 2006 Page 246 of 315 spRENESAS REJ09B0252 0130 R8C 1A
357. the VW2CE6 bit in the VW2C register to the VW2C register to 0 voltage monitor 2 1 voltage monitor 2 interrupt mode reset mode Set the VW2C2 bit in the VW2C register to 0 passing of Vdet2 is not detected Set the CM14 bit in the CM1 register to 0 low speed on chip oscillator on Wait for 4 cycles of the sampling clock of the digital filter No wait time NOTES Set the VW2CO0 bit in the VW2C register to 1 voltage monitor 2 interrupt reset enabled 1 Set the VW2C7 bit to 1 when VCC reaches Vdet2 or below for the voltage monitor 2 reset 2 When the VW2CO0 bit is set to 0 disabled steps 3 4 and 5 can be executed simultaneously with 1 instruction Rev 1 30 REJ09B0252 0130 Dec 08 2006 Page 530f315 stENESAS R8C 1A Group R8C 1B Group 7 Voltage Detection Circuit VCC Vdet2 Typ 3 30 V 2 7 V0 VCA13 bit Sampling clock of digital filt Sampling clock of digital filter x 4 cycles x 4 cycles VW2C2 bit T set to 0 by a program When the VW2C1 bit is set ae Set to 0 by interrupt request to 0 digital filter enabled ag Voltage monitor 2 acknowledgement interrupt request VW2C6 0 Internal reset signal VW2C6 1 Set to 0 by a program x When the VW2C1 bit is VW2C2 bit set to 1 digital filter e disabled and the ee Set to 0 by interrupt VW2C7 bit is set to 0 Voltage monitor 2 request Vdet2 or above interrupt request
358. the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only
359. time p Access restart i ta SR SUS lt l Figure 19 2 Transition Time to Suspend Table 19 6 Voltage Detection 1 Circuit Electrical Characteristics Standard Typ Max Voltage detection level 3 2 85 3 00 Voltage detection circuit self power consumption VCA26 1 Vcc 5 0 V Waiting time until voltage detection circuit operation 100 starts 2 MCU operating voltage minimum value Parameter Condition NOTES 1 The measurement condition is Vcc 2 7 V to 5 5 V and Topr 40 C to 85 C 2 Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0 3 Ensure that Vdet2 gt Vaett Table 19 7 Voltage Detection 2 Circuit Electrical Characteristics Standard Typ Max Voltage detection level 4 3 30 3 60 Voltage monitor 2 interrupt request generation time 40 Voltage detection circuit self power consumption VCA27 1 Vcc 5 0 V 600 Waiting time until voltage detection circuit operation starts 3 Parameter Condition 100 NOTES 1 The measurement condition is Vcc 2 7 V to 5 5 V and Topr 40 C to 85 C 2 Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2 3 Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2 register to 0 4 Ensure that
360. ting the priority for acknowledgement The explanation does not apply to nonmaskable interrupts Use the I flag in the FLG register IPL and bits ILVL2 to ILVLO in each interrupt control register to enable or disable maskable interrupts Whether an interrupt is requested is indicated by the IR bit in each interrupt control register Figure 12 3 shows the Interrupt Control Register and Figure 12 4 shows the INTOIC Register Interrupt Control Register Symbol Address After Reset KUPIC 004Dh XXXXX000b ADIC 004Eh XXXXX000b SSUAIC IIC2A IC 004Fh XXXXX000b CMP1IC 0050h XXXXX000b SOTIC S1TIC 0051h 0053h XXXXX000b SORIC S1RIC 0052h 0054h XXXXX000b TXIC 0056h XXXXX000b TZIC 0058h XXXXX000b INT1IC 0059h XXXXX000b INT3IC 005Ah XXXXX000b b7 b6 b5 b4 b3 b2 b1 b0 TCIC 005Bh XXXXX000b CMPOIC 005Ch XXXXX000b Level 0 interrupt disable Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Requests no interrupt Rw 1 Requests interrupt Nothing is assigned If necessary set to 0 b7 b4 When read the content is undefined 1 Only 0 can be written to the IR bit Do not write 1 2 Rewrite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated Refer to 12 5 6 Changing Interrupt Control Registers 3 The IICSEL bit in the PMR register sw itches functions Figure 12 3 Interrupt Control Register Rev 1 30 Dec 08
361. tion and read the ICDRR register The SCL signal is fixed H after reception of the following byte of data is completed a APLAR PA SDA b bi WW b6 d b7 b d Sy b6 d b7 b input Ee Lf MST bit in ICCR1 register TRS bit in ICCR1 register RDRF bit in ICSR register ICDRS register ICDRR register Processing 2 Set MST bit to 1 3 Read ICDRR register 3 Read ICDRR register by program when transfer clock is output Figure 16 43 Operating Timing in Receive Mode Clock Synchronous Serial Mode Rev 1 30 Dec 08 2006 Page 224 of 315 v ENE SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface 16 3 5 Noise Canceller The states of pins SCL and SDA are routed through the noise canceller before being latched internally Figure 16 44 shows a Block Diagram of Noise Canceller The noise canceller consists of two cascaded latch and match detector circuits When the SCL pin input signal or SDA pin input signal is sampled on f1 and two latch outputs match the level is passed forward to the next circuit When they do not match the former value is retained f1 sampling clock SCL or SDA Match detection circuit Internal SCL or SDA signal input signal Period of f1 f1 sampling clock Figure 16 44 Block Diagram of Noise Canceller Rev 1 30 Dec 08 2006 Page 225 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Sync
362. tion e Clock synchronous serial format MSB first or LSB first selectable as data transfer direction 1 All sources use one interrupt vector for 12C bus interface Rev 1 30 Dec 08 2006 Page 199 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface Transfer clock generation circuit Output ICCR1 register register Transmit receive control circuit ICCR2 register Noise a ICMR register ICDRT register Output SAR register Ea Data bus circuit Noise Address comparison canceller ICDRR register Bus state judgment i circuit Arbitration judgment ICSR register circuit g ICIER register Interrupt generation circuit Interrupt request TXI TEI RXI STPI NAKI Figure 16 22 Block Diagram of 12C bus interface Rev 1 30 Dec 08 2006 Page 200 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group VCC VCC SCL 16 Clock Synchronous Serial Interface SCL input lt q SCL output SDA input SDA output Master SCL input SCL output SDA input SDA output Slave1 SDA input SDA output Slave2 Figure 16 23 External Circuit Connection Example of Pins SCL and SDA Rev 1 30 Dec 08 2006 Page 201 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface IC bus Control Register 1 b7 b6 b5 b4 b3 b2 bi b0 Address A
363. tions e Decrement e After an active edge of the measured pulse is input contents for the read out buffer are retained at the first underflow of prescaler X Then timer X reloads contents in the reload register at the second underflow of prescaler X and continues counting Count start condition 1 count starts is written to the TXS bit in the TXMR register Count stop condition O count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows or reloads timer X interrupt e Rising or falling of CNTRO input end of measurement period INT1 interrupt INT10 CNTROO INT11 CNTRO1 pin functions Measured pulse input 1 INT1 interrupt input CNTRO pin function Programmable I O port Read from timer Contents of the read out buffer can be read out by reading the TX register The value retained in the read out buffer is released by reading the TX register Write to timer When registers TX and PREX are written while the count is stopped values are written to both the reload register and counter e When registers TX and PREX are written during the count the value is written to each reload register of registers TX and PREX at the following count source input the data is transferred to the counter at the second count source input and the count re starts at the third count source input Select functions NOTE e INT1 CNTRO
364. top set the HRAO1 bit to 1 high speed on chip oscillator selected and bits OCD1 to OCDO to 11b oscillation stop detection function enabled Rev 1 30 Dec 08 2006 Page 74 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit Table 10 6 Determining Interrupt Source for Oscillation Stop Detection Watchdog Timer and Voltage Monitor 2 Interrupts Generated Interrupt Source Bit Showing Interrupt Cause Oscillation stop detection a OCD3 bit in OCD register 1 a or b b Bits OCD1 to OCDO in OCD register 11b and OCD2 bit 1 Watchdog timer VW2C3 bit in VW2C register 1 Voltage monitor 2 VW2C2 bit in VW2C register 1 Switch to main clock Determine OCD3 bit a 1 main clock stops 0 main clock oscillates Judge several times Determine several times that the main clock is supplied Set bits OCD1 to OCDO to 00b oscillation stop detection function disabled Set OCD2 bit to 0 select main clock End Bits OCD3 to OCDO Bits in OCD register Figure 10 11 Procedure for Switching Clock Source from Low Speed On Chip Oscillator to Main Clock Rev 1 30 Dec 08 2006 Page 75 of 315 2tENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 10 Clock Generation Circuit 10 6 Notes on Clock Generation Circuit 10 6 1 Stop Mode When entering stop mode set the FMRO1 bit in the FMRO register to 0 CPU rewrite mode disabled and the CM10 bit in the CM1 registe
365. transfer rate selected by bits CKSO to CKS2 in the SSCRH register When the MSS bit in the SSCRH register is set to 0 operates as slave device an external clock can be selected and the SSCK pin functions as input 16 2 1 1 Association between Transfer Clock Polarity Phase and Data The association between the transfer clock polarity phase and data changes according to the combination of the SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register Figure 16 10 shows the Association between Transfer Clock Polarity Phase and Transfer Data Also the MSB first transfer or LSB first transfer can be selected by setting the MLS bit in the SSMR register When the MLS bit is set to 1 transfer is started from the LSB and proceeds to the MSB When the MLS bit is set to 0 transfer is started from the MSB and proceeds to the LSB Rev 1 30 Dec 08 2006 Page 179 0f 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 16 Clock Synchronous Serial Interface e SSUMS 0 clock SE communication mode CPHS bit 0 data change at odd edge and CPOS bit 0 H when clock stops KEE e SSUMS 1 4 wire bus communication mode and CPHS 0 data change at odd edge eso LT LE LILI LIL Lu H when clock stops SSCK CPOS 1 L when clock stops SSO SSI e SSUMS 1 4 wire bus communication mode and CPHS 1 data download at odd edge SSCK CPOS 0 CH when clock stops SSCK C
366. transmit mode are as follows 1 2 3 4 5 6 7 Set the STOP bit in the ICSR register to 0 to reset it Then set the ICE bit in the ICCR1 register to 1 transfer operation enabled Then set bits WAIT and MLS in the ICMR register and set bits CKSO to CKS3 in the ICCR1 register initial setting Read the BBSY bit in the ICCR2 register to confirm that the bus is free Set bits TRS and MST in the ICCR1 register to master transmit mode The start condition is generated by writing 1 to the BBSY bit and 0 to the SCP bit by the MOV instruction After confirming that the TDRE bit in the ICSR register is set to 1 data is transferred from registers ICDRT to ICDRS write transmit data to the ICDRT register data in which a slave address and R W are indicated in the Ist byte At this time the TDRE bit is automatically set to 0 data is transferred from registers ICDRT to ICDRS and the TDRE bit is set to 1 again When transmission of 1 byte of data is completed while the TDRE bit is set to 1 the TEND bit in the ICSR register is set to at the rise of the 9th transmit clock pulse Read the ACKBR bit in the ICIER register and confirm that the slave is selected Write the 2nd byte of data to the ICDRT register Since the slave device is not acknowledged when the ACKBR bit is set to 1 generate the stop condition The stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV instruction The SCL s
367. tten during A D conversion the conversion result is undefined 2 When the VCUT bit is set to 1 connected from 0 not connected w ait for 1 us or more before starting A D conversion Figure 17 4 Registers ADCONO and ADCON1 in One shot Mode Rev 1 30 Dec 08 2006 Page 237 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 2 Repeat Mode 17 A D Converter In repeat mode the input voltage of one selected pin is A D converted repeatedly Table 17 3 lists the Repeat Mode Specifications Figure 17 5 shows Registers ADCONO and ADCON in Repeat Mode Table 17 3 Repeat Mode Specifications Specification Function The Input voltage of one pin selected by bits CH2 to CHO is A D converted repeatedly Start conditions e When the ADCAP bit is set to 0 software trigger set the ADST bit to 1 A D conversion starts e When the ADCAP bit is set to 1 capture timer Z interrupt request is generated while the ADST bit is set to 1 Stop condition Set the ADST bit to 0 Interrupt request generation timing Not generated Input pin Select one of AN8 to AN11 Reading of A D conversion result Read AD register Rev 1 30 Dec 08 2006 Page 238 of 315 pRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 17 A D Converter A D Control Register 0 b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 00D6h 00000XXXb Analog input pin select b2 b1 b bits 100 AN8 101 AN9
368. ual peripheral function Pull up selection Direction register Output fro Data bus Digital filter P3_4 P3_5 P3_7 Input to individual peripheral function NOTE 1 MR symbolizes a parasitic diode Ensure the input voltage to each port will not exceed VCC Figure 5 2 Configuration of Programmable I O Ports 2 Rev 1 30 Dec 08 2006 Page 26 of 315 7RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports Vref of A D converter Data bus Pull up selection E BS Si BD O Data bus Port latch Input to individual peripheral function Digital filter P4_6 XIN Clocked inverter P4_7 XOUT Data bus NOTES 1 When CMO5 1 CM10 1 or CM13 0 the clocked inverter is cut off 2 When CM10 1 or CM13 0 the feedback resistor is disconnected 3 When CM05 CM13 1 or CM10 CM13 1 this pin is pulled up 4 symbolizes a parasitic diode Ensure the input voltage to each port does not exceed VCC Figure 5 3 Configuration of Programmable I O Ports 3 Rev 1 30 Dec 08 2006 Page 270f315 sENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports MODE signal input Gi RESET signal input NOTE 1 symbolizes a parasitic diode Ensure the input voltage to each port will not exceed VCC Figure 5 4 Configuration of UO Pins Rev 1 30 Dec 08 2006 Page 28 of 315
369. uence error Check if command is properly input Re execute the command Erase error Erase error y Execute the clear status register command set these status flags to 0 Erase command Block targeting for erasure re execution times lt 3 times cannot be used fie oT rove Re execute block erase command Program error y Execute the clear status register command set these status flags to 0 Full status check completed y Specify the other address besides the write address where the error occurs for the program address NOTE 1 To rewrite to the address where the program error occurs check if the full y status check is complete normally and write to the address after the block S Re execute program command gt erase command is executed Figure 18 16 Full Status Check and Handling Procedure for Individual Errors Rev 1 30 Dec 08 2006 Page 268 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 18 Flash Memory 18 5 Standard Serial UO Mode In standard serial I O mode the user ROM area can be rewritten while the MCU is mounted on board by using a serial programmer which is suitable for the MCU Standard serial I O mode is used to connect with a serial programmer using a special clock asynchronous serial I O There are three standard serial I O modes e Standard serial I O mode 1 Clock synchronous se
370. undefined added Figure 14 10 pulled up added NOTE 6 In this case of the read out buffer deleted NOTE 7 deleted Figure 15 10 revised Figure 16 3 SSCRL NOTE 2 revised Figure 16 26 NOTE 3 revised Figure 16 32 to Figure 16 36 revised Table 18 3 Item Modes after read status register added Figure 18 8 revised 18 4 3 1 In addition after a reset added 18 4 3 2 The MCU remains in read command is written added 18 4 3 4 The FMROO bit is set to 0 during 1 when auto programming completes When suspend function 0 when autoprogramming completes revised Figure 18 13 added Figure 18 15 revised Figure 18 16 revised Table 19 2 Parameter System clock added 21 2 revised 5 deleted Package Dimensions PWQNO0028KA B revised 1 30 Dec 08 2006 20 Table 4 1 OOOFh After reset OOOXXXXXb 00X11111b Table 5 17 Setting Value revised Figure 10 2 NOTE 4 revised REVISION HISTORY R8C 1A Group R8C 1B Group Hardware Manual D Description ae Summary Dec 08 2006 Figure 10 8 added Figure 10 9 added 10 6 1 revised 10 6 2 Program example to execute the WAIT instruction revised Table 12 6 revised Figure 13 2 WDC After Reset 00011111b gt 00X11111b Figure 15 7 revised Figure 15 10 revised 15 3 To check receive errors read the UiRB register and then use the read data added Figure 16 24 NOTE 1 revised Figure 17 2 ADCONO NOTE 2 re
371. up 7 Voltage Detection Circuit Voltage Monitor 1 Circuit Control Register b7 b6 b5 b4 b3 b2 bi b0 Address After Reset 0036h Hardw are reset 0000X000b Pow er on reset voltage monitor 1 reset 0100X001b Voltage monitor 1 reset enable 0 Disable Voltage monitor 1 digital filter 0 Digital filter enabled mode disable mode select bit digital filter circuit enabled 1 Digital filter disabled mode digital filter circuit disabled We Reserved bit Set to 0 an Reserved bit When read the content is undefined FO b3 Sampling clock select bits b5 b4 VW1F0 0 0 fRING S divided by 1 0 1 fRING S divided by 2 10 fRING S divided by 4 1 1 fRING S divided by 8 Voltage monitor 1 circuit mode When the VW1CO bit is set to 1 voltage select bit monitor 1 reset enabled set to 1 RW RW RW RW VWIF1 RW RW w condition select bit disabled mode set to 1 Voltage monitor 1 reset generation When the VW1C1 bit is set to 1 digital filter H Ri NOTES Set the PRCS bit in the PRCR register to 1 write enable before writing to this register When rewriting the VW1C register the VW1C2 bit may be set to 1 Set the VW1C2 bit to 0 after rewriting the VW1C register The value remains unchanged after a softw are reset w atchdog timer reset or voltage monitor 2 reset The VW1CO0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 voltage detection 1 circuit enabled Set the VW1CO0 bit to 0
372. v EN SAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 5 Programmable UO Ports Port Pi Direction Register i 1 3 4 b7 b6 b5 b4 b3 b2 bi bO Symbol Address After Reset PD1 OOE8h 00h PD3 DOE 00h PD4 OOEAh 00h eseu ee POLO Por RO drectonbt o Input mode Ca functions as an input port Di PD2 Port P2 direction bt Output mode Pw functions as an output port PW Pw w POG _ Port Pi6 direction bit Pw w NOTES 1 Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU If it is necessary to set bits PD3_0 to PD3_2 and PD3_6 set to 0 input mode When read the content is 0 Bits PD4_0 to PD4_4 PD4_6 and PD4_7 in the PD4 register are unavailable on this MCU If it is necessary to set bits PD4_0 to PD4_4 PD4_6 and PD4_7 set to 0 input mode When read the content is 0 Figure 5 5 Registers PD1 PD3 and PD4 Port Pi Register i 1 3 b7 b6 b5 b4 b3 b2 bi bO Address After Reset OOE1h Undefined OOE5h Undefined P3 Bit Symbol Pio Pot Pid bit The pin level of any VO port which is set Port Di bit to input mode can be read by reading the Port Pi2 bit corresponding bit in this register The pin Port Pi3 bit level of any VO port which is set to output Port Pid bit mode can be controlled by writing to the AS Port P5 bit corresponding bit in this register 0 L level me Ieren 1 H level SH a NOTE 1 Bits P3_0 to P3_2 and P3_6 in th
373. v 1 30 Dec 08 2006 Page 298 of 315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 20 Usage Notes 20 2 6 Changing Interrupt Control Register Contents a The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated If interrupt requests may be generated disable interrupts before changing the interrupt control register contents b When changing the contents of an interrupt control register after disabling interrupts be careful to choose appropriate instructions Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction the IR bit may not be set to 1 interrupt requested and the interrupt request may be ignored If this causes a problem use the following instructions to change the register AND OR BCLR BSET Changing IR bit If the IR bit is set to 0 interrupt not requested it may not be set to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag as shown in the sample programs below Refer to b regarding changing the contents of interrupt control registers by the sample programs Sample programs to 3 are for preventing the I flag from being set to 1 interrupts enabled before the interrupt control register is changed for reasons of the internal bus or the instruction
374. vation time CPU clock x 28 cycles 1 1 CPU clock x 11 cycles 1 cue TL aa E a P LOLA LLL OFFFCh OFFFEh y Address internal address signal OFFFDh Content of reset vector NOTE 1 Hardware reset Figure 6 3 Reset Sequence Rev 1 30 Dec 08 2006 Page 390f315 RENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 6 Resets 6 1 Hardware Reset A reset is applied using the RESET pin When an L signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions pins CPU and SFRs are reset refer to Table 6 2 Pin Functions while RESET Pin Level is L When the input level applied to the RESET pin changes from L to H a program is executed beginning with the address indicated by the reset vector After reset the low speed on chip oscillator clock divided by 8 is automatically selected as the CPU clock Refer to 4 Special Function Registers SFRs for the state of the SFRs after reset The internal RAM is not reset If the RESET pin is pulled L while writing to the internal RAM is in progress the contents of internal RAM will be undefined Figure 6 4 shows an Example of Hardware Reset Circuit and Operation and Figure 6 5 shows an Example of Hardware Reset Circuit Usage Example of External Supply Voltage Detection Circuit and Operation 6 1 1 When Power Supply is Stable 1 Apply L to the RESET pin 2 Wait for 500 u
375. vised Table 17 2 Stop conditions when the ADCAP bit is set to 0 software trigger added Figure 17 4 ADCONO NOTE 2 revised Figure 17 5 ADCONO NOTE 2 revised 18 4 1 18 4 2 td SR ES td SR SUS Table 19 2 Parameter OCD2 1 On chip oscillator clock selected revised 20 1 1 revised 20 1 2 Program example to execute the WAIT instruction revised R8C 1A Group R8C 1B Group Hardware Manual Publication Date Rev 0 10 Jun 30 2005 Rev 1 30 Dec 08 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan R8C 1A Group R8C 1B Group Hardware Manual 2tENESAS Renesas Electronics Corporation 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan REJO9B0252 0130
376. wer supply for the A D converter Connect a capacitor between AVCC and AVSS Reset Input RESET Input L on this pin resets the MCU MODE MODE Connect this pin to VCC via a resistor Main Clock Input XIN Main Clock Output XOUT These pins are provided for main clock generation circuit I O Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins To use an external clock input it to the XIN pin and leave the XOUT pin open INT Interrupt INTO INT1 INT3 INT interrupt input pins Key Input Interrupt KIO to KI3 Key input interrupt input pins Timer X CNTRO Timer X I O pin CNTRO Timer X output pin Timer Z TZOUT Timer Z output pin Timer C TCIN Timer C input pin CMP0_0 to CMPO_2 CMP1_0 to CMP1_2 Timer C output pins Serial Interface CLKO Transfer clock I O pin RXDO RXD1 Serial data input pins TXDO TXD1 Serial data output pins Clock synchronous serial I O with chip select SSU SS100 SSI01 Data I O pin SCS Chip select signal I O pin SSCK Clock I O pin SSO Data I O pin 12C bus Interface SCL Clock I O pin SDA Data I O pin Reference Voltage Input VREF Reference voltage input pin to A D converter A D Converter AN8 to AN Analog input pins to A D converter I O Port P1_0 to P1_7 P3_3 to P3_5 P3_7 P4_5
377. y erased because the fixed vector is allocated in block 0 Rev 1 30 Dec 08 2006 Page 306 of 315 RENESAS REJ09B0252 0130 Table 20 2 R8C 1A Group R8C 1B Group Status EW1 Mode Interrupts When Maskable Interrupt Request is Acknowledged 20 Usage Notes When Watchdog Timer Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request is Acknowledged During auto erasure erase Suspend function enabled Auto erasure is suspended after td SR SUS and interrupt handling is executed Auto erasure can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after interrupt handling completes During auto erasure erase suspend function disabled Auto erasure has priority and the interrupt request acknowledgement is put on standby Interrupt handling is executed after auto erasure completes During auto programming program suspend function enabled Auto programming is suspended after td SR SUS and interrupt handling is executed Auto programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 program restart after interrupt handling completes During auto programming program suspend function disabled Auto programming has priority and the interrupt request acknowledgement is put on standby Interrupt handling is executed after auto programming completes Once an interrupt request is acknowledged auto programming
378. ynchronous Serial I O with Chip Select Slave Rev 1 30 Dec 08 2006 Page 285 of 315 seRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics VIH or Von SSCK VIH or Von tsucyc SSO output SSI input Figure 19 6 I O Timing of Clock Synchronous Serial I O with Chip Select Clock Synchronous Communication Mode Rev 1 30 Dec 08 2006 Page 286 of 315 spRENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group 19 Electrical Characteristics Table 19 13 Timing Requirements of 12C bus Interface 1 Standard Min Typ SCL input cycle time 12tcyc 600 2 SCL input H width 3tcyc 300 2 SCL input L width 5tcyc 300 2 SCL SDA input fall time SCL SDA input spike pulse rejection time Parameter Condition SDA input bus free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time 1tcyc 20 2 Data input hold time 0 NOTES 1 Vcc 2 7 to 5 5 V Vss 0 V and Ta 20 to 85 C 40 to 85 C unless otherwise specified 2 1tcyc 1 f1 s 1 U U I NOTES 1 Start condition 2 Stop condition 3 Retransmit start condition Figure 19 7 I O Timing of 12C bus Interface Rev 1 30 Dec 08 2006 Page 287 of 315 speENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Table 19 14 Electrical Charac
379. yte PLSP0020JB A R5F211A1DD 4 Kbytes 384 bytes PRDP0020BA A R5F211A2DD 8 Kbytes 512 bytes PRDP0020BA A R5F211A3DD 12 Kbytes 768 bytes PRDP0020BA A R5F211A4DD 16 Kbytes 1 Kbyte PRDP0020BA A R5F211A2NP 8 Kbytes 512 bytes PWQN0028KA B R5F211A3NP 12 Kbytes 768 bytes PWQN0028KA B R5F211A4NP 16 Kbytes 1 Kbyte PWQN0028KA B R5F211A1XXXSP 4 Kbytes 384 bytes PLSP0020JB A Factory programming product 1 R5F211A2XXXSP 8 Kbytes 512 bytes PLSP0020JB A R5F211A3XXXSP 12 Kbytes 768 bytes PLSP0020JB A R5F211A4XXXSP 16 Kbytes 1 Kbyte PLSP0020JB A R5F211A1DXXXSP 4 Kbytes 384 bytes PLSP0020JB A D version R5F211A2DXXXSP 8 Kbytes 512 bytes PLSP0020JB A R5F211A3DXXXSP 12 Kbytes 768 bytes PLSP0020JB A R5F211A4DXXXSP 16 Kbytes 1 Kbyte PLSP0020JB A R5F211A1XXXDD 4 Kbytes 384 bytes PRDP0020BA A Factory programming product 1 R5F211A2XXXDD_ 8 Kbytes 512 bytes PRDPOO20BA A R5F211A3XXXDD_ 12 Kbytes 768 bytes PRDPOO020BA A R5F211A4XXXDD_ 16 Kbytes 1 Kbyte PRDPOO20BA A R5F211A2XXXNP_ 8 Kbytes 512 bytes PWQNO0028KA B R5F211A3XXXNP_ 12 Kbytes 768 bytes PWQNO0028KA B R5F211A4XXXNP 16 Kbytes 1 Kbyte PWQN0028KA B NOTE 1 The user ROM is programmed before shipment Type No ROM Capacity Package Type Remarks Rev 1 30 Dec 08 2006 Page50f315 stENESAS REJ09B0252 0130 R8C 1A Group R8C 1B Group Type No R5F 21 1A 4 D XXX SP

R8C/1A, R8C/1B Group Hardware Manual

Contents

Download Pdf Manuals

Related Search

Related Contents