807_8300PUG
Contents
1. GPIOE3 GPIOE4 GPIOES5S GPIOE6 GPIOE7 GPIOE8 GPIOE9 GPIOE10 GPIOE11 TD2 GPIOE12 Not Defined GPIOFO D 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 3 Preliminary Table 6 16 56F8300 56F8100 GPIO Assignments Continued 56F834x 56F807 Peripheral S6F835x Bat Function 56F836x Peripheral Function o fow O o e 6 5 5 Power Supervisor In the 56F807 the power supervisor was considered part of the system integration module In the 56F8300 56F8100 devices this function has been decoupled and enhanced Low voltage interrupt enables have been moved from the 56F807 System Control Register SYS _CNTL to the 56F8300 56F8100 Power Supervisor Control Register as shown here 56F807 to 56F8300 56F8100 Porting Guide Rev 0 32 Freescale Semiconductor Preliminary 56F807 System Control Register SYS BASE 0 15 14 13 12 11 10 9 8 7 6 5 TMR CTR ADR DATA Oo 0 O BOOT F i naz LVIE22 pD o Po o Ti v 0 O 0 0 0 0 o XO Of 0 g Unimplemented or Reserved 56F834x 56F835x and 56F836x Power Supervisor Control Register LVI BASE 0 R W LVIE27 LVIE22 RESET Unimplemented or Reserved Figure 6 3 Low Voltage Interrupt Enables The actual status and interrupt bits themselves have been moved from the SYS_STS register to the Power Supervisor Status Register see Figure 6 4 In the 56F807 the status pins were sticky and to2. Table 6 15 GPIO Port Sizes 56F834x 56F835x 56F836x 6 5 4 1 PER for Port B The peripheral enable bits for GPIO B 3 0 are 0 in the 56F807 On the 56F8300 56F8100 devices they are a function of the EXTBOOT and EMI MODE pins as the device exits reset See the Program Memory Map section 1n the individual device s Data Sheet for details 6 5 4 2 GPIO_x_RAWDATA Register These registers are not present on the 56F807 They are an enhancement to the GPIO function which allows the state of GPIO pins to be read at any time even when those pins are not in GPIO mode This isa READONLY register 6 5 4 3 GPIO_x PPMODE Register These registers are not present on the 56F807 They are an enhancement to the GPIO function which allows the GPIO pins to operate in Push Pull Mode or in Open Drain Mode The default is Push Pull Mode which is consistent with previous devices 6 5 4 4 Pin Assignments Table 6 16 illustrates GPIO pin assignments for the 56F807 and 56F8300 56F8100 devices On the 5656F807 peripherals muxed with GPIO took precedence at reset This 1s also true on 56F8300 S56F8100 devices with the exception of GPIOB 3 0 a function of boot mode and GPIOD 5 0 In the latter case GPIO are active at reset even though muxed with EMI chip selects This function is consistent with the 56F807 where those GPIO were not muxed Shaded areas in Table 6 16 indicate which function is active upon exiting reset in 5 6F8300 56F8 100 devices 56F
3. 56F8300 56F8100 devices will be addressed in the sections devoted to individual peripherals later in this manual Table 6 8 Data Memory Peripheral Address Map Summary i Eseries n one foo PFIU1_BASE 1340 00 F400 Common FM on 56F8300 56F8100 devices separate FIU s for each PFIU2_ BASE 1420 flash block on 56F807 BFIU BASE 1380 DFIU_BASE 1360 FlexCAN Not Applicable 00 F800 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 17 Preliminary Table 6 8 Data Memory Peripheral Address Map Summary Continued Peripheral FlexCAN2 GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E GPIO Port F INTC MSCAN PWM A PWM B Power Supervisor SCI 0 SCI 1 SIM SPI 0 SPI 1 System Integation Timer A Timer B Timer C Timer D 56F807 56F834x 56F835x 56F836x Base Address Base Address wro TMRD 1160 00 F100 1 The Power Supervisor Module was previously incorporated into the 56F807 System Integration Module 6 5 Issues Relating to Specific Peripherals 6 5 1 Interrupt Controller The 56F8300 56F8100 devices interrupt controllers include significant enhancements over that found in the 56F807 As shown in Table 6 9 the memory maps are significantly different This section provides an overview of portability issues however the reader is referred to the 56F8300 56F8100 Data Sheets for details 18 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Free
4. bits have been moved into their own register and additional granularity has been provided The TMRPD ADRPD and DATAPD bits from the 56F807 SYS _CNTL register have 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 41 Preliminary been removed from the 56F8300 56F8 T UU since all associated pins have been muxed with GPIO capabilities and the GPIO control registers therefore handle pull up enabling The 56F8300 56F8100 boot modes are a bit different than those on the 56F807 and the BOOTMAP bit has been eliminated as the OMR MA amp MB bits serve that function in the 56F8300 56F8100 devices Finally the low voltage interrupt enable bits have been moved into the power supervisor module register set 56F8300 S6F8100 SIM Control Register feet elelelelal lelele i s fs e s 2 iif s Read EMI_ Ea ar aR E MODE os ar aR E ie gt ERE Y oTo BOOTMAP function covered via OMR MA amp See Section 6 5 5 MB bits in 56F8300 56F8100 For details see the Program Memory Map section in the Data Sheet for the specific device being implemented 56F807 System Control Bian a conn SYS_BASE 0 15 14 13 SEE E EE RR er oes bo oo W SSS POST ie aa S T RESET Unimplemented or Reserved 56F8300 S6F8100 SIM Pull up Disable Register Beret S R T D jeje TETE a Bm Pr a aieas rite eee fee Figure 6 7 56F807 SYS_CNTL Register Mappings 6 5 16 2 System Status Register The low voltage
5. interrupt bits in the 56F807 SYS STS register have been moved to the power supervisor See Section 6 5 5 for details 56F807 to 56F8300 56F8100 Porting Guide Rev 0 42 Freescale Semiconductor Preliminary The COPR EXTR amp POR bits have been moved to the same locations in the 56F8300 56F8 1 00 devices SIM RSTSTS register 56F807 System Status Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 te et ee a ee 7 2 RESET 0 0 0 0 0 0 0 0 0 0 0 0 1 O 0 0 Unimplemented or Reserved 56F8300 56F8100 Reset Status Register 15 14 13 12 11 10 9 8 7 6 5 6 1 0 S 1 78 O O I swe copa ext Oo S 0 0 0 0 Q CS SS SS H a T T Pa T RESET 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 6 8 SYS_STS Mapping to SIM_RSTSTS 6 5 16 3 JTAG ID The 56F807 and 56F8300 S56F8100 devices all provide memory mapped registers containing the chip s JTAG ID These are contrasted in Table 6 21 Table 6 21 56F807 vs 56F8300 56F8100 JTAG IDs 56F834x 56F835x 56F807 56F834x 56F835x 56F836x 01F2 11F4 01F4 01D6 SIM_LSH_ID 701D 401D 601D D01D 1 Value for Rev C and later 56F834x devices value for Rev A and B 56F834x devices is 01F4 6 5 16 4 Test Registers The 56F807 Test Registers 0 4 TST REGO through TST REG4 are never reset during normal operation and were originally intended primarily for factory test scratchpad use The 56F8300 56F8100 devices offer SIM Software Control Registers 0 3 SIM SCRO through SIM SCR3 T
6. only in the mix of peripherals and the amount of on chip memory provided This document will view the memory map as a distinguishing feature and therefore devices will be described using the generic part number such as 56F834x in most cases The 56F8100 family of devices has the same internal address map as the equivalent 56F8300 devices except that certain memory features and peripherals are not provided Table 1 1 Device Naming Conventions Generic Part Name Device Part Number eye 56F8345 568346 56F8347 and 56F8145 56F8146 56F8147 56F835x 56F8355 56F8356 56F 8357 and 56F8155 56F8156 56F8157 56F 8365 56F8366 56F8367 and gaia 56F8165 56F8166 56F8167 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Devices ending in the same last digit such as the 56F8345 56F8355 and 56F8365 are packaged identically and therefore have the same pin out The only deviation is that the 56F8365 56F8366 and 56F8367 devices add a second FlexCAN module 1 2 Conventions This manual uses the following conventions OVERBAR This is used to indicate a signal that is active when pulled low For example the RESET pin is active when low asserted A high true active high signal is high or a low true active low signal is low deasserted A high true active high signal is low or a low true active low signal is high Examples Signal Symbol Logic State Signal State Voltag
7. query the current voltage status it was necessary to clear those bits and reread them In the 56F8300 56F8100 there are sticky and non sticky versions of the same bits all of which may be accessed with a single read operation 56F807 System Status Register SYS BASE 1 15 14 13 12 11 10 R o o o o o o o o o o o ORTE OR iye fiva g 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved 56F8300 S6F8100 Power Hann Status LVI BASE 1 15 14 i opo poyo o o o oo oo T ozs iez w E T T E OE CE D RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved f These are the non sticky versions Figure 6 4 Power Supervisor Status Bits 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 33 Preliminary 6 5 6 CAN Module The 56F8300 56F8100 devices contain Freescale s FlexCAN interface instead of the MSCAN MSCAN represents a basic CAN implementation while FlexCAN represents a full CAN implementation The two modules are not software compatible CAN communication routines must be redesigned for FlexCAN The FlexCAN module will NOT have the option of using the oscillator time clock the PLL clock should be accurate enough for all operation 6 5 7 Analog to Digital Converters The 56F807 and 56F8300 56F8100 devices contain 2 dual ADC converters On the 56F807 each dual has its own single pin voltage reference circuit On 56F8300 S56F8100 devices a single 6 pin circu
8. the 56F807 CLKOSEL field has been relabeled CLKDIS and is now at bit location 5 but the function remains the same The set of clocks available for viewing has necessarily changed The CLKOSEL field has been extended by 1 bit to allow additional choices The two chips are contrasted in Table 6 14 Table 6 14 CLKOSEL Contrasted 56F 834x 56F807 56F835x 56F836x CLKOSEL CLKDIS CLKOSEL 56F807 56F8300 56F8100 1XXXXX No Clock No Clock 000000 ZCLK Default sys_clk Default 000001 T 56800E clock 000010 T1 XRAM clock 000011 T PFLASH odd clock 000100 T PFLASH even clock 000101 PHIO BFLASH clock 000110 PHI1 DFLASH clock 00111 CTZN oscillator output 001000 CT301EN Fout from OCCS 001001 IPB Clock IPB Clock 001010 Feedback Feedback 001011 Prescaler Prescaler 001100 Fout Postscaler 001101 Fout 2 sys_clk_x2 001110 Postscaler sys_clk_div2 001111 Postscaler sys_clk_d 010000 N A ADCA clk 010001 N A ADCB clk 56F807 to 56F8300 56F8100 Porting Guide Rev 0 26 Freescale Semiconductor Preliminary The 56F8300 56F8100 devices have additionally added four bits to CLKOSR which provide individual controls for bringing the oscillator clock sys clk x2 sys_clk and prescaler clocks out on GPIOB 7 4 respectively should these pins not be required for use as GPIO 6 5 2 4 Shutdown Register This register can be used to shut off all system clocks in the event that a loss of reference clock interrupt has occurred indicating that the os
9. 00 56F8100 EMI will emulate the 56F807 EMI in external boot mode subject to the following change On the 56F8300 56F8100 the RD signal assertion is delayed 1 4 cycle from where it occurred on the 56F807 so that 1t can be used as an output enable signal to avoid external bus contention 6 5 10 SCI This is the same module as implemented on the 56F807 Because the bus frequency has been increased to 6 0MHz max it will be necessary to change the value of the SCI Baud Rate Register SCIBR to adjust Table 6 17 and Table 6 18 show baud rate settings for the SCI at bus speeds of 40MHz and 60MHz These correspond to the maximum bus speeds for the 56F807 and the 56F8300 respectively This demonstrates that code previously operating at 9600 baud on the 56F807 at 40MHz set the SBR to 260 This must be changed to SBR 391 for the 56F8300 devices to maintain the same bit rate at a processor speed of 60MHz 56F807 to 56F8300 56F8100 Porting Guide Rev 0 36 Freescale Semiconductor Preliminary Table 6 17 Example Baud Rates Module Clock 40MHz SBR Receiver Clock Transmitter Clock Target Baud Error Bits I aa Rate nang 9384 6 mann 5 38 400 400 E 307692 3 19230 8 19 200 1042 38387 7 2399 2 2400 0 03 2083 19203 1 1200 2 1200 E Table 6 18 Example Baud Rates Module Clock 60MHz SBR ReceiverClock Transmitter Clock Target Baud Error Bits a Rate nua 9 aans 3 38 400 400 307692 3 19230 8 ea ITH
10. 02 0000 P 01 0000 128KB 128KB P 000000 128KB COP Reset Address 00 0002 Boot Location 00 0000 1 If Flash Security Mode is enabled EXTBOOT Mode 1 cannot be used See Security Features Part 7 of the device Data Sheet 2 This mode provides maximum compatibility with 56F80x parts while operating externally 3 EMI MODE 0 when EMI MODE pin is tied to ground at boot up 4 EMI_MODE 1 when EMI_MODE pin is tied to Vpp at boot up 5 Not accessible in reset configuration since the address is above P 00 FFFF The higher bit address GPIO and or chip selects pins must be reconfigured before this external memory is accessible 6 Booting from this external address allows prototyping of the internal Boot Flash 7 Two independent program Flash blocks allow one to be programmed erased while executing from another Each block must have its own mass erase 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Table 6 5 Program Memory Map for 56F836x at Reset Mode 0 MA 0 Mode 11 MA 1 Begin End Internal Boot External Boot Address Internal Boot EMI_MODE 02 2 EMI_MODE 14 16 Bit External Address Bus 16 Bit External Address Bus 20 Bit External Address Bus P 1F FFFF External Program Memory External Program Memory External Program Memory P 10 0000 P 0F FFFF External Program Memory P 05 0000 COP Reset Address 04 00027 P 04 FFFF On Chip Program RAM Boot Locati
11. 07 device did not include a feature for protecting Flash contents from unauthorized access the 56F8300 S56F8100 devices do By necessity this mode prohibits access to off chip program space and disables the EOnCE port This could have the apparent impact of breaking existing code if that earlier code required the disabled features If the Flash security bit is not set then operation is consistent with the 56F807 6 3 3 Interrupt Vector Table Design of the 56F8300 56F8100 Interrupt Vector Table was complicated by changes to the core itself as well as conflicting compatibility requirements with regard to existing S6800E products 56835x family as well as the 56F807 Core SWI SCI PLL SPI 0 SCI 0 and SCI 1 vector locations are compatible with the 56835x 56800E baseline Due to the large number of timer channels on these devices timer interrupt vectors have been condensed in a manner consistent with the S6F80x family The 56800 peripheral vectors have been moved as necessary to fit into the preceding constraints Table 6 6 provides reset and interrupt vectors for 56F807 and 56F8300 S56F8100 devices including on chip peripherals Note that interrupt priorities are set via the interrupt controller In the 56F807 the highest vector number within a given interrupt level has priority For 56F8300 56F8100 devices the lowest vector number within a given interrupt level has higher priority The 56800E core used in the 56F8300 56F8100 devices provide
12. 4
13. 56F807 to 56F8300 56F8100 Porting User Guide 56F8300 16 bit Digital Signal Controllers 0100 AO O Rev 0 12 2004 freescale com 2 freescale semiconductor Document Revision History Version History Description of Change Rev 0 Initial Public Release 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Section 1 Introduction 1 1 Overview Unless otherwise noted the term 56F8300 56F8100 refers to the 56F834x 56F8 14x 56F835x 56F8 15x and 56F836x S56F816x devices only There are several perspectives to take when considering issues which arise when porting code from the 56F807 to any of the 56F8300 56F8100 devices These are Changes in core architecture from 56800 to 56800E family Differences between the 56F807 and 56F8300 56F8100 chip architectures Assembler differences from the 56800 to 56800E family In Line Assembler differences from the 56800 to 56800E family C compiler differences from the 56800 to 56800E family eS o The first item is discussed in detail in 13 References That document complements this one Items 3 through 5 are the subject of separate documents but will be touched on in this document The emphasis of this manual is item 2 The 56F8300 56F8100 families consist of a number of devices Only the devices shown in Table 1 1 will be discussed in this manual The devices listed have identical peripheral implementations and therefore differ
14. 56F8300 S56F8100 devices Interrupt Priority Registers are different but similar to the 56F807 Group Priority Registers Please consult the 56F8300 56F8100 documentation for details In the 56800E family the process for enabling interrupts 1s Clear any outstanding peripheral interrupt status bits peripheral specific Enable interrupts of interest in individual peripheral register sets Enable and assign priorities to interrupts of interest in the appropriate interrupt priority register IPRx in the ITCN module Note that a number of interrupt sources previously hardcoded on the 56F807 must be programmed into the 56F8300 S56F8100 IPRx registers These include IRQA IRQB and some of the EOnCE interrupts A detailed mapping is shown in Table 6 13 See the Interrupt Vector Table Contents section of the 56F8300 56F8100 Data Sheet for additional information Enable interrupts and set IRQA or IRQB to level sensitive or edge sensitive choices in the ICTL Select any two interrupt sources as fast interrupts and assign their ISR location using the ITCN Fast Interrupt Match and Fast Interrupt Vector Address registers Make sure these interrupts are programmed as Level 2 interrupts Enable interrupts in the Status Register SR Fast interrupts are not available on the 56F80x devices and represent a major enhancement in 56F8300 S56F8100 devices 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 21 Preliminary This r
15. 807 to 56F8300 56F8100 Porting Guide Rev 0 28 Freescale Semiconductor Preliminary Table 6 16 56F8300 56F8100 GPIO Assignments 56F 834x 56F 835x 56F807 Peripheral GPIO Function 56F836x Funcion Peripheral Function Cw w Jew ooo o COCs w ew o o o Cw w er ooo Ca m Jex ooo Ce e oew ooo Cw w oew ooo E a a m E 56F834x 56F835x 56F836x Boot determined man from EXTBOOT amp EMI_ MODE pin values during Function A17 preet T HT 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 29 Preliminary Table 6 16 56F8300 56F8100 GPIO Assignments Continued 56F 807 Peripheral Function Not Applicable Was previously Timer B without GPIO Not Defined No Alternate Function TXD1 RXD1 Not Defined TXDO 56F834x 56F835x GPIO 56F836x Function Peripheral Function There was no GPIO c port on DSP56F807 GPIODO These pins were dedicated GPIO on 56F807 On 56F8300 56F8100 GPIO is active upon exiting reset to retain compatibility with 56F 807 CS6 GPIOD4 CS7 GPIOD5 TXD1 GPIOD6 RXD1 GPIOD7 PS CS0 GPIOD8 DS CS1 GPIOD9 ISBO GPIOD10 ISB1 GPIOD11 ISB2 GPIOD12 TXDO GPIOEO 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Table 6 16 56F8300 56F8100 GPIO Assignments Continued 56F 834x eee 56F835x Peripheral aid Function Function 56F836x Peripheral Function GPIOE1 GPIOE2
16. CO OO LO 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary 23 Table 6 13 56F807 GPR to 56F834x 56F835x IPR Mapping Continued 56F807 ISR Vector 56F834x 56F835x Peripheral 56F807 GPR Interrupt Function IPR Number Timer C Timer C Channel 0 GPR8 10 8 IPR6 15 14 Timer D Timer D Channel 3 GPR8 6 4 IPR6 13 12 Timer D Timer D Channel 1 GPR7 14 12 IPR6 9 8 Timer D Timer D Channel 0 GPR7 10 8 IPR6 7 6 Quad Quad Decoder 0 INDEX Pulse GPR7 6 4 IPR6 3 2 Decoder 0 Decoder 0 Watchdog Decoder 1 Decoder 1 Watchdog GPR6I6 4 SPIO IPR4 15 14 SPI1 IPR4 11 10 SPI1 IPR4 13 12 7 Timer D Timer D Channel 2 GPR8 2 0 IPR6 1 1 10 SPI Pl S Program Flash Interface 2 GPR4 10 8 HFM interrupt priority levels are set using IPR2 15 10 MSCAN MSCAN Wakeup GPR4 6 4 FlexCAN WKUP IPR3 7 6 MSCAN MSCAN Error GPR4 2 0 FlexCAN Error IPR3 5 4 MSCAN MSCAN Receiver Full GPR3 14 12 FlexCAN MSG BUF IPR3 9 8 MSCAN MSCAN Transmitter Ready GPR3 10 8 FlexCAN Bus Off IPR3 3 2 O N Ql 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Table 6 13 56F807 GPR to 56F834x 56F835x IPR Mapping Continued 56F807 ISR Vector Peripheral Interrupt Function 56F807 GPR mara a 835x Number DFIU Data Flash Interface GPR93 6 4 HFM interrupt priority levels are set using 12 PFIU1 Program Flas
17. ISR Vector Peripheral Interrupt Function 56F807 GPR SBR DOP SSOX Number ss Low Voltage Interrupts GPR15 14 12 IPR2 7 6 PLL Interrupts GPR15 10 8 IPR2 9 8 PWM A PWM A Fault GPR15 6 4 IPR9 15 14 PWM B PWM B Fault GPR15 2 0 IPR9 13 12 PWM A Reload PWM A GPR14 14 12 IPR9 11 10 PWM B Reload PWM B GPR14 10 8 IPR9 9 8 ADC A ADC A Zero Crossing or Limit Error GPR14 6 4 IPR9 7 6 ADC B GPR14 2 0 IPR9 5 4 ADC A GPR13 14 12 IPR9 3 2 ADC B GPR13 10 8 IPR9 1 0 SCI 0 GPR13 6 4 IPR8 15 14 SCI 0 GPR13 2 0 IPR8 13 12 SCI 0 GPR12 14 12 IPR8 9 8 SCI 0 GPR12 10 8 IPR8 7 6 SCI 1 GPR12 6 4 IPR5 11 10 SCI 1 GPR12 2 0 IPR5 9 8 SCI 1 GPR12 14 12 IPR5 5 4 SCI 1 GPR11 10 8 IPR5 3 2 Timer A GPR11 6 4 IPR8 5 4 Timer A GPR11 2 0 IPR8 3 2 Timer A GPR10 14 12 IPR8 1 0 Timer A Timer A Channel 0 GPR10 10 8 IPR7 15 14 Timer B Timer B Channel 3 GPR10 6 4 IPR7 13 12 Timer B Timer B Channel 2 GPR10 2 0 IPR7 11 10 Timer B Channel 1 GPR9 14 12 IPR7 9 8 ADC B Zero Crossing or Limit Error ADC A Conversion Complete ADC B Conversion Complete SCI 0 Receiver Full SCI 0 Receiver Error SCI 0 Transmitter Ready SCI 0 Transmitter Complete SCI 1 Receiver Full SCI 1 Receiver Error SCI 1 Transmitter Ready SCI 1 Transmitter Complete Timer A Channel 3 Timer A Channel 2 Timer A Channel 1 HR l l l AI AIAI RT RT l OI OT OT OT Oy oy oy oy oe GQ DM oOo Ia Os N O O O 4 NMI ws HRI as ODI N
18. Mode is enabled EXTBOOT Mode 1 cannot be used See Security Features Part 7 of the device Data Sheet 1 2 This mode provides maximum compatibility with 56F80x parts while operating externally 3 EMI MODE 0 EMI_MODE pin is tied to ground at boot up 4 EMI MODE 1 EMI_MODE pin is tied to Vpp at boot up 5 Not accessible in reset configuration since the address is above P 0x00 FFFF The higher bit address GPIO and or chip selects pins must be reconfigured before this external memory is accessible 6 Booting from this external address allows prototyping of the internal Boot Flash 7 The internal Program Flash is relocated in this mode making it accessible 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Table 6 4 Program Memory Map for 56F835x at Reset Mode 0 MA 0 Mode 11 MA 1 Begin End Internal Boot External Boot Address Internal Boot EMI MODE 02 2 EMI_MODE 14 16 Bit External Address Bus 16 Bit External Address Bus 20 Bit External Address Bus P 1F FFFF External Program Memory External Program Memory External Program Memory P 10 0000 P 0F FFFF External Program Memory P 03 0000 COP Reset Address 02 0002 ee 6 P 02 FFFF On Chip Program RAM Boot Location 02 0000 P 02 F800 4KB P 02 F7FF P 02 2000 P 02 1FFF Boot Flash Boot Flash P 02 0000 16KB 16KB COP Reset Address 02 0002 Not Used for Boot in this Mode Boot Location
19. available on the 83x5 and 81x5 parts since most of the required pins are not bonded out in the pack 6 4 1 EOnCE The 56800E core contains an Enhanced OnCE port EOnCE which offers an improved feature set over that used in the 56800 core A discussion of the differences is beyond the scope of this document see 11 References for details about the EOnCE 56F807 to 56F8300 56F8100 Porting Guide Rev 0 k 6 Freescale Semiconductor Preliminary 6 4 2 Peripheral Memory Map On chip peripheral registers are part of the Data memory map for both 56F807 and 56F8300 S56F8100 devices These locations may be accessed with the same addressing modes used for ordinary Data memory except that most peripheral registers should be read written using word accesses only Table 6 8 illustrates the memory mapped peripheral registers The register set for a given peripheral is relatively stable from one member of the 5680x and 56F8xxx families to another however the address of that register set may vary in order to accommodate changes in memory configurations Programmers are encouraged to code their drivers in terms of a peripheral base address plus offset for each register The offset will normally be identical across members of the family while the base addresses will move Exceptions to this will be noted in the sections which follow Peripherals are listed in alphabetical order in Table 6 8 Variances in peripheral implementation between 56F807 and
20. both 56F807 and 56F8300 56F8100 parts There are a number of errata present in the 56F807 implementation of the SPI These have been corrected in the 56F8300 S56F8100 devices 6 5 12 Quad Timer The 56F8300 S6F8100 families use the same timer module as the 56F807 all register definitions from the 56F807 remain unchanged In the 56F8300 S56F8100 families the timer has been enhanced with the addition of the Compare Preload Registers CMPLD1 and CMPLD2 and the associated Compare Status and Control Register COMSCR These new registers ease the software timing constraints associated with CMP land CMP2 register updates Because the IPBus clock frequency is 50 faster in 56F8300 devices relative to the 56F807 device timer register values must be adjusted to account for the change The 56F807 offers four Timers A through D The 56F8300 devices have muxed Timer B DEC 1 with a second SPI If the SPI is used the timer cannot be referenced externally The 56F8100 has only Timer A 6 5 13 Quadrature Decoder This is the same module used on the 56F807 The 56F807 has two Quadrature Decoders one of which is associated with Timer B The 56F8300 56F8100 devices have muxed Timer B DEC 1 with a second SPI If the SPI is used DEC 1 cannot be used 6 5 14 PWM Module This is based upon the 56F807 PWM module but some enhancements have been made for swapping and masking functions The Debug Wait mode operation has been modified and the dead time reg
21. cillator crystal has been damaged This register was not present on 56F807 device 6 5 3 COP 6 5 3 1 COP Control Register COPCTL The 56F8300 56F8100 devices add an extra bit to the COPCTL register to allow the COP to utilize the peripheral clock instead of the oscillator clock as its time base This is intended for factory test use only The default value of this bit yields operation equivalent to the 56F807 6 5 3 2 COP Time Out Register The clock prescaler has been changed from 16384 to 1024 To compensate the time out field CT in 56F807 TIMEOUT in 56F8300 S6F8100 devices has been extended from 12 bits in the 56F807 to 16 bits in 56F8300 56F8100 devices The default value has changed from OxOFFF to OxFFFF In the 56F807 the default time out period assuming 40MHZz is 16384 X OxXFFF 1 40E6 1 67 seconds On the 56F8300 devices the default time out period assuming 60MHz is 1024 X OxXFFFF 1 60E6 1 12 seconds 6 5 3 3 COP Service Register COPSRV COP Counter Register COPCTR In the 56F807 COPSRV always reads as all zeros In the 56F8300 devices it has been renamed COPCTR and yields the current value of the COP counter 6 5 4 GPIO GPIO Ports C and F are new for 56F8300 56F8100 devices On the 56F834x 56F835x and 56F836x the size of all ports except Port B has been increased to allow for more GPIO capability 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 27 Preliminary
22. de Rev 0 oO Freescale Semiconductor 1 Preliminary Table 6 6 Interrupt Vector Table Contents Continued Vector Base 56F807 56F834x 56F835x 56F836x Vector Number Address Peripheral Interrupt Function Peripheral SPI 1 SPI 1 Interrupt Function SPI 1 Receiver Full SPI 1 Transmitter Empty Timer B i Timer B Channel 2 SPI 0 SPI 0 Receiver Full i Timer B Channel 3 SPI O SPI 0 Transmitter Empty 47 P 5E SCI 1 SCI 1 Transmitter Ready DEC 1 Quadrature Decoder 1 Home Switch or Watchdog 48 P 60 SCI 1 SCI 1 Receiver Error DEC1 Quadrature Decoder 1 INDEX Pulse 49 P 62 SCI 1 SCI 1 Receiver Full DECO Quadrature Decoder 0 Home Switch or Watchdog P 64 SCI 0 SCI 0 Transmitter Complete DECO Quadrature Decoder 0 INDEX Pulse 56 P 70 ADC B ADC B Zero Crossing or Limit Timer C Timer C Channel 0 Error P 72 ADC A ADC A Zero Crossing or Limit Timer C Channel 1 Error P 74 PWM B Reload PWM B Timer C Channel 2 P 76 PWM A Reload PWM A Timer C Channel 3 80 P 78 PWM B PWM B Fault Timer B Channel 0 61 P 7A PWM A PWM A Fault Timer B Timer B Channel 1 P 7C LL PLL Interrupts P 7E LVI Low Voltage Interrupts P 80 P 82 P 84 P 86 Timer B Channel 0 Timer B Channel 1 JERE 51 5 55 D D D a H a WU W WU 38 39 40 41 62 63 64 65 Timer B Channel 2 Timer B Channel 3 Timer A Channel 0 Timer A Channel 1 Timer A Channel 2 Timer A Channel 3 Timer B F Timer B Ti
23. devices than in the 56F807 are shown in blue memory sizes smaller in the 56F83xx devices than in the 56F807 are shown in red These larger memory sizes significantly affected organization of the 56F8300 memory map Subsequent sections will detail the changes Table 6 1 Memory Configurations On Chip Memory 56F807 56F834x 56F835x 56F836x Data Fish FLASH aKx1 ae aK T TOK TS Program RAM PRAM 2K x 16 2K x 16 2K x 16 2K x 16 Data RAM XRAM 4K x 16 2K x 32 4K x 32 8K x 32 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 7 Preliminary 6 3 Program Memory 6 3 1 Program Memory Map Table 6 2 Table 6 3 Table 6 4 and Table 6 5 define the Program memory maps for 56F807 S56F834x S56F835x and 56F836x respectively The larger on chip Program memories for 56F834x 56F835x and 56F836x resulted in a different set of trade offs in the area of memory maps however each chip offers both boot from internal Flash and boot from external Program RAM modes of operation The 56F834x 56F835x 56F836x External Memory Interface EMI is easily configured Seventeen of the 21 address lines are brought off chip on the 56F83x6 56F81x6 parts with four chip select lines providing additional addressing capability over that of the 56F807 With the 56F83x7 56F81x7 parts all 21 address lines are available with eight chip select lines A 56F807 compatible external boot mode is available EXTBOOT 1 EMI MODE 0 For additio
24. e PIN True Asserted Vio PIN False Deasserted ViH VoH PIN True Asserted ViH VoH PIN False Deasserted ViL VoL 1 Values for VIL VOL VIH and VOH are defined by individual product specifications 1 3 References 1 DSP56F800 User Manual DSP56F801 7UM Freescale Semiconductor Inc 2 56F8345 56F8145 Data Sheet MC56F8345 Freescale Semiconductor Inc 3 56F8346 56F amp 146 Data Sheet MC56F8346 Freescale Semiconductor Inc 4 56F8347 56F amp 147 Data Sheet MC56F8347 Freescale Semiconductor Inc 6 56F8356 56F8156 Data Sheet MC56F8356 Freescale Semiconductor Inc 7 56F8357 56F8157 Data Sheet MC56F8357 Freescale Semiconductor Inc 8 56F8365 56F amp 165 Data Sheet MC56F8365 Freescale Semiconductor Inc 5 56F8355 56F 8155 Data Sheet MCS56F8355 Freescale Semiconductor Inc 19 1 56F8366 56F amp 166 Data Sheet MC56F8366 Freescale Semiconductor Inc 10 56F 8367 56F amp 167 Data Sheet MC56F8367 Freescale Semiconductor Inc 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary 11 DSP56800E 16 Bit Digital Signal Processor Core Reference Manual DSP56800ERM D Freescale Semiconductor Inc 12 5678300 Peripheral User Manual MC56F8300UM Freescale Semiconductor Inc 13 Porting and Optimizing 56800 Applicatons to 56800E Freescale Semiconductor Inc Section 2 Code Growth amp Execution Speed Code growth and execution speed chan
25. ection of the map allocated to Core Registers in the 56F807 has been merged into the EOnCE and On Chip Peripherals section of the 56F834x 56F835x and 56F836x maps Also the amounts allocated to Flash and dual ported data RAM have been adjusted 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 15 Preliminary Table 6 7 Data Memory Map for 56F807 and 56F834x 56F835x 56F836x SS 56F807 56F834x 56F835x1 56F836x1 EX 0 EX 1 EX 0 EX 1 EX 0 EX 1 EX 0 EX 1 Address FF FFFF EOnCE EOnCE EOnCE FF FFOO 256 locations allocated 256 locations allocated 256 locations allocated NOT APPLICABLE FF FEFF External External External External External External 01 0000 Memory Memory Memory Memory Memory Memory 00 FFFF Core Registers 00 FF80 128 On Chip Peripherals On Chip Peripherals On Chip Peripherals 00 FE7F 4096 locations allocated 4096 locations allocated 4096 locations allocated 00 F000 00 EFFF External 00 8000 Memory External Memory External eee 00 4000 Memory 16K X16 External 00 3FFF Memory 00 3000 External On Chip Data Flash veut On Chip Data 00 2FFF 8K X16 64K 128 External G External External 00 2000 X 16 Memory AK X16 Memory Memory On Chip Data 00 1FFF 00 1800 Reserved On Chip Data RAM Flash 8K X 32 00 17FF On Chip 4K X16 00 1000 Peripherals On Chip Data RAM On Chip Data On Chip Data si 00 OF FF 00 0000 RAM RAM 4K X 16 2K X 32 1 age External memory access is not
26. egister is not present in the 56F8300 56F8100 devices Instead see the ICTL Figure 6 2 56F807 Interrupt Priority Register 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 eo er oajoelon oe ool PT em mo aw as x0 aw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved IRQA IRQB Trigger Mode The I 1 0 field is still present on 56F8300 56F8100 devices but all values are now in use See Table 6 12 for details 56F807 Status Register A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Px Unimplemented or Reserved on the 56800 only used on 56800E Exceptions Permitted Exceptions Masked The 56F807 Group Priority Registers La are not shown Their function has been o o Resev Reseno o w assumed by the 56F8300 56F8100 oa aren YR fesen ped Table 6 13 for mapping from one to the other Figure 6 1 Interrupt Related Registers for 56F807 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Oe TaD TS Swe DIS STATE STATE EDG EDG v a a ee ee ee ee ee E Ee e RESET 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 Reserved or unused Figure 6 2 56F834x 56F835x 56F836x Interrupt Control ICTL Register 56F807 to 56F8300 56F8100 Porting Guide Rev 0 22 Freescale Semiconductor Preliminary Table 6 12 56F800E Interrupt Mask Bit Settings H to Exceptions Permitted Exceptions Masked o 0 IPL01 2 3 LP None o p ens o p fees feo Table 6 13 56F807 GPR to 56F834x 56F835x IPR Mapping 56F807
27. eration with a 180ns device The reset value of the BCR has changed since the register fields have been redefined The BCR no longer distinguishes between Program and Data space accesses since without a CS there is no external indication of which memory space is being referenced As shown in Figure 6 5 the DRY bit has also moved from bit location 9 to bit location 15 It is recommended that the DRV bit be set to 1 except in situations in which multiple processors with similar bus interfaces share a common external memory interface 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 35 Preliminary 56F807 Bus Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 o O O O O DRV 0 Wait State Field for External X Wait State Field for External P Se 9 Memory Memory RESET 0 0 0 0 0 1 56F8300 56F8100 Bus Control Register 1 0 R pmpar z0 BWWSI4 0 S 4 0 E a RESET 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 Unimplemented or Reserved Figure 6 5 Bus Control Register Mapping The 56F8300 56F8100 device s EMI module is signficantly more advanced than the EMI found on the 56F807 device Depending on the package there are eight chip selects available which may be programmed in numerous ways On 56F8300 56F8100 CSO and CS1 are programmed to emulate the 56F807 PS and DS data strobes at reset If the EMI MODE pin is set to 0 and EXBOOT is set to 1 at reset then the 56F83
28. for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part e 7 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2004 All rights reserved 8300PUG Rev 0 12 200
29. ges between 56800 and 56800E compilers is dependent upon the actual code being generated and executed The following are typical numbers e 5 code size increase in ASM based on a V 22bis algorithm study e 25 decease in generated object code from C compiler e 13 improvement in C execution speed Section 3 C Code Differences The C compilers themselves are mostly code compatible Once headers and functions have been adjusted as described in this manual most C code should port directly There are some known issues detailed in the following outline Applications which use Processor Expert PE will have much of this effort taken care of automatically Among the known issues e char and void are byte addresses not word addresses Restricted to 0 32KW address range in small data memory model May cause conversion problems to from word addresses e Data sizes and alignment bit data may cause structure sizes to change 32 bit data must be even word aligned Function pointers are two words in large program memory model e C parameter passing conventions Extended changed to take advantage of additional 56800E registers Non volatile registers are present C D R5 e Stack alignment Top of stack must be odd word aligned at all times 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 5 Preliminary e Peripheral register access The 56F8300 56F8100 peripheral registers a
30. h Interface 1 GPR3 2 0 IPR2 15 10 BFIU Boot Flash Interface GPR2 14 12 core Tn Herdwied IPR core Ina Hardwired iPro core OnCE Trap Hardwired IPRO 13 10 amp IPR1 5 0 56F836x IPR mapping is different due to the addition of a second FlexCAN peripheral 1 2 The MSCAN Error interrupt is generated when any of the following MSCAN interrupt sources is asserted Overrun Receiver Warning Transmitter Warning Receiver Error Passive Transmitter Error Passive and Bus Off 6 5 2 Clock Generation Registers whose function remains unchanged include PLLCR 6 5 2 1 PLL Divide By Register The default value of the PLLDB field has changed from 0x10011 19 to 0x11101 29 The 56F8300 PLL runs at 4x the system speed therefore this translates to changing the instruction rate from 40MIPS to 60MIPS 6 5 2 2 PLL Status Register The interrupt bits have been modified so that they cannot be set unless enabled Previously the LOCI bit could be and often was triggered whenever the PLL was reprogrammed regardless of whether it was enabled or not This has been improved in the 56F8300 S56F8100 devices LOCI can be cleared by writing a one to it or by disabling the interrupt in the PLLCR 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary 25 6 5 2 3 Clock Out Select Register The Clock Out Select Register has been moved from the Clock Generation Module to the System Integration Module Bit 4 of
31. hese are reset only upon power up 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 43 Preliminary 6 5 17 Operating Mode Register The MA bit continues to reflect the state of the EXTBOOT pin upon exiting reset The MB bit shows the secured state of the Flash when the device was reset 56F807 to 56F8300 56F8100 Porting Guide Rev 0 44 Freescale Semiconductor Preliminary Freescale Semiconductor Preliminary 56F807 to 56F8300 56F8100 Porting Guide Rev 0 45 46 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary Freescale Semiconductor Preliminary 56F807 to 56F8300 56F8100 Porting Guide Rev 0 47 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacif
32. ic Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated
33. ighest Illegal Instruction HWS overflow SWI Enhanced OnCE interrupts misaligned data acess Maskable a On chip peripherals IRQA and IRQB SWI 2 instruction Enhanced OnCE interrupts U Maskable a On chip peripherals IRQA and IRQB SWI 1 instruction Enhanced OnCE interrupts 0 Maskable On chip peripherals IRQA and iRQB SWI 0 instruction On chip peripherals IRQA and IRQB SWI 0 instruction LP Maskable SWILP Instruction Column four in Table 6 11 represents one possible way of allocating interrupt sources to interrupt levels In fact the 56F8300 56F8100 devices interrupt controller allows more flexibility in assigning core and EOnCE interrupts to specific levels Recall that in the 56800 family the process for enabling interrupts 19 e Clear any outstanding peripheral interrupt status bits peripheral specific e Enable interrupts of interest in individual peripheral register sets 56F807 to 56F8300 56F8100 Porting Guide Rev 0 20 Freescale Semiconductor Preliminary Enable and assign priorities to interrupts of interest in the appropriate Group Priority Register GPR in the ITCN module Enable interrupts and set IRQA and IRQB to level sensitive or edge sensitive in the Interrupt Priority Register IPR Enable interrupts in the Status Register SR As discussed in Section 6 3 3 the interrupt table has been rearranged This plus the availablity of only five priority levels means that the organization of the
34. ions The following line of code is acceptable for 56800 or S6800E compilers MOVE R3 X C000 R3 is an available register on both 56800 and S6800E There is no conflict in this situation and the code should compile without problems Section 5 In Line Assembler Differences The current version of CodeWarrior s 56800E C compiler supports the inline S6800E assembler The inline 56800 assembler must be converted to 56800E syntax and semantics 56F807 to 56F8300 56F8100 Porting Guide Rev 0 6 Freescale Semiconductor Preliminary Section 6 Issues Resulting from Chip Architectures 6 1 Higher Clock Speeds The top peripheral clock speed on the 56F807 is 40MHz On the 56F8300 devices it is 60MHz Unless the system clock is slowed to 40MHz the values of clock prescalars in serial interface routines for SPI SCI and CAN will have to be changed in order to preserve the frequency of serial bit streams This is handled automatically when utilizing Processor Expert It will be necessary to adjust timer prescalers and or values for the on board Quad Timers PWM modulus and counter values will also require adjustment 6 2 Effects of Different Memory Sizes On chip memory sizes for each device are summarized in Table 6 1 Except for Data Flash 56F8300 memory sizes meet or exceed 56F807 sizes in all cases The 56F8100 family of devices have the same memory sizes except there is no Program RAM or Data Flash Memory sizes larger in the 56F83xx
35. ister PMDEADTM has been increased from 8 to 12 bits Registers which map directly between implementations are PMCTL PMFCTL PMFSA PMOUT PWMCM PWMVALO 5 PMDISMAPI 2 and PMPORT 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 39 Preliminary Bit 13 of the PWM Configure Register PMCFG was reserved in the 56F807 On 56F8300 S56F8100 devices itis WAIT EN which can be used to enable disable PWM operation during Wait mode Bit 14 of the same register previously reserved on the 56F807 is now DBG EN This bit enable disable PWM operation during Debug mode Both WAIT EN and DBG EN default to zero PWM disabled in these modes which is considered the most conservative setting Bit 15 of the PWM Channel Control Register PMCCR has been changed from RESERVED on the 56F807 to the nBX bit on the 56F8300 56F8100 devices It enables an alternate circuit configuration for mask amp swap operations The default value of zero provides operation consistent with the 56F807 A new register the PWM Internal Correction Control Register PMICCR was added on the 56F8300 56F8100 devices This register allows for better control of dead time correction See the PWM section in the 56F8300 Peripheral User Manual for details of the changes outlined in this section 6 5 15 Flash Interface Unit This is anew module in the 56F8300 56F8100 families It is NOT upward compatible from the 56F807 6 5 16 System Integration Function
36. it services both duals This has no effect on software executing on the device The DIV field in ADC Control Register 2 ADCR2 has been increased from four to five bits and its reset value changed from 0111 to 00101 The later will yield a conversion rate of SMHz at a 60MHz system bus rate recommended The 56F8300 56F8100 devices add the ADC Power Control Register ADCPOWER This provides intelligent power savings features for the ADCs which are one of the most power hungry on chip features The reset value of this register is such that the ADCs are powered up upon reset consistent with operation in the 56F807 All other ADC registers map across unchanged from the 56F807 to the 56F8300 S6F8 100 devices To obtain better accuracy the 56F8300 56F8100 devices have also added the ADC CAL register to facilitate on the fly calibration of the ADC This register is not part of the 56F807 design When this register was added the two test bits in the ADSDIS register were removed 6 5 8 Internal Temperature Sensor The 56F8300 devices have added an internal temperature sensor module The voltage output of this module is bonded to the TEMP SENSE pin Wiring this pin to one of the analog inputs at the board level allows the ADC to monitor the IC s internal temperature 1 Accumulated error should be less than or equal to 0 5 PLL cycle plus any inaccuracies due to the crystal 56F807 to 56F8300 56F8100 Porting Guide Rev 0 34 Freescale Se
37. mer A Timer A Not Applicable Not Applicable Not Applicable DHS 212 2 2 gt gt 67 Not Applicable 56F807 to 56F8300 56F8100 Porting Guide Rev 0 IA Freescale Semiconductor Preliminary Table 6 6 Interrupt Vector Table Contents Continued piin Address Peripheral Peripheral P3904 Not Applicable cn P 96 Not Applicable ADC B ADC B Zero Crossing or Limit Error P 98 Not Applicable ADC A ADC A Zero Crossing or Limit Error psa nonpa fewe psec noraspieae fewa psoe norai fewe pesao norai E FlexCAN Bus Off FlexCAN Error 68 eo 70 mt 72 Bo a aa 78 3 B so e pm form oa 70 71 72 73 74 75 76 77 78 79 81 82 83 84 85 1 P A6 Not Applicable 89 P A8 Not Applicable FlexCAN Wake Up P AA Not Applicable FlexCAN Message Buffer Interrupt Two words are allocated for each entry in the vector table This does not allow the full address range to be referenced from the vector table providing only 19 bits of address 2 56F836x devices only unjoni Cl Mm T Mm r X XK K xX O 1O O O90 amp S we az Wh eee ee KM MR MO NM NO NO N N The 56F8300 56F8100 devices interrupt controller contains a Vector Base Address Register VBA which allows the ISR table excluding reset vectors to be allocated to any location in the memory map 6 4 Data Memory Table 6 7 contrasts the Data memory maps for 56F807 and 56F8300 56F8100 devices Note that the s
38. miconductor Preliminary 6 5 9 External Memory Interface In the 56F80x family which includes the 56F807 the user could control wait states for external data memory separately from external Program memory and could also control output drive characteristics of the port signals These controls were lumped into the Bus Control Register BCR which was located in the memory map section devoted to core configuration registers In the 56F8300 56F8100 the external memory interface has been completely redesigned and supports multiple Chip Selects CS Each CS can be configured as either Program space Data space or both Timing can be individually controlled for each CS This provides for optimal performance from the external memory interface Each CS can specify unique wait states for read and write access as well as setting set up and hold wait states if desired To accomplish this three registers are allocated for each CS defined The BCR register has been moved into the EMI module and is now used only to specify default timing if access is made to an area of the memory map not covered by a CS The fields for specifying wait states have increased from 4 to 5 bits The new set up and hold wait states fields are 2 bits each Also in the 56F807 wait states had to be an integer multiple of four That restriction has been removed on the 56F8300 56F8100 devices Note that the default number of wait states at reset has been changed to 11 which allows op
39. mlm 6 5 11 SPI In the SPI Status and Control Register SPSCR the SPR 1 0 field was increased to SPR 2 0 allowing more baud rate flexibility and the bits in the register were rearranged as shown in Figure 6 6 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary 56F807 SPI Status and Control Register SPSCR 15 14 13 12 1 56F8300 56F8100 SPI Statu PA fol Register SPSCR lt gt 9 da aa a i ERRIE MOD sprie cpHal se sfrie SPR OVRE W FEN Oo ee RESET O r r 0 0 0 0 r 0 r 0 0 0 0 0 Unimplemented or Reserved Figure 6 6 SPI Status and Control Register Mapping As shown in Table 6 19 the change to 60MHz for a top speed in 56F8300 devices makes it difficult to maintain consistent baud rates between the two devices Fortunately the SPI protocol is a synchronous one in which CLK is supplied with data Table 6 19 SPI Baud Rate Selection 56F834x 56F807 Baud 56F835x 56F834x 56F834x 56F807 56F835x 56F835x 56F807 Divisor Rate at 40MHz SPR 1 0 56F836x 56F836x S6F836x SPR 2 0 Divisor gaia 60MHz IPBus 56F807 to 56F8300 56F8100 Porting Guide Rev 0 38 Freescale Semiconductor Preliminary The SPI Data Size and Control Register SPDSR adds a Wired OR Mode bit in the 56F8300 56F8100 devices but is upwards compatible from the 56F807 The SPI Data Receive Register SPDRR and SPI Data Transmit Register SPDTR are identical on
40. nal details see the EMI chapter of the 56F8300 Peripheral User Manual Table 6 2 56F807 Program Memory Map Begin End Address Mode 0A Mode 0B FFFF Boot Flash Off Chip Program External Program F800 2K X 16 Memory Memory 32K X 16 64K X 16 F FF Program RAM FOOO 2K X 16 EFFF Program Flash 2 8000 28K X 16 7FFF Program Flash 1 Boot Flash 7800 32K 4 X 16 2K X 16 TEE Program RAM 7000 2K X 16 6FFF Program Flash 1 0004 28K 4 X 16 0003 Boot Flash 4X 16 56F807 to 56F8300 56F8100 Porting Guide Rev 0 8 Freescale Semiconductor Preliminary Table 6 3 Program Memory Map for 56F834x at Reset Mode 0 MA 0 Mode 11 MA 1 Begin End Internal Boot External Boot Address Internal Boot EMI_MODE 02 2 EMI_MODE 14 16 Bit External Address Bus 16 Bit External Address Bus 20 Bit External Address Bus eo FFFF External Program Memory External Program Memory External Program Memory P 310 0000 P 0F FFFF External Program RAM P 03 0000 COP Reset Address 02 0002 Aa 6 P 02 FFFF On Chip Program RAM Boot Location 02 0000 P 02 F800 4KB P 02 F7FF P 02 1000 P 02 OFFF Boot Flash Boot Flash P 02 0000 8KB 8KB COP Reset Address 02 0002 Not Used for Boot in this Mode Boot Location 02 0000 P 01 FFFF External Program RAM Internal Program Flash P 01 0000 128KB P 00 FFFF Internal Program Flash External Program RAM P 00 0000 128KB COP Reset Address 00 0002 Boot Location 00 0000 If Flash Security
41. on 04 00007 P 04 F800 4KB P 04 F7FF P 04 4000 P 04 3FFF Boot Flash Boot Flash P 04 0000 32KB 32KB COP Reset Address 04 0002 Not Used for Boot in this Mode Boot Location 04 0000 P 02 0000 256KB 256KB P 01 0000 256KB 128KB P 00 FFFF External Program Memory P 00 0000 COP Reset Address 00 0002 Boot Location 00 0000 If Flash Security Mode is enabled EXTBOOT Mode 1 cannot be used See Security Features Part 7 of the device Data Sheet This mode provides maximum compatibility with 56F80x parts while operating externally EMI_MODE 0 when EMI_MODE pin is tied to ground at boot up EMI_MODE 1 when EMI_MODE pin is tied to Vpp at boot up Not accessible in reset configuration since the address is above P 00 FFFF The higher bit address GPIO and or chip selects pins must be reconfigured before this external memory is accessible mO e e a 6 Not accessible in reset configuration since the address is above P 0F FFFF The higher bit address GPIO and or chip selects pins must be reconfigured before this external memory is accessible 7 Booting from this external address allows prototyping of the internal Boot Flash 8 Two independent program flash blocks allow one to be programmed erased while executing from another Each block must have its own mass erase 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor 11 Preliminary 6 3 2 Security Features The 56F8
42. re located at the top of the small memory address range to facilitate improved code accesses All references to the registers should be with word access instructions meaning the data must not be typed as bytes Section 4 Assembler Differences from 56800 to 56800E Code written for the 56F807 can be compiled and run on 56F8300 56F8100 devices with a few minor modifications 1 Any addresses pointing to memory mapped registers must be updated 2 Conditional branches for the 56800 series allowed only 6 bit branches the 56800E series allows 16 bit In the conversion from 56800 to 56800E the code between the branch source and destination grows If it grows enough the branch may require a 16 bit number instead of a 6 bit number resulting in a linking error which will require a manual modification to the code As long as the programmer only moves code from 56800 to 56800E these are the only modification that will be necessary In adjusting code for the 56800E series one must be sure not to try to access a 56800E only register with a 56800 only command For example the following piece of code will not work on S6800E MOVE R4 X C000 R4 is a register used only on 56800E MOVE is an instruction for 56800 where only word size moves are allowed The 56800E series allows byte word and long word moves This changes the available move instructions to MOVE B MOVE BP MOVE W and MOVE L One can not intermix 56800E registers with 56800 instruct
43. s The System Integration Module SIM contains much of the glue that ties any hybrid controller together The nature of the glue logic tends to be somewhat chip specific This implies that SIM registers tend to be non portable That said many of the 56F807 SIM features ARE present on 56F8300 56F8100 devices The mapping of SIM functions from the 56F807 to 56F8300 56F8100 is detailed in the following sections Note that COP functionality specified in the 56F807 SIM chapter was previously discussed in Section 6 5 3 Similarly power supervisor functions were discussed in Section 6 5 5 The memory maps for the 56F807 and 56F8300 56F8100 SIM modules are quite different as shown in Table 6 20 56F807 to 56F8300 56F8100 Porting Guide Rev 0 40 Freescale Semiconductor Preliminary Table 6 20 56F807 and 56F8300 56F8100 SIM Memory Maps se wrneee H mana SC S S aires a mana nana T H O ern meaa TH e rcs TT T IIT TH e T o O E a E anaa anaa T E 6 5 16 1 System Control Register Elements of the 56F807 SYS CN TL register map to the 56F8300 S56F8100 SIM Pullup Control Register and to the 56F8300 S56F8100 SIM Control Register The 56F807 has one time and reprogrammable controls for disabling Stop Wait functions The 56F8300 56F8100 have expanded on this by allowing separate controls for Stop and Wait individually Therefore the PD and RPD bits in the 56F807 map into four bits in the 56F8300 56F8100 devices Pull up enable
44. s additional granularity over that available in the 56F807 The first two locations in the vector table must reserve space for the reset branch or jmp statements All other entries must contain jsr statements Table 6 6 Interrupt Vector Table Contents C psa Revenes Oooo P 0A Hardware Stack Overflow Misaligned Long Word Access P 08 Software Interrupt SWI Haredware Stack Overflow P 0C OnCE Trap OnCE Step Counter 56F807 to 56F8300 56F8100 Porting Guide Rev 0 12 Freescale Semiconductor Preliminary Table 6 6 Interrupt Vector Table Contents Continued 56F807 56F834x 56F835x 56F836x Interrupt Function Peripheral C 19 P 26 P 26 GPIOE E GPIOE E Core si reserved s p 28 me D S D Low Voltage Detector Power Sense 21 f P 2Aa Reseved sReserved PLL oo l P 2C GPIO B GPIO B FM_ERR FM Error Interrupt 23 PS2E P 2E 0 GPIOA A GPIOA A FM FMcc FM FM Command Complete FM Command Complete S 30 a a Transmitter Empty FM P FM Command Data and Address Buffers Empty P 34 a Dec 1 Quad Decoder 1 Home Switch FFLEXCAN FlexCAN Bus Off or Watchdog a P 36 Quad Dec1 Quad Decoder 1 INDEX Pulse FLEXCAN FlexCAN Error 28 P 38 Quad Dec 0 Quad Decoder 0 Home Switch FFLEXCAN FlexCAN Wake up or Watchdog Vector Vector Base Number Address Peripheral P 0E Reserved P 10 Core IRQA IRQB OIOIOJIO O IOIOJO s s sa 35 0 IOD 100 l 0 56F807 to 56F8300 56F8100 Porting Gui
45. scale Semiconductor Preliminary Table 6 9 56F807 and 56F835x Interrupt Controller Memory Maps 10 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 56F807 to 56F8300 56F8100 Porting Guide Rev 0 Freescale Semiconductor Preliminary The 56800 core has two priority levels as described in Table 6 10 Additional 56800 hardware resources are shown in Figure 6 1 The 56800 Current Priority Level CPL I 1 0 in the SR indicates which interrupts are currently allowed If CPL 1 all interrupts are allowed if CPL 3 only non maskable interrupts are allowed The 56800 family supplements this mechanism with the CH 6 0 bits in the Interrupt Priority Register IPR These can be used to arbitrate which of several active maskable interrupts is to be asserted when CPL 1 Each on chip interrupt source can be assigned to one of seven priority levels using the group priority registers in the ITCN module The CH 6 0 bit values must be managed by software increasing interrupt latency Table 6 10 56800 Interrupt Priority Levels Non maskable Illegal Instruction OnCE trap HWS overflow SWI OO Maskable On chip peripherals IRQA and IRQB In contrast the S6800E core has five priority levels one is non maskable but no CH bits Once the interrupt assignments have been made the hardware can run itself with no additional software beyond the ISRs required Table 6 11 56800E Interrupt Priority Levels 3 Non maskable H
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