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TM8722 User`s Manual (V1.1) (*)

1. Instruction Machine Code Function Flag Remark NOP 0000 0000 0000 0000 No Operation LCT Lz Ry 0000 001Z ZZZZ YYYY Lz lt 7SEG lt Ry LCB Lz Ry 0000 0107 7777 YYYY Lz lt 7SEG lt Ry Blank Zero LCP Lz Ry 0000 0117 7777 YYYY Lz lt Ry AC LCD Lz HL 0000 100Z ZZZZ 0000 Lz lt R HL LCT Lz HL 0000 100Z ZZZZ 0001 Lz 7SEG LCB Lz HL 0000 100Z ZZZZ 0010 Lz lt 7SEG lt R HL Blank Zero LCP Lz HL 0000 100Z ZZZZ 0011 Lz lt R HL AC OPA Rx 0000 1010 OXXX XXXX IOA lt Rx OPAS RxD 0000 1011 DXXX XXXX IOA1 2 3 4 lt Rx 0 Rx 1 D Pulse 0000 1100 OXXX XXXX lt Rx 0000 1101 OXXX XXXX lt Rx FRQ D Rx 0001 0000 OXXX XXXX FREQ lt AC 0 00 1 4 D 01 1 3 Duty D 10 1 2 Duty D 11 1 1 Duty FRQ D HL 0001 0100 0000 0000 FREQ lt T HL FRQX DX 0001 10DD XXXX XXXX FREQ X MVL Rx 0001 1100 OXXX XXXX L Rx MVH Rx 0001 1101 OXXX XXXX H Rx AC ADC Rx 0010 0000 OXXX XXXX AC lt Rx CF CF HL 0010 0000 1000 0000 AC lt RGHL CF CF ADC Rx 0010 0001 OXXX XXXX AC lt CF HL 0010 0001 1000 0000 AC R HL R HL CF CF SBC Rx 0010 0010 OXXX XXXX AC lt Rx 5 HL 0010 0010 10
2. EL Plant 15 27 XIN CUPI ch 32 768KHz 15P Crystal m T XOUT VDD3 lom a E VDD2 T E VDDI f GARS Rr m RR INE Eo GNp N i TM8722 x AS 11 TN EP NE RESET External INT em NT m I O Port DIOAIOBI0C il Choke Buzzer BZ BZB A v q K1 16 KII KI Key Matrix Li power mode 1 3 Bias 1 5 Duty Key Scanning 11 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Chapter 2 TM8722 Internal System Architecture 2 1 Power Supply TM8722 could operate at Ag Li and EXTV 3 types supply voltage all of these operating types are defined by mask option The power supply also generated the necessary voltage level to drive the LCD panel with different bias Shown below are the connection diagrams for 1 2 bias 1 3 bias and no bias application 2 1 1 BATTERY POWER SUPPLY Operating voltage range 1 2V 1 8V For different LCD bias application the connection diagrams are shown below 2 1 1 1 NO LCD BIAS NEED AT Ag BATTERY POWER SUPPLY Application circuit J SB 848 B 5 8722 MASK OPTION table Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY LCD BIAS 3
3. Mask Option name Selected item Instruction ROM Table ROM memory space memory space Words Bytes INSTRUCTION ROM lt gt TABLE ROM 1 N21 128 3840 INSTRUCTION ROM lt gt TABLE ROM 2 N 2 256 3584 INSTRUCTION ROM lt gt TABLE ROM 3 N23 384 3328 INSTRUCTION ROM lt gt TABLE ROM 4 4 512 3072 INSTRUCTION ROM lt gt TABLE ROM 5 N 5 640 2816 INSTRUCTION ROM lt gt TABLE ROM 6 N 6 768 2560 INSTRUCTION ROM lt gt TABLE ROM 7 N 7 896 2304 INSTRUCTION ROM lt gt TABLE ROM 8 N 8 1024 2048 INSTRUCTION ROM TABLE ROM 9 N 9 1152 1792 INSTRUCTION ROM lt gt TABLE ROM N 10 1280 1536 INSTRUCTION ROM lt gt TABLE ROM N 11 1408 1280 INSTRUCTION ROM TABLE ROM C N 12 1536 1024 INSTRUCTION ROM lt gt TABLE ROM D N 13 1664 768 INSTRUCTION ROM TABLE ROM E N 14 1792 512 INSTRUCTION ROM lt gt TABLE ROM N 15 1920 256 INSTRUCTION ROM lt gt TABLE ROM 16 2048 0 27 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as the interrupt service routines such as reset address 000H interrupt 0 address 014H interrupt 1 address 018H interrupt 2 address 010H interrupt 3 address 01CH interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory
4. Output H Voh12f loh 1uA 1 2 2 2 V Voltage Voh3f lohz 1uA 4 3 SEG n 3 8 V Output L Vol12f lol 1uA 1 2 0 2 V Voltage Vol3f 101 10 3 0 2 V Output H Voh12g loh2 10uA 21 22 2 2 V Voltage Voh3g loh2 10uA 23 COM n 3 8 V Output M Vom12 lol n 10uA 1 2 1 0 1 4 V Voltage g COM n Vom3g lol n 10UA 3 1 8 2 2 V Output L Vol12g 101 100 1 2 0 2 V Voltage Vol3g lol 10uA 3 0 2 V 1 3 Bias display Mode Output H Voh12i lloh luA 1 2 3 4 V Voltage Voh3i lohz 1uA 3 5 8 V Output M1 Vom12illol n 10uA 1 2 1 0 1 4 V Voltage Vom13illol n 10uA 3 SEG n 1 8 2 2 V Output M2 Vom22illol n 10uA 1 2 2 2 2 6 V Voltage Vom23illol n 10uA 3 3 8 4 2 V Output L Vol12i 1 1 2 0 2 V Voltage Vol3i lolz1uA 43 0 2 V Output H Voh12j loh 10uA 1 2 3 4 V Voltage Voh3j lohz 10uA 23 5 8 V Output M1 Vom12jlll h 10uA 1 2 1 0 1 4 V Voltage Vom13jllol h 10uA 3 1 8 22 V Output M2 Vom22j lol h 10uA 1 2 2 2 26 V Voltage Vom23j llol h 10uA 3 3 8 4 2 V Output L Vol12j lol 10uA 1 2 0 2 V Voltage Vol3j 101 100 3 0 2 V 10 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 1 8 TYPICAL APPLICATION CIRCUIT This application circuit is simply an example and is not guaranteed to work LCD Panel COM1 5 SEG1 23
5. Address address 000h Initial reset 000H 010h Interrupt 2 014h Interrupt 0 018h Interrupt 1 zo 01Ch Interrupt 3 8 High Low 55 Nibble Nibble 020h Interrupt 4 0241 Interrupt 5 028 Interrupt 6 XFFH 8 Bits 128 N X 16 N N 1 16 N 1 16 l lt Instruction ROM PROM organization Table ROM TROM organization This figure shows the Organization of ROM 2 4 2 TABLE ROM TROM The table ROM is organized with 256 16 N x 8 bits that shared the memory space with instruction ROM as shown in the figure above This memory space stores the constant data or look up table for the usage of main program All of the table ROM addresses are specified by the index address register HL The data width could be 8 bits 256 16 N x 8 bits or 4 bits 512 16 N x 4 bits which depends on the different usage Refer to the explanation of instruction chapter 28 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 5 INDEX ADDRESS REGISTER HL This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and the contents of the register can be modified by executing MVH and MVL instructions Executed MVL instruction will load the content of specified data memory to the lower nibble of the index register L In the same manner executed MVH instructions may load the contents of
6. 1 32 768KHz Crystal Oscillator Large driver Large driver Voltage on BAK pin VDD2 VDD2 Internal operating voltage VDD2 VDD2 Note For power saving reason it is recommend to reset BCF flag to 0 when back up mode is not used 52 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Chapter 3 Control Function 3 1 INTERRUPT FUNCTION There are 7 interrupt resources 3 external interrupt factors and 4 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine specified by a fix address in the program memory ROM is called The following table shows the flag and service of each interrupt Table 3 5 Interrupt information Interrupt INT pin IOC port TMR1 Pre TMR2 Key underflow divider matrix counter overflow Scanning overflow ER pon poses Ki vector enable flag LN NN priorit Interrupt Interrupt Interrupt ms E BH Ed request 2 0 1 3 4 5 6 flag The following figure shows the Interrupt Control Circuit 53 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Specified signal change at IOC port Timer TM underflow Specified signal change at INT pin Predivider overflow 2 underflow Specified signal enable at Key matrix Scanning RFC counter overflow Interrupt 0 Priori
7. TM instruction IEF Q R C Initial reset B 2 Interrupt 6 bit binary down counter FREQ S 5 gt Q HRF4 SCF 9 6 R Halt release 13 Operand Data 4 X5 X0 Operand Data TM2 instruction 8 7 6 TM2 instruction Interrupt accept signal PLC 10h instruction Initial reset QL TENX Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 2 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TM2 or TM2X instruction Once the TMR2 counts down to 3Fh it stops counting then generates an underflow signal and the halt release request flag 4 HRF4 will be set to 1 When HRF4 1 and the TMR2 interrupt enabler IEF4 is set to 1 the interrupt occurred When HRF4 1 IEF4 0 and the TMR2 halt release enabler HEF4 is set to 1 program will escapes from halt mode if CPU is in halt mode and then HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 5794 After power on reset the default clock source of TMR2 is PH7 If watchdog reset occurred the clock source of TMR2 will still keep the previous selection The following table shows the definition of each bit in TMR2 instructions OPCODE Select clock TM2X X 2 0 AC
8. FOR KEY RESET 1 USE IOCA KI4 FOR KEY RESET 1 USE IOC or pins aren t used as key reset Mask Option name Selected item 1 FOR KEY RESET 2 NO USE 2 2 FOR KEY RESET 2 NO USE FOR KEY RESET 2 NO USE IOCA Kl4 FOR KEY RESET 2 NO USE 59 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The following figure shows the key reset organization 1 5o gt o IOC1 KH A Lucero enu JD s Key Scanning latch circuit K VDD hey reset IOCS KI3 Key Scanning latch circuit 3 2 A WATCHDOG RESET The timer is used to detect unexpected execution sequence caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider When the watchdog timer overflows it generates a reset signal to reset TM8722 and most of the functions in TM8722 will be initiated except for the watchdog timer which is still active flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watchdog timer organization 4 4 WDRS T to reset TM8712 detector Reset pin POR RF 10H During initial reset power on reset POR or reset pin the timer is inactive and the watchdog flag WDF is reset Instruction SF 10h wil
9. Switching pins for supply the LCD driving voltage to the VDD1 2 3 pins Connect the CUP1 and CUP2 pins with non polarized electrolytic capacitor when chip operated in 1 2 or 1 3 bias mode In no BIAS mode application leave these pins opened Time base counter frequency clock specified LCD alternating frequency Alarm signal frequency or system clock oscillation 32KHz Crystal oscillator In FAST mode connect an external resistor could compose the RC oscillator mask option SLOW mode connect an external resistor could compose the RC oscillator mask option COMi 5 Output pins for driving the common pins ofthe LCD or LED panel SEG1 35 Output pins for driving the LCD or LED panelsegment CX 1 input pin and 3 output pins for RFC application Muxed with SEG24 SEG27 RR RT RH ELC ELP O Output port for EL panel driver Muxed with SEG28 SEG29 BZB BZ Output port for alarm clock or single tone melody generator SEG30 SEG31 1 K16 O Output port for key matrix scanning Shared with SEG1 SEG16 Kli 4 port for key matrix scanning Muxed with SEG32 SEG35 GND P JNegative supply voltage 6 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 1 7 CHARACTERISTIC ABSOLOUTE MAXIMUM RATINGS GND 0V Name Symbol Range Unit VDD1 0 3 to 5 5 V Maximum Supply Voltage VDD2 0 3 to 5 5 V VDD
10. Rx lt Ry amp D D represents an immediate data The contents of Ry and D are binary ANDed the result is loaded to AC and working register Ry D 0H FH AC lt Ry 6 D D represents an immediate data The contents of Ry and D are exclusive OREd the result is loaded to AC D 0H T FH Rx lt Ry D represents an immediate data The contents of Ry and D are exclusive OREd the result is loaded to AC and working register Ry D 0H FH AC lt D D represents an immediate data The contents of Ry and D are binary OREd the result is loaded to AC D 0H FH AC lt D 116 tenx technology inc Rev 1 1 2003 11 25 description TM8722 User s Manual D represents an immediate data The contents of Ry and D are binary OREd the result is loaded to and working register Ry D FH 5 4 LOAD STORE INSTRUCTIONS STA Rx function description STA HL function description LDS function description LDA Rx function description LDA HL function description LDH Rx HL function description LDH Rx HL function description LDL Rx HL function description LDL Rx HL function Rx lt AC The content of AC is loaded to data memory specified by Rx R HL lt AC The content of AC is loaded to data memory specified by HL AC Rx lt D Immediate data D is loaded to the AC and data memory specif
11. SIE 20h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter IOC port and INT Interrupt caused by the Key matrix Scanning and interrupt service is concluded interrupt requests have been processed 56 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service address is executed automatically Refer to Table 3 1 In this case the CPU performs the following services automatically 1 As for the return address of the interrupt service routine the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and the interrupt enable flags are all reset When the interrupt occurs the TM8722 will follow the procedure below Instruction 1 In this instruction interrupt is accepted NOP 1M8722 stores the program counter data into the STACK At this time no instruction will be executed as with NOP instruction Instruction A The program jumps to the interrupt service routine Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted I
12. subroutine END 1 LDA 0 store underflow counter to AC JB3 1 if the TM2 underflow counter is equal to 8 exit this JMP RE LOAD RF2 1 disable the re load function gt TM2 1 E pi p B 7th Net count count count oa count count count count HRF4 PLG Re load DED TENX This figure shows the operating timing of TMR2 re load function for RFC 39 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start IEF0 Chattering prevention PLCO SIE LN output of IOC SEF4 SCF1 PLC th HRFO _ Interrupt 0 SCA 10h Initial reset Interrupt eer y Halt release request IEF1 SIE 2h Timer1 underflow HERES SCF5 i Interrupt 1 HEF1 SHE2h IEF2 Signal 4h p Interrupt 2 changed MM sar 7 on INT pin HEF2 SCF4 SHE 4h SE d Interrupt 3 Predivide HRF3 overflorw SCF7 HEF3 SHE 8h IEF4 SIE 10h Interrupt 4 Timer2 HRF4 underflow SCF6 HEF4 SHE 10h ES IEF5 SIE 20h Interrupt 5 Key Scanning HR
13. 3 Start condition flag 9 SCF9 SCF9 is set when a finish signal from mode 3 of RFC function causes the halt release request flag 6 HRF6 to be outputted and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the start condition flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 or the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X Bit 3 Bit 2 Bit 1 Bit 0 Start condition Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 Halt release Halt release Halt release caused by RFC caused by TMR2 caused by SKI counter finish underflow underflow Read only Read only Read only Read only 2 14 5 STATUS REGISTER 4 STS4 Status register 4 STS4 consists of 3 flags 1 System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generator SCG is used Executing SLOW instruction will change the clock source BCLK of the system clock generator SCG to the slow speed oscillator XT clock and the system clock selection flag CSF is reset to 0 Executing FAST instru
14. A high level signal comes from the OR ed output of the signals latch for 4 which causes the stop release flag of Key Scanning SKI to output and stop release enable flag 4 SRF7 is set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output and the stop release enable flag 5 SRF5 is set beforehand The following figure shows the organization of start condition flag 11 SCF 11 HRF2 gt Kis on scF11 Stop KIA release SRF7 request 1 2 CSR IOC4 SRF4 The stop release flags CSR HRF2 were specified by the stop release enable flags SRFx and these flags should be clear before the chip enters the stop mode All of the pins in IOC port had to be defined as the input mode and keep in 0 state before the chip enters the STOP mode or the program can not enter the STOP mode Instruction SRE is used to set or reset the stop release enable flags SRF4 5 7 The following table shows the stop release request flags The OR ed The OR ed input The rising or latched signals for mode pins of IOC falling edge on INT 1 4 Stop release request CSR HRF Stop release enable flag SRF7 98 44 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual 2 15 CONTROL REGISTER CTL The control register CTL comes in 4 types control register 1 CTL1 to control register 4
15. Bit 3 Bit 2 Bit 1 Bit 0 NA Start condition flag 2 Start condition Backup flag SCF2 flag 1 BCF SCF1 NA Halt release caused Halt release by SCF4 5 6 79 causedbythe Ne back up mode status IOC port Read only Read only Read only Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 Start condition flag 2 SCF2 When a factor other than port IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags in SCF4 5 6 7 9 is set to 1 SCF2 will also be set to 1 simultaneously When all of the flags in SCF4 5 6 7 9 are clear start condition flag 2 SCF2 is reset to 0 Note If start condition flag is set to 1 the program will not be able to enter halt mode Backup flag BCF This flag could be set reset by executing the SF 2h RF 2h instruction 41 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual 2 14 3 STATUS REGISTER 3 STS3 When the halt mode is released by start condition flag 2 SCF2 status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal change at the INT pin causes the halt release request flag 2 HRF2 t
16. Set value error 32768 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH9 The 9th stage output of the predivider PH15 The 15th stage output of the predivider 8 When the TMR1 clock is FREQ set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 12 2 RE LOAD OPERATION TMR1 provides the re load function which can extend any time interval greater than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again During this operation the program must use the halt release request flag or interrupt to check the wanted counting value It is necessary to execute the TMS or TMSX instruction to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the TMR1 will stop operating immediately after the re load function is disabled 34 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Fo
17. TM8722 User s Manual Duty Cycle FRQX D X function Frequency generator D X description Loads the data X X7 and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern of preset letter Programmi i i i i i i ng divider Note X0 X7 represents the data specified in operand X Preset Letter D Duty Cycle Di _ DO J 0 1 4 dut xr 0 x O 88 ty L 1 od 1 1 duty 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D HL The content of tables TOM specified by index address buffer as preset data N 3 FRQX D X The data of operand in the instruction assigned as preset data N TMS Rx function Select timer 1 clock source and preset timer 1 description The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction ____ Select clock Set ngvalue TMS 126 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The clock source option for timer 1 olof ge c LO 1 d43 TMS HL function Select timer 1 clock source and preset timer 1 description The content of table ROM specified by HL is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Selec
18. VDD Low active GND in 5 mE YEU Low active GND VDD COM4 in Low active GND VDD COM1 in high active GND VDD in high active GND VDD high active GND VDD COMA in high active GND segments AANA VDD COM 1 4 with unlighted sides GND segments on VDD COM with lighted sides GND 98 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual segments on lighted sides GND VDD VDD segments on COMS with ae y lighted sides GND VDD segments on COMA with e GND lighted sides n VDD segments on COM 2 with d J lighted sides L J O M L l 2 229v GND segments On p Ni B Be EJ EI LI LI u lighted sides L J L3 Ld Ld GND VDD segments on VDD COM1 4 with n lighted sides 1 j OC O x L GND segments on VDD COM2 3 with lighted sides GND segments on COM2 4 with lighted sides GND segments on COM3 4 with lighted sides GND segments on COM1 4 with lighted sides iii Display Turn Off COM1 2 3 4 in low active COM1 2 3 4 in high active All LED driver outputs VDD VDD GND 99 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual iv Stop mode m VDD COM1 2 3 4 M in low active GND VDD COM1 2 8 4 A S S LA SI I N LR Rh A A R Q 0 uu in high activ
19. 65 4257 tenx technology inc 1M 8722 4 Bit Micro Controller with LCD Driver User s Manual tenx technology inc tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual CONTENTS CHAPTER 1 General Description 3 1 1 General Description 3 1 2 uu 3 1 3 Block Diagram 4 1 4 Pad Diagram 5 1 5 Pad Coordinate RENNES Mx 5 6 JezGharacteri2atlgl s mm 7 1 8 Typical Application Circuitry nennen 11 CHAPTER 2 TM8722 Internal System Architecture 12 2 1 Power Supply E 12 2 2 System CGI dicen ttt aoa nde 19 2 3 Program Counter sseccbeivaneeantcntdentnabtanicautinntbestieeteestontgecbbantiasbieabeshoemtmael 26 2 4 Program Table Memory ROM a 27 2 5 Index Address Register HL ede den deer nennen 29 2 6 Stack Register STACK beers 29 2 7 Data Memory HAM 53 55 r1 BUR RERUM ro beide E RE Pe ege Ie apa Eo HR ERAS 30 2 8 Working Register WR 30 2 9 Accumulator AG T aa sanan 30 2 10 ALU Arithmetic and oeste parue 31 2 11 Hexadecimal Convert to Decimal 3
20. LCP Lz HL function LCD latch Lz lt R HL AC description The contents of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz SPA X function Defines the input output mode of each pin for IOA port and enables disables the pull low device description Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the pin was set as input mode The meaning of each bit of X X3 X2 X1 is shown below IOA2 as output mode IOA2 as input mode IOA1 as output mode IOA1 as input mode 104 tenx technology inc Rev 1 1 2003 11 25 function description OPAS Rx D function description Rx function description SPB X function description TM8722 User s Manual lt Rx The content of Rx is outputted to I OA port IOA1 2 lt Rx IOA3 D IOA4 lt pulse Content of Rx is outputted to IOA port D is outputted to IOA3 pulse is outputted to IOA4 D Oor1 Rx AC lt IOA The data of I OA port is loaded to AC and data memory Rx Defines the input output mode of each pin for port and enables disables the pull low device Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X3 X2 X1 is shown below Bit pattern Bit pattern Enable pull low Disable
21. SBC HL function description SBC Rx function description SBC HL function description ADD Rx function description ADD HL function description ADD function description TM8722 User s Manual The contents of data memory specified by QHL AC and CF are binary added the result is loaded to AC and data memory specified by HL Carry flag CF will be affected AC lt Rx The contents of AC and are binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected lt R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC Carry flag CF will be affected AC Rx AC B CF The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx Carry flag CF will be affected AC R HL lt R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by the result is loaded to AC and data memory specified by HL Carry flag CF will be affected lt Rx AC The contents of Rx and AC are binary added the result is loaded to AC Carry flag CF will be affected lt R HL AC contents of data memory specified by and binary added the result is loaded to AC Carry flag CF will be
22. VDD COM1 2 3 4 5 in low active VDD COM1 2 3 4 5 in high active GND VDD All LED driver outputs GND Figure 2 43 1 5 duty LED Waveform 102 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Chapter 5 Detail Explanation of TM8722 Instructions Before using the data memory it is necessary to initiate the content of data memory because the initial value is unknown The working registers are part of the data memory RAM and the relationship between them can be shown as follows The absolute address of working register Rx Ry 70H Note Ry Address of working register the range of addresses specified by Rx is from 00H to 7FH Rx Address of data memory the range of addresses specified by Ry is from to FH Address of working registers specified by Absolute address of data memory Rx lt NINN TI ITI 0 N O OHL is 8 bit index address buffer This buffer may address all data memory and table ROM The contents of the index address buffer may be specified by two instructions MVH and MVL MVH transfers the contents of data memory Rx to the higher nibble 4 bits and MVL to the lower nibble 4 bits The organization of the index address buffer HL is shown below Index Address Buffer Higher nibble OH Lower nibble L 7 0 L3 LO Transferred by MVH Transferred by MVL Lz represents the address of the latch of LCD PLA the add
23. 72 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual For ELP setting X8 X7 X6 UR X5 X4 Duty cycle 000 PH0 34duy BCLK 2 3 duty BCLK 2 BCLK 4 1 1 duty BCLK8 ELC setting X3 X2 0900 pulse Duty cycle requency DPH 00 hH 4duy The default setting after the initial reset is ELP PHO clock of pre divider and 3 4 duty cycle ELC 8 clock of pre divider and 1 4 duty cycle The timing of the duty cycle is shown below PHO PH8 1 4 duty 1 3 duty mur C C i 1 1 duty Example ELC 110h ELP outputs BCLK clock with 1 3 duty cycle and ELC outputs 8 clock with 1 4 duty cycle SF 4h Enables the light control signal LIT and turns on the EL light driver HF 4h Disables the light control signal and turns off the EL light driver 3 7 EXTERNAL INT PIN The INT pin can be selected as pull up or pull down or open type by mask option The signal change either rising edge or falling edge by mask option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted MASK OPTION table 73 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual For internal resistor type Mask Option name Selected item INT PIN INTERNAL
24. HALT Release Enable Flag ontent of generic Index address register Address of LCD PLA Latch Content of lowest nibble Index register STOP Release Enable Flag Content of middle nibble Index register Start Condition Flag Content of highest nibble Index register Address of Table ROM Clock Source of Chattering prevention ckt Clock Source of Frequency Generator High Nibble content of Table ROM Switch Enable Flag Low Nibble content of Table ROM Frequency Generator setting Value Timer Overflow Release Flag Clock Source Flag Clock Source of Timer Pre Divider Program Page RFC Overflow Flag Content of stack Resistor to Frequency counter Timer 1 Bit data of Resistor to Frequency counter Timer 2 135 tenx technology inc Rev 1 1 2003 11 25
25. HL 0010 1110 1000 0000 AC ELN OR AC Rx 0010 1111 XXXX AC lt Rx OR AC 131 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual Instruction Machine Code Function Flag Remark OR HL 0010 1111 1000 0000 AC R HL R HL OR AC Ry D 0011 0000 DDDD YYYY AC lt Ry D CF CF RyD 0011 0001 DDDD YYYY AC Ry lt Ry D CF CF SBCI Ry D 0011 0010 DDDD YYYY lt Ry DB CF SBCl RyD 0011 0011 DDDD YYYY Ry lt DB CF ADDI Ry D 0011 0100 DDDD YYYY AC lt Ry D ADD 0011 0101 DDDD lt D SUBI Ry D 0011 0110 DDDD YYYY AC lt Ry DB 1 CF SUB RyD 0011 0111 DDDD YYYY AC Ry lt DB 1 CF ADNI RyD 0011 1000 DDDD YYYY AC lt Ry D ADNI RyD 0011 1001 DDDD YYYY AC Ry lt Ry D ANDI Ry D 0011 1010 DDDD YYYY AC lt Ry AND D ANDI RyD 0011 1011 DDDD YYYY lt AND D EORI Ry D 0011 1100 DDDD YYYY AC lt Ry EOR D EOR RyD 0011 1101 DDDD YYYY lt Ry EOR D Ry D 0011 1110 DDDD YYYY AC lt Ry OR D ORI Ry D 0011 1111 DDDD YYYY AC Ry Ry ORD INC Rx 0100 0000 AO Rx lt 1
26. INC HL 0100 0000 1000 0000 AC R HL lt RGHL 1 CF Rx 0100 0001 XXXX AC Rx lt Rx 1 CF DEC HL 0100 0001 1000 0000 AC R HL lt R HL 1 CF IPA Rx 0100 0010 OXXX XXXX AC lt IOA IPB Rx 0100 0100 OXXX XXXX AC Rx lt IPC Rx 0100 0111 OXXX XXXX AC RX lt MAF Rx 0100 1010 OXXX XXXX AC STS1 B3 CF B2 ZERO B1 No use BO No use MSB Rx 0100 1011 OXXX XXXX AC STS2 B3 No use B2 SCF2 HRx 1 SCF1 CPT MSC Rx 0100 1100 OXXX XXXX AC lt STS3 B3 SCF7 PDV B2 PH15 B1 SCF5 TM1 BO SCF4 INT MCX Rx 0100 1101 OXXX XXXX AC Rx lt STS3X B3 SCF9 RFC B2 No use B1 SCF6 TM2 BO SCF8 SKI MSD Rx 0100 1110 OXXX XXXX AC Rx lt 5754 No use B2 RFOVF B1 BO CSF SRO Rx 0101 0000 OXXX XXXX AC n Rn 1 AC 3 0 SR1 Rx 0101 0001 OXXX XXXX Rn Rx n 1 AC 3 Rx 3 1 SLO Rx 0101 0010 OXXX XXXX RX n lt Rx n 1 0 Rx O 0 SL1 Rx 0101 0011 OXXX XXXX AC n Rn lt Rx n 1 AC 0 RX O 1 DAA 0101 0100 0000 0000 AC lt BCD AC CF DAA Rx 0101 0101 OXXX XXXX AC Rx lt BCD AC CF DAA HL 0101 0101 1000 0000 AC RGHL lt BCD AC DAS 0101 0110 0000 0000 AC BCD AC CF DAS Rx 0101 0111 OXXX XXXX AC Rx lt BCD AC CF 132 tenx technology inc Rev 1 1 2003 11 25 TM8722 User
27. L Voltage Vil2 0 7 0 7 Input H Voltage OSCIN at Ag Battery Mode 0 8xVDD1 VDD1 V Input L Voltage Vil3 0 0 2 001 V Input H Voltage Vih4 OSCIN at Li Battery Mode 0 8xVDD2 VDD2 V Input L Voltage Vil4 0 0 2 002 V Input H Voltage Vih5 CFIN at Li Battery or EXT V 0 8xVDD2 VDD2 V Input L Voltage Vil5 Mode 0 0 2 002 V Input H Voltage Vih6 RC Mode 0 8xVDDO VDDO V Input L Voltage Vil6 0 0 2xVDDO V Operating Freq Crystal Mode 32 KHZ Fopg2 RC Mode 10 1000 KHZ INTERNAL RC FREQUENCY RANGE Option Mode BAK Min Typ Max 250KHz 1 5V 200KHz 300KH 400KHz 3 0V 200KHz 250KHz 300KHz 500KHz 1 5V 450KHz 600KHz 750KHz 3 0V 400KHz 500KHz 600KHz tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual ELECTRICAL CHARACTERISTICS at 1 VDD1 1 2V Ag at 2 VDD2 2 4V Li at 3 VDD2 4V Ext V Input Resistance Name Symb Condition Min Max Unit L Level Hold Tr IOC Rilh1 Vi 0 2VDD1 1 10 40 100 Kohm Rilh2 Vi 0 2VDD2 2 10 40 100 Kohm Vi 0 2VDD2 3 5 20 50 Kohm IOA B C Pull Down Tr Rmad1 Vi VDD 1 1 200 500 1000 Kohm Rmad2 Vi VDD2 2 200 500 1000 Kohm Rmad3 Vi VDD2 3 100 250 500 Kohm INT Pull up Tr Rintu1 Vi VDD1 1 200 500 1000 Kohm Rintu2 Vi VDD2 2 200 500 1000 Kohm Rintu3 Vi VDD2 3 100 250 500 Kohm INT Pull Down Tr
28. L state and no stop release signal SRFn should be delivered The CPU will then enter the stop mode The following conditions cause the stop mode to be released One of the signals on the input mode pin of IOC port is in H state and holds long enough to cause the CPU to be released from halt mode A signal change in the INT pin The stop release condition specified by the SRE instruction is met INT pin is exclusive When the TM8722 is released from the stop mode the TM8722 enters the halt mode immediately and will process the halt release procedure If the H signal on the IOC port does not hold long enough to set the SCF1 once the signal on the IOC port returns to L the TM8722 will enter the stop mode immediately The backup flag BCF will be set to 1 automatically after the program enters the stop mode 50 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The following diagram shows the stop release procedure STOP HALT normal MODE STOP Yes released mode release Figure 3 16 The stop release state machine Before the stop instruction is executed the following operations must be completed Specify the stop release conditions by the SRE instruction Specify the halt release conditions corresponding to the stop release conditions if needed Specify the interrupt conditions corresponding to the stop release conditions if needed HALT released decision When the stop mode is relea
29. Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required logic GN 18 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual 2 2 SYSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below The system clock generator provided the necessary clocks for execution of instruction The pre divider generated several clocks with different frequencies for the usage of LCD driver frequency generator etc The following table shows the clock sources of system clock generator and pre divider in different conditions BOK Halt mode dual clock option XT clock XT clock Slow mode dual clock option XT clock XT clock Fast mode dual clock option XT clock CF clock 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by mask option or it will be active all the time after the initial reset In stop mode this oscillator will be stopped There are 2 type oscillators can be used in slow clock oscillator selected by mask option 2 2 1 1 External 32 768KHz Crystal oscillator XT CLO
30. PC current page PC11 specified address in operand e Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 Table 2 1 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC2 PC1 PCO 1 0 Interrupt 2 1 interrupt Interrupt SDDDDDDBBDD interrupt CPPP PPP LLLLLLLL efef els ele P8 P8 1 Interrupt 4 timer 2 interrupt Interrupt 5 Key Scanning interrupt Interrupt 6 RFC counter interrupt P10 to PO Low order 11 bits of instruction operand When executing the subroutine call instruction or interrupt service routine the contents of the program counter PC are automatically saved to the stack register STACK 26 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 4 PROGRAWTABLE MEMORY The built in mask ROM is organized with 2048 x 16 bits l 16bits 000h 7FFh Both instruction ROM PROM and table ROM TROM shares this memory space together The partition formula for PROM and TROM is shown below Instruction ROM memory space 128 N words Table ROM memory space 256 16 bytes 1 16 Note The data width of table ROM is 8 bit The partition of memory space is defined by mask option the table is shown below MASK OPTION table
31. SL1 Rx function description MRA Rx function description MAF Rx function description TM8722 User s Manual AC Rx R HL The content of data memory specified by HL is loaded to AC and data memory specified by Rx Rxn ACn lt Rx n 1 AC n 1 Rx3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC 0 gt Rx3 gt Rx2 gt Rx1 Rx0 gt Rxn ACn lt Rx n 1 AC n 1 Rx3 lt 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC 1 gt Rx3 5 Rx2 gt Rx1 gt Rx0 gt Rxn ACn lt Rx n 1 AC n 1 Rx0 ACO 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 lt Rx1 lt Rx0 lt 0 Rxn ACn lt Rx n 1 AC n 1 Rx0 ACO lt 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC lt Rx3 Rx2 Rx1 lt Rx0 lt 1 CF lt Rx 3 Bit3 of the content of Rx is loaded to carry flag CF AC Rx lt CF The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 CF Bit 2 0 zero flag Bit 1 No Use Bit 0 No Use 109 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 5 3 OPERATION INSTRUCTIONS INC Rx function description INC H
32. amp AC TM2 HL 1110 0101 0000 0000 Timer2 lt T HL 2 X 1110 011 XXXX XXXX X8 7 6 111 Ctm PH13 X8 7 6 110 Ctm PH11 X8 7 6 101 Ctm PH7 X8 7 6 100 Ctm PH5 X8 7 6 011 Ctm FREQ X8 7 6 010 Ctm PH15 X8 7 6 001 Ctm PH3 X8 7 6 000 Ctm PH9 X5 0 Set Timer2 Value SHE X 1110 1000 X6 Enable HEF6 RFC X5 Enable HEF5 KEY S X4 Enable HEF4 TMR2 X3 Enable HEF3 PDV 2 Enable HEF2 INT X1 Enable HEF1 TMR1 SIE X 1110 1001 OXXX XXXX X6 Enable IEF6 RFC X5 Enable IEF5 KEY S X4 Enable IEF4 TMR2 X3 Enable IEF3 PDV 2 Enable IEF2 INT X1 Enable IEF1 TMR1 X0 Enable IEFO CPT PLC X 1110 101X OXXX XXXX X8 Reset PH15 11 X6 0 Reset HRF6 0 SRF x 1110 1100 00 XXXX 5 Enable Cx Control X4 Enable TM2 Control x3 Enable Counter ENX 2 Enable RH Output EHM x1 Enable RT Output ETP X0 Enable RR Output ERR SRE X 1110 1101 XOXX 0000 X7 Enable SRF7 SRF7 KEY S X5 Enable SRF5 SRF5 INT X4 Enable SRF4 SRF4 C Port FAST 1110 1110 0000 0000 SCLK High Speed Clock SLOW 1110 1111 0000 0000 SCLK Low Speed Clock SF X 1111 0000 X00X XXXX X7 Reload 1 Set RL1 X4 WDT Enable WDF X3 HALT after EL 2 EL LIGHT On X1 BCF Set BCF X0 CF Set CF RF X 1111 0100 X7 Reload 1 Reset RL1 X4 WDT Reset WDF X2 EL LIGHT Off X1 BCF Reset BCF Reset SF2 X 1111 1000 0000 XXXX x3 Enable INT powerful Pull INTPL low X2
33. disable the counter and the clock source of the counter comes from the output of the frequency generator FREQ The counter will start to count the clock FREQ after the first rising edge signal applied on the CX pin when the counter is enabled Once the second rising edoe is applied to the CX pin after the counter is enabled the halt release request HRF6 will be delivered and the counter will stop counting In this case if the interrupt enable mode IEF6 is provided the interrupt is accepted and if the halt release enable mode HEF6 is provided the halt release request signal is delivered setting the start condition flag 9 SCF9 in status register 4 5794 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF SRF 28h SRF control Enable counter E i CX Content of the counter X 0 X X 2X3 N 1 XNX FREQ HALT released request n Counter starts pone nas to count I 2nd falling edge This figure shows the timing of the counter controlled by the CX pin Example SCG 0h Select the base clock of the frequency generator that comes from PH0 XT clock FRQX 1 5 set the frequency generator to FREQ 6 setting value of the frequency ge
34. C sC T VDD lighted sides fof GND segnments on COM4 with VDD lighted sides fp ets GND segnments on COM5 with VDD lighted sides ff w GND segnments on COM1 2 with Y VDD lighted sides dp J poo ooo cnn enis GND segnments on COM1 3 with 1 jJ TV 1 VDD lighted sides L j jJ ff GND segnments on COM1 4with J VDD lighted sides f J J b cc GND segnments 1 5 with _ dt FF 1 VDD lighted Be eS GND segnments on COM2 3 with D VDD lighted sides ee GND segnments on 2 4 wih J 1 1 22272 VDD lighted sides J J j amma GND segnments on COM2 5 wih T J F jJ o VDD lighted sides J COUOT poc Nem GND segnments on COM3 4 wih O O fT VDD lighted sides A J j j ooo occ sena GND segnments on COM3 5 wih VDD lighted sides J J j J GND segnments on COM4 5 VDD lighted sides GND segnments on COM1 2 3 4 5 with lighted sides _ GND 101 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual iii Display Turn Off VDD COM 1 2 3 4 5 in low active VDD COM 1 2 3 4 5 in high active GND VDD All LED driver outputs GND iv Stop mode
35. CTLA 2 15 1 CONTROL REGISTER 1 CTL1 The control register 1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC defined as input mode that causes the halt mode or stop mode to be released Executed SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 CTL1 Bit 4 Switch enable flag 4 SEF4 Enables the halt release caused by the signal change on IOC port The following figure shows the organization of control register 1 CTL1 HALT Released Request ion Edge detector SEF4 s Q 5 Interrupt 0 SCA 10h request PLC 1 IEF0 Interrupt 2 accept 2 15 1 1 The Setting for Halt Mode If the SEF4 is set to 1 the signal changed on IOC port will cause the halt mode to be released and set SCF1 to 1 Because the input signal of IOC port were ORed so it is necessary to keep the unchanged input signals at 0 state and only one of the input signal could change state 2 15 1 2 The Setting for Stop Mode If SRF4 and SEF4 are set the stop mode will be released to set the SCF1 when a high level signal is applied to one of the input mode pins of IOC port and the other pins stay in 0 state After the stop mode is released TM8722 enters the halt condition The high level signal must hold for a while to cause the chattering prevention circuitry of IOC po
36. D are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D FH AC lt Ry D B 1 D represents an immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH AC Rx lt Ry D B 1 D represents an immediate data The immediate data D is binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D 0H FH lt Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC 115 tenx technology inc Rev 1 1 2003 11 25 Ry D function description ANDI Ry D function description ANDI Ry D function description EORI Ry D function description EORI Ry D function description ORI function description ORI Ry function TM8722 User s Manual The result will not affect the carry flag CF D FH AC lt Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC and working register Ry The result will not affect the carry flag CF D FH AC lt Ry amp D represents immediate data The contents of Ry and D are binary ANDed the result is loaded to AC D 0H FH
37. DRIVER TM8722 provides an EL panel driver for the backlight of the LCD panel The user can choose different voltage pumping frequencies duty cycle and ON OFF frequency to operate with few external components This circuitry could generate output voltage up to AC 150V or above for driving the EL plant the ELC and ELP output is MUXed with IOB1 SEG28 and 2 SEG29 and is selected by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC 3 ELC SEG29 IOB2 ELP 3 ELP The ELP pin will output clocks to pump voltage to the EL plant the ELC pin will output the pulse to discharge the EL plant The EL plant driver will not operate until the light control signal LIT is enabled Once the light control signal LIT is enabled the ELC pin will output a pulse to discharge the capacitor before the pumping clocks output to ELP pin This will insure that there is no residual voltage that may cause damage while the first pumping clock is applied When the light control signal LIT is disabled the ELC pin will output a pulse to discharge the EL plant after the last pumping clock This figure shows the application circuit of EL plant EL plant LIT ELP ELC This figure shows the output waveform of EL plant driver The ELP ELC pulse frequency and duty cycle could be defined by executing ELC instruction When ELC pin outputs the discharge pulse the clock on ELP pin will be inhibited
38. IOB pull low R IOB4 as output mode IOB4 as input mode as output mode as input mode as output mode IOB2 as input mode as output mode IOB1 as input mode OPB Rx function description IPB Rx function description SPC X function description Rx The contents of Rx are outputted to port Rx AC lt The data of port is loaded to AC and data memory Rx Defines the input output mode of each pin for IOC port and enables disables the pull low device or low level hold device Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the pin was set as input mode 105 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Enables all of the pull low Disables all of the pull low X4 1 and disables the low level X4 0 and enables the low level hold devices hold devices OPC Rx function lt Rx description The content of Rx is outputted to I OC port IPC Rx function Rx AC lt description The data of I OC port is loaded to AC and data memory Rx SPK X function Sets Key Matrix scanning output state description When any of SEG1 16 is used for LCD LED by mask option the outputstate in scanning interval is set by X X6 0 Bit Patten Setting Halt Release b X6 0 Normal Key Scanning X6 1 Scanning C
39. JZ and JNZ BCD operation DAA DAS 2 11 HEXADECIMAL CONVERT TO DECIMAL HCD Decimal format is another number format for TM8722 When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown in the following table and illustrated in example 1 AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt lt 9 AZACEF AC 6 0 lt lt 3 1 6 Example 1 LDS 101 9 Load immediate data 9 to data memory address 10H LDS 1th 1 Load immediate data 1 to data memory address 11H and AC HF 1h Reset CF to 0 ADD 10h Contents of the data memory address 10H and AC are binary added the result loads to amp data memory address 10H Rio AC CF 0 DAA 10h Convert the content of AC to decimal format The result in the data memory address 10H is O and in the CF is 1 This rep
40. L1 h CUP1 2 INT N 1 gt 16 4 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 1 4 PAD DIAGRAM The substrate of chip should be connected to GND 0000000000000 Die size 1680um x 1680um D OOOOOOOOOO000 0000600000000 1 5 COORDINATE SEG13 K13 SEG14 K14 SEG15 K15 SEG16 K16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 IOA1 CX SEG25 IOA2 RR SEG26 IOA3 RT SEG1 K1 SEG27 IOA4 RH SEG2 K2 SEG28 IOB1 ELC SEG3 K3 SEG29 IOB2 ELP SEG4 K4 SEG30 IOB3 BZB SEG5 K5 2 SEG31 IOB4 BZ SEG6 K6 2 1 11 SEG7 K7 SEG33 IOC2 KI2 5 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual SEG8 K8 SEGS4 IOC3 KI3 SEG9 K9 SEG35 lOC4 Kl4 SEG10 K10 RESET SEG11 K11 INT SEG12 K12 TEST 1 6 PIN DESCRIPTION Description AE power Mode connect a 0 1u capactorto GND At Li power Mode connect a 0 1u capacitor to GND LCD supply voltage and positive supply voltage In Ag Mode connect positive power to VDD1 In Li or ExtV power mode connect positive power to VDD2 Input pin for external reset request signal built in internal pull down resistor Input pin for external INT request signal Falling edge or rising edge triggered is defined by mask option Internal pull down or pull up resistor is defined by mask option
41. LT LA 1 1 duty carrier out 3 3 2 Melody Output The frequency generator may generate the frequency for melody usage When the frequency generator is used to generate the melody output the tone table is shown below The clock source is i e 32 768 Hz The duty cycle is 1 2 Duty D 2 FREQ is the output frequency ideal is the ideal tone frequency is the frequency deviation Q N The following table shows the note table for melody application FREQ Ideal Tone N FREQ Ideal 1 _ 2 249 055360 65 4064 019 C4 62 260 063 261 626 0 60 E2 198 82 3317 82 4069 0 09 E4 49 327 680 329 628 059 62 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual 0 20 0 19 D3 111 03 98 165 495 164 814 0 41 0 64 69 234 057 233 082 0 42 A5 17 910 222 932 328 2 37 D3 D3 ES 18 G3 8 Note 1 Above variation does not include X tal variation 2 If PHO 65536Hz C3 B5 may have more accurate frequency During the application of melody output sound effect output or carrier output of remote control the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 3 3 3 Halver Doubler Tripler The halver doubler tripler circuits are used to generate the
42. NO BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 12 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual 2 1 1 2 1 2 BIAS amp STATIC AT AG BATTERY POWER SUPPLY MASK OPTION table Internal 3 Mask Option name Selected item POWER SOURCE 3 1 5V BATTERY LCD BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 1 3 1 3 BIAS AT AG BATTERY POWER SUPPLY MASK OPTION table Mask Option name Internal logic Selected item POWER SOURCE 3 1 5V BATTERY LCD BIAS 1 1 3 BIAS 13 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Note 1 The input output ports operate between GND an
43. RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Mask Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE IEF2 Interrupt request HEF2 SCF2 Halt release request HRF CLK PLC 4h Initial clear pulse Mask option Interrupt 2 receive signal Open type Note For Ag battery power supply positive power is connected to VDD1 for anything other than Ag battery power supply it is connected to VDD2 This figure shows the INT Pin Configuration 74 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 3 8 Resister to Frequency Converter RFC The resistor to frequency converter RFC can compare two different sensors with the reference resister separately This figure shows the block diagram of RFC SRF 8h Controlled by Timer 2 SRF 18h SRF 28h CX pin signal interrupt request SCF9 counter over flow flag enable CNT HRF6 16 bit counter SRF 18h CLKIN SRF 28h FREQ output from frequency generator to data memory and AC 4 bit data bus This RFC contains four external pins CX the oscillation Schemmit trigger input RR the reference resister output pin RT the temperature sensor output pin RH the humidity sensor output p
44. The bit meaning of X X4 is shown below Bit pattern Halt mode is released when signal applied to IOC X7 5 X3 0 is reserved Set Reset interrupt enable flag The IEFO is set so that interrupt O Signal change at port IOC specified by SCA is accepted X1 1 The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted X221 SHE X function The IEF2 is set so that interrupt 2 the signal change at the INT pin is accepted The IEF3 is set so that interrupt 3 overflow from the predivider is accepted The IEF4 is set so that interrupt 4 underflow from timer 2 is accepted X5 1 The IEF5 is set so that interrupt 5 key scanning is accepted The IEF6 is set so that interrupt 6 overflow from the RFC counter is accepted X7 is reserved Set Reset halt release enable flag 119 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual description X1 1 The HEF1 is set so that the halt mode is released by TMR1 underflow X2 1 The HEF2 is set so that the halt mode is released by signal changed on INT bin X3 1 The HEF3 is set so that the halt mode is released by predivider overflow X4 1 The HEF4 is set so that the halt mode is released by TMR2 underflow X521 The HEF5 is set so that the halt mode is released by th signal is H L LED LCD on KI1 4 in scanning interval X6 1 The HEF6 is set so that the halt mode is released by RFC counter overflow X7 is reserved SRE X funct
45. latch circuit The data decoder is used for decoding the content of the working register specified in LCD related instructions as 7 segment pattern on LCD panel The decoding table is shown below Content Output of data decoder EOD DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH us qo lox qo 0 o cpu e The DBUSF of decoded output can be selected 0 or 1 mask option The LCD pattern of this option is shown below DBUSA DBUSA DBUSF DBUSB DBUSF DBUSB lt DBUSG gt lt DBUSG gt N DBUSE DBUSC DBUSE DBUSC DBUSD DBUSH DBUSD DBUSH DBUSF 0 DBUSF 1 The following table shows the option table for displaying digit 7 pattern MASK OPTION table Mask Option name Selected item SEGMENT FOR DISPLAY 7 1 SEGMENT FOR DISPLAY 7 _ 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of data memory that specified When the content of data memory that specified by LCB instruction is 0 the decoded output of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on LCD panel The LCP instruction transferred the data of the RAM Rx and accumulator AC directly from to DBUSH without passing through the data decoder 86 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The LCD instruction transfe
46. m VDD in high active mode GND COM2 VDD in high active mode GND high active mode GND segments on veo COM with lighted sides GND segments on with lighted sides GND segments on VDD 1 2 with lighted sides GND segments on J4 os O gt m VDD CONS with lighted sides GND segments on VDD COM1 3 with lighted sides GND segments on VDD COM2 3 with lighted sides GND segments on VDD COM1 2 3 with lighted sides GND segments on 5 2 3 with unlighted sides GND 96 tenx technology inc Rev 1 1 2003 11 25 iii Display Turn Off COM1 COM2 in low active COM1 COM2 in high active All LED driver outputs iv STOP mode COM1 COM2 7 U U U in low active COM1 COM2 in high active All LED driver outputs Figure 2 41 1 3duty LED Waveform 4 2 4 1 4 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode lighting COM1 2 3 4 in low active COM1 2 3 4 in high active All LED driver outputs 97 TM8722 User s Manual dias GND VD ss GND VDD GND ee VDD GND VDD E GND tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual ii Normal operation mode VDD COM1 in Low active GND
47. specified by HL and AC are binary ANDed the result is loaded to AC and data memory specified by lt Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC AC lt R HL AC The contents of data memory specified by and AC are exclusive Ored the result is loaded to AC AC lt Rx AC The contents of Rx and AC are exclusive Ored the result is loaded to AC and data memory 113 tenx technology inc Rev 1 1 2003 11 25 function description OR Rx function description OR HL function description OR Rx function description OR HL function description ADCI Ry D function description ADCI Ry D function description SBCI Ry D function description TM8722 User s Manual AC R HL R HL AC The contents of data memory specified by HL and AC are exclusive Ored the result is loaded to AC and data memory data memory specified by HL AC lt Rx AC The contents of Rx and AC are binary Ored the result is loaded to AC AC lt R HL AC The contents of HL and AC are binary Ored the result is loaded to AC HL indicates an index address of data memory AC lt Rx AC The contents of Rx and AC are binary Ored the result is loaded to AC data memory Rx AC R HL lt R HL AC The contents of data memory specified by HL and AC are binary Ored the result is loaded to AC
48. the data RAM Rx and AC into the higher nibble of the register H L is a 4 bit register and OH is 8 bit register H register register L register Bit7 Bit6 Bits Bit4 Bits Bit2 Biti Bits Biti BitO IDBF11 IDBF10 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO The index address register can specify the full range addresses of the table ROM and data memory index addressing DATA RAM TABLE ROM addressing This figure shows the diagram of the index address register 2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stack register are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the first level will be overwritten 29 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the conte
49. these instructions 88 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual X 5 m 5 m 2 H H m te a EI Driver EIE 5 Figure Sample Organization of Segment PLA Option 4 1 3 4 THE CONFIGURATION FILE FOR MASK OPTION When configuring the mask option of LCD PLA the cfg file provides the necessary format for editing the LCD LED configuration The syntax in cfg file is as follows SEG COM PSTB DBUS SEG Specifies the segment pin COM Specifies the corresponding latch in each segment pin Only 0 1 2 3 4 5 and 9 can be entered into this field 0 is for CMOS type DC output option and 9 is for P open drain DC output option PSTB Specifies the strobe data for the latch DBUS Specifies the DBUS data for the latch 89 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 4 2 LED DRIVER OUTPUT When the LED mode is selected by the mask option TM8722 will be used for LED display The number of the LED driver outputs is 35 segment pins with 5 common pins COM For LED driver outputs COM mask option can be used to select active low LED display or active high LED display and there are static 1 2 duty 1 3 duty 1 4duty or 1 5 duty lighting systems could be used There is no bias issue in LED mode so please select the 1 2 bias or No bias as the bias system In LED mode the segment output pins SEG work always i
50. to higher nibble of index address buffer OH H7 AC3 QH6 AC2 QH5 AC1 H4 ACO QQH3 Rx3 H2 Rx2 H1 Rx1 HO RxO L lt Rx Loads content of Rx to lower nibble of index address buffer L L3 Rx3 L2 Rx2 L1 Rx1 LO Rx0 5 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA function description DAA Rx function description DAA HL function description lt BCD AC Converts the content of to binary format and then restores to When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC Rx BCD AC Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC R HL lt BCD AC Converts the content of AC to decimal format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected 122 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt lt 9 lt lt 0 lt lt 3 function lt BCD AC description Converts the conte
51. to those output latches This will prevent the chattering signal when the pins change to output mode IOC port may select the pull low device or low level hold device for each pin by mask option or enable disable this device by program setting When the pull low device and low level hold device are both enabled by mask option the reset will enable the pull low device and disable the low level hold device Executing SPC 10h instruction may also enable the pull low device and disable the low level hold device and executing SPC Oh may disable the pull low device and enable the low level hold device When the IOC pin has been defined as the output mode both the pull low and low level hold devices will be disabled 69 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual D bit0 Initial clear SPC edge dectect amp u chattering Control 1 L Data Bus IOC3 Y a re ntrol 2 Note M O is mask option IPC This figure shows the organization of IOC port Not
52. tuii enm 103 5 2 Accumulator Manipulation Instructions and Memory Manipulation IS 108 5 3 Operation Instructions 110 5 4 Load Store 117 5 5 CPU Control Instructions 118 5 6 Index Address InstriellOlis 122 5 7 Decimal Arithmetic Instructions KE Re Ra Lena Re KE Rn uH EAE 122 5 8 Jump INS UU CTIOING SEMEN 123 5 9 Miscellaneous Instr ctloris uuu eo eani Duo tona teo Gonna 125 APPNDIX 8722 Instruction Table 131 2 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM8722 is an embedded high performance 4 bit microcomputer with LCD LED driver It contains all the necessary functions such as 4 bit parallel processing ALU ROM RAM ports timer clock generator dual clock operation Resistance to Frequency EL panel driver LCD driver look up table watchdog timer and key matrix scanning circuitry in a signal chip 1 2 FEATURE 1 Low power dissipation 2 Powerful instruction set 143 instructions Binary additions subtraction BCD adjust logical operat
53. will still remain the input mode Executing IPA instructions may store the signals applied to the IO pins into the specified data memory When the IO pins are defined as the output mode executing IPA instruction will store the content that stored in the latch of the output pin into the specified data memory Before executing SPA instruction to define the I O pins as the output mode the OPA instruction must be executed to output the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changed port had built in pull down resistor The pull low device for each pin is selected by mask option and executing SPA instruction to enable disable this device Pull low function option Mask Option name Selected item PULL LOW RESISTOR 1 USE IOA PULL LOW RESISTOR 2 NO USE Initial clear SPA 1 Initial clear SPA2 IOA2 Initial clear SPA 4 IOA3 Initial clear SPA8 IOA4 SPA 10 Note M O is mask option 66 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual This figure shows the organization of IOA port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo seri
54. 0 O O O O O O O Executing SPK X instruction could set the scanning type of key matrix The bit pattern of this instruction is shown below Instruction Bit6 Bit5 Bit4 Bit3 Bit2 BitO SPK X X6 X5 X4 X3 X2 XO Bit Patten Setting Halt Release by X6 0 Normal Key Scanning X6 1 Scanning Cycle The bit pattern of X for Key Matrix scanning output to SEG1 16 0 o 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 1 Hiz 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 1 0 Hrz Hiz 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 000 1 Hi z Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 0 0 1 0 0 Hiz Hiz Hrz Hiz 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 0 0 1 0 1 Hi zlHi z Hi z Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 0 0 1 1 0 HizlHi z Hi z Hi z Hi z Hi z 1 Hi z Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z 79 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z H i z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z H z Hi z Hi z Hi z Hi 2 0 H i zHi zHi zlHi z Hi z Hi z Hi z Hi z Hi z Hi z Hi
55. 00 0000 AC lt SBC Rx 0010 0011 OXXX XXXX AC Rx lt Rx CF CF SBC HL 0010 0011 1000 0000 AC R HL lt CF 0010 0100 XXXX lt HL 0010 0100 1000 0000 AC lt R HL ADD Rx 0010 0101 XXXX lt ADD HL 0010 0101 1000 0000 AC RGHL R HL AC SUB Rx 0010 0110 OXXX XXXX AC lt Rx 1 SUB HL 0010 0110 1000 0000 AC lt 1 SUB Rx 0010 0111 OXXX XXXX lt 1 SUB HL 0010 0111 1000 0000 AC R HL lt 1 CF ADN Rx 0010 1000 OXXX XXXX AC lt Rx AC ADN HL 0010 1000 1000 0000 AC lt R HL AC ADN Rx 0010 1001 OXXX XXXX AC lt Rx AC ADN HL 0010 1001 1000 0000 R HL R HL AC AND Rx 0010 1010 OXXX XXXX AC lt Rx AND AC AND HL 0010 1010 1000 0000 AC lt R HL AND AND Rx 0010 1011 OXXX XXXX AC lt Rx AND AC AND QHL 0010 1011 1000 0000 AC R HL RGHL AND AC EOR Rx 0010 1100 OXXX XXXX AC Rx EOR AC EOR HL 0010 1100 1000 0000 AC lt EOR AC EOR Rx 0010 1101 OXXX XXXX AC RX lt Rx EOR AC EOR HL 0010 1101 1000 0000 AC RGHL lt R HL EOR OR Rx 0010 1110 OXXX XXXX AC lt Rx OR AC OR
56. 1 Hrz Hiz Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 Hi z 010 1 1 1 1 HiziHi zjHiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 106 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Notes 1 1 H L LED LCD 2 K1 16 SEG1 16 output in scanning interval ALM X function Sets buzzer output frequency description The waveform specified by X X8 is delivered to the BZ and BZB pins The output frequency could be any combination in the following table The bit pattern of X for higher frequency clock source clock source higher frequency FREQ _ 0 clock source lower frequency 615 1Hz 11 16Hz 010 32 2 Notes 1 FREQ is output of frequency generator 2 When the buzzer output does not need the envelope waveform X5 should be set to 0 3 The frequency inside the bases on the 0 is 32768Hz ELC X function The bit control of EL light driver description The meaning of each bit specified by X X8 X0 is shown below For ELP pin setting X8 X7 X6 Pumping clock X5 X4 Duty cycle frequency 000 34 BCLK BCLK 2 1 2 duty BCLK 4 BCLK8 107 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual For ELC pin setting X3 X2 Discharge pulse frequency X1 X0 Duty cycle 00 88 0 t 4duy S
57. 15th stage of the Start condition Start condition flag 7 pre divider flag 5 flag 4 SCF7 SCF5 Halt release Halt release Halt release caused by pre caused by TMR1 caused by INT divider overflow underflow i Read only Read only Read only Read only 2 14 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags 1 Start condition flag 8 SCF8 SCF8 is set to 1 when one of KI1 4 1 0 1 4 1 in LED mode 1 4 0 in LCD mode causes the halt release request flag 5 HRF5 to be outputted and the halt release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 42 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 Start condition flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be outputted and the halt release enable flag 4 HEF4 is set beforehand To reset the start condition flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 or the SHE instruction must be used to reset the halt release enable flag 4 HEF4
58. 2 2 12 mmer T SURE RC 33 2 13 Timer 2 TMR2 bc 36 2 14 Stat s 40 2 15 Control Register m 45 2 15 HALT FUNGO reo ie a ibid 48 2 17 Heavy Load 49 2 18 STOP FUNCION 50 2 19 Back Up F etlo fl Meo 51 1 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual CHAPTER 3 Control Function J J 53 3 1 Interrupt 53 S 2 Rese usu u uyu su ccpit cies 57 3 3 Clock Generator Frequency Generator and Predivider 61 3 4 Buzzer 63 3 5 Input Output dino idus 65 3 6 EL Panel EI e 72 3 Ext rmal INT 73 3 8 Resistor to Frequency Converter 75 3 9 Key Matrix uuu uu ni a ex ue etx saya sag e tex to apay asas tem EEUU 79 CHAPTER 4 LCD Driver Output J 83 4 1 LCD driver dic i e 83 4 2 LED driver oso L S a q qbus E 90 CHAPTER 5 Detail Explanation of TM8722 Instructions 103 5 1 Input Ee
59. 3 0 3 to 8 5 V Maximum Input Voltage Vin 0 3 to VDD1 2 0 3 V Maximum output Voltage Vouti 0 3 to VDD1 2 0 3 V Vout2 0 3 to VDD3 0 3 V Maximum Operating Topg 20 to 70 C Temperature Maximum Storage Tstg 25 to 125 C Temperature POWER CONSUMPTION at 20 to 70 C GND 0V Name Sym Condition Min Typ Max Unit HALT mode IHAN Only 32 768KHz Crystal oscillator 2 5 uA operating without loading Ag mode VDD1 1 5V BCF 0 Only 32 768KHz Crystal oscillator 2 5 uA operating without loading Li mode VDD2 3 0V BCF 0 2 STOP mode lsroP 1 uA Note When RC oscillator function is operating the current consumption will depend on the frequency of oscillation 7 tenx technology inc Rev 1 1 2003 11 25 ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND OV TM8722 User s Manual Name Symb Condition Min Max Unit VDD1 1 2 5 25 V Supply Voltage VDD2 2 4 5 25 V VDD3 2 4 8 0 V Oscillator Start Up Voltage VDDB Crystal Mode 1 3 V Oscillator Sustain Voltage VDDB Crystal Mode 1 2 V Supply Voltage VDD1 Ag Mode 1 2 1 65 V Supply Voltage VDD2 EXT V Li Mode 2 4 5 25 V Input H Voltage Vih1 Ag Battery Mode VDD1 0 7 VDD1 0 7 V Input L Voltage Vil 0 7 0 7 V Input Voltage Vih2 Li Battery Mode VDD2 0 7 VDD240 7 V Input
60. 3 11 25 TM8722 User s Manual interrupt service routine is initiated all of the interrupt enable flags IEFO IEF6 are cleared and should be set with the next execution of the SIE instruction Refer to Table 3 1 Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been defined as input mode PLC 7Fh Clear all of the HRF flags SCA 10h enable the interrupt request of IOC SIE 7Fh enable all interrupt requests all interrupts are requested simultaneously Interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 77h Enable the interrupt request except the predivider Interrupt caused by the TM1 underflow occurs and interrupt service is concluded SIE 75h Enable the interrupt request except the predivider and TMR1 Interrupt caused by the TM2 underflow occurs and interrupt service is concluded SIE 65h Enable the interrupt request except the predivider TMR1 and TMR2 Interrupt caused by the RFC counter overflow occurs and interrupt service is concluded SIE 25h Enable the interrupt request except the predivider TMR1 TMR2 and the RFC counter Interrupt caused by the IOC port and interrupt service is concluded SIE 24h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter and IOC port Interrupt caused by the INT pin and interrupt service is concluded
61. 4 15 16 17 Built in R to F Converter circuit e CX RR RT RH Muxed with SEG24 SEG27 Built in key matrix scanning function e K1 K16 Shared with SEG1 SEG16 e 1 4 Muxed with SEG32 SEG35 Two 6 bit programmable timer with programmable clock source Watch dog timer Built in Voltage doubler halver tripler charge pump circuit Dual clock operation slow clock oscillation can be defined as X tal or external RC type oscillator by mask option fast clock oscillation can be defined as internal or external type oscillator by mask option HALT function STOP function 1 3 BLOCK DIAGRAM B1 4 A1 4 ELC ELP CX BZ BZB RR RT RH ON TT CTE ee ee LCD DRIVER PORT A PORT x C PORT c EL DRIVER RFC KEY IN ALARM SEGMENT PLA Iir TXFI ir 4 BITS DATA BUS C1 4 SEG1 35 Kl1 4 COM1 5 K1 K16 VDD1 3 FREQUENCY INDEX ROM 2 DATA RAM GENERATOR 56 16 N X 8 128 X 4 BITS x 6 BITS PRESET INSTRUCTION a dux 3 TIME 1 amp 2 S LEVELS STACK DECODER CONTROL 11 BITS PROGRAM N MASK ROM OSCILLATOR gt y CIRCUIT COUNTER 128N X 16 BITS
62. AM and Working Register Organization 2 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory RAM are not only used as general purpose data memory but also as the working register WR The following will introduce the general usage of working registers 1 Be used to perform operations on the contents of the working register and immediate data Such as ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 Be transferred the data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 Decode or directly transfer the contents of the working register and output to the LCD PLA circuit Such as LCT LCB LCP 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory can be performed 2 10 ALU Arithmetic and Logic Unit This is a circuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI Logic operation AND EOR OR ANDI EORI ORI Shift SRO SR1 SLO SL 1 31 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Decision JB0 JB1 JB2 JB3 JC JNC
63. AST only or DUAL clock options MASK OPTION table Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY amp USE EXTERNAL RESISTOR or 4 DUAL For 250KHz output frequency Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 1 INTERNAL RESISTOR FOR 250KHz For 500KHz output frequency Mask Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 2 INTERNAL RESISTOR FOR 500KHz XTOUT XTIN Internal FREQUENCY RANGE OF INTERNAL RC OSCILLATOR Option Mode BAK Min Typ Max 250KHz 1 5V 200KHz 300KHz 400KHz 3 0V 200KHz 250KHz 300KHz 500KHz 1 5V 450KHz 600KHz 750KHz 3 0V 400KHz 500KHz 600KHz 21 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 2 3 COMBINATION OF THE CLOCK SOURCES There are three types of combination of the clock sources that can be selected by mask option 2 2 3 1 DUAL CLOCK MASK OPTION table Mask Option name Selected item CLOCK SOURCE 4 DUAL The operation of the dual clock option is shown in the following figure When this option is selected by mask option the clock source BCLK of system clock generator will switch between XT clock and CF clock according to the user s program When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically The XT clock provides the clock to the p
64. Bit 2 Bit 1 Bit 0 Start condition flag The content of 15th Start condition flag Start condition flag 7 stage of the 5 4 SCF7 predivider SCF5 SCF4 Halt release Halt release Halt release caused by causedby TM1 caused by INT pin predivider overflow underflow MCX Rx function lt SCF8 SCF6 SCF9 description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning o bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 Start condition NA Start condition Start condition flag 9 flag 6 flag 8 SCF9 SCF6 SCF8 Halt release NA Halt release Halt release caused by caused by TM2 caused by the counter overflow underflow signal change to H L CED LCD on 1 4 in scanning interval MSD Rx function Rx WDF CSF RFOVF description The watchdog flag system clock status and overflow flag of RFC counter are loaded to data memory specified by Rx and AC The content of AC and meaning of bit after execution of this instruction are as follows 121 tenx technology inc Rev 1 1 2003 11 25 Bit 3 TM8722 User s Manual Bit 2 Bit 1 Bit 0 Reserved The overflow flag Watchdog timer System clock of 16 bit counter of enable flag WDF selection flag RFC RFVOF CSF 5 6 INDEX ADDRESS INSTRUCTIONS MVH Rx function description MVL Rx function description Loads content of Rx
65. CK MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 1 15pf Spf XIN ae 32768Hz Crystal 1 X tal When backup flag BCF is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time but this will increase the power consumption Therefore the backup flag should be reset unless required otherwise The following table shows the power consumption of Crystal oscillator in different conditions 19 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual _ Ag power option Li power option EXT V option BCF 1 BCF 0 Normal Normal Increased Initial reset Increased Increased Increased After reset Increased Increased Increased 2 2 1 2 External RC oscillator XT CLOCK MASK OPTION table Mask Option name Selected item SLOW CLOCK TYPE FOR SLOW ONLY OR DUAL 2 RC 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock is a multiple type oscillator mask option which provide a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to system clock generator only When the dual clock option is selected by mask option this osc
66. Close all Segments RSOFF X1 Dis ENX Set DED XO Reload 2 Set RL2 RF2 X 1111 1001 0000 XXXX X3 Disable INT powerful Pull INTPL low X2 Release Segments RSOFF X1 Dis ENX Reset DED 134 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Instruction Machine Code Function Flag Remark X0 Reload 2 Reset RL2 ALM X 1111 101X XXXX XXXX X8 7 6 111 FREQ X8 7 6 100 DC1 X8 7 6 011 PH3 X8 7 6 010 PH4 X8 7 6 001 PH5 X8 7 6 000 DCO X5 0 lt PH15 10 ELC X 1111 110X XXXX XXXX X8 1 BCLKX ELP CLK X8 0 PHO X7 6 11 BCLK 8 BCLKX X7 6 10 BCLK 4 X7 6 01 BCLK 2 X7 6 00 BCLK 5 4 11 1 1 X5 4 10 1 2 EE ee 5 4 01 2 3 5 4 00 3 4 X3 2 11 PH5 X3 2 10 PH6 ELC CLK X3 2 01 PH7 X3 2 00 PH8 X1 0 11 1 1 X1 0 10 1 2 ELC DUTY X1 0 01 1 3 X1 0 00 1 4 HALT 1111 1110 0000 0000 Halt Operation STOP 1111 1111 0000 0000 Stop Operation Symbol Description Immediate Data Content of Register Accumulator Complement of Immediate Data Content of Accumulator bit n Program Counter Complement of content of Accumulator Carry Flag Address of program or control data Zero Flag Watch Dog Timer Enable Flag 7 segment decoder for LCD Address Y of working register System clock for instruction Address of data RAM specified by HL Interrupt Enable Flag Back up Flag HALT Release Flag Generic Index address register
67. F5 overflow SCF8 HEF5 SHE 20h IEFG SIE 40h Interrupt 6 RFC overflow HEF6 SHE 40h condition flags for TM8722 2 14 1 STATUS REGISTER 1 STS1 counter HRF6 SCF9 B Status register 1 STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the result of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 40 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual If the content of the accumulator is not 0 the zero flag is reset to 0 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 Bit 0 Carry flag AC Zero flag Z Read only Read only Read only 2 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 SCF1 SCF2 and the backup flag The MSB instruction can be used to transfer data of status register 2 STS2 to the accumulator AC and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2 The following table shows the bit pattern of each flag in status register 2 STS2
68. H without passing through the data decoder The mapping table is shown below 5 LCT Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 6 LCB Lz HL Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The DBUS A to DBUSH are all 0 when the input data of the data decoder is O 7 LCP Lz HL The data of the index RAM and accumulator AC are transferred directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown below Table 2 4 The mapping table of LCP and LCD instructions DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH T HLO TOHL1 T HL2 TOHL3 T HL4 T HL5 6 TO HL7 5 SF2 4h Turns off the LCD display 6 RF2 4h Turns on the LCD display 4 1 3 3 CONCRETE EXPLANATION Each LCD driver output corresponds to the LCD 1 5 duty panel and has 5 latches refer to Figure Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of the segments in the LCD driver outputs is flexible In other words one of the data decoder outputs DBUSA to is applied to the latch input L and one of the PSTBO to PSTB1Fh outputs are applied to clock CLK Refer to Chapter 5 for detail description of
69. Hz frequency LED Lighting System and Maximum Number of Driving LED Segments Maximum Number of System Driving E EM ments Static Mask option permits LED driver output pins to used for CMOS type DC output or P open drain DC output ports In this case it is possible to use some LED driver output pins for DC output ports and the remaining LED driver output pins for LED driver outputs In the LCD configuration file cfg with the O data listed in the COM column the segment pin will be defined as the CMOS type output port When the 9 data is listed in the COM column the segment pin will be defined as the P open drain type output port 91 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual All of LED driver outputs can be selected as CMOS type or P open drain type output by mask option When the LED driver output pin SEG has been defined as the DC output port the output data will not be affected when the STOP mode or LED turn off mode is active During reset mode all of LED s outputs will be unlighted by default setting as this setting may prevent large power consumption during the initial clear cycle All of the LED output data will keep the initial setting until the LED related instructions are executed in the program The output waveform of the common output and LED driver output for each LED lighting system are shown below 4 2 1 STATIC LIGHTING SYSTEM FOR LED DRIVER i Initi
70. L function description DEC Rx function description DEC HL function description ADC Rx function description ADC HL function description ADC Rx function description ADC HL function Rx AC lt Rx 1 Add 1 to the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected R HL AC lt R HL 1 Add 1 to the content of data memory specified by HL the result is loaded to data memory specified by HL and AC Carry flag CF will be affected Rx lt Rx 1 Substrate 1 from the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected R HL AC R HL 1 Substrate 1 from the content of data memory specified by HL the result is loaded to data memory specified by HL and AC Carry flag CF will be affected AC lt Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC Carry flag CF will be affected lt R HL AC CF The contents of data memory specified by AC and CF are binary added the result is loaded to AC Carry flag CF will be affected AC Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Carry flag CF will be affected AC R HL lt R HL AC CF 110 tenx technology inc Rev 1 1 2003 11 25 description SBC Rx function description
71. O mode changed port had built in pull down resistor The pull low device for each pin is selected by mask option and executing SPB instruction to enable disable this device 68 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Pull low function option Mask Option name Selected item IOB PULL LOW RESISTOR 1 USE IOB PULL LOW RESISTOR 2 NO USE 3 5 3 IOC PORT IOC1 IOC4 pins MUXed with SEG32 KI2 SEG33 SEG34 and SEG35 pins respectively by mask option MASK OPTION table Mask Option name Selected item 5 2 2 IOC1 2 2 2 IOC2 2 IOC3 SEG35 IOCA KI4 2 IOC4 After the reset cycle the IOC port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPC instruction Executed OPC instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IPC instructions may store the signals applied to the IOC pins in the specified data memory When the IOC pins are defined as the output executing IPC instruction will save the data stored in the output latches in the specified data memory Before executing SPC instruction to define the IOC pins as output the OPC instruction must be executed to output the data
72. OW BCLK This figure shows the System Clock Switches from Fast to Slow 2 2 3 2 SINGLE CLOCK MASK OPTION table For Fast clock oscillator only Mask Option name Selected item CLOCK SOURCE 1 FAST ONLY amp USE INTERANL RESISTOR or 2 FAST ONLY amp USE EXTERANL RESISTOR For slow clock oscillator only Mask Option name Selected item CLOCK SOURCE 3 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by mask option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option The backup flag BCF will be set to 1 automatically before the program enters the stop mode This could ensure the Crystal oscillator would start up in a better condition 23 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Halt Normal mode Halt Halt mode OSC active released OSC active Stop Reset Reset release Stop Release Stop mode OSC stop Reset mode Power on Reset Reset pin reset Watchdog timer reset Key reset This figure shows the State Diagram of Single Clock Option 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry PH0 as input When PH0 is changed from H level to L level the content of thi
73. RF X function The operation control for RFC description The meaning of each control bit X5 is shown below peu EI ee the RC oscillation network of RR network of RR ee Md n the RC oscillation network of RT network of RT kaloi o the RC oscillation network of RH network of RH X3 1 enables the 16 bit counter disables the 16 bit counter X4 1 Timer 2 controls the 16 bit counter X3 X4 0 timer 2 to control the 16 bit must be set to 1 when this bit is set to 1 5 1 The 16 bit counter is controlled by 5 0 Disables the pin to control the the signal on CX pin X3 must be 16 bit counter set to 1 when this bit is set to 1 Note X4 and X5 can not be set to 1 at the same time 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx function Rx lt Rx description The content of Rx is loaded to AC and the working register specified by MRW Rx function AC R HL lt Rx description The content of data memory specified by Rx is loaded to AC and data memory specified by HL MWR Rx Ry function AC Rx lt Ry description The content of working register specified by Ry is loaded to AC and data memory specified by Rx 108 tenx technology inc Rev 1 1 2003 11 25 MWR HL function description SRO Rx function description SR1 Rx function description SL0 Rx function description
74. Rintd1 Vi GND 1 200 500 1000 Kohm Rintd2 Vi GND 2 200 500 1000 Kohm Rintd3 Vi GND 3 100 250 500 Kohm RES Pull Down R 1 Vi GND VDD1 1 10 40 100 Kohm Hres2 Vi GND or VDD2 2 10 40 100 Kohm Rres3 Vi GND or VDD2 3 10 40 100 Kohm DC Output Characteristics Name Symb Condition Port Min Typ Max Unit Vohlc jloh 200uA 1 0 8 0 9 1 0 V Output H Voltage Voh2c jloh 1mA 2 1 5 1 8 21 V Voh3c 3 SEG1 35 2 5 3 0 3 5 V Volic jlol 400uA 1 0 2 0 3 0 4 V Output L Voltage 2 2 2 0 3 0 6 0 9 Vol3c lol 6mA 3 0 5 1 0 1 5 V Segment Driver Output Characteristics Name Symb Condition For Min Typ Max Unit Static Display Mode loh 1uA 1 1 0 V Output H Voha2d loh 1uA 2 2 2 V Voltage Voh3d loh 1uA 3 SEG n 3 8 V Volid lol 1uA 1 0 2 V Output L Vol2d lolz1uA 42 0 2 V Voltage Vol3d lol 1uA 3 0 2 V Vohle jloh 10uA 1 1 0 V Output H Voh2e loh 10uA 2 2 2 V Voltage Voh3e loh 10uA 3 COM n 3 8 V Volle llol 10uA 1 0 2 V Output L Vol2e lol 10uA 2 0 2 V Voltage Vol3e lol 10uA 3 0 2 V 1 2 Bias Display Mode 9 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual
75. Rx and AC are binary added the result is loaded to AC The result will not affect the carry flag CF AC lt R HL AC The contents of data memory specified by OHL and AC are binary added the result is loaded to AC The result will not affect the carry flag CF AC Rx lt Rx AC 112 tenx technology inc Rev 1 1 2003 11 25 description ADN HL function description AND Rx function description AND HL function description Rx function description HL function description EOR Rx function description EOR HL function description EOR Rx function description EOR HL TM8722 User s Manual The contents of Rx and AC are binary added the result is loaded to AC and data memory The result will not affect the carry flag CF AC R HL lt R HL AC contents of data memory specified by HL and binary added the result is loaded to AC and data memory specified by HL The result will not affect the carry flag CF lt Rx amp AC The contents of Rx and AC are binary ANDed the result is loaded to AC AC lt R HL 8 AC The contents of data memory specified by HL and AC are binary ANDed the result is loaded to AC AC lt Rx amp AC The contents of Rx and AC are binary ANDed the result is loaded to AC and data memory AC R HL lt R HL amp AC The contents of data memory
76. S AC2 ACO Rx3 R2 Rx1 Rx0 TM2 QHL bite bits Bit4 bits bit2 bito The following table shows the clock source setting for TMR2 1 PHO 00111 PHS 36 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 0 1 0 pO 1 1 FRQ pt o o PA Notes 1 When the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is 11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 error 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 The 7th stage output of the predivider PH9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the
77. X XXXX PC X if AC 3 1 JNZ X 010 XXXX XXXX PC X if AC 0 JNC X 010 1 ex if CF 0 JZ X 011 XXXX XXXX PC X if AC 0 JC X 011 1XXX XXXX XXXX PC eX if CF 1 CALL X 100 OXXX XXXX XXXX STACK lt PC 1 PC X JMP X 101 XXXX XXXX PC X RTS 101 1000 0000 0000 PC lt STACK CALL Return SCC X 101 1001 0X00 OXXX X6 1 BCLK X6 0 PH0 X2 1 0 001 Cch PH10 X2 1 0 010 Cch PH8 2 1 0 100 Cch PH6 SCA X 101 1010 000X 0000 X4 Enable SEF4 C1 4 SPA X 101 1100 000X XXXX X4 Set IOA4 1 Pull Low 0 Set IOA4 1 SPB X 101 1101 000X XXXX X4 Set IOB4 1 Pull Low X3 0 Set IOB4 1 I O SPC X 101 1110 000X XXXX X4 Set IOC4 1 Pull Low Low Level Hold X3 0 Set IOC4 1 I O TMS Rx 110 0000 OXXX XXXX Timer1 lt Rx amp AC TMS HL 110 0001 0000 0000 Timer1 lt T HL TMSX X 110 0010 XXXX XXXX X7 6 11 Ctm FREQ X7 6 10 Ctm PH15 X7 6 01 Ctm PH3 X7 6 00 PH9 X5 0 Set Timer1 Value SPK X 1110 0011 OXXX XXXX X6 1 KEY_S release by scanning cycle X6 0 KEY S release by normal key scanning 133 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Instruction Machine Code Function Flag Remark X5 1 Set all Hi z 1 Set all 1 lOC 2normal X3 0 Set n of 16 IOC KEY SCAN IOC KEY SCAN TM2 Rx 1110 0100 OXXX XXXX Timer2 lt Rx
78. address in the table ROM The LCD outputs could be turned off without changing the segment data Executed SF2 4h instruction could turn off the display simultaneously and executed RF2 4h could turn on the display with the patterns before turned off These two instructions will not affect the content stored in the latch circuitry When the LCD is turned off by executing RF2 4h instruction the program could still execute LCT LCB LCP and LCD instructions to update the content in the latch circuitry and the new content will be outputted to the LCD while the display is turned on again In stop state all COM and SEG outputs of LCD driver will automatically switch to the GND state to avoid the DC voltage bias on the LCD panel 87 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 4 1 3 2 Relative Instructions 1 LCT Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz 2 LCB Lz Ry Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to LCD latch specified by Lz The to DBUSH are all 0 when the input data of the data decoder is 0 3 LCD Lz HL Transfers the table ROM data specified by HL directly to DBUSA to DBUSH without passing through the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry The data of the RAM and accumulator AC are transferred directly to DBUSA to DBUS
79. affected AC Rx AC The contents of Rx and AC are binary added the result is loaded to AC and data memory Carry flag CF will be affected 111 tenx technology inc Rev 1 1 2003 11 25 HL function description SUB Rx function description SUB HL function description SUB Rx function description SUB HL function description ADN Rx function description ADN HL function description ADN Rx function TM8722 User s Manual AC R HL lt R HL AC The contents of data memory specified by HL and AC are binary added the result is loaded to AC and data memory specified by HL Carry flag CF will be affected lt Rx AC B 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected lt R HL AC B 1 The content of AC is binary subtracted from content of data memory specified by HL the result is loaded to AC Carry flag CF will be affected AC Rx lt 1 The content of AC is binary subtracted from content of Rx the result is loaded to AC and Rx Carry flag CF will be affected R HL lt R HL AC B 1 The content of AC is binary subtracted from content of data memory specified by HL the result is loaded to AC and data memory specified by HL Carry flag CF will be affected lt The contents of
80. al clear mode VDD 1 in low active GND VDD COM1 in high active GND VDD All LED driver J ec C c C C v outputs GND ii Normal operation mode mu VDD COM1 in low active GND VDD COM1 in high active GND RS VDD Unlighted LCD driver outputs GND m VDD Lighted LCD driver outputs GND 92 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual iii Display Turn Off m VDD COM1 in ud GND VDD COMA in tas D6J 0 II II II C L LDH high active E GND n VDD All LED driver O outputs GND iv STOP Mode VDD 1 in low active GND aes VDD COM1in L L LLL lIoI ILCGCG X IXI IQ C 202 0 uu high active GND All LED driver outputs GND Figure 2 39 Static LED Waveform 4 2 2 1 2 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode VDD 1 2 in low active 20 0 Jh GND VDD COM1 COM2 J0 in high active ___ GND QO gt VDD All LED driver I zDsee vc outputs GND 93 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual ii Normal operation mode alternating frquency COM1 VDD in low active mode GND COM2 VDD in low active mode GND COM1 VDD in high active mode GND COM2 VDD i
81. al output port by executing OPAS instruction IOA port must be defined as the output mode before executing OPAS instruction 1 BITO and BIT1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS BITS of the port delivers pulses Shown below is a sample program using the OPAS instruction 1 LDS OAH 0 2 SPA LDS 1 5 3 1 1 Bit 0 output shift gate open 4 SRO 1 Shifts bit 1 to bit 0 5 OPAS1 1 Bit 1 output 6 SRO 1 Shifts bit2 to bit 0 7 1 1 Bit 2 output 8 SRO 1 Shifts bit 3 to bit 0 9 OPAS 1 1 Bit 3 output 10 1 1 Lastdata 11 OPAS1 0 Shift gate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 10 11 0 5 2 1 1 Bit0 for Rx 5 Bit1 for Rx 5 Bit2 for Rx 5 Bit3 for Rx 5 A M IOA2 M M 7 IOA3 IOA4 M H M i BCLK 2 If IOA1 pin is used as the CX pin for function and the other pins IOA2 IOA3 are used for normal IO pins IOA1 pin must always be defined as the output mode to avoid the influence from the CX when the input chattering prevention function is active On the other hand the RFC counter can receive the signal changes on IOA1 when the RFC counter is enabled 67 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 3 5 2 IOB PORT IOB1 IOB4 pins are MUX
82. alt release enable flag TMSX 3Fh Setvalue for timer 1 is 3Fh and the clock source is PHY SCC 40h _ Set the clock source of the frequency generator as BCLK FRQX 2 3 FREQ BCLK 4 2 setting value for the frequency generator 15 3 and duty cycle is 1 2 ALM 1COh FREQ signal is outputted This instruction must be executed after the FRQ related instructions HALT for the halt release caused by timer 1 Halt released ALM 0 Stop the buzzer output 3 5 INPUT OUTPUT PORTS Three I O ports are available in TM8722 IOA and IOC Each port is composed of 4 bits and has the same basic function When the I O pins are defined as non IO function by mask option the input output function of the pins will be disabled 65 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 3 5 1 IOA PORT IOA1 IOA4 pins are MUX with CX SEG24 RR SEG25 RT SEG26 and SEG27 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG24 IOA1 CX 2 IOA1 SEG25 IOA2 RR 2 IOA2 SEG26 IOA3 RT 2 IOA3 SEG27 IOA4 RH 2 IOA4 In initial reset cycle the IOA port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined as the input mode
83. and data memory specified by HL lt Ry D CF D represents an immediate data The contents of Ry D and CF are binary ADDed the result is loaded to AC The carry flag CF will be affected D FH AC Rx Ry D CF D represents an immediate data The contents of Ry D and CF are binary ADDed the result is loaded to AC and working register Ry The carry flag CF will be affected D FH lt D B CF D represents an immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC The carry flag CF will be affected 114 tenx technology inc Rev 1 1 2003 11 25 SBCI D function description ADDI Ry D function description ADDI Ry D function description SUBI Ry D function description SUBI Ry D function description ADNI Ry D function description TM8722 User s Manual D 0H FH AC Rx lt Ry D B CF D represents an immediate data The CF and immediate data D are binary subtracted from working register Ry the result is loaded to AC and working register Ry The carry flag CF will be affected D FH lt Ry D D represents an immediate data The contents of Ry and D are binary ADDed the result is loaded to AC The carry flag CF will be affected D FH AC lt Ry D D represents an immediate data The contents of Ry and
84. and the rest LCD LED driver output pins for LCD LED driver Refer to 4 1 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD LED driver output pins SEG are defined as DC output the output data on this port will not be affected while the program entered stop mode or LCD turn off mode VDD P SEG Figure 5 1 CMOS Output Type Figure 5 2 P Open Drain Output Type 4 1 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 1 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION Explained below is how the LCD driver section operates when the instructions are executed QHL gt amp RAM data mem De decoder Data bus Strobe data Dacoder f strobe LO to L4 related E instruction RA cos circuit 175 DBUSA DBUSH segments Segment PLA Figure 5 3 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LO to L4 decoder to decode the Lz specified data in the LCD related instructions which specifies the strobe of the latch circuit e Multiplexer to select 1 2duty 1 3duty 1 4duty 1 5duty LCD driver circuitry 85 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Segment PLA circuit connected between data decoder LO to L4 decoder and
85. ased In the same manner when SRF4 SRF3 and SRF5 are set to 1 the input signal change at the input mode pins of IOC port and the signal changed on INT pin causes the stop mode to be released respectively Example This example illustrates the stop mode released by port IOC KI1 4 and INT pin Assume all of the pins in IOD and IOC have been defined as input mode PLC 25h Reset the HRF2 and HRF5 47 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual SHE 24h HEF2 and is set so that the signal change at INT or Kl1 4 pin causes start condition flag 4 or 8 to be set SCA 10h SEF4 is set so that the signal changes at port IOC cause the start conditions SCF1 to be set SRE ObOh SRF7 5 4 are set so that the signal changes at Kl1 4 pins port and INT pin cause the stop mode to be released STOP Enter the stop mode STOP release MSC 10h Check the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC that causes the stop mode to be released MCX 12h Check the signal change at KI1 4 pins that causes the stop mode to be released 2 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM8722 when LCD is operating During the halt mode the program memory ROM is not in operation and only the oscillator circuit pre divider circuit sound circuit port chatte
86. atrix scanning frequency Hz frame frequency x LCD duty cycle x 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for key matrix is 320Hz 32 x 5 x 2 80 tenx technology inc Rev 1 1 2003 11 25 KI2 TM8722 User s Manual Rising edge strobe k i PLC 20h ey scanning enable signal IPC nitial Reset Interrupt 5 request This figure shows the organization of Key matrix scanning input Example SPC Ofh Disable all the pull down device on internal IOC port Set all of the IOC pins as output mode SPK 10h Generate HALT released request when key depressed scanning all columns simultaneous in each cycle PLC 20h Clear HRF5 SHE 20h Set HEF5 HALT wait for the halt release caused by key matrix MCX 10h Check SCF8 SKI JBO ski_release ski_release IPC 10h 4 input latch state JBO ki release 81 tenx technology inc Rev 1 1 2003 11 25 JB1 JB2 JB3 release SPK PLC CALL scan again IPC JBO wait scan again HALT PLC 20h RTS ki2 release ki3 release ki4 release 40h 20h wait scan again 10h ki1 seg 4fh 20h wait scan again 10h kil seg16 TM8722 User s Manual Check key depressed on K1 column Clear HRF5 to avoid the false HALT released Waiting for the next key matrix scanning cycle wait
87. bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 PH5 When the Li battery application is used the 1 2 VDD voltage generated by the halver operation is supplied to the circuits which are not related to input output operation 3 3 4 Alternating Frequency for LCD The alternating frequency for LCD is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ Each are MUXed with and IOB4 by mask option respectively BZB and BZ pins are versatile output pins with complementary output polarity When buzzer output function combined with the clock source comes from the frequency generator this output function may generate melody sound effect or carrier output of remote control MASK OPTION table Mask Option name Selected item SEG30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 3 BZ 63 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 95 MUX m s ALM X X5 X0 peg This figure shows the organization of the buzzer output 3 4 1 BASIC BUZZER OUTPUT The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output pin or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output any combination of one signal of FREQ PH3 4096Hz PH4 2048Hz PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz PH12 8Hz PH13 4Hz PH14 2Hz PH15 1Hz The ALM
88. cription JNC X function description JZ X function description JC X function description JMP X function description CALL X function description RTS function description TM8722 User s Manual If bit2 of AC is 1 jump occurs the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X if AC3 1 If bit3 of AC is 1 jump occurs the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X if AC 0 If the content of AC is not 0 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X if CF 0 If the content of CF is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X if AC 0 If the content of AC is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X if CF 1 If the content of CF is 1 jump occurs the PC increases by 1 The range of X is from 000H to 7FFH Program counter jumps to X Unconditional jump The range of X is from 000H to 7FFH STACK lt 1 Program counter jumps to X A subroutine is called The range of X is from 000H to 7FFH STACK return from subroutine occurs 124 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 5 9 MISCELLANEOUS INSTRUCTIONS SCC X function Setti
89. ction will change the clock source BCLK of the system clock generator SCG to the fast speed oscillator CF clock and the system clock selection flag CSF is set to 1 For the operation of the system clock generator refer to 3 3 2 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF indicates the operating status of the watchdog timer 3 Overflow flag of 16 bit counter of RFC RFOVF The overflow flag of 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of RFC occurs The flag will reset to 0 when this counter is initiated by executing SRF instruction The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 4 STS4 43 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Bit 3 Bit 2 Bit 1 Bit 0 Reserved The overflow Watchdog timer System clock of 16 bit counter of Enable flag WDF selection flag RFC RFVOF CSF Read only Read only Read only Read only 2 14 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF11 will be set to 1 in STOP mode when the following conditions are met A high level signal comes from the OR ed output of the pins defined as input mode in IOC port which causes the stop release flag of IOC port CSR to output and stop release enable flag 4 SRF4 is set beforehand
90. d VDD1 Note 2 At the initial clear mode the backup flag BCF is set When the backup flag is set the oscillator circuit becomes large in inverter size and the oscillation conditions are improved but the operating current is also increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 2 1 2 LI BATTERY POWER SUPPLY Operating voltage range 2 4V 3 6V For different LCD bias application the connection diagrams are shown below 2 1 2 1 NO BIAS AT LI BATTERY POWER SUPPLY Application circuit Z 2 MM Ld 11 B T 8722 MASK OPTION table Mask Option Selected item POWER SOURCE 2 3V BATTERY OR HIGHER LCD BIAS 3 NO BIAS Note 1 The input output ports operate between GND and VDD2 14 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 1 2 2 1 2 BIAS LIBATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 SW1 BAK logic GND MASK OPTION table Mask Option name Selected item POWER SOURCE 2 3V BATTERY OR HIGHER LCD BIAS 2 1 2 Note 1 The input output ports operate between GND and VDD2 Note 2 At th
91. e GND nYC Nh 1 VDD All LED driver J p s e C Le 5 2 outputs JJ 5 00 0 GND Figure 2 42 1 4 duty LED Waveform 4 2 5 1 5 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode lighting VDD 2 3 4 5 in low active VDD COM1 2 3 4 5 high active GND VDD All LED driver outputs GND 100 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual ii Normal operation mode frame period VDD COMI in Low active GND VDD in Low active eme GND VDD in Low active n GND VDD COM4 in Low active skos VDD COMS5 in Low active 55 80 VDD COMI in High active Basics GND VDD in High active VDD in High active GND I VDD COM4 in High active ssnst GND VDD COMS5 in High active GND segnments on 1 2 3 45 C VDD with unlighted sides segnments on COM1 with o VDD lighted sides LL ll d Dopo cU uem GND segnments on COM2 with gt 1 t VDD lighted sides J fo kJ GND segnmentsonCOM3wih 77 J 7
92. e If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state MASK OPTION table Pull low function option 70 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Mask Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE The low level hold function will not be available when pull low function is not actived Low level hold function option Mask Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO USE 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to IOC4 pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOC port are defined as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry FAS IEFO Interrupt HRFO t SPC 4 Edge S reques SPC 8 detect R IOC1 IOC2 edge dectect amp Q SCF1 released IOC3 chattering request 064 chattering
93. e if these instructions have not been executed and the RR RT RH pins output 0 state at this time To get a better oscillation clock from the CX pin activate the output pin for each RC network before the counter is enabled When the overflow flag RFOVF 1 check by MSD instruction the 16bits counter will be disable to 0000h or not by mask option Mask Option name Selected item OVERFLOW DISABLE COUNTER 1 USE OVERFLOW DISABLE COUNTER 2 NO USE If select NO USE the RFOVF willn t be hold to 1 and counter willn t be disable to 0000h RFOVF just only be used as 17th bit of the counter here The RFC function provides 3 modes for the operation of the 16 bit counter Each mode will be described in the following sections 3 8 2 Enable Disable the Counter by Software The clock input of the 16 bit counter comes from the CX pin and is enabled disabled by the S W When SRF 8h instruction is executed the counter will be enabled and will start to count the signals on the CX pin The counter will be disabled when SRF 0 instruction is executed Executing MRF1 4 instructions may load the result of the counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically Example If you intend to count the clock input from the CX pin for a specified time period you can enable the counter by executing SRF 8 i
94. e initial clear mode the backup flag BCF is set When the backup flag is set the internal logic operated on VDD2 and the oscillator circuit becomes large in driver size At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 3 5 Note 3 The VDD1 level 1 2 VDD2 at the off state of SW1 is used as an intermediate voltage level for the LCD driver 2 1 2 3 1 3 BIAS AT LI BATTERY POWER SUPPLY The backup flag BCF must be reset after the operation of the halver circuit is fully stabilized and a voltage of approximately 1 2 VDD2 appears on the VDD1 pin Backup flag BCF BCF 0 15 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Internal logic MASK OPTION table Mask Option name Selected item POWER SOURCE 2 BATTERY OR HIGHER LCD BIAS 1 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup is set When the backup is set the internal logic operated on VDD2 and the oscillator circuit becomes large in inverter size At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup refer to 3 5 Note 3 The VDD1 level 1 2 VDD at the off state of SW1 is used as an intermediate voltage lev
95. ed in scanning interval If the interrupt enable flag 5 IEF5 is set to 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 3 1 1 2 Internal interrupt factor The internal interrupt factor involves the use of timer 1 TMR1 timer 2 TMR2 RFC counter and the pre divider 1 Timer1 2 TMR1 2 interrupt request An interrupt request signal 4 is delivered when timer1 2 TMR1 2 underflows In this case if the interrupt enable flag 1 4 IEF1 4 is set interrupt 1 4 is accepted and the instruction at address 18H 20H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set interrupt 3 is accepted and the instruction at address 1CH is executed automatically 3 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is delivered when the 2 falling edge applied on CX pin and 16 bit counter stops to operate In this case if the interrupt enable flag6 IEF6 is set interrupt 6 is accepted and the instruction at address 28H is executed automatically 3 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the 55 tenx technology inc Rev 1 1 200
96. ed with ELC SEG28 ELP SEG29 BZB SEG30 and SEG31 pins respectively by mask option MASK OPTION table Mask Option name Selected item SEG28 IOB1 ELC 2 IOB1 SEG29 IOB2 ELP 2 IOB2 SEG30 IOB3 BZB 2 IOB3 SEG31 IOB4 BZ 2 IOB4 following figure shows the organization of IOB port Initial clear Initial clear SPB2 Initial clear SPB 4 aay Initial clear SPB 8 IOB4 SPB 10 Note M O is mask option Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may output the content of specified data memory to the pins defined as output mode the other pins which are defined as the input will still be input Executed IPB instructions may store the signals applied on the IOB pins into the specified data memory When the pins are defined as the output executing IPB instruction will save the data stored in the output latch into the specified data memory Before executing SPB instruction to define the I O pins as output the OPB instruction must be executed to output the data to the output latches This will prevent the chattering signal on the I O pin when the I
97. el for LCD driver 2 1 3 EXTV POWER SUPPLY Operating voltage range 3 6V 5 4V For different LCD bias application the connection diagrams are shown below 2 1 3 1 NO BIAS AT EXT V BATTERY POWER SUPPLY Internal logic 16 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V LCD BIAS 3 NO BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased 2 1 3 2 1 2 BIAS AT EXT V POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V LCD BIAS 2 1 2 Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset Note 3 At the backup flag set mode the operating current is increased Therefore the backup flag must be reset unless otherwise required Internal logic GN 17 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 1 3 3 1 3 BIAS AT EXT V POWER SUPPLY MASK OPTION table Mask Option name Selected item POWER SOURCE 1 EXT V LCD BIAS 1 1 3 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 At the initial clear mode the backup flag BCF is reset
98. elected item lt gt BCLK FOR FAST ONLY BCLK lt gt BCLK FAST ONLY BCLK 4 1 2 lt gt BCLK FAST ONLY 3 BCLK 8 lt gt BCLK FAST ONLY 4 BCLK 16 2 2 5 SYSTEM CLOCK GENERATOR For the system clock the clock switch circuit permits the different clock input from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator SGC The basic system clock is shown below SCLK T1 T2 T3 T4 4 Machine Cycle Instruction N Cycle 25 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 3 PROGRAM COUNTER PC This is an 11 bit counter which addresses the program memory ROM up to 2048 addresses The program counter PC is normally increased by 1 with every instruction execution PC 1 When executing JMP instruction subroutine call instruction CALL interrupt service routine or reset occurs the program counter PC loads the specified address corresponding to table 2 1 PC specified address shows in Table 2 1 When executing a jump instruction except JMP and CALL the program counter PC loads the specified address in the operand of instruction
99. emory specified by Rx Bit 3 RFC 11 Bit 2 RFC 10 Bit 1 RFC 9 Bit lt RFC 8 lt 15 12 Loads the highest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 15 Bit lt RFO 14 Bit lt RFC 13 Bit lt RFC 12 5 5 CPU CONTROL INSTRUCTIONS NOP function description no operation no operation 118 tenx technology inc Rev 1 1 2003 11 25 HALT function description STOP function description SCA X function description SIE X function description TM8722 User s Manual Enters halt mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to IOC 3 The halt release condition specified by SHE instruction is met When an interrupt is accepted to release the halt mode the halt mode returns by executing the RTS instruction after completion of interrupt service Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signal KI1 4 is H L LED LCD in scanning interval 2 A signal change in the INT pin 3 One of the signals on IOC port is H The data specified by X causes the halt mode to be released The signal change at port IOA IOC is specified
100. flag 1 Disable INT powerful pull low X2 1 Enables the segment output X1 1 Resets the DED flag Refer to 2 12 3 for detail 1 Disables the re load function of timer 2 X7 6 is reserved Pulse control The pulse corresponding to the data specified by X is generated 1 Halt release request flag HRFO caused by the signal at I O port C is reset X1 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 129 tenx technology inc Rev 1 1 2003 11 25 X2 X3 X4 X5 X8 TM8722 User s Manual 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset 1 Halt release request flag HRF3 caused by overflow from the predivider is reset 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 1 Halt release request flag HRF5 caused by the signal change to H L LED LCD on KI1 4 in scanning interval is reset 1 Halt release request flag HRF6 caused by overflow from the counter is reset 1 The last 5 bits of the predivider 15 bits are reset When executing this instruction X3 must be set to 1 130 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Appendix A TM8722 Instruction Table
101. gy inc Rev 1 1 2003 11 25 TM8722 User s Manual Interrupt enable flags 0 to 3 IEF0 6 Alarm output ALARM DC 0 Pull down flags in port 1 with pull down resistor Input output ports PORT port chattering clock 10 panel driver pumping clock Celp duty cycle is 3 4 source and duty cycle panel driver clearing clock Celc PH8 duty cycle is 1 4 source and duty cycle Frequency generator clock Cfq PH0 duty cycle is 1 4 output source and duty cycle is inactive Resistor frequency converter Inactive RR RT RH output 0 LCD driver output All lighted mask option Timer 1 2 Inactive Watchdog timer WDT Reset mode WDF 0 BCLK au clock slow speed clock in ual clock option Input mode Notes PH3 the 3rd output of predivider PH10 the 10th output of predivider Mask option can unlighted all of the LCD output 3 2 3 IOC Port Key Matrix RESET Key reset function is selected by mask option When IOC port or key matrix scanning input 4 is in used the 0 signal applied to all these pins that had be set as input mode in the same time KI1 4 pins need to wait scanning time reset signal is delivered MASK OPTION table or KI pins are used as key reset Mask Option name Selected item IOC1 Kl1 FOR KEY RESET 1 USE IOC2 KI2 FOR KEY RESET 1 USE
102. he last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurred disable the re load function by executing RF2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 Setthe initiate value of TMR2 to 52 and start counting 2 Enable the TMR2 halt release or interrupt function 3 Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue counting even if TMR2 underflows 4 When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase the counting value to count the underflow times 5 When halt release or interrupt occurs for the 7 time reset the DED flag 6 When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed In the following example S W enters the halt mode to wait for the underflow of TM2 LDS 0 0 initiate the underflow counting register PLC 10h SHE 10h enable the halt release caused by TM2 SRF 19h enable RFC and controlled by TM2 TM2X 34h initiate the TM value 52 and clock source is 9 SF2 3h enable the re load function and set DED flag to 1 RE LOAD HALT INC 0 increase the underflow counter PLC 10h clear HRF4 38 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual LDS 201 7 SUB 0 when halt is released for the 7 time reset DED flag JNZ NOT RESET DED HF2 2 DED flag NOT RESET DED
103. ied by Rx D FH AC lt Rx The content of Rx is loaded to AC lt R HL content of data memory specified by is loaded to Rx AC H T HL The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx Rx lt H T HL HL lt HL 1 The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx and then is increased in HL Rx lt L T HL The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx Rx AC lt L T HL HL HL 1 117 tenx technology inc Rev 1 1 2003 11 25 description MRF1 Rx function description MRF2 Rx function description MRF3 Rx function description MRF4 Rx function description TM8722 User s Manual The lower nibble data of Table ROM specified by HL is loaded to the data memory specified by Rx and then incremented the content of HL Rx lt 0 Loads the lowest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 3 Bit 2 RFC 2 Bit 1 RFC 1 Bit 0 RFC 0 Rx AC RFC 7 4 Loads the 2 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 7 Bit 2 RFC 6 Bit 1 RFC 5 Bit 0 RFC 4 Rx AC lt RFC 11 8 Loads the 3 nibble data of 16 bit counter of RFC to AC and data m
104. ill be disabled and will stop counting the CX clock at the same time This mode can set an accurate time period with which to count the clock numbers on the CX pin For a detailed description of the operation of TMR2 please refer to 2 12 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 18h SRF 02h SRF control Counter active Timer 2 Content of the counter CX Halt release request 4 counter starts Counting stops caused to count by the Timer 2 underflow This figure shows the timing of the RFC counter controlled by timer 2 Example In this example use the RT network to generate the clock source SRF 1 Build up the RT network and enable the counter controlled by TM2 SHE 10h enable the halt release caused by TM2 TM2X 20h set the PH9 as the clock source of TM2 and the down count value is 20h HALT PLC 10h Clear the halt release request flag of TM2 MRF1 10h read the content of the counter 77 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual MRF2 11h MRF3 12h MRF4 13h 3 8 4 Enable Disable the Counter by CX Signal This is another use for the 16 bit counter previous modes CX is the clock source of the counter and the program must specify a time period by timer or subroutine to control the counter In this mode however the counter has a different operation method CX pin becomes the controlled signal to enable
105. illator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock and the clock source for other functions will still come from XT clock Halt mode stop mode or SLOW instruction execution will stop this oscillator and the system clock BCLK will be switched to XT clock There are 3 type oscillators can be used in slow clock oscillator selected by mask option 2 2 2 1 RC OSCILLATOR WITH EXTERNAL RESISTOR CF CLOCK This kind of oscillator could only be used in FAST only option the fast clock source of dual clock mode cant use this oscillator When this oscillator is used the frequency option of the RC oscillator with internal RC is not cared MASK OPTION table Mask Option name Selected item CLOCK SOURCE 2 FAST ONLY amp USE EXTERNAL RESISTOR MASK OPTION table Mask Option name Selected item FAST CLOCK TYPE FOR FAST ONLY OR DUAL 1 or 2 don t care 20 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual XTOUT External Resistor 2 2 2 2 RC OSCILLATOR WITH INTERNAL RESISTOR CF CLOCK Two kinds of the frequencies could be selected in this mode of oscillator the one is 250KHz and the other is 500KHz When this oscillator is used leave CFOUT and two pins opened This kind of oscillator could be used in F
106. in this can also be used as another temperature sensor or can even be left floating These CX RR RT and RH pins are MUXed with IOA1 SEG37 to 4 SEG40 respectively and selected by mask option Mask Option name Selected item SEG24 IOA1 CX 3 CX SEG25 IDA2 RR 3 RR SEG26 IOA3 RT 3 RT SEG27 IOA4 RH 3 RH 3 8 1 RC Oscillation Network The RFC circuitry may build up 3 RC oscillation networks through RR RT or RH and CX pins with external resistors Only one RC oscillation network may be active at a time When the oscillation network is built up executing SRF 1h SRF 2h SRF 4h instructions to enable RR RT RH networks respectively the clock will be generated by the oscillation network and transferred to the 16 bit counter through the CX pin It will then enable or disable the 16 bit counter in order to count the oscillation clock Build up the RC oscillation network 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 75 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins for RC networks respectively The RR RT RH pins will become of a tri state type when these networks are disabled 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and 16 bit counter The RC oscillation network will not operat
107. ing period must longer than key matrix scanning cycle Read input latch state Only enable SEG16 scanning output Clear HRF5 to avoid the false HALT released Wait for time over halt LCD clock cycle to sure Read input latch state 82 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual CHAPTER 4 LCD LED DRIVER OUTPUT 4 1 LCD DRIVER OUTPUT The number of the LCD driver outputs in TM8722 is 35 segment pins with 5 common pins SEG1 23 output pins could also be used as DC output ports mask option If more than one of LCD driver output pin was defined as DC output the following mask option must be selected MASK OPTION table When more than one of SEG and COM pins have been used to drive LCD panel Mask Option name Selected item LCD LED ACTIVE TYPE 1 LCD When all of SEG1 23 had been used for DC output port amp SEG24 35 not used for SEG Mask Option name Selected item LCD ACTIVE TYPE 4 O P During the initial reset cycle all of LCD s lighting system may be lighted or unlighted by mask option All of the LCD output will keep the initial setting until the LCD relative instructions are executed to change the output data MASK OPTION table Mask Option name Selected item LCD DISPLAY IN RESET CYCLE 1 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 1 LCD LIGHTING SYSTEM IN TM8722 There are several LCD lighting systems could be selected by mask
108. instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope of the modulation output Note 1 The high frequency clock source should only be one of PH3 4 PH5 or FREQ and the lower frequency may be any all of the combinations from PH10 PH15 2 The frequencies in corresponding to the input clock of the pre divider PHO is 32768Hz 3 The BZ and BZB pins will output DCO after the initial reset Example Buzzer output generates a waveform with 1KHz carrier and PH15 PH14 envelope LDS 20h ALM 70h Output the waveform 64 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual In this example the BZ and BZB pins will generate the waveform as shown in the following figure PH15 1HZ m L T L T LL PH5 1KHz BZ 7 BZB L L 8 1 PLIL LU LIL Bzz 3 4 2 THE CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver the waveform for the IR remote controller For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example SHE 2 Enable timer 1 h
109. ion Set Reset stop release enable flag description X4 1 The SRF4 is set so that the stop mode is released by the signal changed on IOC port X5 1 The SRF5 is set so that the stop mode is released by the signal changed on INT pin X7 1 The SRF6 is set so that the stop mode is released by the signal is H l L LED LCD on 74 in scanning interval X6 X3 0 is reserved FAST function Switches the system clock to CFOSC clock description Starts up the CFOSC high speed osc and then switches the system clock to high speed clock SLOW function Switches the system clock to XTOSC clock low speed osc description Switches the system clock to low speed clock and then stops the CFOSC MSB Rx function AC Rx SCF1 BCF2 BCF description The SCF1 SCF2 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 NA Start condition Start condition Backup flag flag 2 flag 1 BCF SCF2 SCF1 Halt release caused Halt release The backup by SCF4 5 6 7 8 9 caused by the mode status IOC port 120 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual MSC Rx function AC Rx lt SCF4 7 description The SCF4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning o bit after execution of this instruction are as follows Bit 3
110. ion in direct and index addressing mode Single bit manipulation set reset decision for branch Various conditional branch 16 working registers and manipulation Table look up LCD driver data transfer 3 Memory capacity ROM capacity 2048 x 16 bits RAM capacity 128 x 4 bits 4 LCD LED driver output 5 outputs and 35 segment outputs up to drive 175 LCD LED segments 1 2 Duty 1 3 Duty 1 4 Duty or 1 5 Duty for both LCD LED drivers is selected by mask option 1 2 Bias or 1 3 Bias for LCD driver is selected by mask option e Single instruction to turn off all segments All segment outputs could be defined as CMOS or P_open drain output type by mask option 5 Input output ports PortlOA 4 pins with internal pull low muxed with SEG24 27 PortlOB 4 pins with internal pull low muxed with SEG28 31 Port IOC 4 pins with internal pull low low level hold muxed with SEG32 35 IOC port had built in the input signal chattering prevention circuitry 6 8level subroutine nesting 7 Interrupt function External factors 3 INT pin Port IOC amp KI input Internal factors 4 Pre Divider Timer1 Timer2 amp RFC 8 Built in EL panel driver ELC ELP Muxed with SEG28 SEG29 9 Built in Alarm clock or single tone melody generator e BZB BZ Muxed with SEG30 SEG31 3 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 10 11 12 13 1
111. k alternating frequency LCD frame frequency 1 SLOW 21Hz LCD frame frequency 2 TYPICAL 42Hz LCD frame frequency 2 FAST 85Hz LCD frame frequency 2 O P 0Hz LCD not used The LCD alternating frequency in 1 4 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz LCD frame frequency 2 O P OHz LCD not used The LCD alternating frequency in 1 5 duty type Mask Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 25Hz LCD frame frequency 2 TYPICAL 51Hz LCD frame frequency 2 FAST 102Hz LCD frame frequency __ 2 O P OHz LCD not used The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments System Driving LCD Segments 05 W3bias 1 4duy 140 1 5 duty 475 j When choosing the LCD frame frequency it is recommended to choice the frequency that higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 84 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 4 1 2 DC OUTPUT TM8722 permits all LCD LED driver output pins to be defined as CMOS type DC output or P open drain DC output ports by mask option In this case it is possible to use some LCD LED driver output pins for DC output
112. k source comes form pre divider long at least 3 2 1 POWER ON RESET TM8722 provides a power on reset function If the power VDD is turned on or power supply drops below 0 6V it will generate a power on reset signal Power on reset function can be disabled by mask option MASK OPTION table Mask Option name Selected item POWER ON RESET 1 USE POWER ON RESET 2 NO USE Note When the power on reset option is selected connected a capacitor between VDD and GND is necessary 3 2 2 RESET PIN RESET When H level is applied to the reset pin the reset signal will be issued There is a built in pull down resistor on this pin It is recommended to connect a capacitor 0 1uf between RESET pin and VDD This connection will prevent the bounce signal on RESET pin Once a 1 signal applied on the RESET pin TM8722 will not release the reset cycle until the signal on RESET pin returned to 0 After the signal on reset pin is cleared to 0 TM8722 begins the internal reset cycle and then release the reset status automatically The following table shows the initial condition of TM8722 in reset cycle Program counter PC Address 000H Start condition flags 1 to 7 SCF1 7 Backup flag BCF Stop release enable flags SRF3 4 5 7 4 5 7 Switch enable flags 4 SEF3 4 Halt release request flag HRF 0 6 Halt release enable flags 1 HEF1 6 to 3 1 Ag Li version 0 EXTV version 58 tenx technolo
113. l enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the content of the timer will be cleared Once the watchdog timer is enabled the timer will be paused when the program enters the 60 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual halt mode or stop mode When the TM8722 wakes up from the halt or stop mode the timer operates continuously It is recommended to execute SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute SF 10h instruction periodically to prevent the timer overflowed The overflow time interval of watchdog timer is selected by mask option MASK OPTION table Mask Option name Selected item WATCHDOG TIMER OVERFLOW TIME INTERVAL 1 8 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 2 64 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 3 512 x PH10 Note timer overflow time interval is about 16 seconds when 32 768KHz 3 3 CLOCK GENERATOR 3 3 1 FREQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator BCLK 8 51 Programmable Du
114. loading function set 1 prevents TM8722 from malfunctioning especially where a battery with high internal impedance such as Li battery or alkali battery is used During back up mode the 32 768KHz Crystal oscillator will add an extra buffer in parallel and switch the internal power BAK from VDD1 to VDD2 Li power option only In this condition all of the functions in TM8722 will work under VDD voltage range this will cause TM8722 to get better noise immunity For shorten the start up time of 32 768KHz Crystal oscillator TM8722 will set the BCF to 1 during reset cycle and reset to 0 after reset cycle automatically in Ag and Li power mode option In EXT V power mode option however BCF is set to 1 by default setting and can not be reset to 0 and BCF will be reset to O by default setting during normal operation Table 3 1 The back up flag status in different conditions Ag option Reset cycle After reset cycle SF 2 executed BCF 1 BCF 1 RF 2 executed BCF 0 BCF 0 For low power consumption application reset BCF to 0 is necessary the 32 768KHz Crystal oscillator operates with a normal buffer only so switch the internal power BAK to VDD1 Li power option only In this condition only peripheral circuitry operates under VDD voltage range the other functions will operate under 1 2 VDD voltage range In Ag and EXT V power options the internal power BAK will not be affected by the setting of BCF Wi
115. n high active mode GND LED driver outputs VDD for LED segments on COM with lighted sides GND LED driver outputs for LED segments u on COM with lighted sides tO o GND LCD driver outputs VDD for LCD segments on COM1 COM2 with lighted sides LCD driver outputs FWD for LCD segments on COM1 COM2 with unlighted sides GND iii Display Turn Off VDD COM1 COM2 in low active 2 0 7 H e D D GND VDD COM1 COM2 D0o LJ L 000 in high active e GND TA e VDD All LED driver outputs GND 94 tenx technology inc Rev 1 1 2003 11 25 STOP Mode COM1 COM2 in low active COM1 COM2 in high active ALL LED driver outputs Figure 2 40 Duplex 1 2 duty LED Waveform 4 2 3 1 3 DUTY LIGHTING SYSTEM FOR LED DRIVER i Initial clear mode COM1 COM2 sm in low active COM 1 COM2 in high active All LED driver outputs 95 TM8722 User s Manual VDD GND VDD GND VDD GND tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual ii Normal operation mode alternating frquency gt COM1 VDD in low active mode GND COM2 VoD in low active mode GND COM3 VDD in low active mode GND COM 1
116. n low active MASK OPTION table When COM pins have been used to drive high active LED panel Mask Option name Selected item LCD LED ACTIVE TYPE 2 LED HIGH ACTIVE When COM pins have been used to drive low active LED panel Mask Option name Selected item LCD LED ACTIVE TYPE 3 LED LOW ACTIVE The following schema will illustrate the application difference between high active mode and low active mode 1 High Active Mode SEG1 s2 ss 55 S7 ss 2 Low Active Mode Note Due to the sink current capability if all segment more than 8 turn on at Low Active Mode in the 90 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual same time the IC may be burn down if one segment have 5mA then eight segment have 40mA Mask option can also be used to select the alternating frequency All of the LED alternating frequencies based on the clock source frequency of the predivider are 32768Hz The LED alternating frequency 1 2 duty mode LED duty cycle 1 2 dut frequency The LED alternating frequency 1 3 duty mode LED duty cycle 1 3 duty Mask option frequenc The LED alternating frequency in 1 4 duty mode LED duty cycle 1 4 dut Mask option frequency The LED alternating frequency in 1 4 duty mode LED duty cycle 1 5 dut Mask option LED alternating wa 205
117. nable the halt Halt release release caused by release caused by release caused by condition pre divider overflow INT pin HRF2 TM1 underflow HRF3 HRF1 When the halt release enable flag 6 HEF6 is set a finish signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF1 to HEF4 are set to 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMR1 the signal change at the INT pin an overflow signal from the pre divider and an underflow signal from TMR2 H signal from OR ed output of 4 latch signals When the stop release enable flag 5 SRF5 and the HEF2 are set the signal change at the INT pin can cause the stop mode to be released When the stop release enable flag 7 SRF7 and the HEF5 are set the signal from OR ed output of K1 4 latch signals can cause the stop mode to be released 2 15 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 7 bits of interrupt enable flags IEF to enable disable interrupts 46 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The interrupt enable flag IEF is set reset by SIE instruction The bit pattern of control register 3 CTL3 is shown below Int t bl IEF6 IEF5 IEF4 flag Ini t Enable the interrupt request Enable the interrupt request Enable the interrupt request nterrupt requ 1 q caused by RFC c
118. nerator is 5 and FREQ 1 3 duty waveform SHE 40h enable the halt release caused by 16 bit counter SRF 28h enable the counter controlled by the CX signal HALT PLC 40h release is caused by the 2 rising edge on CX pin and then clear the halt release request flag MRF1 10h read the content of the counter MRF2 11h MRF3 12h 78 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual MRF4 13h 3 9 Key Matrix Scanning TM8722 shared the timing of LCD LED waveform to scan the key matrix circuitry and these scanning output pins are SEG1 16 for easy to understand named these pins as K1 K16 The time sharing of LCD LED waveform will not affect the display of LCD LED panel The input port of key matrix circuitry is composed by KI4 pins these pins muxed with SEG32 SEG35 pins and selected by mask option MASK OPTION table Mask Option name Selected item SEG32 IOC1 KH 3 KH SEG33 lOC2 Kl2 3 2 SEG34 IOC3 KIS 3 SEG35 lOC4 Kl4 3 The typical application circuit of key matrix scanning is shown below Ki6 K15 K14 K13 K12 K10 K9 K8 K7 K6 K5 K4 K3 K2 o O 0 0 0 0 O Kd O 0 0 0 0 0 O Q Q 0 O O 0 0 0 0
119. ng the clock source for IOA IOC chattering prevention PWM output and frequency generator description The following table shows the meaning of each bit for this instruction Bit pattern Clock source setting Bit pattern Clock source setting X6 1 The clock source comes from X6 0 The clock source comes the system clock BCLK from the 0 Refer to section 3 3 4 for 0 X2 X1 X0 2001 Chattering prevention clock X2 X1 X0 010 Chattering prevention 10 E X2 X1 X0 2100 Chattering clock X7 5 4 3 is reserved FRQ D Rx function Frequency generator lt D Rx AC description Loads the content of AC and data memory specified by Rx and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting The bit pattern of preset letter Bit 0 Rx0 Preset Letter D Duty Cycle L D D1 D a 0 0 1 9 po FRQ HL function Frequency generator lt D T HL description Loads the content of Table ROM specified by HL and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting it pattern of preset letter Programming Bit7 Bite Bit5 Bit4 i Bit1 Bit 0 divider FRQ D HL Note TO T7 represents the data of table ROM 125 tenx technology inc Rev 1 1 2003 11 25
120. nstruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are reset to 0 and the corresponding HRF flag will be cleared the interrupt enable flags IEF must be set again in the interrupt service routine as required 3 2 RESET FUNCTION TM8722 contains four reset sources power on reset RESET pin reset IOC port reset and watchdog timer reset When reset signal is accepted TM8722 will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by mask option the one is PH15 2 and the other is PH12 2 Reset signal JUU Ud uu v 00 0 0 0 O UUU UUU UUU UUL Hold 16384 2048 clocks for gt lt Normal operation internal reset cycle 57 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Internal reset cycle time is PH15 2 MASK OPTION table Mask Option name Selected item RESET TIME 1 PH15 2 In this option the reset cycle time will be extended 16384 clocks clock source comes form pre divider long at least Internal reset cycle time is PH12 2 MASK OPTION table Mask Option name Selected item RESET TIME 2 PH12 2 In this option the reset cycle time will be extended 2048 clocks cloc
121. nstruction and setting timer1 to control the time period Check the overflow flag RFOVF of this counter when the time period elapses If the overflow flag is not set to 1 read the content of the counter if the overflow flag has been set to 1 you must reduce the time period and repeat the previous procedure again In this example use the RR network to generate the clock source Timer 1 is used to enable disable the counter LDS 0 0 Set the TMR1 clock source PH9 LDS 1 3 initiate TMR1 setting value to 3F LDS 2 OFh SHE 2 enable halt release by 1 RE CNT LDA 0 OR 1 combine the TMR1 setting value TMS 2 enable the 1 SRF 9 build up the RR network and enable the counter HALT SRF 1 stop the counter when TMR1 underflows MRF1 10h read the content of the counter MRF2 11h 76 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual MRF3 12h MRF4 13h MSD 20h JB2 CNT1_OF check the overflow flag of counter JMP DATA ACCEPT CNT1 OF DEC 2 decrease the TM1 value LDS 20h 0 SBC 1 JZ CHG CLK RANGE change the clock source of TMR1 PLC 1 clear the halt release request flag of TMR1 JMP RE CNT 3 8 3 Enable Disable the Counter by Timer 2 TMR2 will control the operation of the counter in this mode When the counter is controlled by SRF 18 instruction the counter will start to operate until TMR2 is enabled and the first falling edge of the clock source gets into TMR2 When the TMR2 underflow occurs the counter w
122. nt of AC to decimal format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected DAS Rx function AC Rx lt BCD AC description Converts the content of AC to decimal format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected DAS HL function AC HL lt BCD AC description Converts the content of AC to decimal format and then restores to AC and data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC data before DAS data before data after DAS CF data after DAS execution execution execution execution 0x AC x9 lt lt 5 8 JUMP INSTRUCTIONS JBO X function Program counter jumps to X if ACO 1 description If bitO of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH JB1 X function Program counter jumps to X if AC1 1 description If bit of AC is 1 jump occurs the PC increases by 1 The range of X is from 000H to 7FFH JB2 X function Program counter jumps to X if AC2 1 123 tenx technology inc Rev 1 1 2003 11 25 description JB3 X function description JNZ X function des
123. nt of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupt accepted RTS instruction function STACK ring with Q first in last out 7 2 7 DATA MEMORY RAM The static RAM is organized with 128 addresses x 4 bits and is used to store data The data memory may be accessed using two methods 1 Direct addressing mode The address of the data memory is specified by the instruction and the addressing range is from 00H to 7FH 2 Index addressing mode The index address register HL specifies the address of the data memory and all address space from 00H to 07FH can be accessed The 16 specified addresses 70H to 7FH in the direct addressing memory are also used as 16 working registers The function of working register will be described in detail in section 2 6 30 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 00H 33 DATA 29 RAM x lt lt Working Register 4 Bits This figure shows the Data Memory R
124. o be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC instruction must be used to reset the halt release request flag 2 HRF2 or the SHE instruction must be used to reset the halt release enable flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF1 or the SHE instruction must be used to reset the halt release enable flag 1 HEF1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the halt release enable flag 3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag HRF3 or the SHE instruction must be used to reset the halt release enable flag 4 The 15th stage s content of the pre divider The MSC instruction is used to transfer the contents of status register STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3 5753 Bit 3 Bit 2 Bit 1 Bit 0 Start condition
125. option in TM8722 they are e 1 2 bias 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 4 duty 1 2bias 1 5 1 3 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 5 All of these lighting systems are combined with 2 kinds of mask options the one is LCD DUTY CYCLE and the other is LCD BIAS MASK OPTION table LCD duty cycle option Mask Option Name Selected Item LCD LED DUTY CYCLE 1 LCD LED DUTY CYCLE 2 DUPLEX 1 2 duty LCD LED DUTY CYCLE 3 1 3 DUTY 4 5 LCD LED DUTY CYCLE 4 1 4 DUTY LCD LED DUTY CYCLE 5 1 5 DUTY LCD bias option Mask Option name Selected item LCD BIAS 9 NO BIAS LCD BIAS 2 1 2 LCD BIAS 1 1 3 BIAS 83 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The frame frequency for each lighting system is shown below these frequencies could be selected by mask option All of the LCD frame frequencies in the following tables based on the clock source frequency of the pre divider PHO is 32768Hz The LCD alternating frequency in duplex 1 2 duty type Mask Option name Selected item Remark alternating frequenc LCD frame frequency 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64 2 LCD frame frequency __ 2 O P 0Hz LCD not used The LCD alternating frequency in 1 3 duty type Mask Option name Selected item Remar
126. ounter to caused by Key Scanning caused by TMR2 underflow g mend finished HRF6 EEUU NEN HERD UON Interrupt flag flag 6 4 4 Interrupt enable flag IEF3 IEF2 IEF1 Enable the interrupt request Enable the interrupt request Interrupt request Enable the interrupt request caused by predivider caused by TM1 underflow flag caused by INT pin HRF2 overflow HRF3 HRF1 Interrupt flag Interrupt 3 I 2 1 Interrupt DECEM flag Enable the interrupt a Interrupt request fla caused by IOC port signal to be changed HRF0 Interrupt flag Interrupt 0 When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to O automatically Therefore the desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 2 15 4 CONTROL REGISTER 4 CTL4 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 7 SRF4 SRF3 enable flag Enable the stop release Enable the stop release Enable the stop release request caused by signal request caused by signal request change on KI1 4 SKI change on INT pin change on IOC When the stop release enable flag 7 SRF7 is set to 1 the input signal change at the Kl1 4 pins causes the stop mode to be rele
127. predivider 8 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 13 2 RE LOAD OPERATION TMR2 also provides the re load function is the same as TMR1 The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 2 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER RFC TMR2 also controlled the operation of RFC function TMR2 will set TENX flag to 1 to enable the RFC counter once the TMR2 underflows the TENX flag will be reset to O automatically In this case Timer 2 could set an accurate time 37 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual period without setting a value error like the other operations of TMR1 and TMR2 Refer to 2 16 for detailed information on controlling the RFC counter The following figure shows the operating timing of TMR 2 in RFC mode Clock source of Timer 2 TM2X X Content of 3Fh N N 1 N 2 1 0 3Fh Timer2 HRF4 TMR2 also provides the re load function when controlled the RFC function The SF2 1h instruction enables the re load function and the DED flag should be set to 1 SF2 2h instruction Once DED flag had been set to 1 flag will not be cleared to 0 while TMR2 underflows but HRF4 will be set to1 The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HRF4 occurs thus the TENX flag will be reset to 0 when t
128. prevention PH6 clcok PLC 1 o Interrupt accept SCC s Q intruction intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex IOC2 to IOC4 are held at L level When the signal changes at the input pins of IOC port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF1 At that time the chattering prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to 0 by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOC interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOC1 to the input data at the port IOC must be read into the RAM immediately after the halt mode is released 71 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 3 6 EL PANEL
129. r example if the expected count down value is 500 it may be divided as 52 7 64 First set the initiate count down value of TMR1 to 52 and start counting then enable the TMR1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs clear the HRF1 flag by PLC instruction After halt release or interrupt occurs 8 times disable the re load function and the counting is completed 1st 2nd 3rd 4th 5th 6th 7th 8th 52 64 64 64 64 64 64 64 I count count count count count count count count TMS Re load In the following example S W enters the halt mode to wait for the underflow of TMR1 LDS 0 0 initiate the underflow counting register PLC 2 SHE 2 enable the HALT release caused by TMR1 TMSX 34h initiate the TMR1 value 52 and clock source is 9 SF 80h enable the re load function RE LOAD HALT INC 0 increase the underflow counter PLC 2 clear HRF1 JB3 END 1 if the TMR1 underflow counter is equal to 8 exit subroutine JMP RE LOAD END 1 HF 801 disable the re load function 35 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 13 TIMER 2 TMR2 The following figure shows the TMR2 organization Re load RL2 S
130. re divider timer I O port chattering prevention and LCD circuitry in this option Halt Halt Halt mode Slow mode Slow Fast mode XTOSC active XTOSC active lt XTOSC active CFOSC stop HALT CFOSC stop CFOSC active released Stop Sto released Reset p release Reset Reset state Reset Stop mode XTOSC active 5 stop Power on reset Reset reset CFOSC stop CFOSC stop Watchdog timer reset Key reset State Diagram of Dual Clock Option was shown on above figure After executing FAST instruction the system clock generator will hold 12 CF clocks after the CF clock oscillator starts up and then switches CF clock to BCLK This will prevent the incorrect clock from delivering to the system clock in the start up duration of the fast clock oscillator 22 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual clock xT clock FAST BCLK HOLD12CF CLOCKS This figure shows the System Clock Switches from Slow to Fast After executing SLOW instruction the system clock generator will hold 2 XT clocks and then switches XT clock to BCLK CF Fast clock stops operating clock XT clock SL
131. resents the decimal number 10 Instructions DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 AC data before DAS data before DAS AC data after DAS CF data after DAS execution execution execution execution 0x AC x9 6 lt lt AC 32 tenx technology Rev 1 1 2003 11 25 TM8722 User s Manual Example 2 LDS 10h 1 Load immediate data 1 to the data memory address 10H LDS 11h 2 Load immediate data 2 to the data memory address 11H and AC SF 1h Set CF to 1 which means no borrowing has occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H Rio CF 0 DAS 10h Convert the content of the data memory address 10H to decimal format result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 2 12 TIMER 1 TMR1 Re load RL1 M S TMS instruction IEF1 Q Initial reset Interrupt FREQ 6 bit binary down PH counter 2 XR PH9 PH15 data 5 0 TMS instruction Interrupt accept signal PLC 2 instruction x7 x6 TMS instruction Initial reset SCF5 Halt release Operand data This figure shows the TMR1 organi
132. ress range specified by Lz is from to 1FH 5 1 INPUT OUTPUT INSTRUCTIONS LCT 12 Ry function LCD latch Lz lt data decoder lt Ry description The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder 103 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual LCB Lz Ry function LCD latch Lz lt data decoder lt Ry description The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the outputs of the data decoder are all 0 LCP 12 Ry function LCD latch Lz lt Ry AC description The working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz LCD Lz HL function LCD latch Lz T HL description HL indicates an index address of table ROM The contents of table ROM specified by HL are loaded to the LCD latch specified by Lz directly LCT Lz HL function LCD latch Lz lt data decoder lt R HL description The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder LCB Lz HL function LCD latch Lz lt data decoder lt R HL description The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder If the content of HL is the outputs of the data decoder are all
133. ring prevention circuit and LCD driver output circuit are in operation If the timer has started operating the timer counter still operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters the halt mode The following 3 conditions are available to release the halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When the halt mode is released and an interrupt is accepted the halt release signal is reset automatically 2 The signal change specified by the SCA instruction is applied to port IOC SCF1 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 48 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual When the halt mode is released in either 2 or 3 it is necessary that the MSB MSC or instruction is executed in order to test the halt release signal and that the PLC instruction is then executed to reset the halt release signal HRF Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 2 17 HEAVY LOAD FUNCTION When heavy loading lamp light up motor start etc causes a temporary voltage drop on supply voltage the heavy
134. rs the table ROM data T HL directly from DBUSA to DBUSH without passing through the data decoder Table 2 2 The mapping table of LCP and LCD instructions __ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG LCD T HL0 TOHL1 T HL2 TOHL3 T HL4 TOHL5 T HL6 T HL7 There are 8 data decoder outputs of DBUSA to DBUSH and 32 LO to L4 decoder outputs of PSTB Oh to PSTB 1Fh The input data and clock signal of the latch circuit are DBUSA to DBUSH and PSTB Oh to PSTB 1Fh respectively Each segment pin has 5 latches corresponding to COM1 5 The segment PLA performs the function of combining DBUSA to inputs to each latch and strobe PSTB Oh to PSTB 1Fh is selected freely by mask option Of 256 signals obtainable by combining to DBUSH and PSTB Oh to PSTB 1Fh any 175 corresponding to the number of latch circuits incorporated in the hardware signals can be selected by programming and the above mentioned segment PLA Table 2 7 shows the PSTB Oh to PSTB 1Fh signals concretely Table 2 3 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction strobe signal for Strobe in LCT LCB LCP LCD LCD latch instructions The values of Lz in LCT Lz PSTB 2 2H PSTB 5 1 AH 5 1 1 Note The values of are the addresses of the working register in the data memory RAM In the LCD instruction is the index
135. rt to detect this signal and then set SCF1 to release the halt mode or the chip will return to the stop mode again 45 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 2 15 1 3 Interrupt for CTL1 The control register 1 CTL1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC port will deliver the SCF1 when SEF4 has been set to 1 by executing SCA instruction Once the SCF1 is delivered the halt release request flag HRF0 will be set to 1 In this case if the interrupt enable flag 0 IEF0 is set to 1 by executing SIE instruction the interrupt request flag 0 interrupt 0 will be delivered to interrupt the program If the interrupt 0 is accepted by SEF4 and IEF0 the interrupt 0 request to the next signal change at IOC will be inhibited To release this mode SCA instruction must be executed again Refer to 2 16 1 1 2 15 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 HEF1 2 3 4 5 6 and is set by SHE instruction The bit pattern of the control register CTL2 is shown below Halt release HEF6 enable flag Enable the halt Enable the halt Enable the halt Halt release release caused by release caused by release caused by condition RFC counter to be TMR2 underflow ee Enable the Enable the halt E
136. s Manual Instruction Machine Code Function Flag Remark DAS HL 0101 0111 1000 0000 AC R HL lt BCD AC CF LDS Rx D 0101 1200 DXXX XXXX AC Rx D LDH Rx HL 0110 0000 XXXX lt H T HL LDH Rx HL 0110 0001 XXXX lt H T HL HL lt HL 1 LDL Rx HL 0110 0010 XXXX Rx lt L T HL LDL Rx HL 0110 0011 XXXX lt L TGHL HL lt HL 1 1 0110 0100 AC lt RFC 3 0 Rx 0110 0101 OXXX XXXX AC Rx lt RFC7 4 MRF3 Rx 0110 0110 OXXX XXXX AC Rx lt RFC 11 8 MRF4 Rx 0110 0111 OXXX XXXX AC lt 15 12 STA Rx 0110 1000 OXXX XXXX Rx lt AC STA HL 0110 1000 1000 0000 R HL lt LDA Rx 0110 1100 OXXX XXXX AC lt Rx LDA HL 0110 1100 1000 0000 AC lt R HL MRA Rx 0110 1101 OXXX XXXX CF lt Rx 8 MRW HL Rx 0110 1110 OXXX XXXX AC R HL lt MWR Rx HL 0110 1111 AC lt R HL MRW Ry Rx 0111 OYYY YXXX XXXX Ry lt Rx MWR Rx Ry 0111 1YYY YXXX XXXX AC lt Ry JBO X 000 OXXX XXXX XXXX PC X if AC O 1 JB1 X 000 1 XXXX XXXX PC lt X if AC 1 JB2 X 001 XXXX XXXX PC x if AC 2 1 JB3 X 001 1 XXX
137. s counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or at the initial reset mode The pre divider delivers the signal to the halver tripler circuit alternating frequency for LCD display system clock sound generator and halt release request signal I O port chattering prevention clock Frequency Interrupt request Generator HEF3 Halt mode BCLK Initial SCF7 SLOW instruction PLC 8H FAST instruction Interrupt HALT release Clock switch clock circuit generator MSC instruction b 4 6 Halver tribler circuit Data bus 2 To timer circuit PLC 100H initial switch circuit Single clock Dual clock option To sound circuit 24 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual This figure shows the Pre divider and its Peripherals The PH14 delivers the halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of pre divider is PHO and 4 kinds of frequency of PHO could be selected by mask option MASK OPTION table Mask Option name S
138. sed by an interrupt request the TM8722 will enter the halt mode immediately While the interrupt is accepted the halt mode will be released by the interrupt request The stop mode returns by executing the RTS instruction after completion of interrupt service After the stop release it is necessary that the MSB MSC or MCX instruction be executed to test the halt release signal and that the PLC instruction then be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter the stop mode but the halt mode When the stop mode is released and an interrupt is accepted the halt release signal HRF is reset automatically 2 19 BACK UP FUNCTION TM8722 provide a back up mode to avoid system malfunction when heavy loading occurred such as buzzer is active LED is lighting etc Since the heavy loading will cause a large voltage drop on the supply voltage and the system will be malfunction in this condition Once the program enter back up mode BCF 1 32 768KHz Crystal oscillator will operate in a large driver condition and internal logic function operates with higher supply voltage TM8722 will get more power supply noise margin while back up mode is active but also increases more power consumption The back up flag BCF indicated the status of back up function BCF flag could be set or reset by executing SF or RF instruction respectivel
139. t clock TMS HL The clock source option for timer 1 olol X function Selects timer 1 clock source and preset timer 1 description The data specified by X X7 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Setting value TMSX X X5 X1 The clock source option for timer 1 2 5 2 function Selects timer 2 clock source and preset timer 2 description The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction 127 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual OPCODE Selectclock Imitate value of timer AC3 The clock source setting for timer 2 FREQ TM2 HL function Selects timer 2 clock source and preset timer 2 description The content of Table ROM specified by is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Selectclock value of timer TM2 HL The clock source setting for timer 2 Bit7 po 0 0 TM2X X function Selects timer 2 clock source and preset timer 2 description The data specified by X X8 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction Initiate value of timer X3 X2 The clock source set
140. th Li power option it is necessary to connect a 0 1uf capacitor from BAK power pin to GND for the backup mode application When the heavy load function is performed the current dissipation will increase Table 3 2 Ag power option Initial reset After reset STOP mode SF2 RF2 Bor vif 1 0 _ logic 49 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Table 3 3 Li power option Initial reset After reset BCF 1 T j 1 j 0 1 2 VDD logic Table 3 4 EXT V power option Initial reset After reset Stop mode BCF o 0 1 1 Internal logic logic Note When the program enters the stop mode the BCF will set to 1 automatically to insure that the low speed oscillator will start up in a proper condition while stop release occurs 2 18 STOP FUNCTION STOP The stop function is another solution to minimize the current dissipation for TM8722 In stop mode all of functions in TM8722 are held including oscillators All of the LCD corresponding signals COM and Segment will output L level In this mode TM8722 does not dissipate any power in the stop mode Because the stop mode will set the flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins defined as input mode of IOC port must be in the
141. ting for timer 2 1010 0 9 0j 0 1 8 1010 5 0 1 1 FRQ 1100101 j 1 0 1 1 1 0 m SF X function Sets flag 128 tenx technology inc Rev 1 1 2003 11 25 description RF X machine code function description SF2 X function description RF2 X function description PLC function description TM8722 User s Manual Description of each flag 1 The CF is set to 1 X1 1 The chip enters backup mode and 1 set to 1 X2 1 The EL light driver output pin is active 1 For X221 when the SF instruction is executed at X3 1 the EL light driver is active and the halt request signal is outputted then the chip enters halt mode X4 1 The watchdog timer is initiated and active X7 1 Enables the re load function of timer 1 X6 5 is reserved 1111 0100 X700X4 OX2X1Xo Resets flag Description of each flag 1 The CF is reset to 0 X1 1 The chip is out of backup mode and is reset 0 X2 1 The EL light driver is inactive X4 1 The watchdog timer is inactive X7 1 Disables the re load function of timer 1 X6 5 3 is reserved Sets flag Description of each flag 1 Enable INT powerful pull low X2 1 Disables the LCD LED segment output X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 7 6 is reserved Resets flag Description of each
142. ty control circuit Interrupt 1 Interrupt 2 Interrupt vector address generator Interrupt 3 Interrupt 4 Interrupt 5 Interrupt 6 Interrupt request signal Interrupt accept signal SIE instruction Initial clear tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC ports or Key matrix Scanning 1 External INT pin interrupt request By using mask option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the signal on the INT pin change that matches the mask option will issue the HRF2 interrupt 2 is accepted and the instruction at address10H is executed automatically is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 I O port IOC interrupt request An interrupt request signal HRFO is delivered when the input signal changes at I O port IOC specified by the SCA instruction In this case if the interrupt enabled by flag 0 IEFO is set to 1 interrupt O is accepted and the instruction at address 14H is executed automatically 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal generat
143. ty Cycle SEE Poe woo TT SCC AC1 ACO Rx3 Rx0 SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencies and duty cycles corresponding to the presetting data of FRQ related instructions The FRQ related instructions preset a letter N into the programming divider and letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of data memory and accumulator AC or the table ROM data or operand data specified in the FRQX instruction The following table shows the bit pattern of the combination The following table shows the bit pattern of the preset letter N 61 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual The bit pattern of preset letter N Programming divider Notes 1 TO T7 represents the data of table ROM 2 X7 represents the data specified in operand X The following table shows the bit pattern of the preset letter D EROR pea O 1 4duty _0 1 f 3duy 1 0 f 2duy The following diagram shows the output waveform for different duty cycles clock source N 1 Hz 1 4 duty carrier out 1 3 duty carrier out 1 2 duty carrier out l L l
144. y The back up function has different performance corresponding to different power mode option shown in the following table 1 5V battery mode TM8722 status BCF flag status Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 51 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled TM8722 status BCF 0 1 32 768 Crystal Oscillator Small driver Large driver Voltage on BAK pin VDD1 VDD1 Internal operating voltage VDD1 VDD1 3V battery or higher mode Initial reset cycle 1 hardware controlled After initial reset cycle 1 hardware controlled Executing SF 2h instruction 1 Executing 2h instruction 0 HALT mode Previous state STOP mode 1 hardware controlled BCF 1 32 768KHz Crystal Oscillator Small driver Voltage on BAK pin VDD1 VDD2 Internal operating voltage VDD1 VDD2 Ext V power mode TM8722 status BCF flag status Initial reset cycle BCF 0 hardware controlled After initial reset cycle 0 hardware controlled Executing SF 2h instruction 1 Executing 21 instruction 0 HALT mode Previous state STOP mode 1 hardware controlled
145. ycle The bit pattern of X for Key Matrix scanning output to SEG1 16 1 Hiz Hiz Hiz Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 f1 Hiz 1 Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 0 lHizHiz 1 Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 1 1 Hrz Hiz Hiz 1 MHi z Hi z Hizz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 fHizHiz Hiz Hiz 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z f1 Hi zlHi zHi z Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 0 0 0 1 1 0 fHizHiz Hiz Hiz Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 1 1 Hi zlHi zHi z Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 fHizHizHiz Hiz Hi z Hi z Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z Hiz fo 0 1 Hrz Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z Hi z 1 1 0 hHizHizMHiz Hiz Hiz Hi z Hi z Hi z Hi z 1 Hi z Hi z Hi z Hi z Hi z 1 1 Hriz Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 Hi z Hi z Hi z Hi z 1 0 2 2 Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 Hi z Hi z 2 0 0 1 1 0 1 fHizHiz Hiz Hiz Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 Hi z Hi z 11
146. z Hi z 1 Hi z Hi z 0 0 1 1 1 0 H zlHi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z 1 1 1 1 Hz Hz Hcz Hcz Hz Hiz Hiz Hi z Hi z Hz Hz Hoz Hoz Hoz 1 U O U 8 1 0 0 0 0 0 Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Hi z Notes 1 1 H L LED LCD 2 K1 16 SEG1 16 output scanning interval 0 0 EE 0 1 01 H 1 1 H 0 0 1 1 0 0 When KI1 4 is defined for Key matrix scanning input mask option it is necessary to execute SPC instruction to set the internal unused IOC port as output mode before the key matrix scanning function is active The organization of Key matrix scanning input port is shown in next page Once one of KI1 4 pin detected the signal change from Hi z to 1 TM8722 will set HRF5 to 1 HEF5 had been set to 1 beforehand this will cause SCF7 to be set and release the HALT mode After the key scanning cycle finished the states of 4 will be latched into the IOC port Executing the IPC instruction could store these states into data RAM Executing PLC 20h instruction could clear HRF5 flag Since the key matrix scanning function shared the timing of LCD LED waveform so the scanning frequency is corresponding to LCD frame frequency and LCD duty cycle The formula for key matrix scanning frequency is shown below key m
147. zation 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or TMSX instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request 1 HRF1 to 1 and then stop to count down When HRF1 1 and the TMR1 interrupt enable flag IEF1 1 the interrupt is generated When HRF1 1 if the IEF1 0 and the halt release enable HEF1 1 program will escapes from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 STS3 After power on reset the default clock source of TMR1 is PH3 33 tenx technology inc Rev 1 1 2003 11 25 TM8722 User s Manual If watchdog reset occurred the clock source of TMR1 will still keep the previous selection The following table shows the definition of each bit in TMR1 instructions OPCODE Select clock TMSXX Xz X6 X5 X4 X3 X2 X XO TMSRx _ AC3 AC2 AC1 ACO Rx3 Rx2 Rx1 RxO TMS QHL bit6 bits Bit4 bits bit2 bitt bito The following table shows the clock source setting for TMR1 PHO x 0 1 PHR 1 0 PHS Notes 1 When the TMR1 clock is PH3 TMR1 set time Set value error 8 1 fosc KHz ms 2 When the TMR1 clock is PH9 TMR1 set time Set value error 512 1 fosc KHz ms 3 When the TMR1 clock is PH15 TMR1 set time

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