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DAQ 6052E/6053E User Manual, NI 2000

1. Table 4 3 1 0 Signal Summary Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias ACH lt 0 63 gt AI 100 GQ 25 15 200 pA in parallel with 100 pF AISENSE AI 100 GQ 25 15 200 pA in parallel AISENSE2 with 100 pF AIGND AO DACOOUT AO 0 1Q Short circuit 5 at 10 5 at 10 20 to ground V us DACI1OUT AO 0 1Q Short circuit 5 at 10 5 at 10 20 to ground V us EXTREF Al 10 kQ 25 15 AOGND AO m a DGND DO VCC DO 0 1Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24at0 4 dl 50 kQ pu SCANCLK DO 3 5 at Vec 0 4 5 at 0 4 5 50 KQ pu EXTSTROBE DO 3 5 at Vec 0 4 5 at 0 4 a5 50 KQ pu PFIO TRIG1 AI 10 kQ 35 3 5 at Vec 0 4 5 at 0 4 5 9 KQ pu DIO Vec 0 5 and 10 kQ pd PFIL TRIG2 DIO Vec 0 5 3 5 at Vec 0 4 5at04 5 50 KQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 5 50 KQ pu PFI3 GPCTR1_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at04 5 50 KQ pu PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 5 50 KQ pu GPCTR1_OUT DO 3 5 at Vec 0 4 5at0 4 5 50 KQ pu PFIS UPDATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 5 50 KQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4 5 50 KQ pu PFI7 STARTSCAN DIO Vec 0 5 3 5 at Vec 0 4 5 at 0 4
2. Input Multiplexers o e AISENSE Selected Channel in DIFF Configuration Figure 4 6 Differential Input Connections for Nonreferenced Signals Figure 4 6 shows two bias resistors connected in parallel with the signal leads of a floating signal source If you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA The PGIA will then saturate causing erroneous readings You must reference the source to AIGND The easiest way is to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA without any resistors at all This 4 16 www ni com Chapter 4 Signal Connections connection works well for DC coupled sources with low source impedance less than 100 Q However for larger source impedances this connection leaves the differential signal path significantly out of balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground Hence this noise appears as a differential mode signal instead of a common mode signal and the PGIA does not reject it In this case instead of directly connecting the negative line to AIGND connect it to AIGND through a resistor that is about 100 times the equivalent source impedance The resistor
3. eeeeeeee Each input should remain within 11 V of ground Overvoltage protection ee 25 V powered on 15 V powered off 6052E 6053E User Manual A 2 www ni com Inputs protected PCEI 6052E sscan pas PCI2605 3B sinna eaa FIFO buffer size cececceeeeeeeeeeereee Data transfers eeeeeeeeeeeeseseseerereeerrreees Appendix A Specifications ACH lt 0 15 gt AISENSE ACH lt 0 63 gt AISENSE AISENSE2 512 samples DMA interrupts programmed I O DMA modes niessessies Scatter gather Configuration memory Size 512 words Transfer Characteristics Relative accuracy cee eeeeeeeeeeeeeeeeee 1 5 LSB typ 3 0 LSB max DNE inoa S 0 5 LSB typ 1 0 LSB max No missing codes 0 0 eeeeeeeseeeeeeeteeeenees Offset error Pregain error after calibration Pregain error before calibration Postgain error after calibration Postgain error before calibration 16 bits guaranteed 1 0 uV max 2 6 mV max 76 UV 82 mV Gain error relative to calibration reference After calibration gain 1 Before calibration ccceeeeseeees Gain with gain error adjusted to 0 at gain Loe Amplifier Characteristics Input impedance Normal powered on eseeseeeeeees P wer d OFF saicscxsssstees mieie Overload i aE E Input bias current seeeeeseeeeeeeeeeeeeeeeeee National Instruments Corporation A 3 30 5
4. ACH16 ACH17 ACH18 ACH19 ACH20 ACH21 ACH22 ACH23 ACH32 ACH33 ACH34 ACH35 AISENSE2 ACH36 ACH37 ACH38 ACH39 ACH48 ACH49 ACH50 ACH51 ACH52 ACH53 ACH54 ACH55 ACH24 ACH25 PM ACH26 8 ACH27 ON ojo 10 ACH28 11 12 ACH29 13 14 ACH30 15 16 ACH31 17 18 ACH40 19 20 ACH41 21 22 ACH42 23 24 ACH43 25 26 AIGND 27 28 ACH44 29 30 ACH45 31 32 ACH46 33 34 ACH47 35 36 ACH56 37 38 ACH57 39 40 ACH58 41 42 ACH59 43 44 ACH60 45 46 ACH61 47 48 ACH62 49 50 ACH63 National Instruments Corporation Figure B 3 50 Pin Extended Analog Input Connector Pin Assignments B 5 6052E 6053E User Manual Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your device General Information What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by National Instruments and is the backbone of the E Series devices The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Analog input two 24 bit two 16 bit counters e Analog output
5. 17 ppm C Onboard calibration reference TS Vel iiss tis baths cess tess cbests odeeeets 5 000 V 1 0 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 0 ee 6 ppm 1 000h Output Characteristics Number of channels cceeseeseeeeeees 2 voltage Resolutio s cece Sones cdaes seassa 16 bits 1 in 16 536 Max update rate 333 kS s Type of DA Ce vs scenic tides vegeta tees Double buffered multiplying FIFO buffer size eee eee eee 2 048 samples Data transfers cccccccc cc cccccccseeseeeeeeeeeees DMA interrupts programmed I O DMA modes eee eeeeeseseeseeeeeeeeeees Scatter gather National Instruments Corporation A 5 6052E 6053E User Manual Appendix A Specifications PXI 6052E 6053E Accuracy Information Absolute Accuracy Nominal Range V of Reading Offset Temp Drift Positive FS Negative FS 24 Hrs 90 Days 1 Year uv I C 10 10 0 0044 0 0052 0 0061 798 UV 0 0001 10 0 0 0044 0 0052 0 0061 569 uV 0 0001 Absolute Accuracy of Reading x Voltage Offset Temp Drift x Voltage Note Temp drift applies only if ambient is greater than 10 C of previous external calibration Transfer Characteristics Relative accuracy INL After calibration 0 35 LSB typ 1 0 LSB max Before calibration ccccceeeeees 4 LSB max DNL After calib
6. AISENSE AISENSE2 and AIGND The ACH lt 0 63 gt signals are tied to the 64 analog input channels of the devices In single ended mode signals connected to ACH lt 0 63 gt are routed to the positive input of the PGIA In differential mode signals connected to ACH lt 0 7 16 23 32 39 48 55 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 24 31 40 47 56 63 gt are routed to the negative input of the PGIA Caution Exceeding the differential and common mode input ranges distorts your input signals Exceeding the maximum input voltage rating can damage your device and the computer National Instruments is not liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in the Protection column of Table 4 3 National Instruments Corporation 4 9 6052E 6053E User Manual Chapter 4 Signal Connections 6052E 6053E User Manual In NRSE mode the AISENSE signal is connected internally to the negative input of the PGIA when their corresponding channels are selected In DIFF and RSE modes this signal is left unconnected AIGND is an analog input common signal that is routed directly to the ground tie point on your device You can use this signal for a general analog ground tie point to your device if necessary Connection of analog input signals to your device depends on the configuration of the analog input channels you are using and the type of i
7. conversely if conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal Any PFI pin can externally input the SISOURCE signal which is not available as an output on the I O connector The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for the SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source Figure 4 24 shows the timing requirements for the SISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 24 SISOURCE Signal Timing Waveform Generation Timing Connections The analog group defined for your PCI E Series device is controlled by WFTRIG UPDATE and UISOURCE 6052E 6053E User Manual 4 34 www ni com Chapter 4 Signal Connections WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG
8. 3 10 www ni com counter timer applications C 5 custom cabling B 1 customer education D 1 D DACOOUT signal analog output signal connections 4 21 to 4 22 description table 4 5 T O signal summary table 4 8 DACIOUT signal analog output signal connections 4 21 to 4 22 description table 4 5 T O signal summary table 4 8 DAQ timing connections 4 26 to 4 34 AIGATE signal 4 33 to 4 34 CONVERT signal 4 32 to 4 33 EXTSTROBE signal 4 27 to 4 28 SCANCLK signal 4 27 SISOURCE signal 4 34 STARTSCAN signal 4 30 to 4 32 TRIGI signal 4 28 to 4 29 TRIG signal 4 29 to 4 30 typical posttriggered acquisition figure 4 26 typical pretriggered acquisition figure 4 27 DAQPad 6052E See 6052E 6053E devices DAQ STC C 1 C 4 to C 5 data acquisition timing connections See DAQ timing connections DGND signal description table 4 5 T O signal summary table 4 8 DIFF mode description table 3 2 recommended configuration figure 4 13 National Instruments Corporation l 3 Index differential connections 4 14 to 4 17 ground referenced signal sources 4 14 to 4 15 nonreferenced or floating signal sources 4 16 to 4 17 when to use 4 14 digital I O common questions C 4 to C 6 overview 3 9 signal connections 4 22 to 4 23 specifications A 8 digital trigger specifications A 10 DIO lt 0 7 gt signal description table 4 5 digital I O signal connections 4 22 to 4 23 T O signal summary tabl
9. DC to 1 MHz Glitch energy at midscale transition Magnitude 00 eeeeeeeeeeeeeeee 10 mV DUA OM arein eai 1 us Stability Offset temperature coefficient 35 uV C National Instruments Corporation A 7 6052E 6053E User Manual Appendix A Specifications Gain temperature coefficient Internal reference eeeeeeeees External reference Onboard calibration reference Level ou ccccceccceeeessessssessssseeseeeseeeeess Temperature coefficient Long term stability eee Digital 1 0 Number of channels ccccceeeeseeeeees 6 5 ppm C 5 ppm C 5 000 V 1 0 mV over full operating temperature actual value stored in EEPROM 0 6 ppm C max 6 ppm 1 000h 8 input output Compatibility iederien TTL CMOS Digital logic levels Level Min Max Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vin 0 V 320 uA Input high current Vin 5 V 10 uA Output low voltage Ip 24 mA 0 4 V Output high voltage Ion 13 mA 4 35 V Power on state ccceeececcesesesesesessseeeees Data tr nsf rShoneiionuones isio Timing 1 0 Number of channels cccc0cceseseseeees Resolution Counter timerS cccccccccceceeeeeeseeees Frequency scaler ceseeeseeeseeee Compatibility 000 eee eee eeeeereeeeees 6052E 6053E User Manual A 8 Input High Z Programmed
10. Index PFI6 WFTRIG signal description table 4 7 T O signal summary table 4 8 PFI7 STARTSCAN signal description table 4 7 I O signal summary table 4 8 PFI8 GPCTRO_SOURCE signal description table 4 7 T O signal summary table 4 8 PFI9 GPCTRO_GATE signal description table 4 7 T O signal summary table 4 8 PFIs programmable function inputs common questions C 6 signal routing 3 11 timing connections 4 25 to 4 26 PGIA programmable gain instrumentation amplifier analog input connections 4 10 differential connections ground referenced signal sources figure 4 15 nonreferenced or floating signal sources 4 16 overview 4 14 single ended connections floating signal sources figure 4 19 ground referenced signal sources figure 4 20 physical specifications A 11 pin assignments See I O connectors polarity input polarity and range 3 3 to 3 4 output polarity selection 3 5 posttriggered data acquisition overview 4 26 typical acquisition figure 4 26 power connections 4 24 Power LED 2 4 power requirement specifications A 10 6052E 6053E User Manual l 6 pretriggered acquisition overview 4 26 typical acquisition figure 4 27 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programmable gain instrumentation amplifier PXI using with CompactPCI 1 2 PXI 6052E 6053E See 6052E 6053E devices Q question
11. 4 Signal Connections EXTREF Lot DACOOUT o External Channel 0 Reference V Signal Optional VOUT 1 Load DAC1OUT ee Channel 1 Analog Output Channels 6052E 6053E Device Figure 4 9 Analog Output Connections The external reference signal can be either a DC or an AC signal The device multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage Digital 1 0 Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage your device and the computer National Instruments is not liable for any damages resulting from such signal connections Figure 4 10 shows signal connections for three typical digital I O applications Figure 4 10 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state 6052E 6053E User Manual 4 22 www ni com Chapter 4 Signal Connections of the switch shown in the figure Digital output applications include sending TTL signals
12. ACH1 ACH9 ACH2 ACH10 ACH3 ACH11 ACH4 ACH12 ACH5 ACH13 ACH6 ACH14 ACH7 ACH15 AISENSE DACOOUT DAC10OUT EXTREF AOGND DGND DIOO DIO4 DIO1 DIO5 DIO2 DIOG DIO3 DIO7 DGND 5V 5V SCANCLK EXTSTROBE PFIO TRIG1 PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTR1_SOURCE PFl4 GPCTR1_GATE GPCTR1_OUT PFI5 UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 1 51 2 52 3 53 4 54 5 55 6 56 7 57 8 58 9 59 10 60 11 61 12 62 13 63 14 64 15 65 16 66 17 67 18 68 19 69 20 70 21 71 22 72 23 73 24 74 25 75 26 76 27 77 28 78 29 79 30 80 31 81 32 82 33 83 34 84 35 85 36 86 37 87 38 88 39 89 40 90 41 91 42 92 43 93 44 94 45 95 46 96 47 97 48 98 49 99 50 100 ACH16 ACH24 ACH17 ACH25 ACH18 ACH26 ACH19 ACH27 ACH20 ACH28 ACH21 ACH29 ACH22 ACH30 ACH23 ACH31 ACH32 ACH40 ACH33 ACH41 ACH34 ACH42 ACH35 ACH43 AISENSE2 AIGND ACH36 ACH44 ACH37 ACH45 ACH38 ACH46 ACH39 ACH47 ACH48 ACH56 ACH49 ACH57 ACH50 ACH58 ACH51 ACH59 ACH52 ACH60 ACH53 ACH61 ACH54 ACH62 ACH55 ACH63 National Instruments Corporation Figure 4 2 1 0 Connector Pin Assignment for the 6053E 4 3 6
13. Chapter 4 Signal Connections Differential Connection Considerations DIFF Input Configuration A differential connection is one in which the device analog input signal has its own reference signal or signal return path These connections are available when the selected channel is configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or return is tied to the negative input of the PGIA When you configure a channel for differential input each signal uses two multiplexer inputs one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to eight analog input channels are available You should use differential input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the 6052E 6053E device are greater than 10 ft 3 m e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA Differential Connections for Ground Referenced Signal Sources Figure 4 5 shows how to connect a ground referenced signal source to a channel on the 6052E 605
14. E 4 36 UISOURCE Signal visi 3 24 sch dws eh veh Ee 4 37 General Purpose Timing Signal Connections 0 0 0 0 eee eeeeseeeeeseeeeceeeseeeeees 4 38 GPCTRO_SOURCE Signal eroien hr a bidet 4 38 GPGFRO GATE Signal errre a Mula th e Ea Er E E 4 39 GPCTRO OUT Signali nien e n 4 40 6052E 6053E User Manual vi www ni com GPCTRO_UP_DOWN Signal GPCTR1_SOURCE Signal GPCTR1_GATE Signal ee GPCTR1_OUT Signal oe GPCTR1_UP_DOWN Signal FREQ OUT Signal eee Field Wiring Considerations 0 0 0 0 cece eeeeeeseeeeeeeeeseeeeeeeeens Chapter 5 Calibration Loading Calibration Constants 2 0 eee eeeeseeseeeeeeneeeeeens Self Calibration ccccccccccssssssccccessssececcesssseeeecesessueeecesenanees External Calibration ccccccccsccccccsssssccceesssseeeceeeessseeeceesees Other Considerations sssi Aineen e e eTe Appendix A Specifications Appendix B Custom Cabling and Optional Connectors Appendix C Common Questions Appendix D Technical Support Resources Glossary index National Instruments Corporation vii Contents 6052E 6053E User Manual Contents Figures Figure 1 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 4 14 Figure 4
15. Extended Analog Input Connector Pin Assignments B 3 6052E 6053E User Manual Appendix B Custom Cabling and Optional Connectors 6052E 6053E User Manual Figure B 2 shows the pin assignments for the 50 pin connector This connector is available when you use the SH6850 or R6850 cable assemblies It is also one of the two 50 pin connectors available when you use the R1005050 cable assembly with the PCI PXI 6053E AIGND 1 2 AIGND ACHO 3 4 ACH8 ACH1 5 6 ACH9 ACH2 7 8 ACH10 ACH3 9 10 ACH11 ACH4 11 12 ACH12 ACH5 13 14 ACH13 ACH6 15 16 ACH14 ACH7 17 18 ACH15 AISENSE 19 20 DACOOUT DAC1OUT 21 22 EXTREF AOGND 23 24 DGND DIOO 25 26 DIO4 DIO1 27 28 DIO5 DIO2 29 30 DIO6 DIO3 31 32 DIO7 DGND 33 34 5V 5V 35 36 SCANCLK EXTSTROBE 37 38 PFIO TRIG1 PFI1 TRIG2 39 40 PFI2 CONVERT PFI3 GPCTR1_SOURCE 41 42 PFI4 GPCTR1_GATE GPCTR1_OUT 43 44 PFI5 UPDATE PFI6 WFTRIG 45 46 PFI7 STARTSCAN PFI8 GPCTRO_SOURCE 47 48 PFI9 GPCTRO_GATE GPCTRO_OUT 49 50 FREQ_OUT Figure B 2 50 Pin Connector Pin Assignments B 4 www ni com Appendix B Custom Cabling and Optional Connectors Figure B 3 shows the pin assignments for the 50 pin extended analog input connector This is the other 50 pin connector available when you use the R1005050 cable assembly with the PCI PXI 6053E
16. I O 2 up down counter timers 1 frequency scaler 24 bits www ni com Triggers Base clocks available Counter timers 000000eeeeee Frequency scalers Base clock accuracy eseeeeeeees Max source frequency eee Min source pulse duration Min gate pulse duration Data transfers ccccceceeeseeeeeee DMA modes Analog Trigger Source PCI6052E esiis statii PCI 6053 E cenite na eVelse i R solutoi arnesi Hysteresis aenn Bandwidth 3 dB ceccssssseseeeeen External input PFIO TRIG1 Impedance eee Coupling ee eeeeeeeeeees National Instruments Corporation A 9 Appendix A Specifications 20 MHz 100 kHz 10 MHz 100 kHz waste 0 01 20 MHz 10 ns in edge detect mode 10 ns in edge detect mode DMA interrupts programmed I O Scatter gather ACH lt 0 15 gt PFIO TRIG1 ACH lt 0 63 gt PFIO TRIG1 full scale internal 10 V external Positive or negative software selectable 12 bits 1 in 4 096 Programmable 700 kHz internal 700 kHz external 10kQ DC 6052E 6053E User Manual Appendix A Specifications Bus Interface ProtectrOmins cescacsisi a niessnistecnteeieies 0 5 to Vec 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Power Requirement 6052E 6053E User Manual ACCURACY patanina ay 1 0 of
17. PXI compatible products with standard CompactPCI products is an important feature provided by PXI Specification Revision 1 0 If you use a PXI compatible plug in card in a standard CompactPCI chassis you are unable to use PXI specific functions but you can still use the basic plug in card functions For example the RTSI bus on your PXI 6052E 6053E is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses Your PXI 6052E 6053E works in any standard CompactPCI chassis adhering to PICMG CompactPCI 2 0 R2 1 What You Need to Get Started 6052E 6053E User Manual To set up and use your 6052E 6053E device you need the following One of the following PCI 6052E 6053E PXI 6052E 6053E DAQPad 6052E for 1394 Q 6052E 6053E User Manual UO One of the following software packages and documentation LabVIEW for Macintosh LabVIEW for Windows Measure 1 2 www ni com Chapter 1 Introduction Measurement Studio NI DAQ for Macintosh NI DAQ for PC Compatibles VirtualBench Q Your computer Software Programming Choices You have several
18. Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select_Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals UN Caution If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the device the computer and the connected equipment What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the device circuitry is not actively driving the output either high or low However these lines can have pull up or pull down resistors connected to them as shown in Table 4 2 O Connector Signal Descriptions and Table 4 3 I O Signal Summary These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the h
19. Range V of Reading Offset Quantization V Drift Resolution pV Positive Negative Single Single FS FS 24 Hours 90 Days 1 Year uY Pt Avg C Pt Avg 10 10 0 0304 0 0312 0 0321 1067 981 87 0 0 0006 1145 115 3 5 0 0054 0 0062 0 0071 536 491 43 5 0 0001 573 57 3 2 5 2 5 0 0304 0 0312 0 0321 271 245 21 7 0 0006 286 28 6 1 1 0 0304 0 0312 0 0321 111 98 1 8 7 0 0006 115 11 5 0 5 0 5 0 0304 0 0312 0 0321 58 1 56 2 5 0 0 0006 66 3 6 6 0 25 0 25 0 0304 0 0312 0 0321 31 6 32 8 3 0 0 0006 39 2 3 9 0 1 0 1 0 0304 0 0312 0 0321 15 6 22 4 2 1 0 0006 27 7 2 8 0 05 0 05 0 0304 0 0312 0 0321 10 3 19 9 1 9 0 0006 25 3 2 5 10 0 0 0054 0 0062 0 0071 536 491 43 5 0 0001 573 57 3 5 0 0 0304 0 0312 0 0321 271 245 21 7 0 0006 286 28 6 2 0 0 0304 0 0312 0 0321 111 98 1 8 7 0 0006 115 11 5 1 0 0 0304 0 0312 0 0321 58 1 56 2 5 0 0 0006 66 3 6 6 0 5 0 0 0304 0 0312 0 0321 31 6 39 8 3 0 0 0006 48 2 3 9 0 2 0 0 0304 0 0312 0 0321 15 6 22 4 2 1 0 0006 27 7 2 8 0 1 0 0 0304 0 0312 0 0321 10 3 19 9 1 9 0 0006 25 3 2 5 Note Accuracies are valid for measurements following an internal E Series Calibration Averaged numbers assume dithering and averaging of 100 single channel readings Measurement accuracies are listed for operational temperatures within 1 C of internal calibration temperature and 10 C of external or factory calibration temperature Input Coupling 00 eee ese eeeeeeeeeeee DC Max working voltage signal common mode
20. a Ki 5 ts Trigger i Analog Input i nia y R m Cc PFI Trigger 99 1 Timing Control 1 Request Anka IEEPROM DMA c per y4 2E quest conto Control 1 Interface x lt 1 i Counter Bus haag PS S Tamir DAQ STC inertace baase ag Qo O g nenpt EE e Interface Interface O eT Digital vo Analog Output RTSI Bus Analog 1 a O igital VO 8 j Digital Timing Control Interface output 7 Interface QA AO Control DACO ga mmi Bata PEs UT Calibration 8 DACs 32 for the PCI 6053E Figure 3 1 PCI and PXI Block Diagram National Instruments Corporation 3 1 6052E 6053E User Manual Chapter 3 Hardware Overview Analog Input Input Mode 6052E 6053E User Manual The analog input section of the 6052E 6053E is software configurable You can select different analog input configurations through application software designed to control your device The following sections describe in detail each of the analog input categories The PCI devices have three different input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations provide up to 16 channels on the 6052E or 64 channels on the 6053E The DIFF input configuration provides up to eight channels on the 6052E or 32 channels on the 6053E Input modes are programmed on a per channel basis for multimode scanning For example you can configu
21. and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UI counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 25 and 4 26 show the input and output timing requirements for the WFTRIG signal i tw i lt gt Rising Edge Polarity y Falling Edge _ m Polarity tw 10 ns minimum Figure 4 25 WFTRIG Input Signal Timing ty 50 100 ns Figure 4 26 WFTRIG Output Signal Timing National Instruments Corporation 4 35 6052E 6053E User Manual Chapter 4 Signal Connections 6052E 6053E User Manual UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DA
22. and temperature It is better to self calibrate when the device is installed in the environment in which it will be used Self Calibration Your device can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration 6052E 6053E User Manual Your device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your device at an extreme temperature or if the onboard referenc
23. be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections 6052E 6053E User Manual The DAQ timing signals are SCANCLK EXTSTROBE TRIGI TRIG2 STARTSCAN CONVERT AIGATE and SISOURCE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 12 Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 13 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures is included later in this chapter TRIG1 STARTSCAN CONVERT Ii U U oO Scan Counter 1 Figure 4 12 Typical Posttriggered Acquisition 4 26 www ni com Chapter 4 Signal Connections TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter Don t Care uw 2 2 l 2 0 Figure 4 13 Typical Pretriggered Acquisition SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configur
24. from high current or high voltage lines These lines can induce currents in or voltages on the 6052E 6053E device signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits that also contain power lines Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments National Instruments Corporation 4 45 6052E 6053E User Manual Calibration This chapter discusses the calibration procedures for your device If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the 6052E 6053E devices these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for all but the most forgiving applications If you do not calibrate your device your signals and measurements could have very large offset gain and linea
25. full scale range max Digital Trigger Compatibility siissresrsiiiisiisrssssrii TTL RESPONSE vere eea E E EERS Rising or falling edge Pulse width osrin ans 10 ns min RTSI Trigger lines PCI PXI 6052E 6053E e eee 7 Clock life nna r Er a 1 Type PCI PXI 6052E 6053E 0 c00 Master Slave DAQPad 6052E for 1394 0 Master Slave Asynchronous Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A PCI PXI 6052E 6053E 5 VDC 5 oenen tine 1 3 A does not include current drawn from 5 V fuse on I O connector DAQPad 6052E for 1394 A 10 www ni com Appendix A Specifications Physical Dimensions not including connectors PCI 6052E 6053E eee eee 17 5 by 10 6 cm 6 9 by 4 2 in PXI 6052E 6053E eee 16 by 10 cm 6 3 by 3 9 in DAQPad 6052E for 1394 oe 14 6 by 21 6 by 3 8 cm 5 8 by 8 4 by 1 5 in T O connector PCI 6052E s sicsaitecds tain 68 pin male SCSI II type PEI 6053E tice keith aes 100 pin female 0 05 D type Environment Operating temperature 0 to 55 C Storage temperature 00 eee 20 to 70 C Relative humidity eee 5 to 90 noncondensing National Instruments Corporation A 11 6052E 6053E User Manual Custom Cabling and Optional Connectors This appendix describes the various cabling and connector options Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently cha
26. interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages or National Instruments application software your application uses the NI DAQ driver software as illustrated in Figure 1 1 1 4 www ni com Chapter 1 Introduction ComponentWorks Conventional LabVIEW Programming Environment LabWindows CVI or VirtualBench NI DAQ Driver Software Personal ed A Computer or araware Workstation Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware Optional Equipment National Instruments offers a variety of products to use with your device including cables connector blocks and other accessories as follows e Cables and cable assemblies shielded and ribbon e Connector blocks shielded and unshielded 50 and 68 pin screw terminals e RTSI bus cables e SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3 072 channels e Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold and relays For specific information about these products refer to your National Instruments catalogue or Web site or call the office near
27. of the PCI 6052E 6053E and PXI 6052E 6053E is assigned automatically through the PCI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring my device The PCI 6052E 6053E and PXI 6052E 6053E are jumperless and switchless Which National Instruments document should I read first to get started using DAQ software Your NI DAQ or application software release notes documentation is always the best starting place What version of NI DAQ must I have to program my device You must have NI DAQ version 6 5 or later for the PCI 6052E The PXI 6052E requires NI DAQ version 6 6 or later The PCI PXI 6053E require NI DAQ version 6 9 or later What is Firewire Firewire and IEEE 1394 are the same thing Firewire was the original name when the technology was developed by Apple Later Apple turned over the specification to the IEEE for standardization Firewire is a registered trademark of Apple Can I use a 400 Mbyte s 1394 device with a 100 Mbyte s device Yes However the bus slows to the slowest speed So your 400 Mbytes s 1394 device will operate faster if the 100 Mbytes s device is removed from the bus How many devices can I hook up to a 1394 bus Up to 64 different devices including the PC may be attached to a single device C 2 www ni com Appendix C Common Questions Can I hook up the 1394 bus any way I want No You can not have cycles in the bus cabling and
28. options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software or NI DAQ National Instruments Application Software LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software Measurement Studio which contains LabWindows CVI and measurement tools for Visual C and Visual Basic features interactive graphics configurable user interface controls and language customized interfaces to the NI DAQ software through standard ANSI C functions C classes and ActiveX controls With Measurement Studio you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors Using LabVIEW Measurement Studio or VirtualBench software greatly reduces the develop
29. output polarity is software selectable This output is set to tri state at Startup Field Wiring Considerations 6052E 6053E User Manual Environmental noise can seriously affect the accuracy of measurements made with your device if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to analog input signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential analog input connections to reject common mode noise e Use individually shielded twisted pair wires to connect analog input signals to the device With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PCI DAQ system is the video monitor Separate the monitor from the analog signals as much as possible 4 44 www ni com Chapter 4 Signal Connections The following recommendations apply for all signal connections to your device Separate 6052E 6053E device signal lines
30. value of the square of the instantaneous signal amplitude a measure of signal amplitude referenced single ended mode all measurements are made with respect to acommon reference measurement system or a ground Also called a grounded measurement system resistance temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity real time system integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise synchronization of functions G 8 www ni com s S SCANCLK SCXI SE settling time signal conditioning SISOURCE SOURCE S s STARTSCAN system noise TC tgn gsi gw out National Instruments Corporation G 9 Glossary seconds samples scan clock signal Signal Conditioning eXtensions for Instrumentation the National Instruments product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ devices in the noisy PC environment single ended a term used to describe an analog input that is measured with respect to a common ground the amount of time required for a voltage to reach its final value within specified limits the manipulation of signals to prepare them for digitizing SI counter clock signal source signal samples per second used to express the rate at which a DAQ device samples an analog signa
31. you must have fewer than 16 hops between devices What can I do to optimize the performance of my 1394 device There are several things that can be done to optimize the performance of your 1394 device First try to keep your bus running at the fastest speed possible by attaching only devices that are at least at fast as your 1394 device If a 200 Mbytes s device is added to the bus with your 400 Mbytes s DAQ device you will slow the entire bus down to 200 Mbytes s Second minimize the maximum number of hops between the devices on the bus The more hops you have the slower the bus will run Finally remember there is only a limited amount of bandwidth available on the bus If you stream DV at 20 Mbytes s you will hurt your DAQ performance Will 1394 DAQ work with Windows 95 No Microsoft and National Instruments do not support Windows 95 and 1394 Analog Input and Output I m using my device in differential analog input mode and I have connected a differential input signal but my readings are random and drift rapidly What s wrong Check your ground reference connections Your signal can be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the device reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods ar
32. 052E 6053E User Manual Chapter 4 Signal Connections PXI specific features are implemented on the J2 connector of the CompactPCI bus Table 4 1 shows the J2 pins used by your PXI 6052E 6053E Your PXI device is compatible with any CompactPCI chassis with a sub bus that does not drive these lines Even if the sub bus is capable of driving these lines the PXI device is still compatible as long as those pins on the sub bus are disabled by default and not ever enabled Damage can result if these lines are driven by the sub bus Table 4 1 Pins Used by the PXI 6052E 6053E PXI 6052E 6053E Signal PXI Pin Name PXI J2 Pin Number RTSI lt 0 5 gt PXI Trigger lt 0 5 gt B16 A16 A17 A18 B18 C18 RTSI 6 PXI Star D17 RTSI Clock PXI Trigger 7 E16 Reserved LBL lt 0 3 gt C20 E20 A19 C19 Reserved LBR lt 0 12 gt A21 C21 D21 E21 A20 B20 E15 A3 C3 D3 E3 A2 B2 6052E 6053E User Manual 4 4 www ni com Chapter 4 Signal Connections Table 4 2 1 0 Connector Signal Descriptions Signal Name Reference Direction Description AIGND Analog Input Ground These pins are the reference point for single ended measurements in RSE configuration and the bias current return point for differential measurements All three ground references AIGND AOGND and DGND are connected together on your device ACH lt 0 15 gt AIGND Input Analog Input Channels 0 through 15 Ea
33. 1006868 cable assembly with the PCI PXI 6053E Figure B 1 shows the pin assignments for the 68 pin extended analog input connector This is the other 68 pin connector available when you use the SH1006868 cable assembly with the PCI PXI 6053E 6052E 6053E User Manual B 2 www ni com Appendix B Custom Cabling and Optional Connectors ACH 24 ACH 17 ACH 18 ACH 27 ACH 20 ACH 21 ACH 30 ACH 23 ACH 32 ACH 41 ACH 34 ACH 35 AIGND ACH 44 ACH 37 ACH 38 ACH 47 ACH 48 ACH 49 ACH 58 ACH 51 ACH 52 ACH 61 ACH 54 ACH 55 N C N C N C N C N C N C N C N C N C Q A 68 wo wo 67 ee N 66 wo k 65 wo fo 64 N o 63 iw 62 N a 61 S O 60 N oa 59 N A 58 N wo 57 N N 56 N k 55 N fo 54 mh o 53 ak 52 4 N 51 O 50 oa 49 A 48 ar wo 47 ye 46 a 45 fo 44 o 43 42 41 40 39 38 37 36 N AJAN 35 ACH 16 ACH 25 ACH 26 ACH 19 ACH 28 ACH 29 ACH 22 ACH 31 ACH 40 ACH 33 ACH 42 ACH 43 AISENSE2 ACH 36 ACH 45 ACH 46 ACH 39 ACH 56 ACH 57 ACH 50 ACH 59 ACH 60 ACH 53 ACH 62 ACH 63 N C N C N C N C N C N C N C N C N C National Instruments Corporation Figure B 1 68 Pin
34. 15 Figure 4 16 Figure 4 17 Figure 4 18 Figure 4 19 Figure 4 20 Figure 4 21 Figure 4 22 Figure 4 23 Figure 4 24 Figure 4 25 Figure 4 26 Figure 4 27 6052E 6053E User Manual The Relationship between the Programming Environment NI DAQ and Your Hardwate ccccccsccecssscesssseeesneeeeeseeeesseeessseeeesaaes 1 5 PCI and PXI Block Diagram eee eseeeseeneceseeaeseeeeseeneeeaeeseees 3 1 Analog Trigger Block Diagram 0 cece eee eeeeseceeeesetseeeseeaeeneeeaeens 3 7 Below Low Level Analog Triggering Mode ee eeeeeeeeeeeeeeee 3 7 Above High Level Analog Triggering Mode eee eeeeeeeereeee 3 8 Inside Region Analog Triggering Mode eee ee eee eseeeeeeseeeeeeneeee 3 8 High Hysteresis Analog Triggering Mode eee ec eeeeseeseeeeeeeeee 3 8 Low Hysteresis Analog Triggering Mode eee ee eeeeseeseeeeeeeeee 3 9 CONVERT Signal Routing eee cece csceeseceeecseeseeeseeseeeaeeeeeas 3 10 PCI RTSI Bus Signal Connection cece eceeeeeeeseceeeeseeeseeseeeseeneees 3 12 PXI RTSI Bus Signal Connection eee ec ceeeeeseeeeeeseeeseeseeeeeneees 3 13 T O Connector Pin Assignment for 6052E wee eee eeeeeeeeeeeeeee 4 2 T O Connector Pin Assignment for the 6053E oo eee eeeereeee 4 3 PGT Ars aise ea a A osha dias Nase emanate eta 4 10 Summary of Analog Input Connections 0 0 0 eee eeeeee ese eereeseeeeeeaes 4 13 Differential Input Connections for Ground Referenced Signals 4 15 Differential Input Connections for Non
35. 3E device configured in DIFF input mode 6052E 6053E User Manual 4 14 www ni com Chapter 4 Signal Connections ACH O ome Ground 9 6 o e Referenced P o SO o e Signal p Instrumentation V ae Source s Amplifier E 0 so ACH b le poe Measured Connon Voltage Mode n O oo J p Noise and o o Ground Vom Potential Fa I Input Multiplexers AISENSE AIGND 1 0 Connector Selected Channel in DIFF Configuration Figure 4 5 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as Vem in Figure 4 5 National Instruments Corporation 4 15 6052E 6053E User Manual Chapter 4 Signal Connections Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 6 shows how to connect a floating signal source to a channel on the 6052E 6053E device configured in DIFF input mode 1 0 Connector 6052E 6053E User Manual ACH o oo Bias resistors cos Floating See text o So Signal Q Instrumentation Amplifier Source e s o so ACH Measured ro oo Voltage O so gt Bias o So oO Current 7 Return Paths o So P AIGND v
36. 5 50 KQ pu PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at04 5 50 KQ pu 6052E 6053E User Manual 4 8 www ni com Chapter 4 Signal Connections Table 4 3 1 0 Signal Summary Continued Signal Impedance Protection Sink Rise Type and Input Volts Source mA Time Signal Name Direction Output On Off mA at V at V ns Bias PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu GPCTRO_OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 KQ pu FREQ_OUT DO 3 5 at Vec 0 4 5 at 0 4 1 5 50 kQ pu AI Analog InputDIO Digital Input Outputpu pullup AO Analog OutputDO Digital OutputAI DIO Analog Digital Input Output Indicates active low Note The tolerance on the 50 kQ pullup and pulldown resistors is very large Actual value can range between 17 KQ and 100 KQ Analog Input Signal Connections PCI 6052E and PXI 6052E The analog input signals are ACH lt 0 15 gt AISENSE and AIGND The ACH lt 0 15 gt signals are connected to the 16 analog input channels of your 6052E device In single ended mode signals connected to ACH lt 0 15 gt are routed to the positive input of the device PGIA In differential mode signals connected to ACH lt 0 7 gt are routed to the positive input of the PGIA and signals connected to ACH lt 8 15 gt are routed to the negative input of the PGIA PCI 6053E and PXI 6053E The analog input signals are ACH lt 0 63 gt
37. 53E device sharing the RTSI bus The PCI 6052E 6053E and PXI 6052E 6053E have seven trigger lines These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 9 For the PXI 6052E 6053E National Instruments Corporation 3 11 6052E 6053E User Manual Chapter 3 Hardware Overview the RTSI trigger lines connect to other devices through the PXI bus on the PXI backplane RTSI lt 0 5 gt connect to PXI Trigger lt 0 5 gt respectively RTSI lt 6 gt connects to PXI Star This signal connection scheme is shown in Figure 3 10 a DAQ STC lt TRIG lt _ __ TRIG2 lt _ CONVERT lt _ _ gt _ UPDATE lt WFTRIG lt __ _ _ GPCTRO_SOURCE lt gt GPCTRO_GATE GPCTRO_OUT _ STARTSCAN gt AIGATE SISOURCE gt UISOURCE GPCTR1_SOURCE gt GPCTR1_GATE switch lt ____ _ RTSI_OSC 20 MHz Trigger RTSI Bus Connector RTSI Switch Clock Figure 3 9 PCI RTSI Bus Signal Connection 6052E 6053E User Manual 3 12 www ni com Chapter 3 PXI Bus Connector PXI Star 6 PXI Trigger 0 5 RTSI Switch PXI Trigger 7 switch DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE G
38. ATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Contents About This Manual Conventions Used in This Manual ccccccssccsssseceeseecesneeeesseeeessseeesseeeessseeessneeensaeees xi Related Documentation nioran E atin ee as xii Chapter 1 Introduction About the 6052E 6053E DEVICES nr a RE RER 1 1 Using PXI with CompactPCI 0 sicicssssccsetasccessesctest eprorin ieai iiias esasa Eaa 1 2 What You Need to Get Startedsnieriei o a E E E AE 1 2 Software Programming Choices isene si ai si ia ia 1 3 National Instruments Application Software cee ees eeeeseeseeseesseeeeeseenees 1 3 NI DAQ Driver Software ccccccccssceeesseeesseeesseeeessaeeeseseeeseeeesseeesseeesseeens 1 4 Optional Equipment sore ieran ene a ER E E E NE sine adiaiaiewnte 1 5 Chapter 2 Installation and Configuration Software Installations r cacao A RL 2 1 Unpacking cccies nica suche n Rid aca A AE A E EN N N E 2 1 Hard ware installa O a a a a e E n rar a 2 1 Comm uration osen a a a a a a a a E SES 2 3 Chapter 3 Hardware Overview Analog Mnputins snn a a dhe este ve eee A 3 2 Input Mod s c c cccsceaceveise 4 ctasstecth a E R ERE E i tines 3 2 Input Polarity and Input Range eee eee ceeceesseeeseeeceeeeseeeeesesneeeaeenaes 3 3 Considerations for Selecting Input Ranges 0 0 eee eeeeeeeeeees 3 4 Multichannel Scanning Considerations 0 0 0 eee eeeeeeseceeeeseeseeeseeeeeeateeenaes 3 4 Analog Outputs siete sewed E a E e s
39. Cs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 300 to 350 ns This output is set to tri state at startup Figures 4 27 and 4 28 show the input and output timing requirements for the UPDATE signal i t i lt Rising Edge Polarity o Falling Edge Polarity tw 10 ns minimum Figure 4 27 UPDATE Input Signal Timing tw 300 350 ns Figure 4 28 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches 4 36 www ni com Chapter 4 Signal Connections The 6052E 6053E UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate When using an external UPDATE signal you must supply at least one more external update pulse than the number of points that you want to generate This is necessary for proper hardware operation otherwise the device does not indicate that the waveform
40. DAQ 6052E 6053E User Manual Multifunction 1 0 Device for PCI PXI 1394 Bus Computers Qr NATIONAL August 2000 Edition gt INSTRUMENTS Part Number 322138C 01 Worldwide Technical Support and Product Information www ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 794 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Calgary 403 274 9391 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 China 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 528 94 06 Portugal 351 1 726 9011 Singapore 2265886 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support Resources appendix To comment on the documentation send e mail to techpubs ni com Copyright 1999 2000 National Instruments Corporation All rights reserved Important Information Warranty The PCI 6052E 6053E PXI 6052E 6053E and DAQPad 6052E for 1394 are warranted agai
41. FIFO stores the results of A D conversions until the data can be retrieved into system memory a process that requires the servicing of interrupts and often the programming of the DMA controller This process can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored on the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device frequency output signal feet gate signal general purpose counter general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down general purpose counter gate signal general purpose counter output signal general purpose counter clock source signal general purpose counter up down 6052E 6053E User Manual Glossary Toy INL LSB MB MIO MITE MSB mux 6052E 6053E User Manual hour hexadecimal hertz the number of scans read or updates written per second input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current output low integral nonlinearity a mea
42. ONVERT Signal Any PFI pin can externally input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 12 and 4 13 for the relationship of CONVERT to the DAQ sequence As an input the CONVERT signal is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC This is true even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 22 and 4 23 show the input and output timing requirements for the CONVERT signal Rising Edge Polarity i Falling Edge m Polarity tw 10 ns minimum Figure 4 22 CONVERT Input Signal Timing 4 32 www ni com Chapter 4 Signal Connections i ty 50 100 ns i Figure 4 23 CONVERT Output Signal Timing The ADC switches to hold mode within 60 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next Separate the CONVERT pulses by at least one conversion period The sample interval counter on the 6052E 6053E normally genera
43. OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER CAN USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRI
44. PCTRO_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz Refer to the Timing Connections section of Chapter 4 Signal Connections Figure 3 10 PXI RTSI Bus Signal Connection for a description of the signals shown in Figures 3 9 and 3 10 National Instruments Corporation 3 13 6052E 6053E User Manual Hardware Overview Signal Connections 1 0 Connector This chapter describes how to make input and output signal connections to your device via the device I O connector The I O connector has 68 pins on the 6052E that you can connect to 68 pin accessories with the SH6868 shielded cable or the R6868 ribbon cable You can connect your device to 50 pin signal conditioning modules and terminal blocks with the SH6850 shielded cable or R6850 ribbon cable The I O connector for 6053E has 100 pins that you can connect to 100 pin accessories with the SH100100 shielded cable With the SH1006868 shielded cable you can connect your device to the 68 pin accessories With the R1005050 ribbon cable you can connect your device to 50 pin accessories Figure 4 1 shows the pin assignments for the 68 pin I O connector Figure 4 2 shows the pin assignments for the 100 pin I O connector Refer to Appendix B Custom Cabling and Optional Connectors for the pin assignments of the 50 pin connector A signal description follows the figures UN Caution Connections that exceed any of the maximu
45. PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as V and V input signals are both within 11 V of AIGND 6052E 6053E User Manual 4 20 www ni com Chapter 4 Signal Connections Analog Output Signal Connections The analog output signals are DACOOUT DACIOUT EXTREF and AOGND DACOOUT is the voltage output signal for analog output channel 0 DACI1OUT is the voltage output signal for analog output channel 1 EXTREF is the external reference input for both analog output channels You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel will use the internal reference Analog output configuration options are explained in the Analog Output section in Chapter 3 Hardware Overview The following ranges and ratings apply to the EXTREF input e Usable input voltage range 11 V peak with respect to AOGND e Absolute maximum ratings 15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels and the external reference signal Figure 4 9 shows how to make analog output connections and the external reference input connection to your device National Instruments Corporation 4 21 6052E 6053E User Manual Chapter
46. Q to perform high speed scanning Due to problems with settling times multichannel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as nearly simultaneously as possible The data is much more accurate and channel to channel independent if you acquire data from each channel independently for example 100 points from channel 0 then 100 points from channel 1 then 100 points from channel 2 and so on Analog Output The 6052E 6053E devices supply two channels of analog output voltage at the I O connector The reference and range for the analog output circuitry is software selectable The reference can be either internal or external whereas the range can be either bipolar or unipolar Analog Output Reference Selection You can connect each D A converter DAC to an internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I O connector This signal applied to EXTREF should be within 11 V You do not need to configure both channels for the same mode Analog Output Polarity Selection You can configure each analog output channel for either unipolar or bipolar output A unipolar configuration has a range of 0 to Ve at the analog output A bipolar configuration has a range of Vef to V ef at the analog output Vef is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an exte
47. able as an output on the I O connector General purpose counter counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 36 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your device 4 42 www ni com Chapter 4 Signal Connections i tsc gt q tsp gt q tsp gt V i i i sore ONO A KTO yA NN V IL gt i tou t gt i ton je GATE IH OK X IL lt on gt lt lt tout gt V f OUT OH i V L OL Source Clock Period tea 50 ns minimum Source Pulse Width tsp 23 ns minimum Gate Setup Time tgsu 10 ns minimum Gate Hold Time tgh Ons minimum Gate Pulse Width tow 10 ns minimum Output Delay Time tout 80 ns maximum Figure 4 36 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 36 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges If the counter was programmed to count falling edges the source signal would be inverted and referenced to the falling edge of the source signal in Figure 4 36 The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your device Figure 4 36 shows the GATE si
48. and driving external devices such as the LED shown in the figure 5 V A LED ae a WW a DIO lt 4 7 gt gt l TTL Signal o gt DIO lt 0 3 gt 5 V VW gt Switch as DGND 1 0 Connector T Figure 4 10 Digital 1 0 Connections 6052E 6053E Device National Instruments Corporation 4 23 6052E 6053E User Manual Chapter 4 Signal Connections Power Connections Two pins on the I O connector supply 5 V from the computer power supply via a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry The fuse power rating is 4 65 to 5 25 VDC at 1 A UN Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the device or any other device Doing so can damage the device and the computer National Instruments is not liable for damages resulting from such a connection Timing Connections UN Caution Exceeding the maximum input voltage ratings that are listed in Tables 4 3 can damage your device and the computer National Instruments is not liable for any damages resulting from such signal connections 6052E 6053E User Manual All external control over the timing of your device is routed through the 10 programma
49. any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTRO_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startup Figure 4 30 shows the timing requirements for the GPCTRO_SOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 30 GPCTRO_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source 4 38 www ni com Chapter 4 Signal Connections GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects the actual gate signal connected to general purpose c
50. ble function inputs labeled PFIO through PFI9 These signals are explained in detail in the section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section in this chapter The waveform generation signals are explained in the Waveform Generation Timing Connections section in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section in this chapter All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 11 which shows how to connect an external TRIGI source and an external CONVERT source to two 6052E 6053E PFI pins 4 24 www ni com Chapter 4 Signal Connections PFIO TRIG1 PFI2 CONVERT TRIG1 CONVERT Source Source DGND fo v 1 0 Connector 6052E 6053E Device Figure 4 11 Timing I O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externa
51. ch channel pair ACH lt i i 8 gt i 0 7 can be configured as either one differential input or two single ended inputs ACH lt 16 63 gt AIGND Input Analog Input Channels 16 through 63 6053E only Each channel pair ACH lt i i 8 gt i 16 23 32 39 48 55 can be configured as either one differential input or two single ended inputs AISENSE AIGND Input Analog Input Sense This pin serves as the reference node for any of channels ACH lt 0 15 gt in NRSE configuration AISENSE2 AIGND Input Analog Input Sense 6053E only This pin serves as the reference node for any of channels ACH lt 16 63 gt in NRSE configuration DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 EXTREF AOGND Input External Reference This is the external reference input for the analog output circuitry AOGND Analog Output Ground The analog output voltages are referenced to this node All three ground references AIGND AOGND and DGND are connected together on your 6052E 6053E device DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply All three ground references AIGND AOGND and DGND are connected together
52. clocks 3 11 programmable function inputs 3 11 RTSI triggers 3 11 to 3 13 TRIGI signal 4 28 to 4 29 TRIG signal 4 29 to 4 30 trigger specifications A 9 to A 10 analog trigger A 9 to A 10 digital trigger A 10 RTSI trigger A 10 triggers analog trigger 3 6 to 3 9 RTSI triggers 3 11 to 3 13 U UISOURCE signal 4 37 unipolar input 3 3 unipolar output 3 5 unpacking 6025E devices 2 1 UPDATE signal 4 36 to 4 37 www ni com Index V Web support from National Instruments D 1 VCC signal table 4 8 WETRIGsignal 33 VirtualBench software 1 3 Worldwide technical support D 2 voltage output specifications A 7 W waveform generation glitches in C 3 to C 4 waveform generation timing connections 4 34 to 4 37 UISOURCE signal 4 37 UPDATE signal 4 36 to 4 37 WFTRIG signal 4 35 National Instruments Corporation I 9 6052E 6053E User Manual
53. conversion comes from PFI5 as follows e Ifyou are using NI DAQ call Select_Signal deviceNumber ND_IN CONVERT ND PFI_5 ND HIGH TO LOW e If you are using LabVIEW invoke AI Clock Config VI with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate analog input data acquisition which will start only when the analog output waveform generation starts 4 Initiate analog output waveform generation Timing and Digital 1 0 6052E 6053E User Manual What types of triggering can be hardware implemented on my device Digital triggering is hardware supported as well as analog triggering in hardware What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering C 4 www ni com Appendix C Common Questions selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement What is the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO devices have a 20 MHz timebase The Am9513 based MIO devices have a 1 MHz or 5 MHz timebase Will the c
54. cts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication cannot be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks ComponentWorks CVI DAQ STC LabVIEW Measure Measurement Studio MITE National Instruments ni com NI DAQ NI PGIA PXI RTSI SCXI and VirtualBench are trademarks of National Instruments Corporation FireWire is a trademark of Apple Computer Inc Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER
55. e 4 8 documentation conventions used in manual xi xii related documentation xii E EEPROM storage of calibration constants 5 1 environment specifications A 11 environmental noise 4 44 to 4 45 equipment optional 1 5 EXTREF signal analog output reference selection 3 5 analog output signal connections 4 21 to 4 22 description table 4 5 T O signal summary table 4 8 EXTSTROBE signal DAQ timing connections 4 27 to 4 28 description table 4 6 T O signal summary table 4 8 6052E 6053E User Manual Index F field wiring considerations 4 44 to 4 45 floating signal sources description 4 11 differential connections 4 16 to 4 17 single ended connections RSE configuration 4 19 FREQ_OUT signal description table 4 7 general purpose timing signal connections 4 44 I O signal summary table 4 9 frequently asked questions See questions and answers fuse self resetting C 1 G gain error adjusting 5 3 general purpose timing signal connections 4 38 to 4 44 FREQ _ OUT signal 4 44 GPCTRO_GATE signal 4 39 GPCTRO_OUT signal 4 40 GPCTRO_SOURCE signal 4 38 GPCTRO_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal 4 42 GPCTR1_SOURCE signal 4 40 to 4 41 GPCTR1_UP_DOWN signal 4 42 to 4 44 glitches analog output reglitch 3 6 waveform generation glitches C 3 to C 4 GPCTRO_GATE signal 4 39 GPCTRO_OUT signal description table 4 7 general purpose timing signal co
56. e as much room as possible between the PCI 6052E 6053E and PXI 6052E 6053E and other devices You can connect your DAQPad 6052E to any available 1394 port The following National Instruments Corporation 2 1 6052E 6053E User Manual Chapter 2 Installation and Configuration 6052E 6053E User Manual are general installation instructions Consult your computer user manual or technical reference manual for specific instructions and warnings PCI 6052E 6053E 1 2 3 4 9 Turn off and unplug your computer Remove the top cover of your computer Remove the expansion slot cover on the back panel of the computer Touch any metal part of your computer chassis to discharge any static electricity that might be on your clothes or body Insert your device into a5 V PCI slot Gently rock the device to ease it into place It can be a tight fit but do not force the device into place If required screw the mounting bracket of the PCI 6052E 6053E to the back panel rail of the computer Visually verify the installation Replace the cover Plug in and turn on your computer The PCI 6052E 6053E is now installed PXI 6052E 6053E 1 2 6 Turn off and unplug your computer Choose an unused PXI slot in your system For maximum performance the PXI 6052E 6053E has an onboard DMA controller that can only be used if the device is installed in a slot that supports bus arbitration or bus master cards National Instruments recomm
57. e has not been measured for a year or more you can wish to externally calibrate your device An external calibration refers to calibrating your device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your device by calling the NI DAQ calibration function To externally calibrate your device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For example to calibrate a 16 bit device the external reference should be at least 0 001 10 ppm accurate 5 2 www ni com Chapter 5 Calibration Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information Gain error and offset error are temperature dependent Take care to p
58. e outlined in Chapter 4 Signal Connections I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter to remove some of these glitches depending on the National Instruments Corporation C 3 6052E 6053E User Manual Appendix C Common Questions frequency and nature of your output signal See the Analog Output Reglitch section in Chapter 3 Hardware Overview for more information about reglitching Can I synchronize a one channel analog input data acquisition with a one channel analog output waveform generation on my device Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFIS5 line for output as follows e Ifyou are using NI DAQ call Select Signal deviceNumber ND _PFI_5 ND_OUT_ UPDATE ND HIGH TO LOW e Ifyou are using LabVIEW invoke Route Signal VI with signal name set to PFI5 and signal source set to AO Update 2 Set up data acquisition timing so that the timing signal for A D
59. e signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup National Instruments Corporation 4 4 6052E 6053E User Manual Chapter 4 Signal Connections Figure 4 34 shows the timing requirements for the GPCTR1_GATE signal Rising Edge Polarity i Falling Edge m Polarity tw 10 ns minimum Figure 4 34 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 35 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle Output on TC 6052E 6053E User Manual Figure 4 35 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not avail
60. ed so that a low to high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 14 shows the timing for the SCANCLK signal CONVERT t amr 1 tw SCANCLK tg 50 to 100 ns tw 400 to 500 ns Figure 4 14 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of the EXTSTROBE signal A 10 Us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware strobe mode Figure 4 15 shows the timing for the hardware strobe mode EXTSTROBE signal National Instruments Corporation 4 27 6052E 6053E User Manual Chapter 4 Signal Connections 6052E 6053E User Manual VOH VOL lt gt t w ty 600 ns or 5 us Figure 4 15 EXTSTROBE Signal Timing TRIG1 Signal Any PFI pin can externally input the TRIG1 signal which is available as an output on the PFIO TRIG1 pin Refer to Figures 4 12 and 4 13 for the relationship of TRIG1 to the DAQ sequence As an input the TRIG1 signal is configured in the edge detection mode You can selec
61. eeeeeeseeeeees 4 4 Table 4 2 T O Connector Signal Descriptions eee eee eeeeseeeeeeeeeeteeeeseeeeees 4 5 Table 4 3 T O Signal Summary cenuen ia ie i 4 8 National Instruments Corporation ix 6052E 6053E User Manual About This Manual This manual describes the electrical and mechanical aspects of the PCI 6052E 6053E PXI 6052E 6053E and DAQPad 6052E and contains information concerning operation and programming The PCI 6052E 6053E PXI 6052E 6053E and DAQPad 6052E are high performance multifunction analog digital and timing I O devices for PCI PXI and 1394 computers Supported functions include analog input analog output digital I O and timing I O Conventions Used in This Manual lt gt bold CompactPCI italic monospace The following conventions are used in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt The symbol indicates that the following text applies only to a specific product a specific operating system or a specific software version This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash Bold text denotes items that you must select or click on in the software such as menu items and dialog box options Bold text also denotes parameter na
62. eeensetseeeaees 4 16 Single Ended Connection Considerations 000 000 ccc ecesesseeseeeeeeseceeenseeeeeenees 4 18 Single Ended Connections for Floating Signal Sources RSE Configuration ita eiiies Gest AE E EENS 4 19 Single Ended Connections for Grounded Signal Sources NRSE Configuration 0 cceeseescceseceseeceseeesceceaeceeeeeneceeeeneeeeaees 4 19 Common Mode Signal Rejection Considerations cece eeeeseeeeereeeees 4 20 Analog Output Signal Connections 0 cece eee eeseeeececeeseeeeeeseceeeeseeseeeaeeseceseceeeaeeaeenaes 4 21 Digital I O Signal Connections 0 eee eee eeeeeesececeeseeeeecsesseeeaeeseeeseseeseaeeseseaeenseeaes 4 22 Power Connections sertesa ena a tutes eves E AE E E E EN 4 24 Timing ConnectiOns ia n Eea eta da wie ea as 4 24 Programmable Function Input Connections 00 eee eee eseeeeereeeeeeeeneeeaes 4 25 DAQ Timing Connections isses a o 4 26 SCANCCK Signals ensenen a ence Re ea ai tee a 4 27 EXTSTROBE Signals casi kai wens Glande eee 4 27 TRIGI Sinal iine narrue ea verte steed cpiveess Ranges anes 4 28 TRIG2 Signal sets eit aa nahn eee ts ela 4 29 STARTSCAN Sigh l sorrerak sated E E E EREE 4 30 CONVERT Signal aisiateccisia ennn ar e e aa ea 4 32 AIGATE Signal or oar E E A NE a E i ES 4 33 SISOURCE Signal senie eie E ie RN EE S 4 34 Waveform Generation Timing Connections eseesessesseresesrerrersersrrersrrsrsrese 4 34 WETRIG Signalen e e A ae ee 4 35 UPDATE Signalo e e E EET AE E
63. een E en A aan eines E 3 5 Analog Output Reference Selection 00 ee cece eseceeeseeseeeseeeeeseeneceseeneenaes 3 5 Analog Output Polarity Selection eee eeeeseeseeeseeseeeseeseeeseeseenseeaeenaes 3 5 Analog Output Reglitch eee eee ceeceseceeeeseceeessecseeesececeaseeeeaesneeeaeenees 3 6 ANALOG LTE BER scat css Sia e Ea E EE EEEE K E EE EIRA EER 3 6 Digital NLO E ieee ae A E E E SE 3 9 Timing Signal ROUTO ee re e EEE E T E A A EAE EEEE 3 10 Programmable Function Inputs sssesssessssessssesssrsresreresresrsresresrrsestresreresestse 3 11 National Instruments Corporation v 6052E 6053E User Manual Contents Device and RISE Clocks iii nnie a e a n l a ai 3 11 RIESE TUG gers i n a aiar aa a rap a dash apcestsevtady 3 11 Chapter 4 Signal Connections TVO CODE COR es ies aaeoa Ee REEE E EEE E E R 4 1 Analog Input Signal ConnectionS s sesseessereesesrrsresesresesrrsrestsresesresreseneentesrsresresentees 4 9 Types of Signal SOULCES nenien neee r E e e E E Ea 4 11 Floating Signal Sour eSynsin e Gained tee eae 4 11 Ground Referenced Signal Sources sesseseseesseeeseesessesrrsrssesrestsresrerereesresesee 4 11 Input Configurations siene a a a a EE ee hate A ARN 4 12 Differential Connection Considerations DIFF Input Configuration 4 14 Differential Connections for Ground Referenced Signal Sources 4 14 Differential Connections for Nonreferenced or Floating Signal Sources eee eeseeseeseceeeeeeeesee
64. els at various gains the settling times can increase When the PGIA switches to a higher gain the signal on the previous channel can be well outside the new smaller range For instance suppose a 4 V signal is connected to channel 0 and a mV signal is connected to channel 1 and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1 When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100 the new full scale range is 100 mV if the ADC is in unipolar mode The approximately 4 V step from 4 V to 1 mV is 4 000 of the new full scale range For a 16 bit device to settle within 0 0015 15 ppm or 1 LSB of the 100 mV full scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It can take as long as 200 us for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected If the impedance of the source is not low enough 3 4 www ni com Chapter 3 Hardware Overview the effect of the charge a voltage error will not have decayed by the time the ADC samples the signal For this reason keep source impedances under 1 k
65. ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels centimeter complementary metal oxide semiconductor common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB unwanted signals that appear in equal phase and amplitude on both the inverting and noninverting input in a differential measurement system Ideally but not completely in practice the measurement device ignores this noise because the measurement device is designed to respond to the difference between the inverting and noninverting inputs convert signal a circuit that counts external pulses or clock pulses timing counter digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current analog channel 0 output signal analog channel output signal 6052E 6053E User Manual Glossary DAQ dB DC DGND DIFF DIO DIP dithering DMA DNL DO E EEPROM EXTREF EXTSTROBE 6052E 6053E User Manual data acquisition 1 collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 collecting and measuring the same kinds of electrical signals with A D and or DIO devic
66. ends installing the PXI 6052E 6053E in such a slot The PXI specification requires all slots to support bus master cards but the CompactPCI specification does not If you install in a CompactPCI non master slot you must disable the PXI 6052E 6053E onboard DMA controller using software Remove the filler panel for the slot you have chosen Insert the PXI 6052E 6053E into a 5 V PXI slot Use the injector ejector handle to fully insert the device into the chassis Screw the front panel of the PXI 6052E 6053E to the front panel mounting rail of the system Plug in and turn on your computer The PXI 6052E 6053E is now installed 2 2 www ni com Chapter 2 Installation and Configuration DAQPad 6052E for 1394 3 Note Ifyou are not using the BP 1 battery pack follow the instructions in the next section If you are using the BP 1 battery pack follow the installation instructions in your BP 1 installation guide and disregard step 1 in this section 1 Connect the power cord to the wall outlet and the DAQPad device 2 Connect the 1394 cable from the computer or any other 1394 device to the port on your DAQPad device Your computer should detect your DAQPad device immediately When the computer recognizes your DAQPad devicel the COM LED on the front panel will blink Refer to the Configuration section for information on LEDs 3 The power LED should be on Refer to the Configuration section for information on LEDs 4 Configure yo
67. ere is some gain error from loading down the source National Instruments Corporation 4 17 6052E 6053E User Manual Chapter 4 Signal Connections Single Ended Connection Considerations A single ended connection is one in which the analog input signal is referenced to a ground that can be shared with other input signals The input signal is tied to the positive input of the PGIA and the ground is tied to the negative input of the PGIA When every channel is configured for single ended input up to 16 analog input channels on the 6052E and 64 input channels on the 6053E are available You can use single ended input connections for any input signal that meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the 6052E 6053E are less than 10 ft 3 m e The input signal can share a common reference point with other signals DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions Using your software you can configure the 6052E 6053E channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the 6052E 6053E provides the reference ground point for the external signal The NRSE input configuration is used for ground referenced signal sources in this case the external signal s
68. es plugged into a computer and possibly generating control signals with D A and or DIO devices in the same computer decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log o V V2 for signals in volts direct current digital ground signal differential mode digital input output dual inline package the addition of Gaussian noise to an analog input signal direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB digital output electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed external reference signal external strobe signal G 4 www ni com FIFO FREQ OUT ft G GATE GPCTR GPCTRO_GATE GPCTRO_OUT GPCTRO_SOURCE GPCTRO_UP_DOWN GPCTR1_GATE GPCTR1_OUT GPCTR1_SOURCE GPCTR1_UP_DOWN National Instruments Corporation G 5 Glossary first in first out memory buffer the first data stored is the first data sent to the acceptor FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output For example an analog input
69. est you National Instruments Corporation 1 5 6052E 6053E User Manual Installation and Configuration This chapter explains how to install and configure your device Software Installation Unpacking Install your software before you install your device Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence If you are using LabVIEW Measurement Studio other National Instruments application software packages or the NI DAQ driver software refer to the appropriate release notes After you have installed your application software refer to your NI DAQ release notes and follow the instructions given there for your operating system and application software package Your device is shipped in an antistatic package to prevent electrostatic damage Electrostatic discharge can damage several components on the device To avoid such damage in handling the device take the following precautions e Remove the device from the package and inspect the device for loose components or any other sign of damage Notify National Instruments if the device appears damaged in any way Do not install a damaged device into your computer e Never touch the exposed pins of connectors Hardware Installation You can install your PCI 6052E 6053E or PXI 6052E 6053E in any available 5 V PCI or PXI slot respectively in your computer However to achieve best noise performance leav
70. for the TRIG2 signal Rising Edge Polarity i Falling Edge i m Polarity tw 10 ns minimum Figure 4 18 TRIG2 Input Signal Timing tw 50 100 ns i Figure 4 19 TRIG2 Output Signal Timing STARTSCAN Signal Any PFI pin can externally input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 12 and 4 13 for the relationship of STARTSCAN to the DAQ sequence As an input the STARTSCAN signal is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of the STARTSCAN signal initiates a scan The sample interval counter starts if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress 4 30 www ni com STARTSCAN Start Pulse CONVERT STARTSCAN Chapter 4 Signal Connections STARTSCAN will be deasserted t s after the last conversion in the scan is initiated This output is set
71. front panel user interface and a block diagram program volts input high volts input low G 10 www ni com Glossary Vin volts in Vin measured voltage Vou volts output high VoL volts output low V ief reference voltage Vrms volts root mean square W waveform multiple voltage readings taken at a specific sampling rate WFTRIG waveform generation trigger signal National Instruments Corporation G 11 6052E 6053E User Manual Index Numbers 5 V signal description table 4 5 self resetting fuse C 1 6052E 6053E devices See also hardware overview block diagram 3 1 features 1 1 to 1 2 optional equipment 1 5 requirements for getting started 1 2 to 1 3 software programming choices 1 3 to 1 5 National Instruments application software 1 3 NI DAQ driver software 1 4 to 1 5 using PXI with CompactPCI 1 2 A ACH lt 0 15 gt signals analog input signal connections 4 9 description table 4 5 ACH lt 16 63 gt signals analog input signal connections 4 9 description table 4 5 T O signal summary table 4 8 AIGATE signal 4 33 to 4 34 AIGND signal analog input signal connections 4 9 to 4 10 description table 4 5 T O signal summary table 4 8 AISENSE signal analog input signal connections 4 9 description table 4 5 T O signal summary table 4 8 NRSE mode 4 10 National Instruments Corporation AISENSE2 signal analog input signal connections 4 9 description table 4 5 T O s
72. ftware configured All 6052E 6053E devices use the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamless sampling rate change With other DAQ devices you cannot easily synchronize several measurement functions to a common trigger or timing event The 6052E 6053E devices have the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of the National Instruments RTSI bus interface and a cable to route timing and trigger signals between several functions on as many as five DAQ devices in your computer National Instruments Corporation 1 1 6052E 6053E User Manual Chapter 1 Introduction The 6052E 6053E devices can interface to an SCXI system so that you can acquire over 3 000 analog signals from thermocouples RTDs strain gauges voltage sources and current sources You can also acquire or generate digital signals for communication and control SCX is the instrumentation front end for plug in DAQ devices Detailed specifications of the 6052E 6053E devices are in Appendix A Specifications Using PXI with CompactPCI Using
73. general use GPCTR1_ SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge 4 40 www ni com Chapter 4 Signal Connections As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is being externally generated by another PFI This output is set to tri state at startup Figure 4 33 shows the timing requirements for the GPCTR1_SOURCE signal 1 tp 1 Ad e 1 tw 1 w 1 tp 50 ns minimum tw 23 ns minimum Figure 4 33 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gat
74. generation is complete UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 29 shows the timing requirements for the UISOURCE signal tp 50 ns minimum ty 23 ns minimum Figure 4 29 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source National Instruments Corporation 4 37 6052E 6053E User Manual Chapter 4 Signal Connections General Purpose Timing Signal Connections 6052E 6053E User Manual The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTRO_SOURCE Signal Any PFI pin can externally input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input the GPCTRO_SOURCE signal is configured in the edge detection mode You can select
75. gital I O A 8 environment A 11 physical A 11 GPCTR1_SOURCE signal 4 40 to 4 41 GPCTR1_UP_DOWN signal 4 42 to 4 44 overview 4 24 to 4 25 programmable function input connections 4 25 to 4 26 timing I O connections figure 4 25 waveform generation timing connections 4 34 to 4 37 UISOURCE signal 4 37 UPDATE signal 4 36 to 4 37 WFTRIG signal 4 35 timing I O common questions C 4 to C 6 T specifications A 8 to A 9 timing signal routing 3 9 to 3 13 CONVERT signal routing figure 3 10 power requirement A 10 timing I O A 8 to A 9 triggers A 9 to A 10 analog trigger A 9 to A 10 digital trigger A 10 RTSI trigger A 10 STARTSCAN signal 4 30 to 4 32 system integration by National Instruments D 1 technical support resources D 1 to D 2 timing connections 4 24 to 4 44 DAQ timing connections 4 26 to 4 34 AIGATE signal 4 33 to 4 34 CONVERT signal 4 32 to 4 33 EXTSTROBE signal 4 27 to 4 28 SCANCLK signal 4 27 SISOURCE signal 4 34 STARTSCAN signal 4 30 to 4 32 TRIGI signal 4 28 to 4 29 TRIG signal 4 29 to 4 30 typical posttriggered acquisition figure 4 26 typical pretriggered acquisition figure 4 27 general purpose timing signal connections 4 38 to 4 44 FREQ _ OUT signal 4 44 GPCTRO_GATE signal 4 39 GPCTRO_OUT signal 4 40 GPCTRO_SOURCE signal 4 38 GPCTRO_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal 4 42 6052E 6053E User Manual l 8 device and RTSI
76. gnal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and tgn in Figure 4 36 The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources National Instruments Corporation 4 43 6052E 6053E User Manual Chapter 4 Signal Connections The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the 6052E 6053E Figure 4 36 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal generated from the 6052E 6053E device frequency generator is available only as an output on the FREQ_OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The
77. he DAQ STC that can be controlled by an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable Figure 3 8 shows an example of the signal routing multiplexer controlling the CONVERT signal RTSI Trigger lt 0 6 gt lt p Sample Interval Counter TC gt gt gt CONVERT PFI lt 0 9 gt lt GPCTRO_OUT mie 6052E 6053E User Manual Figure 3 8 CONVERT Signal Routing This figure shows that CONVERT can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO_OUT 3 10 www ni com Chapter 3 Hardware Overview Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs Ten PFI signals are connected to the signal routing multiplexer for each timing signal and software can select one of the PFI pins as the external source for a given timing signal It is important to note that any of the PFI pins can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections
78. house technical resources or other dilemmas you may prefer to employ consulting or system integration services You can rely on the expertise available through our worldwide network of Alliance Program members To find out more about our Alliance system integration solutions visit the System Integration section of www ni com National Instruments Corporation D 1 6052E 6053E User Manual Appendix D Technical Support Resources Worldwide Support National Instruments has offices located around the world to help address your support needs You can access our branch office Web sites from the Worldwide Offices section of www ni com Branch office web sites provide up to date contact information support phone numbers e mail addresses and current events If you have searched the technical support resources on our Web site and still cannot find the answers you need contact your local office or National Instruments corporate Phone numbers for our worldwide offices are listed at the front of this manual 6052E 6053E User Manual D 2 www ni com Glossary Prefix Meanings Value p pico 10 2 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 Numbers Symbols percent positive of or plus negative of or minus gt greater than gt greater than or equal to lt less than lt less than or equal to per E degree Q ohm Wo square r
79. igh impedance state after power on and Table 4 1 shows that there is a 50 kQ pull up resistor This pull up resistor will set the DIO 0 pin to a logic high when the output is in a high impedance state 6052E 6053E User Manual C 6 www ni com Technical Support Resources Web Support National Instruments Web support is your first stop for help in solving installation configuration and application problems and questions Online problem solving and diagnostic resources include frequently asked questions knowledge bases product specific troubleshooting wizards manuals drivers software updates and more Web support is available through the Technical Support section of www ni com NI Developer Zone The NI Developer Zone at ni com zone is the essential resource for building measurement and automation systems At the NI Developer Zone you can easily access the latest example programs system configurators tutorials technical news as well as a community of developers ready to share their own techniques Customer Education National Instruments provides a number of alternatives to satisfy your training needs from self paced tutorials videos and interactive CDs to instructor led hands on courses at locations around the world Visit the Customer Education section of www ni com for online course schedules syllabi training centers and class registration System Integration If you have time constraints limited in
80. ignal Connections Table 4 2 1 0 Connector Signal Descriptions Continued Signal Name Reference Direction Description PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs Output As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is one of the PFIs Output As an output this is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output National Instruments Corporation 4 7 6052E 6053E User Manual Chapter 4 Signal Connections
81. ignal Timing eee eeereceeeeeeneeteeeeeeeeenees 4 35 WFTRIG Output Signal Timing 00 eee eeeeeeeeeeceeeeeeeeeeaees 4 35 UPDATE Input Signal Timing oo cece eeeeceeceeeseeeeeeaeeeeens 4 36 viji www ni com Contents Figure 4 28 UPDATE Output Signal Timing 00 eee eee ceeetetseeeeeeaees 4 36 Figure 4 29 UISOURCE Signal Timing eee ceeeseeseceeeeaeeeeeeaeeneeeseenaes 4 37 Figure 4 30 GPCTRO_SOURCE Signal Timing oo ee eeceseeeeeeeteeeeeeeees 4 38 Figure 4 31 GPCTRO_GATE Signal Timing in Edge Detection Mode 000000 4 39 Figure 4 32 GPCTRO_OUT Signal Timing 0 0 eeeeeceeceeeeeeeeeeeeeeeaes 4 40 Figure 4 33 GPCTR1_SOURCE Signal Timing oo eee ceeeseeeeeeereeeeseenees 4 41 Figure 4 34 GPCTR1_GATE Signal Timing in Edge Detection Mode 00000 4 42 Figure 4 35 GPCTR1_OUT Signal Timing 000 eee eeecnecneeeeeeeeeeeeees 4 42 Figure 4 36 GPCTR Timing Summary ees eeceeseceeenecesecseeneeesesneeeaeenaes 4 43 Figure B 1 68 Pin Extended Analog Input Connector Pin Assignments B 3 Figure B 2 50 Pin Connector Pin Assignment cceeceseeeeseeseeeseeeeeeeeeeeeaes B 4 Figure B 3 50 Pin Extended Analog Input Connector Pin Assignments B 5 Tables Table 3 1 Available Input Configurations for the 6052E 6053E Devices 3 2 Table 3 2 Actual Range and Measurement Precision eee eee eeeeeeeseeeeees 3 3 Table 4 1 Pins Used by the PXI 6052E 6053E 0 0 eee eeeeseeseeeeeeeeeee
82. ignal connections you must first determine whether the signal sources are floating or ground referenced The following sections describe these two types of signals Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to your device analog input ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the device assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improper
83. ignal summary table 4 8 analog input See also analog input modes common questions C 3 to C 4 input polarity and range 3 3 to 3 4 actual range and measurement precision table 3 3 considerations for selecting input ranges 3 4 unipolar and bipolar 3 3 multichannel scanning considerations 3 4 to 3 5 signal connections 4 9 to 4 20 specifications A 1 to A 5 6052E 6053E accuracy information A 2 amplifier characteristics A 3 to A 4 dynamic characteristics A 4 to A 5 input characteristics A 1 to A 3 stability A 5 transfer characteristics A 3 types of signal sources 4 11 floating signal sources 4 11 ground referenced signal sources 4 11 analog input modes available input configurations table 3 2 common mode signal rejection considerations 4 20 differential connections 4 14 to 4 17 ground referenced signal sources 4 14 to 4 15 nonreferenced or floating signal sources 4 16 to 4 17 6052E 6053E User Manual Index exceeding input ranges caution 4 9 overview 3 2 PGIA figure 4 10 recommended input connections figure 4 13 single ended connection 4 18 to 4 20 floating signal sources RSE configuration 4 19 grounded signal sources NRSE configuration 4 19 to 4 20 analog output common questions C 3 to C 4 overview 3 5 polarity selection 3 5 reference selection 3 5 reglitch circuitry 3 6 signal connections 4 21 to 4 22 specifications A 5 to A 8 dynamic characteristics A 7 outpu
84. int of the signal should therefore be connected to the AISENSE pin Any potential difference between the 6052E 6053E ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by the amplifier If the input circuitry of the 6052E 6053E were referenced to ground in this situation as in the RSE input configuration this difference in ground potentials would appear as an error in the measured voltage National Instruments Corporation 4 19 6052E 6053E User Manual Chapter 4 Signal Connections Figure 4 8 shows how to connect a grounded signal source to a channel on the 6052E 6053E configured for NRSE mode Instrumentation Amplifier Ground Referenced v Signal s Source Input Multiplexers gt AISENSE ae n AIGND cm oy Noise and Ground v Potential Measured Voltage Selected Channel in NRSE Configuration I O Connector Figure 4 8 Single Ended Input Connections for Ground Referenced Signals Common Mode Signal Rejection Considerations Figures 4 5 and 4 8 show connections for signal sources that are already referenced to some ground point with respect to the 6052E 6053E In these cases the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with differential input connections the
85. is between V ref 2 and V ef 2 So the device has a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 10 V 5 V Polarity and range settings can be programmed on a per channel basis so that you can configure each input channel uniquely The software programmable gain on the 6052E 6053E devices increases the overall flexibility of each device by matching the input signal ranges to those that the ADC can accommodate Each device has gains of 0 5 1 2 5 10 20 50 and 100 and is suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 2 shows the overall input range and precision according to the input range configuration and gain used Table 3 2 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision 0 to 10 V 1 0 0 to 10 V 153 uV 2 0 0 to 5 V 76 3 uV 5 0 0 to 2 V 30 5 UV 10 0 Oto 1 V 15 3 uV 20 0 0 to 500 mV 7 63 uV 50 0 0 to 200 mV 3 05 uV 100 0 0 to 100 mV 1 53 uV 5 to 5 V 0 5 10 to 10 V 305 uV 1 0 5 to 5 V 153 uV 2 0 2 5 to 2 5 V 76 3 uV 5 0 l to 1 V 30 5 uV 10 0 500 to 500 mV 15 6 uV 20 0 250 to 250 mV 7 63 uV 50 0 100 to 100 mV 3 05 uV 100 0 50 to 50 mV 1 53 uV The value of 1 LSB of the 16 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 16 bit count Note See Appe
86. l start scan signal a measure of the amount of noise seen by an analog circuit or an ADC when the analog inputs are grounded terminal count the highest value of a counter gate hold time gate setup time gate pulse width output delay time 6052E 6053E User Manual Glossary THD thermocouple TRIG UI UISOURCE unipolar update Voc VI Vin 6052E 6053E User Manual total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage a temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function of the temperature trigger signal source clock period source pulse width transistor transistor logic update interval update interval counter clock signal a signal range that is always positive for example 0 to 10 V the output equivalent of a scan One or more analog or digital output samples Typically the number of output samples in an update is equal to the number of channels in the output group For example one pulse from the update clock produces one update which sends one new sample to every analog output channel in the group volts volts direct current virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a
87. lly control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin Be careful not to drive a PFI signal externally when it is configured as an output As an input you can individually configure each PFI signal for edge or level detection as well as for polarity selection You can use the polarity selection for any of the 13 timing signals but the edge or level detection National Instruments Corporation 4 25 6052E 6053E User Manual Chapter 4 Signal Connections will depend upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there can
88. ly measured this difference can appear as an error in the measurement The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal National Instruments Corporation 4 11 6052E 6053E User Manual Chapter 4 Signal Connections Input Configurations You can configure your device for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources 6052E 6053E User Manual 4 12 www ni com Chapter 4 Signal Connections Figure 4 4 summarizes the recommended input configuration for both types of signal sources Signal Source Type Floating Signal Source Not Connected to Building Ground Examples e Ungrounded Thermocouples e Signal conditioning with isolated outputs e Battery devices Differential DIFF See text for information on bias resistors Grounded Signal Source Examples e Plug in instruments with nonisolated outputs NOT RECOMMENDED Single Ended Ground Referenced RSE Single Ended Nonreferenced NRSE AIGND See text for information on bias resistors Ground loop losses Vg are added to measured signal Figure 4 4 Summary of Analog Input Connections National Instruments Corporation 4 13 6052E 6053E User Manual
89. m ratings of input or output signals on the 6052E 6053E device can damage the device and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 3 National Instruments is not liable for any damages resulting from such signal connections National Instruments Corporation 4 1 6052E 6053E User Manual Chapter 4 Signal Connections ACH8 34 68 ACHO ACH1 33 67 AIGND AIGND 32 66 ACH9 ACHi0 31 65 ACH2 ACH3 30 64 AIGND AIGND 29 63 ACH11 ACH4 28 62 AISENSE AIGND 27 61 ACH12 ACH13 26 60 ACH5 ACH6 25 59 AIGND AIGND 24 58 ACH14 ACH15 23 57 ACH7 DACOOUT 22 56 AIGND DAC1OUT 21 55 AOGND EXTREF 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 17 51 DIO5 DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIOS DGND 12 46 SCANCLK PFIO TRIG1 11 45 EXTSTROBE PFI1 TRIG2 10 44 DGND DGND 9 43 PFI2 CONVERT 5V 8 42 PFI3 GPCTR1_SOURCE DGND 7 41 PFI4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1_OUT PFI6 WFTRIG 5 39 DGND DGND 4 38 PFI7 STARTSCAN PFI9 GPCTRO_GATE 3 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 2 36 DGND FREQ_OUT 1 35 DGND Figure 4 1 1 0 Connector Pin Assignment for 6052E 6052E 6053E User Manual 4 2 www ni com Chapter 4 Signal Connections AIGND AIGND ACHO ACH8
90. ment time for your data acquisition and control application National Instruments Corporation 1 3 6052E 6053E User Manual Chapter 1 Introduction NI DAQ Driver Software 6052E 6053E User Manual The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with SCXI or accessory products except for the SCXI 1200 NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI self calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software
91. mentation for more information The DAQPad 6052E for 1394 is equipped with two LEDs to help you determine the state of your device e Power LED Power LED off no power is being provided to the device Either the power cord is unplugged or the power source is broken Power LED dim the device is receiving power but is not connected to an active 1394 port Power LED on the device is receiving power and is connected to an active 1394 port e Communications LED the COM LED blinks whenever the device sends or receives any commands or data This LED should blink once when you first plug in your device If you are transferring a lot of data this light should be on or blinking continuously Refer to your software documentation for configuration instructions 6052E 6053E User Manual 2 4 www ni com Hardware Overview This chapter presents an overview of the hardware functions on your 6052E 6053E device Figure 3 1 shows a block diagram for the 6052E 6053E devices Ther Voltage Calibration Buffer REF DACs 2 8 16 Bit Generic Mux Mode j Hine Selection Programmable Sampling ADC ices 8 Switches Gain AD FIFO Amplifier Converter Calibration Mux Configuration A Conia Memory g T a 2 Q A i Analog Je IRQ K O ad Trigger DMA rh A oO D Trigger Circuitry i
92. mes CompactPCI refers to the core specification defined by the PCI Industrial Computer Manufacturer s Group PICMG Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts National Instruments Corporation xi 6052E 6053E User Manual About This Manual NI DAQ PC PXI PCI E Series SCXI NI DAQ refers to the NI DAQ driver software for Macintosh or PC compatible computers unless otherwise noted Refers to all PC AT series computers with PCI bus unless otherwise noted Stands for PCI eXtensions for Instrumentation The PXI bus is an open specification for instrumentation specific features Refers to switchless and jumperless enhanced MIO devices that use the DAQ STC for timing SCXI stands for Signal Conditioning eXtensions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National Instruments plug in DAQ devices Related Documentation 6052E 6053E User Manual The f
93. ndix A Specifications for absolute maximum ratings National Instruments Corporation 3 3 6052E 6053E User Manual Chapter 3 Hardware Overview Considerations for Selecting Input Ranges The input polarity and range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but can result in the input signal going out of range For best results match the input range as closely as possible to the expected range of the input signal For example if you are certain the input signal is not below 0 V unipolar input polarity is best However if the signal is negative you get inaccurate readings if you use unipolar input polarity Multichannel Scanning Considerations 6052E 6053E User Manual The 6052E 6053E can scan multiple channels at the same maximum rate as its single channel rate however pay careful attention to the settling time The settling time is independent of the selected gain even at the maximum sampling rate The settling time for the very high speed devices is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a complete listing of settling times When scanning among chann
94. nge device interconnections If you want to develop your own cable however the following guidelines can be useful e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source e You should route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals The following list gives recommended part numbers for connectors that mate to the I O connector on your 6052E 6053E device Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments part number 776832 01 e Honda 68 position solder cup female connector part number PCS E68FS e Honda backshell part number PCS E68LKPA National Instruments Corporation B 1 6052E 6053E User Manual Appendix B Custom Cabling and Optional Connectors Optional Connectors Refer to Figure 4 1 I O Connector Pin Assignment for 6052E 6053E Figure 4 1 shows the pin assignments for the 68 pin connector This connector is available when you use the SH6868EP or R6868 cable assemblies with the 6052E device This connector is also one of two 68 pin connectors that is available when you use the SH
95. nnections 4 40 T O signal summary table 4 9 6052E 6053E User Manual GPCTRO_SOURCE signal 4 38 GPCTRO_UP_DOWN signal 4 40 GPCTR1_GATE signal 4 41 to 4 42 GPCTR1_OUT signal description table 4 6 general purpose timing signal connections 4 42 T O signal summary table 4 8 GPCTR1_SOURCE signal 4 40 to 4 41 GPCTR1_UP_DOWN signal 4 42 to 4 44 ground referenced signal sources description 4 11 differential connections 4 14 to 4 15 single ended connections NRSE configuration 4 19 to 4 20 H hardware configuration 2 3 to 2 4 installation 2 1 to 2 3 hardware overview analog input 3 2 to 3 5 input mode 3 2 input polarity and range 3 3 to 3 4 analog output 3 5 to 3 6 block diagram 3 1 digital I O 3 9 timing signal routing 3 9 to 3 13 device and RTSI clocks 3 11 programmable function inputs 3 11 RTSI triggers 3 11 to 3 13 input modes See analog input modes input polarity and range 3 3 to 3 4 actual range and measurement precision table 3 3 considerations for selecting input ranges 3 4 www ni com exceeding input ranges caution 4 9 unipolar and bipolar 3 3 installation common questions C 2 to C 3 hardware 2 1 to 2 3 software 2 1 unpacking 6025E devices 2 1 I O connectors 4 1 to 4 9 exceeding maximum ratings caution 4 1 optional connectors B 2 to B 4 50 pin connector pin assignments figure B 4 50 pin extended analog input connector pin assignments figure B 5 68 pin co
96. nnector pin assignments figure B 3 pin assignments figure 6052E devices 4 2 6053E devices 4 3 pins used by PXI 6052 6053E devices table 4 4 signal descriptions table 4 5 to 4 7 signal summary table 4 8 to 4 9 L LabVIEW application software 1 3 LEDs Communication LED 2 4 Power LED 2 4 manual See documentation Measurement Studio software 1 3 multichannel scanning considerations 3 4 to 3 5 National Instruments Corporation l 5 Index NI Developer Zone D 1 NI DAQ driver software 1 4 to 1 5 noise environmental 4 44 to 4 45 NRSE nonreferenced single ended mode AISENSE signal 4 10 description table 3 2 differential connections 4 16 to 4 17 recommended configuration figure 4 13 single ended connections for ground referenced signal sources 4 19 to 4 20 0 optional equipment 1 5 P PCI 6052E 6053E See 6052E 6053E devices PFIO TRIG1 signal description table 4 6 false triggering due to crosstalk note 3 6 T O signal summary table 4 8 PFI1 TRIG2 signal description table 4 6 T O signal summary table 4 8 PFI2 CONVERT signal description table 4 6 T O signal summary table 4 8 PFI3 GPCTR1_SOURCE signal description table 4 6 I O signal summary table 4 8 PFI4 GPCTR1_GATE signal description table 4 6 T O signal summary table 4 8 PFIS UPDATE signal description table 4 6 T O signal summary table 4 8 6052E 6053E User Manual
97. nput signal source With the different configurations you can use the PGIA in different ways Figure 4 3 shows a diagram of the PGIA Instrumentation Amplifier ins OF Vm Measured Vin C Voltage Vin Vins Vin I Gain Figure 4 3 PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to your device Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the device The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the ground for the device Your device A D converter ADC measures this output voltage when it performs A D conversions You must reference all signals to ground either at the source device or at the device If you have a floating source you should reference the signal to ground by using the RSE input mode or the DIFF input configuration with 4 10 www ni com Chapter 4 Signal Connections bias resistors see the Differential Connections for Nonreferenced or Floating Signal Sources section in this chapter If you have a grounded source you should not reference the signal to AIGND You can avoid this reference by using DIFF or NRSE input configurations Types of Signal Sources When configuring the input channels and making s
98. nst defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this d
99. ocument without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent a
100. of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence In pretriggered mode the TRIG1 signal initiates the data acquisition The scan counter indicates the minimum number of scans before TRIG2 can be recognized After the scan counter decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The device ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero After the selected edge of TRIG is received the device will acquire a fixed number of scans and the acquisition will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup National Instruments Corporation 4 29 6052E 6053E User Manual Chapter 4 Signal Connections 6052E 6053E User Manual Figures 4 18 and 4 19 show the input and output timing requirements
101. ollowing documents contain information you can find helpful e DAQ STC Technical Reference Manual e National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals e PCI Local Bus Specification Revision 2 0 e PICMG CompactPCI 2 0 R2 1 e PXI Specification Revision 1 0 xii www ni com Introduction This chapter describes the 6052E 6053E devices lists what you need to get started describes the optional software and optional equipment and explains how to unpack your device About the 6052E 6053E Devices Thank you for buying a National Instruments 6052E 6053E device The PCI 6052E 6053E PXI 6052E 6053E and DAQPad 6052E are multifunction analog digital and timing I O devices for PCI PXI and 1394 computers Your device features two 16 bit ADCs with 16 analog inputs for 6052E or 64 analog inputs for 6053E 16 bit DACs with voltage outputs eight lines of TTL compatible digital I O and two 24 bit counter timers for timing I O Because your device has no DIP switches jumpers or potentiometers it is easily software configured and calibrated The PCI 6052E 6053E and PXI 6052E 6053E are completely switchless and jumperless data acquisition DAQ devices This feature is made possible by the National Instruments MITE bus interface chip that connects the device to the PCI PXI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all so
102. on your 6052E 6053E device DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO 6 and 7 can control the up down signal of general purpose counters 0 and 1 respectively 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion in the scanning modes when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal National Instruments Corporation 4 5 6052E 6053E User Manual Chapter 4 Signal Connections Table 4 2 1 0 Connector Signal Descriptions Continued Signal Name Reference Direction Description EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIG1 DGND Input PFI0 Trigger 1 As an input this is either one of the Programmable Function Inputs PFIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section in this chapter The hardware analog trigger is explained in the Analog Trigger section in Chapter 3 Hardware Overview Output As an output this is the TRIG1 signal In posttrigger data acquisition sequences a low to high transition indicates the initiation of the acquisition sequence In pretrigge
103. oot of 5 V 5 VDC source signal National Instruments Corporation G 1 6052E 6053E User Manual Glossary A A AC ACH A D ADC Al AIGATE AIGND AISENSE ANSI AO AOGND ASIC BIOS bipolar 6052E 6053E User Manual amperes alternating current analog input channel signal analog to digital analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number analog input analog input gate signal analog ground signal analog sense signal American National Standards Institute analog output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer basic input output system BIOS functions are the fundamental level of any PC or compatible computer BIOS functions embody the basic operations needed for successful use of the computer s hardware resources a signal range that includes both positive and negative values for example 5 V to 5 V G 2 www ni com C C CalDAC CH cm CMOS CMRR common mode noise CONVERT counter timer CTR D D A DAC DACOOUT DAC1OUT National Instruments Corporation G 3 Glossary Celsius calibration DAC channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single
104. ound output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 Mbytes s programmable function input PFI0 trigger 1 PFI1 trigger 2 PFI2 convert PFI3 general purpose counter source PFI4 general purpose counter gate PFI5 update National Instruments Corporation G 7 6052E 6053E User Manual Glossary PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_ SOURCE PFI9 GPCTRO_GATE PGIA port ppm pu R RAM reglitch rms RSE RTD RTSI bus 6052E 6053E User Manual PFI6 waveform trigger PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate programmable gain instrumentation amplifier 1 a communications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output parts per million pullup random access memory circuitry used on analog outputs to generate uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum root mean square the square root of the average
105. ounter 0 This is true even if the gate is being externally generated by another PFI This output is set to tri state at startup Figure 4 31 shows the timing requirements for the GPCTRO_GATE signal Rising Edge Polarity Falling Edge Polarity ty 10 ns minimum Figure 4 31 GPCTRO_GATE Signal Timing in Edge Detection Mode National Instruments Corporation 4 39 6052E 6053E User Manual Chapter 4 Signal Connections GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 32 shows the timing of the GPCTRO_OUT signal GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle Output on TC TC i 6052E 6053E User Manual Figure 4 32 GPCTRO_OUT Signal Timing GPCTRO_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for
106. ounter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some of your applications drawn using the CTR VIs will still run However there are many differences in the counters between the E Series and other devices the counter numbers are different timebase selections are different and the DAQ STC counters are 24 bit counters unlike the 16 bit counters on device without the DAQ STC If you are using the NI DAQ language interface or LabWindows CVI the answer is no the counter timer applications that you wrote previously will not work with the DAQ STC You must use the GPCTR functions ICTR and CTR functions will not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my E Series device but I do not see the counter timer output on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated National Instruments Corporation C 5 6052E 6053E User Manual Appendix C Common Questions What are the PFIs and how do I configure these lines PFIs are
107. ower on your 6052E 6053E for the recommended warmup time in a stable temperature environment before calibrating the device Refer to Appendix A Specifications to determine the warmup time The device should be calibrated at the temperature in which it will operate National Instruments Corporation 5 3 6052E 6053E User Manual Specifications Analog Input This appendix lists the specifications of the 6052E 6053E devices These specifications are typical at 25 C unless otherwise noted Input Characteristics Number of channels PCI 6052E ossiani PCI 6053E oo eee Type of ADC ee Resolution ccccccccceeeeeees Max sampling rate Input signal ranges 16 single ended or 8 differential software selectable 64 single ended or 32 differential software selectable Successive approximation 16 bits 1 in 65 536 333 kS s guaranteed Device Gain Device Range Software Selectable Software Selectable Bipolar Unipolar 0 5 10 V 1 5 V Oto 10 V 2 2 5 V O0to5V 5 1 V 0to2V 10 500 mV Otol V 20 250 mV 0 to 500 mV 50 100 mV 0 to 200 mV 100 50 mV 0 to 100 mV National Instruments Corporation A 1 6052E 6053E User Manual Appendix A Specifications 6052E 6053E Accuracy Information Absolute Accuracy Relative Accuracy Noise Temp Nominal
108. ppm of reading max 22 000 ppm of reading max 200 ppm of reading max 100 GQ in parallel with 100 pF 820 Q min 820 Q min 200 pA 6052E 6053E User Manual Appendix A Specifications 6052E 6053E User Manual Input offset current 0 eee eeeeeeeeeeeees CMRR DC to 60 Hz Gain 0 5 voececccccccccccccccccccceeeeesessseees Dynamic Characteristics Bandwidth Small signal 3 dB eee Large signal 1 THD Dynamic range Settling time for full scale step 1 2 SB wasoiestngeisinnial aes 100 pA 92 dB 97 dB 101 dB 104 dB 105 dB ites 87 dB 10 V input gain 0 5 to 5 83 dB gain 10 seats 5 us max gain 0 5 to 10 8 us max gain 20 to 50 10 us max gain 100 esis 10 us max gain 0 5 to 5 15 us max gain 10 to 100 eats 20 us typical System noise including quantization noise Gain Noise 0 5 to 5 0 95 LSB rms 10 1 1 LSB rms 20 1 3 LSB rms 50 2 3 LSB rms 100 4 2 LSB rms A 4 www ni com Analog Output Appendix A Specifications Crosstalk DC to 100 kHz Adjacent channels eee 75 dB Other channels cccccccecesseeeeee lt 90 dB Stability Recommended warm up time PCI PXI 6052E 6053E eee 15 minutes Offset temperature coefficient Prepainiaiscnc ate bash anes 4 uV C Bipolar postgain eee eee 120 uV C Unipolar postgain eee 30 uV C Gain temperature coefficient 0 0
109. put from the PFIO TRIG1 pin on the I O connector or a postgain signal from the output of the PGIA as shown in Figure 3 2 The trigger level range for the direct analog channel is in 4 9 mV steps The range for the post PGIA trigger selection is the full scale range of the selected channel The resolution is that range divided by 4 096 3 Note The PFIO TRIG1 pin is an analog input when configured as an analog trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 1 kQ source impedance if you plan to enable this input via software 6052E 6053E User Manual 3 6 www ni com Chapter 3 Hardware Overview Analog Bic Input x PGIA ADC Channels ESN eo Analog gt Mux Trigger DAQ STC PFIO TRIG1 Circuit Figure 3 2 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 3 through 3 7 You can set lowValue and highValue independently in software In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue HighValue is unused lowValue Trigger OT LC TLL Figure 3 3 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated
110. puts the signal path nearly in balance so that about the same amount of noise couples onto both connections yielding better rejection of electrostatically coupled noise Also this configuration does not load down the source other than the very high input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 6 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 KQ and produce a 1 gain error Both inputs of the PGIA require a DC path to ground in order for the PGIA to work If the source is AC coupled capacitively coupled the PGIA needs a resistor between the positive input and AIGND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 KQ to 1 MQ In this case you can tie the negative input directly to AIGND If the source has high output impedance you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs you should be aware that th
111. r applications a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input PFI1 Trigger 2 As an input this is one of the PFIs Output As an output this is the TRIG2 signal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications PFI2 CONVERT DGND Input PFI2 Convert As an input this is one of the PFIs Output As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source As an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter output PFI5 UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output primary group is being updated 6052E 6053E User Manual 4 6 www ni com Chapter 4 S
112. ration eee 0 5 LSB typ 1 0 LSB max Before calibration ccccceeeeees 3 LSB max MOonotonicity 0 eee eee eee sseeseeeeeneees 16 bits guaranteed after calibration Offset error After calibration eee eee 305 uV max Before calibration ccccceeeees 17 mV max Gain error relative to internal reference After calibration eee 30 5 ppm of output max Before calibration eee 9 000 ppm of output max Gain error relative to external reference 0 to 0 5 of output 6052E 6053E User Manual max not adjustable A 6 www ni com Appendix A Specifications Voltage Output Rangesi tice atent E os OE EA 10 V 0 to 10 V EXTREF 0 to EXTREF software selectable Output coupling eee DC Output impedance 0 0 eects 0 1 Q max Current rive ceaun 5 mA max Protection sisi sheet ee Stes ee Short circuit to ground Power on state cccecessceeesseeeesteeeeeeees 0 020 V max External reference input RAN 86 sists rennen aea eE 11 V Overvoltage protection 0 25 V powered on 15 V powered off Input impedance eee 10 KQ Bandwidth 3 dB 3 kHz IEW Fale parr nS 0 3 V us Dynamic Characteristics Settling time for full scale step 3 5 us to 1 0 LSB accuracy Settling time for half scale step 3 0 us to 1 0 LSB accuracy Slew rat iiine iisi osaa ii 15 V us NOIS Eissii sta setdeesdestisieegiepssigbes bes 60 uVrms
113. re the circuitry to scan 12 channels four differentially configured channels and eight single ended channels Table 3 1 describes the three input configurations Table 3 1 Available Input Configurations for the 6052E 6053E Devices Configuration Description DIFF A channel configured in DIFF mode uses two analog input lines One line connects to the positive input of the device programmable gain instrumentation amplifier PGIA and the other connects to the negative input of the PGIA RSE A channel configured in RSE mode uses one analog input line which connects to the positive input of the PGIA The negative input of the PGIA is internally tied to analog input ground AIGND NRSE A channel configured in NRSE mode uses one analog input line which connects to the positive input of the PGIA The negative input of the PGIA connects to analog input sense AISENSE For more information about the three types of input configuration refer to the Analog Input Signal Connections section in Chapter 4 Signal Connections which contains diagrams showing the signal paths for the three configurations 3 2 www ni com Chapter 3 Hardware Overview Input Polarity and Input Range The 6052E 6053E devices have two input polarities unipolar and bipolar Unipolar input means that the input voltage range is between 0 and Vier where Vef is a positive reference voltage Bipolar input means that the input voltage range
114. referenced Signals 4 16 Single Ended Input Connections for Nonreferenced or Floating Sigmals ccscc icsdoc cesstkeltaissniestved seivdenestuesvinedeaeieonnsesesseye 4 19 Single Ended Input Connections for Ground Referenced Signals 4 20 Analog Output Connections eeceseeseeeseeneceseeseeneetseseeeeseeeees 4 22 Digital VO Connections ccsccssscssessessgesseusessesepttvesiaseptesesessezeeystdasecteseede 4 23 Timing I O Connections eee ec eeeeeeseeseeeseeseeeseceeeeseseeeaesseeeaseaeens 4 25 Typical Posttriggered Acquisition Lele eee eeeeeseeeeeeeeeeeeaeeeenaeens 4 26 Typical Pretriggered Acquisition eceseeeseceseeeneeeeneceeeeeeeseaeeeteeeeas 4 27 SCANCLE Siptial Timing anii ae e cosets hese 4 27 EXTSTROBE Signal Timing 00 eee eeeeseeneceeeeseeeseceeeeseeeeenaees 4 28 TRIGI Input Signal Timing eee eeseeneceseeseeeeeseeeeeeteeeseens 4 28 TRIG1 Output Signal Timing 0 eneeeeereeeseteeeneeeeeeaees 4 29 TRIG2 Input Signal Timing ee eeeeeeeneceeeeseeeeetseseeeeseeeees 4 30 TRIG2 Output Signal Timing 00 cece ere ceeeeeeeeeeeeeeeeeeeeeaees 4 30 STARTSCAN Input Signal Timing ee eeeeeeceeeeneeeeeeseeeees 4 31 STARTSCAN Output Signal Timing 000 00 eee eee eeeeereeeeeeees 4 31 CONVERT Input Signal Timing oo eee cee eeeeeeeseeeseeneeeeeeneenes 4 32 CONVERT Output Signal Timing eee cece cereeeeeeeeseeneeees 4 33 SISOURCE Signal Timing oo eee aea a p SE E 4 34 WFTRIG Input S
115. rity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your device is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Corporation 5 1 6052E 6053E User Manual Chapter 5 Calibration This method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time
116. rnally supplied reference within 11 V You do not need to configure both channels for the same range Selecting a bipolar range for a particular DAC means that any data written to that DAC is interpreted as two s complement format In two s complement mode data values written to the analog output channel can be either positive or negative If you select unipolar range data is interpreted in straight binary format In straight binary mode data values written to the analog output channel range must be positive National Instruments Corporation 3 5 6052E 6053E User Manual Chapter 3 Hardware Overview Analog Output Reglitch Analog Trigger In normal operation a DAC output glitches whenever it is updated with a new value The glitch energy differs from code to code and appears as distortion in the frequency spectrum Each analog output contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence the 6052E 6053E devices also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog in
117. s and answers C 1 to C 6 analog input and output C 3 to C 4 general information C 1 installation and configuration C 2 to C 3 timing and digital I O C 4 to C 6 R reference selection analog output 3 5 referenced single ended input RSE See RSE referenced single ended mode reglitch analog output 3 6 requirements for getting started 1 2 to 1 3 RSE referenced single ended mode description table 3 2 recommended configuration figure 4 13 single ended connections for floating signal sources 4 19 RTSI clocks 3 11 RTSI triggers overview 3 11 signal connections PCI figure 3 12 PXI figure 3 13 specifications A 10 www ni com S sampling rate C 1 SCANCLK signal DAQ timing connections 4 27 description table 4 5 T O signal summary table 4 8 scanning multichannel 3 4 to 3 5 settling time in multichannel scanning 3 4 to 3 5 signal connections analog input 4 9 to 4 20 common mode signal rejection considerations 4 20 differential connection considerations 4 14 to 4 17 input configurations 4 12 to 4 20 single ended connection considerations 4 18 to 4 20 summary of input connections figure 4 13 types of signal sources 4 11 analog output 4 21 to 4 22 digital I O 4 22 to 4 23 field wiring considerations 4 44 to 4 45 I O connectors 4 1 to 4 9 exceeding maximum ratings caution 4 1 T O connector signal descriptions table 4 5 to 4 7 T O signal summary table 4 8 to 4 9 pin as
118. signments figures 4 2 to 4 3 T O connectors optional B 2 to B 4 50 pin connector pin assignments figure B 4 50 pin extended analog input connector pin assignments figure B 5 68 pin connector pin assignments figure B 3 power connections 4 24 National Instruments Corporation l 7 Index timing connections 4 24 to 4 25 DAQ timing connections 4 26 to 4 34 general purpose timing signal connections 4 38 to 4 44 programmable function input connections 4 25 to 4 26 waveform generation timing connections 4 34 to 4 37 signal sources floating signal sources 4 11 ground referenced signal sources 4 11 single ended connections 4 18 to 4 20 floating signal sources RSE configuration 4 19 grounded signal sources NRSE configuration 4 19 to 4 20 when to use 4 18 SISOURCE signal 4 34 software installation 2 1 software programming choices National Instruments application software 1 3 NI DAQ driver software 1 4 to 1 5 specifications analog input A 1 to A 5 6052E 6053E accuracy information A 2 amplifier characteristics A 3 to A 4 dynamic characteristics A 4 to A 5 input characteristics A 1 to A 3 stability A 5 transfer characteristics A 3 analog output A 5 to A 8 dynamic characteristics A 7 output characteristics A 5 to A 6 PXI 6052E 6053E accuracy information A 6 stability A 7 to A 8 transfer characteristics A 6 voltage output A 7 6052E 6053E User Manual Index bus interface A 10 di
119. sure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry least significant bit meters megabytes of memory multifunction I O MXI Interface to Everything a custom ASIC designed by National Instruments that implements the PCI bus interface The MITE supports bus mastering for high speed data transfers over the PCI bus most significant bit multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel G 6 www ni com NC NI DAQ noise NRSE OUT PCI PFI PFIO TRIGI PFI1 TRIG2 PFI2 CONVERT PFI3 GPCTRI1_ SOURCE PFI4 GPCTR1_GATE PFIS UPDATE Glossary normally closed or not connected National Instruments driver software for DAQ hardware an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive nonreferenced single ended mode all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system gr
120. t any PFI pin as the source for TRIGI and configure the polarity selection for either rising or falling edge The selected edge of the TRIGI signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions See Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIG1 signal reflects the action that initiates a DAQ sequence This is true even if the acquisition is being externally triggered by another PFI The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to tri state at startup Figures 4 16 and 4 17 show the input and output timing requirements for the TRIG1 signal Rising Edge Polarity m o Falling Edge Polarity tw 10 ns minimum Figure 4 16 TRIG1 Input Signal Timing 4 28 www ni com Chapter 4 Signal Connections 1 I I i i lt gt 1 I 2 I i tw 50 100 ns i 1 Figure 4 17 TRIG1 Output Signal Timing The device also uses the TRIG1 signal to initiate pretriggered DAQ operations In most pretriggered applications the TRIG1 signal is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 13 for the relationship
121. t characteristics A 5 to A 6 PXI 6052E 6053E accuracy information A 6 stability A 7 to A 8 transfer characteristics A 6 voltage output A 7 analog trigger 3 6 to 3 9 above high level analog triggering mode figure 3 8 below low level analog triggering mode figure 3 7 block diagram 3 7 crosstalk on PFIO TRIG1 pin note 3 6 high hysteresis analog triggering mode figure 3 8 inside region analog triggering mode figure 3 8 low hysteresis analog triggering mode figure 3 9 specifications A 9 to A 10 6052E 6053E User Manual l 2 AOGND signal analog output signal connections 4 21 to 4 22 description table 4 5 T O signal summary table 4 8 B bipolar input 3 3 bipolar output 3 5 block diagram 3 1 bus interface specifications A 10 C cables See also I O connectors custom cabling B 1 field wiring considerations 4 44 to 4 45 optional equipment 1 5 calibration 5 1 to 5 3 adjusting gain error 5 3 external calibration 5 2 loading calibration constants 5 1 to 5 2 self calibration 5 2 charge injection 3 4 clocks device and RTSI 3 11 commonly asked questions See questions and answers common mode signal rejection considerations 4 20 Communication LED 2 4 CompactPCI using with PXI 1 2 configuration common questions C 2 to C 3 hardware configuration 2 3 to 2 4 connectors See I O connectors CONVERT signal DAQ timing connections 4 32 to 4 33 signal routing figure
122. tes the CONVERT signal unless you select some external source The counter is started by the STARTSCAN signal and continues to count down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence can be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can externally input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN National Instruments Corporation 4 33 6052E 6053E User Manual Chapter 4 Signal Connections The AIGATE signal can neither stop a scan in progress nor continue a previously gated off scan in other words once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and
123. three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamlessly changing the sampling rate are possible What does sampling rate mean to me It means that this is the fastest you can acquire data on your device and still achieve accurate results For example the PCI 6052E 6053E has a sampling rate of 333 kS s This sampling rate is aggregate one channel at 333 kS s or two channels at 166 5 kS s per channel illustrates the relationship Notice however that the PCI 6052E 6053E has settling times that vary with gain and accuracy See Appendix A Specifications for exact specifications What type of 5 V protection do the PCI 6052E 6053E PXI 6052E 6053E and DAQPad 6052E have The PCI 6052E 6053E PXI 6052E 6053E and DAQPad 6052E for 1394 have 5 V lines equipped with a self resetting 1 A fuse National Instruments Corporation C 1 6052E 6053E User Manual Appendix C Common Questions Installation and Configuration 6052E 6053E User Manual How do you set the base address for a PCI 6052E 6053E or PXI 6052E 6053E The base address
124. to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS5 UPDATE pin Device and RTSI Clocks Many functions performed by the 6052E 6053E devices require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector The 6052E 6053E device can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable The PCI 6052E 6053E have separate connectors for the RTSI bus The PXI 6052E 6053E uses signals on the PXI backplane for RTSI Clock The RTSI Clock signal uses the PXI trigger lt 7 gt line for this connection RTSI Triggers The RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for any 6052E 60
125. to tri state at startup Figures 4 20 and 4 21 show the input and output timing requirements for the STARTSCAN signal Rising Edge Polarity _ __ Falling Edge _ m Polarity tw 10 ns minimum Figure 4 20 STARTSCAN Input Signal Timing ty 50 100 ns a Start of Scan tof 10 ns minimum b Scan in Progress Two Conversions per Scan Figure 4 21 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the device generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when the onboard sample interval counter reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one scan period National Instruments Corporation 4 31 6052E 6053E User Manual Chapter 4 Signal Connections 6052E 6053E User Manual A counter on your device internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIGI signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence can be gated by either the hardware AIGATE signal or software command register gate C
126. upplies its own reference ground point The device should not supply one In single ended configurations more electrostatic and magnetic noise couples into the signal connections than in differential configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors 6052E 6053E User Manual 4 18 www ni com Chapter 4 Signal Connections Single Ended Connections for Floating Signal Sources RSE Configuration Figure 4 7 shows how to connect a floating signal source to a channel on the 6052E 6053E configured for RSE mode Floating Signal Vs Source 5 ACH o oo o oie 9 so Instrumentation Amplifier A so Input Multiplexers E P o e AISENSE a yer AIGND 1 O Connector Selected Channel in RSE Configuration Figure 4 7 Single Ended Input Connections for Nonreferenced or Floating Signals Single Ended Connections for Grounded Signal Sources NRSE Configuration To measure a grounded signal source with a single ended configuration you must configure your device in the NRSE input configuration The signal is then connected to the positive input of the PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground po
127. ur DAQPad device and any accessories with NI DAQ Your DAQPad 6052E for 1394 is now installed You are now ready to configure your hardware and software Configuration PCI 6052E 6053E PXI 6052E 6053E The PCI 6052E 6053E and PXI 6052E 6053E are completely software configurable You must perform two types of configuration on the PCI 6052E 6053E and PXI 6052E 6053E bus related and data acquisition related configuration The PCI 6052E 6053E and PXI 6052E 6053E are fully compatible with the industry standard PCI Local Bus Specification Revision 2 0 and PXI Specification Revision 1 0 This allows the PCI PXI system to automatically perform all bus related configurations and requires no user interaction Bus related configuration includes setting the device base memory address and interrupt channel You can modify data acquisition related configuration settings such as analog input polarity and range analog input mode and others through application level software such as NI DAQ ComponentWorks LabVIEW LabWindows CVI and VirtualBench National Instruments Corporation 2 3 6052E 6053E User Manual Chapter 2 Installation and Configuration DAQPad 6052E for 1394 The DAQPad 6052E for 1394 is a completely software configurable hot Plug and Play instrument The Plug and Play services query the instrument and allocate the required resources The operating system enables the instrument for operation Refer to your software docu
128. ut analog output and general purpose counter timer sections For example the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold The analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold Digital 1 0 The 6052E 6053E devices contain eight lines of digital I O for general purpose use You can individually software configure each line for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines National Instruments Corporation 3 9 6052E 6053E User Manual Chapter 3 Hardware Overview Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other devices or external circuitry Your device uses the RTSI bus to interconnect timing signals between devices and the Programmable Function Input PFI pins on the I O connector to connect the device to external circuitry These connections are designed to enable your device to both control and be controlled by other devices and circuits There are a total of 13 timing signals internal to t
129. when the signal value is greater than highValue LowValue is unused National Instruments Corporation 3 7 6052E 6053E User Manual Chapter 3 Hardware Overview highValue Trigger Figure 3 4 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue highValue lowValue Trigger l j l Figure 3 5 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue highValue oe wos onan dod ieee cee 2s ENE ONE lowValue 2 4 ssoccecuc nee ec feo ken fone Se eee Trigger Figure 3 6 High Hysteresis Analog Triggering Mode 6052E 6053E User Manual 3 8 www ni com Chapter 3 Hardware Overview In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue Trigger Ee Figure 3 7 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the analog inp

DAQ 6052E/6053E User Manual, NI 2000

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