Home

eZ80F92 Development Kit User Manual

1. 64 TiLoe GND 9VDC VDD gt gt 9vDC cta U23 KN F1 LM7805C T0220 0 5A U22 q 1 iN cu alo g v 27 io RXE160 9 24 Ss 6 ci m c1 v _ 2 M e HEADER 5 1 J13 D6 N C2 0 1 C16 c17 A 21 55 0 1uF Ou VES S26 1 1 14 9 TD RESET P PD mp HIN Tour PWR JACK G23 E 0 RESET ND 13 10 0 4 22uF T2IN T2OUT SW4 11 RTSO_ PD2 refl T3IN T3OUT RTSO CON DIS 7 FORCEOFF 24 un vour H2 VDP yop 4 GND YDD KAA 23 FORCEON INVALID 21 Po 10K 20 aure 1 LT1086 3 3 T0220 L 19 R1ouT RN LZ s Lo 18 R20UT Ran ND RTSO ire c apa AE p6_ IS PD3_CTS0 R3OUT R3IN CTS0 LTO 91 16 Z Pap lt CONSOLE GREEN PD1 RXDO R40UT RAIN o dig Ze 3 OK EN Ran LB DB9 Female 2 gt GND 2 gt gt DIS_0 o MAX3245CAI RS485_1_EN R17 10K c21 7 VDD U26 m PD1 RXDO Or wH vec 0 1 2d RE a bz us R23 U24 PD2 RTSO S 5p ALS d Ca H V s PDO a Zum cnp LS Bi c1 v i DS1487 i c2 2 3 RTA GND TXDi PCO TXD1 Hmm our CH U27 5 4g DIRI a PC4 DTRT T2IN T20UT DTR1 POL no vec H Sat PC2 RTSD gt gt l2 _ T3IN T30UT RTS 2d RE B pz con8 VDD MOD_DIS PI FORCEOFF EES 3 DE AH SC nos
2. Pin Symbol Description 1 MRESET Reset active Low 50 100ms Closure to GND for reset 3 GND Ground 6 D1 DCD indicator can drive an LED anode without additional circuitry 7 D2 RxD indicator can drive an LED anode without additional circuitry 8 D3 DTR indicator can drive an LED anode without additional circuitry 9 D4 TxD indicator can drive an LED anode without additional circuitry Table 12 Connector J1 Pin Symbol Description 2 MOD DIS Modem disable active Low 4 Vec 5 VDC or 3 3 VDC input 24 GND Ground 25 PC4_DTR1 DTR interface TTL levels 26 PC6 DCD1 DCD interface TTL levels 27 PC3 CTS1 CTS interface TTL levels 28 PC5 DSR1 DSR interface TTL levels 29 PC7 RM Ring Indicator interface TTL levels 30 PCO TXD1 TxD interface TTL levels 31 PC1_RXD1 RxD interface TTL levels 32 PC2_RTS1 RTS interface TTL levels UMO13907 1003 PRELIMINARY Operational Description 30 eZ80F92 Development Kit User Manual 110 Components P4 T1 C3 C4 and U11 provide the phone line interface to the modem On the eZ809 Development Platform LEDs D1 D2 D3 and D4 function as status indicators for this optional modem The phone line connection for the modem is for the United States only Connecting the modem outside of the U S requires modification The tested modem for this eZ80F92 Development Kit is a MultiTech Sys tems formerly Conexant socket modem par
3. User Manual rer Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Pin Symbol Signal Direction Active Level eZ80F92 Signal 1 A6 Bidirectional Yes 2 AO Bidirectional Yes 3 A10 Bidirectional Yes 4 A3 Bidirectional Yes 5 GND 6 Von 7 A8 Bidirectional Yes 8 AT Bidirectional Yes 9 A13 Bidirectional Yes 10 A9 Bidirectional Yes 11 A15 Bidirectional Yes 12 A14 Bidirectional Yes 13 A18 Bidirectional Yes 14 A16 Bidirectional Yes 15 A19 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F92 device 3 External capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ809 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 13 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued 1
4. 47 IrDA Hardware Connections 50 9VDC Universal Power Supply Components 53 Inserting a New Plug Configuration 54 eZ809 Development Platform Schematic Diagram Tl 0E l ose A 61 eZ80 Development Platform Schematic Diagram HL OF CC EE bee he en 62 eZ80 Development Platform Schematic Diagram HOLD cir a Ceri oe bee Ene ERR Re ke eb ea 63 eZ809 Development Platform Schematic Diagram A Sie ed adar adda adaaivdads sax 64 PRELIMINARY List of Figures vii eZ80F92 Development Kit User Manual VIII 110 List of Figures Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 eZ809 Development Platform Schematic Diagram 5 of RS AN5Cable mo 65 Schematic Diagram 1 of 9 Top Level 66 Schematic Diagram 2 of 9 100 Pin QFP eZ80F92 lou EET 67 Schematic Diagram 3 of 9 36 Pin SRAM Device 68 Schematic Diagram 4 of 9 NOR Flash Device 69 Schematic Diagram 5 of 9 eZ80F92 Flash Module 70 Schematic Diagram 6 of 9 IrDA Reset 71 Schematic Diagram 7 of 9 Headers 72 Schematic Diagram 8 of 9 Power Supply 73 Schematic Diagram 9 of 9 Control Logic 74 PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table
5. User Triggers Two general purpose trigger output pins are provided on the eZ809 Development Platform Labeled J21 Trig2 and J22 Trig1 these pins allow the user a way to trigger external equipment to aid in the debug of the system See Figure 8 for trigger pin details J21 J22 E Ground 5 D Z Trigger output Trig2 Toi Figure 8 Trigger Pins J21 and J22 Bits 6 and 7 in Table 9 are the control bits for the user triggers If either bit is a 1 the corresponding Trigl and Trig2 signals are driven High If either bit is O the corresponding Trig1 and Trig2 signals are driven Low UMO13907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 28 110 Embedded Modem Socket Interface The eZ80 Development Platform features a socket for an optional 56K modem a modem is not included in the kit Connectors J1 J5 and J9 provide connection capability The modem socket interface provided by these three connectors is shown in Figure 9 Tables 10 through 12 identify the pins for each connector The embedded modem utilizes UARTI which is available via the Port C pins Figure 9 Embedded Modem Socket Interface J1 J5 and J9 Table 10 Connector J5 Pin Symbol Description 1 M TIP Telephone Line Interface TIP 2 M RING Telephone Line Interface RING eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 29 Table 11 Connector J9
6. located in the address range B00000h B7FFFFh addressing UMO13907 1003 PRELIMINARY Operational Description 40 eZ80F92 Development Kit User Manual Ri k Jumper J20 The J20 jumper connection controls the selection of the external chip select in the external application module When the shunt is placed the external chip select signal CS_EX is disabled See Table 24 Table 24 J20 EX_FL_DIS Shunt Status Function Affected Device IN The jumper for EX_FL_DIS is IN The chip select on the application module is disabled OUT The jumper for EX_FL_DIS is OUT The chip select on the application module is enabled Connectors A number of connectors are available for connecting external devices such as the ZPAKII emulator PC serial ports external modems the con sole and LAN telephone lines J6 and J8 are the headers or connectors that provide pin outs to connect any external application module such as ZiLOG s Thermostat Applica tion Module Connector J6 The J6 connector provides pin outs to make use of GPIO functionality Connector J8 The J8 connector provides pin outs to access memory and other control signals eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 41 Console Connector P2 is the RS232 terminal which can be used for observing the console output P2 can be connected to the HyperTerminal if required Modem Connector P3 provides a term
7. ZiLOG eZ80F92 Development Kit User Manual PRELIMINARY UMO13907 1003 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com eZ80F92 Development Kit User Manual Z 110 This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www zilog com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2003 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is not authorized
8. o lt k gt 3 9 9 N lt 9 PDJ0 7 AO oka oo 000009 _ Poz PDI0 7 ALI AT AO oF oo Canoa PD7 RIO Se 1 R37 AZ n PDSIDCDO 7 pps 0 A3 4 POS DSRO 75 pp4 m PDA DTRO 12 pg 4 RESET RESET x A4 PD3 CTSO CE 974 A5 PD2 RTS0 IR_SD LA 551 4 JTAG 1 4 E lt 4 VDD PD1 RxDO IR_RXD j 92 ASIA TDO H vss U8 PDO TxDO IR_TXD j 92 A6 9 Xe Von LS R28 AT 0 les TDO JTAGO 400 A7 TDO RD A8 6 TDI JTAG1 D j A8 TDI ZDA A9 64 TRIGOUT JIAG2 WR A10 Set eZ80F92 TRIGOUT LES OK T d PM TCK ZCL 65 TAG Aii 14 Bi IOREQ JOREG A A TMS Ce TMM BAT 41 A13 18 15 RTC von Leo RTC VDD MINIMELF_AK MREQ A14 COEPI 9 RTC XOUT REQ lt A14 RTC_XOUT 58 BIC XIN RTC_VDD JiRSTED 38 E VDD RTC XIN 25 GoldCap NSTRD lt ais gt b VSS vss j A15 VDD HE waro EL AS A16 HALT SLP E HALT SE 100nF eis A17 BUSACK HALT_SLP HALT SLP A18 A18 BUSREQ BUSREQ R29 GOLDCAP SD p Sm ED A19 24 REQ SS NMI 329 _ A20 A19 NMI RESET E A20 RESET 10k Q SUSREO BUSREQ 2 2s R32 BUSACK BUSACK ki ZS RTC XIN 220 773 Y3 l C20 v3 3 q LI 32 768kHz 18pF XTAL3 Aq RTC_XOUT VDD Z C24 VSS 18pF o GND NMI EW s AJO 23 C3 A 0 23 A 0 23 CS 0 3 C3 CS 0 3 CSI 0 3 V3 3 V3 3 V3 3 on lt gt DJo 7 D O 7 C21 C22 C23 PLACE CAPS CLOSE 1nF 1nF 1nF RTC VDpD RTE VOD TO PINS 1 l L 97 7 33 43 Figure 23 Schema
9. 110 nEX FL DIS nEM EN nDIS FL nL RD nmemen1l nmemen2 nmemen3 nmemen4 input nFL DIS nCs0 nCS2 A7 A6 A5 A4 A3 A2 Al AO nEX FL DIS Appendix A disables Flash on the expansion module when Low nt Platform LED enables Developm and Port A emulation circuit disables Module Flash when Low enables local data bus to be read by CPU synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc synthesis loc p4 P5 p3 P6 p7 P9 x P10 P11 P12 P13 P16 p2 was 23 input 7 0 A upper part of Address Bus of F92 A23 A7 A22 A6 A2 1 A5 A20 A4 A19 A3 A18 A2 A17 A1 A1 6 A0 PRELIMINARY UM013907 1003 output nCS EX nmemenl nmemen2 nmemen3 nmemen4 nDIS FL wire nCS EX nmemenl nmemen2 nmemen3 nmemen4 syn syn syn syn syn syn syn syn wire MOD DIS nmemen1 0 nmemen2 0 nmemen3 0 nmemen4 0 if any thesis thesis thesis thesis thesis thesis thesis thesis loc loc loc loc loc loc loc loc p17 P18 P19 P20 P21 P24 p25 p23 eZ
10. Ek O Table 26 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads List of Tables PRELIMINARY UMO013907 1003 eZ80F92 Development Kit Introduction User Manual 110 The eZ80F92 Development Kit provides a general purpose platform for evaluating the capabilities and operation of ZiLOG s eZ80F92 microcon troller The eZ80F92 is a member of ZiLOG s eZ80Acclaim product line which offers on chip Flash capability The eZ80F92 Development Kit fea tures two primary boards the eZ809 Development Platform and the eZ80F92 Flash Module This arrangement provides a full development platform when using both boards It can also provide a smaller sized ref erence platform with the eZ80F92 Flash Module as a stand alone devel opment tool Kit Features The Key features of the eZ80F92 Development Kit are eZ809 Development Platform Up to 2MB fast SRAM 12ns access time 1 MB factory installed with 512 KB on module 512KB on platform Embedded modem socket with a U S telephone line interface PC EEPROM DC configuration register GPIO logic circuit and memory headers Supported by ZiLOG Developer Studio II and the eZ809 C Compiler LEDs including a 7x5 LED matrix Platform configuration jumpers 1 Other members of the eZ80Acclaim product line include the eZ80F91 and eZ80F93 microcon trollers A scaled down eZ80F92 Ethernet Module is also available Contact your local Zi
11. Low Yes 34 DO Bidirectional Yes 35 D1 Bidirectional Yes 36 D2 Bidirectional No 37 D3 Bidirectional Yes 38 D4 Bidirectional Yes 39 D5 Bidirectional Yes 40 GND 41 D7 Bidirectional Yes 42 D6 Bidirectional Yes 43 MREQ Bidirectional Low Yes 44 IORQ Bidirectional Low Yes 45 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F92 device 3 External capacitive loads on RD WR IORQ MREQ DO D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ809 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Z 110 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 46 RD Bidirectional Low Yes 47 WR Bidirectional Low Yes 48 INSTRD Input Low Yes 49 BUSACK Input Pull Up 10KQ Low Yes 50 BUSREQ Output Pull Up 10KO Low Yes Notes 1 For the sake of simplic
12. Manual Z TiLag connector 2 PB7 PB6 PB5 4 b PB4 PB3 PB2 O O GND EXT 9 p PCT Pee 9 P PS C 9 S PC3 BGS 9 P PG1 co 9 p P PDE x P Sr EXT PD5 9 E PD4 PD3 P PD2 PDT Y P PDO O O GND EPA q p TRIGOUT TCK 9 5 TMS O RTC VDD q b EZ80CLK IICSDA Q P GND EXT FLASHW B CS3 q b DIS IRDA RESET Q E WAIT V33 EX E b GND EXT 7 IP A b NMI O lO HEADER 25X2 IDC50 Schematic Diagrams eZ80F92 Development Kit User Manual TiLog 73 V3 3 common power plane v3 3 V3 3 100nF GND il GND common ground plane no power supply on board Input VDD V3 3 3 3V 5 Power Pmax 1 6W Ptyp 0 4W Current Imax 200mA IrDA not in use for test purposes Imax 460mA IrDA in use AAA Ityp 100mA L 4 B don t stuff E NET Module Rev B 98Cxxxx xxx Figure 29 Schematic Diagram 8 of 9 Power Supply UM013907 1003 PRELIMINARY Schematic Diagrams D el Delen DIO SD 0 7 A 0 23 ALL only A0 A1 A2 A3 Al0 23 Sait 3 are used here PD3 and PD5 not used here PD O 7 lt RESET gt BESET _ U2D WAIT lt MA 74LCX32 TSSOP14 CSETH RD EEN wR w U6A 74LCX32 TSSOP14 CSI0 3 CS O 3 CS1 and CS2 not used here R30 10k U2B 0603 ep DIS_FLASH 3 DISABLE_FLASH 4 CSFLASH CS0 7ALCXOA TSSOP14 74LCX32 TSSOP14 U6D DIS_IRDA DISABLE_IRDA IRDA_SD PD2 IR SD 43 74LCX04 TSSOP14 74LCX32 TSSOP14 V3
13. No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Z rikoq HI Safeguards The following precautions must be observed when working with the devices described in this document AN Caution Always use a grounding strap to prevent damage resulting from electrostatic discharge ESD UM013907 1003 PRELIMINARY Safeguards eZ80F92 Development Kit User Manual IV 110 Safeguards PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 v Table of Contents safeguards e Qusa cede pee all EEN pu ye pw KEE a iii List Of PIBUFeS Kara ieo me OR PERAE e RR daw dal ela da d vii Listof Tables siye sa e da nde chad t hend Qura EE ix Introduction dre Kel n EE EAR sl db ee sewed 1 Kit Featut s doi e eae ee der ds 1 Hardware Specifications 2 eZ80 Development Platform Overview 3 eZ80 Development Plattform 7 Functional Description sa EEN 1 Physical Dimensions kk kk kK KK KK KK KK KK KK KK KK KK K 9 Operational Description 10 eZ80F92 Flash Module Interface 10 Application Module Interface 20 VO Functionality AA esee be en mathe kb 4 N k l 23 Embedded Modem Socket Interface 28 eZ809 Development Platform Memory 30 LEDS opis ai
14. Pin Symbol Signal Direction Active Level eZ80F92 Signal 16 GND 17 A2 Bidirectional Yes 18 A1 Bidirectional Yes 19 A11 Bidirectional Yes 20 A12 Bidirectional Yes 21 A4 Bidirectional Yes 22 A20 Bidirectional Yes 23 A5 Bidirectional Yes 24 A17 Bidirectional Yes 25 DIS_ETH Output Low No 26 EN_FLASH Output Low No 27 A21 Bidirectional Yes 28 Vpp 29 A22 Bidirectional Yes 30 A23 Bidirectional Yes Notes For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 The Power and Ground nets are connected directly to the eZ80F92 device External capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ809 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UMO13907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 14 110 Table 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 31 CSO Input Low Yes 32 CS1 Input Low Yes 33 CS2 Input
15. Platform consists of seven major hardware blocks These blocks listed below are diagrammed in Figure 4 e eZ80F92 Flash Module interface 2 female headers Power supply for the eZ809 Development Platform the eZ80F92 Flash Module and application modules Application Module interface 2 male headers GPIO and LED matrix e RS232 serial communications ports Embedded modem interface e C devices UMO13907 1003 PRELIMINARY eZ80 Development Platform eZ80F92 Development Kit User Manual Z 8 110 Peripheral Device Signals Address Bus I I I I I I I eZ80 1 Flash MPU Module Deis Bas pu Interface i I I RS232 0 I I Console I I SRAM UR I I up to 2 MB l J RS232 1 Modem Embedded Modem r m Ji E x5 matrix buttons GPIO and Address Decoder EEPROM Register Application Module Headers Figure 4 Basic eZ80 Development Platform Block Diagram v eZ80 Development Platform PRELIMINARY UMO13907 1003 Physical Dimensions eZ80F92 Development Kit User Manual 110 The dimensions of the eZ809 Development Platform PCB is 177 8mm x182 9mm The overall height is 38 1 mm See Figure 5 175 3 mm lt 43 2 mm 114 3 mm 2 VOLT SELECT n H E o o
16. R7 0 001uF 0 001uF GND 12 CH s CIs L CT U13 ED eto TRIG1 1 A 2 En veo Leg GRD MRE G TRIGA gt gt MRESET OVERR N MUXO op 16 TRIGZ n BR nop fe DS Pi MINA MUX SEL 13 SND e ina MZINB M_OUT_A yy E r ral ad m ER L4 Ip 20 VOD N WIND A guo GND M OUT D J T 10 NO 12 N OUT I ER r4 r4 r4 p Pin2 PCA8550 0 tuF 74HCT374 GND A a a A lt MDIZ 0 DIS 1 MD 7 0 e DIO AN 44 r F4 r4 r4 r J CS0 2 2 m MIA Qo H ch cr ch 2 8 gt CON_DIS GND 12 11 gt MOD_DIS Sie au o PRA PHI os H2 2 c D PHI a r1r r r r Td74LvT125 Td74LvT125 GND S D I S we ar K DIS_0 WR ch ch AN WR li ciK ver J J19 Ser 14 OE A 14 2 i M cs EX Soa Sa De ND 4 m SCL 6 Ls CS2 74HCT374 gt DIS_IRDA cs2 gt VDD CS3 cs3 gt n VDD EX SEL LTP 757 TQ74LVT125 R13 10K R10 R11 R12 10K 10K 10K U15 2 GND DIS_EM 1 3 17 EM RD EMEN 4 n hea 18 EM WR SW AD 19 CT WR a 13 1 02 o o gt PB0_T0_I 33 LY 4 103 20 AN WR WR 7 15 vos 21 gt gt DIS_ETH SW PUSHBUTTON 16 W s pa m 17 vos 22 oss M2 iz 8 vor H AS o o gt gt PB1_T1_I 19 1 08 13 Ho yoo HZ A SW PUSHBUTTON 16 jin i vec L AU EM_WR_OE VDD Im ora DD 2 kon GND H4 Lo EM 13 geAB vec H4 A o o 4 gt PB2_SS O 1uF QEBA ND E SW PUSHBUTTON 22V10A LCC_0 ND ula cs xp VDD 23 SEAR 0 1uF GND TALCX543 SO GND UM013907 1003 Figure 18 eZ80 Development Platform Schematic Diagra
17. RIA 23 FORCEON INVALID Ht om Ain cnp S 4 SND i 120 10K RH B 20 ague DS1487 LA DSR PC5 DSRIK 4 R10UT RIIN DSR TE eS 4 RI1_NB 18 5 RI1 psr1 6 RH B i anal m RXDi 2 5 J16 PC7 RII 2 PC3 CTS 177 paour Rain F SH RE Ho REA 3 RXD1 CTST8 1 a PC RXDI amp 16 paour San Z ISt 8 o Header 3 DIRI 4 o L2 gt gt DIS_1 pc6_DcpK 1 RsoUT RsIN DEDI Ri 9i o 5l te MODEM RS485 2 EN 3 DB9 Male i MAX3245CAI UM013907 1003 Figure 20 ez80 Development Platform Schematic Diagram 4 of 5 PRELIMI NARY Schematic Diagrams eZ80F92 Development Kit User Manual zi L k 65 MATES WITH AMP 749268 1 P1 1 6 8 LENGTH 5 WIRES 28 AWG Figure 21 ez80 Development Platform Schematic Diagram 5 of 5 RS 485 Cable UMO13907 1003 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual eZ80F92 Flash Module Z Figures 22 through 30 diagram the layout of the eZ80F92 Flash Module Ethernet circuiting devices are not loaded on the sion 66 eZ80F92 Flash Module However these devices appear in the following schematics for reference purposes RAM CPU Peripherals Connector SRAM eZ80 Reset Headers DIO 7 RESET IRDA_TXD du ROAD RESET D O 7 D O 7 RESET IRDA_RXD BRDA SD RESET IRDA_SD A 0 23 a A 0 23 ELASEWE FLASHWE RD e RD IOREQ RES REG IOREQ zs wR MREQ ween INSTRD ME CS1 INSTRD
18. Status Function Affected Device In The RS485 circuit is enabled on UARTO IrDA UARTO CONSOLE The UARTO CONSOLE interface and IrDA are interface RS485 interface disabled Out The RS485 circuit is disabled on UARTO IrDA UARTO CONSOLE interface RS485 interface Note To enable the RS485 circuit the corresponding IrDA RS232 circuit must be disabled UMO13907 1003 PRELIMINARY Operational Description 38 eZ80F92 Development Kit User Manual Ri D q Jumper J16 The J16 jumper connection controls the selection of the RS485 circuit However UART1 MODEM interface and the socket modem interface are disabled if the RS485 circuit is enabled When the shunt is placed the RS485 circuit is enabled See Table 20 Table 20 J16 RS485 2 EN Shunt Status Function Affected Device In The RS485 circuit is enabled on UART1 UART1 MODEM interface The UART1 MODEM interface and the Socket Modem Interface and Socket Modem interface are disabled RS485 interface Out The RS485 circuit is disabled on UART1 UART1 MODEM interface Socket Modem Interface and RS485 interface Jumper J17 The J17 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 21 Table 21 J17 RT 1 Shunt Status Function Affected Device In The Termination Resistor for RS485 1 is IN RS485 interface Out The Termination Resistor for RS485_1 is OU
19. address latch assign DEM RD nDIS EM 1 nRD 0 amp nEM EN 0 address latch assign nAN WR nDIS EM 1 nWR 0 nEM EN 0 address anode assign nCT WR nDIS EM 1 amp nWR 0 amp nEM EN 0 amp address cathode assign nDIS ETH nCS endmodule Appendix A PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 81 Customer Feedback Form If you note any inaccuracies while reading this User Manual please copy and complete this form then mail or fax it to ZILOG see Return Information below We also welcome your suggestions eZ80F92 Development Kit Serial or Board Fab Rev Software Version Document Number Host Computer Description Type Customer Information Name Country Company Phone Address Fax City State Zip E Mail Return Information ZiLOG System Test Customer Support 532 Race Street San Jose CA 95126 Phone 408 558 8500 Fax 408 558 8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the problem Attach additional pages as necessary UMO13907 1003 PRELIMINARY Customer Feedback Form
20. in Table 26 are for the user s reference These values can vary depending on the type of application that is developed to run with the platform Table 26 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads Current Platform Modules Configurations Requirement mA Status eZ80 Development Platform 173 When connected only to a and eZ80F92 Flash Module power supply and when no program is running eZ80 Development Platform 174 When connected only to a eZ80F92 Flash Module and Modem power supply and when Module no program is running eZ80 Development Platform 195 When connected only to a eZ80F92 Flash Module and power supply and when Thermostat Application Module no program is running eZ80 Development Platform 203 When connected only to a eZ80F92 Flash Module Modem power supply and when Module and Thermostat Application no program is running Module eZ809 Development Platform 325 When the LED demo is and eZ80F92 Flash Module running eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 43 Table 26 DC Current Characteristics of the eZ80 Development Platform with Different Module Loads Continued Current Platform Modules Configurations Requirement mA Status eZ809 Development Platform 325 When the LED demo is eZ80F92 Flash Module and Modem running Module eZ809 Development Platform 350 When the LED demo is eZ80
21. register contains three control bits Bit 0 enables or disables the IrDA encoder decoder block Bit 1 if it is set eZ80F92 Flash Module PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual AR Diipa enables received data to pass into the UARTO Receive FIFO data buffer Bit 2 is a test function that provides a loopback sequence from the TxD pin to the RxD input Bit 1 the Receive Enable bit is used to block data from filling up the Receive FIFO when the eZ80F92 Flash Module is transmitting data Because IrDA data passes through the air as a light source transmitted data can also be received This Receive Enable bit prevents this data from being received After the eZ80F92 Flash Module completes transmitting this bit is changed to allow for incoming messages The code that follows provides an example of how this function is enabled on the eZ80F92 Flash Module Init_IRDA Ensure to first set PD2 as a port bit an output and set it Low PD_ALT1 amp OxFC PD_ALT2 0x03 UART LCTLO 0x80 BRG_DLRLO 0x2F BRG DLRH0 20x00 UART LCTL0 20x00 UART FCTL0 0xC7 UART LCTL0 20x03 IR CTL 0x03 IRDA Xmit IR CTL 0x01 Putchar 0xb0 UMO13907 1003 PDO uartOtx PD1 uart0_rx Enable alternate function Select dlab to access baud rate generator Baud rate Masterclock 16 baudrate High byte of baud rate Disable dlab Clear tx fifo
22. to the GPIO Port B pins PBO The PBO push button switch SW1 is connected to bit O of GPIO Port B This switch can be used as the port input if required by the user UMO013907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 34 110 PB1 The PB1 push button switch SW2 is connected to bit 1 of GPIO Port B This switch can be used as the port input if required by the user PB2 The PB2 push button switch SW3 is connected to bit 2 of GPIO Port B This switch can be used as the port input if required by the user RESET The Reset push button switch SW4 resets the eZ809 CPU and the eZ809 Development Platform Jumpers The eZ80 Development Platform provides a number of jumpers that are used to enable or disable functionality on the platform enable or disable optional features or to provide protection from inadvertent use Jumper J2 The J2 jumper connection enables disables IrDA transceiver functionality When the shunt is placed IrDA communication is disabled See Table 13 Table 13 J2 DIS IrDA Shunt Status Function Affected Device In IrDA interface disabled UARTO is configured to work with the RS232 or the RS485 interfaces Out IrDA interface enabled The IrDA and UARTO interfaces on the eZ80F92 Flash Module perform their functions eZ80 Development Platform PRELIMINARY UMO13907 1003 Jumper J3 eZ80F92 Development Kit User Manual 110 35 The J3 jumper co
23. 00843 T prius e ooko o s l TTT D ES O lt gt Lar o o d o o o ong El Ss o oo oo wem NI 20eh E o o 2 lt 9 Ise E CH o No D o eo BN Zeen 0 o O OUR eeccoce c E oo ES o o o o o ooo o o 0000 o o o Of Rs O ofr af o0 ce N o SCRI S OO ge ER Ies O Q oo OO cs u C16 o di 8 00 7680086 8V4 901 Z O O O O O O O O O O 99 zm CO o Od o o D o KA R34 i1 22 Eum lla s Pe Pu DCH 0000000000000000000000 O O O O O O O O O O O O O O O O O O O O OJ er o e N sot A Ped IN CO o o QZ O g OO OO DEJO 2 c20 LCS o DCH ks Figure 13 eZ80F92 Flash Module Bottom Layer UM013907 1003 PRELIMINARY Functional Description eZ80F92 Development Kit User Manual 48 Diog Operational Description The purpose of the eZ80F92 Flash Module as a feature of the eZ80F92 Development Kit is to provide the application developer with a plug in tool to evaluate the memory IrDA and other features of the eZ80F92 device eZ80F92 Flash Module Memory The eZ80F92 Flash Module comprises both off chip SRAM and on chip Flash memory which are described below Static RAM T
24. 0E GND PC1_RXD1 lt lt 51 52 PBT T1 PC0_TXD12 PBO TO VDD 74LVC244A U5 Mis H A1 Yi MATE le e MATS 8 VDD GND 11 P Me MA21 1 MA22 127 A8 Y6 MA23 17 A7 Y7 AB Ya GND s 40 GND 14 42 TOE vcc m 13 44 Zi GNE 19 20E GND AT 15 16 AT3 A4 17 18 Ai 7ALVC244A GND i 2 GND DIS_IRDA A16 2 X MWAIT A18 AO 25 26 NNT A22 zom 29 0 HE Header 25x2 RDX RESET 33 34 leader 35 36 von BUSACK 37 38 d 0 3 4 HEADER 2 4 42 py 43 44 10K D4 45 46 D6 47 48 ZDI GND 49 50 51 52 INTERFACE CS0 53 54 CS2 55 56 vun EP MEMRO pp 57 58 GND 59 60 Header 30x2 Header 3x2 VDD pee E e USA Tok DCD 2 HL RESET EI L2 4 VDD TC74LVCOB RX p2 UBA 1 2 GND P1 GND R5 TDI DTR 1K TOO z NA TC74LVT125 TCK 3 a GND 5 6 TX ET TVCC_RESETn 7 8 TMS 1 4 2 HEADER 9 HEADER 32 gt 10 PRSTn MODEM CONNECTORS at 2 TRIGOUT 13 44 con 7x2 UM013907 1003 eZ80F92 Development Kit User Manual 61 TiLaog U2 S La spa L SDA gue L aa VDD soL vec H S0 SGL E END H Ls m WP NC 1 AT24C128 2 mp DIS IRDA opis GND HEADER2 J7 4 FLASHWE 2 GND U21 HEADER 2 MCSO 3 23 MES Au 0 CS0 mes Ha vH e MIOR A3 Y3 CS2 Mmea aaa Ya 20 gt S 10RQ MR AS Y5 S MERO Mm 6 Y6 MED s w RD MPH 10748 V His zr todas yo H PHI Q vio 1Llzer 24 VDD GND n 13 2E1 Ke 12 GND cn 74
25. 0F92 Development Kit User Manual 10 Diog Operational Description The eZ80 Development Platform can accept any eZ809 core based mod ules provided that the module interfaces correctly to the eZ809 Develop ment Platform The purpose of the eZ809 Development Platform is to provide the application developer with a tool to evaluate the features of the eZ80F92 Flash MCU and to develop an application without building additional hardware eZ80F92 Flash Module Interface The eZ80F92 Flash Module interface provides easy connection of the eZ80F92 Flash Module It also provides easy connection for any eZ80 based module designed to this interface This includes modules using future eZ80 devices and user developed modules using current eZ809 devices The eZ80F92 Flash Module interface consists of two 50 pin receptacles JP1 and JP2 Peripheral Bus Connector Figure 6 illustrates the pin layout of the Peripheral Bus Connector in the 50 pin header located at position JP1 on the eZ809 Development Plat form Table 2 describes the pins and their functions eZ80 Development Platform PRELIMINARY UMO13907 1003 GND_EXT DIS_ETH WR BUSACK HEADER 25X2 IDC50 eZ80F92 Development Kit User Manual AP ZInp INSTRD BUSREQ Figure 6 eZ80 Development Platform Peripheral Bus Connector Pin Configuration JP1 UMO13907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit
26. 3 VDD DIS_FLASH pp VSS DIS_IRDA DIS IRDa GND Figure 30 Schematic Diagram 9 of 9 Control Logic UM013907 1003 PRELIMINARY eZ80F92 Development Kit User Manual TiLaog 74 AR SDIO 2 SA 0 3 SA 0 3 ETHRD gt qETHRD ETHWR Ceman PD4 EMTHIRO erun To taa kr n H PD7 Rt OR SLEEP DO gt siee PD6 R OR ACTIVE active don t stuff R35 0 WAT AA JIOCHRDY PDO IRDATXD _ IRDA rop PD1 IRDA RXD iRDA pop IRDA SD RDA SD RESET RESFLASH RESFLASH CSFLASH CSFLASH Schematic Diagrams eZ80F92 Development Kit User Manual Diipa 75 Appendix A General Array Logic Equations This appendix shows the equations for disabling the Ethernet signals pro vided by the U10 and U15 General Array Logic GAL devices U10 Address Decoder define define l define define idle 2 b00 statel 2 b01 state2 STEET state3 2 p10 FOR eZ80 Development Platform Rev B This PAL generates 4 memory chip selects module f92 decod nCS EX Enables Extension Module s Memory when Low nFL DIS when Low WEB Module Flash is disabled nDIS FI 0 nCS0 AT A6 A5 Al A3 A2 Al AO nCS2 UMO13907 1003 when High nDIS FL depends upon state of nmemenX A23 A22 A21 A20 A19 A18 A17 A16 PRELIMINARY Appendix A 76 eZ80F92 Development Kit User Manual
27. 3 2 1 0 Anode Col 1 X Anode Col 2 X Anode Col 3 X eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 25 Table 7 LED Anode GPIO Port A Output Control Register Continued Bit Function 7 6 5 4 3 2 1 0 Anode Col 4 X Anode Col 5 X Anode Col 6 X Anode Col 6 X GPIO Output X The GPIO Data Register receives inputs or provides outputs for each of the seven GPIO Port A lines depending on the configuration of the port See Table 8 Table 8 GPIO Data Register Function Bit 7 6 5 4 3 2 1 0 GPIO DO X GPIO D1 X GPIO D2 X GPIO D3 X GPIO D4 X GPIO D5 X GPIO D6 X GPIO D7 X LED Matrix The one 7x 5 LED matrix device on the eZ809 Development Platform is a memory mapped device that can be used to display information such as programmed alphanumeric characters For example the LED display UMO013907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 26 110 sample program that is shipped with this kit displays the alphanumeric message eZ80 To illuminate any LED in the matrix its respective anode bit must be set to 1 and its corresponding cathode bit must be set to 0 Bits 0 6 in Table 7 are LED anode bits They must be set High 1 and their corresponding cathode bits bits 0 4 in Table 9 must be set Low 0 to illuminate each of the LED s respectively Bit 7 in Table 7 does not carry any sig
28. 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 UMO13907 1003 110 eZ80 Development Platform Hardware Specifications 2 eZ80 Development Platform Peripheral Bus Connector Identification JP1 12 eZ80 Development Platform I O Connector Identification JPZ le e atts EE e 17 GPIO Connector Jo 21 CPU Bus Connector J8 23 LED and Port Emulation Addresses 24 LED Anode GPIO Port A Output Control Register 24 GPIO Data Register iii ariba a 25 Bit Access to the LED Cathode Modem and Triggers 26 Connector JD dose ra bleed ia 28 Conn ctor J9 ci dinar cir da En aeg dr RS 4 eni 29 Connector J1 egg ar cause es EN E 29 J2 DIS DA ss eer a daye aku kan aaa 34 3 DIS EE 35 J7 FlashWE Off Chip 35 J11 EN_FLASH Off Chip 36 J12 5VDC 3 3VDC for an Embedded Modem 36 JIA RL icons A eka A 37 J15 RS485_1_EN nne 37 J16 RS485 2 EN 38 J17 RT d suya unc ean dala RR x kh al wawaqa 38 J18 RT WEE 39 RK TT EE 39 J20 EX FL DIS yusa Aze n le Man ela x RD eed 40 IPC Addresses 41 PRELIMINARY List of Tables ix x eZ80F92 Development Kit User Manual
29. 80F92 Development Kit User Manual Diipa 77 enables memory on the Expansion Module enables memory on the Development Platform enables LED and Port A emulation wire nEXP_EN of the signals is Low Elash on the Module will be disabled if nDIS_FL is High nCS0 0 amp A7 0 amp A6 1 expansion module wire nDIS FL nFL DIS UMO13907 1003 nEXP EN PRELIMINARY Flash enabled if this is 0 nFL DIS General Array Logic Equations 78 eZ80F92 Development Kit User Manual 110 wire nDIS FL nFL DIS nEXP_ assign nCS_EX nEX_FL DIS assign nL_RD EN is disabled nEXP EN nEX FL DIS nmemen1 0 nmemen2 0 nCS EX 0 assign nmemen4 nCS2 0 assign nmemen3 nCS2 0 assign nmemen2 nCS2 0 assign nmemenl nCS2 0 assign nEM EN nCS2 0 amp endmodule U15 Address Decoder Appendix A define anode 8 h00 define cathode 8 h01 define latch 8 h02 nmemen3 0 nmemen4 0 amp A7 A6 A5 A4 A3 5 n17 amp A7 A6 A5 A4 A3 5 h16 amp A7 A6 A5 A4 A3 5 h15 amp A7 A6 A5 A4 A3 5 h14 A7 A6 A5 A4 A3 A2 A1 AO FOR eZ80 Development Platform Rev B This PAL generates signals that control Expansion Module access LED and Port A emulation This devi
30. 9 33v E555555555595559599959595 559553595939559 93373 J H IEXANT SOCKETMODEM SF56D SP mn COPYRIGHT ZiLOG INC 2002 loooo0c000000000000000 Ig9 000000000000000000 GND oo o o o uro J9 0666565695509 n z e T C Au d opt C20 A16 DO A18 D I A20 o C29 A22 TRIG2 TRIGI ADIs HDHH gt M Dm OWN mmt Kai RD RESET BUSACK NMI GND 0000000 omii RIS TUUUTUUU PB2 UUUUUUUU zB 000000000000000000000000000000 GND RESET l o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o rp SS 8 o o 5 1mm lt o o o A PI o o eo Zo 50 o 157 5 mm 167 6 mm Y 165 1 mm Figure 5 Physical Dimensions of the eZ80 Development Platform UMO13907 1003 PRELIMINARY Functional Description eZ8
31. C10 10nF 0603 BISIG AX8802UR29D3 IR transceiver v3 3 A R6 2R7 0 25W IRDA TxD RPA TXD 1206 MMA 0204 IRDA_RXD IRDA RXD apx 5D IRDA_SD UM013907 1003 IRDA_TXD IRDA_SD IRDA_RXD Figure 27 Schematic Diagram 6 of 9 IrDA Reset PRELIMINARY VDD VSS gt RESET V3 3 Schematic Diagrams 71 A O 23 o connector 1 JP1 D 0 7 DIO 7 pa d b A0 GND EXT E b Vi3 b em a CS 0 3 R7 R8 Ze 4k7 4k7 ci E E A18 a b A16 IICSDA IICSDA ATO GND_EXT IICSDA A B b AT IICSCL IICSCL IICSCL A p A R9 n qd E 22 CLK_OUT EZ80CLK A AT CLK OUT gt 22 L FUTURE U d b DIS FLASH DIS FLA DIS FLASH place near eZ80 21 E b va EXT CS RAM output PHI CS0 P CS1 DIS ta T SS d b Do Q O FLASHWE D3 D4 CLASHWEC DS DE EXT RTC VDD D7 D6 Rre vpp pPRICVOD Goen b SE GND EXT a b RD WR E b INSTRD PB O 7 lt gt BUSACK 5 E BUSREQ GO 7 PC O 7 A HEADER 25X2 PDIO 7 Pan RESET RESET RD RD we SR IOREQ R33 MRED MREQ 2k2 INSTRD SEH 0603 WAIT WAIT Preset HALT SLE R11 R12 BUSREQ BUSREQ BUSREQ 10k 10k BUSACK BUSACK NMI JTAG1 TDI TW lt JTAGO TDO JTAG2 TRIGOUT JTAGLL4 JTAG3 TCK merae m Tat NS V3 3 V3 3 EXT V3 3 EXT GND EXT EUM GND UM013907 1003 R13 4k7 Figure 28 Schematic Diagram 7 of 9 Headers PRELIMINARY eZ80F92 Development Kit User
32. F92 Development Kit User Manual 110 45 Physical Dimensions The dimensions of the eZ80F92 Flash Module PCB is 64x 64mm With an RJ 45 Ethernet connector the overall height is 25mm See Figure 11 63 5 mm gt 4 mm Top View UO Connector T LO jz 1 Oo O X E O O 0 L lt 55 88 mm Figure 11 Physical Dimensions of the eZ80F92 Flash Module UMO13907 1003 PRELIMINARY Functional Description 46 eZ80F92 Development Kit User Manual Z 110 Figure 12 illustrates the top layer silkscreen of the eZ80F92 Flash Mod ule clos Yt m 1 CTO Oss C 0000 foo o ola A E ool v j E oo e III o ajo So B i s2 wa E o 9 08 OG oo US 2 mim SS o o 0 0 da e HH glo o oo Bh E BY SIO o OO mm u glo 9 OO g Slo O ooz RE BIO o o o lo ES So o o ollo g Slo o o ollo ga RIO o o ollo CSS lo o o ollo o CR SG oo O OO g Si oo ooljo oJ lt leo O OIIO IW um 9 ooo R32 oO 8 siii oo oo 400000 oO Vo of 2 Laf lex J o oJ Figure 12 eZ80F92 Flash Module Top Layer eZ80F92 Flash Module PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Z ZInp Figure 13 illustrates the bottom layer silkscreen of the eZ80F92 Flash Module O ooo ooo SSO 0
33. F92 Flash Module and running Thermostat Application Module eZ809 Development Platform 360 When the LED demo is eZ80F92 Flash Module Modem running Module and Thermostat Application Module UMO13907 1003 PRELIMINARY DC Characteristics eZ80F92 Development Kit User Manual 110 eZ80F92 Flash Module This section describes the eZ80F92 Flash Module hardware its interfaces and key components including the CPU real time clock IrDA trans ceiver and memory Functional Description The eZ80F92 Flash Module is a compact high performance module spe cially designed for the rapid development and deployment of embedded systems Additional devices such as serial ports LED matrices GPIO ports and I C devices are supported when connected to the eZ809 Devel opment Platform A block diagram representing both of these boards is shown in Figure 1 on page 4 The eZ80F92 Flash Module is developed to be a plug in module to the eZ809 Development Platform This small footprint module provides a CPU RAM an IrDA transceiver and a real time clock This low cost expandable module is powered by the eZ80F92 microcontroller members of ZILOG s new eZ80 product family The module also contains a bat tery and an oscillator in support of the on chip Real Time Clock RTC The eZ80F92 Flash Module can also be used as a stand alone develop ment tool when provided with an external power source eZ80F92 Flash Module PRELIMINARY UMO13907 1003 eZ80
34. IMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 57 ZDS II ZiLOG Developer Studio II ZDS II Integrated Development Environ ment is a complete stand alone system that provides a state of the art development environment Based on the Windows Win98SE NT4 0 SP6 Win2000 SP2 WinXP user interfaces ZDS II integrates a language sensitive editor project manager C Compiler assembler linker librarian and source level symbolic debugger that supports the eZ80F92 For further details about ZDS II for eZ80Acclaim products please refer to the ZiLOG Developer Studio eZ80Acclaim User Manual UMO144 UMO13907 1003 PRELIMINARY ZDS II eZ80F92 Development Kit User Manual 58 110 ZDS Il PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Diipa 59 Troubleshooting Overview Before contacting ZiLOG Customer Support to submit a problem report please follow these simple steps If a hardware failure is suspected con tact a local ZiLOG representative for assistance Cannot Download Code If you are unable to download code to RAM using ZDS make sure to press and release the Reset button on the eZ80 Development Platform prior to selecting Build gt Debug gt Reset Go in ZDS No Output on Console Port The eZ80F92 Development Kit is shipped with a Flash Loader utility that is loaded in the protected boot sector of Flash memory U3 Upon power up of the eZ809 Development Platform and
35. INSTRD cs1 4 WAIT WAIT WAIT di waT HALT SLP HALT SLP HALT SIP HALT SUP BUSREQ BUSREQ BU RED d BUSREQ BUSACK BUSACK ROM nmi q AMI NMI NOR Flash pra CLK OUT HS OUT ZIK QUT CLK OUT D O 7 q4 era num RTC_VDD BBI P d d 39 RTE VOR RTC_VDD ajo 231 q IICSDA Logic 11 7 IICSDA RD IICSDA S TICSCL IICSCL P ICSDA RD gt S IICSCL CTRL Logic IICSCL WR E DJO 7 i Se D 0 7 CSFLASH g GT RESET RESET AID 23 WAIT A 0 23 RESFLASH RESELASHI PB O 7 EET 4 RAK WR WR FLASHWE 4 ME PC O 7 c IRDA SD DIS FIA RD RD PDIO 7 DIS FLASH doc FLASH PDIO 7 PD O 7 DIS_IRDA WS DIS_IRDA DIS_IRDA CS 0_3 PB 0 7 CS O 3 CS O 3 CSFLASH PET TM 80 71 CSFLASH TET gt S JTAG 1 4 Y L RESFLASH RESELASH _CSI0 3 TDO is CS 0 3 e ul amp 2 lll JTAG 1 4 E TO TDO i lt Ethernet B Power A CS8900A DA US V3 3 EXT PowerSupply SD 0 7 d GND_EXT E SAD 3 dn A lt V3 3 IOCHRDY P GND GND ETHRD ETHWR ETHIR ETHIRQ P QRO SLEEP 4 ACTIVE ACTIVE Figure 22 Schematic Diagram 1 of 9 Top Level UMO13907 1003 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual XIN VA 67 TiLog eZ80 IIC bus master PC 0 7 IICSDA lICSDA C 5 eSDA IESDA csc C cscL 1ICSCL CLK OUT CLK OUT EE Ut PBJO 7 x F Z lez lelez ecl lee m pan 91 lt e EBR E EE Pcjo 7 lt N 7220088rg Z2 Slalalalol E N
36. LOG Sales Office for more information UMO13907 1003 PRELIMINARY Introduction 2 eZ80F92 Development Kit User Manual 110 Two RS232 connectors console modem RS485 connector with cable assembly ZiLOG Debug Interface ZDI JTAG Debug Interface 9VDC power connector Telephone jack e eZ80F92 Flash Module eZ80F92 microcontroller operating at 20 MHz with 128 KB 256bytes internal Flash and 8KB internal SRAM 512KB off chip SRAM Real Time Clock with Battery Back Up e ZPAKII Debug Interface eZ80F92 Development Kit Software and Documentation CD ROM Hardware Specifications Table 1 lists the specifications of the eZ809 Development Platform Table 1 eZ80 Development Platform Hardware Specifications Operating Temperature 20 C 5 C Operating Voltage 9 VDC 2 Also available is the eZ80F93 microcontroller which features 64 KB of internal Flash memory and 4KB of internal SRAM Please contact your local ZiLOG Sales Office for details Introduction PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Diipa 3 eZ80 Development Platform Overview The purpose of the eZ809 Development Platform is to provide the devel oper with a set of tools for evaluating the features of the eZ809 family of devices and to be able to develop a new application before building appli cation hardware The eZ80F92 Development Kit features two primary boards the eZ809 Development Platform a
37. LVC827ISO Our vcc 91 VDD g 2 d 3 Header 3 u7 MDZ A Bt MD3 A2 B2 Mp4 589 B MBS 32 A4 B4 ee HA5 B5 mor SE Br M RD 1 La DIR vcc L_RD gt 183 0E GND m TALVC245 50 ip 0 1uF gt gt MD 7 0 MDO veo 3 TER von YR s GND 7 Figure 17 ez80 Development Platform Schematic Diagram 1 of 5 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual 62 LR R6 40K Ferrite Core VDD U10 CS2 a 4 ee Liz cs EX a M_TIP amp t 2 FL Di 4 18 MEM CEN FL_DIS 1 CS0 511 vos DS MEM GEN Q MEM CENI P4 Ces 6 20 MEM CERS MEN n 4 A 4 vos H2 MEM CENA MEM CEN3 Lx 114 15 1 04 MEM_CENA 2 m ESA 225 vos H gt gt L_RD E 31 A20 10 24 EM EN a i 4 17 1 06 4 AS 11718 1107 28 Dis FL ATE 12 9 1108 H2 A SIDACTOR P3100SB RJ14 ATT 13 Ho uo9 HZ ut J20 ATR 16 2 i vec 28 VDD M RING 4 e EX FL DIS 1 EX FL DIS 2 cuko Les CH E VDD 22V10A LCC e ND OjduF ca ca 10K
38. M013907 1003 PRELIMINARY Operational Description 50 eZ80F92 Development Kit User Manual 110 however it cannot do both at the same time Only a few registers are required to configure the UARTO port to send and receive IrDA data The RxD and TxD signals on the transceiver perform the same functions as a standard RS232 port However these signals are processed as IrDA 3 16 coding pulses sometimes called IrDA encoder decoder pulses When the IrDA function is enabled the final output to the RxD and TxD pins are routed through the 3 16 pulse generator Another signal that is used in the eZ80F92 Flash Module s IrDA system is Shut Down SD The SD pin is connected to PD2 on the eZ80F92 Flash Module The IrDA control software on the user s wireless device must enable this pin to wake the IrDA transceiver The SD pin must be set Low to enable the IrDA transceiver On the eZ80F92 Flash Module a two input OR gate is used to allow an external pin to shut down the IrDA transceiver Both pins must be set Low to enable this function Figure 14 highlights the eZ80F92 Flash Module IrDA hardware connec tions External Disable ezgoLo2 PD2 IR_SD Device PD1 RxD PDO TxD Figure 14 IrDA Hardware Connections The eZ80F92 Flash Module features an Infrared Encoder Decoder regis ter that configures the IrDA function This register is located at address OBFh in the internal I O register map The Infrared Encoder Decoder
39. O GND SCHNAANMTYHE IS SS XIN N Q Q Z HNN 00 z 2x8xg xdoaouzOooo0 aa Agogo o o ofa amp amp o9 222 aaae EH Ha 2 6 OZ ZZ ZZ Z 6L 1 499 LANLED SD9 aaa Ou2 LANLED poc LINKLED LJ SD8 WO LINKLED HCo D I R22 e So MEMW amp XTAL2 S Y1 4k7 lt MEMR lt XTAL1 Los 20 000 MHz INTRQ2 o AVSS Hi _ HC49SM INTRQ1 ul AVDD LZ ETHIR d Q INTRQO AVSS 94 R23 29 IOCS16 U7 RES FS RXD L d MEMCS16 RXD L RxD 4K99 196 INTRQ3 RXD j 21 lt ZO SHBE CS8900A CQ3 AVDD L SAO S LA SAO AVSS fe XD PEE E SAT TxD L 20 SA2 TOFP100 TXD Cas 44 SA3 AVSS Hi 27 SA4 AVDD 2 Salt 3 E DO Fe 44 DO 2 CL LS lt P Ch 30 lt F 2 DF 2 Di 72 H maed eSTATUSHC K am TA 0 TEST B int Pull Up GND GND pm E TD R24 cial J1 560p device addresses r 00300h bis 0030Fh C13 ETHRD mE ja 100nF ETHWR IOCHRD HFJ11 1041 Geseems s Tx s thtough hole HEADER 1 TX lt gt 2 SD 0 7 lt gt SDIO 7 solder pad SIP1 RX lt gt 3 place don t RX lt gt 6 H SA O 3 gt ETHIRO lt PEHIRO __ sleep gt SEEP ACTIVE lt ACTIVE LANLED ferrite tbd GND dont stuff Figure 26 Schematic Diagram 5 of 9 eZ80F92 Flash Module UM013907 1003 PRELIMINARY Schematic Diagrams power supervisor VDD GND MAX6328UR29 SOT 2343 100nF 0603 R3 2k2 0603 RESET eZ80F92 Development Kit User Manual TiLog open drain
40. T RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 39 Jumper J18 The J18 jumper connection controls the selection of the RS485 termina tion resistor circuit When the shunt is placed the RS485 termination resistor circuit is enabled See Table 22 Table 22 J18 RT 2 Shunt Status Function Affected Device In The Termination Resistor for RS485 2 is IN RS485 interface Out The Termination Resistor for RS485_2 is OUT RS485 interface Note Before enabling the termination resistor ensure that the device is located at the end of the interface line Jumper J19 The J19 jumper connection selects the range of memory addresses for the external chip select signal CS EX to the application module See Table 23 Table 23 J19 EX SEL Shunt Status Function Affected Device 1 2 CS EX is decoded in the CSO memory space and is Application module located in the address range 400000h 7FFFFFh addressing 3 4 CS EX is decoded in the CS2 memory space and is Application module located in the address range A00000h A7FFFFh addressing 5 6 CS_EX is decoded in the CS2 memory space and is Application module located in the address range A80000h AFFFFFh addressing 7 8 CS_EX is decoded in the CS2 memory space and is Application module
41. Z80F92 Flash Module 66 APppendiX ia ias ass mou naq aa sabia a are din dek 75 General Array Logic Equations 75 U10 Address Decoder sis uya a asa teedii RN L ales J3 UlS Addr ss Decoder severa cirios a i d W n 78 Customer Feedback Pom 81 Table of Contents PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 UMO13907 1003 110 eZ80 Development Platform Block Diagram with eZ80F92 Flash Module 4 The eZ809 Development Platform 5 The eZ80F92 Flash Module 6 Basic eZ80 Development Platform Block Diagram 8 Physical Dimensions of the eZ80 Development Platform 9 eZ809 Development Platform Peripheral Bus Connector Pin Configuration JP1 lesse 11 eZ809 Development Platform I O Connector Pin Confeuraton JpiI eee 16 Trigger Pins J21 and Di 27 Embedded Modem Socket Interface J1 J5 and J9 28 Memory Map of the eZ809 Development Platform and eZ80F92 Flash Module 32 Physical Dimensions of the eZ80F92 Flash Module 45 eZ80F92 Flash Module Top Layer 46 eZ80F92 Flash Module Bottom Layer
42. a JJjJ rrr r r gg 33 Push Buttons se x5 casa sa eee EEN e adr tiipii 33 JUMPCLS gy n ere W e ek a ale ENEE ia 34 COMMCCIONS i22 Q k n ia aj W n Rd b n 40 Console vin iis erus Dre ter ended de od MM E HEE 41 Modem NEE 41 EE eet 41 DC Characteristics lt aaa a tott natia e 42 eZ80F92 Flash Module 44 Functional Description 44 Physical Dimensions 45 Operational Description 48 UMO13907 1003 PRELIMINARY Table of Contents vi eZ80F92 Development Kit User Manual 110 eZ80F92 Flash Module Memory 48 Reset Generator e aer e La Re es Re ME E ede 49 IrDA Transceiver uou reb EEN RR RU naa 49 DC Characteristics cis dr D sews e e 3X eR S ee 52 Flash Loader Utility oe ete ay DY TES 52 Mounting the Module 52 Changing the Power Supply Plug 53 EE 55 ZDI Target Interface Module s kk ekl a k ee eee 55 WAG Tu n sea dt marin A Pee eens 55 Application Module 55 LDS IL iz chart re a Rene Rede te ee dx k et eee Qu NON 57 Troubleshoot est Tt er iaa CR a eee RE EET CERA EEG RA 59 OVerVIeW iix EE mmm mm 59 Cannot Download Code 59 No Output on Console Pont 59 IrDA Port Not Working ei er e wem daa 60 Contacting ZiLOG Customer Support 60 Schematic Diagrams ssi a vedas eS e Y aed Ree de 61 eZ809 Development Platform 61 e
43. ce is a GAL22LV10 5JC ns tpd or equivalent with Package 28 pin PLCC module F92 em pal nDIS EM nEM EN AO PRELIMINARY if either of them is 0 Flash EN 0 8 h80 UM013907 1003 A1 A2 23 M AD A6 A7 nRD DCD nWR nMEMRQ nlIORQ nEM RD nEM WR nAN WR nCT WR nDIS ETH input nDIS nEM EN synthesis A0 synthesis Al synthesis A2 synthesis A3 synthesis A4 synthesis A5 synthesis A6 synthesis A7 synthesis nIORQ synthesis UM013907 1003 loc P4 loc P5 loc P6 loc P10 loc P11 loc P12 loc P13 loc P27 loc P26 loc P2 PRELIMINARY eZ80F92 Development Kit User Manual 110 EM synthesis loc P3 General Array Logic Equations 79 eZ80F92 Development Kit User Manual 80 110 nRD synthesis loc P7 ncs synthesis loc P25 CS3 for CS9800 nWR synthesis loc P9 nMEMRQ synthesis loc P16 output nEM RD synthesis loc P17 nEM WR synthesis loc P18 nCT WR synthesis loc P19 nAN WR synthesis loc P20 nDIS ETH synthesis loc P21 parameter anode 8 h00 parameter cathode 8 h01 parameter latch 8 h02 wire 7 0 address A7 A6 A5 A4 A3 A2 A1 A0 assign nEM WR nDIS_EM 1 nWR 0 nEM EN 0
44. e eZ809 Development Platform must align with pin 1 of JP1 on the eZ809 Development Platform Pin 1 of JP2 on the eZ80F92 Flash Module must align with pin 1 of JP2 on the eZ809 Development Platform etc eZ80F92 Flash Module PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Diipa 53 Changing the Power Supply Plug The universal 9VDC power supply offers three different plug configura tions and a tool that aids in removing one plug configuration to insert another as shown in Figure 15 Figure 15 9VDC Universal Power Supply Components To exchange one plug configuration for another perform the following steps 1 Place the tip of the removal tool into the round hole at the top of the current plug configuration 2 Press down to disengage the keeper tab and push the plug configura tion out of its slot 3 Select the plug configuration appropriate for your location and insert it into the slot formerly occupied by the previous plug configuration 4 Push the new plug configuration down until it snaps into place as indicated in Figure 16 UM013907 1003 PRELIMINARY Changing the Power Supply Plug 54 eZ80F92 Development Kit User Manual 110 eZ80F92 Flash Module Figure 16 Inserting a New Plug Configuration PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 55 ZPAKII ZPAKII is a debug tool used to develop and debug hardware and soft ware It is a networked device feat
45. ector Identification JP2 Diipa Pin Symbol Signal Direction Active Level eZ80F92 Signal 1 PB7 Bidirectional Yes 2 PB6 Bidirectional Yes 3 PB5 Bidirectional Yes 4 PB4 Bidirectional Yes 5 PB3 Bidirectional Yes 6 PB2 Bidirectional Yes 7 PB1 Bidirectional Yes 8 PBO Bidirectional Yes 9 GND 10 PC7 Bidirectional Yes 11 PC6 Bidirectional Yes 12 PC5 Bidirectional Yes 13 PC4 Bidirectional Yes 14 PC3 Bidirectional Yes 15 PC2 Bidirectional Yes 16 PC1 Bidirectional Yes 17 PC0 Bidirectional Yes 18 PD7 Bidirectional Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F92 device UM013907 1003 PRELIMINARY Operational Description 17 eZ80F92 Development Kit User Manual 18 ius Table 3 eZ80 Development Platform UO Connector Identification JP2 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 19 PD6 Bidirectional 20 GND 21 PD5 Bidirectional Yes 22 PD4 Bidirectional Yes 23 PD3 Bidirectional Yes 24 PD2 Bidirectional Yes 25 PD1 Bidirectional Yes 26 PDO Bidirectional Yes 27 TDO Input Yes 28 TDI ZDA Output Yes 29 GND 30 TRIGOUT Input High 31 TCK ZCL Output Yes 32 TMS Outpu
46. enable fifo 8bit N 1 stop enable IRDA Encode decode and Receiv enable bit Disable receive Output a byte to the uart0 port PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 110 DC Characteristics As different combinations of application modules are loaded onto the eZ809 Development Platform current requirements change Please see Table 26 on page 42 to reference current consumption values for these different module combinations A 0 1 Farad capacitor is provided on the eZ80F92 Flash Module as a short term battery backup for the RTC see the Schematic Diagrams on page 61 The part number of the capacitor made by Panasonic is EECSOHDV The capacitor is connected to RTC_VDD to provide power to the RTC when main power to the chip is removed it is also connected to the 3 3 V supply to the chip for recharging The RTC can operate down to 3 0 V it requires 10uA of current The keep alive time this capacitor can supply power to the RTC from 3 3 V to 3 0 V is approximately 3000 seconds or 50 minutes Flash Loader Utility The Flash Loader utility allows the user a convenient way to program on chip Flash memory Please refer to the External Flash Loader Product User Guide PUGO0016 for more details Mounting the Module When mounting the eZ80F92 Flash Module onto the eZ809 Development Platform check its orientation to the platform to ensure a correct fit Pin 1 of JP1 on th
47. ent Platform because the eZ80F92 Flash Module features the eZ80F92 microcontroller To mount an application module use the two male headers J6 and J8 Jumper J6 carries the General Purpose Input Output ports GPIO and jumper J8 carries memory and control signals To design an application module the user should be familiar with the architecture and features of the eZ80F92 Flash Module currently installed Tables 4 and 5 list the sig nals and functions related to each of these jumpers by pin Power and ground signals are omitted for the sake of simplicity Table 4 GPIO Connector J6 Signal Pin A Function Direction Notes SCL 5 12C Clock Bidirectional SDA 7 CC Data Bidirectional MOD DIS 9 Modem Disable Input If a shunt is installed between pins 6 and 9 the modem function on the eZ80 Development Platform is disabled MWAIT 13 Wait signal forthe Input CPU EM DO 15 Emulated Port A Bidirectional Bit 0 CS3 17 Chip Select 3 of Output This signal is also present on the CPU the J8 EM D 7 1 21 23 25 Emulated Port A Bidirectional 27 29 31 Bit 7 1 33 Reserved 35 Note All of the signals are driven directly by the CPU UM013907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual 22 110 Table 4 GPIO Connector J6 Continued Signal Pin Function Direction Notes PC 7 0 39 41 43 Port C Bit 7 0 Bidirectional 45 47 49 51 53 ID 2 0 6 8 10 eZ809 Output D
48. evelopment Platform ID CON DIS 12 Console Disable Input If a shunt is installed between pins 12 and 14 the Console function on the eZ80 Development Platform is disabled Reserved 16 18 PD 7 0 22 24 26 Port D Bit 7 0 Bidirectional 28 30 32 34 36 PB 7 0 40 42 44 Port B Bit 7 0 Bidirectional 46 48 50 52 54 Note All of the signals are driven directly by the CPU eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual ara 23 Table 5 CPU Bus Connector J8 Signal Pin Function Direction A 0 7 3 10 Address Bus Low Byte Output A 8 15 13 20 Address Bus High Byte Output A 16 23 23 30 Address Bus Upper Byte Output RD 33 Read Signal Output RESET 35 Push Button Reset Output BUSACK 37 CPU Bus Acknowledge Signal Output NMI 39 Nonmaskable Interrupt Input D 0 7 43 50 Data Bus Bidirectional CS 0 3 53 56 Chip Selects MREQ 57 Memory Request Output WR 34 WRITE Signal Output INSTRD 36 Instruction Fetch Output BUSREQ 38 CPU Bus Request signal PHI 40 Clock output of the CPU Output Note All of the signals except BUSACK and INSTRD are driven by low voltage CMOS technology LVC drivers I O Functionality The eZ80190 microprocessor features General Purpose I O functionality at Port A The eZ80F92 device does not incorporate this Port A feature The eZ809 Development Platform provides additional I O functionality featurin
49. g GPIO for devices without Port A an LED matrix a modem reset and two user triggers UMO13907 1003 PRELIMINARY Operational Description 24 eZ80F92 Development Kit User Manual Li k O These functions are memory mapped with an address decoder based on the Generic Array Logic GAL221V10D U15 device manufactured by Lattice Semiconductor and a bidirectional latch U16 Additionally U15 is used to decode addresses for access to the 7x5 LED matrix Table 6 lists the memory map addresses to registers that allow access to the above functions The register at address 800000h controls GPIO Port A Output Control and LED Anode register functions The register at address 800001h controls the register functions for the LED cathode modem reset and user triggers Address 800002h controls GPIO Port A data Table 6 LED and Port Emulation Addresses Address Register Function Access 800000h LED Anode GPIO Port output control WR 800001h LED Cathode Modem Trig WR 800002h GPIO Data RD WR Port A Emulation GPIO Port A is emulated with the use of the GPIO Output Control Regis ter and the GPIO Data Register If bit 7 in the GPIO Output Control Reg ister is 1 all of the lines on GPIO Port A are configured as input ports If this bit is 0 all of the lines on Port A are configured as output ports Table 7 lists the multiple functions of the register Table 7 LED Anode GPIO Port A Output Control Register Bit Function 7 6 5 4
50. generating a reset pulse with a duration of 200ms if the power supply drops below 2 93 V This reset pulse ensures that the board always starts in a defined condition The RESET pin on the I O connector reflects the status of the RESET line It is a bidirectional pin for resetting external peripheral com ponents or for resetting the eZ80F92 Development Kit with a low imped ance output e g a 100 Ohm push button IrDA Transceiver An onboard IrDA transceiver ZiLOG ZHX1810 is connected to PDO TX PD1 RX and PD2 Shutdown IR_SD The IrDA transceiver is of the LED type 870nm Class 1 The IrDA transceiver is accessible via the IrDA controller attached to UARTO on the eZ80F92 device The UARTO console and the IrDA trans ceiver cannot be used simultaneously To use the UARTO for console or to save power the transceiver can be disabled by the software or by an off board signal when using the proper jumper selection The transceiver is disabled by setting PD2 IR_SD High or by pulling the DIS_IRDA pin on the I O connector Low The shutdown feature is used for power savings To enable the IrDA trans ceiver DIS_IRDA is left floating and PD2 is set to Low The eZ80F92 Flash Module contains a ZiLOG IrDA transceiver that is connected to the UARTO port This port can be used as a wireless connec tion into the eZ80F92 Flash Module The UARTO can connect to a stan dard RS232 port or it can be configured to control the IrDA transceiver U
51. he correct label is EN FLASH Table 16 J11 EN FLASH Off Chip Shunt Status Function Affected Device IN All access to external Flash memory on the External Flash memory on the eZ80190 Module is enabled eZ80190 Module OUT All access to external Flash memory on the External Flash memory on the eZ80190 Module is disabled eZ80190 Module Note As shipped from the factory external Flash memory is not installed Jumper J12 The J12 jumper connection controls the selection of a 5 V or 3 VDC power supply to the embedded modem if an embedded modem is used See Table 17 Table 17 J12 5VDC 3 3VDC for an Embedded Modem Shunt Status Function Affected Device 1 2 5VDC is provided to power the embedded modem Embedded modem 2 3 3 3VDC is provided to power the embedded modem Embedded modem eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 37 Jumper J14 The J14 jumper connection controls the polarity of the Ring Indicator See Table 18 Table 18 J14 RI Shunt Status Function Affected Device 1 2 The Ring Indicator for UART1 is inverted UART 1 2 3 The Ring Indicator for UART1 is not inverted UART 1 Jumper J15 The J15 jumper connection controls the selection RS485 circuit along with UARTO When the shunt is placed the RS485 circuit is enabled See Table 19 RS485 functionality will be available in future eZ80 devices Table 19 J15 RS485 1 EN Shunt
52. he eZ80F92 Flash Module features 512KB of fast SRAM Access speed is typically 50ns allowing zero wait state operation at 20 MHz With the CPU at 20MHz SRAM can be accessed with zero wait states in eZ80 mode CS1_CTL chip select CS1 can be set to 08h no wait states Flash Memory The eZ80F92 Flash Module features 128 KB of Flash memory This on chip memory can be programmed a single byte at a time or in bursts of up to 128 bytes Write operations can be performed using either memory or I O instructions Erasing bytes in Flash memory returns them to a value of FFh Both the MASS ERASE and PAGE ERASE operations are self timed by the Flash controller leaving the CPU free to execute other oper ations in parallel Upon power up the on chip Flash memory is located in the address range 000000h 01FFFFh Four wait states are programmed in Flash control register F8h On chip Flash memory is prioritized over all external Chip Selects can be enabled or disabled power on enabled and can be programmed within any 128KB address space in the 16MB address range The eZ80F92 Flash Module features the following memory configura tions eZ80F92 Flash Module PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 49 On chip SRAM 8KB Off chip SRAM 512KB On chip Flash 128 KB Reset Generator The onboard Reset Generator Chip is connected to the eZ80F92 Reset input pin It performs reliable Power On Reset functions
53. inal for connecting an external modem if used with the eZ80F92 Development Kit RS485 functionality will be available in future eZ809 devices IC Devices The two IC devices on the eZ809 Development Platform are the U2 EEPROM and the U13 Configuration register The EEPROM provides 16KB of memory The Configuration register provides access to control the configuration of an application specific function at the Application Module Interface Neither device is utilized by the eZ80F92 Development Kit software The user is free to develop proprietary software for these two devices The addresses for accessing these devices are listed in Table 25 Table 25 12C Addresses Device Bit 7 6 5 4 3 2 1 0 EEPROM U10 1 0 1 0 0 A1 AO RAW Configuration Register U13 1 0 0 1 1 1 0 RW Note EEPROM address bits AO and A1 are configured for Os UMO13907 1003 PRELIMINARY 12C Devices eZ80F92 Development Kit User Manual 110 DC Characteristics Understanding proper DC current requirements for the eZ809 Develop ment Platform when application modules are plugged into it is very important for developing applications This section provides an estimate of the average current requirement when different combinations of these application modules are plugged in to the eZ809 Development Platform The receiver supply current is 90 150uA and the transmitter supply cur rent is 260mA when the LED is active The measurements of current that are shown
54. ity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F92 device 3 External capacitive loads on RD WR IORQ MREQ DO D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ809 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UMO13907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual Z 16 Diog UO Connector Figure 7 illustrates the pin layout of the I O Connector in the 50 pin header located at position JP2 on the eZ80 Development Platform Table 3 describes the pins and their functions PB7 PB5 PB3 PB1 GND_EXT PC6 PC4 PC2 PCO PD6 PD5 PD3 PD1 TDO GND_EXT TCK RTC_VDD IICSCL IICSDA FLASHWE CS3 RESET V3 3 EXT HALT SLP V3 3 EXT TDI TRIGOUT TMS EZ80CLK GND EXT DIS IRDA WAIT GND EXT NMI HEADER 25X2 IDC50 Figure 7 eZ80 Development Platform UO Connector Pin Configuration JP2 eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual Table 3 eZ80 Development Platform UO Conn
55. m 2 of 5 PRELIMINARY Schematic Diagrams A 23 0 gt oro 2L MEM CEN1 MEM CEN2 MEM CEN3 MEM CEN4 UM013907 1003 REESE CE OE MEM CEN e A18 NC VDDO gt VgD NC VDD1 ce ci 0 1uF vsso 19 Eh VSS1 AS7C34096 A 23 0 MEM CEN2 1 Lo ce RD WE GN RI 1d oe vsso 19 SHO 6 D 7 0 U18 DO Do D1 d D2 D3 D3 D4 D5 D6 E D7 vopo 2 HN VDD1 C10 Our vss1 28 AS7C34096 A 23 0 D 7 0 U19 DO Do LZ Di D1 gt D2 D3 D4 x D5 gt De gt D7 A18 NC VDDO 2 veo NC VDD1 MEM CEN3 Gic c11 3 13 WE 0 1uF EE 31d oE vsso H9 9 VSS1 AS7C34096 GND usc z TC74LVC08 4 o 1 10 sd U9B TC74LVC08 4 6 a M Uap z TC74LVC08 32 L 43 M Figure 19 ez80 Development Platform Schematic Diagram 3 of 5 PRELIMINARY eZ80F92 Development Kit User Manual 63 ZLOG D 7 0 A 23 0 U20 DO DO T D1 2 D2 5 D3 3 D4 e D5 e D6 H D7 A18 NC VDDO 57 RD NC VDD1 MEM_CEN4 6 C12 X Si WE 0 1uF RD OE vsso 12 gd Sy VSS1 AS7C34096 Schematic Diagrams eZ80F92 Development Kit User Manual
56. n chip FFFFFFh SRAM FFE000h Available Address Space DFFFFFh SRAM Memory up to 2 MB CS1 Platform Expansion SRAM Memory up to 4 MB CS2 80FFFFh 800000h 7FFFFFh Off chip Expansion Module Flash memory Flash Memory up to 4 MB 400000h 3FFFFFh Module Expansion Flash Memory up to 4 MB Off chip 120000h Flash memory 11FFFFh Up to 4 MB Flash Memory 020000h On chip 01FFFFh Flash memory 000000h Figure 10 Memory Map of the eZ80 Development Platform and eZ80F92 Flash Module CSO 8 MB eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 33 LEDs As stated earlier LEDs D1 D2 D3 and D4 function as status indicators for an optional modem This section describes each LED and the LED matrix device Data Carrier Detect The Data Carrier Detect DCD signal at D1 indicates that a good carrier signal is being received from the remote modem RX The RX signal at D2 indicates that data is received from the modem Data Terminal Ready The Data Terminal Ready DTR signal at D3 informs the modem that the PC is ready TX The TX signal at D4 indicates that data is transmitted to the modem Push Buttons The eZ80 Development Platform provides user controls in the form of push buttons These push buttons serve as input devices to the eZ80F92 microcontroller The programmer can use them as necessary for applica tion development All push buttons are connected
57. nd the eZ80F92 Flash Module This arrangement provides a full development platform when using both boards It can also provide a smaller sized reference platform with the eZ80F92 Flash Mod ule as a stand alone development tool The eZ80 Development Platform is designed to accept a number of application specific modules and Z8 and eZ809 based add on modules including the eZ80F92 Flash Module which features a real time clock an IrDA transceiver and the eZ80F92 microcontroller The eZ80 Development Platform together with its plugged in eZ80F92 Flash Module can operate in stand alone mode with Flash memory or interface via the ZPAKII emulator to a host PC running ZiLOG Devel oper Studio II Integrated Development Environment ZDS IDE software The address bus data bus and all eZ80F92 Flash Module control signals are buffered on the eZ809 Development Platform to provide sufficient drive capability UMO13907 1003 PRELIMINARY ez80 Development Platform Overview eZ80F92 Development Kit User Manual Z 4 Diog A block diagram of the eZ80 Development Platform and the eZ80F92 Flash Module is shown in Figure 1 Peripheral Device Signals Address Bus eZ80 Flash MPU Module Data Bus Interface RS232 0 Console SRAM EK 512 KB up to 2 MB Battery amp RS232 1 Oscillator Modem for RTC Transceiver j GPIO and Address Decoder Application Module Headers Figure 1 eZ80 Developmen
58. nificance within the LED matrix It is used for GPIO as a Port A control bit Table 9 indicates the multiple register functions of the LED cathode modem and triggers This table shows the bit configuration for each cath ode bit Bits 5 6 and 7 do not carry any significance within the LED matrix These three bits are control bits for the modem reset Trig and Trig2 functions respectively Table 9 Bit Access to the LED Cathode Modem and Triggers Bit Function 7 6 5 4 3 2 1 0 Cathode Row 5 x Cathode Row 4 x Cathode Row 3 x Cathode Row 2 x Cathode Row 1 x Modem RST x Trig 1 x Trig 2 x eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 27 An LED display sample program is shipped with the eZ80F92 Develop ment Kit Please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 or to the Tutorial section in the ZiLOG Developer Studio eZ80Acclaim User Manual UM0144 Modem Reset The Modem Reset signal MRESET is used to reset an optional socket modem This signal is controlled by bit 5 in the register shown in Table 9 The MRESET signal is available at the embedded modem socket interface J9 Pin 1 Setting this bit Low places the optional socket modem into a reset state The user must pull this bit High again to enable the socket modem Reference the appropriate documentation for the socket modem to reset timing requirements
59. nnection controls Port A emulation mode and communi cation with the 7x5 LED When the shunt is placed Port A emulation is disabled See Table 14 Shunt Status Function In Application Module Hardware Disabled Table 14 J3 DIS EM Affected Device Communication with 7x5 LED and Port emulation circuit is disabled Out Application Module Hardware Enabled Jumper J7 Communication with 7x5 LED and Port A emulation circuit is enabled The J7 jumper connection controls Flash boot loader programming When the shunt is placed overwriting of the Flash boot loader program is enabled See Table 15 Table 15 J7 FlashWE Off Chip Shunt Status Function Affected Device Out The Flash boot sector of the eZ80F92 Flash boot sector of the eZ80F92 Flash Flash Module is write protected Module In The Flash boot sector of the eZ80F92 Flash boot sector of the eZ80F92 Flash Flash Module is enabled for writing or Module overwriting Note As shipped from the factory external Flash memory is not installed UMO13907 1003 PRELIMINARY Operational Description 36 eZ80F92 Development Kit User Manual 110 Jumper J11 The J11 jumper connection controls access to the off chip Flash memory device When the shunt is placed access to this Flash device is enabled See Table 16 Note The silk screened label on the eZ80 Development Platform for jumper J11 is incorrect Currently it reads DIS FLASH T
60. perational Description 20 eZ80F92 Development Kit User Manual 110 y Note These three inputs are Enable Flash EN_FLASH Flash Write Enable FlashWE Disable IrDA DIS_IrDA These three signals are described below Enable Flash When active Low the EN_FLASH input signal enables the Flash chip on the eZ80F92 Flash Module Flash Write Enable When active Low the FlashWE input signal enables Write operations on the Flash boot block of the eZ80F92 Flash Module Disable IrDA When the DIS_IrDA input signal is pulled Low the IrDA transceiver located on the eZ80F92 Flash Module is disabled As a result UARTO can be used with the RS232 or the RS485 interfaces on the eZ809 Devel opment Platform These inputs are only used if external Flash is present on the eZ80F92 Flash Module as shipped from the factory external Flash is not installed Application Module Interface An Application Module Interface is provided to allow the user to add an application specific module to the eZ809 Development Platform ZiLOG s Thermostat Application Module not provided in the Kit is an example application specific module that demonstrates an HVAC control system Implementing an application module with the Application Mod ule Interface requires that the eZ80F92 Flash Module also be mounted on eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 21 the eZ809 Developm
61. roubleshooting PRELIMINARY UMO13907 1003 Schematic Diagrams eZ80 Development Platform Figures 17 through 21 diagram the layout of the eZ809 Development Platform or MODEM s AGND 2 MOD DIS vcc DO NOT USE J6 17 AND J6 35 Ut MA 214 ya vcc MA2 eA Y2 9V D 1 2 MAS g 43 Mi evpc gt 34 ln 2 MAL M Y4 SCL 5 6 D1 2 1D_2 MAS yg 5 Ys SDA ND 7 8 i 1071 MAS 13 A6 Y6 9 1 ID o MAT AT Y MoD DIS lt 11 42 ND C N DIS L ig Ya MWAIT 13 14 EM DO cS 15 16 Co 10E vcc GND 17 18 GND DIS_ETH gt 20E GND 19 20 EM D7 21 22 5 PD7 RIO EM D6 28 24 SE po EM D 25 26 SE EM D4 27 28 PD4 DTRO EM D3 29 30 gt gt PD3_CTSO W Au o EM_D2 31 32 lt PD2_RTSO MATO A2 Y2 EM_D1 33 34 gt PD1_RXDO MATT a vs GND 35 36 GND PD0_TXD0 MATZ 11 44 Y4 37 38 PB7 MOSI MATS 13 5 ya PC7 RI 39 40 PBE MISO MATA 15 6 Y6 Pc6_DGD1 gt 4 242 PESTS O MATS 17 A Y7 PCR DSRK 43 44 PBI TA O A8 Ya PC4 DTR12 45 46 PB3 SCK R2 pc EISE 47 48 gt Mk al 10E VCC PC2_RTS1 gt 49 50 PBI TT RGPB2 SS 2
62. t High Yes 33 RTC_Vpp 34 EZ80CLK Input Yes 35 SCL Bidirectional Yes 36 GND Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 2 The Power and Ground nets are connected directly to the eZ80F92 device eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit T User Manual aria 19 Table 3 eZ80 Development Platform UO Connector Identification JP2 Continued Pin Symbol Signal Direction Active Level eZ80F92 Signal 37 SDA Bidirectional Yes 38 GND 39 FlashWE Output Low No 40 GND 41 CS3 Input Low Yes 42 DIS_IrDA Output Low No 43 RESET Bidirectional Low Yes 44 WAIT Output Pull Up 10KQ Low Yes 45 Vpp 46 GND 47 HALT SLP Input Low Yes 48 NMI Output Low Yes 49 Vpp 50 Reserved Notes For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80F92 Module Schematics on pages 66 through 68 The Power and Ground nets are connected directly to the eZ80F92 device Almost all of the connectors signals are received directly from the CPU Three input signals in particular offer options to the application devel oper by disabling certain functions of the eZ80F92 Flash Module UMO13907 1003 PRELIMINARY O
63. t Platform Block Diagram with eZ80F92 Flash Module Introduction PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual j y 4 j 110 5 Figure 2 is a photographic representation of the eZ809 Development Plat form segmented into its key blocks as shown in the legend for the figure Note Key to blocks A E A Power and serial communications D Application module interfaces B eZ80F92 Flash Module interface E GPIO and LED with Address Decoder C Debug interface Figure 2 The eZ80 Development Platform UMO013907 1003 PRELIMINARY ez80 Development Platform Overview eZ80F92 Development Kit User Manual 6 110 Figure 3 is a photographic representation of the eZ80F92 Flash Module segmented into its key blocks as shown in the legend for the figure Note Key to blocks A C A eZ80F92 Flash Module interfaces B CPU C IrDA transceiver Figure 3 The eZ80F92 Flash Module The structures of the eZ809 Development Platform and the eZ80F92 Flash Module are illustrated in the Schematic Diagrams starting on page 61 Introduction PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 7 eZ80 Development Platform This section describes the eZ80 Development Platform hardware its key components and its interfaces including detailed programmer interface information such as memory maps register definitions and interrupt usage Functional Description The eZ80 Development
64. t number SC56H 1 Either the 3 3 V or the 5 0 V version of the modem can be used However jumper J12 should be configured accordingly see Table 17 Information about this modem and its interface is available in the SocketModem data sheet from www multitech com eZ80 Development Platform Memory Memory space on the eZ80 Development Platform consists of onboard SRAM and additional SRAM footprints Onboard SRAM The eZ80 Development Platform features 512KB SRAM at U20 This SRAM provides the basic memory requirement for small applications development This SRAM is in the address range B80000h BFFFFFh With the 512 KB of SRAM on the eZ80F92 Flash Module this addressing structure provides 1 MB of contiguous SRAM for immediate use Chip Select 2 is used to access the 512KB of SRAM on the eZ80 Develop ment Platform Additional SRAM The amount of eZ80 Development Platform memory can be extended if required by adding SRAM devices U19 U18 and U17 provide this capa bility However the user should be aware that additional SRAM must be installed in the following order 1 U19 address range B00000h B7FFFFh eZ80 Development Platform PRELIMINARY UMO13907 1003 eZ80F92 Development Kit User Manual 110 31 2 U18 address range A80000h AFFFFFh 3 U17 address range A00000h A7FFFFh If SRAM memory is installed in a different order than the above sequence SRAM will not be contiguous unless the user is able
65. the eZ80F92 Flash MCU Module the eZ80F92 device on the module starts running code from this Flash memory area This code enables the Console port with settings of 577 6kbps 8 N 1 The Console checks the Receive buffer If a space character is received on the Console port the Flash Loader utility is enabled and a boot message should be displayed on your connected device If no message is displayed check the following Jumper J2 must be ON IrDA is disabled On Connector J6 the jumper must be removed from pins 6 and 9 pin names con dis and GND UMO13907 1003 PRELIMINARY Troubleshooting eZ80F92 Development Kit User Manual 60 110 IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80F92 Flash Module make sure the hardware is set up as follows Jumper J2 must be OFF to enable the control gate that drives the IrDA device Set port pin PD2 Low When this port pin and Jumper J2 are turned OFF the IrDA device is enabled e Install a jumper on connector J6 across pin names con dis and GND to disable the console serial port driver Contacting ZiLOG Customer Support For additional troubleshooting solutions see ZDS Online Help For valuable information about hardware and software development tools visit ZILOG Customer Support online Download the latest released ver sion of ZiLOG Developer Studio Get the latest software updates from ZiLOG as soon as they are available T
66. tic Diagram 2 of 9 100 Pin QFP eZ80F92 Device UMO13907 1003 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual AM zi L k D 7 ele No 23 Alu A19 A20 A21 A22 A23 RKI not used here CS1 Sek RD WR WR A18 AD A16 A A15 AZ 7 ATA A3 A13 CS1 RD DO D7 Di S D6 Z9 0 L D2 D5 D3 DZ WR AT A AB AS A10 AG A7 AA A5 AT B 512kx8 SRAM T SOJ36 400 c7 v3 3 74LVC04 SO U2E U2F 1001 VDD ir vss 74LVCOAISO 7ALVCO4 SO GND Figure 24 Schematic Diagram 3 of 9 36 Pin SRAM Device UM013907 1003 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual AP TiLog Intel Type DFLASHO DFLASH2 DFLASH4 4 DFLASH6 a5 DFLASH7 OCH OH OD IGO BY SI IS un pm nu R1 10K CSFLASH FLASHWE 74LVC04 SO A20 A21 used for Pin37 N C 16 32Mbit Flash for 4Mbit Flashes MT28F008B3VG TSOP40 20MM U3 IS NOT POPULATED T 100nF D 7 eh A o 23 LL A22 A23 not used here VDD CSFLASH CSFLASH RD yes RD WR WR RESFLASH RESRLASH GND FLASHWE Ian _ Note Must be pulled low externally for programming Figure 25 Schematic Diagram 4 of 9 NOR Flash Device UM013907 1003 PRELIMINARY Schematic Diagrams eZ80F92 Development Kit User Manual V3 3 Z 70 TiLog VDD R19 vss L o d C o col lo o A d 10k MR colo C9 L T TO
67. to change the address decoder U10 Memory access decoding is performed by this address decoder implemented in the Generic Array Logic device GAL22LV 10D U10 On Chip SRAM The eZ80F92 device on the eZ80F92 Flash Module contains 8 KB of on chip SRAM Upon power up this SRAM is enabled and mapped to the top 8KB of memory address space Using the RAM Address Register this 8KB memory can be mapped to the top of any 64 KB block It can also be disabled Please see the eZ80F92 eZ80F92 Product Specification PS0153 for more information Flash Memory The eZ80F92 Development Kit allows off chip Flash memories between 1 MB and 4MB This Flash memory is entirely located on the eZ80F92 Flash Module in footprint only as shipped from the factory external Flash is not installed Memory Map A memory map of the eZ809 CPU is illustrated in Figure 10 Flash mem ory and SRAM on the eZ80F92 Flash Module are addressed when CSO and CS are active Low SRAM on the eZ80 Development Platform is addressed when CS2 is active Low The location of on chip SRAM is programmable by setting the RAM address upper byte register The upper 8 KB of any 64 KB memory page can be selected Addresses to enabled on chip memories assume priority over all chip selects Please refer to the eZ80F92 eZ80F92 Product Speci fication PS0153 for more details UMO13907 1003 PRELIMINARY Operational Description eZ80F92 Development Kit User Manual Z 32 110 O
68. uring an Ethernet interface and an RS232 console port ZPAKII is shipped with a preconfigured IP address that can be changed to suit the user on a local network For more informa tion about using and configuring ZPAKII please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0020 and the ZPAKII Product User Guide PUGO0015 ZDI Target Interface Module JTAG The ZDI Target Interface Module provides a physical interface between ZPAKII and the eZ80 Development Platform The TIM module supports ZDI functions For more information on using the TIM module or ZDI please refer to the eZ80Acclaim Development Kits Quick Start Guide QS0019 the eZ80F92 Ethernet Module Product Specification PS0186 and the eZ80F92 Flash Module Product Specification PS0189 Connector P1 is the JTAG connector on the eZ80 Development Plat form JTAG will be supported in the next offering of eZ809 products Application Modules ZiLOG offers the Thermostat Application module which can be used for evaluating and developing process control and simple I O applications The Thermostat Application module is equipped with an LCD display that can be used to display process control and other physical parameters For UMO13907 1003 PRELIMINARY ZPAKII 56 eZ80F92 Development Kit User Manual 110 additional reading about the Thermostat application please see the Java Thermostat Demo Application Note AN0104 on zilog com ZPAKII PREL

eZ80F92 Development Kit User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents