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AT-MIO-16D User Manual

1. 1 31 9 9 Bus Regs fa fe ste wemme 0 71 ENERENEREENEIITIILIOIT nae Setting of Contro Word The control register is composed of 7 bit latch circuit and 1 bit flag as shown below Group A Control Bits Group 8 Control Bits Definition of input Output of low order 4 bits of port nput Definition of input output of 8 bits of 9 Output port B Mode definition Mode 0 of group B 1 Mode 1 Definition of input output of high order 12 io 4 bits of port C Definition of input output of Sbitsof 402 Output port A nput Mode definition of group A Control word identification flag Be sure to set 1 for the control word to define a mode and input output When set to 0 it becomes the control word for bit set resat Precaution for mode selection Bit Set Reset Function The output registers for ports A and C are cleared When port C is defined as output port it is possible to each time data is written in the command register to set set output to 1 or reset set output to 0 any the mode is changed but the port B state is un one of 8 bits without affecting other bits as shown defined next page 337 AT MIO 16D User Manual 10 National Instruments Corporation Appendix F a O MSM82C55A 2RS GS VJS Don t Care Control word identification fl
2. 3 17 RTSI Switch Control Pattern ati te e adea taie 4 75 C ntrol Word tes Coreen AETS 4 79 Calibration Trimpot Location 1 5 2 AT MIO 16D 16 I O Connector eere B 1 AT MIO 16D DIO 24 I O Connector eene C 1 AT MIO 16D DO CODBOEIDOE mc fete D 1 Tables Bus Interface Factory PRO gs 2 1 Default Settings of Other National Instruments Products for the PC 2 3 Switch Settings with Corresponding Base I O Address and Base I O Address POAC ade 2 5 DMA Channels for the 16 2 4 2 6 Analog V O Jumper Setting S ni sen ec na tga ats 2 9 Input Configurations Available for the 16 2 10 Configurations for Input Range and Input Polarity eese 2 13 Actual Range and Measurement Precision Versus Input Range Selection E NE CETTE 2 14 Configurations for RTSI Bus Clock Selection eese 2 19 Recommended Input Configurations for Ground Referenced and Floating Sienal SOUECEN doe leid SUR Lacs 2 27 Port Signal oeil orate etate stes qat 2 45 AT MIO 16D Maximum Recommended Data A
3. 4 s 1 0 MSM82C55A 2RS GS vJS m 2 Mode 1 Strobe input output operation In mode 1 the strobe interrupt and other control signals are used when input output operations are made from a specified port This mode is available for both groups A and B In group A at this time port is used as the data line and port C as the con trol signal Following is a deserption of the input operation in mode 1 STB Strobe input When this signal is low level the data output from terminal to port is fetched into the internal latch of the port This can be made independent from the CPU and the data is not output to the data bus until the RD signal arrives from the CPU IBF Input buffer full fiag output This is the response signal for the STB This signal when tumed to high level indicates that data is fetched into the input latch This signal turns to high level at the falling edge of STB and to low level at the rising edge of RD INTR interrupt request output This is the interrupt request signal for the CPU of the data fetched into the input latch It is in dicated by high level only when the intemal INTE flip flop is set This signal turns to high level at the rising edge of the STB IBF 1 at this time Mode 1 input Nots Aithough belonging to group B PC operates as the control signal of group functionally and low level at the falling edge of the RD when the INTE is se
4. 4 80 Mode 0 Programming Example 4 81 Mode 1S trobed euo oec pea baee sedie iens 4 82 Mode 1 Input Programming Example ss 4 84 Mod 1 Str ob d e ux 4 84 Mode 1 Output Programming 4 86 Mode 2 Bidirectionial eerte di quss 4 87 Mode 2 Programming Example eene 4 88 Single Bit SCURESEL Feature eee eit ies o ede vd edis deco Uber que 4 80 Interrupt Programming Examples esee 4 89 DIO 24 Interrupt Handlifig 55 e eter eed 4 90 Chapter 5 Calibration Procedures ee S Hu e te 5 1 Calibration Equipment Req irermenfs o oo sod ed ma dace Pestle 5 1 e Osce soie ade beni s dis irse Maleate ire tU s 5 2 Analog Input Calibration ierat Deed dosis S 5 3 Board e Ese 5 4 Bipolar Input Calibration 5 4 Unipolar Input Calibration 5 5 Analog Output Calibrations o dae onte dle dat Gens 5 6 Ones ue ati OM RERA 5 7 Bipolar Output Calibration Procedure
5. 331 AT MIO 16D User Manual F 4 National Instruments Corporation Appendix F Oki MSM82C55A Data Sheet 2 1 0 MSM82C55A 2RS GS VJS AC CHARACTERISTICS 4 5 to 55V Ta 40 to 80 C 5 82 55 2 sre Tm ue pee tan m Time of aero tothe ring oie of ma 0 ame 6 Delay Time from the falling edge of RD to the output of defined data Delay Time from the rising edge of RD to the 75 floating of data bus Time from the rising edge of RD or WR to the next falling edge of RD or WA Setup Time of address before the falling edge of WA uw 9 ns Hold Tie of dren the rng ee wA 20 we ww 15 oa REN Time of Holt Time of bus data after the rising edge of WR data after the rising Holt Time of bus data after the rising edge of WR of WR Delay Time from the rising edge of WR to the output of defined data m Time of port data before the falling edge of bw Tine of por ae tert wav ot RD wn 0 te we e Setup Time of port data before the rising edge of ee STB Hold Time of port data after the rising edge of STB Hold Time of port data after the rising edge of STB 50 ms Delay Time from the falling edge of ACK to the output of defined data Delay Time from the rising edge of ACK to the floating of port Po
6. eae A 6 Storage Environment RNC A 6 Appendix B MIO I6 I O COUn6GlOLr i rr ree ree a orte te B 1 MIO 16 Signal Connection 1 B 2 Appendix C DIO 24 I O C 1 DIO 24 Signal Connection Descriptions eese enne C 2 Appendix D 16 VO Connector 222 2 2 20 0000000000080080000000000000044 D 1 Appendix E AMD Am9513A Data SIMCOE c e Itn i Appendix F Oki MSM82C55A Data SDegb oen tte Beak els ed F 1 Appendix G Customer Communication 7 eese G 1 Ille X oe curtes oct ote Index 1 National Instruments Corporation xiii AT MIO 16D User Manual Contents Figures Figure 1 1 AT MIO 16D Interface 2 2 2 14 1 1 2 Figure 1 2 XT MIO 16D Cable Assembly eio tope ucl 1 6 Figure 2 l Parts Locator Dideram i ee a Bed 2 2 Figure 2 2 Example Base I O Address Switch Settings eese 2 4 Figure 2 3 Jumper Settings for DMA Channels 6 and 7 Factory Setting 2 6 Figure 2 4 Jumper Settings for DMA Channel 6 Only eee 2 6 Figure 2 5 Jumper Settings f
7. 10 V 5 V range V diff max 5 V AT MIO 16D User Manual 2 32 National Instruments Corporation Chapter 2 Configuration and Installation For example for a differential voltage as large as 20 mV and a gain of 500 the largest common mode voltage that can be rejected is 7 V However if the differential signal is 10 mV with a gain of 500 9 5 V common mode voltage can be rejected The common mode voltage is measured with respect to the AT MIO 16D ground and can be calculated by the following formula Vta Vem actual 2 where V is the signal at the positive input of the instrumentation amplifier and V is the signal at the negative input of the instrumentation amplifier If the input signal common mode range exceeds 7 V with respect to the AT MIO 16D ground you need to limit the amount of floating that occurs between the signal ground and the AT MIO 16D ground Analog Output Signal Connections Pins 20 through 23 of the MIO 16 I O connector are analog output signal pins Pins 20 and 21 are OUT and DAC1 OUT signal pins DACO OUT is the voltage output signal for analog output channel 0 DACI OUT is the voltage output signal for analog output channel 1 Pin 22 EXTREF is the external reference input for both analog output channels You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be u
8. 4 15 Analog Output Register GrOUpoii s editis or tess ae ess tal de oa a cs petas 4 16 DAC REGIS aute Mace dea cha to ed 4 17 DACT Registe 4 18 INT2CER RE IST eda ott los Saat tat 4 19 Analog Input Register 4 20 M x Counter bs ta A Dee 4 21 Mux Guam INC SIS LER ioc Mei e b 4 22 A D FIFRO Resister terit jiu 4 24 DNIA TCINTF Clear 4 25 Am9513A Counter Timer Register Group eese nennen 4 26 Am9513A Data 4 27 Am9513A Command iae i edi det 4 28 Am9o5T3N Status Register 4 29 MIO 16 Digital I O Register 4 30 MIO 16 Digital Input 4 31 MIO 16 Digital Output Registers canines 4 32 The REST Switch Register CITOUD ee ort iocos e sesso to oar 4 33 RRS ES Witch Shit Regi Stet as 4 34 REST Switch Strobe 1 te tree ror teo o ponti etie 4 35 DIO 24 R sister GIFOUD eot ad poder tae 4 36 DIO 24 POR PA Reglsteoss ee
9. National Instruments Corporation 2 11 AT MIO 16D User Manual Configuration and Installation Chapter 2 Considerations in using the ground referenced single ended analog configuration are discussed in the Signal Connections section later in this chapter Figure 2 28 shows a schematic diagram of this configuration NRSE Analog Input 16 Channels NRSE analog input means that all input signals are referenced to the same common mode voltage but that this common mode voltage is allowed to float with respect to the analog ground of the AT MIO 16D board This common mode voltage is subsequently subtracted by the input instrumentation amplifier This configuration is useful when measuring ground referenced signal sources See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 16D can measure 16 different analog input signals You select the NRSE analog input configuration by setting jumpers W6 and W9 as follows W6 is tied into the negative input of the instrumentation amplifier C E Jumperis placed in standby position Jumper can be discarded H Multiplexer outputs are tied together into the positive input of the instrumentation amplifier W9 B C Multiplexer control is configured for 16 input channels This configuration is shown in Figure 2 11 Figure 2 11 NRSE Analog Input Configuration Considerations in using the NRSE con
10. Read High to Read Low Read Recovery Time o 77 21 190 LIRHSH Read High to CS High RHWL Read High to Write Low Read Recovery Tima 1 9 TRLOV Read Low to Data Out Vaid TRLOX Read Low to Data Bus Driven Data Bus Dre Time zi 29 TRLRH Read Low to Read High Head Puise Duration Note 12 19 TSURL CS Low 0 Read Low LI LTStwH CS Low to Write High Note i2 TWHAX Write High to C D Dont caa O O O a S TWHDX Write High to Data in Dont Care UUU a a _TWHEH Write High to Count Source High Notes 5 7 14 15 et se TWHGV Write High to Gate Valid Notes 5 10 14 O u a s TWHRL Write High to Read Low Write Recovery Time Note 10 a poj TWHSH Write High to CS High 2 TWHWL Write High to Write Low Write Recovery Time Noe i TWHYV Write High to Out Valid Notes 6 14 O _ a 65 TWLWH Write Low to Write High Write Pulse Curation Note 12 1 18 TGVEHZ Gate Valid to Count Source High Special Gate Notes 10 13 17 _TEHGV2 Count Source High to Gate Valid Special Gate Notes 10 13 18 T a2 e Notes E Enabled counter source input SRC1 5 5 1 Abbreviations used for the switching parameter symbols are BRI given as the letter T followed four or five characters The _ 2 fir
11. Chapter 4 Programming Table 4 2 Straight Binary Mode A D Conversion Values Input Voltage A D Conversion Result Gain 1 Range 0 to 10 V To convert from the A D FIFO value to the input voltage measured use the following formula V A D Count 10V 4 096 Gain Table 4 3 Two s Complement Mode A D Conversion Values Input Voltage A D Conversion Result Gain 1 Range 5 to 5 V Range 10 to 10 V INN NE AN To convert from the A D FIFO value to the input voltage measured use the appropriate formula as follows 5V Range A D Count 5 V 2 048 Gain 10V Range A D Count 10 V 2 048 Gain Clearing the Analog Input Circuitry The analog input circuitry can be cleared by writing to the A D Clear Register This operation leaves the analog input circuitry in the following state National Instruments Corporation 4 45 AT MIO 16D User Manual Programming Chapter 4 Analog input error flags OVERFLOW and OVERRUN are cleared e Pending interrupt requests are cleared e A D FIFO is emptied Empty the A D FIFO before starting any A D conversions This action guarantees that the A D conversion results read from the A D FIFO are the results from the initiated conversions not results left over from previous conversions To clear the analog input circuitry and the A D FIFO write 0 to the A D Clear Register Programming Multiple A D Conversions on a Single Input Channel The AT MIO 16D boa
12. Pins 25 27 29 and 31 are connected to the digital lines ADIO lt 3 0 gt for digital I O port A Pins 26 28 30 and 32 are connected to the digital lines BDIO lt 3 0 gt for digital I O port B Pin 24 DIG GND is the digital ground pin for both digital I O ports Ports A and B can be programmed individually to be inputs or outputs The following specifications and ratings apply to the MIO 16 digital I O lines Absolute maximum voltage input rating 5 5 V with respect to DIG GND Digital input specifications referenced to DIG GND input logic high voltage 2 V minimum input logic low voltage 0 8 V maximum AT MIO 16D User Manual 2 34 National Instruments Corporation Chapter 2 Configuration and Installation input current load logic high input voltage 40 LA maximum input current load logic low input voltage 120 LA maximum Digital output specifications referenced to DIG GND output logic high voltage 2 4 V minimum VoL output logic low voltage 0 5 V maximum output source current logic high 2 6 mA maximum output sink current logic low 24 mA maximum With these specifications each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads The MIO 16 circuitry digital I O lines are pulled up through 100 resistors to 5 V Figure 2 32 depicts signal connections for three typical digital I O applications Pot ADIO lt 3 0 gt Port B BDIO lt 3 0 gt S
13. STB 1 to INTR 1 300 5 Data after STB 1 180 6 RD 0 to INTR 0 400 7 RD 1 to IBF 0 300 All timing values are in nanoseconds National Instruments Corporation 2 47 AT MIO 16D User Manual Configuration and Installation Chapter 2 DIO 24 Mode 1 Output Timing The following are the timing specifications for an output transfer in Mode 1 Name Description Minimum Maximum Tl WR 0 to INTR 0 450 2 WR 1 to Output 350 T3 WR 1 to OBF 0 650 T4 ACK 0 to OBF 1 350 5 Pulse Width 300 6 ACK 1 to INTR 1 350 All timing values are in nanoseconds AT MIO 16D User Manual 2 48 National Instruments Corporation Chapter 2 Configuration and Installation DIO 24 Mode 2 Bidirectional Timing The following are the timing specifications for bidirectional transfers in Mode 2 Name Description Minimum Maximum Tl WR 1 to OBF 0 650 T2 Data before STB 1 0 T3 STB Pulse Width 500 T4 STB 0 to IBF 1 300 5 Data after STB 1 180 6 ACK 0 to 1 350 7 Pulse Width 300 8 ACK 0 to Output 300 T9 ACK to Output Float 20 250 T10 RD 1 to IBF 0 300 All timing values are in nanoseconds National Instruments Corporation 2 49 AT MIO 16D User Manual Configuration and Installation Chapter 2 Cabling and Field Wiring This section discusses cabling and field wiring guidelines for the AT MIO 1
14. d Write the least significant 16 bits of the sample count value minus 1 to the Am9513A Data Register to store the Counter 4 load value e Ifthe least significant 16 bits are all zeros write FFFF e Write FF48 to the Am9513A Command Register to load Counter 4 f Write 0 to the Am9513A Data Register to store 0 into the Load Register for Counter 4 reloading National Instruments Corporation 4 53 AT MIO 16D User Manual Programming Chapter 4 g Write FF28 to the Am9513A Command Register to arm Counter 4 h Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register k Take the most significant 16 bits of the sample count and do the following e Ifthe least significant 16 bits of the sample count are all zeros or all zeros except for a 1 in the least significant bit write the most significant 16 bits to the Am9513A Data Register to store the Counter 5 load value e Otherwise add one to the most significant 16 bits of the sample count and write that value to the Am9513A Data Register to store the Counter 5 load value l Write FF70 to the Am9513A Command Register to load and arm Counter 5 m Setthe 16 32 CNT bit in Command Register 1 to notify the hardware that both Counters 4 and 5 will be used as the sample counter After you complete this prog
15. eh 3 17 DIO 24 Circuitry VOC Onn Ct dae e ase Ee dr 3 18 AT MIO 16D User Manual x National Instruments Corporation Contents 82C55A Programmable Peripheral 3 18 S62 CIA Of ote neo aue QE 3 18 hier P M 3 18 Mod 3 19 Mod 2 3 19 Single Bit Set Reset Features decani 3 19 4 Prosrammill 4 1 Mapenor a aan ets 4 1 ILLA BEI VA EE 4 2 Resister Description ndena 4 2 Register Description ets err nee rene eo ee se ete 4 3 Configuration and Status Register Group seen 4 3 Command Register oio cca senate eerte ne tae Pc aeons 4 4 ade RD DR C c E 4 6 Command Register 2 4c aca Qaqis teams istis aM ii esed e Mss 4 9 The Event Strobe Register Group oc oe ss sae Queso do ibas oda Qut edidere 4 11 Start Convert 4 12 Stat DAQ Registern E 4 13 A D Clear beh Re MUR Mun tas 4 14 External Strobe Re8lStep odes debe ta cae sae
16. Load Counters Coding C6 CS C4 C2 C1 CO Description Any combination of counters as specified in the S field will be loaded with previously entered values The source of information for each counter wiil be either the associated Load register or the associated Hold register as determined by the operating configuration in the Mode register The Load Hold contents are not changed This command will cause a transfer independent of any current operating configuration for the counter it will often be used as a software retrigger or as Unused except when 111 001 or 000 Figure 20 Am9513A Unused Command Codes Arm Counters Coding cr C6 cS C4 C2 Ci CO Description Any combination of counters as specified by the S field will be enabled for counting A counter must be armed before counting can commerce Once armed the counting process may be further enabled or disabled using the hard ware gating facilities This command can only arm or do nothing for a given counter a zero in the S field does not disarm the counter ARM and DISARM commands can be used to gate counter operation on and off under software control DISARM com mands entered while a counter is in the TC state will not take effect until the counter leaves TC This ensures that the counter never latches up in a TC state The counter may leave the TC state because of application of a count source edge execution of a LOAD or LOAD AND ARM comm
17. b Take analog input readings from channel 0 at the following gains both 1 and 500 for the AT MIO 16DL both 1 and 8 for the AT MIO 16DH c Adjust trimpot R2 until the readings match to within one count at both gain settings 2 Adjust the ADC input offset Adjust the ADC input offset by applying an input voltage across ACHO and ACHS This input voltage is V 1 2 LSB and depends on the input range selected AT MIO 16D User Manual 5 4 National Instruments Corporation Chapter 5 Calibration Procedures Input Range Calibration Voltage 10 to 10 V 9 99756 V 5 to 5 V 4 99878 V a Connect the calibration voltage across ACHO pin 3 on the I O connector and ACH8 pin 4 Connect the ground point on the calibration voltage source to AI SENSE pin 19 b Take analog input readings from channel 0 at a gain of 1 and adjust trimpot R6 until the ADC readings flicker evenly between 2 048 and 2 047 3 Adjust the analog input gain Adjust the analog input gain by applying an input voltage across ACHO and ACH8 This input voltage is Vg 3 2 LSB and depends on the input range selected Input Range Calibration Voltage 10 to 10 V 9 99268 V 5to 45 V 4 99634 V a Connect the calibration voltage across ACHO pin 3 on the I O connector and ACHS pin 4 Connect the ground point on the calibration voltage source to AI SENSE pin 19 b Take analog input readings from channel 0 at a gain of 1 and adjust trimpot R1 until t
18. 91 640 0533 08 730 43 70 056 20 51 55 02 737 4644 0635 523154 AT MIO 16D User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax __ Phone ___ Computer brand Model Processor Operating system Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps will reproduce the problem AT MIO 16D Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting N
19. CMO 100 is selected the Status register will reflect an active low TC output For Counters 1 and 2 the OUT pin will reflect the comparator output if the comparators are enabled The Status register bit and OUT pin active high if CM2 0 and active low if CM2 1 When the high impedance option is selected and the comparator is enabled the status register bit will reflect an active high comparator output When the low impedance to Ground option is selected and the comparator is enabled the Status register bit will reflect an active low comparator output The Status register is normally accessed by reading the Control port see Figure 6 but may also be read via the Data port as part of the Contre Group BYTE POINTER Ours OUT 3 OUT 1 0 001900 Figure 10 Status Register Bit Assignments DATA PORT REGISTERS Counter Logic Groups As shown in Figures 4 and 5 each of the five Counter Logic Groups consists of a 16 bit general counter with associated control and output logic 16 bit Load register a 16 bit Hold register and a 16 bit Mode register In addition Counter Groups 1 and 2 aiso include 16 bit Comparators and 16 bit Alarm registers The comparator alarm functions are con trolled by the Master Mode register The operation of the Counter Mode registers is the same for all five counters The host CPU has both read and write access to all registers in the Counter Logic Groups through the Data port The counter
20. Connect the external signal that should trigger an interrupt to either PC3 or PCO When the external signal becomes logic high an interrupt request occurs To disable the external signal interrupt set the selected interrupt enable bit to logic high National Instruments Corporation 4 91 AT MIO 16D User Manual Chapter 5 Calibration Procedures This chapter discusses the calibration procedures for the AT MIO 16D analog input and analog output circuitry The AT MIO 16D is calibrated at the factory before shipment To maintain the 12 bit accuracy of the AT MIO 16D analog input and analog output circuitry recalibration at six month intervals is recommended Factory calibration is performed with the AT MIO 16D in its default factory configuration e DIFF analog input mode e 10 to 10 V analog input range bipolar e 10to 10 V analog output range bipolar with internal reference selected Recalibration of your AT MIO 16D board is recommended any time you change your board configuration Calibration Equipment Requirements For best measurement results the AT MIO 16D analog input circuitry needs to be calibrated so that its measurement accuracy is within 0 012 of its input range 2 LSB According to standard practice the equipment used to calibrate the AT MIO 16D should be 10 times as accurate that is have 0 001 rated accuracy Practically speaking calibration equipment with four times the accuracy of the item under calibr
21. Counter Mode 7 7 1 5 Reload Sowe cme oe Repetiton oe ope To il Gate Control 15 1 fever EDGE lever EDGE ooo LEVEL EDGE 000 LEVEL EDGE Count to TC then x Court to TC we then dam L _Count to TC repestedy without disarming Gab input not gate comer input x 1x 1 1 Count only during active gate level Lp aeg BC OR EM OU next TC oee second TC hardware retriggering 8 x x x x x x x x xlxlxi x _Reload counter from Load register on TC x x x x x x f 1 1 1 xI Load and Hold regi OE dedita A E E ERE MR D DR gate is LOW transfer Hold register into counter on each TC that gate is HIGH Sor eter me nsus register and then reload counter from Load register SERPENS SEEN EORR RESET E PCR CECI Counter Mode Seca Gate Cm a lo Lio Reload Source CMe Repetition CMS oo CM15 CM13 ______ LEVEL EDGE ooo L
22. DII DII DIO D9 ps D7 De Ds D3 D2 DI MSB LSB Bit Name Description 15 0 D lt 15 0 gt These bits are the two s complement result of a 12 bit A D conversion Bit D11 is inverted and extended out to bits D12 through D15 Values read therefore range from 2 048 to 2 047 decimal F800 to 7FF hex Two s complement mode is useful for bipolar analog input readings because the values read reflect the polarity of the input signal AT MIO 16D User Manual 4 24 National Instruments Corporation Chapter 4 Programming DMA TC INT Clear Register Writing to the DMA TC INT Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected Address Base address 16 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used National Instruments Corporation 4 25 AT MIO 16D User Manual Programming Chapter 4 Am9513A Counter Timer Register Group The three registers making up the Am9513A Counter Timer Register Group access the onboard Am9513A Counter Timer The Am9513A controls onboard data acquisition timing as well as general purpose timing for the user The Am9513A registers described here are the Am9513A Data Register the Am9513A Command Register and the Am9513A Status Register The Am9513A contains 18 additional internal registers These internal registers are accessed through the Am9513A Data Register A detailed register description of all Am95
23. DIO 24 circuitry 2 47 output timing DIO 24 circuitry 2 48 strobed input programming 4 82 to 4 84 strobed output programming 4 84 to 4 86 Mode 2 bidirectional bus programming 4 87 to 4 89 bidirectional timing DIO 24 circuitry 2 49 MSMS82C55A Programmable Peripheral Interface See 82C55A Programmable Peripheral Interface multiple A D conversions programming continuous channel scanning round robin applying a trigger 4 61 clearing A D circuitry 4 61 enabling scanning data acquisition operation 4 61 overflow and overrun conditions 4 61 to 4 62 overview 4 57 resetting multiplexer counter 4 61 sample counter programming 4 59 to 4 60 sample interval counter programming 4 58 to 4 59 servicing data acquisition operation 4 61 to 4 62 setting up analog channel and gain selection sequence 4 58 external timing considerations 4 51 to 4 57 controlling with EXTCONV signal 4 55 to 4 57 clearing A D circuitry 4 56 overflow and overrun conditions 4 56 to 4 57 selecting analog input channel and gain 4 56 servicing data acquisition operation 4 56 to 4 57 overflow and overrun conditions 4 55 pretriggering with STOP TRIG signal applying a trigger 4 54 clearing A D circuitry 4 54 sample counter programming 4 52 to 4 54 sample interval counter programming 4 52 National Instruments Corporation Index 15 AT MIO 16D User Manual Index selecting analog input channel and gain 4 51 servicing data acquisition operation 4 5
24. See pin assignments I O signal rating specifications DIO 24 circuitry 5 J jumper settings analog I O jumper settings 2 8 to 2 9 bipolar output selection 2 16 to 2 17 bus interface factory settings 2 1 default settings for National Instrument products 2 3 DIFF differential input configuration 2 10 to 2 11 DIO 24 circuitry interrupt handling 2 8 4 91 DMA jumper settings 2 5 to 2 7 example base I O address switch settings 2 4 external reference selection 2 15 input polarity and range 2 13 to 2 14 internal reference factory setting 2 15 to 2 16 interrupt jumper settings 2 7 to 2 8 NRSE input 16 channels 2 12 overview 2 1 RSE input 16 channels 2 11 to 2 12 RTSI bus clock selection 2 18 to 2 20 straight binary mode 2 17 switch settings with base I O address and address space 2 5 two s complement mode 2 17 unipolar output selection 2 18 L LabWindows software 1 4 AT MIO 16D User Manual Index 14 O National Instruments Corporation Index M MIO 16 cabling considerations 2 50 to 2 51 digital I O circuitry block diagram 3 12 programming 4 72 to 4 73 theory of operation 3 11 to 3 13 digital I O signal connections 2 34 to 2 36 digital I O specifications A 5 I O connector pin assignments 2 22 B 1 MIO 16 Digital I O Register Group 4 30 to 4 32 MIO 16 Digital Input Register 4 31 MIO 16 Digital Output Register 4 32 register map 4 2 Mode 0 programming 4 80 to 4 81 Mode 1 input timing
25. and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB bit 15 for a 16 bit register bit 7 for an 8 bit register shown on the left and the LSB bit 0 shown on the right A square is used to represent each bit Each bit is labeled with a name inside its square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers several bits are labeled with an X indicating don t care bits When register is read these bits may appear set or cleared but should be ignored because they have no significance When a register is written to setting or clearing these bit locations has no effect on the AT MIO 16D hardware The bit map field for some write only registers states not applicable no bits used Writing to these registers generates a strobe in the AT MIO 16D These strobes are used to cause some onboard event to occur For example they can be used to clear the analog input circuitry or to start a data acquisition operation The data is ignored when writing to these registers therefore any bit pattern will suffice Configuration and Status Register Group The three registers making up the Configuration and Status Register Group allow general control and monitoring of the AT MIO 16D hardware Command Registers 1 and 2 contain bits that control operation of several different pieces of the AT MIO 16D hardware The St
26. hex The interrupt request is serviced by writing to the DMA TC INT Clear Register When TCINTEN is cleared no DMA terminal count interrupts are generated y CONVINTEN This bit enables and disables the generation of an interrupt when A D conversion results are available If CONVINTEN is set an interrupt is generated whenever an A D conversion is available to be read from the A D FIFO If CONVINTEN is cleared no interrupt is generated 6 DBDMA This bit selects the DMA mode If DBDMA is cleared and DMAEN is set a single channel single buffered DMA mode is selected If DBDMA is set and DMAEN is set a double channel double buffered DMA mode is selected AT MIO 16D User Manual 4 4 National Instruments Corporation Chapter 4 Bit Name 5 DMAEN 4 DAQEN 3 SCANEN 2 SCANDIV 1 16 32CNT 0 2SCADC Programming Description continued This bit enables and disables the generation of DMA requests If DMAEN is set a DMA request is generated whenever an A D conversion result is available to be read from the A D FIFO If DMAEN is cleared no DMA request is generated This bit enables and disables a data acquisition operation that is controlled by the onboard sample interval and sample counters If DAQEN is set a software or start trigger starts the counters assuming that the counters are programmed and enabled thereby initiating a data acquisition operation If DAQEN is cleared software and start triggers are ignored This
27. lower numbered counter The Counter 5 TC wraps around to the Counter 1 input This option allows internal concatenating that permits very long counts to be accumulated Since all five counters may be concatenated it is possible to configure a counter that is 80 bits long on one Am9513A chip When TCN 1 is the source the count ripples between the connected Counters External connections can also be made and can use the toggle bit for even longer counts This is easily accomplished by selecting a TC Toggied output mode and wiring OUTN to one of the SRC inputs Gating Control Counter Mode bits CM15 CM14 CM13 specify the hardware gating options When no gating is selected 000 the AMD 9513 Data Sheet counter will proceed unconditionally as long as it is armed For any other gating mode the count process is conditioned by the specified gating configuration For a code of 100 in this field counting can proceed only when the pin labeled GATEN associated with Counter is at a logic high ievel When it goes LOW counting is simply suspended until the Gate goes HIGH again A code of 101 performs the same function with an opposite active polarity Codes 010 and 011 offer the same function as 100 but specify alternate input pins as Gating Sources This allows any of three interface pins to be used as gates for a given counter On Counter 4 for example pin 34 pin 35 or pin 36 may be used to perform the gating function This
28. operating mode One special case occurs when the Time of Day option is revoked and both Comparators are enabled The operation of Comparator 2 will then be conditioned by Comparator 1 so that a full 32 bit compare must be true in order to generate a true signal on OUT2 OUT will continue as usuai to reflect the state of the 16 bit comparison between Alarm 1 and Counter 1 2 126 AT MIO 16D User Manual E 12 FOUT Source Master Mode bits MM4 through specify the source input for the FOUT divider Fifteen inputs are available for selection and they include the five Source pins the five Gate pins and the five internal frequencies derived from the oscillator The 16th combination of the four control bits all zeros is used to assure that an active frequency is availabie at the input to the FOUT divider following reset FOUT Divider Bits MM8 through MM11 specify the dividing ratio for the FOUT Divider The FOUT source selected by bits MM4 through MM7 is divided by an integer value between 1 and 16 inclusive and is then passed to the FOUT output buffer After power on or reset the FOUT divider is set to divide by 16 FOUT Gate Master Mode bit MM12 provides a software gating capability for the FOUT signal When 12 1 FOUT is off and in a low impedance state to ground MM12 may be set or cleared in conjunction with the loading of the other bits in the Master Mode register alternatively there are commands that allo
29. terion gases 65 V6 Suy Stony Sui PETER 5 GN mutemmxs 25 pins not under test at O V __ 18 20 e P 20 20 Guaranteed by design SWITCHING TEST INPUT OUTPUT WAVEFORMS 2 4 20 _ TEST 29 7 POINTS 0 8 0 45 f WF004810 002000 Crystal is fundamental mode parallel resonant 32 pF load capacitance less than 100 2 ESR less than 100 pF Am9513A 2 147 National Instruments Corporation E 33 AT MIO 16D User Manual AMD Am9513A Data Sheet The second and fourth ietters designate the reference states of the signals named in the first and third letters respectively using the following abbreviations H HIGH L Low VALID X Unknown or Don t care Z High Impedance 2 Any input transition that occurs before this minimum setup requirement will be reflected in the contents read from the status register 3 Any input transition that occurs before this minimum setup requirement will act on the counter before the execution of the operation initiated by the write and the counter may be off by one count 4 Any input transition that occurs after this minimum hoid time is guaranteed to not influence the contents read from the status register on the current read operation 5 Any input transition that occurs after this minimum hold time is guaranteed to be seen by the c
30. the analog output circuitry should be initialized to 0 V If the analog output channel is configured for unipolar operation write 0 to the DAC Register 16 bit write for that channel If the analog output channel is configured for two s complement bipolar output write 0 to the DAC Register 16 bit write for that channel Programming the Analog Input Circuitry Programming the analog input circuitry to obtain a single A D conversion involves the following sequence of steps 1 Select the analog input channel and gain 2 Initiate an A D conversion 3 Read the A D conversion result In addition you can program the binary format of the A D conversion result and you can reset the analog input circuitry 1 Select analog input channel and gain The analog input channel and gain are selected by writing to the Mux Gain Register Bits 7 and 6 control the gain and bits 3 through 0 select the analog input channel See the Mux Gain Register bit description earlier in this chapter for gain and analog input channel bit patterns Set up the bits as given in the Mux Gain Register bit description and write to the Mux Gain Register Once the Mux Gain Register is set up it needs to be written to only when you need to change the analog input channel or gain setting 2 Initiate an A D conversion An A D conversion can be initiated in one of two ways a software generated pulse or a hardware pulse To initiate an A D conversion through software
31. write 0 to the A D Start Convert Register To initiate an A D conversion through hardware apply an active low pulse to the EXTCONV pin on the AT MIO 16D I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for EXTCONV signal specifications Once an A D conversion is initiated the ADC automatically stores the result in the A D FIFO at the end of its conversion cycle National Instruments Corporation 4 43 AT MIO 16D User Manual Programming Chapter 4 3 Read the A D conversion result A D conversion results are obtained by reading the A D FIFO Register Before reading the A D FIFO however the Status Register must be read to determine whether the A D FIFO contains any results To read the A D conversion result do the following a Read the Status Register 16 bit read b Ifthe CONVAVAIL bit is set bit 13 then read the A D FIFO Register to obtain the result Reading the A D FIFO Register removes the A D conversion result from the A D FIFO The binary modes of the A D FIFO output are explained below The CONVAVAIL bit indicates whether one or more A D conversion results are stored in the A D FIFO If the CONVAVAIL bit is not set the A D FIFO is empty and reading the A D FIFO Register returns meaningless data Once an A D conversion is initiated the CONVAVAIL bit is set within 10 indicating that the data conversion result can be read from the FIFO An A D FI
32. 11 The Group fieid circulates oniy within the five Counter Group codes if E2 E1 11 and a Counter Group are selected then oniy the Group field is sequenced This is the Hold cycle It allows the Hold registers to be sequentially accessed while bypassing the Mode and Load registers The third type of sequencing is the Control cycle If G4 G2 G1 111 and E2 E1 11 the Element Pointer will be incremented through the values 00 01 and 10 with no change to the Group Pointer When G4 G2 G1 111 and E2 E1 11 no incrementing takes place and only the Status register will be available through the Data port Note that the Status register can also always be read directly through the Control port For these auto sequencing modes if an 8 bit data bus is used the Byte pointer will toggle after every data transfer to allow the least and most significant bytes to be transferred before the Element or Group fields are incremented Prefetch Circuit To minimize the read access time to internal Am9513A registers a prefetch circuit is used for all read operations through the Data port Following each read or write operation through the Data port the Data Pointer register is updated to point to the next register to be accessed Immediately following this update the new register data is transferred to a speciai prefetch latch at the interface pad logic When the user performs a subsequent read of the Data port the data bus drive
33. 15 0 gt Counter Ti 16 GATEI TREE Am9513 RD WR SOURCEI OUTI GATES SOURCES OUTS e 8 9 e Q SOURCE4 RTSI Bus SOURCE3 PC AT I O Channel OUTI CONVERT OUT3 Data STOP TRIG GATE4 OUT4 Acquisition SCANCLK OUTS Timing GATE3 MUX CTR CLK Figure 3 6 Timing I O Circuitry Block Diagram Am9513A contains five independent 16 bit counter timers a 4 bit frequency output channel and five internally generated timebases The five counter timers can be programmed to operate in several useful timing modes The programming and operation of the Am9513A is presented in detail in Appendix E Am9513A Data Sheet The Am9513A clock input is one tenth the MYCLK frequency selected by the W5 jumpers The factory default for MYCLK is 10 MHz which generates a 1 MHz clock input to the Am9513A The Am9513A uses this clock input to generate five internal timebases These timebases can be used as clocks by the counter timers and by the frequency output channel When MYCLK is 10 MHz the five internal timebases normally used for AT MIO 16D timing functions are 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz National Instruments Corporation 3 13 AT MIO 16D User Manual Theory of Operation Chapter 3 The 16 bit counters in the Am9513A can be diagrammed as shown in Figure 3 7 SOURCE COUNTER OUT GATE Figure 3 7 Counter Block Diagram Each counter has a SOURCE input p
34. 16D I O Connector Pin Description eene 2 21 MIO 16 I O Connector Pin DeScriptiOn eeeeceeeeeeeceeeceeeeeeeeeteeeeneeeenaeeeenes 2 22 MIO 16 Signal Connection 2 23 Analog Input Signal Connections 2 25 Types Of Signal SOUFCeS dedu ole but edo 2 26 Fl ating Signal Sources Alia tena da rds 2 26 Ground Referenced Signal Sources sse 2 27 COBTIBUEAUOFS stiano eret e Mr 2 27 Differential Connection Considerations DIFF Configuration 2 27 Differential Connections for Grounded Signal Sources 2 28 Differential Connections for Floating Signal Sources 2 29 Single Ended Connection Considerations sess 2 30 National Instruments Corporation ix AT MIO 16D User Manual Contents Single Ended Connections for Floating Signal Sources RSE Configuration siye sue steers 2 30 Single Ended Connections for Grounded Signal Sources NRSE onim ute 2 31 Common Mode Signal Rejection 2 32 Analog Output Signal 5 2 33 Digital I O Signal Connections 11 cr
35. 3 Adjust the analog input gain Adjust the analog input gain by applying an input voltage across ACHO and ACHS This input voltage is 9 99634 V or 3 2 LSB a Connect the calibration voltage 9 99634 V across ACHO pin 3 on the I O connector and ACHS pin 4 Connect the ground point on the calibration voltage source to AI SENSE pin 19 b Take analog input readings from Channel 0 at a gain of 1 and adjust trimpot R1 until the ADC readings flicker evenly between 4 094 and 4 095 Analog Output Calibration To null out error sources that affect the accuracy of the output voltages generated you must calibrate the analog output circuitry by adjusting the following potential sources of error Analog output offset error Analog output gain error Offset error in the analog output circuitry is the total of the voltage offsets contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is independent of D A setting To correct this offset gain error set the D A to negative full scale and adjust a trimpot until the output voltage is the negative full scale value 2 LSB AT MIO 16D User Manual 5 6 National Instruments Corporation Chapter 5 Calibration Procedures Gain error in the analog output circuitry is the product of the gains contributed by each component in the circuitry This error appears as a voltage differenc
36. 4 The analog circuitry is then controlled by the multiplexer address and gain settings in mux gain memory location 4 see the Mux Gain Register description later in this chapter National Instruments Corporation 4 21 AT MIO 16D User Manual Programming Chapter 4 Mux Gain Register The Mux Gain Register controls the multiplexer and gain settings and when used in conjunction with the Mux Counter Register allows a scan sequence to load into the mux gain memory Address Base address 6 hex Type Write only Word Size 16 bit Bit Map 15 14 13 11 9 amp ER Oe 5 0 a Bit Name Description 15 8 X Don t care bits 7 6 GAIN lt 1 0 gt This 2 bit field controls the gain setting of the input instrumentation amplifier The actual amplifier gains depend on the type of AT MIO 16D board The following gains can be selected on the AT MIO 16DH board The following gains can be selected on the AT MIO 16DL board 01 10 10 11 5 X Don t care bit AT MIO 16D User Manual 4 22 National Instruments Corporation Chapter 4 Programming Bit Name Description continued 4 LASTONE This bit should be set in the last entry of the scan sequence loaded into the mux gain memory 3 0 lt 3 0 gt This 4 bit field controls the multiplexer address setting of the input multiplexers thereby allowing the analog input channel to be selected In single ended mode NRSE
37. 4 37 DIO 24 PORTB Register 4 38 DIO 24 PORTC Register 4 39 overview 4 36 to 4 40 register map 4 2 DMA channel configuration 2 5 to 2 7 default settings for National Instrument products 2 3 PC AT I O channel interface 3 4 programming DMA operations 4 76 to 4 77 DMA TC INT Clear Register 4 25 documentation abbreviations used in the manual vi vii acronyms used in the manual vii organization of v vi related documentation vii E enabling data acquisition operation See data acquisition programming equipment optional 1 5 to 1 7 National Instruments Corporation Index 11 AT MIO 16D User Manual Index event counting event counting application with external switch gating 2 39 programming 2 38 to 2 39 Event Strobe Register Group 4 11 to 4 15 A D Clear Register 4 14 External Strobe Register 4 15 register map 4 1 Start Convert Register 4 12 Start DAQ Register 4 13 EXTCONV signal controlling multiple A D conversions 4 55 to 4 57 clearing A D circuitry 4 56 selecting analog input channel and gain 4 56 servicing data acquisition operation 4 56 to 4 57 definition of 2 24 initiating A D conversions 4 43 4 46 RTSI switch 3 16 timing connections 2 37 external reference selection 2 15 External Strobe Register 4 15 external timing considerations for multiple A D conversions programming See multiple A D conversions programming EXTREF signal 2 23 2 33 to 2 34 EXTSTROBE signal definition of 2 23 di
38. 5 5 bipolar output analog output circuitry 3 11 calibration procedure 5 7 to 5 8 configuration 2 16 to 2 17 configuring input polarity and range 2 12 to 2 14 unipolar input calibration procedure 5 5 to 5 6 unipolar output National Instruments Corporation Index 17 AT MIO 16D User Manual Index analog output circuitry 3 11 calibration procedure 5 8 configuration 2 18 Port C See DIO 24 Register Group posttrigger data acquisition 4 46 power connections DIO 24 I O connector 2 44 MIO 16 I O connector 2 36 power requirements A 6 pretrigger data acquisition 4 46 pretriggering multiple A D conversions with STOP TRIG signal 4 51 to 4 55 applying a trigger 4 54 clearing A D circuitry 4 54 sample counter programming 4 52 to 4 54 sample interval counter programming 4 52 selecting analog input channel and gain 4 51 servicing data acquisition operation 4 55 programming DIO 24 4 78 to 4 91 82C55A modes of operation 4 80 to 4 89 interrupt programming examples 4 89 to 4 90 Mode 0 basic I O 4 80 to 4 81 programming example 4 81 to 4 82 Mode 1 strobed input 4 82 to 4 84 pin assignments 4 84 Port C status word bit definitions 4 83 to 4 84 programming example 4 84 Mode 1 strobed output 4 84 to 4 86 pin assignments 4 86 programming example 4 86 status word bit definitions 4 85 to 4 86 Mode 2 bidirectional bus 4 87 to 4 89 control word 4 87 pin assignments 4 87 to 4 88 status word bit definitions 4 87 to
39. A 5 signal rating 5 operating environment A 6 output signal A 6 physical characteristics A 6 power requirements A 6 storage environment A 6 transfer rates A 6 MIO 16 circuitry analog data acquisition rates A 3 analog input A 1 to A 3 analog output A 4 digital I O A 4 timing I O A 5 square waves producing 2 39 Start Convert Register 4 12 National Instruments Corporation Index 23 AT MIO 16D User Manual Index Start DAQ Register 4 13 START TRIG signal definition of 2 24 initiating A D conversions 4 46 RTSI switch 3 16 timing connections 2 37 to 2 38 Status Register 4 6 to 4 8 STOP TRIG signal data acquisition timing connections 2 38 definition of 2 24 pretriggering multiple A D conversions 4 51 to 4 55 applying a trigger 4 54 clearing A D circuitry 4 54 sample counter programming 4 52 to 4 54 sample interval counter programming 4 52 selecting analog input channel and gain 4 51 servicing data acquisition operation 4 55 RTSI switch 3 16 storage environment specifications A 6 straight binary mode A D conversion values 4 45 output selection 2 17 system noise A 3 T technical support G 1 theory of operation 82C55A Programmable Peripheral Interface 3 18 to 3 19 Mode 0 3 18 Mode 1 3 19 Mode 2 3 19 modes of operation 3 18 single bit set reset feature 3 19 analog input circuitry 3 6 to 3 7 A D converter 3 7 ADC FIFO buffer 3 7 block diagram 3 5 channel selection ci
40. Appendix AMD Am9513A Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Commercial C Devices Storage Temperature 65 C to 150 C Temperature 0 to 70 VCC with Respect to VSS 05 V to 7 0 V Supply Voltage VOC 5 V 5 Signal Voltages 4 with Respect to 5 0 5 V to 7 0 V Industrial I Devices Power Dissipitation Package Limitation 15 W Temperature 40 to 85 Supply Voltage VCC 5 V 596 Stresses above those listed under ABSOLUTE MAXIMUM Military M Devices RATINGS may cause permanent device failure Functionality Temperature 58 to 125 C at or above these limits is not implied Exposure to absolute maximum ratings for extended periods may affect device reliability Operating ranges define those limits between which the functionality of the device is guaranteed DC CHARACTERISTICS over operating ranges unless otherwise specified Tes Condos _All inputs Except x2 VSS 9 _All input Except x20 N Le Tat years GAG and GATE laps Oop ow ves l omwirvaae Tet Vonage 00 Lu i mea Eug XE ae a Te
41. DMA terminal count is received the board automatically switches the DMA operation to DMA Channel 2 and Memory Buffer 2 DMA 2 Therefore the board can collect data into one buffer and service data in another buffer simultaneously If the DMA controller is programmed for auto reinitialize mode DMA 1 and DMA 2 are continuously served in turn Interrupt Programming Four different interrupts are generated by the AT MIO 16D board An interrupt whenever a conversion is available to be read from the A D FIFO An interrupt whenever a DMA terminal count is received e An interrupt whenever a data acquisition operation is completed either normally or due to an error condition e An interrupt whenever a rising edge on the OUT2 pin of the Am9513A is detected These four interrupts are enabled individually To use any one of these interrupts the overall interrupt enable bit INTEN in Command Register 2 must be set To use the conversion interrupt set the CONVINTEN bit in Command Register 1 and the INTEN bit in Command Register 2 If these bits are set if an interrupt occurs from the AT MIO 16D board and if the CONVAVAIL bit in the Status Register is set then a conversion interrupt has occurred Reading from the A D FIFO Register clears this interrupt condition Writing to the A D Clear Register also clears the conversion interrupt To use the DMA terminal count interrupt set the DMAEN and TCINTEN bits in Command Register 1 and the INTEN bit
42. Differential connections are those in which each AT MIO 16D analog input signal has its own reference signal or signal return path These connections are available when the AT MIO 16D is configured in the DIFF mode Each input signal is tied to the positive input of the instrumentation amplifier and its reference signal or return is tied to the negative input of the instrumentation amplifier When the AT MIO 16D is configured for DIFF input each signal uses two of the multiplexer inputs one for the signal and one for its reference signal Therefore only eight analog input channels are available when using the DIFF configuration The DIFF input configuration should be used when any of the following conditions are present National Instruments Corporation 2 27 AT MIO 16D User Manual Configuration and Installation Chapter 2 1 Input signals are low level less than 1 V 2 Leads connecting the signals to the AT MIO 16D are greater than 15 ft 3 Any of the input signals requires a separate ground reference point or return signal 4 The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode signal and noise rejection They also allow input signals to float within the common mode limits of the input instrumentation amplifier Differential Connections for Grounded Signal Sources Figure 2 27 shows how to connect a ground referenced signal source to an AT M
43. Each cycle of the scan sequence begins at the time interval specified by the scan interval If the sample interval counter is programmed for the minimum time required to complete an A D conversion interval channel scanning can be thought of as a pseudo simultaneous scanning of multiple channels that is all channels in the scan sequence are read as quickly as possible at the beginning of each scan interval Multiple A D Conversions with Continuous Channel Scanning Round Robin Programming continuous scanning of multiple A D conversions involves the following programming steps 1 Set up the analog channel and gain selection sequence Program the sample interval counter Program the sample counter Clear the A D circuitry and reset the multiplexer counter Enable the scanning data acquisition operation WU SV Apply a trigger 7 Service the data acquisition operation Setting the SCANEN bit in Command Register 1 enables scanning during multiple A D conversions You must set this bit regardless of the type of scanning used otherwise only a single channel is scanned In addition a channel and gain scan sequence must be stored in the mux gain memory National Instruments Corporation 4 57 AT MIO 16D User Manual Programming Chapter 4 1 Set up the analog channel and gain selection sequence During a scanning data acquisition operation a selected number of locations in the mux gain memory are clocked through A n
44. Ended configuration Provides 16 single ended inputs with the negative input of the instrumentation amplifier referenced to analog ground NRSE Nonreferenced Single Ended configuration Provides 16 single ended inputs with the negative input of the instrumentation amplifier tied to AI SENSE and not connected to ground While reading the following paragraphs you may find it helpful to refer to the Analog Input Signal Connections section later in this chapter which contains diagrams showing the signal paths for the three configurations DIFF Analog Input Eight Channels Factory Setting DIFF input means that each input signal has its own reference and the difference between each signal and its reference is measured The signal and its reference are each assigned an input channel With this input configuration the AT MIO 16D can monitor eight different analog input signals You select the DIFF analog input configuration by setting jumpers W6 and W9 as follows W6 A C Jumperis placed in standby position Jumper can be discarded B D is tied to the instrumentation amplifier output ground point Channels 0 through 7 are tied to the positive input of the instrumentation amplifier Channels 8 through 15 are tied to the negative input of the instrumentation amplifier AT MIO 16D User Manual 2 10 National Instruments Corporation Chapter 2 Configuration and Installation 9 Multiplexer i
45. OFFF hex This mode is useful if a unipolar input range is used If 2SCADC is cleared a 16 bit two s complement mode is used and the data read from the ADC ranges from 2 048 to 2 047 decimal F800 to 07FF hex This mode is useful if a bipolar input range is used National Instruments Corporation 4 5 AT MIO 16D User Manual Programming Chapter 4 Status Register The Status Register contains 16 bits of AT MIO 16D hardware status information including interrupt and analog input status Address Base address hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 GINT DAQSTOPINT CONVAVAIL OUT2INT DAQPROG DMATCINT OVERFLOW OVERRUN 7 6 5 4 3 2 1 0 Bit Name Description 15 GINT This bit reflects the overall state of interrupts generated by the MIO 16 circuitry on the AT MIO 16D board If GINT is set the AT MIO 16D is asserting an interrupt request on the MIO 16 interrupt that has not yet been serviced If GINT is cleared no MIO 16 interrupt is pending This bit is normally cleared 14 DAQSTOPINT This bit reflects the status of the data acquisition termination interrupt If DAQSTOPINT is set and either OVERFLOW or OVERRUN is set the current interrupt is due to an error condition If DAQSTOPINT is set and neither OVERFLOW nor OVERRUN is set the current interrupt is due to the completion of the data acquisition operation DAQSTOPINT is cleared by writing to the A D Clear Register 13 CONVAVA
46. RD is in low level data is transferred from 5 82 55 to CPU When WR is in low level data or control words are transferred from CPU to 5 82 55 By combination of AO and A1 either one is selected from among port port B port C and controi register Thess pins are usually connected to low order 2 bits of the address bus PA7 PAO Input and output puts can be determined by writing a control word Especially port A can be used as a bidirectional port when it is set to mode 2 PB7 PBO Port B input and These are universal amp bit 1 ports The direction of inputs out Output puts can be determined by writing control word These are universal amp bit I O ports The direction of inputs out puts can be determined by writing a control word as 2 ports with 4 bits each When port A or port B is used in mode 1 or mode 2 port A only they become control pins Especially when port C is used as an output port each bit can be set reset Chip select input These are universal 8 bit I O ports The direction of inputs out BASIC FUNCTIONAL DESCRIPTION When used in mode 1 or mode 2 however port C has bits to be defined as ports for control signal for Group and Group B operation ports port A for group A and port B for When satting mode to port having 24 bits set group B of their respective groups it by dividing it into two groups of 12 bits each Group A Port 8 bits and h
47. Register Group control the analog input circuitry and allow the A D FIFO to be read from The Mux Counter Register generates addresses for the mux gain memory The Mux Gain Register controls the current multiplexer and gain settings and allows the mux gain memory to be written to Reading the A D FIFO Register returns stored A D conversion results Writing to the DMA TC INT Clear Register clears the interrupt request generated by a DMA terminal count pulse Bit descriptions for the registers making up the Analog Input Register Group are given on the following pages AT MIO 16D User Manual 4 20 National Instruments Corporation Chapter 4 Programming Mux Counter Register The Mux Counter Register loads the counter that sequences through the mux gain memory Address Base address 4 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp 7 6 5 4 3 2 1 0 Bit Name Description 15 4 X Don t care bits 3 0 MC lt 3 0 gt These four bits are loaded into the multiplexer counter by writing to the Mux Counter Register The multiplexer counter generates addresses for the mux gain memory therefore writing to the Mux Counter Register allows a specific location in the mux gain memory to be addressed The mux gain memory contains a sequence of multiplexer addresses and gain settings For example writing 0004 hex to the Mux Counter Register loads the multiplexer counter with the value 4 and addresses mux gain memory location
48. Register Write only DAC Register Write only INT2CLR Register Write only continues National Instruments Corporation 4 1 AT MIO 16D User Manual Programming Chapter 4 Table 4 1 AT MIO 16D Register Map continued Register Name OffSet Address Analog Input Register Group Mux Counter Register Write only Mux Gain Register Write only A D FIFO Register Read only DMA TC INT Clear Register Write only Am9513A Counter Timer Register Group Am9513A Data Register Read and write Am9513A Command Register Write only Am9513A Status Register Read only MIO 16 Digital I O Register Group MIO 16 Digital Input Register Read only MIO 16 Digital Output Register Write only RTSI Switch Register Group RTSI Switch Shift Register Write only RTSI Switch Strobe Register Write only DIO 24 Register Group DIO 24 PORTA Register Read and write DIO 24 PORTB Register Read and write DIO 24 PORTC Register Read and write DIO 24 CNFG Register Write only Register Sizes The IBM PC AT and compatibles support two different transfer sizes for read and write operations byte 8 bit and word 16 bit Table 4 1 shows the size of each AT MIO 16D register For example reading the A D FIFO Register requires a 16 bit word read operation at the specified address whereas writing to the RTSI Strobe Register requires an 8 bit byte write operation at the specified address Register Description Table 4 1 divides the AT MIO 16D registers into eight dif
49. Signals Data Buffers Internal Data Bus 5 S e E lt 5 DMA AT MIO 16D DMA Request DMA Request Control DMA ircuitry AT MIO 16D Acknowledge DMA Acknowledge amp Terminal Count IRQ Interrupt AT MIO 16D Control Interrupt Circuitry Request Figure 3 2 PC AT I O Channel Interface Circuitry Block Diagram The PC AT I O channel interface circuitry consists of address latches address decoder circuitry data buffers PC AT I O channel interface timing signals interrupt circuitry and DMA arbitration circuitry The PC AT I O channel interface circuitry generates the signals necessary to control and monitor the operation of the AT MIO 16D multiple function circuitry The PC AT I O channel has 24 address lines the AT MIO 16D uses 10 of these lines to decode the board address Therefore the board address range is hex 000 to SA5 through SA9 are used to generate the board enable signal SAO through SA4 are used to select onboard registers These address lines are latched by the address latches at the beginning of an I O transfer The latched address lines send the same address to the address decoding circuitry during the entire I O transfer cycle The address decoding circuitry generates the register select signals that specify which AT MIO 16D register is being accessed The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfe
50. THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ and RTSI are trademarks of National Instruments Corporation Product and company names listed are trademarks or
51. User Manual Chapter 2 uoistAeMd pue JequinN q quiessy IC J3uvds 010 3uVdS DIM sei 0000000 142 E n ren Bb ds sd E 31998 0000000 0000000000 000000000 C 9 928 223 i fe vai 00000000000 Ald s 000 00 pi sl 000000000 piso 10 cam ps 0860000 0000000 a 00000005048 ooooooogao o ini inen pen agg 8000009 gium p Me a 3 pes 8 09116659000 00000007 0000000 220 3 pe 0 Fini 6 1 000000 0040 ein FA Am qu 1000000 Bew 2 E gin uk eu MEUS 5 quits RS n Oto Ot o n VARA 10 696181 559 om N S w 2 T9I UINW lw p e Bo 26610 amp 10092000 8 000000 serm m pua wale ed MAE 7 oa INN as 22 Ei eae 0000000 i nn n 004 89998909 ee 0000904 z0 v vooz Beo 00000000000000 q c 660600000000 0000000000 0000000 0000000 Configuration and Installation Figure 2 1 Parts Locator Diagram National Instruments Corporation 2 2 AT MIO 16D User Manual Chapter 2 Configuration and Installation Base I O Address Selection The base I O address for the AT MIO 16D is dete
52. a TC inhibiting further counting As is fully explained in the TC section of this document for these modes the counter is actually stopped or disarmed following the active going source edge which drives the counter out of TC in other words since a counter in the TC state always counts irrespective of its gating or arming status the stopping or disarming of the count sequence is delayed until TC is terminated MODE A Software Triggered Strobe with No Hardware Gating cans cuna Joms cura curs owe owe cus cma cus cus x x Am9513A National Instruments Corporation Figure 15a Mode A Waveforms AMD Am9513A Data Sheet Mode A shown in Figure 15a is one of the simplest operating modes The counter will be availabie for counting source edges when it is issued an ARM command On each TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting Counting will resume when a new ARM command is issued MODE B Software Triggered Strobe with Level Gating euis cura curs 12 cuni cmo cue Luv x px x x x cus jupe 9 Mode 8 shown in Figure 15b is identical to Mode A except that source edges are counted only when the assigned Gate is active The counter must be a
53. aiso allows a single Gate pin to simulta neously contro up to three counters Counters 1 and 5 are considered adjacent when using TCN 1 001 Gate N 1 010 and Gate N 1 011 controls For codes of 110 or 111 in this field counting proceeds after the specified active Gate edge until one or two TC events occur Within this interval the Gate input is ignored except for the retriggering option When repetition is selected a cycle wiil be repeated as soon as another Gate edge occurs With repetition selected any Gate edge applied after TC goes active will start a new count cycle Edge gating is useful when implementing a digital single shot since the gate can serve as a convenient firing trigger A 001 code in this field selects the TC not TOGGLE output from the adjacent ower numbered counter as the gate This is useful for synchronous counting when adjacent counters are concatenated COMMAND DESCRIPTIONS The command set for the Am9513A allows the host processor to customize and manage the operating modes and features for particular applications to initialize and update both the internal data and control information and to manipulate operating bits during operation Commands are entered direct ly into the 8 bit Command register by writing into the Control port see Figure 6 Ail available commands are described in the following text Figure 19 summarizes the command codes and includes a brief description of each function Figur
54. allowing an external device to drive the digital lines 7 INTEN This bit enables and disables any interrupt generated from the MIO 16 circuitry of the AT MIO 16D board If this bit is cleared all MIO 16 interrupts are disabled from the AT MIO 16D board To generate a specific interrupt INTEN and a specific interrupt enable bit must be set 6 INT2EN This bit enables and disables the generation of an interrupt on the OUT signal of the Am9513A Counter Timer If INT2EN is set interrupt requests are generated when a rising edge on OUT2 is detected The interrupt is cleared by writing to the INTZCLR Register When INT2EN is cleared OUT2 interrupts are not generated This interrupt is useful for waveform generation or interrupt generation on an external signal connected to OUT2 National Instruments Corporation 4 9 AT MIO 16D User Manual Programming Bit Name 5 LDAC 4 SCN2 3 A4 RCV 2 A4 DRV 1 A2 RCV 0 A2 DRV AT MIO 16D User Manual Chapter 4 Description continued This bit selects the update method for the DAC outputs When LDAC is cleared both DACO and DACI are updated when either DAC is written to If LDAC is set both DACS are updated when an active low pulse is detected on the OUT signal of the Am9513A Counter Timer This bit selects the data acquisition scanning mode used when scanning multiple A D channels If SCN2 is cleared continuous channel scanning is used In this mode scan sequences are repeated with no d
55. and interrupt installation routines are not included See the JBM Personal Computer AT Technical Reference manual for additional information Main define BASE ADDRESS 0x210 Board located at address 210 define PORTAoffset 0x00 Offset for Port A define PORTBoffset 0x01 Offset for Port B define PORTCoffset 0x02 Offset for Port C define CNFGoffset 0x03 Offset for CNFG register unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE ADDRESS PORTAoffset portb BASE ADDRESS PORTBoffset portc BASE ADDRESS PORTCoffset cnfg BASE ADDRESS CNFGoffset EXAMPLE 1 Set up interrupts for Mode 1 input for Port A Select PC6 as the interrupt enable bit outp cnfg O0xB0 Port is an input in Mode 1 outp cnfg 0x09 Set PC4 to enable interrupts from 82C55A outp cnfg 0x0C Clear PC6 to enable interrupts National Instruments Corporation 4 89 AT MIO 16D User Manual Programming Chapter 4 EXAMPLE 2 Set up interrupts for Mode 1 input for Port B Select PC6 as the interrupt enable bit outp cnfg 0x86 Port B is an input in Mode 1 outp cnfg 0x05 Set PC2 to enable interrupts from 82C55A outp cnfg 0x0C Clear PC6 to enable interrupts EXAMPLE 3 Set up interrupts fo
56. another board can control single and multiple A D conversions on the AT MIO 16D The AT MIO 16D is available in two gain ranges The AT MIO 16DL 9 has software programmable gain settings of 1 10 100 and 500 for low level analog input signals The AT MIO 16DH 9 has software programmable gain settings of 1 2 4 and 8 for high level analog input signals The AT MIO 16D contains ADC with a 9 conversion time and is capable of data acquisition rates of up to 100 kbytes sec Detailed specifications for the AT MIO 16D are listed in Appendix A Specifications What Your Kit Should Contain Each version of the AT MIO 16D board has a different part number and kit part number listed as follows Kit Name Kit Part Number Kit Component Board Part Number AT AT MIO 16DL 9 16DL 9 776646 01 01 AT MIO 16DL 9 board 16DL 9 board 181965 01 01 EE NI EN board ELM The board part number is printed on your board along the top edge on the component side You can identify which version of the AT MIO 16D board you have by looking up the part number in the preceding table In addition to the board each version of the AT MIO 16D kit contains the following components Kit Component Part Number AT MIO 16D User Manual 320489 01 NI DAQ software for DOS Windows LabWindows with manuals 776250 01 NI DAQ Software Reference Manual for DOS Windows LabWindows 320498 01 NI DAQ Function Reference Manual for DOS Windows LabWin
57. basic control logic and control registers Counters 1 and 2 have additional Alarm registers and comparators associated with them plus the extra logic necessary for operating in a 24 hour time of day mode For real time operation the time of day logic will accept 50Hz 60Hz or 100Hz input frequencies Each generai counter has a single dedicated output pin It may be turned off when the output is not of interest or may be configured in a variety of ways to drive interrupt controllers Darlington buffers bus drivers etc The counter inputs on the other hand are specifically not dedicated to any given interface line Considerable versatility is available for configur ing both the input and the gating of individual counters This not only permits dynamic reassignment of inputs under soft ware control but aiso allows multiple counters to use a single input and a single gate pin to control more than one counter Indeed a single pin can be the gate for one counter and at the same time the count source for another Figure 5 Counter Logic Groups 3 4 and 5 9513 Appendix National Instruments Corporation Appendix E AMD Am9513A Data Sheet counten MODE REGISTER MODE REGISTER COUNTER 1 LOAD REGISTER COUNTER t MOLD REGISTER COUNTERS 2 3 LOAD AND HOLD REGISTERS COUNTER 1 ALARM REGISTER COUNTER 2 ALARM REGISTER AF002531 Figure 6 Am9513A Register Access Command ee ees eee
58. be read before the A D FIFO Register is read If the A D FIFO contains one or more A D conversion values the CONVAVAIL bit is set in the Status Register and the A D FIFO Register can be read to retrieve a value If the CONVAVAIL bit is cleared the A D FIFO is empty in which case reading the A D FIFO Register returns meaningless information The values returned by reading the A D FIFO Register are available in two different binary formats straight binary which generates only positive numbers or two s complement binary which generates both positive and negative numbers The binary format used is selected by the 2SCADC bit in Command Register 1 The bit pattern returned for either format is given below Address Base address 16 hex Type Read only Word Size 16 bit Bit Map Straight binary mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oO ofo o bs D7 D6 D5 D4 D3 D2 DI DO MSB LSB Bit Name Description 15 0 D lt 15 0 gt These bits are the straight binary result of a 12 bit A D conversion The most significant four bits are set to 0 in order to return a 16 bit result Values read therefore range from 0 to 4 095 decimal 0000 to OFFF hex Straight binary mode is useful for unipolar analog input readings because all values that are read reflect a positive polarity input signal Bit Map Two s complement binary mode 15 14 13 12 11 10 9 8 7 23 2 4 3 2 1 0 DII DII DII
59. be used during asynchronous operations Disarm Counters Coding C7 C6 CS C4 C3 C2 Ci CO 1 1 0 S5 54 53 52 51 Description Any combination of counters as specified by the S fieid will be disabled from counting A disarmed counter will cease all counting independent of other conditions The only exception to this is that a counter in the TC state will always count once in order to leave TC before DISARMing This count may be generated by a source edge by a LOAD or LOAD AND ARM command the LOAD AND ARM command will negate the DISARM command or by a STEP command A disarmed counter may be updated using the LOAD command and may be read using the SAVE command A count process may be resumed using an ARM command See the ARM command description for further details Save Counters Coding C5 C4 C2 CO 1 0 1 5 54 53 52 SI Description Any combination of counters as specified by S field will have their contents transferred into their associated Hold register The transfer takes place without interfering with any counting that may be underway This command will overwrite any previous Hold register contents The SAVE command is designed to allow an accumulated count to be preserved so that it can be read by the host CPU at some later time Disarm and Save Counters Coding 3 AMD Am9513A Data Sheet Description Any combination of counters as specified by the S field will be disarmed and the contents
60. between 9 99268 and 9 99756 V e For analog output channel 1 a Connect the voltmeter between DACI OUT pin 21 on the I O connector and AOGND pin 23 b Set the analog output channel to 9 99512 V by writing 2 047 to the DAC c Adjust trimpot R4 until the output voltage read is 49 990512 V 2 44 mV that is between 9 99756 and 9 99268 V Unipolar Output Calibration Procedure If your analog output channel is configured for unipolar output which provides an output range of 0 to 10 V then calibrate your board by performing the following procedure 1 Adjust the analog output offset Adjust the analog output offset by measuring the output voltage generated with the DAC set at zero This output voltage should be 1 2 LSB For unipolar output V f 0 V and 1 2 LSB 1 22 mV AT MIO 16D User Manual 5 6 National Instruments Corporation Chapter 5 Calibration Procedures For analog output channel 0 a b Connect the voltmeter between DACO OUT 20 on the I O connector AO GND pin 23 Set the analog output channel to 0 V by writing 0 to the DAC Adjust trimpot R7 until the output voltage read is 0 V 1 22 mV e For analog output channel 1 a Connect the voltmeter between DACI OUT pin 21 on the I O connector and AO GND pin 23 Set the analog output channel to 0 V by writing 0 to the DAC Adjust trimpot R3 until the output voltage read is 0 V 1 22 mV 2 Adjust the analog
61. bit enables and disables multiple channel scanning during data acquisition If SCANEN is set alternate analog input channels are sampled during data acquisition under control of the mux gain memory If SCANEN is cleared a single analog input channel is sampled during the entire data acquisition operation This bit enables and disables division of the mux counter clock during data acquisition The mux counter clock controls sequencing of the mux gain memory If SCANDIV is set the mux counter clock is controlled by Counter of the Am9513A Counter Timer If SCANDIV is cleared the mux counter clock generates one pulse per conversion This bit selects the count resolution for the number of A D conversions to be performed in a data acquisition operation If 16 32CNT is cleared a 16 bit count mode is selected and Counter 4 of the Am9513A Counter Timer controls conversion counting If 16 32CNT is set a 32 bit count mode is selected and Counter 4 is concatenated with Counter 5 to control conversion counting A 16 bit count mode can be used if the number of A D sample conversions to be performed is less than 65 537 A 32 bit count mode should be used if the number of A D sample conversions to be performed is greater than or equal to 65 537 This bit selects the binary format for the 16 bit data word read from the A D FIFO If 2SCADC is set a straight binary format 15 used and the data read from the A D FIFO ranges from 0 to 4 095 decimal 0 to
62. bits in the Master Mode register MM12 controls the output state of the FOUT signal When gated off the FOUT line will exhibit a low impedance to ground MM12 may also be controlled by loading the full Master Mode register in parallel Gate On FOUT Coding C7 C5 C4 CS C2 C1 00 Description This command clears Master Mode bit 12 without affecting other bits in the Master Mode register MM12 controis the output status of the FOUT signal When MM12 is 2 146 AT MIO 16D User Manual Description This command clears Master Mode bit 13 without Appendix E cleared FOUT will become active and will drive out the selected and divided FOUT signal MM12 may be controlled by loading the full Master Mode register in parallel When FOUT is gated on or off a transient pulse may be generated on the FOUT signal Disable Prefetch for Write Operations Coding C7 C6 C5 C4 C3 C2 Ci CO Description This command disables the prefetch circuitry during Write operations if does not affect Read operations This reduces the write recovery time and ailows the user to use block move instructions for initialization of the Am9513A registers Once prefetch is disabled for writing an Enable Prefetch for Write or a Reset command is necessary to re enable the prefetch circuitry for writing Note This command is only available in Am9513A de vices it is an illegal command in the Am9513 device Enable Prefetch for Write Operat
63. channel and gain 4 43 straight binary mode A D conversion values 4 45 two s complement mode A D conversion values 4 45 sample and hold amplifier 3 6 to 3 7 sign extension circuitry 3 7 theory of operation 3 6 to 3 7 analog input configuration analog I O jumper settings 2 8 to 2 9 DIFF differential input 2 10 to 2 11 factory settings 2 8 to 2 9 input mode 2 10 input polarity and range 2 12 to 2 14 AT MIO 16D User Manual Index 4 National Instruments Corporation Index NRSE input 16 channels 2 12 RSE input 16 channels 2 11 to 2 12 Analog Input Register Group 4 20 to 4 25 A D FIFO Register 4 24 DMA TC INT Clear Register 4 25 Mux Counter Register 4 21 Mux Gain Register 4 22 to 4 23 register map 4 2 analog input signal connections instrumentation amplifier 2 26 pin descriptions 2 25 to 2 26 warning against exceeding input ranges 2 25 analog input specifications differential nonlinearity A 2 explanation of specifications A 2 to A 3 integral nonlinearity A 2 relative accuracy A 2 system noise A 3 analog output calibration 5 8 bipolar output calibration procedure 5 7 to 5 8 board configuration 5 7 unipolar output calibration procedure 5 8 analog output circuitry block diagram 3 10 DAC operation 3 10 to 3 11 initializing 4 43 programming 4 71 to 4 72 analog output voltage versus digital code bipolar mode 4 72 unipolar mode 4 71 formulas for voltage output 4 71 theory of operation 3 10 to
64. contro signal and The status read out is as foliows Group B Status read on the data bus 5 Ds 5s os o o o input EE me a eee we oe Pome are emm m mm ome pem RID pe m m we m e me re mn pum pe pe pne je me eme m me RSE BS e e ite rs ms re ore gt TSS n mem m me IE E meme me 1 1 6 Reset of 5 82 55 becomes the input mode at high level pulse above Be sure to keep the RESET signal at power ON in 500 ns the high level at least for 50 us Subsequently it Note 5 82 55 After a write cornmand is executed to the command register the internal latch is cleared in PORTA PORTC For instance OOH is output at the beginning of write command when the output port is assigned However if PORTB is not cleared at this time PORTB is unstable In other words PORTB only outputs ineffective data unstable value according to the device during the period from after a write command is executed till the first data is written to PORTB 5 82 55 2 After a write command is executed to de command register the internal latch is cleared in All Ports PORTA PORTB PORTO OOH is ontput at the beginning of a write command when the output port is assigned 344 O National Instruments Corporation 1
65. eee 5 7 Unipolar Output Calibration Procedure eee 5 8 AT MIO 16D User Manual xii National Instruments Corporation Contents Appendix A Specifications ni cect antec Soon trees cl aidan oa te mes nena oak A 1 MIO T6 Circuitry Specifications cadena 1 Puce PE vs need eevee 1 Explanation of Analog Input A 2 Analog Data Acquisition e ere suse A 3 Single Channel Acquisition Rates eene A 3 Multiple Channel Scanning Acquisition 1 2 A 3 Analog Output occas ety sete tasses prediis Lie aM 4 Explanation of Analog Output Specifications A 4 Digital I O MIO 16 I O Connector A 5 Timme 5 DIG 24 Circuitry Specifications eco ad eed 5 ah oes 5 Input Signal SpecifiCatlons 5 Output Signal Specifications oan ee ce Bs Reade 6 MR EET 6 Power Requirement from PC AT I O Channel eene A 6 ebd mmn Ee 6 TET TT TINS UA ei acd duet
66. in Command Register 2 If these bits are set if an interrupt occurs from the AT MIO 16D board and if the DMATC bit in the Status Register is set then a DMA terminal count interrupt has occurred Writing to the DMA TC INT Clear Register or to the A D Clear Register clears this interrupt condition To use the data acquisition completion interrupt set the DAQSTOPINTEN bit in Command Register 1 and the INTEN bit in Command Register 2 If these bits are set if an interrupt occurs from the AT MIO 16D board and if the DAQSTOPINT bit in the Status Register is set then a data acquisition completion interrupt has occurred If either the OVERFLOW or the OVERRUN bit is set in the Status Register this interrupt is the result of a data acquisition termination error condition Otherwise the normal data acquisition completion interrupt has occurred Writing to the A D Clear Register clears the data acquisition completion interrupt and the error condition if any are set To use the OUT2 interrupt set the INTEN and the INT2EN bits in Command Register 2 If these bits are set if a rising edge occurs on OUT2 and if the OUT2INT bit in the Status Register is set then an OUT2 interrupt has occurred Writing to the INT2CLR Register clears the OUT2 National Instruments Corporation 4 77 AT MIO 16D User Manual Programming Chapter 4 interrupt This interrupt is helpful when using the DACs to implement a waveform generator This interrupt can also be used to
67. interrupt on an external signal connected to the OUT2 pin If OUT is connected to an external signal make certain that Counter 2 is reset as described under the Resetting the Hardware after a Data Acquisition Operation section earlier in this chapter If Counter 2 is not reset it may drive the OUT2 line preventing the external signal from successfully driving the line high or low DIO 24 Circuitry Programming Considerations The DIO 24 circuitry is designed around the 82C55A integrated circuit The 82C55A is a general purpose peripheral interface containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 82C55A These ports can be programmed as two groups of 12 signals or as three individual 8 bit ports This section includes programming information for the DIO 24 circuitry along with program examples written in C The three 8 bit ports of the 82C55A are divided into two groups Group A and Group B two groups of 12 signals One 8 bit configuration or control word determines the mode of operation for each group The Group A control bits configure Port A AO through A7 and the upper 4 bits nibble of Port C C4 through C7 The Group B control bits configure Port B BO through B7 and the lower nibble of Port C CO through C3 These configuration bits are defined later in this chapter DIO 24 Circuitry Register Descriptions Figure 4 2 shows the two control word formats used to completely prog
68. is driven by OUT2 If A2DRV is cleared pin A2 is not driven 4 10 National Instruments Corporation Chapter 4 Programming The Event Strobe Register Group The Event Strobe Register Group consists of four registers that when written to cause the occurrence of certain events on the AT MIO 16D board such as clearing flags and starting A D conversions Descriptions of the four registers making up the Event Strobe Register Group are given on the following pages National Instruments Corporation 4 11 AT MIO 16D User Manual Programming Chapter 4 Start Convert Register Writing to the Start Convert Register location initiates an A D conversion Address Base address 8 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used Note A D conversions can be initiated in one of two ways by writing to the Start Convert Register by detecting an active low signal on the EXTCONV signal The EXTCONV signal is connected to pin 40 on the MIO 16 I O connector to OUT3 of the Am9513A and to the AO pin of the RTSI bus switch If EXTCONV is driven low by any one of these sources it prevents the Start Convert Register from initiating an A D conversion If the Start Convert Register is to initiate A D conversions the OUT3 signal should be initialized to a high impedance state any signal connected to pin 40 of the I O connector should be in a high impedance or high state and the pin of the RTSI bus switch
69. is simply written to or read from a selected port Mode 0 has the following features e Two 8 bit ports A and and two 4 bit ports upper and lower nibble of Port C e Any port can be input or output e Outputs are latched but inputs are not latched AT MIO 16D User Manual 3 18 O National Instruments Corporation Chapter 3 Theory of Operation Mode 1 This mode transfers data that is synchronized by handshaking signals Ports A and B use the eight lines of Port C to generate or receive the handshake signals This mode divides the ports into two groups Group A and Group B and has the following features e Each group contains one 8 bit data port Port A or Port B and one 4 bit control data port upper or lower nibble of Port e 8 bit data ports can be either input or output both of which are latched e The 4 bit ports are used for control and status of 8 bit data ports e Interrupt generation and enable and or disable functions are available Mode 2 This mode can be used for communication over a bidirectional 8 bit bus Handshaking signals are used in a manner similar to Mode 1 Interrupt generation and enable and or disable functions are also available Other features of this mode include the following e Used in Group A only Port A and upper nibble of Port C 8 bit bidirectional port Port A and a 5 bit control status port Port C e Latched inputs and outputs Single Bit Set Reset Feature Any
70. itself is never directly accessed Load Register The 16 bit read write Load register is used to control the effective length of the general counter Any 16 bit value may be written into the Load register That vaiue can then be transferred into the counter each time the Terminal Count TC occurs Terminal Count is defined as that period of time when the counter contents would have been zero if an external value had not been transferred into the counter Thus the terminal count frequency can be the input frequency AMD Am9513A Data Sheet divided by the value in the Load register In ali operating modes either the Load or Hold register will be transferred into the counter when TC occurs in cases where values are being accumulated in the counter the Load register action can become transparent by filling the Load register with all zeros Hold Register The 16 bit read write Hold register is dual purpose It can be used in the same way as the Load register thus offering an alternate source for module definition for the counter The Hold register may aiso be used to store accumulated counter values for later transfer to the host processor This allows the count to be sampied while the counting process proceeds without interruption Transfer of the counter contents into the Hold register is accomplished by the hardware interface in Some operating modes or by software commands at any time Counter Mode Register The 16 bit read writ
71. may be off by one count 10 This parameter assumes that the GATENA input is unused 16 bit bus mode or is tied high In cases where the GATENA input is used this timing specification must be met by both the GATE and GATENA inputs 11 Signals F1 F5 cannot be directly monitored by the user The phase difference between these signais will manifest itself by causing counters using two different F signals to count at different times on nominally simultaneous transi tions in the F signals F1 X2 12 This timing specification assumes that CS is active when ever RD or WR are active CS may be held active 13 This parameter assumes X2 is driven from an external gate _ with a square wave 14 This parameter assumes that the write operation is to the command register 15 This timing specification applies to single action com mands only e g LOAD ARM SAVE etc For double action commands such as LOAD AND ARM and DISARM AND SAVE TWHEH minimum 700 ns 16 1 short data write mode TWHRL and TWHWL mini mum 1000 ns 17 This parameter applies to the hardware retrigger save modes Q R and X CM7 1 and CM15 CM13 lt gt 000 This parameter ensures that the gating puise initiates hardware retrigger save operation 18 This parameter applies to hardware load source select modes S and V CM7 1 and 15 13 000 This represents the minimum hold time to ensure parameter that the GATE input
72. of the Am9513A SOURCE inputs The counter value can then be read to determine the number of edges that have occurred You can gate counter operation on and off during event counting Figure 2 37 shows connections for a typical event counting operation where a switch is used to gate the counter on and off DIG GND MIO 16 I O Connector AT MIO 16D Boar Figure 2 37 Event Counting Application with External Switch Gating To perform pulse width measurement program a counter to be level gated The pulse to be measured is applied to the counter GATE input Program the counter to count while the signal at the GATE input is either high or low If the counter is programmed to count an internal timebase then the pulse width is equal to the counter value multiplied by the timebase period National Instruments Corporation 2 39 AT MIO 16D User Manual Configuration and Installation Chapter 2 For time lapse measurement program a counter to be edge gated Apply an edge to the counter GATE input to start the counter You can program the counter to start counting after receiving either a high to low edge or a low to high edge If the counter is programmed to count an internal timebase then the time lapse since receiving the edge is equal to the counter value multiplied by the timebase period To measure frequency program a counter to be level gated and the rising or falling edges are counted in a signal applied to a SOURCE input The gate sign
73. of the counter will be transferred into the associated Hold registers This com mand is identical to issuing a DISARM command followed by a SAVE command Set TC Toggie Output Coding C7 C6 C5 C4 C2 CO i 1 1 0 1 N4 N2 Ni 001 lt N lt 101 Description The initial output level for TC Toggle mode is set HIGH for counter N selected by 4 N2 N1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 17 but does not appear at the counter output uniess TC Toggle mode CM2 1 CMO 010 is selected Clear TC Toggie Output Coding C7 C6 CS C4 C3 C2 Ci CO 001 lt N 101 Description The initial output level for TC Toggle mode is Cleared LOW for counter selected by 4 2 N1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 17 but does not appear at the counter output unless TC Toggle mode CM2 CM1 CMO 010 is selected Step Counter Coding 9 8 C7 C6 C5 C4 C3 C2 1 1 1 1 0 N4 001 lt N lt 101 Description Counter N is incremented or decremented by one depending on its operating configuration if the Counter Mode register associated with the selected counter has its CM3 bit cleared to zero this command will cause the counter to decrement by one If CM3 is set to a logic high this command will increment the counter by one The STEP command will take effect even
74. of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A lt 6 0 gt This capability provides a completely flexible signal interconnection scheme for any AT Series board sharing the RTSI bus The RTSI switch is programmed via its select and data inputs On the AT MIO 16D board nine signals are connected to pins A lt 6 0 gt of the RTSI switch with the aid of additional drivers The signals OUTI OUT2 OUTS FOUT and STOP TRIG are shared with the AT MIO 16D I O connector and Am9513A Counter Timer The signal SOURCES is connected to the Am9513A SOURCES pin The EXTCONV and START TRIG signals are shared with the I O connector and the data acquisition timing circuitry These onboard interconnections allow AT MIO 16D general purpose and data acquisition timing to be controlled over the RTSI bus as well as externally and allow the AT MIO 16D and the I O connector to provide timing signals to other AT boards connected to the RTSI bus AT MIO 16D User Manual 3 16 O National Instruments Corporation Chapter 3 Theory of Operation DIO 24 Functional Overview The block diagram in Figure 3 9 illustrates the key functional components of the AT MIO 16D DIO 24 circuitry Transceivers 82C55A PPI PC AT I O Channel Control Circuitry Connector Ss E Q Q lt o Interrupt Control Circuitry Figure 3 9 AT MIO 16D DIO 24 Block Diagr
75. onboard 6 9 MHz maximum 145 nsec period with a minimum pulse width of 70 nsec 200 uA 3 2mA DIO 24 Circuitry Specifications I O Signals Rating Absolute maximum voltage input rating Input Signal Specifications Input logic high voltage Input logic low voltage Input current 0 lt Ijin lt 5 V National Instruments Corporation 0 5 to 7 0 V with respect to GND Minimum Maximum 20 5 25 V 0 0 V 0 8 V 10 0 uA 10 0 pA 5 AT MIO 16D User Manual Specifications Output Signal Specifications Pin 49 at 5 V Output logic high voltage at Iout 200 UA Output logic low voltage at Iout 1 7 mA Darlington drive current REXT 750 VEXT 1 5 V Transfer Rates Maximum Typical Appendix A 1 0 A typical fused Minimum Maximum 24 5 0 V 0 0 V 0 45 V 1 0 mA 4 0 mA 500 kbytes sec 300 kbytes sec Note The transfer rate depends on both the computer speed and the software speed The maximum transfer rate shown previously is the result of running an assembly program which continuously writes a constant to an output port on an 8 MHz PC AT compatible The typical transfer rate is the result of running an assembly program which continuously reads data from memory and writes to an output port on an 8 MHz PC AT compatible Power Requirement from PC AT I O Channel Power consumption Physical Board dimensions connector Operating Environment Component temperature Relative humidi
76. output gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full scale 4 095 This output voltage should be 2 LSB For unipolar output Vafs 9 99756 and 1 2 LSB 1 22 mV e For analog output channel a Connect the voltmeter between DACO OUT pin 20 on the I O connector and AO GND pin 23 Set the analog output channel to 9 99756 V by writing 4 095 to the DAC Adjust trimpot 5 until the output voltage read is 9 99756 V 1 22 mV that is between 9 99634 and 9 99878 V e For analog output channel 1 a Connect the voltmeter between DACI OUT pin 21 on the I O connector and AO GND pin 23 Set the analog output channel to 9 99756 V by writing 4 095 to the DAC Adjust trimpot R4 until the output voltage read is 9 99756 V 1 22 mV that is between 9 99634 and 9 99878 V National Instruments Corporation 5 9 AT MIO 16D User Manual Appendix Specifications This appendix lists the specifications for the AT MIO 16D These are typical at 25 C unless otherwise stated The operating temperature range is 0 to 70 C MIO 16 Circuitry Specifications Analog Input Number of input channels Analog resolution Relative accuracy nonlinearity quantization error see explanation of specifications Integral nonlinearity Differential nonlinearity Differential analog input ranges Analog input range Common mode range Inst
77. procedure differs depending on input ranges and input configuration modes selected Two analog input calibration procedures are given below one for the two bipolar input configurations 10 to 10 V and 5 to 5 V and one for the unipolar input configuration to 10 V The calibration procedures presented here assume that your AT MIO 16D board is configured for DIFF input If necessary reconfigure your board for DIFF input before using the following calibration procedures To calibrate your board with a nondifferential input setting the procedure is similar to the procedures outlined below with the following exception the procedures given below apply the input calibration voltages across the positive and negative inputs for DIFF channel 0 For single ended input apply your calibration voltages between the channel 0 positive input and whichever ground system you are using refer to Chapter 2 Configuration and Installation for instructions on using single ended input connections Bipolar Input Calibration Procedure If your board is configured for bipolar input which provides the ranges 5 to 5 V or 10 to 10 V then complete the following procedure in the order given This procedure assumes that ADC readings are in the range 2 048 to 2 047 1 Adjust the amplifier input offset To adjust the amplifier input offset follow these steps a Connect both ACHO pin 3 on the I O connector and ACHS pin 4 to AI SENSE pin 19
78. rate for the AT MIO 16D is 100 ksamples sec AT MIO 16D User Manual 4 56 National Instruments Corporation Chapter 4 Programming Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A D Clear Register An A D conversion is initiated and stored in the A D FIFO every time a low to high edge is detected on the EXTCONV input See Chapter 2 Configuration and Installation for EXTCONV signal specifications Programming Multiple A D Conversions with Channel Scanning The data acquisition programming sequences described earlier program the AT MIO 16D for multiple A D conversion on a single input channel You can also program the AT MIO 16D for scanning analog input channels and switching gain settings during the data acquisition operation The sequence of A D channels and gain settings called the scan sequence is programmed into the mux gain memory There are two types of multiple A D conversions with channel scanning continuous channel scanning and interval channel scanning Continuous channel scanning cycles through the scan sequence in the mux gain memory and repeats the scan sequence until the sample counter terminates the data acquisition There is no delay between the cycles of the scan sequence Continuous channel scanning can be thought of as a round robin approach to scanning multiple channels Interval channel scanning gives each scan sequence a programmed time interval called a scan interval
79. relative accuracy of the system is therefore limited to the worst case deviation from the ideal correspondence a straight line excepting noise If a D A system has been calibrated perfectly then the relative accuracy specification reflects its worst case absolute error Differential nonlinearity in a D A system is a measure of deviation of code width from 1 LSB In this case code width is the difference between the analog values produced by consecutive digital codes A specification of 1 LSB differential nonlinearity ensures that the code width is always greater than 0 LSBs guaranteeing monotonicity and is always less than 2 LSBs AT MIO 16D User Manual A 4 National Instruments Corporation Appendix Specifications Digital MIO 16 I O Connector only Compatibility Output current source capability Output current sink capability Timing I O Number of channels Resolution Base clock available Base clock accuracy Compatibility Counter input frequency Current source capability Current sink capability Transistor transistor logic TTL compatible Can source 2 6 mA and maintain Voy at 2 4 V Can sink 24 mA and maintain Vo at 0 5 V Four three counter timers and one frequency output 16 bit for 3 counter timers 4 bit for frequency output channel 1 MHz 100 kHz 10 kHz 1 kHz 100 Hz 0 01 TTL compatible inputs and outputs Counter gate and source inputs are pulled up with 4 7 resistors
80. signal lines The RTSI switch is programmed by shifting a 56 bit routing pattern into the RTSI switch and then loading the internal RTSI Switch Control Register The routing pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register The RTSI Switch Control Register is then loaded by writing to the RTSI Switch Strobe Register Bit descriptions for the registers making up the RTSI Switch Register Group are given on the following pages National Instruments Corporation 4 33 AT MIO 16D User Manual Programming Chapter 4 RTSI Switch Shift Register The RTSI Switch Shift Register is written to in order to load the RTSI switch internal 56 bit Control Register with routing information for switching signals to and from the RTSI bus trigger lines The RTSI Switch Shift Register is a 1 bit register and must be written to 56 times to shift the 56 bits into the internal register Address Base address 1E hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Bit Name Description 7 1 X Don t care bits 0 RSI The name of this bit stands for RTSI switch serial input This bit is the serial input to the RTSI switch Each time the RTSI Switch Shift Register is written to the value of this bit is shifted into the RTSI switch See the Programming the RTSI Switch section later in this chapter for more information AT MIO 16D User Manual 4 54 National Instruments Corporation Chapt
81. the START TRIG starts the counters thereby initiating a data acquisition sequence The data acquisition operation is initiated by the high to low edge of the applied pulse Figure 2 35 shows the timing requirements for the START TRIG signal National Instruments Corporation 2 37 AT MIO 16D User Manual Configuration and Installation Chapter 2 tw 50 nsec minimum First A D conversion starts within one sample interval from this point Figure 2 35 START TRIG Signal Timing The minimum allowed pulse width is 50 nsec The first A D conversion starts within one sample interval from the high to low edge The sample interval is controlled by Counter 3 There is no maximum pulse width limitation however START TRIG should be high for at least 50 nsec before going low The START TRIG signal is one LS TTL load and is pulled up to 5 V through a 4 7 kQ resistor The STOP TRIG pin is used during AT MIO 16D pretriggered data acquisition operations In pretriggered mode data is acquired but no sample counting occurs until a rising edge is applied to the STOP TRIG pin This causes the sample counter to then start counting conversions The acquisition then completes when the sample counter decrements to zero This mode acquires data both before and after a hardware trigger is received Figure 2 36 shows the timing requirements for the STOP TRIG signal V STOP TRIG ty 50 nsec minimum First sample counting occurs within one sam
82. the counting process CM3 and 4 operate independently of the others and control up down and BCD binary counting They may be combined freely with other control bits to form many types of counting configurations The other three bits and the Gating Control field interact in complex ways Bit CM5 controls the repetition of the count process When CMS 1 counting will proceed in the specified mode until the counter is disarmed When 5 0 the count process will proceed only until one full cycie of operation occurs This may occur after one or two TC events The counter is then disarmed automatically The single or double TC requirement will depend on the state of other control bits Note that even if the counter is automat cal ly disarmed upon a TC it always counts the count source edge which generates the trailing TC edge When TC occurs the counter is always reloaded with a value from either the Load register of the Hold register Bit CM6 specifies the source options for reloading the counter When CM6 0 the contents of the Load register will be transferred into the counter at every occurrence of TC When CM6 1 the counter reload location will be either the Load or Hold Register The reload location in this case may be controlled extemally by using a Gate pin Modes S and V or may alternate on each TC Modes G through L With alternating sources and with the TC Toggled output selected the duty cycie of the output wavef
83. the signal 6 MHz maximum National Instruments Corporation 4 63 AT MIO 16D User Manual Programming Chapter 4 Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register Write 2 to the Am9513A Data Register to store the Counter 3 load value Write FF44 to the Am9513A Command Register to load Counter 3 Write FFF3 to the Am9513A Command Register to step Counter 3 down to one mp g Write the desired sample interval to the Am9513A Data Register to store the Counter 3 load value e If the sample interval is between 2 and FFFF 65 535 decimal write the sample interval to the Am9513A Data Register e If the sample interval is 10000 65 536 decimal write 0 to the Am9513A Data Register h Write FF24 to the Am9513A Command Register to arm Counter 3 After you complete this programming sequence Counter 3 is configured to generate A D conversion pulses as soon as application of a trigger causes it to be enabled 3 Program the sample counter Use Counters 4 and 5 of the Am9513A Counter Timer as the sample counter The sample counter tallies the number of A D conversions initiated by Counter 3 and stops Counter 3 when the desired sample count is reached The sample count should be programmed as a multiple of the number of entries in the mux gain memory If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If
84. to 2 17 straight binary mode settings 2 17 two s complement mode 2 17 bit descriptions 16 32CNT 4 5 2SCADC 4 5 A2DRV 4 10 A2RCV 4 10 AADRV 4 10 AARCV 4 10 ADIO 3 0 4 31 4 32 BDIO lt 3 0 gt 4 31 4 32 BYTEPTR 4 29 lt 7 0 gt 4 28 CONVAVAIL 4 6 CONVINTEN 4 4 CW lt 7 0 gt 4 40 D lt 7 0 gt 4 37 4 38 4 39 D lt 11 0 gt 4 17 4 18 AT MIO 16D User Manual Index 6 O National Instruments Corporation D lt 15 0 gt 4 24 4 27 DAQEN 4 5 DAQPROG 4 7 DAQSTOPINT 4 6 DAQSTOPINTEN 4 4 DBDMA 4 4 DMACH 4 7 DMAEN 4 5 DMATCINT 4 7 DOUTENO 4 9 DOUTENI 4 9 GAIN lt 1 0 gt 4 7 4 22 GINT 4 6 IBFA 4 83 4 88 IBFB 4 83 INT2EN 4 9 INTEI 4 88 INTE2 4 88 INTEA 4 83 4 85 INTEB 4 83 4 85 INTEN 4 9 INTRA 4 83 4 85 4 88 INTRB 4 83 4 85 I O 4 83 4 85 4 88 LASTONE 4 23 LDAC 4 10 lt 2 0 gt 4 8 lt 3 0 gt 4 23 MC lt 3 0 gt 4 21 MUXOEN 4 8 MUXIEN 4 7 OBFA 4 85 4 87 OBFB 4 85 OUT 5 1 4 29 OUTZINT 4 6 OVERFLOW 4 7 OVERRUN 4 7 RSI 4 34 SCANDIV 4 5 SCANEN 4 5 SCN2 4 10 TCINTEN 4 4 board configuration See calibration procedures configuration cables and cabling custom cables 1 6 National Instruments Corporation Index 7 Index AT MIO 16D User Manual Index DIO 24 cabling 2 51 to 2 52 field wiring considerations 2 50 MIO 16 cabling 2 50 to 2 51 standard cables 1 6 to 1 7 calibration procedures analog inp
85. to Counter N as shown in Figure 12 The output of the AND gate is then used as the gating signal for Counter N Data Pointer Sequencing Bit MM14 controls the Data Pointer logic to enable or disable the automatic sequencing functions When 14 1 the contents of the Data Pointer can be changed only directly by entering a command When MM14 0 several types of automatic sequencing of the Data Pointer are available These described in the Data Pointer register section of this document AMD Am9513A Data Sheet Figure 12 Gating Control Thus the host processor by controlling MM14 may repetitive ly read write a single internal location or may sequentially read write groups of locations Bit MM14 can be loaded by writing to the Master Mode register or can be set or cleared by software command Sealer Ratios Master Mode bit MM15 controis the counting configuration of the Frequency Scaler counter When 15 0 the Scaler divides the oscillator frequency in binary steps so that each subfrequency is 1 16 of the preceding frequency When 15 1 the Scaler divides in BCD steps so that adjacent frequencies are related by ratios of 10 instead of 16 see Figure 13 Seating MM15 0 osc Ft 16 Fi 256 F1 4 096 F1 65 536 Figure 13 Frequency Scaler Ratios Am9513A National Instruments Corporation E 13 2 127 AT MIO 16D User Manual AMD Am9513A Data Sheet Appendix E
86. trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Preface This manual describes the electrical and mechanical aspects of the AT MIO 16D and contains information concerning its operation and programming The AT MIO 16D a member of the National Instruments AT Series of expansion boards for the IBM PC AT and compatible computers combines the functionality of two popular National Instrument
87. volume for this device Consult the local AMD sales office to confirm availability of specific valid 5962 8552301 LAX combinations or to check for newly released valid Group A Tests Group A tests consist of Subgroups 1 2 3 7 8 9 10 11 2 118 9513 AT MIO 16D User Manual 4 National Instruments Corporation Appendix E AMD Am9513A Data Sheet ORDERING INFORMATION continued APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges APL Approved Products List products are fully compliant with MIL STD 883C requirements The order number Valid Combination for APL products is formed by a combination of a Device Number b Speed Option if applicable c Device Class d Package Type e Lead Finish A tem LEAD FINISH A Hot Solder DIP d PACKAGE TYPE 40 Pin Ceramic DIP CD 040 U 44 Pin Ceramic Leadiess Chip a DEVICE NUMBER DESCRIPTION Am9513A System Timing Controller Valid Combinations Valid Combinations list configurations planned to be binati supported in volume for this device Consuit the local AMD Valid ms sales office to confirm availability of specific valid 513 BUA combinations or to check for newiy reieased valid binati Group A Tests Group A tests consist of Subgroups 1 2 3 7 8 9 10 11 Am9513A 2 419 National Instruments Corporation E 5 AT M
88. 0 I O Configurations Group A Group B Upper nibble of Port 2 _ Lower nibble of Port C Mode 0 Programming Example Main define BASE _ ADDR ESS define PORTAoffset define PORTBoffset define PORTCoffset define CNFGoffset register unsigned int porta char valread Calcula porta BASE portb BASE portc BASE cnfg BASE National Instruments Corporation te register ADDRE ADDRE ADDRE ADDRE 0 220 0x00 0x01 0x02 0x03 a addresses PORTAoffset PORTBoffset PORTCoffset CNFGoffset 4 Board located at address 220 Offset for Port A Offset for Port B Offset for Port C Offset for CNFG portb portc cnfg Variable to store data read froma port AT MIO 16D User Manual Programming ou ou ou ou ou ou valread inp porta EXAMPLE 1 cnfg 0x80 tp porta 0x12 tp portb 0x34 tp portc 0x56 EXAMPLE 2 tp cnfg 0x90 tp portb 0x22 tp portc 0x55 EXAMPLE 3 outp cnfg 0x82 EXAMPLE 4 outp cnfg 0x89 Mode 1 Strobed Input Ports A B and C are Write data to Port A Write data to Port B Write data to Port C Chapter 4 outputs v P
89. 100 XXXXXNXX Oxxx0111 Oxxx0110 XXXXNXXX Oxxx1001 1000 XXXNXXXX Oxxx1011 Oxxx1010 XXNXXXXX Oxxx1101 Oxxx1100 XNXXXXXX Oxxx1111 Oxxx1110 NXXXXXXX 0 1 2 3 4 5 6 7 82C55A Modes of Operation The three basic modes of operation for the 82C55A are as follows e Mode 0 Basic I O e Mode 1 Strobed I O e Mode 2 Bidirectional bus The 82 55 also has a single bit set reset feature for Port C The 8 bit control word also E this function For additional information refer to Appendix Oki MSM amp 2C55A Data Mode 0 Basic I O Mode 0 can be used for simple input and output operations for each of the ports No handshaking is required data is simply written to or read from a selected port Mode 0 has the following features e Two 8 bit ports and B and two 4 bit ports upper and lower nibble of Port Any port can be input or output e Outputs are latched but inputs are not latched The 16 possible Mode 0 I O configurations are shown in Table 4 9 Notice that bit 7 of the control word is set when programming the mode of operation for each port AT MIO 16D User Manual 4 80 National Instruments Corporation Chapter 4 Word Number Bit Port A Port Port Port 76543210 10000000 10000001 10000010 10000011 10001000 10001001 10001010 10001011 10010000 10010001 10010010 10010011 10011000 10011001 10011010 10011011 0 1 2 3 4 5 6 7 8 9 Programming Table 4 9 Mode
90. 13A registers is included in Appendix E Am9513A Data Sheet Bit descriptions for the Am9513A Counter Timer Register Group registers are given in the following pages AT MIO 16D User Manual 4 26 National Instruments Corporation Chapter 4 Programming Am9513A Data Register The Am9513A Data Register allows any of the 18 internal registers of the Am9513A to be written to or read from The Am9513A Command Register must be written to in order to select the register to be accessed by the Am9513A Data Register The internal registers accessed by the Am9513A Data Register are as follows e Counter Mode Registers for Counters 1 2 3 4 and 5 Counter Load Registers for Counters 1 2 3 4 and 5 e Counter Hold Registers for Counters 1 2 3 4 and 5 The Master Mode Register The Compare Registers for Counters 1 and 2 these registers are 16 bit registers Bit descriptions for each of these registers are included in Appendix E Am9513A Data Sheet Address Base address 18 hex Type Read and write Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 2 4 3 2 1 0 D15 D14 D13 D12 D10 D9 D7 D6 D5 D4 D3 D2 DI DO Bit Name Description 15 0 D lt 15 0 gt These 16 bits are loaded into the Am9513A Internal Register currently selected See Appendix E 9513 Data Sheet for the detailed bit descriptions of the 18 registers accessed through the Am9513A Data Register N
91. 151 is similar to Mode J except that counting will not begin until a Gate edge is applied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded The counter will start counting proceed unti the second TC Note that after application of a triggering Gate edge the Gate input will be disregarded for the remainder of the count cycle This differs from Mode where the gate can be modulated throughout the count cycle to stop and start the counter On the first TC after application of the triggering Gate edge the counter will be reloaded from the Hold register On the second TC the counter will be reloaded from the Load register and counting will stop until a new gate edge is issued to the counter Note that unlike Mode new Gate edges are required after every second TC to continue counting Software Triggered Strobe with Level Gating and Hardware Retriggering cuts cusa curs ca cus own cvs cue ee x x xixIix CMT 5 cm4 2 x shown in Figure 15n provides software triggered strobe with levei gating that is also hardware retriggerabie The counter must be issued an ARM command before counting can occur Once armed the counter will count all source edges which occur while the gate is active and disregard those source edges which occur whil
92. 2 Program the sample interval counter Use Counter 3 of the Am9513A Counter Timer as the sample interval counter Counter 3 can be programmed to generate a pulse once every N counts is referred to as the sample interval that is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the sample interval counter use the following programming sequence All writes are 16 bit operations All values given are hexadecimal a Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register b Write the mode value to the Am9513A Data Register to store the Counter 3 mode value Use one of the following mode values 8B25 Selects 1 MHz clock 8C25 Selects 100 kHz clock 8025 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum c Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register d Write 2 to the Am9513A Data Register to store the Counter 3 load value e Write FF44 to the Am9513A Command Register to load Counter 3 f Write FFF3 to the Am9513
93. 2 048 to 2 047 Data Acquisition Timing Circuitry A data acquisition operation refers to the process of taking a sequence of A D conversions with the sample interval the time between successive A D conversions carefully timed The data acquisition timing circuitry consists of various clocks and timing signals Three types of data acquisition are supported by the AT MIO 16D board single channel data acquisition multiple channel data acquisition with continuous scanning and multiple channel data acquisition with interval scanning Scanned data acquisition uses the multiplexer counter and the mux gain memory to automatically switch between analog input channels during data acquisition Continuous scanning cycles through the mux gain memory without any delays between cycles Interval scanning assigns a National Instruments Corporation 3 7 AT MIO 16D User Manual Theory of Operation Chapter 3 time interval called the scan interval to each cycle through the mux gain memory The scan interval is basically the time between starts for each cycle through the mux gain memory Data acquisition timing consists of signals that initiate a data acquisition operation initiate individual A D conversions gate the data acquisition operation and generate scanning clocks The sources for these signals can be supplied by timers on the AT MIO 16D board by signals connected to the AT MIO 16D I O connector or by signals from other AT Series boards connecte
94. 2 V minimum Vj input logic low voltage 0 8 V maximum Input load current 10 WA maximum Am9513A digital output specifications referenced to DIG GND Voy Output logic high voltage 2 4 V minimum Voz output logic low voltage 0 4 V maximum output source current at 200 HA maximum Io output sink current at VoL 3 2 mA maximum Output current high impedance state 25 LA maximum Figure 2 39 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of the Am9513A V SOURCE 145 nsec minimurr 70 nsec minimum 100 nsec minimun 10 nsec minimum 145 nsec minimurr 300 nsec maximun Figure 2 39 General Purpose Timing Signals National Instruments Corporation 2 41 AT MIO 16D User Manual Configuration and Installation Chapter 2 The GATE and OUT signal transitions in Figure 2 39 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram with the source signal inverted and referenced to the falling edge of the source signal applies to the case in which the counter is programmed to count falling edges The signal applied at a SOURCE input can be used as a clock source by any of the Am9513A counter timers and by the Am9513A frequency division output FOUT The signal applied to a SOURCE input must not exceed a frequency of 6 MHz for proper operation of th
95. 3 11 unipolar and bipolar output 3 11 voltage reference source 3 11 analog output configuration 2 15 to 2 18 external reference selection 2 15 internal reference selection factory setting 2 15 to 2 16 polarity selection bipolar output selection 2 16 to 2 17 unipolar output selection 2 18 RTSI bus clock selection 2 18 to 2 20 Analog Output Register Group DACO Register 4 17 DACI Register 4 18 INT2Clear Register 4 19 register map 4 1 analog output signal connections 2 33 to 2 34 analog output specifications explanation of A 4 National Instruments Corporation Index 5 AT MIO 16D User Manual Index list of A 4 AO GND signal 2 23 2 33 to 2 34 applying a trigger See trigger applying AT MIO 16D See also specifications theory of operation block diagram 3 1 definition of v description of 1 1 to 1 3 illustration of 1 2 interface with other AT series boards 1 2 to 1 3 kit contents 1 3 to 1 4 optional equipment 1 5 to 1 7 optional software 1 4 parts locator diagram 2 2 unpacking 1 7 B base I O address default settings for National Instrument products 2 3 to 2 5 example switch settings 2 4 factory setting for 2 3 switch settings with base I O address and address space 2 5 verifying the address space 2 3 BDIO lt 0 3 gt signal 2 23 bipolar input calibration procedure 5 4 to 5 5 bipolar output analog output circuitry 3 11 calibration procedure 5 7 to 5 8 configuration jumper settings 2 16
96. 30 mV for 0 to 10 V range System noise figures are for 0 15 LSB rms for gains 1 to 10 20 V range multiply by 2 for 0 25 LSB rms for gain 100 10 V range 0 5 LSB rms for gain 500 Explanation of Analog Input Specifications Relative accuracy is a measure of the linearity of an ADC However relative accuracy is a tighter specification than a nonlinearity specification Relative accuracy indicates the maximum deviation from a straight line for the analog input to digital output transfer curve If an ADC has been calibrated perfectly then this straight line is the ideal transfer function and the relative accuracy specification indicates the worst deviation from the ideal that the ADC permits A relative accuracy specification of 1 LSB is roughly equivalent to but not the same as a 1 2 LSB nonlinearity or integral nonlinearity specification because relative accuracy encompasses both nonlinearity and variable quantization uncertainty a quantity often mistakenly assumed to be exactly 2 LSB Although quantization uncertainty is ideally 2 LSB it can be different for each possible digital code and is actually the analog width of each code Thus it is more specific to use relative accuracy as a measure of linearity than it is to use what is normally called nonlinearity because relative accuracy ensures that the sum of quantization uncertainty and analog to digital A D conversion error does not exceed a given amount Integral nonlinearity i
97. 4 88 single bit set reset feature 4 89 control word formats 4 79 interrupt handling 4 90 to 4 91 Port C set reset control words 4 80 register descriptions 4 78 to 4 80 programming MIO 16 See also programming multiple A D conversions MIO 16 registers Am9513A Counter Timer 4 73 analog input circuitry 4 43 to 4 46 A D FIFO output binary formats 4 44 to 4 45 clearing analog input circuitry 4 46 to 4 46 initiating A D conversions 4 43 reading A D conversion results 4 44 selecting analog input channel and gain 4 43 straight binary mode A D conversion values 4 45 AT MIO 16D User Manual Index 18 National Instruments Corporation Index two s complement mode A D conversion values 4 45 analog output circuitry 4 71 to 4 72 analog output voltage versus digital code bipolar mode 4 72 unipolar mode 4 71 formulas for voltage output 4 71 voltage control 4 71 to 4 72 DMA operations 4 76 to 4 77 initialization 4 41 to 4 43 Am9513A Counter Timer 4 42 analog output circuitry 4 43 MIO 16 circuitry 4 41 to 4 43 interrupts 4 77 to 4 78 MIO 16 digital I O circuitry 4 72 to 4 73 register programming considerations 4 41 resetting hardware after data acquisition Counter 2 4 69 Counter 3 4 69 Counter 4 4 70 Counter 5 4 70 RTSI switch 4 73 to 4 76 interrupt programming 4 77 to 4 78 procedure for programming 4 76 RTSI switch signal connection 4 74 programming multiple A D conversions MIO 16 continuous channel scan
98. 4 PORTC Register Port C of the DIO 24 circuitry is special in the sense that it can be used as an 8 bit I O port like Port A and Port B if neither Port A nor Port B is used in handshaking latched mode If either Port A or Port B is configured for latched I O some of the bits in Port C are used for handshaking signals See DIO 24 Circuitry Programming Considerations later in this chapter for a description of the individual bits in the DIO 24 PORTC Register Address Base address 0x02 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 DG sp Bit Name Description 7 0 D lt 7 0 gt These eight bits are written to or read from Port C National Instruments Corporation 4 39 AT MIO 16D User Manual Programming Chapter 4 DIO 24 CNFG Register The DIO 24 CNFG Register can be used to configure Port A Port B and Port C of the DIO 24 circuitry as inputs or outputs as well as selecting simple mode basic I O or handshaking mode strobed I O for transfers See DIO 24 Circuitry Programming Considerations later in this chapter for a description of the individual bits in the DIO 24 CNFG Register Address Base address 0x03 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Bit Name Description 7 0 CW lt 7 0 gt These eight bits are written to or read from the DIO 24 CNFG Register AT MIO 16D User Manual 4 40 National In
99. 40 Am9513A AT MIO 16D User Manual E 26 National Instruments Corporation Appendix Note See Figure 15 for restrictions on Count Control and Gating Control bit combinations Figure 16 Counter Mode Register Bit Assignments Figure 17 Output Control Logic National Instruments Corporation Am9513A E 27 20 BE Wan we vo AMD Am9513A Data Sheet Hi 3 ri ER 100 Inactive Output High impedance 101 Active Low Terminal Count 110 Megai 111 Regal DF003784 2 141 AT MIO 16D User Manual 2 142 AMD 9513 Data Sheet WF004780 Figure 18 Counter Output Waveforms The other output form TC Toggied uses the trailing edge of TC to toggle a flip flop to generate an output level instead of a pulse The toggle output is half the frequency of TC The TC Toggied output will frequently be used to generate variable duty cycle square waves in Operating Modes G through in Mode L the TC Toggled output can be used to generate a one shot function with the delay to the start of the output puise and the width of the output pulse separately programma ble With selection of the minimum delay to the start of the pulse the output will toggle on the second source pulse following application of the triggering Gate edge Note that the TC Toggled output form contains no implication about whether the output is active high or active low Unlike the TC o
100. 5 scanned data acquisition 4 68 interval channel scanning pseudo simultaneous 4 62 to 4 68 applying a trigger 4 67 clearing A D circuitry 4 67 enabling scanning data acquisition operation 4 67 multiple channel data acquisition rates 4 68 overflow and overrun conditions 4 68 overview 4 57 resetting multiplexer counter 4 67 sample counter programming 4 64 to 4 65 sample interval counter programming 4 63 to 4 64 scan interval counter programming 4 66 servicing data acquisition operation 4 67 to 4 68 setting up analog channel and gain selection sequence 4 63 single input channel 4 46 to 4 51 applying a trigger 4 50 clearing A D circuitry 4 49 to 4 50 enabling data acquisition operation 4 50 overflow and overrun conditions 4 50 to 4 51 sample counter programming 4 48 to 4 49 sample interval counter programming 4 47 to 4 48 selecting input channel and gain 4 47 servicing data acquisition operation 4 50 to 4 51 steps for 4 46 to 4 47 multiple channel scanned data acquisition 3 9 multiplexer input 3 6 multiplexer counter resetting continuous channel scanning round robin 4 61 interval channel scanning pseudo simultaneous 4 67 Mux Counter Register 4 21 mux gain memory analog input circuitry 3 6 data acquisition timing circuitry 3 9 Mux Gain Register 4 22 to 4 23 MUXCTRCLK signal 3 9 N noise minimizing environmental noise 2 50 system noise A 3 nonreferenced single ended NRSE input configu
101. 5 to 5 5 to 5 V 2 5 to 2 5 V 1 25 to 1 25 V 0 625 to 0 625 V 0 5 to 0 5 V 50 mV to 50 mV 10 mV to 10 mV 10 to 10 V 10 to 10 V 5 to 5 V 2 5 to 2 5 V 1 25 to 1 25 V l to 1 V 0 1 to 0 1 V 20 mV to 20 mV The value of 1 LSB of the 12 bit ADC that is the voltage increment corresponding to a change of 1 count in the ADC 12 bit count AT MIO 16D User Manual 2 14 National Instruments Corporation Chapter 2 Configuration and Installation Analog Output Configuration You can select different analog output configurations by using the jumper settings shown in Table 2 5 The following paragraphs describe in detail each of the analog output configurations Analog Output Reference Selection Each DAC can be connected to the AT MIO 16D internal reference of 10 V or to the external reference signal connected to the EXTREF pin on the I O connector This signal applied to EXTREF must be between 10 V and 10 V Both channels need not be configured the same way External Reference Selection You select the external reference signal for each analog output channel by setting the following jumpers Analog Output Channel 0 W3 External reference signal connected to DAC 0 reference input Analog Output Channel 1 W2 External reference signal connected to DAC 1 reference input This configuration is shown in Figure 2 15 DAC DAC Channel 0 Channel 1 Figure 2 15 External Reference Confi
102. 65 535 or 32 bit for counts up to 232 1 If a 16 bit counter is needed Counter 4 of the Am9513A Counter Timer is used If more than 16 bits are needed Counter 4 is concatenated with Counter 5 of the Am9513A to form a 32 bit counter The sample counter decrements its count each time the sample interval counter generates an A D conversion pulse and the sample counter stops the data acquisition process when it counts down to zero You can trigger the sample counter externally with the STOP TRIG input on the AT MIO 16D I O connector The counter does not begin counting the A D conversion pulses until a rising edge signal occurs on STOP TRIG With this method A D conversion samples can be collected both before and after a hardware trigger is received You can initiate the data acquisition process by writing to the Start DAQ Register on the AT MIO 16D board or by applying an active low pulse to the START TRIG input on the AT MIO 16D I O connector These triggers start the sample interval and sample counters The sample interval counter then manages the data acquisition process until the sample counter reaches Zero AT MIO 16D User Manual 3 6 O National Instruments Corporation Chapter 3 Theory of Operation Single Channel Data Acquisition During single channel data acquisition the mux gain memory is set up to select the gain and analog input channel before data acquisition is initiated These gain and multiplexer settings remain constant durin
103. 6D Board The MIO 16 hardware must be initialized for the circuitry to operate properly To initialize the MIO 16 hardware complete these steps 1 Write 0 to Command Register 1 16 bit write 2 Write 0 to Command Register 2 16 bit write 3 Write 0 to the Mux Gain Register 4 Initialize the Am9513A described below 5 Write 0 to the A D Clear Register 6 Write 0 to the INT2CLR Register 16 bit write This sequence leaves the AT MIO 16D circuitry in the following state e DMA disabled e All interrupts disabled e Outputs of counter timers in high impedance state e Analog input circuitry initialized A D FIFO cleared e Analog input channel 0 selected National Instruments Corporation 4 41 AT MIO 16D User Manual Programming Chapter 4 e Gain of 1 selected e pins on the RTSI switch configured as input pins Initializing the Am9513A Follow the sequence below to initialize the Am9513A Counter Timer writes are 16 bit operations All values are given in hexadecimal 1 Issue a master reset by writing FFFF to the Am9513A Command Register 2 Setup Am9513A 16 bit mode by writing FFEF to the Am9513A Command Register 3 Point to the Am9513A Master Mode Register by writing FF17 to the Am9513A Command Register 4 Load the master mode value into the Am9513A Master Mode Register by writing F000 to the Am9513A Data Register 5 To initialize all five counters for ctr 1 to 5 follow these step
104. 6D board Field Wiring Considerations Accuracy of measurements made with the AT MIO 16D can be seriously affected by environmental noise if proper considerations are not taken into account when running signal wires between signal sources and the AT MIO 16D board The following recommendations mainly apply to analog input signal routing to the AT MIO 16D board though they are applicable for signal routing in general You can minimize noise pickup and maximize measurement accuracy by doing the following e Use individually shielded twisted pair wires to connect analog input signals to AT MIO 16D With this type of wire the signals attached to the CH and CH inputs are twisted together and then covered with a shield This shield is then connected only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference e Use differential analog input connections to reject common mode noise The following recommendations apply for all signal connections to the AT MIO 16D e Physically separate AT MIO 16D signal lines from high current or high voltage lines These lines are capable of inducing currents in or voltages on the AT MIO 16D signal lines if they run in parallel paths at a close distance Reduce the magnetic coupling between lines by separating them by a reasonable distance if they run in parallel or by running the lines at
105. 7 AT MIO 16D User Manual Appendix G Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster National Instruments provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 00 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 848400 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 National Instruments Corporation G 1 Fax Number 03 879 9179 0662 437010 19 02 757 03 11 45 76 71 11 90 502 2930 1 48 14 24 14 089 714 60 35 02 48301915 03 3788 1923 95 800 010 0793 03480 30673 32 848600 2265887
106. A Command Register to step Counter 3 down to 1 National Instruments Corporation 4 47 AT MIO 16D User Manual Programming Chapter 4 g Write the desired sample interval to the Am9513A Data Register to store the Counter 3 load value e If the sample interval is between 2 and FFFF 65 535 decimal write the sample interval to the Am9513A Data Register e Ifthe sample interval is 10000 65 536 decimal write 0 to the Am9513A Data Register h Write FF24 to the Am9513A Command Register to arm Counter 3 After you complete this programming sequence Counter 3 is configured to generate A D conversion pulses as soon as application of a trigger causes it to be enabled 3 Program the sample counter Use Counters 4 and 5 of the Am9513A Counter Timer as the sample counter The sample counter tallies the number of A D conversions initiated by Counter 3 and stops Counter 3 when the desired sample count is reached If the desired sample count is 65 536 or less use only Counter 4 making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 use both Counters 4 and 5 Sample Counts 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the following programming sequence The minimum permitted sample count is two writes are 16 bit operations values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Registe
107. A4 with the signal OUTS set the AA4DRV bit in Command Register 2 Otherwise clear the A4DRV bit drive the signal STOP TRIG from pin A4 of the RTSI switch set the A4RCV bit in Command Register 2 Otherwise clear the A4RCV bit Note If both the A4DRV and A4RC bits are set the STOP TRIG signal is driven by the signal OUTS This arrangement is probably not desirable AT MIO 16D User Manual 4 74 National Instruments Corporation Chapter 4 Programming Programming the RTSI Switch The RTSI switch can be programmed to connect any of the signals on the A side to any of the signals on the B side and vice versa To do this a 56 bit pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register and then writing to the RTSI Switch Strobe Register to load the pattern into the RTSI switch The 56 bit pattern is made up of two 28 bit patterns one for side A and one for side B of the RTSI switch The low order 28 bits select the signal sources for the B side pins The high order 28 bits select the signal sources for the A side pins Each of the 28 bit patterns are made up of seven 4 bit fields one for each pin The 4 bit field selects the signal source and the output enable for the pin Figure 4 1 shows the bit map of the RTSI switch 56 bit pattern Bit Number 55 51 47 43 39 35 31 27 23 APPT AO Control f Jor Bit Number 30 Figure 4 1 RTSI Switch Control Pattern In Figure 4 1
108. AO GND ADIOO ADIOI ADIO2 ADIO3 DIG GND 5 EXTSTROBE STOP TRIG SOURCEI OUTI GATE2 SOURCES OUTS AI GND ACH8 ACH9 ACHIO ACHII ACHI2 13 14 15 DACO OUT EXTREF DIG GND BDIOO BDIOI BDIO2 BDIO3 5 SCANCLK START TRIG EXTCONV GATEI SOURCE2 OUT2 GATES FOUT Figure 2 25 MIO 16 I O Connector Pin Assignments AT MIO 16D User Manual National Instruments Corporation Chapter 2 Configuration and Installation MIO 16 Signal Connection Descriptions Pin Signal Name Reference Description 1 2 AI GND N A Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements 3 18 lt 0 15 gt AIGND Analog Input Channels 0 through 15 In differential mode the input is configured for up to eight channels In single ended mode the input is configured for up to 16 channels 19 AI SENSE AIGND Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground 20 DACO OUT AOGND Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 21 DACI OUT AOGND Analog Channel Output This pin supplies the voltage output of analog output channel 1 22 EXTREF AOGND External Reference This is the external reference input for the analog output ci
109. AT MIO 16D User Manual Multifunction I O Board for the PC AT March 1995 Edition Part Number 320489 01 Copyright 1992 1995 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 800 328 2203 512 794 5678 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 Limited Warranty The AT MIO 16D is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instru
110. C An 82C55A PPI controls the 24 bits of digital I O The 82 55 is very flexible and powerful when interfacing with peripheral equipment can operate in either a unidirectional or bidirectional mode and can generate interrupt request outputs You can program the 82C55A for almost any 8 bit or 16 bit digital I O application The 100 pin connector of the AT MIO 16D breaks out into two standard 50 pin female connectors via a cable assembly The pin assignments for these connectors are compatible with standard 24 channel digital I O applications Figure 1 1 shows the AT MIO 16D interface board National Instruments Corporation 1 1 AT MIO 16D User Manual Introduction Chapter 1 Figure 1 1 AT MIO 16D Interface Board You can use the AT MIO 16D with its multifunction analog digital and timing I O in many applications including the automation of machine and process control level monitoring and control instrumentation electronic testing and many others You can use the multichannel analog input for signal and transient analysis data logging and chromatography The two analog output channels are useful for machine and process control analog function generation 12 bit resolution voltage source and programmable signal attenuation You can use the eight TTL compatible digital I O lines for machine and process control intermachine communication and relay switching control The three 16 bit counter timers can be used for such function
111. CES This pin is from the Am9513A Counter 5 signal GATES This pin is from the Am9513A Counter 5 signal OUTS This pin is from the Am9513A Counter 5 signal Frequency Output This pin is from the Am9513A FOUT signal B 3 AT MIO 16D User Manual Appendix DIO 24 I O Connector This appendix describes the pinout and signal names for the DIO 24 50 pin I O connector of the AT MIO 16D EI 9 10 Figure C 1 AT MIO 16D DIO 24 I O Connector National Instruments Corporation 1 AT MIO 16D User Manual DIO 24 I O Connector Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 All even numbered pins Signal Name PC7 through PCO PB7 through PBO PA7 through PAO 5 DIGGND AT MIO 16D User Manual Reference DIGGND DIGGND DIGGND DIGGND C 2 Appendix C Description Bidirectional data lines for Port C PC7 is the MSB PCO the LSB Bidirectional data lines for Port B PB7 is the MSB PBO the LSB Bidirectional data lines for Port A PA7 is the MSB PAO the LSB This pin provides 5 VDC These signals are connected to the PC ground signal National Instruments Corporation Appendix D AT MIO 16D I O Connector This appendix describes the pinout and signal names for the AT MIO 16D 100 pin I O connector AI GND AI GND ACHO ACH8 1 ACH9 ACH2 ACH10 ACH3 11 ACH4 ACH12 ACHS ACH13 ACH6 A
112. CH14 ACH7 ACHIS AI SENSE DACO OUT DACI OUT EXTREF AO GND DIG GND ADIOO BDIOO ADIOI BDIOI ADIO2 BDIO2 ADIO3 BDIO3 DIG GND 5 5 EXTSTROBE START TRIG STOP TRIG EXTCONV SOURCEI GATEI OUTI SOURCE2 GATE2 OUT2 46 96 SOURCES GATES 48 98 OUTS 49 99 FOUT ZzUWZWUWZzWUWZzUWzWzoazazazazazazaza gd ug gtgugepg gegtgpijo tu meg teg oral gt Pep AVATATAVAVAVATVAVAVAVATATAVAVATATATAQTATATATATATYA ee et eee eee eee es lt Q Z J Figure D 1 AT MIO 16D I O Connector Detailed signal specifications are included in Chapter 2 Configuration and Installation National Instruments Corporation D 1 AT MIO 16D User Manual Appendix E AMD Am9513A Data Sheet This appendix contains the manufacturer data sheet for the Am9513A System Controller integrated circuit Advanced Micro Devices Inc This device is used on the AT MIO 16D Copyright Advanced Micro Devices Inc 1989 Reprinted with permission of copyright owner All rights reserved Advanced Micro Devices Inc 1990 Data Book Personal Computer Products Processors Coprocessors Video and Mass Storage National Instruments Corporation 1 AT MIO 16D User Manual AMD Am9513A Data Sheet Appendix E Am9513A System Timing Controller DISTINCTIVE CHARACTERISTICS Five independent 16 bit counters High speed counting rates Up down and binary BCD counting internal
113. CIreullty hese testa date atcha ate a ees 3 6 Analog Input 1 A antacid 3 6 Analog Input Mode Selection oe iter tet arte 3 6 The Instrumentation Amplifier 3 6 Channel Selection o ott utes dot ise pda edv da ues 3 6 3 7 ADC FIFO Buffet E c cT 3 7 Data Acquisition Timing Circuitry eese eeeeee eene enne entente nne 3 7 single CONVERSIONS 3 8 sample Interval TIMEN 3 8 sample Counter ously Geass 3 8 Single Channel Data Acquisition 3 0 Multiple Channel Scanned Data 1 0 3 0 Data Acquisition Bates 3 9 Analog Output CIECUIEY dace ede do aed anu le ever eis Pees 3 10 Palos 3 11 Analog Output Data Codtnp a cedi bald Seen oases 3 11 MIO 16 reor seed fend ecol eee 3 11 Timne aloe ED Lm 3 13 RISI Bus Interface Ot CUT Iani esc tu p 3 15 DIO 74 Functional OVeEVIe W aaa es bat 3 17 DIO 24 Interrupt Control CICUIUY
114. Corporation Chapter 4 Programming 1 Set up the analog channel and gain selection sequence During a scanning data acquisition operation a selected number of locations in the mux gain memory are clocked through A new mux gain memory location is selected after each A D conversion The first conversion is performed on the first channel and gain setting in the memory The second conversion is performed on the second channel and gain setting and so on The last entry written to the mux gain memory must have the LASTONE bit set This bit marks the end of the scan sequence After the last conversion is performed the scan sequence starts over If there are X entries in the mux gain memory every Xth conversion in the data collected is performed on the same channel and gain setting Multiple conversions can be performed on each entry in the mux gain memory before incrementing to the next entry in the scan sequence If the SCANDIV bit in Command Register 1 is set the mux gain memory increments to the next entry when an active low pulse is detected the Am9513A Counter Timer OUT signal If the SCANDIV bit is cleared the mux gain memory is incremented to the next entry after every conversion The mux gain memory must be loaded with the desired scan sequence before data acquisition begins To load the mux gain memory perform the following write operations where X is the number of entries in the scan sequence For i 0 to X 1 do the following
115. Cycie Rate Generator with Level Gating 1 cuna 3 Cm12 cum cma cme Luv p x p x x cus Gwe cus ow 996 Lo E Ex Ex DIT Mode shown in Figure 15k is identical to Mode J except that source edges are oniy counted when the Gate is active The counter must be armed for counting to occur Once armed the counter will count source edges which occur while Gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off As with Mode J the reload source used will aiternate on each TC starting with the Hold register on the first TC after any ARM command When the TC Toggled output is used this mode allows the Gate to modulate the duty of the output waveform It can affect both the HIGH and LOW portions of the output waveform Am9513A Appendix E National Instruments Corporation Appendix E AMD Am9513A Data Sheet PPPS PDP SPSS NINI N COUNT 2 CC Cais NIE Figure 15 Mode J Waveforms DUE NINI NININI NINI NINI NINININI Y em Wwy Ww No wo Tar CD CD EOE Figure 15k Mode K Waveforms MODE L Hardware Triggered Delayed Puise One Shot cuss cara 3 12 1 cto cmo LEE x x xe x x een ep Mode L shown in Figure
116. D User Manual 3 5 National Instruments Corporation Theory of Operation Chapter 3 Analog Input Circuitry The analog input circuitry consists of an input multiplexer multiplexer mode selection jumpers a software programmable gain instrumentation amplifier a sample and hold amplifier a 12 bit analog to digital converter ADC and a 12 bit FIFO with a 16 bit sign extension option Analog Input Multiplexers The input multiplexer consists of two CMOS analog input multiplexers and has 16 analog input channels Multiplexer MUXO is connected to analog input channels 0 through 7 Multiplexer MUX I is connected to analog input channels 8 through 15 The input multiplexers provide input overvoltage protection of 35 V powered on and 20 V powered off Analog Input Mode Selection The multiplexer mode selection jumpers configure the analog input channels as 16 single ended inputs or 8 differential inputs When single ended mode is selected the outputs of the two multiplexers are tied together and routed to the positive input of the instrumentation amplifier The negative input of the instrumentation amplifier is tied to the AT MIO 16D ground for RSE input or to the analog return of the input signals via the AI SENSE input on the I O connector for NRSE input When DIFF mode is selected the output of MUXO is routed to the positive input of the instrumentation amplifier and the output of MUX1 is routed to the negative input of t
117. DIO 24 circuitry are disabled Figure 2 8 shows the possible jumper settings for W14 The board is shipped with this jumper set to PC4 therefore interrupt requests from the board are enabled and controlled by PC4 W14 KT eee ope be N C DIO INT DIO INT DIO INT Default Factory Setting Figure 2 8 Jumper Settings PC6 PC4 PC2 N C Analog I O Jumper Settings The AT MIO 16D is shipped from the factory with the following configuration e Differential analog input eight channels e Bipolar analog input e 10 V input range AT MIO 16D User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation e 10 output range with internal reference selected e Two s complement digital to analog converter DAC input modes e AT MIO 16D clock signal set to 10 MHz Table 2 5 lists all the available analog I O jumper configurations for the AT MIO 16D with the factory settings noted Table 2 5 Analog I O Jumper Settings Configuration Jumper Settings ADC Input Range ADC Input Mode Am9513A amp RTSI Bus Clock Select DACO Reference DACI Reference DACO Output Polarity Digital Format DACI1I Output Polarity Digital Format National Instruments Corporation 2 9 Unipolar 0 V to 10 V Bipolar 5 V Bipolar 10 V factory setting Differential DIFF factory setting Nonreferenced single ended NRSE Referenced single e
118. E 15 to E 26 ordering information E 3 to E 5 output control E 26 to E 28 output control logic E 27 pin description E 6 prefetch circuit E 10 programming 4 73 register access E 9 National Instruments Corporation Index 3 AT MIO 16D User Manual Index scaler ratios E 13 specifications E 33 to E 38 status register E 10 to E 11 switching test circuit E 37 switching waveforms E 38 TC terminal count E 28 TEHWH TGVWH timing diagram E 40 Time of Day E 12 timing I O circuitry 3 13 to 3 15 troubleshooting E 39 analog data acquisition rates multiple channel rates A 3 single channel rates A 3 analog input calibration 5 3 to 5 6 bipolar input calibration procedure 5 4 to 5 5 board configuration 5 4 unipolar input calibration procedure 5 5 to 5 6 analog input channel and gain programming analog input circuitry 4 43 multiple A D conversions continuous channel scanning round robin 4 58 controlling with EXTCONV signal 4 56 interval channel scanning pseudo simultaneous 4 63 pretriggering with STOP TRIG signal 4 51 on single channel 4 47 analog input circuitry A D converter 3 7 A D FIFO buffer 3 7 block diagram 3 5 input multiplexers 3 6 instrumentation amplifier 3 6 mux gain memory 3 6 programming 4 43 to 4 46 A D FIFO output binary formats 4 44 to 4 45 clearing analog input circuitry 4 45 to 4 46 initiating A D conversions 4 43 reading A D conversion results 4 44 selecting analog input
119. E VALUE 1 Output H Voltage vs Output Current gt gt 5 gt gt 3 3 0 2 3 4 5 Output current mA 2 Output L Voltage VoL vs Output Current 101 Output L voltage Voi V Output current loi mA Note The diraction of flowing into the device is taken as positive for the output current 335 AT MIO 16D User Manual F 8 National Instruments Corporation Appendix F Oki 82 55 Data Sheet 1 O MSM82C55A 2RS GS VJS_ FUNCTIONAL DESCRIPTION OF PIN rome eevee Bidirectional Input and These are three state 8 bit bidirectional buses used to write and data bus output read data upon recaipt of the WR and RD signals from CPUand aiso used when contro words and bit set reset data trans ferred from CPU to 5 82 55 Reset input This signal is used to reset the control register and ali internal registers when it is in high level At this time ports are all made into the input mode high impedance status all port latches are cleared to O and ali ports groups are set to mode O When the CS is in low level data transmission is enabled with CPU When it is in high isvel the data bus is made into the high impedance status where no write nor read operation is performed Internal registers hold their previous status however Read input When
120. EA Element Pointer 00 Mode Register 01 Load Register Element Cycie increment 10 Hold Register 11 Hold Register Hold Cycie increment 00 Alasm Register 1 101 Counter Group 5 01 Alarm Register 2 Control increment 110 egal 10 Master Mode Reg 111 Control Group 11 Status Register No Increment 0 001890 Figure 7 Data Pointer Register Am9513A 2 123 National Instruments Corporation E 9 AT MIO 16D User Manual AMD Am9513A Data Sheet Sas Register Register Register Register Counter 1 9 Counter 2 2 Counter 3 FFOB Counter 4 FFO4 5 FFOD Master Mode Register FF17 Alarm 1 Register FF07 Alarm 2 Register FFOF Status Register FFIF Figure 8 Load Data Pointer Commands Sequencing is enabied by clearing Master Mode bit 14 MM14 to zero As shown in Figure 9 several types of sequencing are available depending on the data bus width being used and the initial Data Pointer value entered by command When E1 0 E2 0 and G4 G2 G1 points to a Counter Group the Data Pointer will proceed through the Element Cycle The Element field will automatically sequence through the three values 00 01 and 10 starting with the value entered When the transition from 10 to 00 occurs the Group fieid will also be incremented by one Note that the Element field in this case does not sequence to a value of
121. FO overflow condition occurs if more than 512 conversions are initiated and stored in the A D FIFO before the A D FIFO Register is read If this condition occurs the OVERFLOW bit is set in the Status Register to alert you that one or more A D conversion results have been lost because of FIFO overflow Writing to the A D Clear Register clears this error flag and empties the A D FIFO A D FIFO Output Binary Formats The A D conversion result can be returned from the A D FIFO as a two s complement or straight binary value by setting or clearing the 25CADC bit in Command Register 1 If the analog input circuitry is configured for the input range 0 to 10 V straight binary format is recommended set the 28CADC bit Straight binary format returns numbers between 0 and 4 095 decimal when the A D FIFO Register is read If the analog input circuitry is configured for the input ranges 5 to 5 V or 10 to 10 V two s complement format is recommended clear the 28 CADC bit Two s complement format returns numbers between 2 048 and 42 047 decimal when the A D FIFO Register is read The factory default setting is the input range 10 to 10 V Table 4 2 shows input voltage versus A D conversion value for straight binary format and 0 to 10 V input range Table 4 3 shows input voltage versus A D conversion value for two s complement format for both 5 to 5 V and 10 to 10 V input ranges AT MIO 16D User Manual 4 44 National Instruments Corporation
122. FP44 P 910 VIK CIRCUIT CONFIGURATION i 329 AT MIO 16D User Manual F 2 National Instruments Corporation Appendix F Oki 82 55 Data Sheet 1 0 MSM82C55A 2RS GS VJS_ PIN CONFIGURATION MSMB2C55A 2RS Top View 40 pin Plastic DIP 5 82 55 265 44 pin Plastic Quad Flat Package MSM82C55A 2VJS Top View 44 pin Plastic Leaded Chip Carrier 330 National Instruments Corporation F 3 AT MIO 16D User Manual Oki 5 82 55 Data Sheet Appendix F 1 0 MSM82C55A 2RS GS VJS ABSOLUTE MAXIMUM RATINGS Limits Parameter Symbol Conditions Ssupply Voltage Voltage vcc Ta 25 05t47 5to 7 h input Voltage EE 0 5 to Veg 0 5 EN Output Voltage Vout to GND 0 5 to Veg 0 5 Storage Temperature Tag 85 1 150 OPERATING RANGE oem Sopp Vora we EEECTE TY RECOMMENDED OPERATING RANGE reme v Sem vae Umevawe ww 95 TW inet Vora Ww ve Y DC CHARACTERISTICS EE fos input Leak Current i Leak Current 0 lt Lr VIN Vcc Output Leak Current o lt Supply Current gt Vee 502 Vin 2 02V standby purs S 02V Average mn d Current mn d
123. IL This bit reflects the state of the A D FIFO If CONVAVAIL is set one or more A D conversion results are available to be read from the A D FIFO If conversion interrupts are enabled CONVINTEN is set and CONVAVAIL is set the current interrupt indicates that A D conversion data is available in the A D FIFO If CONVAVAIL is cleared the A D FIFO is empty and no conversion interrupt request is asserted 12 OUT2INT This bit reflects the status of the OUT2INT interrupt OUT2INT is cleared by writing to the INT2CLR Register OUT2INT is set whenever a rising edge on OUT2 is detected this condition generates an interrupt request only if the INT2EN bit in Command Register 2 1s set AT MIO 16D User Manual 4 6 National Instruments Corporation Chapter 4 Bit 11 10 7 6 Name DAQPROG DMATCINT OVERFLOW OVERRUN GAIN 1 0 DMACH MUXIEN Programming Description continued This bit indicates whether a data acquisition operation is in progress If DAQPROG is set a data acquisition operation is in progress If DAQPROG is cleared a data acquisition operation is not in progress This bit reflects the status of the DMA terminal count interrupt If DMATCINT is set and if TCINTEN is set in Command Register l then the current interrupt is due to the detection of a DMA terminal count pulse DMATCINT is cleared by writing to the DMA TC Clear Register This bit indicates whether the A D FIFO has overflowed during a
124. IO 16D User Manual Programming Chapter 4 Table 4 7 RTSI Switch Signal Connections RTSI Switch Pin Signal Name Signal Direction EXTCONV FOUT OUT2 GATEI SOURCES OUTS STOP TRIG OUTI START TRIG TRIGGERO TRIGGERI TRIGGER2 TRIGGER3 TRIGGER4 TRIGGERS TRIGGER6 Bidirectional Output Output Input Bidirectional Output Input Output Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Figure 3 8 in Chapter 3 Theory of Operation diagrams the AT MIO 16D RTSI switch connections AT MIO 16D RTSI Signal Connection Considerations The AT MIO 16D board has a total of nine signals connected to the seven A side pins of the RTSI switch These same signals also appear at the AT MIO 16D I O connector As shown in Table 4 8 two AT MIO 16D signals are connected to pin A2 and two signals are connected to pin A4 The routing of these signals is further controlled by the bits A4DRV A4RCV A2DRV and A2RCV in Command Register 2 e To drive the RTSI switch pin A2 with the signal OUT2 set the A2DRV bit in Command Register 2 Otherwise clear the A2DRV bit e To drive the signal GATEI from pin A2 of the RTSI switch set the A2RCV bit in Command Register 2 Otherwise clear the A2RCV bit Note If both the A2DRV and 2 bits are set the GATE signal is driven by the signal OUT2 This arrangement is probably not desirable e To drive the RTSI switch pin
125. IO 16D User Manual dts ends did dabo CR AMD Am9513A Data Sheet Appendix PIN DESCRIPTION Crystal X1 and X2 are the connections for an extemal crystal used to determine the frequency of the intemal oscillator The crystal shouid be a parailel resonant fundamental mode type RC or LC or other reactive network may be used instead of a crystal For driving from an external frequency source X1 should be left open and X2 should be connected to a TTL source and a pull up resistor Frequency Out The FOUT output is derived from a 4 bit counter that may be programmed to divide its input by any integer value from 1 through 16 inclusive The input to the counter is selected from any of 15 sources including the internal scated oscillator FOUT may be gated and off under software control and when off will exhibit a low impedance to ground Control over the various FOUT options resides in the Master Mode register After power up FOUT TNS a frequency that is 1 16 that of the oscillator The input source on power up is F1 GATE1 GATES Gate The Gate inputs may be used to contro the operations of individual counters by determining when counting may proceed sama Gate Input may coniol up t0 three counters Gate pins may also be selected as count sources for any of the counters and for the FOUT divider The active polarity tor a selected Gate input is programmed at each counter Gating function op
126. IO 16D board configured for DIFF input Configuration instructions are included under the Analog Input Configuration section earlier in this chapter Ground Referenced Signal Instrumentation Source Amplifier V Measured Voltage Common Mode Noise Ground Potential Etc 15 Input Multiplexers AI SENSE 1 2 MIO 16 I O Connector AT MIO 16D Board in DIFF Configuration Figure 2 27 Differential Input Connections for Grounded Signal Sources AT MIO 16D User Manual 2 28 National Instruments Corporation Chapter 2 Configuration and Installation With this type of connection the instrumentation amplifier rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT MIO 16D ground shown as V in Figure 2 27 Differential Connections for Floating Signal Sources Figure 2 28 shows how to connect a floating signal source to an AT MIO 16D board configured for DIFF input Configuration instructions are included under the Analog Input Configuration section earlier in this chapter Floating Signal Source Instrumentation Amplifier Measured m Voltage Connector AT MIO 16 Board in DIFF Configuration Figure 2 28 Differential Input Connections for Floating Sources The 100 kQ resistors shown in Figure 2 28 create a return path to ground for the bias currents of the instrumentation amplifier If a return path is not provided the ins
127. IP PD 040 D 40 Pin Ceramic DIP 040 J 44 Pin Plastic Loaded Chip PL 044 b SPEED OPTION Not Applicable amp DEVICE NUMBER DESCRIPTION Am9513A System Timing Controller Valid Combinations Vals Xu G bu io Valid Combinations yota Inis devico conau the local AMD sales ofica t0 confirm availability of specific valid combinations to check on AMES ISA PC DC 08 Jc newly released combinations and to obtain additional data on This device is also available in Military temperature AMD s standard military grade range Am9513A 2 117 National Instruments Corporation E 3 AT MIO 16D User Manual AMD Am9513A Data Sheet Appendix E ORDERING INFORMATION continued Standard Military Drawing SMD DESC Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges Standard Military Drawing SMD DESC products are fully compliant with MIL STD 883C requirements The order number Valid Combination for SMD DESC products is formed by a combination of a Military Drawing Part Number b Device Type Case Outiine d Lead Finish 5262 85523 a x p LEAD FINISH X Any Lead Finish Acceptable CASE OUTLINE 40 Pin Ceramic DIP CD 040 X 44 Pin Ceramic LCC CL 044 b MILITARY DEVICE 0197 MHz 9513A Valid Combinations Valid Combinations list configurations planned to be c supported
128. Low indicates that the CPU has written data out to Port B 0 INTRB Interrupt request status for Port B When INTEB is high and OBFB is high this bit is high indicating that a DIO interrupt request is asserted National Instruments Corporation 4 85 AT MIO 16D User Manual Programming Chapter 4 At the digital I O connector Port C has the following pin assignments when in Mode output Notice that the status of ACKA and ACKB is not included when Port C is read Mode 1 Output Programming Example Main define BASE ADDRESS 0x210 Board located at address 210 define PORTAoffset 0x00 Offset for Port A fdefine PORTBoffset 0x01 Offset for Port B define PORTCoffset 0x02 Offset for Port C define CNFGoffset 0x03 Offset for CNFG register unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE ADDRESS PORTAoffset portb BASE ADDRESS PORTBoffset portc BASE ADDRESS PORTCoffset cnfg BASE ADDRESS CNFGoffset EXAMPLE 1 Port A output outp cnfg 0xAO0 Port A is an output in Mode 1 while inp portc amp 0x80 Wait until OBFA is set indicating that the data last written to Port A has been read outp porta 0x12 Write data to Port A EXAMPLE 2 Port B output outp cnfg 0x84 Port B i
129. MIO 16D User Manual Programming Chapter 4 Mode 1 Input Programming Example Main define BASE ADDRESS 0x210 define PORTAoffset 0x00 define PORTBoffset 0x01 define PORTCoffset 0x02 define CNFGoffset 0x03 register unsigned int porta char valread Calculate register addresses porta BASE_ADDRESS PORTAoffset portb BASE_ADDRESS PORTBoffset portc BASE_ADDRESS PORTCoffset cnfg BASE ADDRESS CNFGoffset EXAMPLE 1 Port A input outp cnfg 0xBO while inp portc amp 0x20 valread inp porta EXAMPLE 2 Port B input outp cnfg 0x86 while inp portc amp 0x02 valread inp portb Mode 1 Strobed Output portb portc Wait data Read Port Wait data Board located at address 210 Offset Offset Offset Offset cnfg Variable to store port for for for for x Port A Port B Port C CNFG data read from a in Mode 1 Port A is an input until IBFA is set has been loaded in Port A the data from Port A B is an input indicating that Xu uri in Mode 1 until IBFB is set has been loaded in Port B indicating that The control word written to the DIO 24 Register to configure Port A for output in Mode 1 is shown as follows Bits PC4 and PC5 of Port C can be used as extra input or
130. ND Appendix B Description Analog Input Ground These pins are the reference point for single ended measurements and the bias current return point for differential measurements Analog Input Channels 0 through 15 In differential mode the input is configured for up to eight channels In single ended mode the input is configured for up to 16 channels Analog Input Sense This pin serves as the reference node when the board is in NRSE configuration If desired this signal can be programmed to be driven by the board analog input ground Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 Analog Channel 1 Output This pin supplies the voltage output of analog output channel 1 External Reference This is the external reference input for the analog output circuitry Analog Output Ground The analog output voltages are referenced to this node Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply Digital I O port A signals Digital I O port B signals 5 VDC Source This pin is fused for up to 1 A of 5 V supply Scan Clock This pin pulses once for each A D conversion in the scanning modes The low to high edge indicates when the input signal can be removed from the input or switched to another signal External Strobe Writing to the EXTSTROBE Register results in a minimum 200
131. SS 8 2 9 Ts Cl o Count Source High to Out Valid Note 7 immediate or Delayed Toggle 300 ms ee eee i eee E brc n _ Tavev Gato Vaid to Gate Vaid Gate Notes 810 Gate Vaid to wie High Notes 3 1 2 UUO Read High to C D _TRHEH Read High to Count Source High Notes 4 7 Read High to Data Ow did 0 Read High to Data Out at High Impedance TRHOZ Gina GO dame Tene 5 TRHAL Read High to Head Low Head Reeve Time Read High to CS High Noe i Read High to Wite Low Read Recovery TRLOV Read Low to Data Out Valid dL TRLOX Read Low to Data Bus Driven Data Bus Drive Time 20 RLRH Read Low to Read High Read Noe 1j 389 CS Low to Read Low Note 12 19 C Low to Write High Note 12 TWHAX We High to C DomtCae TWHOK Write High is Data TWHEH Write High to Count Source High Notes 5 7 14 15 50 TWHGV High to Gate Vaid Notes 10 19 OO 55 TWHRL Write High to Read Low Wrte Recovery Time Note ij 1899 We High to Noe 1 211 11 Write H
132. VO Jumper Seung oe ei etie duce dte 2 8 Analog Input Configurations aden ee 2 10 dede ad ioc e P ides 2 10 DIFF Analog Input Eight Channels Factory Setting 2 10 RSE Analog Input 16 5 22222412 1 2 11 NRSE Analog Input 16 Channels eene 2 12 Analog Input Polarity and Range det dere eed gern ae 2 12 Considerations for Selecting Analog Input 2 14 Analog Output Configuration 2 15 Analog Output Reference 1 ashes ee 2 15 External Reference Selectlon cedo Bea ee BAe ade 2 15 Internal Reference Selection Factory 2 15 Analog Output Polarity Selection 2 16 Bipolar Output Selection Factory Setting esses 2 16 Straight Binary Mode acido ett dete ones 2 17 Two s Complement Mode Factory Setting 2 17 Unipolar Output Selection ect tete 2 18 RUST Bus Clock Selection ze caeco dit aiat eaae eee olden ee 2 18 Hardware Installations Bees 2 20 SIGBIALCODBHCOHODS oa ta Caccia Rcs 2 20 AT MIO
133. Write i to the Mux Counter Register to select the mux gain memory location b Write the desired analog channel selection and gain setting to the Mux Gain Register to load the mux gain memory at location i c If i X 1 also set the LASTONE bit when writing to the Mux Gain Register 2 Program the sample interval counter Use Counter 3 of the Am9513A Counter Timer as the sample interval counter You can program Counter 3 to generate a pulse once every N counts N is referred to as the sample interval that is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the sample interval counter use the following programming sequence writes are 16 bit operations values given are hexadecimal a Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register b Write the mode value to the Am9513A Data Register to store the Counter 3 mode value Use one of the following mode values 8B25 Selects 1 MHz clock 8C25 Selects 100 kHz clock 8025 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of
134. X 1 also set the LASTONE bit when writing to the Mux Gain Register 2 Program the sample interval counter Use Counter 3 of Am9513A Counter Timer as the sample interval counter Counter 3 can be programmed to generate a pulse once every N counts N is referred to as the sample interval that Is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the sample interval counter use the following programming sequence writes are 16 bit operations values given are hexadecimal a Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register b Write the mode value to the Am9513A Data Register to store the Counter 3 mode value Use one of the following mode values 8B25 Selects 1 MHz clock 8 25 Selects 100 kHz clock 8025 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum AT MIO 16D User Manual 4 56 National Instruments Corporation Chapter 4 Programming c Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register d Wr
135. _ _ TCHCH X2 High to X2 High 02 Period Noe 13 77 _ gt 345 X2 High to X2 Low X2 High Pulse Note ia O OOOO 1 2 TCLCH 2 Low to X2 High X2 Low Pulse Width Note 13 22 79 Dam m Vaid to Wie High 2 TEHEH Count Source High to Count Source High Source Cycle Time Note 7 22 14 WE cess oreo Cd me pT _TEHFV Count Source High to FOUT Vaid TEHGV Count Source High to Gate Valid Level Gating Hold Time Notes 7 9 10 22 10 Count Source High to Read Low Set up Time Notes 2 7 21 199 TEHWH Count Source High to Write High Set up Time Notes 2 7 121 49 conse are vn EE TEHYV Count Source High to Out Valid Note 7 Immediate or Delayed Toggle Output 22 300 Comparator Output 22 350 TEN FN High to FN Vaid Note 1 TGVEH Gate Valid to Count Source High Level Gating Setup Time Notes 7 910 22 100 TGVGV Gate Vaid to Gate Valid Gate Duration Notes 8 1 O 45 TGVWH Gate Valid to Wate High Notes 3 1 zi _TRHAX Read High to C D Care O _TRHEH Read High to Count Source High Notes 4 D CT et 9 TRHQX Read High to Data Out valid 91 TRHGZ Read High to Data Out at High impedance Data Bus Release Time 85
136. ad the Status Register 16 bit read b Ifthe CONVAVAIL bit is set bit 13 read the A D FIFO Register to obtain the result Interrupts or DMA can also be used to service the data acquisition operation These topics are discussed later in this chapter Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the CONVAVAIL bit If either of these error conditions occurs the data acquisition operation stops An overflow condition occurs if more than 512 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if an A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is set The maximum recommended single channel data acquisition
137. ag Be sure to set to 0 for bit sst reset When set to 1 it becomes the control word to define a mode and input output Interrupt Control Function When the 5 82 55 is used in mode 1 mode 2 the interrupt signa for the CPU is provided The interrupt request signal is output from port C When the internal flip flop INTE is set beforehand at this time the desired interrupt request signal is output When it is reset beforehand however the interrupt request sig nat is not output The set reset of the internal flip flop is made by the bit set reset operation for port C virtually Bit set gt INTE is set gt Interrupt allowed Be reset gt INTE is reset gt Interrupt inhibited CommiWed gt Word Note When used in mode 0 for both groups A and B 338 O National Instruments Corporation 11 Oki MSM82C55A Data Sheet Definition of set reset 0 Reset for a desired bit 1 Operational Description by Mode 1 Mode 0 Basic input output operation Mode makes the MSMB2C55A operate as a bas ic input port or output port No control signals such as interrupt request etc are required in this mode All 24 bits can be used as two 8 bit ports and two 4 bit ports Sixteen combinations are then possible for inputs outputs The inputs are not latched but the outputs are Group a Pare par rtc AT MIO 16D User Manual Oki MSM82C55A Data Sheet Appendix F
138. al A D conversions can be externally triggered with the EXTCONV pin Applying an active low pulse to the EXTCONV signal initiates an A D conversion The A D conversion is initiated by the low to high edge of the applied pulse Figure 2 34 shows the timing requirements for the EXTCONV signal tw 50 nsec minimum A D conversion starts within 250 nsec from this point Figure 2 34 EXTCONV Signal Timing The minimum allowed pulse width is 50 nsec An A D conversion starts within 250 nsec of the low to high edge There is no maximum pulse width limitation EXTCONV should be high for at least 50 nsec before going low The EXTCONV signal is one LS TTL load and is pulled up to 5 V through a 4 7 kQ resistor Note EXTCONV is also driven by the output of Counter 3 of Am9513A Counter Timer This counter is also referred to as the sample interval counter The output of Counter 3 must be disabled to a high impedance state if A D conversions are to be controlled by pulses applied to the EXTCONV pin If Counter 3 is used to control A D conversions its output signal can be monitored at the EXTCONV pin You can initiate any data acquisition sequence controlled by the onboard sample interval and sample counters by an external trigger applied to the START TRIG pin If conversions are generated by the EXTCONV signal START TRIG does not affect the acquisition timing Once the two counters are initialized and armed applying a falling edge to
139. al applied to the counter GATE input is of some known duration In this case program the counter to count either rising or falling edges at the SOURCE input while the gate is applied The frequency of the input signal is then the count value divided by the known gate period Figure 2 38 shows the connections for a frequency measurement application You could use a second counter to generate the gate signal in this application 33 DIG GND MIO 16 I O Connector AT MIO 16D Boar Figure 2 38 Frequency Measurement Application Two or more counters can be concatenated by tying the OUT signal from one counter to the SOURCE signal of another counter You can then treat the counters as one 32 bit or 48 bit counter for most counting applications The GATE SOURCE and OUT signals for Counters 1 2 and 5 and the FOUT output signal are tied directly from the Am9513A input and output pins to the I O connector In addition the GATE SOURCE and OUTI pins are pulled up to 5 V through a 4 7 kQ resistor The input and output ratings and timing specifications for the Am9513A signals are given below AT MIO 16D User Manual 2 40 National Instruments Corporation Chapter 2 Configuration and Installation The following specifications and ratings apply to the Am9513A I O signals Absolute maximum voltage input rating 0 5 V to 7 0 V with respect to DIG GND Am9513A digital input specifications referenced to DIG GND input logic high voltage 2
140. alue will not correspond to the new value saved in the Hold Register To avoid reading an incorrect value a new Load Data Pointer command should be issued before attempting to read the saved data A Data port write to another register will also initiate a prefetch subsequent reads will access the recently saved Hold register data Many systems will use the saving gate edge to interrupt the host CPU In systems such as this the interrupt service routine should issue a Load Data Pointer command prior to reading the saved data Status Register The 8 bit read only Status register indicates the state of the Byte Pointer bit in the Data Pointer register and the state of the Appendix E 2 124 Am9513A AT MIO 16D User Manual National Instruments Corporation Appendix E OUT signal for each of the genera counters See Figures 10 and 17 The OUT signals reported are those internal to the chip after the polarity select logic and just before the three state interface buffer circuitry Bits 6 and SR7 may be 0 or 1 The Status register OUT bit reflects an active high or active low TC output or a TC Toggled output as programmed in the Output Control Field of the Counter Mode register That is it feflects the exact state of the OUT pin When the low impedance to Ground Output option CM2 CMO 000 is selected the Status register will reflect an active high TC Output When a high impedance Output option CM2
141. am DIO 24 Interrupt Control Circuitry The interrupt level used by the DIO 24 circuitry of the AT MIO 16D is selected by the onboard jumper W13 Another onboard jumper W14 is used to enable interrupts from the DIO 24 circuitry The setting for W14 selects PC2 PC4 or PC6 as the active low interrupt enable signal Selecting N C for W14 disables interrupts from the DIO 24 circuitry When the onboard jumpers are set to enable interrupts the 82C55A can be programmed to generate an interrupt request by setting INTRA for Group A or INTRB for Group B When interrupts are enabled for Group A an active high signal on the PC3 line generates an interrupt request When interrupts are enabled for Group B an active high signal on the PCO line generates an interrupt request National Instruments Corporation 3 17 AT MIO 16D User Manual Theory of Operation Chapter 3 DIO 24 Circuitry I O Connector All digital I O is transmitted through a 100 pin male connector This 100 pin connector is physically divided into two standard 50 pin female connectors using a cable assembly The pin assignments for the 50 pin DIO 24 I O connector are compatible with standard 24 channel digital I O applications All even pins on the 50 pin DIO 24 connector are attached to logic ground and pin 49 is connected to 5 V through a protection fuse F4 which is often required to operate I O module mounting racks See Chapter 2 Configuration and Installation for additional informa
142. and or execution of a STEP command In modes which alternate reload sources Modes G L the ARMing operation is used as a reset for the logic which counter initialization prior to active hardware gating a LOAD or LOAD AND ARM command is executed during the cycle preceding TC the counter will go immediately to TC This occurs because the LOAD operation is performed by generating pseudo count pulse intemal to the Am9513A and the Am9513A is expecting to go into TC on the next count pulse The reload source used to reload the counter will be the same as that which would have been used if the TC were generated by a source edge rather than by the LOAD operation Execution of a LOAD or LOAD AND ARM command while the counter is in TC will cause the TC to end For Armed counters in all modes except S or V the LOAD source used will be that to be used for the upcoming TC The LOADing operation will not alter the selection of reload source for the upcoming TC For Disarmed counters in modes except S or V the reload Sources used will be the LOAD register For modes S or V the reload source will be selected by the GATE input regardless of whether the counter is Armed or Disarmed 2 144 Am9513A AT MIO I6D User Manual E 30 National Instruments Corporation Appendix E Special considerations apply when modes with alternating reload sources are used Modes L if a LOAD command drives the counter to TC i
143. and Register to select the Counter 4 Mode Register b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the least significant 16 bits of the sample count value minus 1 to the Am9513A Data Register to store the Counter 4 load value e If the 16 LSBs are all write FFFF e Write FF48 to the Am9513A Command Register to load Counter 4 f Write 0 to the Am9513A Data Register to store 0 into the Load Register for Counter 4 reloading Write FF28 to the Am9513A Command Register to arm Counter 4 h Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register k Take the most significant 16 bits of the sample count and do the following e Ifthe least significant 16 bits of the sample count are all 0 or all 0 except for a 1 in the least significant bit write the most significant 16 bits to the Am9513A Data Register to store the Counter 5 load value e Otherwise add 1 to the most significant 16 bits of the sample count and write that value to the Am95134A Data Register to store the Counter 5 load value l Write FF70 to the Am9513A Command Register to load and arm Counter 5 m Setthe 16 32 CNT bit in Command Register 1 to notify the hardware th
144. annel Scanning section later in this chapter The following programming sequences for sample counts less than 65 537 allow the data acquisition circuitry to be retriggered The sample interval and sample counters are reloaded at the end of the data acquisition to prepare for another data acquisition operation The counters do not need reprogramming and the next data acquisition operation starts when a trigger is received Programming multiple A D conversions on a single channel requires the following programming steps 1 Select analog input channel and gain 2 Program the sample interval counter 3 Program the sample counter AT MIO 16D User Manual 4 46 National Instruments Corporation Chapter 4 Programming 4 Clear the A D circuitry 5 Enable the data acquisition operation 6 Apply a trigger Service the data acquisition operation Each of these programming steps is explained below 1 Select analog input channel and gain The analog input channel and gain are selected by writing to the Mux Gain Register Bits 7 and 6 control the gain and bits 3 through 0 select the analog input channel See the Mux Gain Register bit description earlier in this chapter for gain and analog input channel bit patterns Set up the bits as given in the Mux Gain Register bit description and write to the Mux Gain Register The Mux Gain Register needs to be written to only when you need to change the analog input channel or gain setting
145. ansi tions in the F signals F1 X2 12 This timing specification assumes that CS is active when ever RD or WA are active TS may be held active indefinitely 13 This parameter assumes X2 is driven from an external gate with a square wave 14 This parameter assumes that the write operation is to the command register 15 This timing specification applies to single action com mands e g LOAD ARM SAVE etc For double action commands such as LOAD AND ARM and DISARM AND SAVE TWHEH minimum 700 ns 16 1 short data write mode TWHRL and TWHWL mini mum 1000 ns 17 This parameter applies to the hardware retrigger save modes N R and X CM7 1 and CM15 CM13 lt gt 000 This parameter ensures that the gating pulse initiates a hardware retrigger save operation 18 This parameter applies to hardware load source select modes 5 and V CM7 1 and CM15 CM13 000 This parameter represents the minimum hold time to ensure that the GATE input selects the correct load source on the active source edge 2 148 9513 AT MIO 16D User Manual E 34 National Instruments Corporation iem ee Appendix E j Appendix E AMD Am9513A Data Sheet SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Note 1 Parameters Description Min Max TAVRL C D Vaid to Read Low C D Vaid to Witte High
146. anual E 40 National Instruments Corporation Appendix Oki MSM82C55A Data Sheet This appendix contains the manufacturer data sheet for the MSM82C55A CMOS Programmable Peripheral Interface Oki Semiconductor This device is used on the AT MIO 16D Copyright Oki Semiconductor 1990 Reprinted with permission of copyright owner All rights reserved Oki Semiconductor Microprocessor Data Book 1990 1991 National Instruments Corporation 1 AT MIO 16D User Manual Oki MSM82C55A Data Sheet Appendix F MSMB82CSSA 2RSIGSIVU S CMOS PROGRAMMABLE PERIPHERAL INTERFACE GENERAL DESCRIPTION The MSMB2CS55A is a programmable universal I O interface device which operates as high speed and on low power consumption due to 3 silicon gate CMOS technology It is the best fit as an I O port a system which employs the 8 bit parallel processing 5 CPU This device has 24 bit I O pins equivalent to three 8 bit ports and ail inputs outputs TTL interface compatible FEATURES High speed and low power consumption due to 3 Bit set reset function Port C silicon gate CMOS technology TTL compatible 3 V to6 V single power Compatible with 8255A 5 Fuil static operation 940 pin Plastic DIP DIP40 P 600 Programmable 24 bit 1 ports 644 pin PLCC QFJ44 P S650 Bidirectional bus operation Port A 944 pin V Plastic QFP 44 910 944 pin VI Plastic QFP Q
147. any location in the mux gain memory The SCAN CLK signal is generated from the sample interval counter This signal pulses once at the beginning of each A D conversion and is supplied at the I O connector During multiple channel scanning the multiplexer counter is incremented repeatedly thereby sequencing through the mux gain memory and automatically selecting new channel and gain settings during data acquisition The MUX CTR CLK signal is generated from the SCAN CLK and provides the pulses that increment the multiplexer counter MUX CTR CLK can be identical to SCAN CLK incrementing the multiplexer counter once after every A D conversion MUX CTR CLK can also be generated by dividing SCAN CLK by Counter 1 of the Am9513A Counter Timer With this method the multiplexer counter can be incremented once every N A D conversions such that N conversions can be performed on a single channel and gain selection before switching to the next channel and gain selection Data Acquisition Rates Data acquisition rates number of samples per second are determined by the conversion period of the ADC plus the sample and hold acquisition time During multiple channel scanning the data acquisition rates are further limited by the settling time of the input multiplexers and instrumentation amplifier After the input multiplexers are switched the instrumentation amplifier should be allowed to settle to the new input signal value before an A D conversion is performed o
148. ard located at address 210 define PORTAoffset 0x00 Offset for Port A fdefine PORTBoffset 0x01 Offset for Port B define PORTCoffset 0x02 Offset for Port C define CNFGoffset 0x03 Offset for CNFG register unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE ADDRESS PORTAoffset portb BASE ADDRESS PORTBoffset portc BASE ADDRESS PORTCoffset cnfg BASE ADDRESS CNFGoffset AT MIO 16D User Manual 4 86 National Instruments Corporation Chapter 4 Programming EXAMPLE 1 outp cnfg 0xC0 Port A is in Mode 2 while inp portc amp 0x80 Wait until OBFA is set indicating that the data last written to Port A has been read outp porta 0x67 Write the data to Port A while inp portc amp 0x20 Wait until IBFA is set indicating that data is available in Port A to be read valread inp porta Read data from Port A Single Bit Set Reset Feature You can set or reset any of the eight bits of Port C with one control word This feature generates status and control for Port A and Port when operating in Mode 1 or Mode 2 Interrupt Programming Examples The following examples show the process required to enable interrupts for several different operating modes The interrupt handling routines
149. at both Counters 4 and 5 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and Counter 5 decrements every time Counter 4 reaches zero The data acquisition operation is terminated when both Counters 4 and 5 reach Zero 4 Clear the A D circuitry Before you start the data acquisition operation you must empty the A D FIFO to clear out any old A D conversion results This emptying must be done after the counters are programmed in National Instruments Corporation 4 49 AT MIO 16D User Manual Programming Chapter 4 case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 5 Enable the data acquisition operation To enable the data acquisition operation such that A D conversions begin when a trigger is received set the DAQEN bit in Command Register 1 6 Apply a trigger Once set up by the preceding steps the data acquisition operation is initiated when a trigger is received A trigger can be provided in one of two ways through software or through hardware To initiate the data acquisition operation through software write 0 to the Start DAQ Register 16 bit write To initiate the data acquisition operation through hardware apply an active low pulse to the START TRIG pin on the AT MIO 16D I O connector See the Data Acquisition Timing Connections section i
150. ated by writing to the Start DAQ Register or by a pulse on the START TRIG input The sample count register does not begin counting samples until a rising edge is applied to STOP TRIG To perform this operation complete these steps 1 Select analog input channel and gain 2 Program the sample interval counter 3 Program the sample counter 4 Clear the A D circuitry 5 Apply a trigger 6 Service the data acquisition operation Select analog input channel and gain The analog input channel and gain are selected by writing to the Mux Gain Register Bits 7 and 6 control the gain and bits 3 through 0 select the analog input channel See the Mux Gain Register bit description earlier in this chapter for gain and analog input channel bit patterns Set up the bits as given in the Mux Gain Register bit description and write to the Mux Gain Register Once set up with an initial value the Mux Gain Register needs to be written to only when you need to change the analog input channel or gain setting National Instruments Corporation 4 51 AT MIO 16D User Manual Programming Chapter 4 2 Program the sample interval counter Use Counter 3 of the Am9513A Counter Timer as the sample interval counter Counter 3 can be programmed to generate a pulse once every N counts N is referred to as the sample interval that Is the time between successive A D conversions N can be between 2 and 65 536 One count is equal to the period of the t
151. ation is generally considered acceptable Four times the accuracy of the AT MIO 16D is 0 003 To calibrate the AT MIO 16D board you need the following equipment For analog input calibration a precision variable DC voltage source usually a calibrator Accuracy 0 001 standard 0 003 sufficient Range greater than 10 V Resolution 100 in 10 V range 51 2 digits For analog output calibration a voltmeter Accuracy 0 001 standard 0 003 sufficient Range greater than 10 V Resolution 100 in 10 V range 51 2 digits National Instruments Corporation 5 1 AT MIO 16D User Manual Calibration Procedures Chapter 5 Calibration Trimpots There are eight trimpots on the AT MIO 16D for calibration The location of these trimpots on the AT MIO 16D board is shown in the partial diagram of the board below in Figure 5 1 ETT d Siento U4360000000000000 duc M E Smeg APCS C7 I Bee M Iove LS 4 lez 000007 00000007 8 5874 Dii 000000 Sm 00000000 5 55 60000 000001 000000 a UID Ol 49 14 000000000 vm Figure 5 1 Calibration Trimpot Location Diagram The following trimpots are used to calibrate the analog input circuitry R1 Gain trim analog input R6 Bipola
152. ational Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products AT MIO 16D Model Number for example AT MIO 16DL 9 MIO 16 Circuitry Interrupt Level of AT MIO 16D Factory Setting 10 DIO 24 Circuitry Interrupt Level of AT MIO 16D Factory Setting 5 DMA Channels of AT MIO 16D Factory Setting 6 and 7 Base I O Address of AT MIO 16D Factory Setting hex 0220 NI DAQ Version Other Products Computer Make and Model Microprocessor Clock Frequency of Video Board Installed DOS Version Programming Language Programming Language Version Other Boards System Base I O Address of Other Boards DMA Channels of Other Boards Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title 16 User Manual Edition Date March 1995 Part Number 320489 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publication
153. ational Instruments Corporation 2 31 AT MIO 16D User Manual Configuration and Installation Chapter 2 Ground Instrumentation Reference J Amplifier Signal Source Measured Common m Voltage Mode Noist and So MIO 16 I O Connector AT MIO 16D Board in NRSE Input Configuration Figure 2 30 Single Ended Input Connections for Grounded Signal Sources Common Mode Signal Rejection Considerations Figures 2 27 and 2 30 located earlier in this chapter show connections for signal sources that are already referenced to some ground point with respect to the AT MIO 16D In these cases the instrumentation amplifier can reject any voltage due to ground potential differences between the signal source and the AT MIO 16D In addition with differential input connections the instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the AT MIO 16D The common mode input range of the AT MIO 16D instrumentation amplifier is defined as the magnitude of the greatest common mode signal that can be rejected The common mode input range for the AT MIO 16D depends on the size of the differential input signal V and the gain setting of the instrumentation amplifier The exact formula for the allowed common mode input range is as follows Vdiff Gain Vem max 12 V 2 where the maximum value for is as follows 10 V range V diff max 10 V 0 to 10 V range
154. ational Instruments Corporation 4 27 AT MIO 16D User Manual Programming Chapter 4 Am9513A Command Register The Am9513A Command Register controls the overall operation of the Am9513A Counter Timer and controls selection of the internal registers accessed through the Am9513A Data Register Address Base address 1A hex Type Write only Word Size 16 bit Bit Map 15 14 13 2 11 10 9 8 7 6 3 4 3 2 1 0 Bit Name Description 15 8 1 These bits must always be set when writing to the Am9513A Command Register 7 0 C lt 7 0 gt These eight bits are loaded into the Am9513A Command Register See Appendix E Am9513A Data Sheet for the detailed bit description of the Am9513A Command Register AT MIO 16D User Manual 4 28 National Instruments Corporation Chapter 4 Programming Am9513A Status Register The Am9513A Status Register provides information about the output pin status of each counter in the Am9513A Address Base address 1A hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp 7 6 5 4 3 2 1 0 5 OUT4 OUT3 OUT2 OUTI BYTEPTR Bit Name Description 15 6 X Don t care bits 5 1 OUT 5 1 Each of these five bits returns the logic state of the associated counter output pin For example if OUTA is set then the output pin of Counter 4 is at a logic high state 0 BYTEPTR This bit represents the state of the Am9513A Byte Pointer Flip Flop This bit has no significance for AT MIO 16D
155. ational Instruments Corporation 4 55 AT MIO 16D User Manual Programming Chapter 4 First make certain that Counter 3 is reset as described in the Resetting the Hardware after a Data Acquisition Operation section later in this chapter If Counter 3 is not reset it may be driving the EXTCONV line and therefore prevent another signal from successfully driving the line high or low 1 Select analog input channel and gain The analog input channel and gain are selected by writing to the Mux Gain Register Bits 7 and 6 control the gain and bits 3 through 0 select the analog input channel See the Mux Gain Register bit description earlier in this chapter for gain and analog input channel bit patterns Set up the bits as given in the Mux Gain Register bit description and write to the Mux Gain Register The Mux Gain Register needs to be written to only when you need to change the analog input channel or gain setting 2 Clear the A D circuitry Before starting the data acquisition operation the A D FIFO must be emptied to clear out any old A D conversion results Write 0 to the A D Clear Register to empty the FIFO 3 Service the data acquisition operation Once an external trigger starts the data acquisition operation the operation is serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Re
156. atus Register can be used to read the state of different pieces of the AT MIO 16D hardware Bit descriptions of the three registers making up the Configuration and Status Group are given on the following pages National Instruments Corporation 4 5 AT MIO 16D User Manual Programming Chapter 4 Command Register 1 Command Register 1 contains ten bits that control AT MIO 16D interrupts direct memory access DMA and some analog input and output modes Address Base address hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp 7 6 5 4 3 2 1 0 CONVINTEN DBDMA DMAEN DAQEN SCANEN SCANDIV 16 32CNT 2SCADC Bit Name Description 15 10 X Don t care bits 9 DAQSTOPINTEN This bit enables and disables the generation of an interrupt when a data acquisition operation is terminated This termination can be caused by either the normal completion of a data acquisition operation or by an error condition If an error condition occurs either OVERFLOW or OVERRUN is set in the Status Register The interrupt is serviced by writing to the A D Clear Register If DAQSTOPINTEN is cleared no data acquisition termination interrupts are generated 8 TCINTEN This bit enables and disables generation of an interrupt when a DMA terminal count pulse is received from the DMA controller in the PC AT If TCINTEN is set an interrupt request is generated when the DMA controller transfer count register decrements from 0 to FFFF
157. bed in Chapter 4 Programming You can use the AT MIO 16D with LabVIEW for Windows or LabWindows for DOS LabVIEW and LabWindows are innovative program development software packages for data acquisistion and control applications LabVIEW uses graphical programming whereas LabWindows enhances Microsoft C and QuickBASIC Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation Part numbers for these software packages are listed in the following table LabVIEW for Windows 776670 01 LabWindows Standard package 776473 01 Advanced Analysis Library 776474 01 Standard package with the Advanced Analysis 776475 01 Library AT MIO 16D User Manual 1 4 National Instruments Corporation Chapter 1 Introduction Optional Equipment Equipment Part Number CB 100 I O connector block 0 5 m cable 776455 01 1 0 m cable 776455 02 Type NB5 100 conductor ribbon cable 0 5 m cable 181304 05 1 0 m cable 181304 10 SCXI signal conditioning modules SCXI 1100 32 channel differential multiplexer amplifier 776572 00 SCXI 1120 8 channel isolated analog input 776572 20 SCXI 1121 4 channel isolated transducer amplifier with excitation 776572 21 SCXI 1140 8 channel simultaneously sampling differential amplifier 776572 40 SCXI 1180 feedthrough panel 776572 80 SCXI 1181 breadboard 776572 81 AMUX 64T analog multiplexer board without cable 776366 90 with 0 2 m ribbon cable 776366 02 wi
158. board jumper To program the single channel DMA operation perform the following steps after the circuitry on the AT MIO 16D is set up for a data acquisition operation and before the data acquisition operation begins 1 Set the DMAEN bit in Command Register 1 to enable DMA request generation 2 Program the DMA controller to service DMA requests from the AT MIO 16D board Refer to the IBM Personal Computer AT Technical Reference manual for more information on DMA controller programming 3 If aDMA terminal count is received after the DMA service write 0 to either the DMATC Clear Register or the A D Clear Register to clear the DMATC bit in the Status Register Once steps 1 and 2 are completed the DMA controller automatically reads the A D FIFO Register whenever an A D conversion result is available and then stores the result in a buffer in memory To program the dual channel DMA operation perform the following steps 1 Set the DMAEN and DBDMA bits in Command Register 1 2 Write 0 to either the DMATC Clear Register or the A D Clear Register AT MIO 16D User Manual 4 76 National Instruments Corporation Chapter 4 Programming 3 Program the DMA controller to set up two DMA channels and two memory buffers for each DMA channel data collection 4 After the DMA service write 0 to either the DMATC Clear Register or the A D Clear Register During the DMA operation DMA Channel 1 and Memory Buffer 1 DMA 1 are served first When a
159. btained by reading Port C The Port C status word bit definitions for a Mode 2 transfer are shown as follows The following are the Port C status word bit definitions for bidirectional data path Port A only 7 6 5 4 3 2 1 0 OBFA INTEI IBFA INTE2 INTRA Bit Name Description 7 Output buffer full Low indicates that the CPU has written data to Port A continues National Instruments Corporation 4 87 AT MIO 16D User Manual Programming Chapter 4 Bit Name Description continued 6 INTEI Interrupt enable bit for output If this bit is set DIO interrupts are enabled from the 82C55A for OBFA Controlled by bit set reset of PC6 5 IBFA Input buffer full High indicates that data has been loaded into the input latch of Port A 4 INTE2 Interrupt enable bit for input If this bit is set DIO interrupts are enabled from the 82C55A for IBFA Controlled by bit set reset of PC4 3 INTRA Interrupt request status If INTEI is high and IBFA is high this bit is high indicating that a DIO interrupt request is asserted for input transfers If INTE2 is high and is high this bit is high indicating that a DIO interrupt request is asserted for output transfers 2 1 0 Extra I O status lines available if Port is not configured for Mode 1 At the DIO 24 I O connector Port C has the following pin assignments when in Mode 2 Mode 2 Programming Example Main define BASE ADDRESS 0x210 Bo
160. can use signals connected to any of the Am9513A SOURCE input pins To program the scan interval counter use the following programming sequence All writes are 16 bit operations All values given are hexadecimal a Write FF02 to the Am9513A Command Register to select the Counter 2 Mode Register b Write the mode value to the Am9513A Data Register to store the Counter 2 mode value Use one of the following mode values 8B25 Selects 1 MHz clock 8C25 Selects 100 kHz clock 8025 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum c Write FFOA to the Am9513A Command Register to select the Counter 2 Load Register d Write 2 to the Am95134A Data Register to store the Counter 2 load value e Write FF42 to the Am9513A Command Register to load Counter 2 f Write FFF2 to the Am9513A Command Register to step Counter 2 down to one g Entries stored in the mux gain memory should be scanned once during a scan interval The following condition must be satisfied scan interval 2 sample interval x where x is the number of entries in the scan sequence Write the desired scan interval to the Am9513A Data Register to store the Counter 2 load value e Ifthe scan interval is between 2 and FFFF 65 535 decimal write the scan interval to the Am9513A Data Register e If the scan interval is 10000 65 536 decima
161. cimal write the sample count to the Am9513A Data Register e Ifthe sample count is 10000 65 536 decimal write 0 to the Am9513A Data Register e Write FF48 to the Am9513A Command Register to load Counter 4 f Write FFF4 to the Am9513A Command Register to decrement Counter 4 g Write FF28 to the Am9513A Command Register to arm Counter 4 h Clear the 16 32 CNT bit in Command Register 1 to notify the hardware that only Counter 4 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition operation when Counter 4 decrements to zero Counter 4 begins counting A D conversion pulses when a rising edge signal is received on the STOP TRIG input A D conversion data stored before receipt of the STOP TRIG signal are pretrigger samples Sample Counts Greater Than 65 536 To program the sample counter for sample counts greater than 65 536 use the following programming sequence The lower 16 bits of the sample count are stored in Counter 4 and the upper 16 bits of the sample count are stored in Counter 5 AII writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 9025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register
162. counter must be armed before appii cation of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded irrespective of the Gate level the counter will count all source edges after the triggering Gate edge until the first TC On the first TC the counter will be reloaded from the Load register and disarmed A new ARM command and a new Gate edge must be applied in that order to initiate a new counting cycle Unlike Modes C F and L which disregard the Gate input once counting starts in Mode the count process will be retriggered on all active going Gate edges including the first Gate edge used to start the counter On each retriggering Gate edge the counter contents will be transferred into the Hold register On the first source edge after the retriggering Gate edge the Load register contents will be transferred into the counter Counting will resume on the second source edge after a retrigger Appendix E 2 136 Am9513A AT MIO 16D User Manual E 22 National Instruments Corporation Appendix E AAAI CD CD ED D AMD Am9513A Data Sheet OUTPUT Figure 150 Mode Waveforms MODE Q Rate Generator with Synchronization Event Counter with Auto Read Reset Fes cusa curs cusa cars dx Mode shown Figure 15 provides a rate gen
163. cquisition Rates 3 10 AT NIO TOD Repister eodd nel neat ete esie teh ae 4 1 Straight Binary Mode A D Conversion Values eene 4 45 Two s Complement Mode A D Conversion Values eese 4 45 Multiple Channel Data Acquisition 0 4 68 Analog Output Voltage Versus Digital Code Unipolar Mode 4 7 Analog Output Voltage Versus Digital Code Bipolar Mode 4 72 RTSI Switch Signal Connections Sees a eee tes eee alas 4 74 Port Seu Reset Control Words c iinne a a 4 80 Mode 0 T O Cone uration s dssdo eiue ecce iie ste 4 81 DIO 24 Interrupt Enable Signals for All Mode Combinations 4 9 National Instruments Corporation AT MIO 16D User Manual Chapter 1 Introduction This chapter describes the AT MIO 16D lists the contents of your AT MIO 16D kit the optional software and optional equipment and explains how to unpack the AT MIO 16D The AT MIO 16D combines the functionality of two popular National Instruments boards the AT MIO 16 and the PC DIO 24 The AT MIO 16D contains two logical sections the MIO 16 circuitry and the DIO 24 circuitry Henceforth we will refer to the entire board as the AT MIO 16D and to a particular logical part of the board as either the MIO 16 or DIO 24 circuitry The MIO 16 circuitry contains a 12 bit ADC with up to 16 analo
164. cted interrupts are enabled if PC2 is logic low If PC2 is logic high interrupts from the DIO 24 circuitry are disabled Table 4 10 summarizes which signal should be used as the interrupt enable for all mode combinations AT MIO 16D User Manual 4 90 National Instruments Corporation Chapter 4 Programming Table 4 10 DIO 24 Interrupt Enable Signals for All Mode Combinations Port B Port A Interrupt Mode 0 Mode 0 Enable Bit The recommended jumper settings for W14 are as follows e PC6 If Port A is in Mode 1 input e PC4 If Port A is in Mode 1 output e PC2 If Port A is in Mode 2 Port B is not in Mode 1 To enable interrupts from the DIO 24 circuitry of the AT MIO 16D board select PC2 PC4 or PC6 as the active low interrupt enable signal Initially set the selected bit high to disable unwanted interrupts Program the DIO 24 circuitry for the I O mode you want To enable interrupts from the 82 55 set either the INTEA or the INTEB bit to enable interrupts from Port A or Port B respectively In Mode 2 set either INTEI or INTE2 for interrupts on input or output transfers After interrupts have been enabled from the 82C55A clear the selected interrupt enable bit to enable interrupts from the DIO 24 circuitry An external signal can be used to interrupt the AT MIO 16D when Port A or Port B is in Mode 0 Select PC2 PC4 or PC6 as the interrupt enable bit and clear the selected bit to enable interrupts
165. ctronic Products Division 3M part number 3439 2 amp Ansley Corporation part number 609 0005 Unpacking Your AT MIO 16D board is shipped in an antistatic plastic bag to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions Touch the plastic bag to a metal part of your PC chassis before removing the board from the bag Remove the board from the bag and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer National Instruments Corporation 1 7 AT MIO 16D User Manual Chapter 2 Configuration and Installation This chapter describes the AT MIO 16D jumper configuration installation of the AT MIO 16D board into the PC signal connections to the AT MIO 16D board cable wiring and handshake timing diagrams for the DIO 24 circuitry of the AT MIO 16D Board Configuration The AT MIO 16D contains 14 jumpers and one dual inline package DIP switch to configure the AT bus interface and analog input output I O settings The DIP switch is used to set the base I O address Three jumpers are used as interrupt and direct memory access DMA selectors The remaining 11 jumpers are used to change the analog input and analog output circuitry The jumpers are shown
166. d to the RTSI bus Single Conversions You can initiate single A D conversions by applying an active low pulse to the EXTCONV input on the I O connector or by writing to the Start Convert Register on the AT MIO 16D board During data acquisition the onboard sample interval counter Counter 3 of the Am9513A Counter Timer generates pulses that initiate A D conversions External control of the sample interval is possible by applying a stream of pulses at the EXTCONV input In this case you have complete external control over the sample interval and the number of A D conversions performed Sample Interval Timer The sample interval timer is a 16 bit down counter that can be used with the five internal timebases of the Am9513A to generate sample intervals from 2 usec to 6 sec see the Timing I O Circuitry section later in this chapter The sample interval timer can also use any of the external clock inputs to the Am9513A as a timebase During data acquisition the sample interval counts down at the rate given by the internal timebase or external clock Each time the sample interval timer reaches zero it generates a pulse and reloads with the programmed sample interval count This operation continues until data acquisition halts Sample Counter The onboard sample counter can control data acquisition Load this counter with the number of samples to be taken during a data acquisition operation The sample counter can be 16 bit for counts up to
167. damages resulting from any such signal connections AT MIO 16D I O Connector Pin Description Figure 2 24 shows the pin assignments for the AT MIO 16D I O connector Refer to MIO 16 Signal Connection Descriptions and DIO 24 Signal Connection Descriptions later in this chapter for descriptions of the AT MIO 16D signal connections National Instruments Corporation AI GND AI GND ACHO ACH8 1 ACH9 ACH2 ACH10 ACH3 ACHII ACHA ACHI2 5 13 6 14 ACH7 ACHI5 AI SENSE DACO OUT DACI OUT EXTREF AO GND DIG GND ADIOO BDIOO ADIOI BDIOI ADIO2 BDIO2 ADIO3 BDIO3 DIG GND 5 5 SCANCLK EXTSTROBE START TRIG STOP TRIG EXTCONV SOURCEI GATEI OUTI SOURCE2 GATE2 OUT2 SOURCES GATES OUTS FOUT 6 56 8 58 59 10 60 16 66 18 68 19 69 30 80 36 86 39 89 40 90 46 96 48 O8 49 99 2 21 DWAVAVAVAVATAVOVAVAVOVAVOVOAVAVOAYVAY gt gt gt gt gt C EegrgtpeETgvgp egpuigeguegp Pag pg Figure 2 24 AT MIO 16D I O Connector Pin Assignments AT MIO 16D User Manual Configuration and Installation MIO 16 I O Connector Pin Description Chapter 2 Figure 2 25 shows the pin assignments for the MIO 16 I O connector of the AT MIO 16D AI GND ACHO ACHI ACH2 ACH3 ACHA 5 ACH6 ACH7 AI SENSE DACI OUT
168. data bus When inputs are ignored The first Chip Select signal after power up is software reset command must be issued following The active low Read signal is conditioned by Chip Select and indicates that internal information is be transferred to the data bus The source will be determined by the being addressed and for Data Port reads by the contents of the Data Pointer register WA and shouid be mutually exclusive The active low Write signa is conditioned by Chip Select and indicates that data bus information is be transferred to an internal location The destination will be determined by the being addressed and for Data Port writes by the contents of the Data Pointer register WR and RD should be mutually exctusive Control Data Tha CO ee ee sourco and locations for Raad and Wms operations on the data bus Contro Write operations load the Command register and the Data Pointer Control Read operations output the Status register Data Read and Data Write transfers communicate with other internal registers indirect addressing at the data part is controlled internally by the Data Pointer register 2 120 9513 16 User Manual 6 National Instruments Corporation didici dE S bu ER D Appendix Chip Select Control Data Source N Gate N Data Bus Figure 1 interface Signal Summary Figure 1 summarizes the i
169. de and provides a true OUT signal when the counter contents match the contents of an Alarm register 087 Data Bus The 16 bidirectional Data Bus lines are used for information exchanges with the host processor DB8 D815 HIGH on a Data Bus line corresponds to one and LOW corresponds to zero These lines act as inputs when WA and CS are active and as outputs when RD and CS are active When CS is inactive these pins are placed in a high impedance state After power up or reset the data bus will be configured for 8 bit width and will use oniy through 087 080 is the least significant and is the most significant bit position The data bus may be for 16 bit width by changing a control bit in the Master Mode register This is accomplished by writing an 8 bit command into the low order lines while holding the DB13 0815 lines at a logic high level Thereator M 16 CN TOS used with D90 as The and as Ue most Saran bit es When operating in the d cit data bus envionment DES 15 will never be driven active by the Am9513A DBS through 0812 may optionally be used as additional Gate inputs see Figure 2 If unused they should be held HIGH When pulled LOW a GATENA signal will disable the action of the counter N gating DB13 DB15 should be held HIGH in 8 bit bus mode whenever CS and simultaneously active Chip Select The active low Chip Select input enables Read and Write operations on the
170. detected on OUT2 This interrupt can be used to update the DACs or to interrupt on an external signal connected to OUT2 through the I O connector Counters 3 and 4 of the Am9513A are dedicated to data acquisition timing and therefore are not made available for general purpose timing applications Signals generated at OUT3 and OUTA are provided to the data acquisition timing circuitry GATES is controlled by the data acquisition timing circuitry Counter 5 is sometimes used by the data acquisition timing circuitry and concatenated with Counter 4 to form a 32 bit sample counter The SCAN CLK signal is connected to the SOURCE3 input of the Am9513A and is provided to the data acquisition timing circuitry This allows Counter 1 to be used to divide the SCAN CLK signal for generating the MUX CTR CLK signal see the Data Acquisition Timing Circuitry section earlier in this chapter Counter 2 is sometimes used by the data acquisition timing circuitry to assign a time interval to each cycle through the scan sequence programmed in the mux gain memory This mode is called interval channel scanning See the Multiple Channel Scanned Data Acquisition section earlier in this chapter The Am9513A 3 bit programmable frequency output channel is provided at the I O connector FOUT pin Any of the five internal timebases and any of the counter SOURCE or GATE inputs can be selected as the frequency output source The frequency output channel divides the select
171. dows 320499 01 If your kit is missing any of the components or if you received the wrong version contact National Instruments National Instruments Corporation 1 3 AT MIO 16D User Manual Introduction Chapter 1 Your AT MIO 16D is shipped with the NI DAQ software for DOS Windows LabWindows NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer SCXI RTSI and self calibration NI DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to your code NI DAQ comes with language interfaces for Professional BASIC Turbo Pascal Turbo C Turbo C Borland C and Microsoft C for DOS and Visual Basic Turbo Pascal Microsoft C with SDK and Borland C for Windows NI DAQ software is on high density 5 25 in and 3 5 in diskettes Optional Software This manual contains complete instructions for directly programming the AT MIO 16D Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the AT MIO 16D is included with the board Using NI DAQ is quicker and easier than and as flexible as using the low level programming descri
172. e eee SRE ES In this mode the reload source for LOAD commands irre Spective of whether the counter is armed or disarmed and for TC initiated reloads is determined by the Gate input The Gate input in Mode S is used only to select the reioad source not to Start or modulate counting When the Gate is Low the Load register is used when the Gate is High the Hold register is used Note the Low Load High Hold mnemonic convention Once armed the counter will count to TC twice and then disarm itseif On each TC the counter will be reloaded from the reload source selected by the Gate Following the second TC an ARM command is required to start a new counting cycle Mode S is shown in Figure 15s 2 138 AT MIO 16D User Manual MODE V Frequency Shift Keying Mode V shown in Figure 15v provides frequency shift keying modulation capability Gate operation in this mode is identical to that in Mode S If the Gate is Low a LOAD command or a TC induced reload will reload the counter from the Load register If the Gate is HIGH LOADs and reloads will occur from the Hold register The polarity of the Gate only selects the reload source it does not start or modulate counting Once armed the counter will count repetitively to TC On each TC the counter will reload itself from the register determined by the polarity of the Gate Counting will continue in thi
173. e ONE etienne 4 37 DIO 24 POR TB ReBISEGE aeg erre de ecce Hee te des 4 38 DICEZ4 POR TC Registers o PROS 4 30 DIO 2Z4 C NPGr Register zelo uta adden dec te Dua 4 40 MIO 16 Programming Considerations eese esee nennen enne 4 4 Register Programming Considerations 4 4 Initializing the MIO 16 Circuitry of the AT MIO 16D Board 4 4 Initiahzing the Am99513 cio soda def desee 4 42 Initializing the Analog Output Circuitry eene 4 43 National Instruments Corporation AT MIO 16D User Manual Contents Programming the Analog Input Circuitry 4 43 A D FIFO Output Binary 15 222 24 41 1 11 4 44 Clearing the Analog Input Circuitry eee 4 45 Programming Multiple A D Conversions on a Single Input Channel 4 46 External Timing Considerations for Multiple A D Conversions 4 51 Pretriggering with the STOP TRIG 22222 22 4 51 Controlling Multiple A D Conversions with the EXTCONV Signal 4 55 Programming Multiple A D Conversions with Channel Scanning 4 57 Multiple A D Conversions with Continuous Channel Scanning Round oerte crit reete tese boss SIT ETC ERR QURE 4 57 Mult
174. e National Instruments Corporation 4 67 AT MIO 16D User Manual Programming Chapter 4 checked every time the Status Register is read to check the CONVAVAIL bit If either of these error conditions occurs the data acquisition operation stops An overflow condition occurs if more than 512 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if a second A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is set Scanned data acquisition requires slower acquisition rates than single channel data acquisition because signals must settle each time channels are switched See Table 4 4 for the maximum recommended multiple channel data acquisition rates The rates in Table 4 4 refer to typical settling accuracies of 0 5 LSBs of the final value Table 4 4 Multiple Channel Data Acquisition Rates Data Acq
175. e 20 shows ali the unused code combinations unused codes should not be entered into the Command register since undefined activities may occur Six of the command types are used for direct software control of the counting process and they each contain a 5 bit S field In a linear select fashion each bit in the S field corresponds to one of five general counters 51 Counter 1 S2 Counter 2 etc When an S bit is a one the specified operation is performed on the counter so designated when an S bit is a zero no operation occurs for the corresponding counter This type of command format has three basic advantages saves host software by allowing any combination of counters to be acted on by a singie command It allows simultanecus action on muitiple counters where synchronization of commands is important It allows counter specific service routines to control individual counters without needing to be aware of the operating context of other counters Three of the commands use a 3 bit binary code N4 N2 1 to identify the affected counter a 001 programs counter 1 etc Unlike the previously mentioned commands these commands allow you to program only one counter at a time Am9513A 2 143 E 29 National Instruments Corporation AT MIO 16D User Manual AMD Am9513A Data Sheet Appendix E Command Description Load Data Pointer register with contents of E and G fields 000 G 110 sS counting
176. e Am9513A The Am9513A counters can be individually programmed to count rising or falling edges of signals applied at any of the Am9513A SOURCE or GATE input pins In addition to the signals applied to the SOURCE and GATE inputs the Am9513A generates five internal timebase clocks from the clock signal supplied by the AT MIO 16D This clock signal is selected by the W5 jumper and then divided by 10 The factory default value is 1 MHz into the Am9513A 10 MHz clock signal on the AT MIO 16D The five internal timebase clocks can be used as counting sources and these clocks have a maximum skew of 75 nsec between them The SOURCE signal shown in Figure 2 38 represents any of the signals applied at the SOURCE inputs GATE inputs or internal timebase clocks See Appendix E 9513 Data Sheet for further details Specifications for signals at the GATE input are referenced to the signal at the SOURCE input or one of the Am9513A internally generated signals Figure 2 39 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low at least 100 nsec before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by tgsu and tgh in Figure 2 39 Similarly the gate signal must be held for at least 10 nsec after the rising or falling edge of a source signal for the gate to take effect at that source edge The gate high or low period must be at least 145 nsec i
177. e Am9513A Data Register h Write FF24 to the Am9513A Command Register to arm Counter 3 After you complete this programming sequence Counter 3 is configured to generate A D conversion pulses as soon as you enable it by applying a trigger 3 Program the sample counter Counters 4 and 5 of the Am9513A Counter Timer are used as the sample counter The sample counter tallies the number of A D conversions initiated by Counter 3 and stops Counter 3 when the desired sample count is reached If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 both Counters 4 and 5 must be used AT MIO 16D User Manual 4 52 National Instruments Corporation Chapter 4 Programming Sample Counts 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the following programming sequence The minimum permitted sample count is two All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 9025 to the Am95134A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the sample count value to Am95134A Data Register to store the Counter 4 load value Ifthe sample count is between 2 and FFFF 65 535 de
178. e Counter Mode register controls the gating counting output and source select functions within each Counter Logic Group The Counter Mode Controi Options section of this document describes the detailed control options available Figure 16 shows the bit assignments for the Counter Mode registers Alarm Registers Comparators Added functions are available in the Counter Logic Groups tor Counters 1 and 2 see Figure 4 Each contains a 16 bit Alarm register and a 16 bit Comparator When the value in the Counter reaches the value in the Alarm register the Compara tor output will go true The Master Mode register contains contro bits to individually enable disable the comparators When enabled the comparator output appears on the OUT of the associated counter in piace of the normal counter output The output will remain true as long as the comparison is true that is until the next input causes the count to change The polarity of the Comparator output will be active high if the Output Control field of the Counter Mode register is 001 or 010 and active low if the Output Control field is 101 MASTER MODE CONTROL OPTIONS The 16 bit Master Mode MM register is used to control those internal activities that are not controlled by the individual Counter Mode registers This includes frequency control Time of Day operation comparator controis data bus width and data pointer sequencing Figure 11 shows the bit assign ments fo
179. e Gate be modulated throughout the count cycle to stop and start the counter EERE AOI VALUE TC TOOGLED i i Y Figure 15c Mode C Waveforms 2 130 AT MIO 16D User Manual Am9513A E 16 Appendix E O National Instruments Corporation Appendix MODE Rate Generator with No Hardware Gating 15 cur CMe cme po poy xt xi xi xt x cus 2 cmo 1 1 x Mode D shown in Figure 15d is typically used in frequency generation applications In this mode the Gate input does not affect counter operation Once armed the counter will count to TC repetitively On each TC the counter will reload itself from the Load register hence the Load register value determines the time between TCs A square wave rate generator may be obtained by specifying the TC Toggled output mode in the Counter Mode register AMD Am9513A Data Sheet MODE E Rate Generator with Level Gating Lewis ewe cue cura curs oma owe wm eur cus cus cus Mods E shown in Figure 15 is identical to Mode D except the counter will only count those source edges which occur while the Gate input is active This feature allows the counting process to be enabled and disab
180. e Onboard Oscillator Factory Setting Eton 2 19 Figure 2 22 Receive RTSI Bus Clock Signal opio atest 2 19 Figure 2 23 Drive RTSI Bus Clock Signal with Onboard Oscillator 2 20 Figure 2 24 16 I O Connector Pin 51 2 21 Figure 2 25 16 I O Connector Pin Assignments eee 2 22 Figure 2 26 AT MIO 16D Instrumentation Amplifier 2 26 Figure 2 27 Differential Input Connections for Grounded Signal Sources 2 28 Figure 2 28 Differential Input Connections for Floating 2 29 Figure 2 29 Single Ended Input Connections for Floating Signal Sources 2 31 Figure 2 30 Single Ended Input Connections for Grounded Signal Sources 2 32 Figure 2 31 Analog Output ae et ees i ee ee 2 34 Figure 2 32 Digital UO CONDECHOS eiae ode e Bi Beat ea 2 35 Figure 2 33 EXTSTROBE Signal Timing iiec Gesta ins Reads 2 36 Figure 2 34 EXTCONV Signal Timing uode reote Diete pa tds 2 37 Figure 2 35 START TRIG Signal Ting oer i Sie ede 2 38 Figure 2 36 STOP TRIG Signal 2 38 Figure 2 37 Event Counting Application w
181. e between the desired voltage and the actual output voltage generated which depends on the D A setting This gain error is corrected by setting the D A to positive full scale and adjusting a trimpot until the output voltage corresponds to the positive full scale value 2 LSB Board Configuration The calibration procedure differs if you select either bipolar or unipolar output configuration A procedure for each configuration is given below The calibration procedures presented in this chapter assume that the internal voltage reference 10 V is selected for the analog output channel to be calibrated To calibrate your board to an external reference input DC only you must recalculate the desired output voltages to calibrate to e For bipolar output 1 LSB Vextref 2 048 therefore 2 LSB V extref 4 096 Vextref Vextref 1 LSB e For unipolar output 1 LSB Vextref 4 096 therefore 2 LSB Vextref 8 192 Vg 20V Vits Vexget 1 LSB In calibrating to your own external reference you should write your own procedures using the following procedures as a guide Substitute your calculated voltages for those given Bipolar Output Calibration Procedure If your board is configured for bipolar output and two s complement mode which provides an output range of 10 to 10 V then complete the following procedure in the order given 1 Adjust the analog output offset Adjust the analog output offset by measu
182. e low pulse is detected on the OUT2 bit of the Am9513A Counter Timer The update method is selected with the LDAC bit in Command Register 2 The third register in the Analog Output Register Group is the INT2CLR Register The AT MIO 16D can be programmed to interrupt when it detects a rising edge signal on the OUT2 pin of the Am9513A Counter Timer This interrupt can be cleared by writing to the INTZCLR Register Descriptions of the three registers making up the Analog Output Register Group are given on the following pages AT MIO 16D User Manual 4 16 National Instruments Corporation Chapter 4 Programming DACO Register Writing to DACO loads the corresponding analog output channel DAC The voltages generated by the analog output channels are updated either immediately or when an active low pulse occurs on OUT2 The update method is selected by the LDAC bit in Command Register 2 Address Base address 10 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xX x x x DiI pid D9 D6 D7 D5 D4 D3 D2 DI DO MSB LSB Bit Name Description 15 12 X Don t care bits 11 0 D lt 11 0 gt These 12 bits are loaded into the DAC and update the voltage generated by the analog output channel in one of two ways immediately or upon an OUT2 pulse See the Programming the Analog Output Circuitry section later in this chapter for Table 4 5 and 4 6 both of which map digital va
183. e preceding steps the data acquisition operation is initiated when a trigger is received A trigger can be provided in one of two ways through software or through hardware To initiate the data acquisition operation through software write 0 to the Start Register To initiate the data acquisition operation through hardware apply an active low pulse to the START TRIG pin on the AT MIO 16D I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for START TRIG signal specifications Once the trigger is applied Counter 3 generates pulses initiating A D conversions once every sample interval until the sample counter reaches zero 7 Service the data acquisition operation Once the data acquisition operation is started by application of a trigger the operation is serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Read the Status Register 16 bit read b If the CONVAVAIL bit is set bit 13 read the A D FIFO Register to obtain the result Interrupts or DMA can also be used to service the data acquisition operation These topics are discussed later in this chapter Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Re
184. e the Gate is inactive This permits the Gate to tum the count process on and off After the issuance of the ARM command and the application of an active Gate the counter will count to TC Upon reaching TC the counter will reload from the Load register and automatically disarm itself inhibiting further count ing Counting wili resume upon the issuance of a new ARM command active going Gate edges issued to an armed counter will cause a retrigger operation Upon application of the Gate edge the counter contents will be saved in the Hoid register On the first qualified source edge after application of the retriggering gate edge the contents of the Load register will be transferred into the counter Counting will resume on occur while the Gate is active 2 135 National Instruments Corporation E21 AT MIO 16D User Manual AMD Am9513A Data Sheet AANA XAOS Figure 15 Mode L Waveforms CD CE CO Figure 15n Mode N Waveforms MODE O Software Triggered Strobe with Edge Gating and Hardware Retriggering 1 14 cma 12 Curt 10 cms emcee x Ex x x cms cus 2 CMO Mode shown in Figure 150 is similar Mode N except that counting will not begin until an active going Gate edge is applied to an armed counter and the Gate level is not used to modulate counting The
185. east one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if an A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is set The maximum recommended single channel data acquisition rate for the AT MIO 16D is 100 ksamples sec Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A D Clear Register Once steps 1 through 5 of this sequence are completed Counter 3 is armed and begins generating pulses The sample counter does not begin counting samples until a rising edge signal is detected on the STOP TRIG input When the sample count decrements to zero the data acquisition operation is halted The STOP TRIG signal specifications are given in Chapter 2 Configuration and Installation Controlling Multiple A D Conversions with the EXTCONV Signal When you use EXTCONV to control multiple A D conversions none of the onboard counters are used Pulses applied to the EXTCONV input initiate the A D conversions To perform this operation complete these steps 1 Select analog input channel and gain 2 Clear the A D circuitry 3 Service the data acquisition operation N
186. ected to a common ground point with respect to the AT MIO 16D board assuming that the PC AT is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected If the grounded signal source is measured improperly this difference may show up as an error in the measurement The connection instructions for grounded signal sources below are designed to eliminate this ground potential difference from the measured signal Input Configurations The AT MIO 16D can be configured for one of three input modes NRSE RSE or DIFF following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Table 2 10 summarizes the recommended input configuration for both types of signal sources Table 2 10 Recommended Input Configurations for Ground Referenced and Floating Signal Sources Type of Signal Recommended Input Configuration Ground Referenced DIFF nonisolated outputs NRSE plug in instruments Floating DIFF with bias resistors batteries thermocouples RSE isolated outputs Differential Connection Considerations DIFF Configuration
187. ecting Analog Input Ranges Analog input polarity range selection depends on the expected input range of the incoming signal A large input range can accommodate a large signal variation but sacrifices voltage resolution Choosing a smaller input range increases voltage resolution but may result in the input signal going out of range For best results the input range should be matched as closely as possible to the expected range of the input signal For example if the input signal is guaranteed to never go negative below 0 V a unipolar input is best However if the signal does go negative inaccurate readings will occur Software programmable gain on the AT MIO 16D increases overall flexibility by matching input signal ranges to those accommodated by the AT MIO 16D analog to digital converter ADC The AT MIO 16DH board has gains of 1 2 4 and 8 and is suited for high level signals near the range of the ADC The AT MIO 16DL board is designed to measure low level signals and has gains of 1 10 100 and 500 With the proper gain setting the full resolution of the ADC can be used to measure the input signal Table 2 8 shows the overall input range and precision according to the input range configuration and gain used Table 2 8 Actual Range and Measurement Precision Versus Input Range Selection and Gain Range Configuration Actual Input Range 0to 10V 0 to 10 V 0 to 5 V 0 to 432 5 V 0 to 1 25 V 0 to 1 V 0 to 0 1 V mV to 20 mV
188. ector The pin assignments are compatible with the standard 24 channel I O module mounting racks such as those manufactured by Opto 22 and Gordos The CB 100 cable termination accessory is available from National Instruments for use with the DIO 24 circuitry of the AT MIO 16D This kit includes two 50 conductor flat ribbon cables and two 50 pin CB 50 connector blocks Signal input and output wires can be attached to screw terminals on the connector block and are therefore connected to the DIO section I O connector The CB 100 is useful for initial prototyping of an application or in situations where DIO section interconnections are frequently changed Once you develop a final field wiring scheme however you may want to develop your own cable This section contains information and guidelines for the design of custom cables National Instruments Corporation 2 51 AT MIO 16D User Manual Configuration and Installation Chapter 2 The DIO 24 circuitry I O connector is a 50 pin female ribbon cable header The manufacturers and the appropriate part numbers for this connector are as follows Electronic Products Division 3M part number 3596 5002 T amp B Ansley Corporation part number 609 5007 The mating connector for the DIO section is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the DIO section Recommended manufacturer
189. ed source by its 4 bit programmed value and provides the divided down signal at the FOUT pin RTSI Bus Interface Circuitry The AT MIO 16D is interfaced to the National Instrument RTSI bus The RTSI bus has seven trigger lines and a system clock line National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC AT and share these signals A block diagram of the RTSI bus interface circuitry is shown in Figure 3 8 National Instruments Corporation 3 15 AT MIO 16D User Manual Theory of Operation Chapter 3 WS 10 MHz Oscillator Drivers EXTCONV 4 FOUT Trigger SOURCES 7 OUTI START TRIG OUT5 Drivers STOP TRIG 9 9 Nn 24 p NH E 24 RTSI SEL SEL Internal DATA Data Bus RTSI Switch Figure 3 8 RTSI Bus Interface Circuitry Block Diagram The RTSI CLK line can be used to source a 10 MHz signal across RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus MYCLK is the system clock used by the AT MIO 16D The W5 jumpers select how these clock signals are routed The RTSI switch is a National Instruments custom integrated circuit that acts as a 7x7 crossbar switch Pins B lt 6 0 gt are connected to the seven RTSI bus trigger lines Pins A lt 6 0 gt are connected to seven signals on the board The RTSI switch can drive any of the signals at pins A lt 6 0 gt onto any one or more
190. ed in This Manual The following conventions are used to distinguish elements of text throughout this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept PC PC refers to the IBM PC AT and compatible computers Abbreviations The following metric system prefixes are used with abbreviations for units of measure in this manual The following abbreviations are used in this manual A amperes dB decibels ft feet hex hexadecimal Hz hertz kbytes 1 000 bytes ksamples 1 000 samples M megabytes of memory AT MIO 16D User Manual vi National Instruments Corporation Preface Abbreviations continued m meters Q ohms ppm parts per million sec seconds V volts Vrms volts root mean square Acronyms The following acronyms are used in this manual AC alternating current A D analog to digital ADC A D converter D A digital to analog DAC D A converter DIP dual inline package DMA direct memory access FIFO first in first out VO input output LS low power Schottky LSB least significant bit MSB most significant bit PPI programmable peripheral interface RTSI Real Time System Integration SSR solid state relays TTL transistor transistor logic VDC volts direct current Related Documentation The following document contains information that you may find helpful as you read this manual IBM Personal Computer AT Technical Reference manual You may also want to c
191. ed to the negative input of the instrumentation amplifier When the AT MIO 16D is configured for single ended input NRSE or RSE 16 analog input channels are available You can use single ended input connections when the following criteria are met by all input signals 1 Input signals are high level greater than 1 V 2 Leads connecting the signals to the AT MIO 16D are less than 15 ft 3 All input signals share a common reference signal at the source If any of the above criteria is not met using DIFF input configuration is recommended You can jumper configure the AT MIO 16D for two different types of single ended connections RSE configuration and NRSE configuration Use the RSE configuration for floating signal sources in this case the AT MIO 16D provides the reference ground point for the external signal Use the NRSE configuration for ground referenced signal sources in this case the external signal supplies its own reference ground point and the AT MIO 16D should not supply one Single Ended Connections for Floating Signal Sources RSE Configuration Figure 2 29 shows how to connect a floating signal source to an AT MIO 16D board configured for single ended input You must configure the AT MIO 16D analog input circuitry for RSE input to make these types of connections Configuration instructions are included under the Analog Input Configuration section earlier in this chapter AT MIO 16D User Manual 2 30 National Inst
192. eep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set AT MIO 16D User Manual 4 50 National Instruments Corporation Chapter 4 Programming An overrun condition occurs if an A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is set The maximum recommended single channel data acquisition rate for the AT MIO 16D is 100 ksamples sec Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A D Clear Register External Timing Considerations for Multiple A D Conversions The case of controlled data acquisition operations using the onboard sample interval and sample counters was described above The two external timing cases are described here using the STOP TRIG input to control the sample counter and applying pulses to the EXTCONV input Pretriggering with the STOP TRIG Signal In this case the sample interval counter starts counting when a rising edge signal is applied to the STOP TRIG input on the AT MIO 16D I O connector You program the sample counter for active high level gating on Gate 4 The data acquisition operation is initi
193. egister contents into the counter There after the counter will count qualified source edges When some form of Gating is specified CM7 controls hard ware retriggering in this case when CM7 0 hardware retriggering does not occur when CM7 1 the counter is retriggered any time an active going Gate edge occurs Retriggering causes the counter value to be saved in the Hold register and the Load register contents to be transferred into the counter When No Gating is specified the definition of CM7 changes In this case when CM7 0 the Gate input has no effect on the counting when CM7 1 the Gate input specifies the source selecting either the Load or Hold register used to reload the counter when TC occurs Figure 14 shows the various available control combinations for these interrelated bits Count Source Selection Counter Mode bits CM8 through CM12 specify the source used as input to the counter and the active edge that is counted Bit CM12 controls the polarity for the sources logic zero counts rising edges and logic one counts falling edges Bits CM8 through CM11 select 1 of 16 counting Sources to route to the counter input Five of the available inputs are internal frequencies derived from the internal oscillator see Figure 13 for frequency assignments Ten of the available inputs aro interface pins five are labeled SHC and five are labeled GATE The 16th available input is the TC output from the adjacent
194. elays between cycles If SCN2 is set interval channel scanning is used In this mode scan sequences occur during a programmed time interval called a scan interval One cycle of the scan sequence occurs during each scan interval This bit controls a driver that allows the STOP TRIG signal to be driven from pin A4 of the RTSI switch This bit allows a signal to be received from one of the RTSI bus trigger lines and driven onto the STOP TRIG line If A4RCV is set pin A4 of RTSI switch drives the STOP TRIG signal If A4RCV is cleared the STOP TRIG signal is not driven by the RTSI switch This bit controls a driver that allows the OUTS signal to drive pin 4 of the RTSI switch This driver allows the OUTS signal to be driven onto one of RTSI bus trigger lines If A4DRV is set pin 4 of the RTSI switch is driven by OUTS If 4 is cleared pin A4 is not driven This bit controls a driver that allows the GATEI signal to be driven from pin A2 of the RTSI switch This driver allows a signal to be received from one of the RTSI bus trigger lines and driven onto the GATE line If A2RCV is set pin A2 of the RTSI switch drives the GATEI signal If A2RCV is cleared the GATEI signal is not driven by the RTSI switch This bit controls a driver that allows the OUT2 signal to drive pin A2 of the RTSI switch This driver allows the OUT2 signal to be driven onto one of the RTSI bus trigger lines If A2DRV is set pin A2 of the RTSI switch
195. ence The minimum permitted sample count is 2 All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the sample count value to the Am9513A Data Register to store the Counter 4 load value Ifthe sample count is between 2 and FFFF 65 535 decimal write the sample count minus 1 to the Am9513A Data Register e Ifthe sample count is 10000 65 536 decimal write 0 to the Am9513A Data Register Write FF48 to the Am9513A Command Register to load Counter 4 Write FFF4 to the Am9513A Command Register to decrement Counter 4 Write FF28 to the Am9513A Command Register to arm Counter 4 Clear the 16 32 CNT bit in Command Register to notify the hardware that only Counter 4 will be used as the sample counter National Instruments Corporation 4 59 AT MIO 16D User Manual Programming Chapter 4 After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition operation when Counter 4 reaches zero Sample Counts Greater Than 65 536 To program the sample counter for sample counts greater than 65 536 use the following programming sequence The lower 16 bits of the sample c
196. enerated from the digital code depends on the configuration unipolar or bipolar of the associated analog output channel This configuration is determined by configuration jumpers on the AT MIO 16D board In bipolar mode configuration jumpers also determine if the digital code written to the DACS is in straight binary form or in a two s complement form The factory default is the bipolar configuration in two s complement mode See the Analog Input Configuration section in Chapter 2 Configuration and Installation for more information Table 4 5 shows the output voltage versus digital code for a unipolar analog output configuration Table 4 6 shows the voltage versus digital code for a bipolar analog output configuration The formula for the voltage output versus digital code for a unipolar analog output configuration is as follows Vout Vref digital code 4 096 where is the reference voltage applied to the analog output channel The digital code in the above formula is a decimal value ranging from 0 to 4 095 Table 4 5 Analog Output Voltage Versus Digital Code Unipolar Mode Digital Code Voltage Output 0 0 0 OV Vref 4 096 Vref 4 Vref 5 2 Vref 3 7 5 V 4 Vref 4 095 9 9976 V 4 096 National Instruments Corporation 4 71 AT MIO 16D User Manual Programming Chapter 4 The formula for the voltage output versus digital code for a bipolar analog output configuration in straight binary form is as follo
197. er programming 4 63 to 4 64 scan interval counter programming 4 66 servicing data acquisition operation 4 67 to 4 68 setting up analog channel and gain selection sequence 4 63 single input channel 4 46 to 4 51 applying a trigger 4 50 clearing A D circuitry 4 49 to 4 50 enabling data acquisition operation 4 50 overflow and overrun conditions 4 50 to 4 51 sample counter programming 4 48 to 4 49 sample interval counter programming 4 47 to 4 48 selecting input channel and gain 4 47 servicing data acquisition operation 4 50 to 4 51 steps for 4 46 to 4 47 pulse width measurement 2 39 pulses producing 2 39 R referenced single ended RSE input configuration 2 11 to 2 12 definition of 2 10 single ended connections for floating signal sources 2 30 to 2 31 registers See also 82C55A Programmable Peripheral Interface Am9513 Counter Timer Register Group 4 26 to 4 29 Am9513A Command Register 4 28 Am9513A Data Register 4 27 Am9513A Status Register 4 29 Analog Input Register Group 4 20 to 4 25 A D FIFO Register 4 24 DMA TC INT Clear Register 4 25 Mux Counter Register 4 21 Mux Gain Register 4 22 to 4 23 Analog Output Register Group 4 16 to 4 19 DACO Register 4 17 DACI Register 4 18 INT2Clear Register 4 19 Configuration and Status Register Group 4 3 to 4 10 Command Register 1 4 4 to 4 5 AT MIO 16D User Manual Index 20 National Instruments Corporation Index Command Register 2 4 9 to 4 10 Status Reg
198. er 4 Programming RTSI Switch Strobe Register The RTSI Switch Strobe Register is written to in order to load the contents of the RTSI Switch Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSI Switch Strobe Register is written to after shifting the 56 bit routing pattern into the RTSI Switch Shift Register Address Base address 1F hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used National Instruments Corporation 4 35 AT MIO 16D User Manual Programming Chapter 4 DIO 24 Register Group The DIO 24 circuitry uses an 82 55 integrated circuit The 82C55A is a general purpose PPI containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 82C55A These ports can be programmed as two groups of 12 signals or as three individual 8 bit ports The DIO 24 Register Group contains the following four registers DIO 24 PORTA Register DIO 24 PORTB Register DIO 24 PORTC Register and DIO 24 CNFG Register Bit descriptions for the registers in the DIO 24 Register Group are given on the following pages AT MIO 16D User Manual 4 36 National Instruments Corporation Chapter 4 Programming DIO 24 PORTA Register Reading the DIO 24 PORTA Register returns the logic state of the eight digital I O lines constituting Port A of the DIO 24 circuitry that is PA lt 7 0 gt If Port A is configured for output
199. erating levels Note howev er that input energy levels can nonetheless be too high to be Successfully absorbed Conventional design storage and handling precautions should be observed so that the protec tion networks themselves are not overstressed Within the limits of normal operation the input protection circuitry is inactive and may be modeled as a lumped series RC as shown in Figure 3 a The functionally active input Connection during normal operation is the gate of a MOS transistor No active sources or drains are connected to the inputs so that neither transient nor steady state currents are impressed on the driving signals other than the charging or discharging of the input capacitance and the accumulated leakage associated with the protection network and the input circuit I Figure 3 input Circuitry The only exception to the purely capacitive input case is the X2 crystal input As shown in Figure 3 b an internal resistor connects X1 and X2 in addition to th protection network The resistor is a modestly high value of more than 100kohms Fanout from the driving circuitry into the Am9513A inputs will generally be limited by transition time considerations rather than DC current limitations when the loading is dominated by conventional MOS circuits In an operating environment inputs should be terminated so they do not float and therefore will not accumulate stray static charges Unused inputs sh
200. eration when Counter 4 reaches zero Sample Counts Greater Than 65 536 To program the sample counter for sample counts greater than 65 536 use the following programming sequence The lower 16 bits of the sample count are stored in Counter 4 and the upper 16 bits of the sample count are stored in Counter 5 All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the least significant 16 bits of the sample count value minus 1 to the Am9513A Data Register to store the Counter 4 load value Ifthe least significant 16 bits are all zeros write FFFF e Write FF48 to the Am9513A Command Register to load Counter 4 f Write 0 to the Am9513A Data Register to store 0 into the Load Register for Counter 4 reloading g Write FF28 to the Am9513A Command Register to arm Counter 4 h Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register k Take the most significant 16 bits of the sample count and do the following e Ifthe least significant 16 bits of the sample count are all zeros or all zeros excep
201. erator with synchronization or an event counter with auto read reset The counter must first be issued ARM command before counting can occur Once armed the counter will count all source edges which occur while the Gate is active and disregard those edges which cccur while the Gate is inactive This permits the Gate to turn the count process on and off After the issuance of an ARM command and the application of an active Gate the counter will count to TC repetitively On each TC the counter will reload itself from the Load register The counter may be retriggered at any time by presenting an active going Gate edge to the Gate input The retriggering Gate edge will transfer the contents of the counter into the Hold register The first qualified source edge after the retrig gering Gate edge transfer the contents of the Load register into the Counter Counting will resume on the second TEE WF004720 MODE R Retriggerable One Shot Lewes eure cus cuna curi cu eme ox 3 x T x cus cus cus cus cuz Mode shown in Figure 15r is similar to Mode except that edge gating rather than level gating is used In other words rather than use the Gate levei to qualify which source edges to count Gate edges are used to start the counting operation The counter must be armed before application of the triggering Gate ed
202. ether a board is to drive the onboard 10 MHz oscillator onto the RTSI bus receive the RTSI bus clock or disconnect from the RTSI bus clock This clock source whether local or RTSI signal is then divided by 10 and used as the Am9513A frequency source The jumper selections are listed in Table 2 9 Table 2 9 Configurations for RTSI Bus Clock Selection Disconnect board from RTSI bus clock use local C D E F factory setting oscillator Receive RTSI bus clock signal A B E F Drive RTSI bus clock signal with local oscillator A B C D Figures 2 21 2 22 and 2 23 show the jumper positions for each of the configurations described above Figure 2 21 Disconnect from RTSI Bus Clock Use Onboard Oscillator Factory Setting Figure 2 22 Receive RTSI Bus Clock Signal National Instruments Corporation 2 19 AT MIO 16D User Manual Configuration and Installation Chapter 2 Figure 2 23 Drive RTSI Bus Clock Signal with Onboard Oscillator Hardware Installation The AT MIO 16D can be installed in any available 16 bit expansion slot AT style in your computer The AT MIO 16D does not work if installed in an eight bit expansion slot PC style After you have changed if needed verified and recorded the switches and jumper settings you are ready to install the AT MIO 16D The following are general installation instructions but consult the user manual or technical reference manual of your PC AT for specific instructions and warni
203. ever EDGE ooo LEVEL EDGE 000 LEVEL EDGE Count to TC once then aisen er Court to TC twice then isan 1 1 Count to TC repeatedly without disarming DD Lp Ee x Gate input does not gate counter input X1 L LXL L Count during acie gate level T x pu meo peor a e e d eps ad second TC _No hardware retriggering ae x Reload counter from toad register on TC TT x x TT xx Rieioad counter on each TC alternating reload source between Load and Hold registers Transfer Load register into counter on each TC that gate is LOW transfer Hold register into counter on each TC that gate is HIGH On active gate edge transfer counter into Hold register and then reload counter from Load registor eee emer m s 1 L ll Notes 1 Counter modes M P T U and W are reserved and should not be used 2 Mode X is available for Am9513A Figure 14 Counter Mode Operating Summary COUNTER MODE DESCRIPTIONS the ARM command is omitted The retriggering modes N O and are shown with one retrigger operation Both a TC Counter Mode register bits CM15 CM13 and 7 5 select output waveform and a TC Toggled output waveform are the operating mode for each counter see Figure 14 To shown for each mode The symb
204. ew mux gain memory location is selected after each A D conversion The first conversion is performed on the first channel and gain setting in the memory The second conversion is performed on the second channel and gain setting and so on The last entry written to the mux gain memory must have the LASTONE bit set This bit marks the end of the scan sequence After the last conversion is performed the scan sequence starts over If there are X entries in the mux gain memory every Xth conversion in the data collected is performed on the same channel and gain setting Multiple conversions can be performed on each entry in the mux gain memory before incrementing to the next entry in the scan sequence If the SCANDIV bit in Command Register 1 is set the mux gain memory increments to the next entry when an active low pulse is detected on the Am9513A Counter Timer OUTI signal If the SCANDIV bit is cleared the mux gain memory is incremented to the next entry after every conversion The mux gain memory must be loaded with the desired scan sequence before data acquisition begins To load the mux gain memory perform the following write operations where X is the number of entries in the scan sequence For i 0 to X 1 do the following a Write i to the Mux Counter Register to select the mux gain memory location b Write the desired analog channel selection and gain setting to the Mux Gain Register to load the mux gain memory at location i c Ifi
205. ferenced to ground somewhere either at the source device or at the AT MIO 16D If you have a floating source you must use a ground referenced input connection at the AT MIO 16D If you have a grounded source you must use a nonreferenced input connection at the AT MIO 16D Types of Signal Sources When configuring the input mode of the AT MIO 16D and making signal connections you must first determine whether the signal source is floating or ground referenced These two types of signals are described in the following sections Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers The ground reference of a floating signal must be tied to the AT MIO 16D analog input ground in order to establish a local or onboard reference for the signal Otherwise the measured input signal varies or appears to float An instrument or device that provides an isolated output falls into the floating signal source category AT MIO 16D User Manual 2 26 National Instruments Corporation Chapter 2 Configuration and Installation Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already conn
206. ferent register groups A bit description of each of the registers making up these groups is included later in this chapter AT MIO 16D User Manual 4 2 National Instruments Corporation Chapter 4 Programming The Configuration and Status Register Group controls the overall operation of the AT MIO 16D hardware The Event Strobe Group is a group of registers that when written to generate some event on the AT MIO 16D board The registers in the Analog Output Group access the AT MIO 16D DACs The Analog Input Group allows ADC output to be read The Counter Timer Group consists of the three registers of the onboard Am9513A Counter Timer chip The registers in the Digital I O Group access the onboard digital input and output lines The registers in the RTSI Switch Group control the onboard RTSI switch The DIO 24 Register Group controls all operations and modes of the DIO 24 circuitry on the AT MIO 16D board You may notice that the DIO 24 registers have the same offset as Command Register 1 and Command Register 2 Access to the DIO 24 registers are distinguished by means of performing an 8 bit bus transfer versus a 16 bit bus transfer Register Description Format The remainder of this register description chapter discusses each of the AT MIO 16D registers in the order shown in Table 4 1 Each register group is introduced followed by a detailed bit description of each register The individual register description gives the address type word size
207. figuration are discussed under the Signal Connections section later in this chapter Figure 2 29 shows a schematic diagram of this configuration Analog Input Polarity and Range The AT MIO 16D offers two analog input polarities unipolar input and bipolar input Unipolar input means that the analog input voltage range is between 0 and Vref where Vref is some positive reference voltage Bipolar input means that the analog input voltage range is between Vref and Vref The AT MIO 16D also has two input ranges 10 V input range and a 20 V input range The selection of input polarity and range are combined into three possible configurations as shown in Table 2 7 AT MIO 16D User Manual 2 12 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 7 Configurations for Input Range and Input Polarity Input Range Input Polarity Jumper Settings wi W4 0 to 10 V 10 V range Unipolar A B 5 to 5 V 10 V range Bipolar B C 10 to 10 V 20 V range Bipolar B C factory setting Figures 2 12 2 13 and 2 14 show the jumper positions for the 0 to 10 V 5 to 5 V and 10 to 10 V input polarity range configurations respectively ADC Range 20V 10V ADC Range 20V 10V ADC Range 20V 10V A B ADC Mode Figure 2 14 Factory 10 to 10 V Analog Input Configuration National Instruments Corporation 2 13 AT MIO 16D User Manual Configuration and Installation Chapter 2 Considerations for Sel
208. for an seoa outers a 1 5 5s 54 52 contents of source ino al selected curis s ss ss Sz St Lond and all selected 1 9 9 ss se Se 52 St and Save Por pe 3 ps se se 52 5 Save alt selected counters n TT ee Te se se ee s comes 3 3 e 3 We We N Se Toggle out HGH for counter O O UOO 3 3 5 9 3 m Ges out ROW for counter N orenean La prp 9 w w N SesmeNOreNew L3 333 9 9 9 Gata Poner OO OO OOOO O UOU serie Gate of FOU 99191910 Eraio Oma Pomor pepe 9 9ewmzGwewton Pee 9 51 9e SSS LOC 3 3 9 9 0 tor operations amasisa ony CSCS Fe o 1 sae Preteen for write operations amasisa Soo i i a to be used for asynchronous operations Figure 19 Am9513A Command Summary determines which reload source to use on the upcoming TC Following each ARM or LOAD AND ARM command a counter in one of these modes will reload from the Hoid register on the first TC and alternate reload sources thereafter reload from the Load register on the second TC the Hold register on the third etc
209. from the status register 3 Any input transition that occurs before this minimum setup requirement will act on the counter before the execution of the operation initiated by the write and the counter may be off by one count 4 Any input transition that occurs after this minimum hold time is guaranteed to not influence the contents read from the status register on the current read operation 5 Any input transition that occurs after this minimum hold time is guaranteed to be seen by the counter as occurring after the action initiated by the write operation and the counter may be off by one count 6 This parameter applies to cases where the write operation causes a change in the output bit 7 enabled count source is one of 1 5 TCN 1 SRC1 SRCS or GATE1 GATE 5 as selected in the applicable Counter Mode register The timing diagram assumes the counter counts on rising source edges The timing specifications are the same for falling edge counting 8 This parameter applies to edge gating CM15 CM13 110 or 111 and gating when both CM7 1 and CM15 CM13 000 This parameter represents the minimum GATE pulse width needed to ensure that the pulse initiates counting or counter reloading 9 This parameter applies to both edge and level gating AMD Am9513A Data Sheet rameter represents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and the counter
210. functional overview of the MIO 16 circuitry of the AT MIO 16D board RTSI Bus Interface Internal pau Acquisition Timing Data Bus i Internal Control Bus PC AT I O Channel PC AT I O Channel Interface I O Connector Figure 3 1 AT MIO 16D MIO 16 Circuitry Block Diagram National Instruments Corporation 3 1 AT MIO 16D User Manual Theory of Operation Chapter 3 The following are the major components making up the MIO 16 section of the AT MIO 16D board e PC AT I O channel interface circuitry e Analog input and data acquisition circuitry e Analog output circuitry Digital I O circuitry Timing I O circuitry e RTSI bus interface circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chapter PC I O Channel Interface Circuitry The AT MIO 16D board is a full size 16 bit PC AT I O channel adapter The PC AT I O channel consists of a 24 bit address bus a 16 bit data bus a direct memory access DMA arbitration bus interrupt lines and several control and support signals The components making up the AT MIO 16D PC AT I O channel interface circuitry are shown in Figure 3 2 AT MIO 16D User Manual 3 2 National Instruments Corporation Chapter 3 Theory of Operation Address Register Latches Selects PC AT I O Channel I O Channel Timing Read amp Write Control Lines
211. g 4 67 to 4 68 pretriggering with STOP TRIG signal servicing 4 55 single channel enabling 4 50 servicing 4 50 to 4 51 data acquisition timing circuitry block diagram 3 5 definition of 3 7 maximum recommended data acquisition rates 3 10 multiple channel scanned data acquisition 3 9 rates of data acquisition 3 9 sample counter 3 8 sample interval timer 3 8 National Instruments Corporation Index 9 AT MIO 16D User Manual Index single channel data acquisition 3 9 single conversions 3 8 theory of operation 3 7 to 3 10 data acquisition timing connections 2 36 to 2 38 EXTCONV signal 2 37 EXTSTROBE signal 2 36 to 2 37 SCANCLK signal 2 36 START TRIG signal 2 37 to 2 38 STOP TRIG signal 2 38 default settings for National Instrument products 2 3 differential connections floating signal sources 2 29 to 2 30 general considerations 2 27 to 2 28 ground referenced signal sources 2 28 to 2 29 differential input configuration 2 10 to 2 11 definition of 2 10 differential nonlinearity specification analog input A 2 analog output A 4 DIG GND signal 2 23 digital I O circuitry See MIO 16 digital I O circuitry DIO 24 circuitry cabling considerations 2 51 to 2 52 interrupt handling 4 90 to 4 91 interrupt enable settings 2 8 interrupt enable signals for all modes 4 91 interrupt programming examples 4 89 to 4 90 jumper settings 4 91 theory of operation 3 17 specifications input signal A 5 I O signal rat
212. g input signal pins Pins 1 and 2 are AI GND signal pins AI GND is an analog input common signal that is routed directly to the ground tie point on the AT MIO 16D These pins can be used for a general analog power ground tie point to the AT MIO 16D if necessary Pin 19 is the AI SENSE pin In single ended mode this pin is connected internally to the negative input of the AT MIO 16D instrumentation amplifier In DIFF mode this signal is connected to the reference ground at the output of the instrumentation amplifier Pins 3 through 18 are ACH lt 15 0 gt signal pins These pins are tied to the 16 analog input channels of the AT MIO 16D In single ended mode signals connected to ACH lt 15 0 gt are routed to the positive input of the AT MIO 16D instrumentation amplifier In DIFF mode signals connected to ACH 7 0 are routed to the positive input of the AT MIO 16D instrumentation amplifier and signals connected to ACH lt 15 8 gt are routed to the negative input of the AT MIO 16D instrumentation amplifier The following input ranges and maximum ratings apply to inputs ACH lt 15 0 gt Differential input range 10 V Common mode input range 7 V with respect to AT MIO 16D AGND Input range 12 V with respect to AT MIO 16D AGND Maximum input voltage rating 20 V for AT MIO 16D board powered off 35 V for AT MIO 16D board powered on Warning Exceeding the differential and common mode input ranges will result in distorted inp
213. g inputs two 12 bit DACS with voltage outputs eight lines of transistor transistor logic TTL compatible digital I O and three 16 bit counter timer channels for timing I O The DIO 24 circuitry is a 24 bit parallel digital I O interface based on an 82C55A programmable peripheral interface PPI The MIO 16 circuitry of the AT MIO 16D is a high performance multifunction analog digital and timing I O circuit for the PC The AT MIO 16D has a fast 12 bit ADC 16 single ended or eight differential channels expandable with SCXI and the AMUX 64T and programmable gains of 1 10 100 and 500 or 1 2 4 and 8 The AT MIO 16D has a 9 usec converter guaranteed transfer rates of up to 100 ksamples sec and a 512 word A D FIFO buffer to obtain the highest possible data acquisition rate The AT MIO 16D has internal or external A D timing two double buffered multiplying 12 bit DACS unipolar or bipolar voltage output and an onboard DAC reference voltage of 10 V The AT MIO 16D also has onboard timers for waveform generation eight digital I O lines that can sink up to 24 mA of current and three independent 16 bit counter timers for frequency counting event counting and pulse output applications The AT MIO 16D has timer generated interrupts a high performance RTSI bus interface with four triggers for system level timing and full PC AT I O channel DMA capability The DIO 24 circuitry of the AT MIO 16D is a 24 bit parallel digital I O interface for the P
214. g the entire data acquisition process therefore all A D conversion data is read from a single channel Multiple Channel Scanned Data Acquisition You perform multiple channel data acquisition by enabling scanning during data acquisition You control multiple channel scanning with the multiplexer counter and the mux gain memory The mux gain memory consists of 16 words of memory Each word of memory contains a multiplexer address 4 bits for input analog channel selection a gain setting 2 bits and a bit indicating if the entry is the last in the scan sequence The mux gain memory address is controlled by the multiplexer counter Whenever a mux gain memory address location is selected the multiplexer and gain control bits contained in that memory location are applied to the analog input circuitry For scanning operations the multiplexer counter steps through successive locations in the mux gain memory at a rate determined by the scan clock With the mux gain memory therefore an arbitrary sequence of channels 16 maximum with a separate gain setting for each channel can be clocked through during a scanning operation Both the multiplexer counter and the mux gain memory can be directly written to through AT MIO 16D registers For writing purposes the multiplexer counter serves as a pointer to the mux gain memory The counter can be loaded with any 4 bit value to point to any mux gain memory location With this counter scanning can start at
215. ge Gate edges applied to a disarmed counter are disregarded After application of a Gate edge an armed counter will count all source edges until TC irrespective of the Gate level On the first TC the counter will be reloaded from the Load register and stopped Subsequent counting will not occur until a new Gate edge is applied All Gate edges applied to the counter including the first used to trigger counting initiate a retrigger operation Upon application of a Gate edge the counter contents are saved in the Hold register On the first source edge after the retriggering Gate edge the Load register contents will be transferred into the counter Counting will resume on the second source edge after the retriggering qualified source edge after the retriggering Gate edge Quali Gate edge fied source edges are active going edges which occur while the Gate is active Am9513A 2 137 National Instruments Corporation E23 AT MIO 16D User Manual AMD Am9513A Data Sheet COUNT AAAA AOX A ON oya Te OutPuT TC TOGGLEO OuTPuUT GATE Figure 15q Mode Q Waveforms ease AAAA VAM Output TOGCLED Oursur Figure 15r Mode R Waveforms MODE S RELOAD SOURCE canis oma owns owe omo owe cwe outs wre ours cura curs Jomo owe cus ope oe ae ox px px xo xj ous ow ous Tow oe eN owe cvs ov
216. gister and should be checked every time the Status Register is read to check the CONVAVAIL bit If either of these error conditions occurs the data acquisition operation stops An overflow condition occurs if more than 512 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more National Instruments Corporation 4 61 AT MIO 16D User Manual Programming Chapter 4 data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if a second A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small the sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is set Scanned data acquisition requires slower data acquisition rates than single channel data acquisition because signals must settle each time channels are switched See Table 4 4 for the maximum recommended multiple channel data acquisition rates Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A D Clear Register Multiple A D Conversi
217. gital I O circuitry 3 12 to 3 13 timing connections 2 36 to 2 37 F fax technical support G 1 field wiring considerations 2 50 floating signal sources description of 2 26 differential connections 2 29 to 2 30 recommended configurations for ground referenced and floating signal sources 2 27 single ended connections for floating signal sources 2 30 to 2 31 FOUT signal 2 24 2 42 3 16 frequency measurement 2 40 functional overview See theory of operation fuse 5 V power supply 2 23 2 36 2 44 3 18 6 B 2 G GATE OUT and SOURCE timing signals 2 38 to 2 42 3 14 to 3 15 3 16 GATE signal 2 24 AT MIO 16D User Manual Index 12 National Instruments Corporation Index GATE2 signal 2 24 GATES signal 2 24 general purpose connections 2 38 to 2 42 event counting application with external switch gating 2 39 frequency measurement 2 40 GATE SOURCE and OUT signals 2 38 to 2 42 input and output ratings 2 40 to 2 41 time lapse measurement 2 39 to 2 40 timing signals 2 38 to 2 42 GND signal 2 44 ground referenced signal sources definition and requirements 2 27 differential connections 2 28 to 2 29 recommended configurations for ground referenced and floating signal sources 2 27 single ended connections for grounded signal sources 2 31 to 2 32 H hardware installation 2 20 I initialization Am9513A Counter Timer 4 42 analog output circuitry 4 43 16 board 4 41 to 4 43 input configu
218. gital Output Register are driven onto the digital lines corresponding to that port The digital output for both ports 0 and 1 are updated by writing the desired pattern to the MIO 16 Digital Output Register The input ports must be enabled for an external device to drive the MIO 16 digital I O lines Clear the DOUTOEN bit in Command Register 2 if an external device is driving digital I O lines ADIO lt 3 0 gt Clear the DOUTIEN bit in Command Register 2 if an external device is driving digital I O lines BDIO lt 3 0 gt The MIO 16 Digital Input Register can then be read to monitor the state of the digital I O lines as driven by the external device The logic state of all eight MIO 16 digital I O lines can be read from the MIO 16 Digital Input Register If the digital output ports are enabled the MIO 16 Digital Input Register serves as a read back register that is you can determine how the AT MIO 16D is driving the digital I O lines by reading the MIO 16 Digital Input Register Programming the Am9513A Counter Timer Counters 1 2 and 5 of the Am9513A Counter Timer are available for general purpose timing applications The programmable frequency output pin FOUT is also available as a timing signal source These applications and a general description of the Am9513A Counter Timer are included in the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation The Timing I O Circuitry section in Chapter 3 Theory of Operat
219. guration Internal Reference Selection Factory Setting You select the onboard 10 V reference for each analog output channel by setting the following jumpers Analog Output Channel 0 W3 B C 10V onboard reference connected to DAC 0 reference input Analog Output Channel 1 W2 B C 10V onboard reference connected to DAC 1 reference input This configuration is shown in Figure 2 16 National Instruments Corporation 2 15 AT MIO 16D User Manual Configuration and Installation Chapter 2 Channel 0 Channel 1 Figure 2 16 Factory Internal Reference Configuration Analog Output Polarity Selection Each analog output channel can be configured for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vref at the analog output A bipolar configuration has a range of Vref to Vref at the analog output Vref is the voltage reference used by the DACs in the analog output circuitry and can either be the 10 V onboard reference or an externally supplied reference between 10 V and 10 V Both channels need not be configured the same way however at the factory both channels are configured for bipolar output Bipolar Output Selection Factory Setting You select the bipolar output configuration for each analog output channel by setting the following jumpers Analog Output Channel 0 W8 A B Analog Output Channel 1 W7 A B This configuration is shown in Figure 2 17 B C A B C DAC 0 DAC 1 Channel 0 Chan
220. hapter are the AT MIO 16D register address map a detailed register description and a functional programming description e Chapter 5 Calibration Procedures discusses the calibration procedures for the AT MIO 16D analog input and analog output circuitry e Appendix A Specifications lists the specifications for the AT MIO 16D e Appendix B MIO 16 I O Connector describes the pinout and signal names for the MIO 16 50 pin I O connector of the AT MIO 16D e Appendix C DIO 24 I O Connector describes the pinout and signal names for the DIO 24 50 pin I O connector of the AT MIO 16D e Appendix D AT MIO 16D I O Connector describes the pinout and signal names for the AT MIO 16D 100 pin I O connector National Instruments Corporation v AT MIO 16D User Manual Preface e Appendix E AMD Am9513A Data Sheet contains the manufacturer data sheet for the Am9513A System Controller integrated circuit Advanced Micro Devices Inc This device is used on the AT MIO 16D e Appendix Oki MSM82C55A Data Sheet contains the manufacturer data sheet for the MSM82C55A CMOS Programmable Peripheral Interface Oki Semiconductor This device is used on the AT MIO 16D e Appendix G Customer Communication contains forms for you to complete to facilitate communication with National Instruments concerning our products The ndex alphabetically lists topics covered in this manual including the page where the topic can be found Conventions Us
221. he ADC readings flicker evenly between 2 046 and 2 047 Unipolar Input Calibration Procedure If your board is configured for unipolar input which provides an input range of 0 to 10 V then complete the following procedure in the order given This procedure assumes that ADC readings are in the range 0 to 4 095 1 Adjust the amplifier input offset To adjust the amplifier input offset follow these steps a Connect both ACHO pin 3 on the I O connector and ACHS pin 4 to AI SENSE pin 19 National Instruments Corporation 5 5 AT MIO 16D User Manual Calibration Procedures Chapter 5 b Take analog input readings from channel 0 at a gain of 1 and adjust trimpot R8 until a reading of roughly two counts is returned c Take analog input readings from channel 0 at the following gains both 1 and 500 for the AT MIO 16DL both 1 and 8 for the AT MIO 16DH d Adjust trimpot R2 until the readings at each gain setting match to within one count of each other 2 Adjust the ADC input offset Adjust the ADC input offset by applying an input voltage across ACHO and ACHS This input voltage is 1 22 mV or 0 V 2 LSB a Connect the calibration voltage 1 22 mV across ACHO pin 3 on the I O connector and ACHS pin 4 Connect the ground point on the calibration voltage source to AI SENSE pin 19 b Take analog input readings from channel 0 at a gain of 1 and adjust trimpot R8 until the ADC readings flicker evenly between zero and one
222. he instrumentation amplifier The Instrumentation Amplifier The instrumentation amplifier fulfills two purposes on the AT MIO 16D board It converts a differential input signal into a single ended signal with respect to the AT MIO 16D ground for a minimum input common mode rejection ratio of 85 dB This conversion allows the input analog signal to be extracted from any common mode voltage or noise before being sampled and converted The instrumentation amplifier also applies gain to the input signal allowing an input analog signal to be amplified before being sampled and converted and thus increasing measurement resolution and accuracy The gain of the instrumentation amplifier is selected under software control The AT MIO 16DL L stands for low level signals provides gains of 1 10 100 and 500 The AT MIO 16DH H stands for high level signals provides gains of 1 2 4 and 8 Channel Selection Circuitry Selection of the analog input channel and the gain settings is controlled by the mux gain memory The mux gain memory provides two gain control bits to the instrumentation amplifier and four multiplexer address bits to the input multiplexers and multiplexer mode selection circuitry that select the analog input channels Operation of the mux gain memory is explained in more detail in the Data Acquisition Timing Circuitry section later in this chapter The sample and hold amplifier aids the ADC in performing A D conversions At the beginning
223. he interrupt jumper on the appropriate pins to enable the interrupt line The interrupt jumper set 15 W13 The default interrupt lines are IRQ10 for the MIO 16 circuitry and 5 for the DIO 24 circuitry which are selected by placing the jumpers on the pins in rows 5 and 10 Figure 2 6 shows the default interrupt jumper settings IRQ5 and IRQIO To change to another line remove the jumper from IRQ5 or IRQ1O and place it on the new pins MIO IRQ 3 4567 DIO IRQ Figure 2 6 Factory Interrupt Jumper Settings IRQ5 DIO 24 and IRQ10 MIO 16 National Instruments Corporation 2 7 AT MIO 16D User Manual Configuration and Installation Chapter 2 If you do not want to use interrupts place the jumpers on W13 in the position shown in Figure 2 7 This setting disables the AT MIO 16D from asserting an interrupt line on the PC AT I O channel MIO IRQ 3 4 5 6 7 9 10 11 12 14 15 DIO IRQ Figure 2 7 Interrupt Jumper Setting for Disabling Interrupts DIO 24 Circuitry Interrupt Enable Settings To enable interrupt requests from the DIO 24 circuitry you must set jumper 14 to select PC2 PC4 or PC6 as the active low interrupt enable line When the interrupt enable line is logic low interrupts are enabled from the DIO 24 circuitry of the AT MIO 16D board Refer to Chapter 4 Programming for the suggested interrupt enable line setting for each digital I O mode of operation If W14 is set to N C all interrupt requests from the
224. hould not be modified when the counter is armed 7 The LOAD and HOLD registers should not be changed during TC 8 When using the different clocks for different counters be aware that there is a 75 ns skew between F1 F2 F3 F4 and F5 9 The TC output will remain inactive if programmed to be in the TC TOGGLE mode and the step command is used to increment or decrement the counter The output will go into TC if programmed to be in the active High or active Low terminal count modes The only two ways out of TC in this Case are Arming the counter and having an active source con nected to it issuing another step command Troubleshooting Symptom Solution 10 Timing parameters TEHWH and TGVWH are specified as negative The diagrams in Figure A3 show the relationship between these signals 11 In mode X the counter wili count all qualified source edges until the second not the first TC and then stop 12 A TC can occur when the counters are loaded if the counter was stopped at FFFF or 999949 in the count up mode or at count 0001 when counting down This is because an internal TC is generated which forces TC to be generated on the next count pulse 13 In modes that alternate the reload source between the load and the hold registers e g mode J if the counter is disarmed at 0001 for down counting or 999940 for BCD up counting or for binary up counting and rearmed the reload source after the first TC
225. igh order 4 bits Port A B C of port C PC7 PC4 The internai structure of 3 ports is as follows B Port 8 bits and low order 4 bits of Port A amp bit data output latch buffer and port C PC3 PCO one amp bit data input latch amp bit data input output latch buf Mode 0 1 2 fer and one amp bit data input buffer There are 3types iof modes to be set by grouping Port C One amp bit data output latch buffer and as follows one amp bit data input buffer no latch Mode 0 Basic input operation output operation for input Available for both groups A and B Mode 1 Strobe input operation output opere Single bit set resst function for port C tion When port C is defined as an output port it is pos Available for both groups A and sible to set to turn to high level or reset to turn to Mode 2 Bidirectional bus operation _ low level any one of 8 bits individually without affect Available for group A oniy ing other bits 336 National Instruments Corporation F 9 AT MIO 16D User Manual Oki M M82C55A Data Sheet ME Appendix F l O MSM82C55A 2RS GS VJS OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals e g read and write etc are as shown in the table below eme ee 771 sd rner ree fe e fmcsbmRe 91919191141 vassa Pets le memes 0070
226. igh to Write Low Recovery Time Note jjj 190 Write High to Out Valid Notes 6 14 TWLWH Write Low to Write High Write Duration Note 12 180 TGVEH2 Gate Valid to Count Source High Special Gate Notes 10 713 17 20 TEHGV2 Count Source High to Gate Valid Special Gate Notes 10 13 18 180 Notes E Enabied counter source input SRC1 5 1 Abbreviations used for the switching parameter symbols are E MU GATES 1 5 given as the letter T followed by four or five characters The 2 first and third characters represent the signal names on e Ban ha eu TE1 GATES which the measurements start and end Signal abbrevia Read RB Sons aro S Chip Select CS A Address C D W Write WR C Clock X2 Y Output OUT1 OUTS D Data In DBO 0815 a a a ajaja a a a a 8 d 2 8 2 a 8 8 12 2 150 Am9513A AT MIO 16D User Manual E 36 National Instruments Corporation Appendix E The second and fourth letters designate the reference states of the signals named in the first and third letters respectively using the following abbreviations H HIGH L LOW V VALID X Unknown or Don t care Z High impedance 2 Any input transition that occurs before this minimum setup requirement will be reflected in the contents read
227. ime with one channel at the positive end of the full scale range and the other channel at the negative end of the full scale range The lower the analog input source impedance the better the settling time performance National Instruments Corporation A 3 AT MIO 16D User Manual Specifications Analog Output Number of output channels Type of digital to analog converter Relative accuracy nonlinearity Differential nonlinearity Gain error includes pot adjustment range but excludes reference Voltage offset includes pot adjustment range Internal voltage reference Output voltage ranges jumper selectable Current drive capability Output settling time to 0 01 Output slew rate Output noise Output impedance Appendix A Two 12 bit multiplying 0 5 LSB maximum 0 25 LSB typical 1 LSB maximum monotonic over temperature 0 2 LSB typical 0 77 of full scale voltage adjustable to zero 64 mV bipolar mode 32 mV unipolar mode adjustable to zero 10 V 10 mV maximum 10 ppm C drift 0 to 10 V unipolar mode 10 V bipolar mode 2 mA 4 usec for 20 V step 30 V usec mV rms DC to 1 MHz lt 020 Explanation of Analog Output Specifications Relative accuracy in a digital to analog D A system is the same as nonlinearity because no uncertainty is added due to code width Unlike an ADC every digital code in a D A system represents a specific analog value rather than a range of values The
228. imebase clock used by the counter The following clocks are available internal to the Am9513A 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the sample interval timer can use signals connected to any of the Am9513A SOURCE input pins To program the sample interval counter use the following programming sequence writes are 16 bit operations All values given are hexadecimal a Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register b Write the mode value to the Am9513A Data Register to store the Counter 3 mode value Use one of the following mode values 8B25 Selects 1 MHz clock 8C25 Selects 100 kHz clock 8025 Selects 10 kHz clock 8E25 Selects 1 kHz clock 8F25 Selects 100 Hz clock 8525 Selects signal at SOURCES input as clock counts the rising edge of the signal 6 MHz maximum c Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register d Write 2 to the Am9513A Data Register to store the Counter 3 load value e Write FF44 to the Am9513A Command Register to load Counter 3 f Write FFF3 to the Am9513A Command Register to step Counter 3 down to one g Write the desired sample interval to the Am9513A Data Register to store the Counter 3 load value e Ifthe sample interval is between 2 and FFFF 65 535 decimal inclusive write the sample interval to the Am95134A Data Register e If the sample interval is 10000 65 536 decimal write 0 to th
229. in a GATE input pin and an output pin labeled OUT The Am9513A counters are numbered 1 through 5 and their GATE SOURCE and OUT pins are labeled GATE N SOURCE and OUT N where N is the counter number For counting operations the counters can be programmed to use any of the five internal timebases any of the five GATE and five SOURCE inputs to the Am9513A and the output of the previous counter Counter 4 uses Counter 3 output and so on A counter can be configured to count either falling or rising edges of the selected input The counter GATE input allows counter operation to be gated Once a counter is configured for an operation through software a signal at the GATE input can be used to start and stop counter operation There are five gating modes supported by the Am9513A no gating level gating active high level gating active low low to high edge gating and high to low edge gating A counter can also be active high level gated by a signal at GATE N 1 and GATE N 1 where N is the counter number The counter generates timing signals at its OUT output pin The OUT output pin can also be set to a high impedance state or a grounded output state The counters generate two types of output signals during counter operation terminal count pulse output and terminal count toggle output Terminal count is often referred to as TC A counter reaches TC when it counts up or down and rolls over In many counter applications the counter reloads fro
230. in the parts locator diagram in Figure 2 1 Jumpers W1 W4 W6 and W9 configure the analog input circuitry Jumpers W2 W3 W7 W8 W10 and W11 configure the analog output circuitry Jumper W5 selects the clock signal used by the Am9513A Counter Timer and the clock pin on the Real Time System Integration RTSI bus Jumpers W12 and W13 select the DMA channel and the interrupt level respectively Jumper W 14 selects the DIO 24 circuitry interrupt enable line AT Bus Interface The AT MIO 16D is configured at the factory to a base I O address of hex 220 to use DMA channels 6 and 7 to use interrupt level 10 for the MIO 16 circuitry and to use interrupt enable line PC4 with interrupt level 5 for the DIO 24 circuitry These settings as shown in Table 2 1 are suitable for most systems However if your system has other hardware at this base I O address DMA channel or interrupt level you will need to change these settings on the other hardware or on the AT MIO 16D as described in the following pages Table 2 1 AT Bus Interface Factory Settings Base I O Address Hex 220 The shaded portion indicates the side of the base address switch that is pressed down DMA Channel DMA 1 DMA Channel 6 W12 R6 A B A6 A B DMA 2 Channel 7 12 R7 B C A7 B C Interrupt Level Interrupt levels 5 and 10 W13 IRQ 10 MIO 16 selected IRQ 5 DIO 24 DIO Interrupt PC4 W14 Row PC4 Enable Line National Instruments Corporation 2 1 AT MIO 16D
231. ines BDIO lt 3 0 gt are connected to bits lt 7 4 gt of the Digital Input Register When a port is enabled the Digital Input Register serves as a read back register returning the digital output value of the port When a port is not enabled reading the Digital Input Register returns the state of the digital I O lines as driven by an external device Both the digital input and output registers are TTL compatible The digital output ports when enabled are capable of sinking 24 mA of current and sourcing 2 6 mA of current on each digital line When the ports are not enabled the digital I O lines act as high impedance inputs The external strobe signal EXTSTROBE shown in Figure 3 5 is a general purpose strobe signal Writing to an address location on the AT MIO 16D board generates an active low 200 nsec AT MIO 16D User Manual 3 12 National Instruments Corporation Chapter 3 Theory of Operation pulse on this output pin EXTSTROBE is not necessarily part of the digital I O circuitry but is shown here because it can be used to latch digital output from the AT MIO 16D into an external device Timing I O Circuitry The AT MIO 16D uses an Am9513A Counter Timer for data acquisition timing and for general purpose timing I O functions An onboard oscillator is used to generate the 10 MHz clock Figure 3 6 shows a block diagram of the timing I O circuitry 1 MHz Am9513 GATE2 5 SOURCE2 Channel OUT2 DATA lt
232. ing 5 operating environment A 6 output signal A 6 physical characteristics A 6 power requirements A 6 storage environment A 6 transfer rates A 6 theory of operation 3 17 DIO 24 circuitry programming 4 78 to 4 91 82C55A modes of operation 4 80 to 4 89 interrupt programming examples 4 89 to 4 90 Mode 0 basic I O 4 80 to 4 81 possible configurations 4 81 programming example 4 81 to 4 82 Mode 1 strobed input 4 82 to 4 84 pin assignments 4 84 AT MIO 16D User Manual Index 10 O National Instruments Corporation Index Port C status word bit definitions 4 83 to 4 84 programming example 4 84 Mode 1 strobed output 4 84 to 4 86 pin assignments 4 86 programming example 4 86 status word bit definitions 4 85 to 4 86 Mode 2 bidirectional bus 4 87 to 4 89 control word 4 87 pin assignments 4 87 to 4 88 status word bit definitions 4 87 to 4 88 single bit set reset feature 4 89 control word formats 4 79 interrupt handling 4 90 to 4 91 Port C set reset control words 4 80 register descriptions 4 78 to 4 80 DIO 24 I O connector pin 2 43 to 2 49 Mode 1 input timing 2 47 Mode 1 output timing 2 48 Mode 2 bidirectional timing 2 49 pin assignments 2 43 C 1 Port C pin assignments 2 44 to 2 45 power connections 2 44 signal descriptions 2 44 theory of operation 3 18 timing specifications 2 45 to 2 46 DIO 24 Register Group See also DIO 24 circuitry programming DIO 24 CNFG Register 4 40 DIO 24 PORTA Register
233. ing A D conversions once every sample interval until the sample counter reaches 0 AT MIO 16D User Manual 4 54 National Instruments Corporation Chapter 4 Programming 6 Service the data acquisition operation Once the data acquisition operation is started by application of a trigger the operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Read the Status Register 16 bit read b Ifthe CONVAVAIL bit is set bit 13 read the A D FIFO Register to obtain the result You can use interrupts or DMA to service the data acquisition operation These topics are discussed later in this chapter Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the CONVAVAIL bit If either of these error conditions occurs the data acquisition operation stops An overflow condition occurs if more than 512 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at l
234. ion explains how the Am9513A is used on AT MIO 16D board Initialization of the Am9513A as required by the AT MIO 16D and specific programming requirements for the sample interval and sample counters are given earlier in this chapter For general programming details for Counters 1 2 and 5 and the programmable frequency output refer to Appendix E Am9513A Data Sheet Write and read operations to the Am9513A registers require a minimum 1 5 usec recovery time between operations If two operations to the Am9513A occur within 1 5 usec the second operation is ignored by the AT MIO 16D Caution should be taken when writing to the Am9513A registers so that this access recovery time is not violated In programming the Master Mode Register keep the following considerations in mind The Am9513A must be used in 16 bit bus mode scalar control should be set to BCD division for correct operation of the clocks as described under the Programming Multiple A D Programming Conversions on a Single Input Channel section earlier in this chapter RTSI Bus Trigger Line Programming Considerations The RTSI switch connects signals on the AT MIO 16D to the seven RTSI bus trigger lines The RTSI switch has seven pins labeled A lt 6 0 gt connected to AT MIO 16D signals and seven pins labeled B lt 6 0 gt connected to the seven RTSI bus trigger lines Table 4 7 shows the signals connected to each pin National Instruments Corporation 4 73 AT M
235. ions Coding C6 C5 C4 C3 C2 1 CO Description This command re enables the prefetch circuitry for Write operations It is used only to terminate the Disable Prefetch Command Note This command is oniy availabie in Am9513A de vices it is an illegal command in the non A Am9513 device Master Reset Coding a 8 8 jg 8 8 jo 8 Description The Master Reset command duplicates the action of the power on reset circuitry It disarms ail counters enters 0000 in the Master Mode Load and Hold registers and enters OBCO hex in the Counter Mode registers Following either a power up or software reset the LOAD command should be applied to all the counters to clear any that be in a TC state The Data Pointer register should also be set to a legal value since reset does not initialize it A complete reset operation follows 1 Using the procedure given in the Command Initiation section of this document enter the FF hex command to perform a software reset 2 Using the Command Initiation procedure enter the LOAD command for all counters opcode 5F hex 3 Using the procedure given in the Setting the Data Pointer Register section of this document set the Data Pointer to a valid code The legal Data Pointer codes are given in Figure 8 The Master Mode Counter Mode Load and Hold registers can now be initialized to the desired values Am9513A National Instruments Corporation
236. iple A D Conversions with Interval Channel Scanning 5 8 2 0 000 01000100000000000 4 62 External Timing Considerations for Scanned Data Acquisition 4 68 Resetting the Hardware after a Data Acquisition 4 68 Resetting Co nter 2 in emet eh teen ga 4 69 Counter o 4 69 Resetting Counter 4 4 70 Conter 2 4 70 Programming Analog Output Circuitry eene 4 7 Programming the MIO 16 Digital I O 4 72 Programming the Am9513A Counter Timer eene 4 73 RTSI Bus Trigger Line Programming Considerations sess 4 73 AT MIO 16D RTSI Signal Connection Considerations 4 74 Programming the RTSI Switch eene itte dn eed et eto eo eee 4 75 Programming DMA Operations cceeccecesceceeececescceceeceeceeeecsaeeesneeeenaeeeenas 4 76 Interrupt Programming 5 aaa bones thes 4 77 DIO 24 Circuitry Programming 4 78 DIO 24 Circuitry Register Descriptions 4 78 82C55A Modes of 4 80 Node
237. iplexer 1 Multiplexer 1 controls analog input channels 8 through 15 If this bit is set multiplexer 1 is currently enabled If this bit is cleared multiplexer 1 is currently disabled In single ended mode multiplexer 1 is enabled only when one of the input channels 8 through 15 is selected In this mode the output of multiplexer 1 is connected to the positive input of the instrumentation amplifier In DIFF mode multiplexer 1 is always enabled In this mode the output of multiplexer 1 is connected to the negative input of the instrumentation amplifier National Instruments Corporation 4 7 AT MIO 16D User Manual Programming Bit Name 3 MUXOEN 2 0 lt 2 0 gt AT MIO 16D User Manual Chapter 4 Description continued This bit indicates the state of multiplexer 0 Multiplexer 0 controls analog input channels 0 through 7 If this bit is set multiplexer 0 is currently enabled If this bit is cleared multiplexer 0 is currently disabled In single ended mode multiplexer 0 is enabled only when one of the input channels 0 through 7 is selected In DIFF mode multiplexer 0 is always enabled The output of multiplexer 0 is always connected to the positive input of the instrumentation amplifier lt 2 0 gt give the low order three bits of the analog input channel address MA stands for multiplexer address These three bits in conjunction with the MUX1EN and MUXOEN bits indicate which analog input channel is c
238. ister 4 29 register map 4 2 Am9513A System Timing Controller alarm registers and comparators E 11 block diagram E 2 bus transfer switching waveforms E 38 AT MIO 16D User Manual Index 2 National Instruments Corporation Index bus width E 13 characteristics E 2 command descriptions E 29 to E 32 command summary E 30 comparator enable E 12 connection diagrams E 3 count control E 28 count source selection E 29 counter logic groups E 8 E 11 counter mode control options E 26 to E 29 counter mode descriptions E 14 to E 26 counter mode operating summary E 14 counter mode register E 11 Counter Mode Register bit assignments E 27 counter output waveforms E 28 counter switching waveforms E 38 crystal input configuration E 40 data bus assignments E 7 data pointer register E 9 data pointer sequencing E 10 E 13 data port registers E 11 design hints E 39 detailed description E 8 to E 11 FOUT divider E 12 FOUT gate E 12 FOUT source E 12 frequency scaler ratios E 13 GATE SRC configuration suggestion E 40 gating control E 13 E 29 gating modes 3 14 general description E 2 hardware retriggering E 29 hold register E 11 initialization 4 42 input circuitry E 7 interface considerations E 7 interface signal summary E 7 load data pointer commands E 10 load register E 11 master mode control options E 11 to E 13 master mode register bit assignments E 12 mode waveforms
239. ister 4 6 to 4 8 description format 4 3 DIO 24 Register Group 4 36 to 4 40 DIO 24 CNFG Register 4 40 DIO 24 PORTA Register 4 37 DIO 24 PORTB Register 4 38 DIO 24 PORTC Register 4 39 Event Strobe Register Group 4 11 to 4 15 A D Clear Register 4 14 External Strobe Register 4 15 Start Convert Register 4 12 Start DAQ Register 4 13 MIO 16 Digital I O Register Group 4 30 to 4 32 MIO 16 Digital Input Register 4 31 MIO 16 Digital Output Register 4 32 programming considerations 4 41 register map 4 1 to 4 2 register sizes 4 2 RTSI Switch Register Group 4 33 to 4 35 RTSI Switch Shift Register 4 34 RTSI Switch Strobe Register 4 35 relative accuracy specification analog input A 2 analog output A 4 resetting hardware after data acquisition Counter 2 4 69 Counter 3 4 69 Counter 4 4 70 Counter 5 4 70 round robin scanning See multiple A D conversions programming RSE input See referenced single ended RSE input RTSI bus clock selection 2 18 to 2 20 RTSI bus interface circuitry 3 15 to 3 16 block diagram 3 16 RTSI switch definition of 3 16 programming 4 73 to 4 76 procedure for 4 76 RTSI switch control pattern 4 75 signal connections 4 74 RTSI Switch Register Group 4 33 to 4 35 register map 4 2 RTSI Switch Shift Register 4 34 RTSI Switch Strobe Register 4 35 National Instruments Corporation Index 21 AT MIO 16D User Manual Index S sample and hold amplifier 3 6 sample counter programming con
240. it digital to analog converter DAC output operational amplifiers op amps reference selection jumpers and unipolar bipolar output selection jumpers The DAC in each analog output channel generates a current proportional to the input voltage reference multiplied by the digital code loaded into the DAC Each DAC can be loaded with a 12 bit digital code by writing to registers on the AT MIO 16D board The output op amps convert the DAC current output to a voltage output provided at the AT MIO 16D I O connector DACO OUT and 1 OUT pins The analog output of the DACs is updated to reflect the loaded 12 bit digital code in one of two ways immediately when the 12 bit code is written to the DACs or when an active low pulse occurs on the Am9513A OUT2 pin The update method used is selected by the LDAC bit in Command Register 2 Analog Output Range The DAC output op amps can be jumper configured to provide either a unipolar voltage output or a bipolar voltage output range A unipolar output has an output voltage range of Oto 1 LSB V A bipolar output provides an output voltage range of to V e 1 LSB V For unipolar output V output corresponds to a digital code word of zero For bipolar output the form of the digital code input is jumper selectable If straight binary form is selected V output corresponds to a digital code word of 2 048 If two s complement form is selected 0 V output corresponds to a digital code w
241. ite 2 to the Am9513A Data Register to store the Counter 3 load value e Write FF44 to the Am9513A Command Register to load Counter 3 f Write FFF3 to the Am9513A Command Register to step Counter 3 down to one g Write the desired sample interval to the Am9513A Data Register to store the Counter 3 load value e If the sample interval is between 2 and FFFF 65 535 decimal write the sample interval to the Am9513A Data Register e If the sample interval is 10000 65 536 decimal write 0 to the Am9513A Data Register h Write FF24 to the Am9513A Command Register to arm Counter 3 After you complete this programming sequence Counter 3 is configured to generate A D conversion pulses as soon as application of a trigger causes it to be enabled 3 Program the sample counter Use Counters 4 and 5 of the Am9513A Counter Timer as the sample counter The sample counter tallies the number of A D conversions initiated by Counter 3 and stops Counter 3 when the desired sample count is reached The sample count should be programmed as a multiple of the number of entries in the mux gain memory If the desired sample count is 65 536 or less only Counter 4 needs to be used making Counter 5 available for general purpose timing applications If the desired sample count is greater than 65 536 both Counters 4 and 5 must be used Sample Counts 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the following programming sequ
242. ith External Switch Gating 2 39 Figure 2 38 Frequency Measurement Application esee 2 40 Figure 2 39 General Purpose Timing 1 2 41 Figure 2 40 DIO 24 I O Connector Pin Assignments 2 43 Figure 3 1 AT MIO 16D MIO 16 Circuitry Block Diagram eene 3 1 Figure 3 2 PC AT I O Channel Interface Circuitry Block Diagram 3 3 Figure 3 3 Analog Input and Data Acquisition Circuitry Block Diagram 3 5 Figure 3 4 Analog Output Circuitry Block Diagram eee 3 10 Figure 3 5 Digital I O Circuitry Block 3 12 Figure 3 6 Timing I O Circuitry Block Diagram 3 13 AT MIO 16D User Manual xiv National Instruments Corporation Figure 3 7 Figure 3 8 Figure 3 9 Figure 4 1 Figure 4 2 Figure 5 1 Figure B 1 Figure C 1 Figure D 1 Table Table Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table 2 10 Table 2 11 Table 3 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 4 8 4 9 4 1 1 gt Contents Counter Block Diagram sedet seisis iin a iasi 3 14 Bus Interface Circuitry Block Diagram eere 3 16 AT MIO 16D DIO 24 Block Diagram
243. ither group is set to mode or mode 2 it is control word Mode combinations that define no contro bit st port C Pce Pes Pca Pes output n m m mmm m e me m output Mode 1 Mode 1 tes oe oe pm me me e mn nme Mode 1 Mode 1 INTR oe ire e Po ese pm pe ase im a wo 19 ema tre wre Ls ate S wren ve vo ve Controlied at the 3rd bit D3 Controlled at the Oth bit DO of the control word of the contro word When the I O bit is set to input in this case it is pos The bit set reset function can be used for ali of sible to access data by the normal port C read PC3 PCO bits Note that the status of port C operation varies according to the combination of modes like When set to output PC7 PC4 bits can be ac this cessed by the bit set reset function only Meanwhile 3 bits from PC2 to PCO can be accessed by normal write operation 343 AT MIO 16D User Manual F 16 National Instruments Corporation Appendix F Oki MSM82C55A Data Sheet a 1 0 MSM82C55A 2RS GS VJS 5 Port C Status Read bus status signal can be read out by sa the When port C is used for the contro signal that is content of port in either mode 1 or mode 2 each
244. itici tases ieee 2 34 PO Wer C OMMEC HONS 2 36 Timing Connections REPE 2 36 Data Acquisition Timing 2 36 General Purpose Timing Signal Connections usse 2 38 DIO 24 I O Connector Pin Description eene 2 43 DIO 24 Signal Connection Descriptions esee 2 44 Power C ODMECU OMS 2 44 Port Pin Assignments inea Lus 2 44 Timing Sp cifications sss seb cederet es Shes avr acer 2 45 DIO 24 Mode 1 Input Timing eene 2 47 DIO 24 Mode 1 Output oce coner 2 48 DIO 24 Mode 2 Bidirectional Timing eee 2 49 Cabling and Field WIDE em coset at nes 2 50 Field Wiring Considerations iie tette to sepe 2 50 MIO 16 Cabling CODSIderdtlGlis soiree t as 2 50 DIO 24 Cabling 2 5 Chapter 3 Theory of ODerallOT io oleis tei qure refte da es 3 1 MIO T6 Functional Overview nic nha eR 3 1 PC AT TO Channel Interface Circuitry dogs 3 2 Analog Input and Data Acquisition Circuitry eese 3 4 Analog Input
245. l write 0 to the Am9513A Data Register h Write FF22 to the Am9513A Command Register to arm Counter 2 After you complete this programming sequence Counter 2 is configured to assign a time interval to scan sequences once the trigger to enable A D conversions is detected AT MIO 16D User Manual 4 66 National Instruments Corporation Chapter 4 Programming 5 Clear the A D circuitry and reset the multiplexer counter Before starting the data acquisition operation the A D FIFO must be emptied to clear out any old A D conversion results This emptying must be done after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 16 bit write Write 0 to the Mux Counter Register to set the analog input circuitry to the first channel and gain setting of the scan sequence Write 0 to the INT2CLR Register to clear any spurious edge caused by programming Counter 2 6 Enable the scanning data acquisition operation To enable the scanning data acquisition operation such that A D conversions begin when a trigger is received set the DAQEN bit and the SCANEN bit in Command Register 1 To enable the scan interval timing set the SCN2 bit in Command Register 2 7 Apply a trigger Once set up by the preceding steps the data acquisition operation is initiated when a trigger is received A trigger can be provided in one of two ways through software or
246. l from the CPU At this time port A is still in the high im pedance status and the data is not yet output to the outside This signal turns to low ievel at the rising edge of the WR and high level at the falling edge of the ACK Acknowledge input When a low level signal is input to this pin the high impedance status of port A is cleared the buffer is enabled and the data written to the in temal output latch is output to port A When the input returns to high level port is made into the high impedance status AT MIO 16D User Manual Group A Mode 1 input Group Mode 1 output STB Strobe input When this signal tums to low level the data out put to the port from the pin is fetched into the internal input latch The data is output to the data bus upon receipt of the RD signal from the CPU but it remains high impedance sta tus until then IBF Input buffer full fiag output This signal when turned to high level indicates that data from the pin has been fetched into the input latch This signal turns to high level at the falling edge of the STB and low level at the ris ing edge of the RD INTR interrupt request output This signal is used to interrupt the CPU and its F 14 operation in the same as in mode 1 There are two INTE flip flops internally availabie for input and output to select either interrupt of input or output operation The INTE1 is used to control the interrupt re
247. led under hardware control A Square wave rate generator may be obtained by specifying the TC Toggled output mode COUNT ney OPNS CSS Figure 15d Mode D Waveforms m PNIANININININININININININININA CD CD CD C CD CO ED OT V DEENS GRR Figure 15e Mode E Waveforms Am9513A National Instruments Corporation 17 2 131 AT MIO 16D User Manual 9513 Data Sheet MODE F Nor Retriggerable One Shot 15 12 cuti cmo LEGE x x xj xj x ear cus cus cma cus oma cuo pax dens Mode shown in Figure 151 provides a non retriggerabie one shot timing function The counter must be armed before it will function Application of a Gate edge to the armed counter will enable counting When the counter reaches TC it will reload itself from the Load register The counter will then stop counting awaiting a new Gate edge Note that unlike Mode C anew ARM command is not needed after TC only a new Gate edge After application of a triggering Gate edge the Gate input is disregarded until TC MODE G Software Triggered Delayed Puise One Shot ees es cara cara cars ovo eve cue cus cue cus cuz e esposo d in Mode G the Gate does not affect the counter s operati
248. ls on the PC AT I O channel The AT MIO 16D does not use and cannot be configured to use the 8 bit DMA channels on the PC AT I O channel gt lt gt lt 0 0 0 0 0 0 0 0 0 1 1 FR rR SB OS OS a OO SO Oe Oe oe 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Each DMA channel consists of two signal lines as shown in Table 2 4 National Instruments Corporation 2 5 AT MIO 16D User Manual Configuration and Installation Chapter 2 Table 2 4 DMA Channels for the AT MIO 16D DMA DMA DMA Channel Acknowledge Request 5 6 7 DACKS A5 5 R5 DACK6 A6 DRQ6 R6 DACK7 7 DRQ7 R7 Two jumpers must be installed to select a DMA channel The DMA Acknowledge and DMA Request lines selected must have the same number suffix for proper operation When you use dual DMA mode the left two rows of W12 are used for DMA 1 and the right two rows of W12 are used for DMA 2 Figure 2 3 displays the jumper positions for selecting DMA channels 6 and 7 In this setting DMA 1 uses DMA channel 6 and DMA 2 uses DMA channel 7 Figure 2 3 DMA Jumper Settings for DMA Channels 6 and 7 Factory Setting If you want to use only one DMA channel then place the configuration jumpers on W12 in the position shown in Figure 2 4 Figure 2 4 DMA Jumper Settings for DMA Channel 6 On
249. lues to output voltage National Instruments Corporation 4 17 AT MIO 16D User Manual Programming Chapter 4 DACI1 Register Writing to DACI loads the corresponding analog output channel DAC The voltages generated by the analog output channels are updated either immediately or when an active low pulse occurs on OUT2 The update method is selected by the LDAC bit in Command Register 2 Address Base address 12 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xX x x x D6 D7 D5 D4 D3 D2 DI DO MSB LSB Bit Name Description 15 2 X Don t care bits 11 0 D lt 11 0 gt These twelve bits are loaded into the DAC and update the voltage generated by the analog output channel in one of two ways immediately or upon an OUT2 pulse See the Programming the Analog Output Circuitry section later in this chapter for Tables 4 5 and 4 6 both of which map digital values to output voltage AT MIO 16D User Manual 4 18 National Instruments Corporation Chapter 4 Programming INT2CLR Register Writing to INT2CLR clears the interrupt request asserted when an OUT2 pulse is detected Address Base address 14 hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used National Instruments Corporation 4 19 AT MIO 16D User Manual Programming Chapter 4 Analog Input Register Group The four registers making up the Analog Input
250. ly AT MIO 16D User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation If you do not want to use DMA for AT MIO 16D transfers then place the configuration jumpers on W12 in the position shown in Figure 2 5 Figure 2 5 DMA Jumper Settings for Disabling DMA Transfers Interrupt Selection The AT MIO 16D board can connect to any of the 11 interrupt lines of the PC AT I O channel The interrupt lines for the MIO 16 and DIO 24 circuitry are selected by jumpers on one of the rows of pins located above the I O slot edge connector on the AT MIO 16D refer to Figure 2 1 To use the interrupt capability of the AT MIO 16D you must select an interrupt line and place the jumper in the appropriate position to enable that particular interrupt line The AT MIO 16D can share interrupt lines with other devices by using a tristate driver to drive its selected interrupt line The interrupt lines supported by the AT MIO 16D hardware for the MIO 16 circuitry are IRQ3 IRQ4 5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 and IRQIS The interrupt lines supported by the AT MIO 16D hardware for the DIO 24 circuitry are IRQ3 IRQ4 5 IRQ6 IRQ7 9 Note Do not use interrupt line 6 or interrupt line 14 Interrupt line 6 is used by the diskette drive controller and interrupt line 14 is used by the hard disk controller on most IBM PC ATs and compatibles Once you have selected an interrupt level place t
251. m an internal register when it reaches TC In TC pulse output mode the counter generates a pulse during the cycle that it reaches TC and reloads In TC toggle output mode the counter output changes state after it reaches TC and reloads In addition the counters can be configured for positive logic output or negative inverted logic output for a total of four possible output signals generated for one timing mode The SOURCE GATE and OUT pins for Counters 1 2 and 5 of the onboard Am9513A are located on the AT MIO 16D I O connector A rising edge signal on the STOP TRIG pin of the I O connector sets the flip flop output signal connected to the GATE4 input of the Am9513A and can be used as an additional gate input The flip flop output connected to GATE4 is cleared when the sample counter reaches TC when an overflow or overrun occurs or when the A D Clear Register is written to The Am9513A SOURCES pin is connected to the AT MIO 16D RTSI switch which means that a signal from the RTSI trigger bus can be used as a counting source for the Am95134A counters AT MIO 16D User Manual 3 14 O National Instruments Corporation Chapter 3 Theory of Operation The Am9513A OUT2 pin can be used in several different ways If the LDAC bit is set in Command Register 2 an active low pulse on OUT2 updates the analog output on the two DACs OUT can also be used to trigger interrupt requests If INT2EN bit is set an interrupt occurs when a rising edge signal is
252. med for counting to occur Once armed the counter will count ail source edges that occur while the Gate is active This permits the Gate to tum the count process on and off As with Mode G the counter will be reloaded from the Hold register on the first TC and reloaded from the Load register and disarmed on the second TC This mode allows the Gate to control the extension of both the initial output delay time and the puise width AMD Am9513A Data Sheet MODE 1 Hardware Triggered Delayed Puise Strobe ons 1 cmo cmo LEE ome T 1 x Mode shown in Figure 15i is identical to Mode except that counting will not begin until a Gate edge is applied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded An armed counter will start counting on the first source edge after the triggering Gate edge Counting will then proceed in the same manner as in Mode G After the second TC the counter will disarm itself An ARM command and Gate edge must be issued in this order to restart counting Note that after application of a triggering Gate edge the Gate input will be disregarded until the second TC This differs from Mode H where the Gate can be modulated throughout the count cycle to stop and
253. ments is not liable for any damages resulting from any such signal connections Figure 2 40 DIO 24 I O Connector Pin Assignments National Instruments Corporation 2 43 AT MIO 16D User Manual Configuration and Installation Chapter 2 DIO 24 Signal Connection Descriptions Pin Signal Name Reference Description 1 3 PC7 through DIGGND Bidirectional data lines for Port C 7 9 11 7 is the MSB PCO the LSB 13 15 17 19 21 PB7 through DIGGND Bidirectional data lines for Port B 23 25 27 PB7 is the MSB PBO the LSB 29 31 33 35 37 PA7 through PAO DIGGND Bidirectional data lines for Port A 39 41 43 PA7 is the MSB PAO the LSB 45 47 49 5 DIGGND This pin provides 5 VDC All even DIGGND These signals are connected to the PC ground numbered signal pins The absolute maximum voltage input rating is 0 5 to 7 0 V with respect to GND Power Connections Pin 49 of the DIO 24 I O connector provides 5 V from the PC AT power supply This pin is referenced to DIG GND and can be used to power external digital circuitry Power rating 1 Aat 5 10 Warning This 5 V power pin should not be directly connected to analog or digital ground or to any other voltage source on the AT MIO 16D or any other device Doing so can damage the AT MIO 16D and the PC AT National Instruments is not liable for damages resulting from such a connection A spare DIO 24 fuse is provided in case the power rating is inad
254. ments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT
255. n Chapter 2 Configuration and Installation for START TRIG signal specifications Once the trigger is applied Counter 3 generates pulses initiating A D conversions once every sample interval until the sample counter reaches zero 7 Service the data acquisition operation Once the data acquisition operation is started by application of a trigger the operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Read the Status Register 16 bit read b If the CONVAVAIL bit is set bit 13 read the A D FIFO Register to obtain the result You can also use interrupts or DMA to service the data acquisition operation These topics are discussed later in this chapter Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the CONVAVAIL bit If either of these error conditions occurs the data acquisition operation stops An overflow condition occurs if more than 512 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to k
256. n Index 1 AT MIO 16D User Manual Index Port C status word bit definitions 4 83 to 4 84 programming example 4 84 Mode 1 strobed output 4 84 to 4 86 pin assignments 4 86 programming example 4 86 status word bit definitions 4 85 to 4 86 Mode 2 bidirectional bus 4 87 to 4 89 control word 4 87 pin assignments 4 87 to 4 88 status word bit definitions 4 87 to 4 88 single bit set reset feature 3 19 4 89 theory of operation 3 18 A ACHO through ACHI5 signals 2 23 A D circuitry clearing analog input circuitry 4 45 to 4 46 multiple A D conversions continuous channel scanning round robin 4 61 controlling with EXTCONV signal 4 56 interval channel scanning pseudo simultaneous 4 67 pretriggering with STOP TRIG signal 4 54 on single channel 4 49 to 4 50 A D Clear Register 4 14 A D conversion See analog input circuitry multiple A D conversions programming A D converter 3 7 A D FIFO output binary formats 4 44 to 4 45 straight binary mode A D conversion values 4 45 two s complement mode A D conversion values 4 45 A D FIFO Register description of 4 24 output binary formats 4 44 to 4 45 reading conversion results 4 44 ADC FIFO buffer 3 7 ADIO lt 0 3 gt signal 2 23 AI GND signal 2 23 AI SENSE signal 2 23 Am9513 Counter Timer Register Group 4 26 to 4 29 See also sample counter programming sample interval counter programming Am9513A Command Register 4 28 Am9513A Data Register 4 27 Am9513A Status Reg
257. n a single analog input channel the time required for the input sample and hold amplifier to acquire the input signal and settle to 12 bit accuracy 0 01 is added to the conversion time of the ADC The sample and hold amplifier in the AT MIO 16D takes 1 usec typical and 1 5 usec maximum to settle to 0 01 for a 10 V step The data acquisition rates shown in the preceding table are the best rates for single channel acquisition These rates take into account the specified typical and maximum worst case conversion times of the ADC plus 2 usec to allow for sample and hold settling time Multiple Channel Scanning Acquisition Rates The following are the maximum multiple channel scan rates recommended for the AT MIO 16D Data Acquisition Rate 100 ksamples sec 100 ksamples sec 70 ksamples sec 20 ksamples sec Recommended multiple channel scanning rates are slower than single channel acquisition rates for higher gains because as gain is increased the AT MIO 16D circuitry takes longer to settle from one channel voltage to the next The recommended settling time for gains of 1 through 10 is 10 usec for a gain of 100 14 usec is recommended and 50 usec is recommended for a gain of 500 For these settling times the circuitry on the AT MIO 16D boards will settle to 0 5 LSBs of the final value or to 0 01 for a full scale step A full scale difference between input channels is the worst case switching condition for channel scanning settling t
258. n an ADC is an often ill defined specification that is supposed to indicate overall A D transfer linearity of a converter The manufacturers of the ADC chips used by National Instruments specify their integral nonlinearity by stating that the analog center of any code will not deviate from a straight line by more than 2 LSB This specification is misleading because although the center of a particularly wide code can be found within 2 LSB of the ideal one of its edges may be well beyond 1 LSB thus the ADC would have a relative accuracy of that amount National Instruments tests its boards to ensure that they meet all three linearity specifications defined in this appendix specifications for integral nonlinearity are included primarily to maintain compatibility with a convention of specifications used by other board manufacturers Relative accuracy however is much more useful Differential nonlinearity is a measure of deviation of code widths from their theoretical value of 1 LSB The width of a given code is the size of the range of analog values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code width exceeds 2 LSBs AT MIO 16D User Manual A 2 National Instruments Corporation Appendix Specifications System noise is the amount of noise seen by the ADC when there is no signal present at the in
259. n duration If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement provides an uncertainty of one source clock period with respect to unsynchronized gating sources Signals generated at the OUT output are referenced to the signal at the SOURCE input or to one of the Am9513A internally generated clock signals Figure 2 39 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 300 nsec after the source signal rising or falling edge AT MIO 16D User Manual 2 42 National Instruments Corporation Chapter 2 Configuration and Installation DIO 24 I O Connector Pin Description The I O connector contains 100 pins that can be split into two standard 50 pin connectors via a cable assembly such as a Type NBS ribbon cable see Figure 1 2 One 50 pin connector contains signals associated with the MIO 16 circuitry while the other 50 pin connector contains signals for the DIO 24 circuitry Figure 2 40 shows the pin assignments for the DIO 24 circuitry I O connector Warning Connections that exceed any of the maximum ratings of input or output signals on the AT MIO 16D may result in damage to the AT MIO 16D board and to the PC Maximum ratings for each signal are given in this chapter under the discussion of that signal National Instru
260. n these modes the reload source for the next TC will be from the opposite reload location In other words the LOAD generated TC will cause the reload sources to aiternate just as a TC generated by a source edge would Note that if a second LOAD command is issued during the LOAD generated TC or during any other TC for that matter the second LOAD command wiil terminate the TC and cause a reload from the source designated for use with the next TC The second LOAD will not aiter the reload source for the next TC since the second LOAD does not generate a TC reload Sources alternate on TCs only not on LOAD commands Load and Arm Counters Coding C7 C6 C5 C4 C3 C2 Ci CO 0 1 1 55 Ss S3 52 51 Description Any combination of counters as specified in the S field will be first loaded and then armed This command is equivalent to issuing a LOAD command and then an ARM command A LOAD AND ARM command which drives a counter to TC generates the same sequence of operations as execution of a LOAD command and then an ARM command modes which disarm on TC Modes A C and N and Modes G l and S if the current TC is the second in the cycle the ARM part of the LOAD AND ARM command will re enable counting for another cycle In modes which alternate reload sources Modes G L the ARMing operation will cause the next TC to reload from the HOLD register irrespective of which reload source the current TC used This command should not
261. nded RSE A C B D E F W9 A B C E G H W9 A B C D 9 AT MIO 16D clock signal 10 MHz factory setting AT MIO 16D clock signal RTSI clock signal AT MIO 16D amp RTSI clock signals both 10 MHz Internal factory setting External Internal factory setting External Unipolar Straight binary mode Bipolar Two s complement mode factory setting Unipolar Straight binary mode Bipolar Two s complement mode factory setting AT MIO 16D User Manual Configuration and Installation Chapter 2 Analog Input Configuration You can select different analog input configurations by using the jumper settings shown in Table 2 5 The following paragraphs describe in detail each of the analog input categories In the configuration illustrations throughout this chapter the black bars show where to place jumpers Input Mode The AT MIO 16D offers three different analog input modes nonreferenced single ended NRSE input referenced single ended RSE input and differential DIFF input The single ended input configurations use 16 channels The DIFF input configuration uses eight channels These configurations are described in Table 2 6 Table 2 6 Input Configurations Available for the AT MIO 16D DIFF Differential configuration Provides eight differential inputs with the negative input of the instrumentation amplifier tied to the multiplexer output of channels 8 through 15 RSE Referenced Single
262. nel 1 Figure 2 17 Factory Bipolar Output Configuration AT MIO 16D User Manual 2 16 National Instruments Corporation Chapter 2 Configuration and Installation When you use the bipolar configuration you need to select whether to write straight binary or two s complement to the DAC In straight binary mode data values written to the analog output channel range from 0 to 4 095 decimal 0 to OFFF hex In two s complement mode data values written to the the analog output channel range from 2 048 to 2 047 decimal F800 to 07FF hex Straight Binary Mode The data value written to each analog output channel is interpreted as a straight binary number when the following jumpers are set Analog Output Straight Binary for Channel 0 W10 B C Analog Output Straight Binary for Channel 1 Wil B C This configuration is shown in Figure 2 18 wio wil pac ABC ABC Channel 0 Channel 1 Figure 2 18 Straight Binary Mode Two s Complement Mode Factory Setting The data value written to each analog output channel is interpreted as a two s complement number when the following jumpers are set Analog Output Two s Complement for Channel 0 W10 Analog Output Two s Complement for Channel 1 Wil This configuration is shown in Figure 2 19 wio wi paci ABC ABC Channel 0 Channel 1 Figure 2 19 Two s Complement Mode Factory Setting National Instruments Corpo
263. nel 1 Line 7 2B8 hex GPIB PCIIA Channel 1 Line 7 02 1 hex GPIB PCIII Channel 1 Line 7 280 hex Lab PC Channel 3 Line 5 260 hex PC DIO 24 None Line 5 210 hex PC DIO 96 None Line 5 180 hex PC LPM 16 None Line 5 260 hex PC TIO 10 None Line 5 1A0 hex These settings are software configurable and are set to default at startup time Each switch in U61 corresponds to one of the address lines A9 through A5 Press the side marked OFF to select a binary value of 1 for the corresponding address bit Press the other side of the switch to select a binary value of 0 for the corresponding address bit Figure 2 2 shows two possible switch settings The shaded portion indicates the side of the switch that is pressed down National Instruments Corporation 2 3 AT MIO 16D User Manual Configuration and Installation Chapter 2 This side down for This side down for 1 A Switches Set to Base I O Address of Hex 00 This side down for This side down for 1 B Switches Set to Base I O Address of Hex 220 Factory Settin Figure 2 2 Example Base I O Address Switch Settings The five least significant bits LSBs of the address A4 through 0 are decoded by the AT MIO 16D to select the appropriate AT MIO 16D register To change the base I O address remove the plastic cover on U61 press each switch to the desired position check each switch to make sure the switch is pressed down all the way and replace the plastic cover Make a note of
264. ngs 1 Turn off your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the AT MIO 16D into a 16 bit slot It may be a tight fit but do not force the board into place 5 Screw the mounting bracket of the AT MIO 16D to the back panel rail of the computer 6 Check the installation 7 Replace the cover The AT MIO 16D board is installed and ready for operation Signal Connections This section describes input and output signal connections to the AT MIO 16D board via the AT MIO 16D I O connector This section includes specifications and connection instructions for the signals given on the AT MIO 16D I O connector The I O connector contains 100 pins that can be split into two standard 50 pin connectors via a cable assembly such as a Type NBS ribbon cable see Figure 1 2 One 50 pin connector contains signals associated with the MIO 16 circuitry while the other 50 pin connector contains signals for the DIO 24 circuitry AT MIO 16D User Manual 2 20 National Instruments Corporation Chapter 2 Warning Configuration and Installation Connections that exceed any of the maximum ratings of input or output signals on the AT MIO 16D can result in damage to the AT MIO 16D board and to the PC AT Maximum input ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any
265. ning round robin 4 57 to 4 62 applying a trigger 4 61 clearing A D circuitry 4 61 enabling scanning data acquisition operation 4 61 overflow and overrun conditions 4 61 to 4 62 resetting multiplexer counter 4 61 sample counter programming 4 59 to 4 60 sample interval counter programming 4 58 to 4 59 servicing data acquisition operation 4 61 to 4 62 setting up analog channel and gain selection sequence 4 58 external timing considerations 4 51 to 4 57 controlling with EXTCONV signal 4 55 to 4 57 clearing A D circuitry 4 56 overflow and overrun conditions 4 56 to 4 57 selecting analog input channel and gain 4 56 servicing data acquisition operation 4 56 to 4 57 overflow and overrun conditions 4 55 pretriggering with STOP TRIG signal 4 51 to 4 55 applying a trigger 4 54 clearing A D circuitry 4 54 sample counter programming 4 52 to 4 54 sample interval counter programming 4 52 selecting analog input channel and gain 4 51 servicing data acquisition operation 4 55 National Instruments Corporation Index 19 AT MIO 16D User Manual Index scanned data acquisition 4 68 interval channel scanning pseudo simultaneous 4 62 to 4 68 applying a trigger 4 67 clearing A D circuitry 4 67 enabling scanning data acquisition operation 4 67 multiple channel data acquisition rates 4 68 overflow and overrun conditions 4 68 resetting multiplexer counter 4 67 sample counter programming 4 64 to 4 65 sample interval count
266. nsec low pulse on this pin B 2 National Instruments Corporation Appendix Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name START TRIG STOP TRIG EXTCONV SOURCEI OUTI SOURCE2 GATE2 OUT2 SOURCES GATES OUTS FOUT Reference DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND National Instruments Corporation MIO 16 I O Connector Description continued External Trigger In posttrigger data acquisition sequences a high to low edge on START TRIG initiates the sequence In pretrigger applications the high to low edge of START TRIG initiates pretrigger conversions while the STOP TRIG signal initiates the posttrigger sequence Stop Trigger In pretrigger data acquisition the high to low edge of STOP TRIG initiates the posttrigger sequence External Convert A high to low edge on EXTCONV causes an A D conversion to occur If EXTGATE or EXTCONV is low conversions are inhibited SOURCE This pin is from the Am9513A Counter 1 signal GATE This pin is from the Am9513A Counter 1 signal OUTPUT This pin is from the Am9513A Counter 1 signal SOURCE2 SOURCES This pin is from the Am9513A Counter 2 signal GATE2 This pin is from the Am9513A Counter 2 signal OUTPUT This pin is from the Am9513A Counter 2 signal SOUR
267. nt and write that value to the Am9513A Data Register to store the Counter 5 load value l Write FF70 to the Am9513A Command Register to load and arm Counter 5 m Setthe 16 32 CNT bit in Command Register 1 to notify the hardware that both Counters 4 and 5 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and Counter 5 increments every time Counter 4 reaches zero The data acquisition operation terminates when both Counters 4 and 5 reach zero and the last entry in the mux gain memory is served AT MIO 16D User Manual 4 60 National Instruments Corporation Chapter 4 Programming 4 Clear the A D circuitry and reset the multiplexer counter Before starting the data acquisition operation the A D FIFO must be emptied to clear out any old A D conversion results You must do this emptying after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO Write 0 to the Mux Counter Register to set the analog input circuitry to the first channel and gain setting of the scan sequence 5 Enable the scanning data acquisition operation To enable the scanning data acquisition operation such that A D conversions begin when a trigger is received set the DAQEN bit and the SCANEN bit in Command Register 1 6 Apply a trigger Once set up by th
268. nterface signals and their abbreviations for the a som STC Figure 2 Data Bus Assignments Interface Considerations All of the input and output signais for the Am9513A are specified with logic levels compatible with those of standard TTL circuits addition to providing TTL compatible voltage levels other output conditions are specified to help configure non standard interface circuitry The logic level specifications take into account all worst case combinations of the three variables that affect the logic level thresholds ambient tem perature supply voltage and processing parameters A change in any of these toward nominal values will improve the actual operating margins and will increase noise immunity Unprotected open gate inputs of high quality MOS transistors exhibit very high resistances on the order of perhaps 1015 ohms it is easy therefore in some circumstances for charge to enter the gate node of such an input faster than it can be discharged and consequently for the gate voltage to rise high enough to break down the oxides and destroy the transistor Am9513A National Instruments Corporation AMD Am9513A Data Sheet All inputs to the Am9513A include protection networks to help prevent damaging accumulations of static charge The protec tion circuitry is designed to slow the transitions of incoming Current surges and to provide iow impedance discharge paths for voltages beyond the normai op
269. of an A D conversion the sample and hold amplifier is put in hold mode which means that it holds its output voltage at a steady value the value when the hold period started regardless of voltage changes at its input This sample and hold amplifier provides the ADC with a steady voltage while AT MIO 16D User Manual 3 6 O National Instruments Corporation Chapter 3 Theory of Operation it is performing an A D conversion Without the sample and hold amplifier the analog input signal could change during a conversion thereby causing errors during A D conversion By isolating the ADC from the analog input signals during conversion you can change the input multiplexer and allow the instrumentation amplifier to settle to a new value while the ADC is converting the old value This isolation creates a two stage pipeline and increases and optimizes the performance of the analog input circuitry during high speed multiple A D conversions A D Converter The ADC is a 12 bit successive approximation ADC with a maximum conversion time of 9 usec The 12 bit resolution allows the converter to resolve its input range into 4 096 different steps This resolution also provides a 12 bit digital word that represents the value of the input voltage level with respect to the converter input range The ADC supports three input ranges that are jumper selectable on the AT MIO 16D board 10 to 10 V 5 to 5 V or 0 to 10 V ADC FIFO Buffer When an A D conversion i
270. of the eight bits of Port C can be set or reset with one control word This feature generates status and control for Port A and Port when operating in Mode 1 or Mode 2 National Instruments Corporation 3 19 AT MIO 16D User Manual Chapter 4 Programming This chapter discusses the programming of the AT MIO 16D Included in this chapter are the AT MIO 16D register address map a detailed register description and a functional programming description Note If you plan to use a programming software package such as NI DAQ for DOS Windows or LabWindows with your AT MIO 16D board you need not read this chapter However you will gain added insight into your AT MIO 16D board by reading this chapter Register Map The register map for the AT MIO 16D is shown in Table 4 1 This table gives the register name the register offset address the size of the register in bits and the type of the register read only write only or read and write The actual register address is computed by adding the individual offset address to the board base address Table 4 1 AT MIO 16D Register Map Register Name OffSet Address Hex Configuration and Status Register Group Command Register 1 Write only Status Register Read only Command Register 2 Write only Event Strobe Register Group Start Convert Register Write only Start DAQ Register Write only A D Clear Register Write only External Strobe Register Write only Analog Output Register Group DACO
271. ogic Groups 1 and 2 2 122 AT MIO 16D User Manual provides direct access to the Status and Command registers as well as allowing the user to update the Data Pointer register The Data port is used to communicate with all other addressable internal locations The Data Pointer register controls the Data port addressing Among the registers accessible through the Data port are the Master Mode register and five Counter Mode registers one for each counter The Master Mode register controls the program mable options that are not controlled by the Counter Mode registers Each of the five general purpose counters is 16 bits long and is independently controlled by its Counter Mode register Through this register a user can software select one of 16 sources as the counter input a variety of gating and repetition modes up or down counting in binary or BCD and active high or active fow input and output polarities Associated with each counter are a Load register and a Hoid register both accessibie through the Data port The Load register is used to automatically reload the counter to any predefined value thus controlling the effective count period The Hold register is used to save count values without disturbing the count process permitting the host processor to read intermediate counts in addition the Hoid register may be used as a second Load register to generate a number of complex output waveforms five counters have the same
272. ols L and H are used to simplify references to a particular mode each mode is represent count values equal to the Load and Hold register assigned a letter from A through X Representative waveforms contents respectively The symbols K and N represent for the counter modes are illustrated in Figures 15a through arbitrary count values For each mode the required bit pattem 15v Because the letter suffix in the figure number is koyed to in the Counter Mode register is shown don t care bits are the mode Figures 15m 15p 15t 15u and 15w do not exist marked X These figures are designed to clarify the mode The figures assume down counting on rising source edges descriptions the Am9513A Electrical Specification shouid be Those modes which automatically disarm the counter used as the authoritative reference for timing relationships CMS 0 are shown with the WR plus entering the required between signals ARM command for modes which count repetitively CMS 1 2 128 Am9513A AT MIO 16D User Manual E 14 National Instruments Corporation Appendix E To keep the following mode descriptions concise and to the point the phrase source edges is used to refer to active going source edges only not to inactive going edges Simi larly the phrase gate edges refers only to active going gate edges Also again to avoid verbosity and euphuism the descriptions of some modes state that a counter is stopped or disarmed
273. on Once armed the counter will count to TC twice and then automatically disarm itself For most applications the counter will initially be loaded from the Load register either by a LOAD command or by the last TC of an earlier timing cycle Upon counting to the first TC the counter will reload itself from the Hold register Counting will proceed until the second TC when the counter will reload itself from the Load register and automaticaily disarm itself inhibiting further counting Counting can be resumed by issuing a new ARM command A software triggered delayed pulse one shot may be generated by speci fying the TC Toggled output mode in the Counter Mode register The initial counter contents control the delay from the ARM command until the output pulse starts The Hold register contents contro the pulse duration Mode G is shown in Fig ure 15g ru NIS IU IU PN ec NN OON Figure 15f Mode Waveforms 2 132 Am9513A Appendix E AT MIO 16D User Manual E 18 National Instruments Corporation Appendix E MODE Software Triggered Delayed Pulse One Shot with Hardware Gating 15 cuna wis 2 curs cuo omo cve L uve x x CM cms 2 Mode shown Figure 15h is identical to Mode G except that the Gate input is used to qualify which source edges are to be counted The counter must be ar
274. on a disarmed counter Load Data Pointer Register Coding N2 C5 C4 C3 C2 Ci CO 0 0 0 E2 G4 G2 GI G4 G2 Gt 000 110 Description Bits the and fields will be transferred into the corresponding Element and Group fields of the Data Pointer register as shown in Figure 7 The Byte Pointer bit in the Data Pointer register is set Transfers into the Data Pointer onty occur for G field values of 001 010 011 100 101 and 111 Values of 000 and 110 for G should not be used See the Setting the Data Pointer Register section of this document for additional details Disable Data Pointer Sequencing Coding C6 C5 C2 C1 CO 1 1 1 0 1 00 0 Description This command sets Master Mode bit 14 without affecting other bits in the Master Mode register MM14 controis the automatic sequencing of the Data Pointer regis ter Disabling the sequencing allows repetitive host processor access to a given intemal location without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode register Am9513A 2 145 E 31 National Instruments Corporation AT MIO 16D User Manual AMD Am9513A Data Sheet Enable Data Pointer Sequencing Coding C7 C6 C5 C4 C3 C2 C1 CO 1 1 1 0 0 0 0 0 Description This command clears Master Mode bit 14 without affecting other bits in the Maste
275. onnector National Instruments Corporation 4 31 AT MIO 16D User Manual Programming Chapter 4 MIO 16 Digital Output Register Writing to the MIO 16 Digital Output Register controls the eight AT MIO 16D digital I O lines The MIO 16 Digital Output Register controls both ports A and B When either digital port is enabled the pattern contained in the MIO 16 Digital Output Register is driven onto the lines of the digital port at the MIO 16 I O connector Address Base address 1C hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIOI BDIOO ADIO3 ADIO2 ADIOI ADIOO Bit Name Description 15 8 X Don t care bits 7 4 BDIO lt 3 0 gt These four bits control the digital lines BDIO lt 3 0 gt at the MIO 16 I O connector The bit DOUTIEN in Command Register 2 must be set for BDO lt 3 0 gt to be driven onto the digital lines BDIO lt 3 0 gt 3 0 ADIO lt 3 0 gt These four bits control the digital lines ADIO lt 3 0 gt at the MIO 16 I O connector The bit DOUTOEN in Command Register 2 must be set for ADIO 3 0 to be driven onto the digital lines ADIO lt 3 0 gt AT MIO 16D User Manual 4 32 National Instruments Corporation Chapter 4 Programming The RTSI Switch Register Group The two registers making up the RTSI Switch Register Group allow the AT MIO 16D RTSI switch to be programmed for routing of signals on the RTSI bus trigger lines to and from several AT MIO 16D
276. ons with Interval Channel Scanning Pseudo Simultaneous Programming scanned multiple A D conversions with a scan interval involves the following programming steps 1 Set up the analog channel and gain selection sequence Program the sample interval counter Program the sample counter Program the scan interval counter Clear the A D circuitry and reset the multiplexer counter Sx gRe D Enable the scanning data acquisition operation 7 Apply a trigger 8 Service the data acquisition operation Setting the SCANEN bit in Command Register 1 enables scanning during multiple A D conversions You must set this bit regardless of the type of scanning used otherwise only a single channel is scanned In addition a channel and gain scan sequence must be stored in the mux gain memory Setting the SCN2 bit in Command Register 2 enables the use of a scan interval during multiple A D conversions The scan interval counter gives each cycle through the scan sequence a time interval The scan interval counter begins counting at the start of the scan sequence programmed into the mux gain memory When the scan sequence completes the next cycle through the scan sequence does not begin until the scan interval counter has reached its terminal count Be sure that the scan interval counter allows enough time for all conversions in a scan sequence to occur so that conversions are not missed AT MIO 16D User Manual 4 62 National Instruments
277. onsult the following Advanced Micro Devices manual if you plan to program the Am9513A Counter Timer used on the AT MIO 16D e Am9513A Am9513 System Timing Controller technical manual Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix G Customer Communication at the end of this manual National Instruments Corporation vii AT MIO 16D User Manual Contents Chapter 1 Introdu tio cases A 1 1 What Your Kit Should CODI pe tees ido arist 1 3 Optional SoftWare 1 4 Optional RETOURNER RORIS qe 1 5 Custom SCIL C Cm 1 6 Unpacking ERR Ts 1 7 Chapter 2 Configuration and Installation sss 2 1 Board Conf eur an ptr eere fedi aded 2 1 A T Dus Interbabe s ceo ideo est teet ts 2 1 Base DO Address Selections anode tore eo eate Aa 2 3 DNLA Channel Selection ood ma eee Ree 2 5 Tnt rrupt SCS CE ON ce MEE 2 7 DIO 24 Circuitry Interrupt Enable Settings eee 2 8 Analog
278. ontrol circuitry generates DMA requests whenever an A D measurement is available from the A D FIFO if the DMA transfer is enabled The DMA circuitry supports full PC AT I O channel 16 bit DMA transfers DMA channels 5 6 and 7 of the PC AT I O channel are available for such transfers With the DMA circuitry either single channel transfer mode or dual channel transfer mode can be selected for DMA transfer Analog Input and Data Acquisition Circuitry The AT MIO 16D handles 16 channels of analog input with software programmable gain and 12 bit A D conversion In addition the AT MIO 16D contains data acquisition circuitry for automatic timing of multiple A D conversions and includes advanced options such as external triggering gating and clocking Figure 3 3 shows a block diagram of the analog input and data acquisition circuitry AT MIO 16D User Manual 3 4 O National Instruments Corporation Theory of Operation Chapter 3 x gt m e a 5 e UM ALOXNW s euaig Jour 1ojuno uonisinboy J9 19AUO Iogrdury 8 6M 79 aol Uuonoo og 9poIN XAN LNOOXNW 103290007 DIAL dOLS ANOO LX DIAL LAV LIS WTO NVOS STHOV TIHOV CIHOV IIHOV OIHOV 6HOV 8HOV 5 5 IV LHOV 9HOV SHOV VHOV CHOV THOV 3 Analog Input and Data Acquisition Circuitry Block Diagram Figure 3 AT MIO 16
279. operation because the Am9513A should always be used in 16 bit mode on the AT MIO 16D National Instruments Corporation 4 29 AT MIO 16D User Manual Programming Chapter 4 MIO 16 Digital I O Register Group The two registers making up the MIO 16 Digital I O Register Group monitor and control the AT MIO 16D digital I O lines The MIO 16 Digital Input Register returns the digital state of the eight digital I O lines A pattern written to the MIO 16 Digital Output Register is driven onto the digital I O lines when the digital output drivers are enabled see the description for Command Register 2 Bit descriptions for the registers making up the MIO 16 Digital I O Register Group are given on the following pages AT MIO 16D User Manual 4 30 National Instruments Corporation Chapter 4 Programming MIO 16 Digital Input Register The MIO 16 Digital Input Register when read returns the logic state of the eight AT MIO 16D digital I O lines at the MIO 16 I O connector Address Base address 1C hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 amp 7 6 5 4 3 2 1 0 BDIO3 BDIO2 BDIOI BDIOO ADIO3 ADIO2 ADIOI ADIOO Bit Name Description 15 8 X Don t care bits 7 4 BDIO lt 3 0 gt These four bits represent the logic state of the digital lines BDIO lt 3 0 gt from the MIO 16 I O connector 3 0 ADIO lt 3 0 gt These four bits represent the logic state of the digital lines ADIO lt 3 0 gt from the MIO 16 I O c
280. or Disabling DMA Transfers esse 2 7 Figure 2 6 Factory Interrupt Jumper Settings IRQ5 DIO 24 and IRQ10 16 2 7 Figure 2 7 Interrupt Jumper Setting for Disabling Interrupts eese 2 8 Figure 2 8 Jumper Settings PC6 PC4 2 2 2 8 Figure 2 9 DIFF Analog Input Configuration Factory Setting sess 2 11 Figure 2 10 RSE Analog Input are nbn ads 2 11 Figure 2 11 NRSE Analog Input Configuration epe per tds 2 12 Figure 2 12 10 V Input Conn guration eq era eee daret need deine ae 2 13 Figure 2 13 5 to 45 V Input CODLIPUFaltlOl sect Regn nera ee e are 2 13 Figure 2 14 Factory 10 to 10 V Analog Input Configuration eene 2 13 Figure 2 15 External Reference Config ratiOn eu eui Qk edet ecc te puedas 2 15 Figure 2 16 Factory Internal Reference Configuration esee 2 16 Figure 2 17 Factory Bipolar Output Configuration ee 2 16 Fig fr 2 18 Straight Binary epe oerte etas ere 2 17 Figure 2 19 Two s Complement Mode Factory Setting esee 2 17 Figure 2 20 Unipolar Output Configuration essent nre 2 18 Figure 2 21 Disconnect from RTSI Bus Clock Us
281. or RSE only one analog input channel is selected In DIFF mode two analog input channels are selected A table showing the analog input channel selected for either mode is given below lt 3 0 gt Selected Analog Input Channels Single Ended DIFF Un gt 0 1 2 3 4 5 6 7 8 9 gt Re Pe Re 0 Re 0 Re Ro 0 Po Pe m D m me m e e Un gt Writing to the Mux Gain Register updates the current analog input channel selection and the current gain setting The mux gain memory is also loaded by writing to the Mux Gain Register The multiplexer counter is written to in order to address a specific location in the mux gain memory Any subsequent value written to the Mux Gain Register is then stored in that memory location as well as applied to the analog input multiplexer and gain circuitry National Instruments Corporation 4 23 AT MIO 16D User Manual Programming Chapter 4 A D FIFO Register Reading the A D FIFO Register returns the oldest A D conversion value stored in the A D FIFO Whenever the A D FIFO is read the value read is removed from the A D FIFO thereby leaving space for another A D conversion value to be stored Values are stored into the A D FIFO by the ADC whenever an A D conversion is complete The A D FIFO is emptied when all values it contains are read The Status Register should
282. ord of zero One LSB is the voltage increment corresponding to an LSB change in the digital code word For unipolar output 1 LSB V445 4 096 For bipolar output 1 LSB V 9 2 048 Analog Output Data Coding The voltage reference source for each DAC is jumper selectable and can be supplied either externally at the EXTREF input or internally The external reference can be either a DC or an AC signal If an AC reference is applied the analog output channel acts as a signal attenuator and the AC signal appears at the output attenuated by the digital code divided by 4 096 for unipolar output Bipolar output with an AC reference provides four quadrant multiplication which means that the signal is inverted for digital codes 0 to 2 047 and not inverted for digital codes 2 049 to 4 095 In straight binary mode a digital code word of 2 048 attenuates the input signal to 0 V This attenuation is equivalent to multiplying the signal by digital code word 2 048 2 048 In two s complement mode a digital code word of zero attenuates the input signal to The internal voltage reference is a buffered version of the 10 V reference supplied by the ADC Using the internal reference supplies an output voltage range of to 9 9976 V in steps of 2 44 mV for unipolar output and an output voltage range of 10 V to 9 9951 V in steps of 4 88 mV for bipolar output MIO 16 Digital Circuitry The MIO 16 circuitry of the AT MIO 16D provides eight digi
283. orm is controlled by the relative Load and Hold values and very fine resolution of duty cycles ratios may be achieved Bit CM7 controls the special gating functions that allow retriggering and the selection of Load or Hold sources for counter reloading The use and definition of CM7 will depend Am9513A Appendix E National Instruments Corporation Appendix on the status of the Gating Control field and bits 5 and CM6 Hardware Retriggering Whenever hardware rotriggering is enabled Modes N Q and active going Gate edges initiate retrigger opera tions On application of the Gate edge the counter contents will be transferred to the Hold register On the first qualified Source edge after application of the retriggering Gate edge the Load register contents will be transferred into the counter Qualified source edges are edges which occur while the counter is gated on and Armed This means that if level gating is used the edge occurring on active going gate transitions will initiate a retrigger Similarly when edge gating is enabled an edge used to start the counter will also initiate a retrigger The first count source edge applied after the Gate edge will not increment decre ment the counter but retrigger it LOAD LOAD AND ARM or a STEP Command occurs between the retriggering Gate edge and the first qualified Source edge it will be interpreted as a source edge and transfer the Load r
284. ort is input Ports are outputs Write data to Port B Write data to Port C Read data from Port A Ports are outputs Port is an input Ports A and B are outputs Port C is an input Mode transfers data that is synchronized by handshaking signals Ports A and B use the eight lines of Port C to generate or receive the handshake signals This mode divides the ports into two groups Group A and Group B Each group contains one 8 bit data port Port A or Port B and one 4 bit control data port upper or lower nibble of Port C The 8 bit data ports can be either input or output both of which are latched The 4 bit ports are used for control and status of the 8 bit data ports The transfer of data is synchronized by handshaking signals in the 4 bit port Interrupt generation and enable and or disable functions are available The control word written to the DIO 24 CNFG Register to configure Port A for input in Mode 1 is shown as follows Bits PC6 and PC7 of Port C can be used as extra input or output lines 71 6 5 4 3 2 1 0 Port C bits PC6 and PC7 1 input 0 output AT MIO 16D User Manual 4 82 National Instruments Corporation Chapter 4 Programming The control word written to the DIO 24 CNFG Register to configure Port B for input in Mode 1 is shown as follows Notice that Port B does not have extra input or outp
285. oscillator frequency source Programmable input and output polarities Programmable gating functions GENERAL DESCRIPTION The 51 System Timing Controller is LSI circuit The STC includes five general purpose 16 bit counters A selectable active high or active low input polarity Both hardware and software gating of each counter is available Three state outputs for each counter provide pulses or levels and can be active high or active iow The counters be programmed to count up or down in either binary or BCD The host processor may read an accumulated count at any time without disturbing the counting process Any of the counters may be intemally concatenated to form any effective counter length up to 80 bits 2 116 16 User Manual E2 National Instruments Corporation Appendix E AMD Am9513A Data Sheet CONNECTION DIAGRAMS USSNHOTCESESUSS BRERERRSE DBIO GATESA 9 DBt GATE4A JN D812 GATESA T X Note Pin 1 is marked for orientation ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges The order number Valid Combination is formed by a combination of a Device Number b Speed Option if applicable Type ESNE een Blank Standard processing B Burin d TEMPERATURE RANGE C Commercial 0 to 70 C Industrial 40 to 85 C PACKAGE TYPE 40 Pin Plastic D
286. ould be tied directly to Ground or VCC as appropriate An input in use wil have some type of logic output driving it and termination during operation wiil not be a problem Where inputs are driven from logic extemal to the card containing this chip however on board termination should be provided to protect the chip when the board is unplugged the input would otherwise float A pull up resistor or a simpie gne will suffice E 7 2 121 AT MIO 16D User Manual AMD 9513 Data Sheet DETAILED DESCRIPTION The Am9513A System Timing Controller STC is a support device for processor oriented systems that is designed to enhance the available capability with respect to counting and timing operations It provides the capability for programmable frequency synthesis high resolution programmable duty cycle waveforms retriggerable digital timing functions time of day clocking coincidence alarms complex pulse generation high resolution baud rate generation frequency shift keying stop watching timing event count accumulation waveform analysis and many more A variety of programmable operating modes and control features allow the Am9513A to be personalized for particular applications as well as dynamically reconfigured under program control The STC includes five general purpose 16 bit counters A variety of interna frequency sources and external pins may be selected as inputs for individual counters with sof
287. ount are stored in Counter 4 and the upper 16 bits of the sample count are stored in Counter 5 All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the least significant 16 bits of the sample count value minus 1 to the Am9513A Data Register to store the Counter 4 load value e Ifthe least significant 16 bits are all zero write FFFF e Write FF48 to the Am9513A Command Register to load and arm Counter 4 f Write 0 to the Am9513A Data Register to store 0 into the Load Register for Counter 4 reloading g Write FF28 to the Am9513A Command Register to arm Counter 4 h Write 05 to the Am9513A Command Register to select the Counter 5 Mode Register i Write 25 to the Am9513A Data Register to store the Counter 5 mode value j Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register k Take the most significant 16 bits of the sample count and do the following e Ifthe least significant 16 bits of the sample count are all zeros or all zeros except for a 1 in the least significant bit write the most significant 16 bits to the Am9513A Data Register to store the Counter 5 load value e Otherwise add 1 to the most significant 16 bits of the sample cou
288. ount state National Instruments Corporation 4 69 AT MIO 16D User Manual Programming Chapter 4 Resetting Counter 4 To reset Counter 4 use the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FFC8 to the Am9513A Command Register to disarm Counter 4 2 Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register 3 Write 4 to the Am9513A Data Register to store the Counter 4 mode value such that counter output becomes high impedance If Counter 4 is not to be used during the next data acquisition operation write 0 to the Am9513A Data Register to drive the output low 4 Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register 5 Write 3 to the Am9513A Data Register to store non terminal count value in the Counter 4 Load Register 6 Write FF48 to the Am9513A Command Register to load Counter 4 7 Write FF48 to the Am9513A Command Register a second time to load Counter 4 again to guarantee that Counter 4 is not left in a terminal count state Resetting Counter 5 To reset Counter 5 use the following programming sequence writes are 16 bit operations values given are hexadecimal 1 Write FFDO to the Am9513A Command Register to disarm Counter 5 2 Write FF05 to the Am9513A Command Register to select the Counter 5 Mode Register 3 Write 4 to the Am9513A Data Register to store the Counter 5 mode value such that c
289. ounter output becomes high impedance 4 Write FFOD to the Am9513A Command Register to select the Counter 5 Load Register 5 Write 3 to the Am95134A Data Register to store non terminal count value in the Counter 5 Load Register 6 Write FF50 to the Am9513A Command Register to load Counter 5 7 Write FF50 to the Am9513A Command Register a second time to load Counter 5 again to guarantee that Counter 5 is not left in a terminal count state After resetting the counters write 0 to the A D Clear Register to clear all error conditions and to empty the A D FIFO AT MIO 16D User Manual 4 70 National Instruments Corporation Chapter 4 Programming Programming the Analog Output Circuitry The voltage at the analog output circuitry output pins pins DACO OUT and DACI OUT on the AT MIO 16D MIO 16 I O connector is controlled by loading the DAC in the analog output channel with a 12 bit digital code This DAC is loaded by writing the digital code to the DACO and DACI Registers Writing to the DACO Register controls the voltage at the DACO OUT pin on the MIO 16 I O connector Writing to the DACI Register controls the voltage at the DACI OUT pin The analog output on pins DACO OUT and DACI OUT can be updated in one of two ways immediately when DACO or DACI is written or when an active low pulse is detected on the OUT2 pin of the Am9513A Counter Timer The LDAC bit in Command Register 2 selects which update method is used The output voltage g
290. ounter as occurring after the action initiated by the write operation and the counter may be off by one count 6 This parameter applies to cases where the write operation causes a change in the output bit 7 The enabled count source is one of F1 F5 TCN 1 SRC1 SRCS or GATE1 GATE 5 as selected in the applicable Counter Mode register The timing diagram assumes the counter counts on rising source edges The timing specifications are the same for failing edge counting 8 This parameter applies to edge gating CM15 CM13 110 or 111 and gating when both CM7 1 and 15 CM13 000 This parameter represents the minimum GATE pulse width needed to ensure that the pulse initiates counting or counter reloading 9 This parameter applies to both edge and level gating CM15 CM13 001 through 111 and CM7 0 This pa rameter represents the minimum setup or hold times to ensure that the Gate input is seen at the intended level on the active source edge and the counter may be off by ono count 10 This parameter assumes that the GATENA input is unused 16 bit bus mode or is tied high In cases where the GATENA input is used this timing specification must be met by both the GATE and GATENA inputs 11 Signals F1 F5 cannot be directly monitored by the user The phase difference between these signals will manifest itself by causing counters using two different F signals to count at different times on nominally simultaneous tr
291. ources 2 28 to 2 29 floating signals 2 26 recommended configurations for ground referenced and floating signal sources 2 27 single ended connections floating signal RSE sources 2 30 to 2 31 general considerations 2 30 AT MIO 16D User Manual Index 22 O National Instruments Corporation Index grounded signal NRSE sources 2 31 to 2 32 MIO 16 signal descriptions 2 23 to 2 24 pin assignments AT MIO 16D I O connector 2 21 D 1 DIO 24 I O connector 2 43 C 1 MIO 16 I O connector 2 22 B 1 power connections MIO 16 I O connector 2 36 RTSI switch 4 74 timing connections 2 36 to 2 42 data acquisition timing connections 2 36 to 2 38 general purpose connections 2 38 to 2 42 pins for 2 36 types of signal sources floating signal sources 2 26 ground referenced signal sources 2 27 warning against exceeding ratings 2 21 single channel data acquisition 3 9 single channel multiple A D conversions See multiple A D conversions programming single ended connections floating signal RSE sources 2 30 to 2 31 general considerations 2 30 grounded signal NRSE sources 2 31 to 2 32 single ended input configuration NRSE input 16 channels 2 12 RSE input 16 channels 2 11 to 2 12 software optional 1 4 SOURCE OUT and GATE timing signals 2 38 to 2 42 3 14 to 3 15 3 16 SOURCE signal 2 24 SOURCE signal 2 24 SOURCES signal 2 24 specifications Am9513A System Timing Controller E 33 to E 38 DIO 24 circuitry input signal
292. output lines when Port A uses Mode 1 output AT MIO 16D User Manual 4 84 National Instruments Corporation Chapter 4 Programming Port C bits PC4 and PC5 1 input 0 output The control word written to the DIO 24 CNFG Register to configure Port for output in Mode 1 is shown as follows Notice that Port B does not have extra input or output lines from Port C 7 6 5 4 3 2 1 0 IJXIXIXIX 150 X During a Mode 1 data write transfer the status of the handshaking lines and interrupt signals can be obtained by reading Port C Notice that the bit definitions are different for a write and a read transfer The following are the Port C status word bit definitions for output Port A and Port B 7 6 5 4 3 2 1 0 INTEA INTRA INTEB OBFB INTRB Bit Name Description 7 Output buffer full for Port Low indicates that the CPU has written data to Port A 6 INTEA Interrupt enable bit for Port A If this bit is high DIO interrupts are enabled from the 82C55A for Port A Controlled by bit set reset of PC6 5 4 UO Extra I O status line when Port A is in Mode 1 output 3 INTRA Interrupt request status for Port A When INTEA is high and OBFA is high this bit is high indicating that a DIO interrupt request is asserted 2 INTEB Interrupt enable bit for Port B If this bit is high interrupts are enabled from the 82C55A for Port B Controlled by bit set reset of PC2 1 OBFB Output buffer full for Port B
293. p B Output Group B Input Group B Output Notes VO is a bit not usad as the control signal but it is available as port of mode 0 Examples of the relation between the control words and pins when used in mode 1 is shown below When group is mode 1 output and group is mode 1 input As all of PCo PC3 bits become a contro Selection of 1 0 pin in this case this of PC4 and bit is Don t Care when not defined e as 8 control pin 1 Input 0 Output OBFA ACKA INTRA Vo Group A Mode 1 output gt Group Mode 1 input STBg 340 National Instruments Corporation F 13 16 User Manual Oki MSM82C55A Data Sheet b When group A is mode 1 input and group B is mode 1 output D7 De Ds D4 D3 Di Do Selection of I O of PCS and PC7 when not de fined as a control pin 1 input O Output STBA IBFA INTRA Vo OBFg ACKg INTRg 3 Mode 2 Strobe bidirectional bus 1 operation In mode 2 it is possible to transfer data in 2 direc tions through a single 8 bit port This operation is akin to a combination between input and output operations Port C waits for the control signal in this case too Mode 2 is available only for group A however Next description is made on mode 2 OBF Output buffer full flag output This signal when turned to low level indicates that data has been written to the internal out put latch upon receipt of the WR signa
294. pin female connectors with 50 conductor ribbon cables via a cable assembly National Instruments uses a keyed connector to prevent inadvertent upside down connection to the board The recommended manufacturer part number for this mating connector is as follows e Robinson Nugent part number P50E 100S TG Figure 1 2 shows the AT MIO 16D cable assembly MIO 16 50 pin I O Connector AT MIO 16D Board DIO 24 50 pin I O Connector Figure 1 2 AT MIO 16D Cable Assembly Recommended manufacturer part numbers for standard ribbon cable 50 conductor 28 AWG stranded that can be used with the mating connector are as follows Electronic Products Division 3M part number 3365 50 e T amp B Ansley Corporation part number 171 50 Recommended manufacturer part numbers for the 50 pin edge connector for connecting to a module rack with an edge connector are as follows Electronic Products Division 3M part number 3415 0001 e T amp B Ansley Corporation part number 609 5015 AT MIO 16D User Manual 1 6 National Instruments Corporation Chapter 1 Introduction You can plug a polarizing key into these edge connectors to prevent inadvertent upside down connection to the I O module rack The location of this key varies from rack to rack Consult the specification for the rack you intend to use for the location of any polarizing key The recommended manufacturer part numbers for this polarizing key are as follows Ele
295. ple interval from this point Figure 2 36 STOP TRIG Signal Timing The STOP TRIG signal is one LS TTL load and is pulled up to 5 V through a 4 7 kQ resistor General Purpose Timing Signal Connections The general purpose timing signals include the GATE SOURCE and OUT signals for the Am9513A Counters 1 2 and 5 and the FOUT signal generated by the Am9513A Counters 1 2 AT MIO 16D User Manual 2 38 National Instruments Corporation Chapter 2 Configuration and Installation and 5 of the Am9513A Counter Timer can be used for general purpose applications such as pulse and square wave generation event counting and pulse width time lapse and frequency measurements For these applications SOURCE and GATE signals can be directly applied to the counters from the I O connector and the counters are programmed for various operations The Am9513A Counter Timer is described briefly in Chapter 3 Theory of Operation For detailed programming information consult Appendix E 9513 Data Sheet For detailed applications information consult 9513 9513 System Timing Controller technical manual published by Advanced Micro Devices Inc You can produce pulses and square waves by programming Counter 1 2 or 5 to generate a pulse signal at its OUT output pin or to toggle the OUT signal each time the counter reaches the terminal count For event counting program one of the counters to count rising or falling edges applied to any
296. put of the board The amount of noise that is reported directly without any analysis by the ADC is not necessarily the amount of real noise present in the system unless the noise is gt 0 5 LSB root mean square rms Noise that is less than this magnitude produces varying amounts of flicker and the amount of flicker seen is a function of how near the real mean of the noise is to a code transition If the mean is near or at a transition between codes the ADC flickers evenly between the two codes and the noise is seen as very nearly 0 5 LSB If the mean is near the center of a code and the noise is relatively small very little or no flicker is seen and the noise is reported by the ADC as nearly 0 LSB From the relationship between the mean of the noise and the measured rms magnitude of the noise the character of the noise can be determined National Instruments has determined that the character of the noise in the AT MIO 16D is fairly Gaussian and so the noise specifications given are the amounts of pure Gaussian noise required to produce our readings Analog Data Acquisition Rates Single Channel Acquisition Rates The maximum data acquisition rate for the AT MIO 16D is 100 ksamples sec Permissible data acquisition rates are determined by the minimum A D conversion time of the system This minimum conversion time is the sum of the conversion time of the ADC and the settling time of the analog input front end When data acquisition is performed o
297. quest for output operation and it can be reset by the bit set for PC6 INTE2 is used to controi the interrupt request for the in Lh operation and it can be set by the bit set for 341 i O MSM82C55A 2RS GS VJS m Appendix F National Instruments Corporation Appendix F Oki 5 82 55 Data Sheet a O MSM82C55A 2RS GS VJS Mods 2 1 Operation Port C Function Allocation in Mode 2 Confirmed to the group B mode Following is an example of the relation between the controi word and the pin when used in mode 2 When input mode 2 for group and in mode 1 for group B As all of 8 bits of port C be come control pins in this case D3 and DO bits are treated as Don t Care When group A is set to mode 2 this bit is troated No 1 0 specification is required for mode 2 since it is a bidirec tional operation This bit is therefore treated as Don t INTRA OBFA STB IBFA Group A Group B 342 Q National Instruments Corporation F 15 AT MIO 16D User Manual Oki MSM82C55A Data Sheet Appendix F ns yO MSM82C55A 2RS GS VJS 4 When Group A is Different in Mode from Group B possible to set the one not defined as a control pin Group A and group B can be used by setting them in port C to both input and output as a port which in different modes each other at the same time operates in mode at the 3rd and Oth bits of the When e
298. r b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the sample count value to the Am9513A Data Register to store the Counter 4 load value Ifthe sample count is between 2 and FFFF 65 535 decimal write the sample count to the Am9513A Data Register Ifthe sample count is 10000 65 536 decimal write 0 to the Am9513A Data Register e Write FF48 to the Am9513A Command Register to load Counter 4 f Write FFF4 to the Am9513A Command Register to decrement Counter 4 g Write FF28 to the Am9513A Command Register to arm Counter 4 h Clear the 16 32 CNT bit in Command Register 1 to notify the hardware that only Counter 4 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition operation when Counter 4 decrements to zero AT MIO 16D User Manual 4 48 National Instruments Corporation Chapter 4 Programming Sample Counts Greater Than 65 536 To program the sample counter for sample counts greater than 65 536 use the following programming sequence The lower 16 bits of the sample count are stored in Counter 4 and the upper 16 bits of the sample count are stored in Counter 5 All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Comm
299. r else high accuracy will not be achieved The settling time is determined by the gain selected Table 3 1 shows the maximum recommended data acquisition rates for both single channel and multiple channel data acquisition The rates in Table 3 1 refer to typical settling accuracies of 0 5 LSBs of the final value National Instruments Corporation 3 9 AT MIO 16D User Manual Theory of Operation Chapter 3 Table 3 1 AT MIO 16D Maximum Recommended Data Acquisition Rates Data Acquisition Type Data Acquisition Rate Single channel data acquisition Any gain setting 100 ksamples sec Multiple channel data acquisition Gain 1 2 4 8 100 ksamples sec Gain 10 100 ksamples sec Gain 100 70 ksamples sec Gain 500 20 ksamples sec Analog Output Circuitry The AT MIO 16D provides two channels of 12 bit digital to analog D A output Each analog output channel provides options such as unipolar or bipolar output and internal or external reference voltage selection Figure 3 4 shows a block diagram of the analog output circuitry Bipolar Unipolar Selection DACOWR op amps DACI OUT REF Sch DACIWR DACI op amps DACO OUT EXTREF I O Connector W8 W7 PC AT I O Channel Bipolar Unipolar Selection REF Selection Figure 3 4 Analog Output Circuitry Block Diagram AT MIO 16D User Manual 3 10 O National Instruments Corporation Chapter 3 Theory of Operation Each analog output channel contains a 12 b
300. r Mode 1 output for Port A Select 4 as the interrupt enable bit outp cnfg 0xA0 Port is an output in Mode 1 outp cnfg 0 0 Set PC6 to enable interrupts from 82C55A outp cnfg 0x0C Clear PC4 to enable interrupts EXAMPLE 4 Set up interrupts for Mode 1 output for Port B Select 4 as the interrupt enable bit outp cnfg 0x84 Port B is an output in Mode 1 outp cnfg 0x05 Set PC2 to enable interrupts from 82C55A outp cnfg 0x08 Clear PC4 to enable interrupts EXAMPLE 5 Set up interrupts for Mode 2 output transfers Select PC2 as the interrupt enable bit 0 0 Mode 2 output outp cnfg 0 0 Set PC6 to enable interrupts from 82C55A outp cnfg 0x04 Clear PC2 to enable interrupts EXAMPLE 6 Set up interrupts for Mode 2 input transfers Select 2 as the interrupt enable bit outp cnfg 0xD0 Mode 2 input outp cnfg 0x09 Set PC4 to enable interrupts from 82C55A outp cnfg 0x04 Clear PC2 to enable interrupts DIO 24 Interrupt Handling A jumper setting on the AT MIO 16D selects the signal that is used for the DIO 24 interrupt enable signal If jumper W14 is set to N C interrupts are disabled Jumper W14 be used to select PC2 PC4 or PC6 as the active low interrupt enable signal For example if PC2 is sele
301. r Mode register MM14 controls the automatic sequencing of the Data Pointer regis ter Enabling the sequencing allows sequential host processor access to several internal locations without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode register See the Data Pointer Register section of this document for additional information on Data Pointer sequencing Enable 16 Bit Data Bus Coding C6 CS C4 C2 1 34 0 d 4 1 Description This command sets Master Mode bit 13 without affecting other bits in the Master Mode register MM13 controls the multiplexer in the data bus buffer When MM13 is set no multiplexing takes place and 16 external data bus lines are used to transfer information into and cut of the STC MM13 may also be controlled by loading the full Master Mode register in parailel Enable 8 Bit Data Bus C7 C6 C5 C4 C2 Ci CO 1 1 1 0 0 14d 1 1 affecting other bits in the Master Mode register MM13 controls the multiplexer in the data bus buffer When MM13 is Cleared the multiplexer is enabled and 16 bit internal informa tion is transferred eight bits at a time to the eight low order external data bus lines MM13 may aiso be controlled by loading the full Master Mode register in parallel Gate Off FOUT Coding ce C5 C4 C3 C2 co 0 1 1 0 Description This command sets Master Mode bit 12 without affecting other
302. r is a read or a write The PC AT I O channel interface timing signals are used to generate read and write signals and to define the transfer cycle A transfer cycle can be either an 8 bit or a 16 bit data I O operation The AT MIO 16D returns signals to the PC AT I O channel to indicate when the board has been National Instruments Corporation 3 3 AT MIO 16D User Manual Theory of Operation Chapter 3 accessed when the board is ready for another transfer and the data bit size of the current I O transfer The interrupt control circuitry routes any enabled interrupt requests to the selected interrupt request line The interrupt requests are tristate output signals allowing the AT MIO 16D board to share the interrupt lines with other devices Eleven interrupt request lines are available for use by the 16 IRQ3 IRQ4 5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 and IRQI5 Five different interrupts can be generated by the MIO 16 circuitry of the AT MIO 16D e When an A D conversion is available to be read from the A D FIFO memory e When a data acquisition operation completes e When a DMA terminal count pulse is received e When arising edge signal is detected on the OUT2 pin of the Am9513A Counter Timer When either an OVERFLOW or an OVERRUN error occurs Each one of these interrupts is individually enabled and cleared See Chapter 4 Programming for more information about programming with interrupts The DMA c
303. r offset trim analog input R8 Unipolar offset trim analog input R2 Instrumentation amplifier input offset trims The following trimpots are used to calibrate the analog output circuitry R5 Gain trim analog output channel 0 R4 Gain trim analog output channel 1 R7 Offset trim analog output channel 0 Offset trim analog output channel 1 AT MIO 16D User Manual 5 2 National Instruments Corporation Chapter 5 Calibration Procedures Analog Input Calibration To null out error sources that compromise the quality of measurements you must calibrate the analog input circuitry by adjusting the following potential sources of error e Offset error at the input of the instrumentation amplifier e Offset error at the input of the ADC e Gain error of analog input circuitry Offsets at the input to the instrumentation amplifier contribute gain dependent error to the analog input system This offset is multiplied by the gain of the instrumentation amplifier To calibrate this offset you must ground the analog input read it at two different gain settings and adjust a trimpot until the readings match at the two different gain settings Offset error at the input of the ADC is the total of the voltage offsets contributed by the circuitry from the output of the instrumentation amplifier to the ADC input including the offsets of the ADC Offset errors appear as a voltage added to the input voltage being measured To calibra
304. r the Master Mode register This section describes the use of each control field Master Mode register bits MM12 MM13 and 14 can be individually set and reset using commands issued to the Command register In addition they can all be changed by writing directly to the Master Mode register After power on reset or a Master Reset command the Master Mode register is cleared to an all zero condition This results in the following configuration Time of Day disabled Both Comparators disabled FOUT Source is frequency F1 FOUT Divider set for divide by 16 FOUT gated on Data Bus 8 bits wide Data Pointer Sequencing enabled Frequency Scaler divides in binary Am9513A 2 125 National Instruments Corporation 11 AT MIO 16D User Manual Am9513A Data Sheet FOUT Divider 0000 Divide by 16 0001 Oide by 1 0010 Divide by 2 0011 Ode by 3 0100 Oivide by 4 0101 Divide by 5 0110 by 6 0111 Divide by 7 1000 Divide by 8 1001 Oivide by 9 1010 Divide by 10 1011 Oivide by 11 1100 Divide by 12 1101 Divide by 13 1110 Divide by 14 1111 by 15 FOUT Source 0000 Et 0001 SRC 1 0010 SRC 2 0011 SRC3 0100 SRC 4 0101 SRC 5 0110 GATE 1 011 GATE 2 1000 GATE 3 1001 GATE 4 1010 GATE 5 1011 Ft 1100 F2 1101 F3 1110 F4 1111 F5 1 FOUT OF Low Z to GND Date Bus Width 0 8 Bit Bus 1 16 86 Gus Date Pointer Con
305. r to disarm Counter 2 2 Write FF02 to the Am9513A Command Register to select the Counter 2 Mode Register 3 Write 4 to the Am9513A Data Register to store the Counter 2 mode value such that counter output becomes high impedance 4 Write FFOA to the Am9513A Command Register to select the Counter 2 Load Register 5 Write 3 to the Am9513A Data Register to store nonterminal count value in the Counter 2 Load Register 6 Write FF42 to the Am9513A Command Register to load Counter 2 7 Write FF42 to the Am9513A Command Register a second time to load Counter 2 again to guarantee that Counter 2 is not left in a terminal count state Resetting Counter 3 To reset Counter 3 use the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FFC4 to the Am9513A Command Register to disarm Counter 3 2 Write FF03 to the Am9513A Command Register to select the Counter 3 Mode Register 3 Write 4 to the Am9513A Data Register to store the Counter 3 mode value such that counter output becomes high impedance 4 Write FFOB to the Am9513A Command Register to select the Counter 3 Load Register 5 Write 3 to the Am9513A Data Register to store nonterminal count value in the Counter 3 Load Register 6 Write FF44 to the Am9513A Command Register to load Counter 3 7 Write FF44 to the Am9513A Command Register a second time to load Counter 3 again to guarantee that Counter 3 is not left in a terminal c
306. ram the 82 55 The Control Word Flag determines which control word format is being programmed When the Control Word Flag is 1 bits 0 through 6 determine the I O characteristics of the 82C55A ports and the mode in which they are operating that is Mode 0 Mode 1 or Mode 2 When the Control Word Flag is 0 bits 3 through 0 determine the bit set reset format of Port C AT MIO 16D User Manual 4 78 National Instruments Corporation Chapter 4 Control Word Flag 1 Mode Set Mode Selection 00 Mode 0 01 Mode 1 1X Mode 2 Port A 1 input 0 output Port C high nibble input 0 output Control Word Flag 0 Bit Set Reset Unused dc eee eS leona 57 b 5s va n o Figure 4 2 Control Word Formats Programming Port C low nibble input 0 output Port B input 0 output Mode Selection 0 2 Mode 0 Mode 1 Bit Set Reset 1 Set 0 Reset Bit Select 000 001 010 111 Table 4 8 shows the control words for setting or resetting each bit in Port C Notice that bit 7 of the control word is cleared when programming the set reset option for the bits of Port C National Instruments Corporation 4 79 AT MIO 16D User Manual Programming Chapter 4 Table 4 8 Port C Set Reset Control Words Bit Set Bit Reset Bit Set or Control Word Control Word Reset in Port C Oxxx0001 0000 XXXXXXXN Oxxx0011 Oxxx0010 XXXXXXNX Oxxx0101 Oxxx0
307. ramming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and Counter 5 decrements every time Counter 4 reaches zero The data acquisition operation is terminated when both Counters 4 and 5 reach Zero Counters 4 and 5 begin counting A D conversion pulses when a rising edge signal is received on the STOP TRIG input A D conversion data stored before receipt of the STOP TRIG signal are pretrigger samples 4 Clear the A D circuitry Before you start the data acquisition operation the A D FIFO must be emptied to clear out any old A D conversion results You must do this emptying after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 16 bit write 5 Apply a trigger Once set up by the preceding steps the data acquisition operation is initiated when a trigger is received A trigger can be provided in one of two ways through software or through hardware To initiate the data acquisition operation through software write to the Start Register 16 bit write To initiate the data acquisition operation through hardware apply an active low pulse to the START TRIG pin on the AT MIO 16D I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for START TRIG signal specifications Once the trigger is applied Counter 3 generates pulses initiat
308. ration 2 12 definition of 2 10 single ended connections for grounded signal sources 2 31 to 2 32 NRSE input See nonreferenced single ended NRSE input AT MIO 16D User Manual Index 16 O National Instruments Corporation Index O Oki MSM82C55A Programmable Peripheral Interface See 82C55A Programmable Peripheral Interface operating environment specifications A 6 operation of AT MIO 16 See theory of operation optional equipment 1 5 to 1 7 optional software 1 4 OUT GATE and SOURCE timing signals 2 38 to 2 42 3 14 to 3 15 3 16 OUT signal 2 24 2 signal 2 24 OUTS signal 2 24 output signal specifications DIO 24 circuitry A 6 overflow and overrun conditions See programming multiple A D conversions MIO 16 P PA7 through PAO signals 2 44 PB7 through PBO signals 2 44 PC AT I O channel interface circuitry 3 2 to 3 4 address decoder circuitry 3 3 address latches 3 3 address lines 3 3 block diagram 3 3 data buffers 3 3 DMA control circuitry 3 4 interrupt control circuitry 3 4 timing signals 3 3 PC7 through PCO signals 2 44 physical specifications A 6 pin assignments 82C55A Programmable Peripheral Interface F 3 Mode 1 strobed input 4 84 Mode 1 strobed output 4 86 Mode 2 bidirectional bus 4 88 Am9513A System Timing Controller E 6 AT MIO 16D I O connector 2 21 D 1 DIO 24 I O connector 2 43 C 1 MIO 16 I O connector 2 22 B 1 polarity bipolar input calibration procedure 5 4 to
309. ration 2 17 AT MIO 16D User Manual Configuration and Installation Chapter 2 Unipolar Output Selection You select the unipolar output configuration for each analog output channel by setting the following jumpers Analog Output Channel 0 W8 B C Analog Output Straight Binary for Channel W10 B C Analog Output Channel 1 W7 B C Analog Output Straight Binary for Channel 1 Wil B C Notice that the straight binary format must be used when in unipolar output mode This configuration is shown in Figure 2 20 U ABC ABC DAC 0 DAC 1 Channel 0 Channel 1 wio wi e ABC ABC Channel 0 Channel 1 Figure 2 20 Unipolar Output Configuration Note If you are using a software package such as LabWindows or NI DAQ you may need to reconfigure your software to reflect any changes in jumper or switch settings RTSI Bus Clock Selection When multiple AT Series boards are connected via the RTSI bus you may want to have all the boards use the same 10 MHz clock This arrangement is useful for applications that require counter timer synchronization between boards Each AT Series board with a RTSI bus interface has an onboard 10 MHz oscillator Thus one board can drive the RTSI bus clock signal and the other boards can receive this signal or disconnect from it AT MIO 16D User Manual 2 18 National Instruments Corporation Chapter 2 Configuration and Installation The configuration for jumper W5 specifies wh
310. rations common mode signal rejection 2 32 to 2 33 differential input floating signal sources 2 29 to 2 30 general considerations 2 27 to 2 28 ground referenced signal sources 2 28 to 2 29 recommended configurations for ground referenced and floating signal sources 2 27 single ended connections floating signal RSE sources 2 30 to 2 31 general considerations 2 30 grounded signal NRSE sources 2 31 to 2 32 input polarity and range configuring 2 12 to 2 14 actual range and measurement precision versus input range selection and gain 2 14 considerations for selecting ranges 2 14 jumper settings 2 13 to 2 14 input signal specifications DIO 24 circuitry A 5 installation See also configuration hardware installation 2 20 unpacking the AT MIO 16 1 5 to 1 7 instrumentation amplifier 2 26 3 6 INT2Clear Register 4 19 National Instruments Corporation Index 13 AT MIO 16D User Manual Index integral nonlinearity specification A 2 internal reference selection 2 15 to 2 16 interrupts configuration 2 7 to 2 8 default settings for National Instrument products 2 3 DIO 24 circuitry interrupt enable settings 2 8 interrupt enable signals for all modes 4 91 interrupt handling 4 90 to 4 91 programming examples 4 89 to 4 90 theory of operation 3 17 PC AT I O channel interface 3 4 programming 4 77 to 4 78 interval channel scanning pseudo simultaneous See multiple A D conversions programming I O connector pin assignments
311. rcuitry 23 AO GND N A Analog Output Ground The analog output voltages are referenced to this node 24 33 DIG GND N A Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply 25 27 ADIO lt 0 3 gt DIGGND Digital I O port A signals 29 31 26 28 BDIO lt 0 3 gt DIGGND Digital I O port B signals 30 32 34 35 5 V DIGGND 5 VDC Source This pin is fused for up to 1 A of 5 V supply 36 SCANCLK DIGGND Scan Clock This pin pulses once for each A D conversion in the scanning modes The low to high edge indicates when the input signal can be removed from the input or switched to another signal 37 EXTSTROBE DIGGND External Strobe Writing to the EXTSTROBE Register results in a minimum 200 nsec low pulse on this pin National Instruments Corporation 2 23 AT MIO 16D User Manual Configuration and Installation Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name START TRIG STOP TRIG EXTCONV SOURCEI GATEI OUTI SOURCE2 GATE2 OUT2 SOURCES GATES OUTS FOUT Reference DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND DIGGND Chapter 2 Description continued External Trigger In posttrigger data acquisition sequences a low to high edge on START TRIG initiates the sequence In pretrigger applica
312. rcuitry 3 6 to 3 7 input multiplexers 3 6 instrumentation amplifier 3 6 mode selection 3 6 analog output circuitry 3 10 to 3 11 block diagram 3 10 data coding 3 11 output range 3 11 AT MIO 16D block diagram 3 1 data acquisition timing circuitry 3 7 to 3 10 AT MIO 16D User Manual Index 24 National Instruments Corporation Index data acquisition circuitry block diagram 3 5 data acquisition rates 3 9 maximum recommended data acquisition rates 3 10 multiple channel scanned data acquisition 3 9 sample counter 3 8 sample interval timer 3 8 single channel data acquisition 3 9 single conversions 3 8 DIO 24 circuitry block diagram 3 17 functional overview 3 17 interrupt control circuitry 3 17 I O connector 3 18 MIO 16 digital I O circuitry 3 11 to 3 13 MIO 16 functional overview 3 1 to 3 2 PC AT I O channel interface circuitry 3 2 to 3 4 RTSI bus interface circuitry 3 15 to 3 16 timing I O circuitry 3 13 to 3 15 time lapse measurements 2 39 to 2 40 timing connections 2 36 to 2 42 data acquisition timing connections 2 36 to 2 38 signal 2 37 EXTSTROBE signal 2 36 to 2 37 SCANCLK signal 2 36 START TRIG signal 2 37 to 2 38 STOP TRIG signal 2 38 general purpose connections 2 38 to 2 42 event counting application with external switch gating 2 39 frequency measurement 2 40 GATE SOURCE and OUT signals 2 38 to 2 42 input and output ratings 2 40 to 2 41 time lapse measurement 2 39
313. rd can be programmed to execute a multiple A D conversion sequence with the following options e A D conversions can be initiated either by pulses generated by the onboard sample interval counter or by pulses applied to the EXTCONV input These pulses control the conversion rate e entire conversion sequence can be started by a software write operation to the board or by a signal applied to the START TRIG input e You select either posttrigger or pretrigger operation In posttrigger operation the sample counter begins decrementing with each conversion pulse once the conversion sequence 1s started When the sample counter reaches zero the conversion sequence terminates Thus all acquired data was received after the trigger or software start In pretrigger operation the sample counter does not decrement until a trigger signal is applied to the STOP TRIG input When the conversion sequence terminates some of the acquired data has been received before the trigger signal and some has been received after this signal The most commonly used configuration is for the onboard sample interval and sample counters to control the entire data acquisition operation Programming this configuration is explained here The other timing configurations are explained in the External Timing Considerations for Multiple A D Conversions section later in this chapter Multiple channel scanning is discussed in the Programming Multiple A D Conversions with Ch
314. right angles to each other e Do not run AT MIO 16D signal lines through conduits that also contain power lines e Protect AT MIO 16D signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running the AT MIO 16D signal lines through special metal conduits MIO 16 Cabling Considerations National Instruments has a cable termination accessory the CB 100 for use with the AT MIO 16D board This kit includes two terminated 50 conductor flat ribbon cables and two 50 pin CB 50 connector blocks You can attach signal I O leads to screw terminals on the connector block and thereby be connected to the AT MIO 16D I O connector The CB 100 is useful for prototyping an application or in situations where AT MIO 16D interconnections are frequently changed Once you develop a final field wiring scheme however you may want to develop your own cable This section contains information and guidelines for design of such a cable AT MIO 16D User Manual 2 50 National Instruments Corporation Chapter 2 Configuration and Installation The 16 circuitry I O connector is a 50 pin female ribbon cable header The manufacturer part numbers for this header are as follows Electronic Products Division 3M part number 3596 5002 T amp B Ansley Corporation part number 609 5007 The mating connector for the MIO 16 circuitry is a 50 position ribbon socket connector polarized with strain relief National Inst
315. ring the output voltage generated with the DAC set at negative full scale 0 This output voltage should be 2 LSB For bipolar output V amp 10 and 1 2 LSB 2 44 mV e For analog output channel 0 a Connect the voltmeter between DACO OUT pin 20 on the I O connector and AOGND pin 23 b Set the analog output channel to 10 V by writing 2 048 to the DAC National Instruments Corporation 5 7 AT MIO 16D User Manual Calibration Procedures Chapter 5 c Adjust trimpot R7 until the output voltage read is 10 V 2 44 mV that is between 10 00244 and 9 99756 V e For analog output channel 1 a Connect the voltmeter between DAC1 OUT pin 21 on the I O connector and AOGND pin 23 b Set the analog output channel to 10 V by writing 2 048 to the DAC c Adjust trimpot R3 until the output voltage read is 10V 2 44 mV that is between 10 00244 and 9 99756 V 2 Adjust the analog output gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full scale 2 047 This output voltage should be 1 2 LSB For bipolar output 9 99512 V and 1 2 LSB 2 44 mV e For analog output channel 0 a Connect the voltmeter between DACO OUT pin 20 on the I O connector and AOGND pin 23 b Set the analog output channel to 9 99512 V by writing 2 047 to the DAC c Adjust trimpot R5 until the output voltage read is 9 99512 V 2 44 mV that is
316. rmed before counting can occur Once armed the counter will count all source edges which occur while the Gate is active and disregard those edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off On each TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting uniti new ARM command is issued 2 129 AT MIO 16D User Manual AMD Am9513A Data Sheet Figure 15b Mode B Waveforms MODE C Hardware Triggered Strobe cara 2 11 10 oms _ x x x x x oms cma 2 cm1 Lojojojilxy x x j xx Mode C shown in Figure 15c is identical to Mode A except that counting will not begin until a Gate edge is applied to the armed counter The counter must be armed before application of the triggered Gate edge Gate edges applied to a disarmed counter are disregarded The counter will start counting on the first source edge after the triggering Gate edge and will continue counting until TC At TC the counter will reload from the Load register and automatically disarm itself Counting will then remain inhibited until a new ARM command and a new Gate edge are applied in that order Note that after application of a triggered Gate edge the Gate input be disregarded for the remainder of the count cycie This differs from Mode B where th
317. rminate 3 When TC is active the counter will always count the next Source edge issued to it even if it is disarmed or gated off during TC This means that TC will never be active for longer than one count period and it may in fact be shorter if a STEP command or a LOAD or LOAD AND ARM command is applied during TC see item 2 above This also means that a counter that is disarmed or stopped on TC is actually disarmed stopped immediately following TC AT MIO 16D User Manual This may cause count sequences different from what a user might expect Since the counter is always reloaded at the start of TC and since it always counts at the end of TC the counter contents following TC will differ by one from the reloaded value irrespective of the operating mode used if the reloaded value was 0001 for down counting 9999 BCD for 8CD up counting or FFFF hex for binary up counting the count at the end of TC will drive the counter into TC again regardless of whether the counter is gated off or disarmed As long as these values are reloaded the TC output wili stay active If a TC Toggled output is selected it will toggle on each Count Execution of a LOAD LOAD AND ARM or STEP command with these counter contents will act the same as application of a source pulse causing TC to remain active and a Toggled output to toggle Count Controi Counter Mode bits CM3 through CM7 specify the various options available for direct control of
318. rmined by the switches at position U61 as shown in Figure 2 1 The switches are set at the factory for the base I O address hex 220 This factory setting is used as the default base I O address value by National Instruments software packages for use with the AT MIO 16D The AT MIO 16D uses the base I O address space hex 220 through 23F with the factory setting Note Verify that this space is not already used by other equipment installed in your computer If any equipment in your computer uses this base I O address space you must change the base I O address of the AT MIO 16D or of the other device If you change the AT MIO 16D base I O address you must make a corresponding change to any software packages you use with the AT MIO 16D Table 2 2 lists the default settings of other National Instruments products for the PC AT For more information about the I O address of your PC AT refer to the technical reference manual for your computer Table 2 2 Default Settings of Other National Instruments Products for the PC DMA Channel Interrupt Level Base I O Address AT A2150 None None 120 hex AT AO 6 10 Channel 5 Lines 11 12 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT DSP2200 None None 120 hex AT GPIB Channel 5 Line 11 2 hex AT MIO 16 Channels 6 7 Line 10 220 hex AT MIO 16D Channels 6 7 Line 5 10 220 hex AT MIO 16F 5 Channels 6 7 Line 10 220 hex AT MIO 16X None None 220 hex AT MIO 64F 5 None None 220 hex GPIB PCII Chan
319. rs are enabled outputting the prefetched data on the bus Since the internal data register is accessed prior to the start of the read operation its access time is transparent to the user To keep the prefetched data consistent with the Data Pointer prefetches are aiso performed after each write to the Data port and after execution of the Load Data Pointer com mand The following rules should be kept in mind regarding Data port Transfers Counter 1 Mode Reg 1 Load Reg Counter 1 Hold Reg Counter 2 Mode Reg Counter 2 Load Reg Counter 2 Hold Reg Alarm Reg 1 ELEMENT CYCLE Alarm Reg 2 Master Mode Reg Status Reg CONTROL GROUP CYCLE STATUS CYCLE LS001240 Figure 9 Data Pointer Sequencing 1 The Data Pointer register should always be reloaded betore reading from the Data port if a command other than Load Data Pointer was issued to the Am9513A following the last Data port read or write The Data Pointer does not have to be loaded again if the first Data port transaction after a command entry is a write since the Data port write will automatically cause a new prefetch to occur 2 Operating modes and X allow the user to save the counter contents in the Hold register by applying an active going gate edge If the Data Pointer register had been pointing to the Hold register in question the pre fetched v
320. rt A in mode 2 Delay Time from the rising edge of WR to the falling edge of Delay Time from the falling edge of ACK to the i rising edge of Delay Time from the faliing edge of STB to the rising edge of IBF Delay Time from the rising edge of RD to the falling edge of IBF Delay Time from the falling edge of RD to the E falling edge of INTR RIT Delay Time from the rising edge of STB to the i rising edge of INTR SIT Deiay Time from the rising edge of ACK to the t rising edge of INTR AMT Delay Time from the falling edge of WR to the wi falling edge of INTR Note Timing is measured at Vi 0 8 and 2 2 V for both input and outputs 332 National Instruments Corporation F 5 AT MIO 16D User Manual Oki MSM82C55A Data Sheet Appendix F rn yO MSM82C55A 2RS GS VJS Basic Input Operation Mode 0 RD Port input CS A4 Ag Basic Output Operation Mode 0 333 AT MIO 16D User Manual F 6 National Instruments Corporation Appendix F Oki MSM82C55A Data Sheet 1 0 MSM82C55A 2RS GS VJS_ amp ____ Strobe Output Operation Mode 1 Port output Bidirectional Bus Operation Mode 2 334 National Instruments Corporation F 7 AT MIO 16D User Manual Oki MSM82C55A Data Sheet Appendix F lt y O MSMB82C55A 2RS GS VJS OUTPUT CHARACTERISTICS REFERENC
321. rumentation amplifier Common mode rejection ratio Input bias current Input offset current Input impedance Gain ranges Gain accuracy includes pot adjustment range gain 1 gain gt 1 Temperature drift National Instruments Corporation 16 single ended 8 differential 12 bit 1 in 4 096 1 5 LSB maximum 0 75 LSB typical 0 5 LSB maximum 1 LSB maximum no missing codes over temperature 0 5 LSB typical worst case codes 10 V 5 V or 0 to 10 V jumper selectable 12 V 7 V for 10 V differential analog input range 9 5 V for 5 V differential analog input range 7 V for 0 to 10 V differential analog input range 75 dB minimum DC through 100 Hz 25 nA maximum 15 nA maximum 1 GQ 1 2 4 and 8 for AT MIO 16DH 1 10 100 and 500 for AT MIO 16DL software selectable 0 83 of full scale voltage adjustable to zero 0 85 of full scale voltage 0 08 of full scale voltage maximum when gain error adjusted to zero at gain 1 36 ppm A 1 AT MIO 16D User Manual Specifications Appendix A Analog Input continued Input offset voltage 50 mV for gain 1 adjustable to zero includes pot adjustment range 25 mV for gain 2 15 mV for gain 4 10 mV for gain 8 5 mV for gain 10 2 mV for gain 100 1 5 mV for gain 500 Temperature drift 160 uV C 6uV C gain Other system offset voltage 85 mV for 10 V range adjustable to zero includes pot adjustment range 45 mV for 5 V range
322. ruments Corporation Chapter 2 Configuration and Installation Instrumentation Floating Amplifier Signal Source Measured Voltage MIO 16 I O Connector AT MIO 16D Board in RSE Configuration Figure 2 29 Single Ended Input Connections for Floating Signal Sources Single Ended Connections for Grounded Signal Sources NRSE Configuration If a grounded signal source is to be measured with a single ended configuration then you must configure the AT MIO 16D in the NRSE input configuration Connect the signal to the positive input of the AT MIO 16D instrumentation amplifier and connect the signal local ground reference to the negative input of the AT MIO 16D instrumentation amplifier The ground point of the signal should therefore be connected to the AI SENSE pin Any potential difference between the AT MIO 16D ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the instrumentation amplifier and this difference is rejected by the amplifier On the other hand if the input circuitry of the AT MIO 16D is referenced to ground such as in the RSE configuration this difference in ground potentials appears as an error in the measured voltage Figure 2 30 shows how to connect a grounded signal source to an AT MIO 16D board configured in the NRSE configuration Configuration instructions are included under the Analog Input Configuration section earlier in this chapter N
323. ruments uses a polarized keyed connector to prevent inadvertent upside down connection to the AT MIO 16D Recommended manufacturer part numbers for this mating connector are as follows Electronic Products Division 3M part number 3425 7650 T amp B Ansley Corporation part number 609 5041CE The following is the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors Electronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 In making your own cabling you may decide to shield your cables The following guidelines may help e For the analog input signals shielded twisted pair wires for each analog input pair yield the best results assuming that differential inputs are used Tie the shield for each signal pair to the ground reference at the source analog lines pins 1 through 23 should be routed separately from the digital lines pins 24 through 50 e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so will result in noise from switching digital signals coupling into the analog signals DIO 24 Cabling Considerations The DIO 24 circuitry of the AT MIO 16D can be interfaced to a wide range of printers plotters test instruments I O racks and modules screw terminal panels and almost any device with a parallel interface The DIO 24 circuitry I O connector is a standard 50 pin header conn
324. ry The following specific events occur Any data acquisition operation in progress is canceled The A D FIFO is emptied The overrun flag is cleared The overflow flag is cleared Any pending CONV interrupt is cleared Any pending DAQSTOP interrupt is cleared Any pending DMATCINT interrupt is cleared Any pending DMA request is cleared Address Base address C hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used AT MIO 16D User Manual 4 14 National Instruments Corporation Chapter 4 Programming External Strobe Register Writing to the External Strobe Register location generates an active low approximately 200 nsec strobe pulse at the EXTSTROBE output at the MIO 16 I O connector This pulse may be useful for several applications including generating external general purpose triggers and latching data into external devices from the digital output port for example Address Base address E hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used National Instruments Corporation 4 15 AT MIO 16D User Manual Programming Chapter 4 Analog Output Register Group Two of the three registers making up the Analog Output Register Group load the two analog output channels DACO controls analog output channel 0 DACI controls analog output channel 1 These DACS are written to individually and the analog output can be updated immediately or each time an activ
325. s a Write FF00 ctr to the Am9513A Command Register to select the Counter Mode Register b Write 0004 to the Am9513A Data Register to store the counter mode value c Write 08 ctr to the Am9513A Command Register to select the Counter Load Register d Write 3 to the Am9513A Data Register to store an inactive count value in the Counter Load Register 6 Load all counters with their Counter Load Register values by writing FF5F to the Am9513A Command Register After this sequence of writes the Am9513A Counter Timer is in the following state e 16 bit mode is enabled BCD scalar division is selected The FOUT signal is turned off All counter OUT output pins are set to high impedance output state e All counters are loaded with a non terminal count value For additional details concerning the Am9513A Counter Timer see Appendix E Am9513A Data Sheet Note If a data acquisition operation is to be executed and Counter 4 of Am9513A is not to be used then write 0000 to the Am9513A Data Register instead of 0004 when ctr 4 Writing 0000 to the Am9513A Data Register causes the output of Counter 4 to be low and therefore prevents improper termination of the data acquisition operation AT MIO 16D User Manual 4 42 National Instruments Corporation Chapter 4 Programming Initializing the Analog Output Circuitry The AT MIO 16D powers up with the analog output circuitry at an unknown voltage For most applications
326. s 2 50 to 2 52 DIO 24 cabling 2 51 to 2 52 field wiring 2 50 MIO 16 cabling 2 50 to 2 51 default settings for National Instrument products 2 3 DMA channel selection 2 5 to 2 7 field wiring considerations 2 50 interrupt selection 2 7 to 2 8 AT MIO 16D User Manual Index 8 National Instruments Corporation Index parts locator diagram 2 2 Configuration and Status Register Group 4 3 to 4 10 Command Register 1 4 4 to 4 5 Command Register 2 4 9 to 4 10 overview 4 3 register map 4 1 Status Register 4 6 to 4 8 continuous channel scanning round robin See multiple A D conversions programming control word formats 82C55A Programmable Peripheral Interface 4 79 Mode 1 strobed output 4 82 to 4 83 Port C set reset control words 4 80 counter block diagram 3 14 counters resetting See resetting hardware after data acquisition counter timer See Am9513A System Timing Controller timing I O circuitry Counter Timer Register Group See Am9513 Counter Timer Register Group custom cables 1 6 customer communication vii G 1 D DACO OUT signal 2 23 2 33 to 2 34 DACO Register 4 17 OUT signal 2 23 2 33 to 2 34 DACI Register 4 18 data acquisition programming continuous channel scanning round robin enabling 4 61 overflow and overrun conditions 4 61 to 4 62 servicing 4 61 to 4 62 controlling with EXTCONV signal servicing 4 56 to 4 57 interval channel scanning pseudo simultaneous enabling 4 67 servicin
327. s National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53 02 MS 53 02 Austin TX 78730 5039 512 794 5678 Index Numbers Symbols 5 V power pins warning against connecting 2 36 2 44 5 V signal 2 23 2 44 82C55A Programmable Peripheral Interface data sheet absolute maximum ratings F 4 AC characteristics F 5 basic functional description F 9 basic input operation F 6 basic output operation F 6 bidirectional bus operation F 7 circuit configuration F 2 control logic F 10 control word setting F 10 DC characteristics F 4 features F 2 functional description of pin F 9 general description F 2 Group A different in mode from Group B F 16 interrupt control function F 11 Mode 0 basic input output operation F 11 Mode 1 strobe bidirectional operation F 14 to F 15 Mode 1 strobe input output operation F 12 to F 14 operating range F 4 operational description F 10 to F 17 output characteristics reference value F 8 pin configuration F 3 Port C status read F 16 reset F 16 strobe input operation F 6 strobe output operation F 7 modes of operation 3 18 to 3 19 Mode 0 3 18 Mode 1 3 19 Mode 2 3 19 programming DIO 24 4 80 to 4 89 interrupt programming examples 4 89 to 4 90 Mode 0 basic I O 4 80 to 4 81 possible configurations 4 81 programming example 4 81 to 4 82 Mode 1 strobed input 4 82 to 4 84 pin assignments 4 84 National Instruments Corporatio
328. s an input acknowledge signal ACK input Acknowledge Input A low signal on this handshaking line indicates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the AT MIO 16D OBF output Output Buffer Full A low signal on this handshaking line indicates that data has been written from the selected port INTR output Interrupt Request This signal becomes high when the 82C554 is requesting service during a data transfer The appropriate DIO interrupt enable bits must be set to generate this signal National Instruments Corporation 2 45 AT MIO 16D User Manual Configuration and Installation Name Type RD internal WR internal DATA bidirectional AT MIO 16D User Manual Chapter 2 Description continued Read Signal This signal is the read signal generated from the control lines of the PC Write Signal This signal is the write signal generated from the control lines of the PC Data Lines at the Selected Port This signal indicates when the data on the data lines at a selected port is or should be available 2 46 National Instruments Corporation Chapter 2 Configuration and Installation DIO 24 Mode 1 Input Timing The following are the timing specifications for an input transfer in Mode 1 Name Description Minimum Maximum Tl STB Pulse Width 500 2 STB 0 to IBF 1 300 T3 Data before STB 1 0
329. s an output in Mode 1 while inp portc amp 0x02 Wait until OBFB is set indicating that the data last written to Port B has been read outp portb 0x34 Write the data to Port B AT MIO 16D User Manual 4 86 National Instruments Corporation Chapter 4 Programming Mode 2 Bidirectional Bus Mode 2 has a bidirectional 8 bit bus that can transfer both input and output without changing the configuration The data transfers are synchronized with handshaking lines in Port C in a manner similar to that of Mode 1 This mode uses only Port A however Port B can be used in either Mode 0 or Mode 1 while Port A is configured for Mode 2 Interrupt generation and enable and or disable functions are also available Other features of this mode include the following Used in Group A only Port A and upper nibble of Port C 8 bit bidirectional port Port A and a 5 bit control status port Port e Latched inputs and outputs The control word written to the DIO 24 CNFG Register to configure Port as a bidirectional data bus in Mode 2 is shown as follows If Port B is configured for Mode 0 then PC2 PCI and PCO of Port C can be used as extra input or output lines doi 6 5 4 3 2 1 0 Port C PC2 PC0 1 input 0 output Port B 1 input 0 output Group B Mode 0 Mode 0 1 Mode 1 During a Mode 2 data transfer the status of the handshaking lines and interrupt signals can be o
330. s and the appropriate part numbers for this mating connector are as follows Electronic Products Division 3M part number 3425 7650 T amp B Ansley Corporation part number 609 5041CE The standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors is as follows Electronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 If you plan to use the DIO section of the AT MIO 16D for a communications application you may need shielded cables to meet FCC requirements The DIO section I O bracket has been designed so that the shield of the I O cable can be grounded through the computer chassis when a mating connector such as the following is used AMP Special Industries part number 2 746483 2 Many varieties of shielded ribbon cable are available to work with the mating connector listed previously One type of shielded cable encloses a standard ribbon cable with a shielded jacket Recommended manufacturers and the appropriate part numbers for this type of cable are as follows Belden Electronic Wire and Cable number 9L28350 T amp B Ansley Corporation part number 187 50 AT MIO 16D User Manual 2 52 National Instruments Corporation Chapter 3 Theory of Operation This chapter contains a functional overview of the AT MIO 16D and explains the operation of each functional unit making up the AT MIO 16D MIO 16 Functional Overview The block diagram in Figure 3 1 is a
331. s as pulse and clock generation timed control of laboratory equipment and frequency event and pulse width measurement With all these functions on one board you can automatically monitor and control laboratory processes The additional digital I O of the AT MIO 16D DIO 24 circuitry is useful for a wide range of digital VO applications With the DIO 24 circuitry and I O connector you can interface a PC to any of following Other computers Another PC with a National Instruments PC DIO 24 AT DIO 32F or AT MIO 16D IBM Personal System 2 with a National Instruments MC DIO 24 or MC DIO 32F Apple Macintosh II or Quadra with a National Instruments NB DIO 24 or NB DIO 32F Any other computer with an 8 bit or 16 bit parallel interface e Centronics compatible printers and plotters e Panel meters Instruments and test equipment with BCD readouts and or controls e Opto isolated solid state relays SSRs and I O module mounting racks AT MIO 16D User Manual 1 2 National Instruments Corporation Chapter 1 Introduction With the AT MIO 16D the PC can serve as a digital I O system controller for laboratory testing production testing and industrial process monitoring and control The AT MIO 16D is interfaced to the National Instruments RTSI bus With this bus National Instruments AT Series boards can send timing signals to each other The AT MIO 16D can send signals from the onboard counter timer to another board or
332. s boards the AT MIO 16 and the PC DIO 24 The AT MIO 16D contains two logical sections the MIO 16 circuitry and the DIO 24 circuitry The MIO 16 circuitry contains a 12 bit ADC with up to 16 analog inputs two 12 bit DACS with voltage outputs eight lines of transistor transistor logic TTL compatible digital I O and three 16 bit counter timer channels for timing I O The DIO 24 circuitry is a 24 bit parallel digital I O interface based on an 82C55A programmable peripheral interface PPI If you require signal conditioning or additional analog inputs you can use the SCXI signal conditioning modules the SCXI multiplexer products or the AMUX 64T multiplexer board Organization of This Manual The AT MIO 16D User Manual is organized as follows e Chapter 1 Introduction describes the AT MIO 16D lists the contents of your AT MIO 16D kit the optional software and optional equipment and explains how to unpack the AT MIO 16D e Chapter 2 Configuration and Installation describes the AT MIO 16D jumper configuration installation of the AT MIO 16D board into the PC signal connections to the AT MIO 16D board cable wiring and handshake timing diagrams for the DIO 24 circuitry of the AT MIO 16D Chapter 3 Theory of Operation contains a functional overview of the AT MIO 16D and explains the operation of each functional unit making up the AT MIO 16D e Chapter 4 Programming discusses the programming of the AT MIO 16D Included in this c
333. s complete the ADC clocks the result into the A D FIFO The A D FIFO is 12 bits wide and 512 words deep This FIFO serves as a buffer to the ADC and provides two benefits Any time an A D conversion is complete the value is saved in the A D FIFO for later reading and the ADC is free to start a new conversion Secondly the A D FIFO can collect up to 512 A D conversion values before any information is lost thus software or DMA has extra time 512 times the sample interval to catch up with the hardware If more than 512 values are stored in the A D FIFO without the A D FIFO being read from an error condition called A D FIFO overflow occurs and A D conversion information is lost The A D FIFO generates a signal that indicates when it contains A D conversion data You can read the state of this signal from the AT MIO 16D Status Register You can use this signal to generate a DMA request signal or to generate an interrupt Sign extension circuitry at the A D FIFO output adds four most significant bits MSBs bits 15 through 12 to the 12 bit FIFO output bits 11 through to produce a 16 bit result The sign extension circuitry is software programmable to generate either straight binary numbers or two s complement numbers In straight binary mode bits 15 through 12 are always zero and provide a range of 0 to 4 095 In two s complement mode the MSB of the 12 bit ADC result bit 11 is inverted and extended to bits 15 through 12 providing a range of
334. s configured to control eight input channels This configuration is shown in Figure 2 9 n w ABC Input Mode Figure 2 9 DIFF Analog Input Configuration Factory Setting Considerations in using the DIFF analog input configuration are discussed in the Signal Connections section later in this chapter Figure 2 26 shows a schematic diagram of this configuration RSE Analog Input 16 Channels RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the AT MIO 16D board The negative input of the differential input amplifier is tied to the analog ground This configuration is useful when measuring floating signal sources See the Types of Signal Sources section later in this chapter for more information With this input configuration the AT MIO 16D can monitor 16 different analog input signals You select the RSE analog input configuration by setting jumpers W6 and W9 as follows W6 AISENSE is tied to the negative input of the instrumentation amplifier C D Thenegative input of the instrumentation amplifier is tied to the instrumentation amplifier signal ground G H Multiplexer outputs are tied together into the positive input of the instrumentation amplifier 9 B C Multiplexer control is configured to control 16 input channels This configuration is shown in Figure 2 10 Figure 2 10 RSE Analog Input Configuration
335. s manner untii a DISARM command is issued to the counter Frequency shift keying may be obtained by specifying a TC Toggled output mode in the Counter Mode register The switching of frequencies is achieved by modulating the Gate Am9513A E 24 Appendix E National Instruments Corporation Appendix AMD Am9513A Data Sheet DU AVAVAVAVAUAVAWAUAUAUAUAG jase care ARRAY XA AX 5 TUE RS UM Figure 15s Mode 5 Waveforms wx AYYY OX AXOQUQOQQ WF004760 Figure 15v Mode V Waveforms Am9513A 2 139 National Instruments Corporation E 25 AT MIO 16D User Manual AMD Am9513A Data Sheet LPP ALS PN P PPPs on TT NNNM UNNNNNSNNN TM MODE X Hardware Save available in Am9513A onty cms 4 3 12 1 comto oms x x x x x Mode X as shown in Figure 15x provides a hardware sampling of the counter contents without interrupting the count A LOAD AND ARM command or a LOAD command followed by an ARM command is required to initialize the disregarded After application of the Triggering Gate edge the counter will count ail qualified source edges until the first TC irrespective of the gate level All gate edges applied during the counting sequence will store the current count in the Hold regis
336. sample run OVERFLOW is an error condition that occurs if the FIFO fills up with A D conversion data and A D conversions continue If OVERFLOW is set A D conversion data has been lost because of FIFO overflow If OVERFLOW is cleared no overflow has occurred If OVERFLOW occurs during a data acquisition operation the data acquisition is terminated immediately This bit can be reset by writing to the A D Clear Register This bit indicates whether an A D conversion was initiated before the previous A D conversion was complete OVERRUN is an error condition that may occur if the data acquisition sample interval is too small sample rate is too high If OVERRUN is set one or more conversions were skipped If OVERRUN is cleared no overrun condition has occurred If OVERRUN occurs during a data acquisition operation the data acquisition is terminated immediately This bit can be reset by writing to the A D Clear Register These two bits show the current gain setting for the programmable gain amplifier see Mux Gain Register later in this chapter This bit indicates the current DMA channel If DBDMA in Command Register 1 is set dual DMA mode is selected In this mode DMA transfers switch between two DMA channels DMACH indicates which DMA channel is currently in use for DMA operation If DMACH is cleared then DMA 1 is in use If DMACH is set then DMA 2 is in use In single DMA mode only DMA 1 is used This bit indicates the state of mult
337. se signals are explained under the Data Acquisition Timing Connections section later in this chapter Pins 41 through 50 carry general purpose timing signals provided by the onboard Am9513A Counter Timer These signals are explained under the General Purpose Timing Signal Connections section later in this chapter Data Acquisition Timing Connections The data acquisition timing signals are SCANCLK EXTSTROBE START TRIG STOP TRIG EXTCONV SCANCLK is an output signal that generates a high to low edge whenever an A D conversion begins SCANCLK pulses only when scanning is enabled on the AT MIO 16D SCANCLK is normally high and pulses low for approximately 1 usec after the A D conversion begins The low to high edge signals that the input signal has been acquired This signal can be used to clock external analog input multiplexers The SCANCLK signal is driven by one LS TTL gate A low pulse is generated on the EXTSTROBE pin when the External Strobe Register is loaded see the External Strobe Register section in Chapter 4 Programming Figure 2 33 shows the timing for the EXTSTROBE signal tw approx 200 nsec Figure 2 33 EXTSTROBE Signal Timing AT MIO 16D User Manual 2 36 National Instruments Corporation Chapter 2 Configuration and Installation The pulse is typically 200 nsec in width The EXTSTROBE signal be used by an external device to latch signals or trigger events The EXTSTROBE signal is an LS TTL sign
338. sed by that channel Analog output configuration instructions are included under the Analog Output Configuration section earlier in this chapter The following ranges and ratings apply to the EXTREF input Useful input voltage range 10 V peak with respect to AO GND Absolute maximum ratings 25 V peak with respect to AO GND Pin 23 AO GND is the ground reference point for both analog output channels and for the external reference signal Figure 2 31 shows how to make analog output connections and the external reference input connection to the AT MIO 16D board If neither channel is configured to use an external reference signal do not connect anything to the EXTREF pin National Instruments Corporation 2 33 AT MIO 16D User Manual Configuration and Installation Chapter 2 External Reference Signal Optional Analog Output Channels MIO 16 I O Connector AT MIO 16D Boar Figure 2 31 Analog Output Connections The external reference signal can be either a DC or an AC signal This reference signal is multiplied by the DAC code to generate the output voltage The DACs in the analog output channels are rated for 82 dB total harmonic distortion with a 1 kHz 6 Vrms sine wave reference signal and with the DACs set at their maximum full scale digital value Digital I O Signal Connections Pins 24 through 32 of the MIO 16 I O connector are digital I O signal pins associated with the MIO 16 circuitry of the AT MIO 16D board
339. selects the correct load source on the CM15 CM13 001 through 111 and CM7 x 0 This p activa source edge SWITCHING TEST CIRCUIT This test circuit is the dynamic of Teradyne J941 Am9513A 2 151 National Instruments Corporation E37 AT MIO 16D User Manual Am9513A Data Sheet Appendix E SWITCHING WAVEFORMS Tem TEMWM Temen NOTE 2 quoted NOTE 5 i i TWMGV f Br s Q p C 7 NOTE ores COUMT NOTE 7 GATE INPUT NOTE 10 WF004792 Figure 21 Bus Transfer Switching Waveforms Figure 22 Counter Switching Waveforms 2 152 Am9513A AT MIO 16D User Manual E 38 National Instruments Corporation terne er eei eR repr e Appendix E AMD Am9513A Data Sheet APPENDIX A Design Hints 1 When a crystal is not being used X1 and X2 should be connected as shown for TTL input Figure A1 and no input Figure A2 2 Recommended oscillator capacitor values are 18 pF on X1 and X2 3 Unused inputs should be tied to VCC 4 The TC output can glitch when the counter is loaded For this reason this output should not be connected to edge sensitive interrupts The counter output should be set or cleared after the LOAD command 5 The two most significant bits of the status register are Specified They may be zero or one 6 The mode register s
340. should be configured as an input pin AT MIO 16D User Manual 4 12 National Instruments Corporation Chapter 4 Programming Start DAQ Register Writing to the Start DAQ Register location initiates a multiple A D conversion data acquisition operation Note Several other pieces of AT MIO 16D circuitry must be set up before a data acquisition run can occur See the Programming Multiple A D Conversions on a Single Input Channel section later in this chapter Address Base address A hex Type Write only Word Size 16 bit Bit Map Not applicable no bits used Note Multiple A D conversion data acquisition operations can be initiated in one of two ways by writing to the Start DAQ Register or by detecting an active low signal on the START TRIG signal The START TRIG signal is connected to pin 38 on the MIO 16 I O connector and to the A6 pin of the RTSI bus switch If START TRIG is driven low by either of these sources it prevents the Start DAQ Register from initiating a multiple A D conversion data acquisition operation If the Start DAQ Register is to initiate multiple A D conversions any signal connected to pin 38 of the I O connector should be in a high impedance or high state and the A6 pin of the RTSI bus switch should not be driven low National Instruments Corporation 4 13 AT MIO 16D User Manual Programming A D Clear Register Chapter 4 Writing to the A D Clear Register location clears the data acquisition circuit
341. sitive true input polarity No gating Output Controi Counter mode bits CMO through CM2 specify the output control configuration Figure 17 shows a schematic represen tation of the output control logic The OUT pin may be off a high impedance state or it may be inactive with a low impedance to ground The three remaining valid combinations represent the active high active low or TC Toggle output waveforms One output form available is called Terminal Count TC and represents the period in time that the counter reaches an equivalent value of zero TC will occur on the next count when the counter is at 0001 for down counting at 9999 BCD for BCD up counting or at FFFF hex for binary up counting Figure 18 shows a Terminal Count pulse and an exampie context that generated it The TC width is determined by the period of the counting source Regardless of any gating input or whether the counter is Armed or Disarmed the terminal count will go active for only one clock cycie Figure 18 assumes active high source polarity counter armed counter decrementing and an external reload value of K The counter will always be loaded from an external location when TC occurs the user can choose the source location and the value if a non zero value is picked the counter will never really attain a zero state and TC will indicate the counter state that would have been zero had no parallel transfer occurred Appendix E 2 1
342. st and third the signal a 2 GATES 1 which the measurements start and end Signal abbrevia eee tions used are S Chip Select CS A Address C D W Write WR C Clock X2 Y Output OUT1 OUTS D Data in 15 Am9513A Unit a aja a a a a a a a a a a ja ajajata a a a a a aj8 a a a a u a a a 8 8 8 2 8 2 149 National Instruments Corporation 5 AT MIO 16D User Manual AMD Am9513A Data Sheet Appendix E SWITCHING CHARACTERISTICS over MILITARY operating range for SMD DESC and APL Products Group A Subgroups 9 10 11 are tested unless otherwise noted Paramet ma TAVWH C O Valid to Write High O O OOOO O O O Valid to Waite C D Valid to Write High O _ _ _ _ ___ _ ___ 4 3 TCHCH X2 High to X2 High X2 Period Note i 346 X2 High to X2 Low X2 High Pulse Width Note 13 000 TCLCH Low to X2 High X2 Low Pulse width Note 33 39 TOWH Data in to W e Hgh 89 Count Source High to Count Source High Source Cycie Time Note 7 145 Count Source Pulse Duration Note 7 Count Source High to FOUT Valid Nowe 7 so Count Source Hi Vaid Loval Rod Tiraj Te TAERE Coum Source High io Read Low Setup 2 7 S
343. start the counter Figure 15h Mode H Waveforms Am9513A 2 133 AT MIO 16D User Manual E 19 National Instruments Corporation AMD Am9513A Data Sheet yt Ae ROR RY AU AVAT AV AT AUAT AU AY UI ESAE ERK RR Figure 15i Mode Waveforms MODE J Variable Duty Cycle Rate Generator with No Hardware Gating CMts 14 3 12 10 cmo ome cus cus ows cuz e 3 3 x X Dx Ex Tx Mode J shown in Figure 15j will find the greatest usage in frequency generation applications with variable duty cycle requirements Once armed the counter will count continuously until it is issued a DISARM command On the first TC the Counter will be reloaded from the Hold register Counting will then proceed until the second TC at which time the counter will be reloaded from the Load register Counting wiil continue with the reload source alternating on each TC until a DISARM command is issued to the counter The third TC reloads from the Hold register the fourth TC reloads from the Load register etc A variable duty cycle output can be generated by specifying the TC Toggied output in the Counter Mode register The Load and Hold values then directly contro the output duty cycle with high resolution available when relatively high count vaiues are used 2 134 AT MIO 16D User Manual MODE K Variable Duty
344. struments Corporation Chapter 4 Programming MIO 16 Programming Considerations This chapter contains programming instructions for operating the MIO 16 circuitry on the AT MIO 16D board Programming the AT MIO 16D involves writing to and reading from the various registers on the board The programming instructions list the sequence of steps to take The instructions are language independent that is they instruct you to write a value to a given register to set or clear a bit in a given register or to detect whether a given bit is set or cleared without presenting the actual code Register Programming Considerations Several write only registers on the AT MIO 16D contain bits that control several independent pieces of the onboard circuitry In the instructions for setting or clearing bits specific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to these registers simultaneously affects all register bits You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and write the software copy to the register Initializing the MIO 16 Circuitry of the AT MIO 1
345. t INTE of group A is set when the bit for PC is set while INTEg of group B is set when the bit for PC is sat Following is a description of the output opera i tion of mode 1 Output buffer full flag output This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU This sig nal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK Acknowledge input This signal when turned to low level indicates that the terminal has received data INTR interrupt request output This is the signal used to interrupt the CPU when terminal receives data from the CPU via the MSMB2C554A 5 it indicates the occurrence of the interrupt in high level only when the inter nal INTE flip flop is set This signal tums to high level at the rising edge of the ACK 1 at this time and low level at the falling edge of WR when the INTEg is set INTE of group A is set when the bit for PC is set while INTEg of group B is set when the bit for PC is set Mode 1 output I INTE Ay 339 AT MIO 16D User Manual F 12 National Instruments Corporation Appendix F Oki MSM82C55A Data Sheet 1 0 MSM82C55A 2RS GS VJS_ Port C Function Allocation in Mode 1 Combination of Input Output Group A input Group A input Group A Output Group A Output Group B input Grou
346. t for a 1 in the least significant bit write the most significant 16 bits to the Am9513A Data Register to store the Counter 5 load value e Otherwise add 1 to the most significant 16 bits of the sample count and write that value to the Am9513A Data Register to store the Counter 5 load value l Write FF70 to the Am9513A Command Register to load and arm Counter 5 m Setthe 16 32 CNT bit in Command Register 1 to notify the hardware that both Counters 4 and 5 will be used as the sample counter After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and Counter 5 increments every time Counter 4 reaches zero The data acquisition operation is terminated when both Counters 4 and 5 reach zero and the last entry in the mux gain memory is served National Instruments Corporation 4 65 AT MIO 16D User Manual Programming Chapter 4 4 Program the scan interval counter Use Counter 2 of the Am9513A Counter Timer as the scan interval counter Counter 2 can be programmed to generate a pulse once every N counts N is referred to as the scan interval that is the time between successive scan sequences programmed into the mux gain memory N can be between 2 and 65 536 One count is equal to the period of the timebase clock used by the counter The following clocks are available internal to the Am9513A 1 MHz 100 kHz 10 kHz 1 kHz and 100 Hz In addition the scan interval timer
347. tal I O lines while the DIO 24 circuitry provides 24 lines of digital I O discussed later in this chapter The eight lines of digital I O from the MIO 16 circuitry are divided into two ports of four lines each and are located at pins ADIO lt 3 0 gt and BDIO lt 3 0 gt on the I O connector Figure 3 5 shows a block diagram of the digital I O circuitry National Instruments Corporation 3 11 AT MIO 16D User Manual Theory of Operation Chapter 3 ADIO lt 3 0 gt Digital Output Register DOUTO ENABLE DO REG WR DOUT DATA lt 7 4 gt BDIO lt 3 0 gt Digital Output Register DOUT1 ENABLE A Digital DATA lt 7 0 gt cm E e gt o e Q PC AT I O Channel 4 B EXTSTROBE EXT STROBE WR Figure 3 5 Digital I O Circuitry Block Diagram The digital I O lines are controlled by the Digital Output Register and monitored by the Digital Input Register The Digital Output Register is an 8 bit register that contains the digital output values for both ports 0 and 1 When port 0 is enabled bits lt 3 0 gt in the Digital Output Register are driven onto digital output lines ADIO lt 3 0 gt When port 1 is enabled bits lt 7 4 gt in the Digital Output Register are driven onto digital output lines BDIO lt 3 0 gt Reading the Digital Input Register returns the state of the digital I O lines Digital I O lines ADIO lt 3 0 gt are connected to bits lt 3 0 gt of the Digital Input Register Digital I O l
348. te this offset you must apply V fs 1 2 LSB to the analog input circuitry and adjust a trimpot until the ADC returns readings that flicker between its most negative count and the most negative count plus one The voltages corresponding to and 1 LSB are given in the following table All the stages up to and including the input of the ADC contribute to the gain error of the analog input circuitry With the instrumentation amplifier set to a gain of 1 the gain of analog input circuitry is ideally one The gain error is the deviation of the gain from 1 and appears as a multiplication of the input voltage being measured To calibrate this offset you must apply 3 2 LSB to the analog input circuitry and adjust a potentiometer until the ADC returns readings that flicker between its most positive count and the most positive count minus one The voltages corresponding to and 1 LSB are given below The voltages corresponding to V_ which is the most negative voltage that the ADC can read 1 which is the most positive voltage the ADC can read and 1 LSB which is the voltage corresponding to one count of the ADC depend on the input range selected The value of these voltages for each input range is given in this table 10 to 10 V 9 99512 V 5 to 5 V 4 99756 V Oto 10 V 9 99756 V National Instruments Corporation 5 3 AT MIO 16D User Manual Calibration Procedures Chapter 5 Board Configuration Calibration
349. ter but they will not interrupt the counting sequence On each TC the counter wili be reloaded from the Load register and stopped Subsequent counting requires a new triggering Gate edge counting resumes on the first source edge following the triggering Gate edge Note Mode X is only available in the Am9513A devices COUNTER MODE CONTROL OPTIONS Each Counter Logic Group includes 16 bit Counter Mode CM register used to control all of the individual options available with its associated general counter These options include output configuration count control count source and gating control Figure 16 shows the bit assignments for the Counter Mode registers This section describes the control options in detail Note that generaily each counter is indepen dently configured and does not depend on information outside its Counter Logic Group The Counter Mode register should be loaded only when the counter Disarmed Attempts to load the Counter Mode register when the counter is armed may resuit in erratic counter operation XX Figure 15x Mode X Waveforms After power on reset or a Master Reset command the Counter Mode registers are initialized to a preset condition The value entered is 0800 hex and results in the following control configuration Output low impedance to ground Count down Count binary Count once Load register selected No retriggering F1 input source selected Po
350. th 0 5 m ribbon cable 776366 05 with 1 0 m ribbon cable 776366 10 with 2 0 m ribbon cable 776366 20 AT Series RTSI bus cables for 2 boards 776249 02 3 boards 776249 03 4 boards 776249 04 5 boards 776249 05 Cable adapter board for signal conditioning SC 2050 without cable 776335 90 SC 2051 without cable 776335 91 SC 2060 optically isolated digital input board with conductor cable 776336 00 776336 10 SC 2061 optically isolated digital output board with 26 conductor cable 776336 01 776336 11 SC 2062 electromechanical relay digital control board with 26 conductor cable 776336 02 776336 12 General purpose termination breadboard SC 2070 without cable 776358 90 SC 2072 without cable 776358 92 SC 2072D without cable 776358 192 BNC 2080 BNC adapter board without cable 776579 90 Digital signal conditioning modules SSR Series mounting rack and 1 0 m cable 24 channel without cable 776290 924 16 channel without cable 776290 9 16 8 channel without cable 776290 908 8 channel with SC 205X cable 776290 18 National Instruments Corporation 1 5 AT MIO 16D User Manual Introduction Chapter 1 Custom Cables The AT MIO 16D I O connector is a 100 pin male ribbon cable header The manufacturer part number National Instruments uses for this header is as follows e Robinson Nugent part number PSOE 100P1 SR1 TG The mating connector for the board is a 100 position polarized ribbon socket connector This connector breaks out into two 50
351. the DIO 24 PORTA Register can be written to in order to control the eight digital I O lines constituting Port A See DIO 24 Circuitry Programming Considerations later in this chapter for information on how to configure Port A for input or output Address Base address 0x00 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 L Dg qp p ops poo 1 Bit Name Description 7 0 D lt 7 0 gt These eight bits are written to or read from Port A National Instruments Corporation 4 37 AT MIO 16D User Manual Programming Chapter 4 DIO 24 PORTB Register Reading the DIO 24 PORTB Register returns the logic state of the eight digital I O lines constituting Port B of the DIO 24 circuitry that is PB lt 7 0 gt If Port B is configured for output the DIO 24 PORTB Register can be written to in order to control the eight digital I O lines constituting Port B See 82C55A Programming Considerations later in this chapter for information on how to configure Port B for input or output Address Base address 0x01 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 L Dg FR p ops poo 1 Bit Name Description 7 0 D lt 7 0 gt These eight bits are written to or read from Port B AT MIO 16D User Manual 4 56 National Instruments Corporation Chapter 4 Programming DIO 2
352. the desired sample count is greater than 65 536 both Counters 4 and 5 must be used Sample Counts 2 through 65 536 To program the sample counter for sample counts up to 65 536 use the following programming sequence The minimum permitted sample count is two All writes are 16 bit operations All values given are hexadecimal a Write FF04 to the Am9513A Command Register to select the Counter 4 Mode Register b Write 1025 to the Am9513A Data Register to store the Counter 4 mode value c Write FFOC to the Am9513A Command Register to select the Counter 4 Load Register d Write the sample count value to the Am9513A Data Register to store the Counter 4 load value Ifthe sample count is between 2 and FFFF 65 535 decimal write the sample count minus 1 to the Am9513A Data Register Ifthe sample count is 10000 65 536 decimal write 0 to the Am9513A Data Register Write FF48 to the Am9513A Command Register to load Counter 4 Write FFF4 to the Am9513A Command Register to decrement Counter 4 Write FF28 to the Am9513A Command Register to arm Counter 4 Clear the 16 32 CNT bit in Command Register to notify the hardware that only Counter 4 will be used as the sample counter AT MIO 16D User Manual 4 64 National Instruments Corporation Chapter 4 Programming After you complete this programming sequence Counter 4 is configured to count A D conversion pulses generated by Counter 3 and turns off the data acquisition op
353. the fields labeled A6 through AO and B6 through BO are the 4 bit control fields for each RTSI switch pin of the same name The 4 bit control field for pin AO is shown in Figure 4 1 The bits labeled S2 through SO are the signal source selection bits for the pin One of seven source signals can be selected Pins A6 through AO can select any of the pins B6 through BO as signal sources Pins B6 through BO select any of the pins through as signal sources For example the pattern 011 for S2 through SO in the AO control field selects the signal connected to pin B3 as the signal source for pin AO The bit labeled OUTEN is the output enable bit for that pin If the OUTEN bit is set the pin is driven by the selected source signal the pin acts as an output pin If the OUTEN bit is cleared the pin is not driven regardless of the source signal selected instead the pin can be used as an input pin If the AO control field above contains the pattern 0111 the signal connected to pin B3 Trigger Line 3 appears at pin AO On the AT MIO 16D board this arrangement allows the EXTCONV signal to be driven by Trigger Line 3 Conversely if the B4 control field contains the pattern 1011 the signal connected to pin A5 appears at pin B4 This arrangement allows Trigger Line 4 to be driven by the AT MIO 16D signal In this way boards connected via the RTSI bus can send signals to each other over the RTSI bus trigger lines National Instrumen
354. the new AT MIO 16D base I O address for use when configuring the AT MIO 16D software a form is provided for you in Appendix G Customer Communication Table 2 3 lists the possible switch settings the corresponding base I O address and the base I O address space used for that setting AT MIO 16D User Manual 2 4 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 3 Switch Settings with Corresponding Base I O Address and Base I O Address Space Switch Setting Base I O Address Base I O Address A9 8 7 A6 5 hex Space Used hex 000 00 100 120 140 160 180 1A0 1 0 1 0 200 240 25F 260 27F 280 29F 2A0 2BF 2 0 2DF 2 0 2FF 300 31F 320 33F 340 35F 360 37F 380 39F 3A0 3BF 3DF 3E0 3FF This setting is the factory default setting DMA Channel Selection The DMA channel used by the AT MIO 16D is selected by jumpers on W12 as shown in Figure 2 1 The AT MIO 16D is set at the factory to use DMA channels 6 and 7 for dual DMA mode These are the default DMA channels used by the AT MIO 16D software handler Verify that these DMA channels are not also used by equipment already installed in your computer If any device uses DMA channel 6 and or channel 7 change the DMA channel used by either the AT MIO 16D or the other device The DMA channels supported by the AT MIO 16D hardware are channels 5 6 and 7 Notice that these are the three 16 bit channe
355. through hardware To initiate the data acquisition operation through software write to the Start Register To initiate the data acquisition operation through hardware apply an active low pulse to the START TRIG pin on the AT MIO 16D I O connector See the Data Acquisition Timing Connections section in Chapter 2 Configuration and Installation for START TRIG signal specifications Once the trigger is applied Counter 3 generates pulses initiating A D conversions once every sample interval until the sample counter reaches 0 and the last scan cycle is completed Counter 2 generates a scan interval for each cycle through the scan sequence in the mux gain memory 8 Service the data acquisition operation Once the data acquisition operation is started by application of a trigger the operation is serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Read the Status Register 16 bit read b If the CONVAVAIL bit is set bit 13 read the A D FIFO Register to obtain the result Interrupts or DMA can also be used to service the data acquisition operation These topics are discussed later in this chapter Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should b
356. tinuous channel scanning round robin 4 59 to 4 60 interval channel scanning pseudo simultaneous 4 64 to 4 65 pretriggering with STOP TRIG signal 4 52 to 4 54 single channel 4 48 to 4 49 sample interval counter programming continuous channel scanning round robin 4 58 to 4 59 interval channel scanning pseudo simultaneous 4 63 to 4 64 pretriggering with STOP TRIG signal 4 52 single channel 4 47 to 4 48 scan interval counter programming 4 66 SCANCLK signal 2 23 2 36 3 9 servicing data acquisition operation See data acquisition programming sign extension circuitry 3 7 signal connections analog input signal connections 2 25 to 2 26 instrumentation amplifier 2 26 pin descriptions 2 25 to 2 26 warning against exceeding input ranges 2 25 analog output signal connections 2 33 to 2 34 cabling considerations 2 50 to 2 52 DIO 24 cabling 2 51 to 2 52 field wiring 2 50 MIO 16 cabling 2 50 to 2 51 digital I O signal connections 2 34 to 2 36 DIO 24 I O connector pin 2 43 to 2 49 Mode 1 input timing 2 47 Mode 1 output timing 2 48 Mode 2 bidirectional timing 2 49 pin assignments 2 43 Port C pin assignments 2 44 to 2 45 power connections 2 44 signal descriptions 2 44 timing specifications 2 45 to 2 46 field wiring considerations 2 50 input configurations common mode signal rejection 2 32 to 2 33 differential connections floating signal sources 2 29 to 2 30 general considerations 2 27 to 2 28 grounded signal s
357. tion 82C55A Programmable Peripheral Interface The 82C55A PPI is the heart of the AT MIO 16D DIO 24 circuitry This chip has 24 programmable I O pins that represent three 8 bit ports PA PB and PC Each port can be programmed as an input or an output port The 82C55A has three modes of operation simple I O Mode 0 strobed I O Mode 1 and bidirectional I O Mode 2 In Modes 1 and 2 the three 8 bit ports are divided into two groups Group A and Group B two groups of twelve signals One 8 bit configuration or control word determines the mode of operation for each group The Group A control bits configure Port A AO through A7 and the upper 4 bits nibble of Port C C4 through C7 The Group B control bits configure Port B BO through B7 and the lower nibble of Port C CO through C3 Modes 1 and 2 use handshaking signals from Port C to synchronize data transfers Refer to Chapter 4 Programming or to Appendix Oki MSM82C55A Data Sheet for more detailed information 82C55A Modes of Operation The three basic modes of operation for the 82C55A are as follows e Mode 0 Basic I O e Mode 1 Strobed I O e Mode 2 Bidirectional bus The 82C55A also has a single bit set reset feature for Port C The 8 bit control word also a as this function For additional information refer to Appendix F Oki MSM82C55A Data Mode 0 This mode can be used for simple input and output operations for each of the ports No handshaking is required data
358. tions the low to high edge of START TRIG initiates pretrigger conversions while the STOP TRIG signal initiates the posttrigger sequence Stop Trigger In pretrigger data acquisition the high to low edge of STOP TRIG initiates the posttrigger sequence External Convert A high to low edge on EXTCONV causes an A D conversion to occur If EXTGATE or EXTCONV is low conversions are inhibited SOURCEI This pin is from Am9513A Counter 1 signal This pin is from the Am9513A Counter 1 signal OUTPUT This pin is from Am9513A Counter 1 signal SOURCE2 SOURCES This pin is from the Am9513A Counter 2 signal GATE2 This pin is from the Am9513A Counter 2 signal OUTPUT This pin is from the Am9513A Counter 2 signal SOURCES This pin is from the Am9513A Counter 5 signal GATES This pin is from the Am9513A Counter 5 signal OUTS This pin is from the Am9513A Counter 5 signal Frequency Output This pin is from the Am9513A FOUT signal The signals on the connector can be classified as analog input signals analog output signals digital I O signals digital power connections or timing I O signals Signal connection guidelines for each of these groups are given as follows AT MIO 16D User Manual 2 24 National Instruments Corporation Chapter 2 Configuration and Installation Analog Input Signal Connections Pins 1 through 19 of the MIO 16 I O connector are analo
359. tions allow level sensitive gating or edge initiated gating Other gating modes are available inciuding one that allows the Gate input to select between two counter output frequencies All gating functions may aiso be disabled The active Gate input conditioned by an auxiliary input when the unit is operating with an external 6 bit data bus See Data description Schmitt trigger circuitry on the GATE inputs allows slow transition times to be used Source The Source inputs provide external signals that may be counted by any of the counters Any Source lino may be routed to any or of the counters and the FOUT divider The active polarity for a selected SRC input is programmed at each counter Any duty cycle waveform will be accepted as long as tha minimum pulse width is at least half the period of the maximum specified counting frequency for the part Schmitt trigger circuitry on the SRC inputs allows slow transition times to be used OUT1 OUTS Counter Each 3 state OUT signal is directly associated with a corresponding individuat counter Docencia an me urns nities Ee redondas sad Aara Wars ee cycle waveform OUT pulse polarities are individually programmable The output circuitry detects the counter state that would have been all bits zero in the absence of a reinitialization That information is used to generate the selected waveform type An optional output mode for Counters 1 and 2 overrides the normai output mo
360. to 2 40 timing signals 2 38 to 2 42 pins for 2 36 timing I O circuitry block diagram 3 13 counter block diagram 3 14 timing I O specifications A 5 timing signals PC AT I O channel interface 3 3 timing specifications DIO 24 circuitry 2 45 to 2 49 Mode 1 input timing 2 47 Mode 1 output timing 2 48 Mode 2 bidirectional timing 2 49 signals 2 45 to 2 46 transfer rate specifications DIO 24 circuitry A 6 trigger applying continuous channel scanning round robin 4 61 interval channel scanning pseudo simultaneous 4 67 pretriggering multiple A D conversions 4 54 National Instruments Corporation Index 25 AT MIO 16D User Manual Index single input channel 4 50 two s complement mode A D conversion values 4 45 factory settings 2 17 U unipolar input calibration procedure 5 5 to 5 6 unipolar output analog output circuitry 3 11 calibration procedure 5 8 configuration 2 18 unpacking the AT MIO 16 1 7 AT MIO 16D User Manual Index 26 O National Instruments Corporation
361. trol 0 Enable increment 1 Disable increment Sealer Control 0 Binary Owision 1 SCD Division wre z Disabled 12 Time of Dey Mode 00 TOD Disabisc 01 TOD Enabled 5 input 10 TOD Enabisd 6 input 11 TOD Enabled 10 input DF001913 Figure 11 Master Mode Register Bit Assignments Time of Day Bits MMO and MM1 of the Master Mode register specify the Time of Day TOD options When MMO 0 and MM1 0 the special logic used to implement TOD is disabled and Count ers 1 and 2 will operate in exactly the same way as Counters 3 4 and 5 When MMO 1 or MM1 1 additional counter decoding and contro logic is enabled on Counters 1 and 2 which causes their decades to turn over at the counts that generate appropriate 24 hour TOD accumulations For addi tional information see the Time of Day chapter in the 9513A System timing controller technical manual Comparator Enable Bits MM2 and control the Comparators associated with Counters 1 and 2 When a Comparator is enabled its output is substituted for the normal counter output on the associated QUT1 or OUT pin The comparator output will be active high if the output control field of the Counter Mode register is 001 or 010 and active fow for a code of 101 Once the compare output is true it will remain so until the count changes and the comparison therefore goes false The two Comparators can always be used individually in any
362. trumentation amplifier bias currents charge up stray capacitances resulting in uncontrollable drift and possible saturation in the amplifier Typically values from 10 kQ to 100 kQ are used National Instruments Corporation 2 29 AT MIO 16D User Manual Configuration and Installation Chapter 2 A resistor from each input to ground as shown in Figure 2 28 provides bias current return paths for an AC coupled input signal This solution although necessary for AC coupled signals lowers the input impedance of the analog input channel In addition the input offset current of the instrumentation amplifier contributes a DC offset voltage at the input The amplifier has a maximum input offset current of 15 nA and a typical offset current drift of 20 pA C Multiplied by the 100 kQ resistor this current contributes a maximum offset voltage of 1 5 mV and a typical offset voltage drift of 2 uV C at the input Keep this in mind when you observe DC offsets with AC coupled inputs If the input signal is DC coupled then you only need the resistor connecting the negative signal input to ground This connection does not lower the input impedance of the analog input channel Single Ended Connection Considerations Single ended connections are those in which all AT MIO 16D analog input signals are referenced to one common ground The input signals are tied to the positive input of the instrumentation amplifier and their common ground point is ti
363. ts Corporation 4 75 AT MIO 16D User Manual Programming Chapter 4 To program the RTSI switch complete these steps 1 Calculate the 56 bit pattern based on the desired signal routing a Clear the OUTEN bit for all input pins and for all unused pins b Specify the signal source pin for all output pins by setting bits S2 through SO to the source pin number c Set the OUTEN bit for all output pins 2 Fori 0to 55 do the following a Copy bit i of the 56 bit pattern to bit 0 of an 8 bit temporary variable b Write the temporary variable to the RTSI Switch Shift Register 8 bit write 3 Write 0 to the RTSI Switch Strobe Register 8 bit write This operation loads the 56 bit pattern into the RTSI switch At this point the new signal routing goes into effect Step 2 above can be completed by simply writing the low order eight bits of the 56 bit pattern to the RTSI Switch Shift Register then shifting the 56 bit pattern right once and repeating this two step operation a total of 56 times Only bit 0 of the word written to the RTSI Switch Shift Register is used The higher order bits are ignored Programming DMA Operations The AT MIO 16D can be programmed so that the A D FIFO generates a DMA request signal every time one or more A D conversion values are stored in the A D FIFO There are two DMA modes single channel transfer and dual channel transfer In single channel mode one DMA channel is used The DMA channel is selected by the on
364. tware select able active high or active low input polarity Both hardware and software gating of each counter is available Three state Outputs for each counter provide either pulses or levels The counters can be programmed to count up or down in either binary or BCD The accumulated count may be read without disturbing the counting process Any of the counters may be internally concatenated to form an effective counter length of up to 80 bits The Am9513A block diagrams indicate the interface signals and the basic of information internal control lines and the internal data bus have been omitted The control and data registers are all connected to a common internal 16 bit bus The external bus may be 8 or 16 bits wide in the 8 bit mode the internal 16 bit information is multiplexed to the low ord data bus pins DBO through DB7 An internal oscillator provides a convenient source of frequen cies for use as counter inputs The osciliator s frequency is controlled at the X1 and X2 interface pins by an external reactive network such as a crystal The oscillator output is divided by the Frequency Scaler to provide several sub frequencies One of the scaled frequencies or one of ten input Signals may be selected as an input to the FOUT divider and then comes out of the chip at the FOUT interface pin The STC is addressed by the extemal system as two locations a Control port and a Data port The Control port Figure 4 Counter L
365. ty Storage Environment Temperature Relative humidity AT MIO 16D User Manual 1 6 A typical at 5 VDC 13 3 in by 3 9 in 100 pin male separable into two 50 pin female ribbon cable connectors 0 to 70 C 5 to 90 noncondensing 55 to 150 C 5 to 90 noncondensing A 6 National Instruments Corporation Appendix 16 I O Connector This appendix describes the pinout and signal names for the MIO 16 50 pin I O connector of the AT MIO 16D AI GND ACHO ACHI ACH2 ACH3 ACHA 5 6 ACH7 AI SENSE DACI OUT AO GND ADIOC ADIOI ADIOZ ADIO DIG GND 5 V EXTSTROBE STOP TRIG SOURCEI OUTI GATE2 SOURCES OUTS AI GND ACH8 ACH9 10 11 12 ACH13 14 15 DACO OUT EXTREF DIG GND BDIOO BDIOI BDIO2 BDIO3 5 SCANCLK START TRIG EXTCONV GATEI SOURCE2 OUT2 GATES FOUT Figure B 1 AT MIO 16D MIO 16 I O Connector National Instruments Corporation AT MIO 16D User Manual MIO 16 I O Connector Pin 1 2 3 18 19 20 21 22 23 24 33 25227 29 31 26 28 30 32 34 35 36 37 Signal Name AI GND lt 0 15 gt AI SENSE DACO OUT DAC1 OUT EXTREF AO GND DIG GND ADIO lt 0 3 gt BDIO lt 0 3 gt 5 SCANCLK EXTSTROBE AT MIO 16D User Manual Reference N A AIGND AIGND AOGND AOGND AOGND N A N A DIGGND DIGGND DIGGND DIGGND DIGG
366. uisition Rate 100 ksamples sec 100 ksamples sec 70 ksamples sec 20 ksamples sec Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A D Clear Register External Timing Considerations for Scanned Data Acquisition After you follow the programming instructions listed previously under External Timing Considerations for Multiple A D Conversions complete these additional steps 1 Set up the analog channel and gain sequence as given above 2 Set the SCANEN bit in Command Register 1 3 Set the multiplexer counter to 0 before starting the data acquisition operation Resetting the Hardware after a Data Acquisition Operation After a data acquisition operation is complete if no errors occurred and the sample count was less than or equal to 10000 hex then the AT MIO 16D is left in the same state as it was at the beginning of the data acquisition operation The counters do not need to be reprogrammed another data acquisition operation begins when a trigger is received If the next data acquisition AT MIO 16D User Manual 4 66 National Instruments Corporation Chapter 4 Programming operation requires the counters to be programmed differently the Am9513A counters that were used must be disarmed and reset Resetting Counter 2 To reset Counter 2 use the following programming sequence All writes are 16 bit operations All values given are hexadecimal 1 Write FFC2 to the Am9513A Command Registe
367. urrently selected In single ended mode the analog input channel selected is determined by the value of MA lt 2 0 gt if MUXOEN is set and by the value of MA lt 2 0 gt 8 if MUXIEN is set In DIFF mode two analog input channels are selected simultaneously The two channels are MA lt 2 0 gt and MA x2 0 8 4 8 National Instruments Corporation Chapter 4 Programming Command Register 2 Command Register 2 contains 10 bits that control AT MIO 16D interrupts digital output drivers and scan modes used by the data acquisition circuitry Address Base address 2 hex Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTEN INT2EN LDAC SCN2 A4RCV A4DRV A2RCV A2DRV Bit Name Description 15 10 X Don t care bits 9 DOUTENI This bit enables and disables driving of the 4 bit MIO 16 digital output port 1 by the MIO 16 Digital Output Register If DOUTENT is set the MIO 16 Digital Output Register drives the digital lines If DOUTENI is cleared the MIO 16 Digital Output Register drivers are set to a high impedance state thereby allowing an external device to drive the digital lines 8 DOUTENO This bit enables and disables driving of the 4 bit MIO 16 digital output port 0 by the MIO 16 Digital Output Register If DOUTENO is set the MIO 16 Digital Output Register drives the digital lines If DOUTENO is cleared the MIO 16 Digital Output Register drivers are set to a high impedance state thereby
368. ut calibration 5 3 to 5 6 bipolar input calibration procedure 5 4 to 5 5 board configuration 5 4 unipolar input calibration procedure 5 5 to 5 6 analog output calibration 5 8 bipolar output calibration procedure 5 7 to 5 8 board configuration 5 7 unipolar output calibration procedure 5 8 equipment requirements 5 1 trimpots 5 2 channel scanning continuous round robin See multiple A D conversions programming channel scanning interval pseudo simultaneous See multiple A D conversions programming channel selection circuitry 3 6 to 3 7 clearing A D circuitry See A D circuitry clearing clearing analog input circuitry See analog input circuitry Command Register 1 4 4 to 4 5 Command Register 2 4 9 to 4 10 common mode signal rejection considerations 2 32 to 2 33 configuration See also installation jumper settings signal connections analog input configuration 2 10 to 2 14 DIFF differential input 2 10 to 2 11 input mode 2 10 input polarity and range 2 12 to 2 14 NRSE input 16 channels 2 12 RSE input 16 channels 2 11 to 2 12 analog I O jumper settings 2 8 to 2 9 analog output configuration 2 15 to 2 18 bipolar output selection 2 16 to 2 17 external reference 2 15 internal reference 2 15 to 2 16 polarity selection 2 16 to 2 18 RTSI bus clock selection 2 18 to 2 20 unipolar output selection 2 18 base I O address selection 2 3 to 2 5 board configuration 2 1 AT bus interface 2 1 cabling consideration
369. ut lines from Port C 7 6 5 4 3 2 1 0 During a Mode 1 data read transfer the status of the handshaking lines and interrupt signals can be obtained by reading Port C The Port C status word bit definitions for an input transfer are shown as follows The following are the Port C status word bit definitions for input Port A and Port B 7 6 5 4 3 2 1 0 Bit Name Description 7 6 VO Extra I O status lines when Port A is in Mode 1 input 5 IBFA Input buffer full for Port A High indicates that data has been loaded into the input latch for Port A 4 INTEA Interrupt enable bit for Port A Enables DIO interrupts from the 82C55A for Port A Controlled by bit set reset of 3 INTRA Interrupt request status for Port A When INTEA is high and IBFA is high this bit is high indicating that a DIO interrupt request is asserted 2 INTEB Interrupt enable bit for Port B Enables DIO interrupts from the 82 55 for Port B Controlled by bit set reset of PC2 1 IBFB Input buffer full for Port B High indicates that data has been loaded into the input latch for Port B 0 INTRB Interrupt request status for Port B When INTEB is high and IBFB is high this bit is high indicating that a DIO interrupt request is asserted At the digital I O connector Port C has the following pin assignments when in Mode 1 input Notice that the status of STBA and STBB are not included in the Port C status word National Instruments Corporation 4 83 AT
370. ut signals Exceeding the maximum input voltage rating may result in damage to the AT MIO 16D board and to the PC AT National Instruments is not liable for any damages resulting from any such signal connections Connection of analog input signals to the AT MIO 16D depends on the configuration of the AT MIO 16D analog input circuitry and the type of input signal source The different AT MIO 16D configurations allow the AT MIO 16D instrumentation amplifier to be used in different ways Figure 2 26 shows a diagram of the AT MIO 16D instrumentation amplifier National Instruments Corporation 2 25 AT MIO 16D User Manual Configuration and Installation Chapter 2 Instrumentation Amplifier Measured Voltage Vm Vig Vig GAIN Figure 2 26 AT MIO 16D Instrumentation Amplifier The AT MIO 16D instrumentation amplifier applies gain common mode voltage rejection and high input impedance to the analog input signals connected to the AT MIO 16D board Signals are routed to the positive and negative inputs of the instrumentation amplifier through input multiplexers on the AT MIO 16D The instrumentation amplifier converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the AT MIO 16D ground The AT MIO 16D ADC measures this output voltage when it performs A D conversions signals must be re
371. utput which generates a transient pulse which can clearly be active high or active low the TC Toggled output waveform only flips the state of the output on each TC The sole criterion of whether the TC Toggled output is active high or active low is the level of the output at the start of the count cycle This can be controlled by the Set and Clear Output commands See Figure 19 TC Terminal Count On each Terminal Count TC the counter will reload itseif from the Load or Hold register TC is defined as that period of time when the counter contents would have been zero had no reload occured Some special conditions apply to counter operation immediately before and during TC 1 In the clock cycle before TC an internal signal is generated that commits the counter to go to TC on the next count and retriggering by a hardware Gate edge Modes and or a software LOAD or LOAD AND ARM command will not extend the time to TC Note that the next count driving the counter to TC can be caused by the application of a count source edge in level gating modes the edge must occur while the gate is active or it will be disregarded by the application of a LOAD or LOAD AND ARM command see 2 below or by the appiication of a STEP command 2 If a LOAD or LOAD AND ARM command is executed during the cycle preceding TC the counter will immediately go to TC if these commands are issued during TC the TC state will immediately te
372. vertently exceeded You should use this fuse only after the cause of the initial problem is known so as not to blow the spare fuse as well Port C Pin Assignments The signals assigned to Port C depend on the mode in which the 82 55 is programmed In Mode O0 Port C is considered two 4 bit I O ports In Modes 1 and 2 Port C is used for status and handshaking signals with two or three I O bits mixed in Table 2 11 summarizes the signal assignments of Port C for each programmable mode See Chapter 4 Programming for programming information AT MIO 16D User Manual 2 44 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 11 Port C Signal Assignments Programming Mode Mode 1 Input IBFa STBA STBp IBFBp Mode 1 Output OBFA ACKA INTRA INTRB Indicates that the signal is active low Timing Specifications This section lists the timing specifications for handshaking with the DIO 24 circuitry The handshaking lines STB and IBF synchronize input transfers The handshaking lines OBF and ACK synchronize output transfers The following signals are used in the timing diagrams that follow Name Type Description STB input Strobe Input A low signal on this handshaking line loads data into the input latch IBF output Input Buffer Full A high signal on this handshaking line indicates that data has been loaded into the input latch This i
373. w 12 to be individually set or cleared directly without chang ing any other Master Mode bits After power up or reset FOUT is gated on When changing the FOUT divider ratio FOUT source transient pulses as short as half the period of the FOUT source may appear on the FOUT pin Tuming the FOUT gate on or off can also generate a transient This should be considered when using FOUT as a system clock source Am9513A Appendix E National Instruments Corporation Appendix E Bus Width Bit MM13 controls the multiplexer at the data bus interface in order to configure the part for an 8 bit or 16 bit external bus The internal bus is always 16 bits wide When MM13 1 16 bit data is transterred directly between the internal bus and 16 of the external bus lines In this configuration the Byte Pointer bit in the Data Pointer register remains set at ail times When MM13 0 16 bit internal data is transferred a byte at a time to and from the eight low order external data bus lines The Byte Pointer bit toggles with each byte transfer in this mode When the Am9513A is set to operate with an 8 bit data bus width pins 088 through DB15 are not used for the data bus and are available for other functions Pins 0813 through DB15 should be tied high Pins DB8 through DB12 are used as auxiliary gating inputs and are labeled GATE1A through GATESA respectively The auxiliary gate pin GATENA is togically ANDed with the gate input
374. will be the load register instead of the hold ragister To avoid this issue a software dummy load to the counter immediately after the disarm command 14 in the down counting mode of the 9513 if a 0001 is loaded into the counter and another LOAD COUNTER command is issued the TC of that counter will go active If the load register contents are subsequently changed and the counter armed the first clock edge will cause the new load register contents to transfer into the counter and the next clock edge will decrement the counter and make it go out of TC 15 Glitches on CS just before the RD or WR pulse may cause the part to behave incorrectly 16 Timing parameters TGVEH amp TEHGV must not be vio lated Figure A4 shows a method 1 Registers not being programmed correctly Check READ or WRITE recovery time 2 Setup and hold problems observed in synchronous systems Try switching from positive edge to negative edge triggering TCO04080 812 68 10 R2 is a function of Driver Circuitry to meet X2 VIH 3 8 V X2 ViL 08V Figure A1 Crystal input Configuration Am9513A National Instruments Corporation 2 153 AT MIO 16D User Manual Am9513A Data Sheet Appendix E TC002000 Figure A2 Crystai input Configuration WF023981 Figure A3 TEHWH TGVWH Timing Diagram GATE GATE Am9513A TC004100 Figure A4 GATE SRC Configuration Suggestion 2454 Am9513A AT MIO 16D User M
375. witch MIO 16 I O Connector AT MIO 16D Boar Figure 2 32 Digital I O Connections National Instruments Corporation 2 35 AT MIO 16D User Manual Configuration and Installation Chapter 2 In Figure 2 32 port A is configured for digital output and port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2 32 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2 32 Power Connections Pins 34 and 35 of the MIO 16 I O connector provide 5 V from the PC AT power supply These pins are referenced to DIG GND and can be used to power external digital circuitry Power rating 1 Aat 5 10 Warning These 5 power pins should not be directly connected to analog digital ground or to any other voltage source on the AT MIO 16D or any other device Doing so can damage the AT MIO 16D and the PC AT National Instruments is not liable for damages resulting from such a connection A spare MIO 16 fuse is provided in case the power rating is inadvertently exceeded You should use this fuse only after the cause of the initial problem is known so as not to blow the spare fuse as well Timing Connections Pins 36 through 50 of the MIO 16 I O connector are connections for timing I O signals Pins 36 through 40 carry signals used for data acquisition timing The
376. ws Vout Vref digital code 2 048 2 048 where V efis the reference voltage applied to the analog output channel The digital code in the above formula is a decimal value ranging from 0 to 4 095 The formula for the voltage output versus digital code for a bipolar analog output configuration in two s complement form is as follows Vout Vref digital code 2 048 where V efis the positive reference voltage applied to the analog output channel The digital code in the above formula is a decimal value ranging from 2 048 to 2 047 Table 4 6 Analog Output Voltage Versus Digital Code Bipolar Mode Digital Code Straight Binary Two s Complement Voltage Output 0 0 10 V Vref 2 047 9 9951 V 2 048 Vref 5 V 2 Vref 2 048 0 Vref 2 048 Vref 5 2 Vref 2 047 9 9951 2 048 Programming MIO 16 Digital I O Circuitry The digital input circuitry is controlled and monitored using the MIO 16 Digital Input Register the MIO 16 Digital Output Register and the two bits DOUTOEN and DOUTIEN in Command Register 2 See the register bit descriptions earlier in this chapter for more information AT MIO 16D User Manual 4 72 National Instruments Corporation Chapter 4 Programming To enable digital output port 0 set the DOUTOEN bit in Command Register 2 To enable digital output port 1 set the DOUTIEN bit in Command Register 2 When a digital output port is enabled the contents of the MIO 16 Di

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