STM32L152D-EVAL evaluation board
Contents
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4. 23 2 20 4 24 2204 Runmode saa beban aah bh uq aca dom d 24 2202 Low power mode tee 25 2 20 3 Ibias current measurement procedure 26 3 COMNEGIONS osse ba RP xd d E E WR AE EE reu 27 2 59 Doc ID 022868 Rev 2 ky UM1521 Contents 3 1 RS 232 connector CNT ues osa dioec m E 27 3 2 Power connectorCN2 27 3 3 TFT LCD connectorCN4 27 3 4 Daughterboard extension connector CN5 10 28 3 5 LCD glass daughterboard connectors CN6 and 7 31 3 6 ST LINK V2 programming connector 32 3 7 ST LINK V2 USB type B connector CN14 32 3 8 JIAG connector CNTG mo comes kena has kasqa 32 3 9 Trace debugging connector CN11 33 3 10 Audio jack an so men od ena Ca p s 33 3 11 MicroSD connector CN3 34 3 12 Analog input output 2 pin connectorCN8 34 3 13 User USB type B connector 15 35 3 14 RF EEPROM daughterboard connector 12 35 4 Schematics Da 36 Appendix
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6. 5 ZHMO Kouenbe 250 ano LT EN ES t HO T SIN LAOGPODTOA TFLNS M Ka n GqA a c 201 IXNOQ99DIOATPLNS ESA LI 2 v vO HANAA8 66XVW 6IN 39 59 Doc ID 022868 Rev 2 UM1521 Schematics Figure 24 JTAG and Trace ad ITCENLS 5 59 JOJOSUUOD 284 4 gt I e 4 bid Gad 4JOJOSUUOD OVI 93d 02 02 sor sen 61 ST Orla ZI Z 1 I I er T TH v N Ti vrl 6 6 8 E 8 AAN LI 9 9 5 if Y Y B 9INO AQT 10 01 I HSL TINO V N very AAS ena a s if l ISA v NIV NT NIEW NI DIEN DE Doc ID 022868 Rev 2 40 59 Schematics RS 232 and LCD UM1521 Figure 25
7. Table 34 STM32L152D EVAL I O assignment continued Pin No Pin name STM32L152D EVAL I O assignment 138 BOOTO BOOTO 139 PB8 SEG16 AUDIO RF Temp SCL 140 PB9 COM3 AUDIO RF Temp SDA 141 PEO SEG36 BLNO 142 PE1 SEG37 BLN1 143 VSS 3 GND 144 VDD 3 VDD Doc ID 022868 Rev 2 UM1521 Mechanical dimensions AppendixB Mechanical dimensions Figure 36 Mechanical dimension MS30022V1 Table 35 Mechanical dimensions Symbol Size mm Symbol Size mm Symbol Size mm A 68 58 e 72 363 P2 84 455 al 2 54 H 11 P3 115 247 a2 2 54 h 12 Q1 24 13 a3 2 54 Lx 5 715 Q2 26 67 B 17 78 Ly 5 715 Q3 24 792 C 36 Mx 17 145 X 114 3 D 3 5 My 20 32 Y 172 72 d 3 2 P1 18 415 Doc ID 022868 Rev 2 57 59 Revision history UM1521 Revision history Table36 Document revision history Date Revision Changes 30 Mar 2012 1 Initial release Updated Section 2 19 Display and input devices and added Table 21 03 Jul 2012 2 Added Table 1 Applicable products Figure 34 LCD glass daughter board MB979 and Figure 35 TFT LCD daughter board MB895 Added note in Section 2 18 Temperature sensor 58 59 Doc ID 022868 Rev 2 ky UM1521 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes cor
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9. qi 4 1 2 Demonstration software 4 1 3 Order Code se vc Lam EG EEG RE ese 4 1 4 Delivery recommendations 5 2 Hardware layout and configuration 6 2 1 Development and debug support 8 2 2 Power SUPPLY 2 2 Det E qawa ew cep bien an 9 2 3 Clocksource 11 24 Reset source 11 2 5 BOO ODIOM sei uzun s a a a ats a pse unha 12 2 6 LCD glass module 13 27 OA 17 28 SB Seong usnu an 17 2 9 RS 232 and IrDA an aa RR NES 17 210 Touch sensing slider isse 19 MicroSD CSI cua Mana sc sikta s uiw S CORE RE ES is 19 22127 Sernal EEPROM bia ou bae Mee wasata 20 23 REEEPROM oan aa MAAN 20 204 bsc asya pataka pagakuq d hua 20 235 NOR Flasi u zu yaa al ni ua uama amauta KUE 20 215 JAnaloggipil sos aces Dab PRESE ERES eRe eer eee ni 21 2 17 Comparator 21 2 18 Temperature sensor 22 219 Display and input devices
10. 5G 41 4 4G COM5 19 18 17a 16a 15a 14a 12a 11 10a 9 8 7 6 199 186 179 166 156 146 126 115 100 8b 70 COM7 S 7D Q6 04 6D Q5 5D Q4 40 03 4 COMB nA 7K 7L 6K 6L 5K 5L mA 4K 141 Table 13 LCD glass segments mapping table pins 37 48 Pin 37 38 39 40 41 42 43 44 45 46 47 48 COM1 3N 3E 2J 2N 2E 1J 1N 1E 2 P2 2C 2M P1 1C 1M t COMS 3H 3F 2B 2H 2F 1B 1H 1F 3A 3G 21 2 26 11 1 19 COM5 4 2 1 S3 S1 COM5 COME 6b 5b 4b 3b 2b 1b S4 52 COM6 COM7 3D Q2 C1 2D Q1 S5 1D COM7 8 C2 2K 2L S6 1K 1L COM8 ky Doc ID 022868 Rev 2 15 59 Hardware layout and configuration UM1521 Figure 6 LCD segment names 000000000 0000000000 0000000000 lt 00000000001 Ex 00000090000 00000000061 0000000006 ES mE E mm B Em mum E E E _ E __ nnt su Em r1 16 59 Doc ID 022868 Rev 2 ky UM1521 Hardware layout and configuration 2 7 2 8 2 9 Audio The STM32L152D EVAL evaluation board supports stereo audio play by using an audio DAC CS43L22 connected to bot
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12. UM1521 User manual STM32L152D EVAL evaluation board Introduction The STM32L152D EVAL evaluation board is a complete demonstration and development platform for the ARM Cortex M3 core based STM32L152ZDT6 microcontroller from STMicroelectronics featuring two 1205 three SPIs five USARTs 12 bit ADC 12 bit DAC LCD driver internal 48 KB SRAM and 384 KB Flash touch sensing USB FS LCD controller FSMC and JTAG debugging support This board can be used as reference design for user application development but it is not considered as final application The full range of hardware features on the board helps you evaluate all peripherals USB FS USART audio DAC microphone ADC dot matrix LCD LCD glass IrDA LDR SRAM NOR Flash MicroSD Card temperature sensor and so on and develop your own applications Extension headers make it possible to easily connect a daughterboard or wrapping board for your specific application An ST LINK V2 is integrated on the board as embedded in circuit debugger and programmer for the STM32 MCU Figure 1 STM32L152D EVAL evaluation board This user manual applies to the products listed in Table 1 Table 1 Applicable tools Type Part numbers Evaluation tools STM32L152D EVAL July 2012 Doc ID 022868 Rev 2 1 59 www st com Contents UM1521 Contents 1 OVerVieW eno etr dod a o oa Mb 4 1 1 liuc c EMT das
13. 0 ANY ANY LO gt SSTA stia 99 9 Zi 018 Ss 55 Ain 40joeuuo OVTFOGV AN ECRIRE EN he gt gt sq31 i 85 uo 85015 i BU es 4 T i wy I 089 PE v N 1 rg TG 4 1 1 0152 LdITOLESL pou ovaoav gt 18 1 gt 159 VLIN gt e RES TA OT 4 T 1 pas E 015 ead 0 Dn 5 4 1 A EI v t 44 59 Schematics UM1521 Power Figure 29 r z bL 30 9155 10MOd 9 LICEWLS foot fiuoor 19001 feoor 10001 NOW S21u0J 29 90J9IIN 1S ani 4 TZEWLS 992 CA VAI 5 11 SSA NOW Jno A68S FCL CEC D SC I M0A SSA 0001 ori HEN S E LEO ey BS Sep 1 I I LSSA LOTA 9 SSA 9 GGA SSSA S ddA FSSA QdA ESSA ddA
14. 51085 6955 9 sc irapa ER s 15 820 t u 159 H Iman 01 02 61 6 21985 90045 05 61 asi 6 8L LI or 61985 56045 6 SE EE 8 91 SI 1995 vCOSS 8 91 SI SEO I 6085 52048 9 Z ep 01985 Tuas 9 ci 6 06 1985 12088 5 o 6 s 4 cp NOD VINOO 8 L aa 9 gp SWOO n c 9 s pe ip 9500 97100 caos El El Zz I a LWOO 88 CEN TED lt 50 59 Doc ID 022868 Rev 2 ky Schematics UM1521 TFT LCD daughter board MB895 Figure 35 t 4 I L jo KHOS HOd O ew Ss688W qumN 19 91 10 45 1 uoddns 407 YoU p Z S91U01 9913049IIN LS gage SISISIS sals g ln zzz uoypoyddo 101428 145 40 22uu07 2 5 E z ara LI LI Lx Lx Li i raul eau or 6 E g 9 10120110 dS ANOTA 19 49000 91
15. F96gA19qumN IYATGCSI 5 nu 6 soqos 404 n Wawainseow quouomseour Gar n 15 NIT 13 n 220110 20 CIUS USE PN VUS USUL PNVIS n Ht QYS VAN ZEZSA AIT 5854 OPS ASON n now 1012 103390000 uorsuonx n 2OGHOS HSY H JWyiosussue IdSWWONdCH POs suL n ooquos orpny 20AWS JOPHIS qono L Yono Doc ID 022868 Rev 2 36 59 Schematics UM1521 v paS ZLOZIEIZ 8 eW F96giviequnN IVAS QCSTTCEW LS enr S21U04129J 90J9 IN 1S Audio Figure 21 37 59 god uo NOW 25019 4 TAL IH LOFLCOOH 000 9051 5O2 4dosI 880 Id LTA 417700 4 085 gt te 6 0 5 9 N A 45007 8 SLI 14 6 7 SAC dng ang 51 S 68d UM1521 Schematics Extension connector Figure 22 1 jo 9245
16. Table 10 Table 11 Table 12 and Table 13 and segment names are given in Figure 6 Table10 LCD glass segments mapping table pins 1 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 COM1 COM1 1g 2g 3g 4g 5g 6g 7g 8g COM2 COM2 1h 2h 3h 4h 5h 6h 7h 8h COM3 COM3 li 2i 3i 4i 8i COM4 1 2 3j 4j 5j 6j 7j 8j COM5 1d 2d 3d 4d 5d 7d 8d COM6 1 2 3c 4c 5c 6c 7c 8 COM7 1e 2e 3e 4e 7 8 COM8 1f 2f 3f 4f 5f 6f 7f 8f Table 11 LCD glass segments mapping table pins 13 24 Pin 13 14 15 16 17 18 19 20 21 22 23 24 99 100 119 129 13g 149 15g 16g 17g 18g 19g 5J COM2 9h 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 5C COM3 9i 10i 111 121 13i 14i 15i 16i 171 18i 19i 5B 9 10 11j 12j 13j 14j 15j 16j 17j 18j 19 5 5 94 10d 11d 12d 13d 14d 15d 16d 17d 18d 19d 13a COME 9 10 11c 12c 13c 14c 15c 16c 17c 18c 19c 13b 7 10 116 12 13 14e 15e 16 17e 18 19 01 8 Of 10f 11f 12f 13f 14f 15f 16f 17f 18f 19f O2 14 59 Doc ID 022868 Rev 2 UM1521 Hardware layout and configuration Table12 LCD glass segments mapping table pins 25 36 Pin 25 26 27 28 29 30 31 32 33 34 35 36 COM1 7 7N 7E 6J 6N 6E 5N 5E 4J 4N 4 3 COM2 7C 7M P6 6C 6M P5 5M P4 4C 4M P3 3C COM3 7 7H 7F 68 6H 6F 5H 5F 4B 4H 4 38 71 7G 6
17. Table 17 NOR Flash related jumpers Jumper Description Write protection is enabled when JP9 is fitted while write protection is disabled when JP9 is JP9 not fitted Default setting Not fitted The LCD glass module has to be mounted on IO position for NOR Flash usage Refer to Section 2 6 LCD glass module for detail Doc ID 022868 Rev 2 ky UM1521 Hardware layout and configuration 2 16 2 17 Analog input A 2 pin connector CN8 is connected to PA4 of the STM32L152ZDT6 as an external analog input or DAC output A low pass filter can be implemented for a 2 pin connector by replacing R43 and C35 with ADC input or replacing R36 and C35 with DAC output with correct values of resistor and capacitor as requested by end user s application There are also three analog signals available on the board 1 10 KOhm potentiometer connected to PF10 2 10 KOhm potentiometer connected to OpAmp2 PA6 3 measurement output signal connected to PF11 for MCU power consumption test Table 18 Analog input related jumpers Jumper Description 10 KOhm potentiometer connected to OpAmp2 PA6 when JP12 is closed Default setting Closed JP12 JP7 Description of JP7 is in Section 2 7 Audio Comparator Three I Os implement a comparator feature as shown in Figure 8 e Comparator non inverting input 4 connected to LDR R157 e Comparator inverting input PB3 connecte
18. USB type B connector CN14 viewed from front Table27 USB type B connector CN14 Pin Description Pin Description 1 VBUS power 4 GND 2 DM 5 6 Shield 3 DP 3 8 JTAG connector CN16 Figure 14 JTAG debugging connector CN16 viewed from above PCB Y 1917151311 9 7 5 3 1 Wirt 201816141210 8 6 4 2 MS30918V1 Table 28 JTAG debugging connector CN16 Pin Description Pin Description 1 VDD power 2 VDD power 3 PB4 4 GND 5 PA15 6 GND 7 PA13 8 GND 9 PA14 10 GND 32 59 Doc ID 022868 Rev 2 ky UM1521 Connectors Table 28 JTAG debugging connector CN16 continued Pin Description Pin Description 11 RTCK 12 GND 13 PB3 14 GND 15 RESET 16 GND 17 DBGRQ 18 GND 19 DBGACK 20 GND 3 9 Trace debugging connector CN11 Figure 15 Trace debugging connector CN11 viewed from above PCB Y 1917151311 9 7 5 3 1 20 18 16 141210 8 6 4 2 MS30918V1 Table29 Trace debugging connector CN11 Pin Description Pin Description 1 VDD power 2 TMS PA13 3 GND 4 TCK PA14 5 GND 6 TDO PB3 7 KEY 8 TDI PA15 9 GND 10 RESET 11 GND 12 TraceCLK PE2 13 GND 14 TraceD0 PE3 or SWO PB3 15 GND 16 TraceD1 PE4 or nTRST PB4 17 GND 18 TraceD2 PE5 19 GND 20 TraceD3 PE6 3 10 Audio jack CN13 A 3 5 mm stereo audio jack CN13 connected to audio DAC is available on
19. 87 PG2 A12 88 PG3 A13 89 PG4 A14 90 PG5 A15 91 PG6 JOYSTICK LEFT 92 PG7 JOYSTICK RIGHT 93 PG8 JOYSTICK DOWN 94 VSS 9 GND 95 VDD 9 VDD 96 6 SEG24 1282 97 SEG25 uSD_DET 98 PC8 SEG26 uSD_D0 99 PC9 SEG27 uSD_D1 100 PA8 COM0 101 PA9 COM1 USART1_TX 102 PA10 COM2 USART1_RX Doc ID 022868 Rev 2 UM1521 STM32L152D EVAL I O assignment Table 34 STM32L152D EVAL I O assignment continued Pin No Pin name STM32L152D EVAL I O assignment 103 PA11 USB_DM 104 PA12 USB_DP 105 PA13 JTMSSWDAT 106 PH2 A22 107 VSS_2 GND 108 VDD_2 VDD 109 PA14 JTCKSWCLK 110 PA15 SEG17 111 PC10 SEG28 SEG40 uSD D2 112 PC11 5 SEG29 SEG41 USD D3 113 PC12 COM6 SEG30 SEG42 USD 114 PDO D2 115 PD1 D3 116 PD2 SEG31 SEG43 uSD CMD 117 PD3 LED1 118 PD4 OEN 119 PD5 WEN 120 VSS 10 GND 121 VDD 10 VDD 122 PD6 WAITN 123 PD7 LED2 124 PG9 CS NOR EBAR1 125 PG10 CS RAM EBAR2 126 PG11 JOYSTICK UP 127 PG12 LCD EBAR3 128 PG13 JOYSTICK SELECT 129 PG14 LED3 130 VSS 11 GND 131 VDD 11 VDD 132 PG15 LED4 133 PB3 SEG7 POT COMP INN JTDO SWO 134 PB4 SEG8 LDR COMP INP JTRST 135 PB5 SEG9 POT COMP Temp SMBAI 136 PB6 Shield CT 6 3 137 PB7 Shield CT 6 4 Doc ID 022868 Rev 2 55 59 STM32L152D EVAL I O assignment UM1521 56 59
20. 9 AND juo RES H PROT TE cd 145 Quo bres Eod t DA bor 6 mmm 3 Pwd TIT qo 1012002 24 P PAUP 2 L ods lt B daama as Tas lt DS 3A Premed 1991 HTO MONLATOT OTT NV 0 1 50 HOO MONLATOCEOPT NV 15 10195 Ta TNO SOMESE O SIS 9CHA anoa ZI BB in ao E MD es MS D ERE nq 9 40120007 er 5 CROPS aa Tad 91 es ae Sy avol so tO sad 11 Ot L9 WOtTISALS 3 90d s 4 lt x 11 4 4 i 10120102 114 91 Laa sr ME Ts HA 9 DA 12 oE Tas TE 19 gt EGA oas ca avast B 18 Hy laa 1g Hs lt Es 9Idd OT siad h Sidd 61 DA 92 sc 15549 31 adaa ZL 5 vc L Tas IonuoO Tg oas Tidd 91 and ET lonuoO 78 9104 80 oF ods Um 7 fl o su A 7 cat sad SN dd sc E so L DS
21. CN12 9 RF EEPROM En uM daughterboard U16 Ira A8 E ee connector STM32L152ZDT6 PASCERE g L rd 116 C52 C49 659 sei CNI USARTI PES CN6 CN7 15 LCD glass ion daughter board GND Oni Mien CN1 connector USART1 15 Pot USB FS PEZ GND MCD PEB Cb6c 1 C60L 1 Fea 85 25 MBI64 nove R157 HE LDR U2 ma cri a js ZL Pe u2 OR CH c3 trace 5285 qm MEA 6 m2 r 3 950 CN7 7 a 3 E CN16 CN13 78 ISI 34323333233 JTAG MicroSD Card ees 5 LB 15 EX Maat LD5 TN ST LINK V2 Ic COM LED mg Lob dd s CHEM CN14 2838 n T 8 cm ST LINK V2 USB ug 28 1 J 1 LA sgere Audio jack pI ra us Mitch 3 us duoc s B 45888 EUN b 3 RE m E CN2 20 e E 4 Pa EER DE Power jack yd 115 DE eu nan B a 150452 0251 igs ti SZA Tamper key zz a button ep ili ep 8 8 Reset Joystick Key Tamper RV1 U23 joystick VDD adjustment 4 color LEDs RV3 potentiometer P
22. SD 9d sa 9v Opa 19001 660 AW 98 8 vH 9 6v loo a m vu ge boo TV 49 88 ccv 85 V T OIV ST Ola Figure 30 SRAM Flash Schematics Doc ID 022868 Rev 2 46 59 Schematics UM1521 ST LINK Figure 31 t P jo 815245 ZL0Z e wq f 968W 39qumN LS TVAHGCSITCEWLS gsn e SI godA gsn rary TIAHS S21U0J 29 90J92IINL S E AND da 88n 11577 Sci a Wd asn 115 cc Schi 29A VINO YANIT IS ASN ANIT IS ASN now lt rr OMS 1 AEF w c mrt 6 L lt NI OIOMS L r t Por 8 T SWIF WIS 9cn am dda At 160 i Clad TS 9 Swirl ee ISOW zs 8 4 OON 60 ANIES Isu WIS eani ONSI Te nd Ind 250 TIS Zt ziva SAN poso uS nd WIAS dams Snir nis pe C 88 Ip se lt GGA 0 _ 00 10 41 45
23. TCLS S21u04329 90J2IIN1S 10JODUUOI 55 401 TEDAS 12095 2 SWOI LWOO VENLS Jojoeuuo 858819 401 Xyz COW m ET UST xa gt m lt AAST gt moss NOVA Yg soar UV 90 WTA Lva is l M 5154 uw 1194 60 100620609 104 IAS Tove 5 1 6 10d 65 904 Sv pos a 2618 adgo A veu 199 gt gi E 8946 0909 9020 489 4 s 381 69 OFT Tene Lad SEL 6015 Kn 8045 100625060 LOSS 6 9995 5 I 5085 Tov siva _ 21585 601 SOL O 701 8Vd TOD 74927 TOSS 5085 99 NOW 950 0 2085 H ps i ta Doc ID 022868 Rev 2 42 59 Schematics UM152
24. VDD range B2 reset key LEDs MS30021V1 4 Doc ID 022868 Rev 2 7 59 Hardware layout and configuration UM1521 2 1 Note 8 59 Development and debug support Version 2 of the ST LINK called ST LINK V2 is embedded on the board This tool allows program loading and debugging on the STM32L using a JTAG or SWD interface Third party debug tools are also supported by JTAG connector CN16 and Trace connector CN11 A specific driver must be installed on your PC for communication with embedded ST LINK V2 To download and install this driver use the install shield called ST LINK V2 USBariver exe available on the Software and development tools page for ultra low power STM32L family available on www st com Third party toolchains support ST LINK V2 according to Table 2 Table 2 Third party support of ST LINK V2 Third party Toolchain Version Atollic TrueSTUDIO 21 IAR EWARM 6 20 4 Keil MDK ARM 4 20 Tasking VX Toolset ARM Cortex M 4 01 The embedded ST LINK V2 is connected to the PC via a standard USB cable connected to connector CN14 The bicolor LED LD5 COM advises on the communication status as follows e Slow blinking Red LED Off At power on before USB initialization e Fast blinking Red LED Off After the first correct communication between PC and ST LINK V2 enumeration Red LED On When initialization between PC and ST LINK V2 is successfully finished Green LED On After success
25. WA 9 gt 50 HA pal sdi eaa uu SN ON sqa 5 E w 27 En n tad 6 E HET car edd OSA ON ON ET caa sy DS ON ONASA m 22 sa aa 9 52 55 moog 5 ONS TNO toed 6r T eigen L E QNO jay 51 59 Doc ID 022868 Rev 2 STM32L152D EVAL I O assignment UM1521 Appendix STM32L152D EVAL I O assignment Table 34 STM32L152D EVAL I O assignment Pin No Pin name STM32L152D EVAL I O assignment 1 PE2 SEG 38 A23 TRACECK 2 PE3 SEG 39 A19 3 PE4 A20 TRACED1 4 PE5 A21 TRACED2 5 PE6 WKUP3 U5V DET 6 VLCD V LCD 7 PC13ANTI TAMP IDD CNT EN 8 1405 32 IN OSC32 IN 9 PC150SC32 OUT OSC32 OUT 10 PFO 0 11 PF1 A1 12 PF2 A2 13 PF3 A3 14 PF4 A4 15 PF5 A5 16 VSS 5 GND 17 VDD 5 VDD 18 SLIDER_CT_11_1 19 PF7 SLIDER_CT_11_2 20 PF8 SLIDER_CT_11_3 21 PF9 SLIDER_CT_11_4 22 PF10 POTENTIOMETER_ADC31 23 PHOOSC 24 PH1OSC OUT OSC OUT 25 NRST NRST 26 PCO SEG18 27 PC1 SEG19 LPF OA3 INP 28 PC2 SEG20 29 PC3 SEG21 LPF OA3 OUT 30 VSSA GND 31 VREF GND 32 VREF VDDA 52 59 Doc ID 022868 Rev 2 ky UM1521 STM32L152D EVAL I O assignment Table 34 STM32L152D EVAL I O assignment c
26. by D type 9 pin RS 232 connector CN1 and IrDA transceiver U2 which is connected to USART1 of the STM32L152ZDT6 on the STM32L152D EVAL evaluation board The signals Bootloader RESET and Bootloader BOOTO can be added on RS 232 connector CN1 for ISP support If Bootloader RESET signal is used mount R39 Default Unmounted with a 0 Ohm resistor as Figure 7 shows Doc ID 022868 Rev 2 17 59 Hardware layout and configuration UM1521 Note 18 59 Figure 7 R39 resistor placement 152D EVAL rw cera 21 888 8 amp Pie cam BRL 2 MB964 Reva uus sel en O 5 5 If Bootloader_ RESET signal is not used remove R39 to avoid disturbance due to CTS signal from pin8 of CN1 which could cause MCU reset with some software Table 15 5 232 amp IrDA related jumpers Jumper Description Setting 05 1 is connected to RS 232 transceiver and RS 232 communication is 123 enabled when JP4 is set as shown to
27. is lit when the MCU is powered by voltage 1 8 V lt VDD lt 2 2 V Green LED LD6 is lit when the MCU is powered by voltage 2 2 V lt VDD The power supply is configured by setting the related jumpers JP1 JP5 and JP10 as described in Table 3 Table 3 Power supply jumper settings Jumper Description Setting JP1 JP1 selects one of the four possible power supply sources NSd ASN MLS For power supply jack CN2 to the STM32L152D EVAL only JP1 is set as shown to the right For power supply from the daughterboard connectors CN10 to STM32L152D EVAL only JP1 is set as shown to the right B For power supply from USB CN15 to STM32L152D EVAL only JP1 is set as shown to the right For power supply from USB connector of ST LINK V2 CN14 to STM32L152D EVAL only is set as shown to the right Default setting ele For power supply from power supply jack CN2 to both STM32L152D EVAL and daughterboard connected on CN5 and 10 JP1 is set as shown to the right daughterboard must not have its own power supply connected Doc ID 022868 Rev 2 9 59 Hardware layout and configuration UM1521 Note Note 10 59 Table 3 Power supply jumper settings continued Jumper Description Setting VDD is connected to fixed 3 3 V DC power when JP5 is set as shown to the right Default setting Jt di 4 JP5 VDD is conn
28. the STM32L152D EVAL board ky Doc ID 022868 Rev 2 33 59 Connectors UM1521 3 11 3 12 34 59 MicroSD connector CN3 Figure 16 MicroSD connector CN3 viewed from above PCB Table30 MicroSD connector CN3 Pin Description Pin Description 1 SDIO_D2 PC10 6 Vss GND 2 SDIO D3 PC11 7 SDIO DO PC8 3 SDIO 2 8 SDIO D1 PC9 4 VDD 9 GND 5 SDIO CLK PC12 10 MicroSDcard detect PC7 Analog input output 2 pin connector CN8 Figure 17 Analog input output connector CN8 viewed from top 1 2 Table 31 Analog input output connector CN8 Pin Description Pin Description 1 GND 2 Analog input output PA4 Doc ID 022868 Rev 2 ky UM1521 Connectors 3 13 User USB type B connector CN15 Figure 18 USB type B connector CN15 viewed from front Table 32 USB type B connector CN15 Pin Description Pin Description 1 VBUS power 4 GND 2 DM 5 6 Shield 3 DP 3 14 RF EEPROM daughterboard connector CN12 Figure 19 RF EEPROM daughterboard connector CN12 viewed from front 01 04 Table 33 USB type B connector CN15 Pin Description Pin Description 1 SDA PB9 3 VDD 2 SCL PB8 4 GND Doc ID 022868 Rev 2 35 59 UM1521 Schematics Schematics 4 Figure 20 STM32L152D EVAL 8 4 o 5946 2102 6 0 9190
29. 1 Figure 27 MicroSD Card ovd quim PIE9GSOIIIN TYAT GCSL 15 5 GSOJIIN PiIEOGSODIA gt MT Zod 0007 800Sfd END Lt 81 Ate LI d 43 59 Doc ID 022868 Rev 2 UM1521 Peripherals Schematics Figure 28 r 5 s pL 30 7122545 2102 p968W3 qumN asn TVA3 G2S 15 59 youshor 3 a 52 E E 74 119 8 m m 0 TISHS m AND ENT 0 METH 7 t as 0 euondo 9qz 95188 4 22A 1 TOA 1opoouuoo gadA gSN 44001 2 SINO 012 9 1 Doc ID 022868 Rev 2 aa B SITA GT uopng apiezeduioy2ejeuioguejod E Sad 584 Ovd ilu 5 Y N x gt dri e AZ Z lt A INOGLA 012 LSTA WNA oo Ia LdIZOLESL 19 001
30. IZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 022868 Rev 2 59 59
31. LCD glass module daughterboard MB979 is mounted on the STM32L152D EVAL evaluation board It can be connected to the LCD driver of the STM32L152ZDT6 or work as a set of jumpers by mounting it on two possible positions position IO or position LCD e When the LCD glass module is mounted on position IO see Figure 4 all peripherals memories USART audio EEPROM potentiometer MicroSD Card microphone etc shared with the LCD glass are connected to the STM32L152ZDT6 the LCD glass is disconnected default setting e When the LCD glass module is mounted on position LCD see Figure 5 the LCD glass is connected to the LCD driver of the STM32L152ZDT6 and all peripherals shared with LCD glass are disconnected Figure 4 Position IO R106_C97 Ceo ky Doc ID 022868 Rev 2 13 59 Hardware layout and configuration UM1521 Table 9 LCD glass related jumpers Jumper Description Setting PA1 is connected to microphone MIC_INP signal when JP8 is set as shown to N 123 the right Default setting JP8 PA1 is connected to LCD glass as SEG0 when JP8 is set as shown to the right 123 ole 2 is connected to microphone MIC INN signal when JP6 is set as shown to 123 the right Default setting JP6 PA2 is connected to LCD glass as SEG1 when JP6 is set as shown to the right 123 ole The custom LCD glass on MB979 is model XHO5002B The signal mapping is shown in
32. STM32L152D EVAL I O assignment 52 Appendix Mechanical 57 REVISION history aw an sake amas a ca 58 ky Doc ID 022868 Rev 2 3 59 Overview 1 1 1 2 1 3 4 59 UM1521 Overview Features e Four 5 V power supply options Power jack ST LINK V2 USB connector user USB connector or daughterboard Audio jack connected to 125 DAC STM32L152ZDT6 internal DAC Microphone connected to ADC using integrated op amp as amplifier 2 GByte or more MicroSD Card on SDIO interface Temperature sensor and EEPROM on I2C compatible serial interface RS 232 interface configurable for communication or Flashloader IrDA transceiver JTAG and trace debug support embedded ST LINK V2 4 Kbit serial Flash 512K x16 bit SRAM and 128 Mbit NOR Flash 240x320 TFT color LCD connected to FSMC interface of STM32L152ZDT6 Joystick with 4 direction control and selector Reset and Tamper or key button 4 color user LEDs and 3 LEDs as MCU power range indicator MCU consumption measurement circuit LCD glass 40 x 8 segments connected to LCD driver of STM32L152ZDT6 Extension connector for daughterboard or wrapping board MCU voltage choice of 3 3 V or adjustable from 1 65 V to 3 6 V USB FS connector Touch slider Light dependent resistor LDR One MCU integrated op amp configured as Sallen Key 2nd order low pass filter One MCU integrated op amp configured as amplifier wit
33. a ASP SSS Lap 918260142618 4 oy 864 MTA 5 Pp io gt lw IE Ej A 0015 001 o 6 E 48001 8 0012 82 92 9 0 XNRIS GST 2 v 47 59 Doc ID 022868 Rev 2 19 619945 10 ea UM1521 45814 145 2 48 9 1ZEWLS S EEPROM and temperature sensor 407056 WI HS T 0I WSSI Josues eJnjeJed 49001 ACNSLNILS Qu E H IV 150 TIN Doc ID 022868 Rev 2 NLCENGA 685 9 E TA 0 105 vas TAL Schematics Figure 32 48 59 Schematics UM1521 Touch slider Figure 33 v bL Jo ZL0Z e Z owd F968W oqumN TYAT GTSI TENIS S31u04 29 90J9 IN 1 S Z uo uejd 34022 49N0 S PISIUS S x LO uso v 915 900 dup 10 ied zz PEIUS S S X a 912 Pes
34. bit M95040 R serial EEPROM is connected to SPI1 of the STM32L152ZDT6 Serial Flash chip select is managed by I O pin PB0 The EEPROM will work properly when VDD gt 1 8 V The LCD glass module has to be mounted on 10 position for SPI usage Refer to Section 2 6 LCD glass module for detail RF EEPROM The RF EEPROM daughterboard MB1020 implemented on the module is the M24LR64 R This EEPROM can be accessed by the MCU via the I2C bus or by RF using a 13 56 MHz reader for instance CR95HF The daughterboard can be connected to the STM32L152ZDT6 via the I2C bus on CN2 The address of RF EEPROM is 0b1010E2E1E0 EO E2 values are determined by the RF EEPROM daughterboard The RF EEPROM will work properly when VDD gt 1 8 V The LCD glass module has to be mounted on IO position for RF EEPROM usage Refer to Section 2 6 LCD glass module for detail SRAM 512Kx16 bit SRAM is connected to bank2 of the FSMC interface and both 8 bit and 16 bit accesses are allowed by BLNO and BLN1 connected to BLE and BHE of SRAM respectively The SRAM will work properly when VDD gt 2 4 V The LCD glass module has to be mounted on IO position for SRAM usage Refer to Section 2 6 LCD glass module for detail NOR Flash 128 Mbit NOR Flash is connected to bank1 of the FSMC interface The 16 bit operation mode is selected by pull up resister connected to BYTE pin of NOR Flash Write protection is enabled or disabled by jumper JP9
35. d to potentiometer used as variable threshold input for comparison to luminosity measured on LDR e Comparator non inverting input PB5 connected to potentiometer RV3 used as analog voltage input for comparison with internal voltage reference for instance Band gap in order to test analog Wakeup feature of the MCU Figure 8 STM32L152D EVAL comparator features LOR OUT ET AA GP comparator GPCOMP_IN GPCOMP_IN GPCO MP IN prio ADC_IN18 Badgapi2v _ GND Doc ID 022868 Rev 2 21 59 Hardware layout and configuration UM1521 2 18 22 59 Table 19 LDR and potentiometer related jumpers Jumper Description Setting PB4 is connected to LDR OUT when JP2 is set as shown to the right 123 JP2 PB4 is connected to TRST when JP2 is set as shown to the right 123 Default setting R oO 2 Potentiometer RV3 is connected to ADC input PF10 used as ADC input when 13 is set as shown to the right Default setting eel FE Potentiometer RV3 used as LDR variable threshold input is connected to 13 comparator inverting input GRCOMP_IN when JP13 is set as shown to the right Potentiometer is connected to non input TR GPCOMP_IN PB5 The comparator inverting input can be connected to 9i o c 1 4 band band gap band gap or DAC internally in orde
36. e ADC to measure voltage the IDD Measurement pin PF11 Configure PAO to serve as wakeup pin Enter Low power mode after setting IDD EN PC13 signal low IDD WAKEUP rising edge wakes up the MCU after around 300 ms Start ADC conversion as soon as possible after wakeup in order to measure the voltage corresponding to Low power mode on capacitor C82 6 Resetthe counter by programming IDD CNT EN high in less than 70 ms after the wakeup to avoid the R81 1 KOhm resistor being connected later in Run mode ark In Low power modes the 1 resistor is connected when 1 goes off after entering Low power mode Q12 output of the counter allows connection of the 1 K resistor when the current Ipp becomes very low Figure 10 STM32L152D EVAL Ipp Low power modes measurement timing diagram Wake up Ipp period measurement Wake up Clear CNT event E event MCU mode Run Low power gt gt gt IDD EN PC13 Gl TON 012 LOW POWER T1 pin 3 Q13 IDD WAKEUP _ Q13n disconnect filter E U18 pin 4 i i 0 ms 150 ms 300 ms Figure 10 shows how the counter and T1 ensure that 150 ms after IDD_CNT_EN falling edge the shunt resistor R81 is connected between VDD_MCU and the power supply in order to reduce the measurement range to 30 uA full scale when VDD 1 8 V Then after another 150 ms for current stabilization R81 is sh
37. e layout and configuration 2 3 Clock source Two clock sources are available on the STM32L152D EVAL evaluation board for the STM32L152ZDT6 and RTC embedded e 1 8 MHz crystal with socket for the STM32L152ZDT6 microcontroller it can be removed from socket when internal RC clock is used e 32 kHz crystal for embedded RTC Table 5 8 MHz crystal X1 related solder bridges Solder bridge Description PH1 is connected to 8 MHz crystal when 581 is open Default setting SB1 PH1 is connected to extension connector CN10 when SB1 is closed In such case R51 must be removed to avoid disturbance due to the 8Mhz quartz PHO is connected to 8 MHz crystal when SB2 is open Default setting SB2 is connected to extension connector CN10 when SB2 is closed In such case C53 and X1 must be removed Table 6 32 kHz crystal X3 related solder bridges Solder bridge Description PC14 is connected to 32 kHz crystal when SB8 is open Default setting SB8 PC14 is connected to extension connector CN5 when 588 is closed In such case R85 must be removed to avoid disturbance due to the 32kHz quartz PC15 is connected to 32 kHz crystal when SB7 is open Default setting SB7 PC15 is connected to extension connector CN5 when 587 is closed In such case R84 must be removed to avoid disturbance due to the 32 kHz guartz 2 4 Reset source The reset signal of the STM32L152D EVAL evaluation board is low active and the reset sources include e Reset button B1 Debug tools
38. ected to adjustable DC power from 1 65 V to 3 6 V when hd 123 JP5 is set as shown to the right e eje VDD power is directly connected to MCU VDD when JP10 is set as shown to the right Default setting Note For manual Ipp measurement the jumper on JP10 must be 123 removed and replaced by an ammeter connected between pin 1 and 2 of eje JP10 JP10 Connect VDD power to MCU with current sampling resister 1 Ohm or 1 KOhm in series for current measurement when JP10 is set as 123 shown to the right Due to some peripheral component specifications the low voltage limitations component will not work correctly when power level is under low voltage limitation related to the operating voltage of the peripherals are shown in Table 4 Table 4 Low voltage limitation Peripheral Component name Low voltage limitation USB CN15 USB 3V MicroSD Card CN3 SDIO 2 7 V SRAM U5 FSMC 2 4 V EEPROM U25 SPI 1 8 V RF EEPROM CN12 12 1 8 V The recommended AC220 V to DC5 V power adapter is PSU 5V2A It is not included with the board but can be ordered from ST as a separate item You can also use another equivalent 5 V power adapter polarity compatible with CN2 to power the STM32L152D EVAL board via the CN2 power jack on the board To order the recommended power supply use the order code PSU 5V2A Doc ID 022868 Rev 2 UM1521 Hardwar
39. from JTAG connector CN16 and trace connector CN11 Daughterboard from CN10 Embedded ST LINK V2 RS 232 connector for ISP Doc ID 022868 Rev 2 11 59 Hardware layout and configuration UM1521 2 5 Boot option The STM32L152D EVAL evaluation board is able to boot from e Embedded user Flash e System memory with boot loader for ISP e Embedded SRAM for debugging The boot option is configured by setting switch SW1 BOOTO SW2 The BOOTO can be configured also via the RS 232 connector CN1 Table 7 Boot related switch Switch SW1 and SW2 Boot from STM32L152D EVAL boots from user Flash when SW1 is set as Switch configuration SW2 are set as shown to the right 0 lt gt 1 shown to the right SW2 is don t in this configuration Default setting m eje gt 0 lt gt 1 STM32L152D EVAL boots from embedded when SW1 and Sa SW2 are set as shown to the right a m Swi 0 lt gt 1 STM32L152D EVAL boots from system memory when SW1 and In ojo Table 8 Boot0 related jumpers Jumper JP11 Description Default setting Not fitted The Bootloader BOOTO is managed by pin 6 of connector CN1 RS 232 DSR signal when JP11 is closed This configuration is used for boot loader application only 12 59 Doc ID 022868 Rev 2 UM1521 Hardware layout and configuration 2 6 LCD glass module An
40. ful target communication initialization Blinking Red Green LED During communication with target Red LED On Communication finished and OK Orange LED On Communication failure Itis possible to power the board via CN14 embedded ST LINK V2 USB connector even if an external tool is connected to CN11 Trace connector or CN16 external JTAG amp SWD connector Doc ID 022868 Rev 2 ky UM1521 Hardware layout and configuration 2 2 Power supply The STM32L152D EVAL evaluation board is designed to be powered by a 5 V DC power supply and to be protected by PolyZen from a wrong power plug in event It is possible to configure the evaluation board to use any of following four sources for the power supply 5 V DC power adapter connected to CN2 the power jack on the board power supply unit PSU on silkscreen The external power supply is not provided with the board 5 V DC power with 500mA limitation from CN14 the USB type B connector of ST LINK V2 USB 5 V power source on silkscreen ST LINK V2 5 V DC power with 500mA limitation from CN15 the USB type B connector USB 5V power source on silkscreen USB 5 V DC power from CN10 the extension connector for daughterboard daughterboard power source on silkscreen D5V The LEDs indicate the following LED LD9 is lit when the STM32L152D EVAL board is powered by 5 V correctly Red LED LD8 is lit when the MCU is powered by low voltage VDD lt 1 8 V Yellow LED LD7
41. h I2S2 port and one channel of DAC in the microcontroller STM32L152ZDT6 e OpAmp3 of the STM32L152ZDT6 acts as a low pass filter of audio output for this DAC e Aheadphone jack is connected to the output of CS43L22 e Amicrophone is connected to ADC through OpAmp1 of STM32L152ZDT6 Table 14 Audio related jumpers Jumper Description Setting PA4 is connected to analog input signal for ADC or output signal from DAC on 123 CN8 when JP7 is set as shown to the right JP7 PA4 output signal to OpAmp3 as low pass filter when JP7 is set as shown to the 123 right Default setting e e JP8 Description of JP8 is in Section 2 6 LCD glass module JP6 Description of JP6 is in Section 2 6 LCD glass module The I2C address of CS43L22 is 0b1001010 The LCD glass module has to be mounted on IO position for Audio I2C usage Refer to Section 2 6 LCD glass module for detail USB The STM32L152D EVAL evaluation board supports USB2 0 compliant full speed communication via a USB type B connector CN15 The evaluation board can be powered by this USB connection at 5 V DC with a 500 mA current limitation USB disconnection simulation can be implemented by controlling the internal 1 5 K pull up resistor on USB line and detection of 5 V power on USB connector CN15 by using resistor bridge connected to PEG USB will work properly when VDD 3 V RS 232 and IrDA RS 232 and IrDA communication is supported
42. h adjustable gain One ADC DAC input signal connector Potentiometer Demonstration software Demonstration software is preloaded in the board s Flash memory for easy demonstration of the device peripherals in stand alone mode For more information and to download the latest version available please refer to the STM32L152D EVAL demonstration software available on www st com Order code To order the STM32L152ZDT6 evaluation board use the order code STM32L152D EVAL Doc ID 022868 Rev 2 ky UM1521 Overview 1 4 Delivery recommendations Some verifications are needed before using the board for the first time to make sure that nothing was damaged during shipment and that no components are unplugged or lost When the board is extracted from its plastic bag please check that no component remains in the bag The main components to verify are 1 The 8 MHz crystal X1 which may have been removed by a shock from its socket 2 The MicroSD Card which may have been ejected from the connector CN3 left side of the board 3 dual interface EEPROM board ANT7 M24LR A which have been unplugged from the connector CN12 top right corner of the board ky Doc ID 022868 Rev 2 5 59 Hardware layout and configuration UM1521 2 Hardware layout and configuration The STM32L152D EVAL evaluation board is designed around the STM32L152ZDT6 144 pin TQFP package The hardware block diagram Figure 2 illustrates the connect
43. into account the RDS in series with R62 1 Ohm in the Ipp Run mode current calculation To avoid current injection from MCU to components on the board during Ipp measurement it is strongly recommended to keep VDD MCU s 3 3 V Some components on the board are powered by 3 3 V for instance the ST LINK so if VDD MCU is higher than 3 3 V a current can be in injected on signals like T NRST PBO of U21 which disturbs the measurement in low power mode Doc ID 022868 Rev 2 ky UM1521 Connectors 3 3 1 3 2 3 3 Connectors RS 232 connector CN1 Figure 11 RS 232 connector viewed from front 1 2 3 4 5 QUO QI QUE O 6 7 8 9 Table 23 65 232 connector CN1 with HW flow control and ISP support Pin Description Pin Description 1 NC 6 Bootloader BOOTO 2 RS 232 RX PB11 7 NC 3 RS 232 TX PB10 8 Bootloader RESET 4 NC 9 NC 5 GND Power connector CN2 The STM32L152D EVAL evaluation board can be powered from DC 5 V power supply via the external power supply jack CN2 shown in Figure 12 The central pin of CN2 must be positive Figure 12 Power supply connector CN2 viewed from front DC 45V GND TFT LCD connector CN4 A TFT color LCD board MB895 is mounted on CN4 Doc ID 022868 Rev 2 27 59 Connectors UM1521 3 4 28 59 Daughterboard extension connector CN5 and CN10 Two 42 pin male headers CN5 and CN10 can connect the daughterboard o
44. ion 18 PD14 FSMC D12 19 PD15 FSMC D13 20 PD16 FSMC D14 21 PD17 FSMC D15 22 BL_GND GND 23 BL_control 5V 24 VDD 3 3V 25 VCI 3 3V 26 GND GND 27 GND GND 28 BL_VDD 5V 29 SDO 30 SDI GND Ipp measurement The built in Ipp measurement circuit implemented allows the consumption measurement of the STM32L152ZDT6 while the MCU is in Run or Low power saving modes For Ipp measurement the circuit below is implemented on the STM32L152D EVAL Figure 9 STM32L152D EVAL lpp measurement circuit VDO MCU U19 MAX9938FEUK Uu vec Q Rs Oseskator fragueney 30KH7 Run mode In Run mode Ipp current is measured using operational amplifier MAX9938FEUK 019 connected to the 1 Ohm shunt resistor R62 In this case IDD CNT EN remains high Doc ID 022868 Rev 2 437 UM1521 Hardware layout and configuration 2 20 2 during measurement so R81 remains in short circuit during measurement because of transistor T1 which remains ON permanently JP10 must be connected between pins 2 8 3 Low power mode In Low power modes Stop or Standby the operational amplifier MAX9938FEUK 019 is connected to the 1 KOhm shunt resistor R81 controlled by the analog switch T1 In this case the counter 74HC4060 U15 enabled by IDD CNT EN manages the measurement timing according to Figure 10 The principle used to measure a current when the STM32L is in Low power mode is 1 Configur
45. ion between STM32L152D EVAL and peripherals LCD glass Color LCD Touch slider USB FS connector Temperature Sensor USART IrDA Audio SRAM Nor Flash EEPROM RF EEPROM MicroSD Card and embedded ST LINK and Figure 3 will help you locate these features on the actual evaluation board Figure2 Hardware block diagram pem RS 232 USART1 transceiver connector Voltage transceiver Dot Matrix LCD SRAM NOR Flash Embedded USB TypeB ST LINK V2 connector JTAG amp Trace connector 1 65V to 3 6V USB FS adjustable connector regulator Temperature Ee Sensor regulator LEDs Wakeup button D TS controller Touch slider 2 pin connector USB connector Audio Card amplifier MCU consumption measurement Potentiometer Extension connector for D Microphone GPIOs O I O shared with LCD glass MS30020V1 6 59 Doc ID 022868 Rev 2 UM1521 Hardware layout and configuration Figure 3 Hardware block diagram U3Microphone S1 CN5 10 Touch slider extension connection header 2 rm
46. ion How to disconnect with function block on STM32L152D EVAL board 21 PD1 FSMC_D3 23 PH0 OSC_IN Remove X1 from socket and close SB2 25 PA14 JTCK SWCLK 27 PH2 FSMC_A22 29 PA12 USB_DP Remove R136 31 11 USB DM Remove R149 33 PG7 JOYSTICK RIGHT Remove R117 35 PF6 SLIDER CT 11 1 Remove R77 and close SB6 37 PF8 SLIDER CT 11 3 Remove R69 and close SB4 39 41 4 FSMC A14 2 4 PB6 Shield CT 6 3 Remove R92 and close SB10 6 PG14 LED3 Remove R67 8 PG12 LCD EBAR3 10 GND 12 PG11 JOYSTICK UP Remove R119 14 PG9 CS NOR EBAR1 Remove R31 16 PD6 5 WAITN 18 PD4 FSMC 20 PD3 LED1 Remove R74 22 PD0 FSMC D2 24 VDD 26 1 OSC OUT Remove X1 from socket amp close SB1 28 PA13 JTMS SWDAT 30 GND 32 PG8 JOYSTICK DOWN Remove R110 34 PG6 JOYSTICK LEFT Remove R104 36 PF7 SLIDER CT 11 2 Remove R73 and close SB5 38 PF9 SLIDER CT 11 4 Remove C54 and close SB3 40 5 FSMC A15 42 FSMC A13 Doc ID 022868 Rev 2 UM1521 Connectors 3 5 Note LCD glass daughterboard connectors CN6 and CN7 Two 48 pin male headers CN6 and CN7 connect the LCD glass daughterboard MB979 GPIOs which act as LCD glass signals and are not on CN5 and CN10 are available on these two connectors The space between these two connectors and the position of every LCD glass signal is defined as a standard which allows develop
47. ment of common daughterboards for several evaluation boards The standard width between the pin1 and CN6 pin1 is 700 mils 17 78 mm GPIO signals on these two connectors can be tested on odd pins when the LCD glass board is absent Signal assignments are detailed in Table 26 If CN6 and CN7 are used as GPIO extension connector on a common daughterboard do not connect odd pins and even pins directly onto the daughterboard and leave Trace connector CN11 JTAG connector CN16 and JP2 open Table26 LCD glass daughterboard connectors CN6 and CN7 CN7 CN6 Odd pin GPIO signal Odd pin GPIO signal 1 PA9 1 PD2 3 PA8 3 PC12 5 PA10 5 PC11 7 PB9 7 PC10 9 PB11 9 PC3 11 PB10 11 PC4 13 PB5 13 PC5 15 PB14 15 PC6 17 PB13 17 PC7 19 PB12 19 21 15 21 9 23 PB8 23 PD8 25 PB15 25 PD9 27 PC2 27 PD10 29 PC1 29 PD11 31 PC0 31 PD12 33 PA3 33 PD13 35 PA2 35 PD14 37 PB0 37 PD15 39 PA7 39 PE0 41 PA6 41 PE1 43 PB4 43 PE2 45 PB3 45 PE3 47 PB1 47 PA1 Doc ID 022868 Rev 2 31 59 Connectors UM1521 3 6 ST LINK V2 programming connector CN9 Connector CN9 is used only for embedded ST LINK V2 programming during board manufacture It is not populated by default and is not for end user use 3 7 ST LINK V2 USB type B connector CN14 The USB connector CN14 is used to connect the embedded ST LINK V2 to a PC for debugging the board Figure 13
48. nd a 240x320 TFT color LCD connected to bank3 of the STM32L152ZDT6 FSMC interface port The LCD glass module must be mounted on IO position for color LCD usage Refer to Section 2 6 LCD glass module for detail Input devices are the 4 direction joystick U23 with selection key and wakeup button B2 Three LCD references using different controllers can be mounted on LCD board MB895 as shown in Table 21 The driver provided in the library is able to identify which LCD is used by reading the controller ID and then to adapt communication according to each controller specificity The LCD references and corresponding controllers used are summarized below Table21 LCD references LCD reference Controller Controller manufacturer AM 240320LDTNQW 02H SPFD5408B Orise Technology AM 240320LDTNQW 05H RM68050 Raydium AM240320LGTNQW 01H HX 8347D Himax Table 22 LCD modules Pin Description Pin connection 1 CS CS of Bank3 of FSMC 2 RS FSMC 0 3 WR SCL FSMC NWE 4 RD FSMC NOE 5 RESET RESET 6 PD1 FSMC_D0 7 PD2 FSMC_D1 8 PD3 FSMC_D2 9 PD4 FSMC_D3 10 PD5 FSMC_D4 11 PD6 FSMC_D5 12 PD7 FSMC_D6 13 PD8 FSMC_D7 14 PD10 FSMC_D8 15 PD11 FSMC_D9 16 PD12 FSMC_D10 17 PD13 FSMC_D11 Doc ID 022868 Rev 2 23 59 Hardware layout and configuration UM1521 2 20 2 20 1 24 59 Table22 LCD modules continued Pin Description Pin connect
49. nected to extension connector CN10 when SB5 is closed In this case R73 must be removed to avoid disturbance due to the touch slider PF6 is connected to touch slider when SB6 is open Default setting SB6 PF6 is connected to extension connector CN10 when SB6 is closed In this case R77 must be removed to avoid disturbance due to the touch slider PB6 is connected to touch slider when SB10 is open Default setting SB10 PB6 is connected to extension connector CN10 when SB10 is closed In this case R92 must be removed to avoid disturbance due to the shield PB7 is connected to touch slider when SB11 is open Default setting SB11 PB7 is connected to extension connector CN10 when SB11 is closed In this case R101 must be removed to avoid disturbance due to the capacitor Note The slider is optimized when the board is powered at 3 3 V It may be necessary to adjust the capacitor value of C54 47nF COG and the firmware to adapt them to a low voltage 2 11 MicroSD Card The 2 GB or more MicroSD Card connected to the SDIO port of the STM32L152ZDT6 is available on the board MicroSD Card detection is managed by standard I O port PC7 The MicroSD Card will work properly when VDD 2 7 V The LCD glass module has to be mounted on IO position for MicroSD Card usage Refer to Section 2 6 LCD glass module for detail Doc ID 022868 Rev 2 19 59 Hardware layout and configuration UM1521 2 12 2 13 2 14 2 15 20 59 Serial EEPROM A 4 K
50. ontinued Pin No Pin name STM32L152D EVAL I O assignment 33 VDDA VDDA 34 PAOWKUP IDD_WAKEUP KEY_TAMPER2 WKUP1 35 PA1 SEGO Micro_OA1_INP 36 PA2 SEG1 Micro OA1 INN 37 PA3 SEG2 Micro OA1 OUT 38 VSS 4 GND 39 VDD 4 VDD 40 PA4 CON ADC4 1 Audio OUT 41 5 2 5 42 SEG3 ADJ OA2 INP 43 PA7 SEG4 ADJ OA2 INN 44 PC4 SEG22 45 PC5 SEG23 2 CS 46 PBO SEG5 G OA2 OUT 47 PB1 SEG6 Audio DAC RST 48 PB2 BOOT1 49 PF11 ADC IN1b 50 PF12 A6 51 VSS 6 GND 52 VDD 6 VDD 53 PF13 A7 54 PF14 A8 55 PF15 9 56 PGO A10 57 PG1 A11 58 PE7 D4 59 PE8 D5 60 PE9 D6 61 VSS 7 GND 62 VDD 7 VDD 63 PE10 D7 64 PE11 D8 65 PE12 D9 66 PE13 D10 67 PE14 D11 E2P MISO ky Doc ID 022868 Rev 2 53 59 STM32L152D EVAL I O assignment UM1521 54 59 Table 34 STM32L152D EVAL I O assignment continued Pin No Pin name STM32L152D EVAL I O assignment 68 PE15 D12 E2P MOSI 69 PB10 SEG10 70 PB11 SEG11 71 VSS_1 GND 72 VDD_1 VDD 73 PB12 12 1252 WS 74 PB13 SEG13 1282 75 PB14 SEG14 76 PB15 15 1252 SD 77 PD8 SEG28 D13 78 PD9 SEG29 D14 79 PD10 SEG30 015 80 PD11 SEG31 A16 81 PD12 SEG32 A17 82 PD13 SEG33 A18 83 VSS 8 GND 84 VDD 8 VDD 85 PD14 SEG34 DO 86 PD15 SEG35 D1
51. orted the Ipp measurement is stored in C82 and the MCU is woken up After wakeup the MCU can measure the Ipp current corresponding to the Low power mode stored in C82 Doc ID 022868 Rev 2 25 59 Hardware layout and configuration UM1521 2 20 3 Note 26 59 1 Ibias current measurement procedure In Low power mode the bias current of operational amplifier input U19 pin 4 is not negligible compared to lpp current typical Ibias is 240 nA To obtain a reliable MCU Ipp measurement it is possible to subtract the bias current from the Ipp low power measurement since this current is sinked by the MCU The procedure for accurate Ipp measurement is Set jumper JP10 on pin 1 and pin 2 Follow the Low power mode procedure to measure 11 bias Remove jumper JP10 from pins 1 and 2 and place it on pins 2 and 3 Follow the Low power mode procedure to measure 12 Ipp bias 5 Calculate actual Ipp Ipp I2 gt xw If JP10 jumper is in pins 2 3 STM32L is powered through Ipp measurement circuit default If JP10 jumper is in pins1 2 STM32L is powered directly by 3V3 measurement circuit is bypassed Refer to Section 2 2 Power supply for detail When jumper JP10 is removed the current consumption of the STM32L can be measured by connecting an ammeter between jumper JP10 pins 1 and 2 RDS on typical value of analog switch T1 50 MOhm so to improve measurement accuracy it is recommended to take
52. r standard wrapping board to the STM32L152D EVAL evaluation board All GPIOs are available on them and the LCD glass connectors CN6 CN7 The space between these two connectors and positions of POWER GND and RESET pins are defined as a standard which allows common daughterboards to be developed for several evaluation boards The standard width between CN5 pin1 and CN10 pin1 is 2700 mils 68 58 mm This standard has been implemented on the majority of evaluation boards Each pin on CN5 and CN10 can be used by a daughterboard after disconnecting it from the corresponding function block on the STM32L152D EVAL evaluation board Refer to Table 24 and Table 25 for detail Table 24 Daughterboard extension connector CN5 How to disconnect with function block on Pin Description Alternative function STM32L152D EVAL board 1 GND 3 PF5 FSMC_A5 5 PF3 FSMC_A3 7 PF1 FSMC_A1 9 PE6 Tamper Key U5V_DET Remove R150 11 PC14 32K OSC Remove R85 and close SB8 e ps RCS 15 PC15 32K OSC Remove R84 and close SB7 CON_ADC4 DAC1 17 PA4 Audio DAC OUT JP7 open 19 GND 21 PB2 BOOT1 Remove R89 23 PF12 FSMC_A6 25 PF14 FSMC_A8 27 PGO FSMC_A10 29 PE7 FSMC_D4 31 VLCD 33 9 FSMC_D6 35 PE11 FSMC_D8 37 PE13 FSMC_D10 39 GND 41 PG2 FSMC_A12 2 Doc ID 022868 Rev 2 ky UM1521 Connectors
53. r to test the possibility to wakeup the MCU when an external voltage reaches a programmable threshold when JP13 is set as shown to the right 5 connected to 2 5 the interrupt output of temperature sensor dg U24 when JP14 is closed Default setting 14 PB5 is disconnected from 2 SMB but remains connected to COM IN when JP14 is open for comparator application The LCD glass module has to be mounted in IO position for comparator usage Refer to Section 2 6 LCD glass module for detail Temperature sensor Temperature sensor STLM75M2E is connected to the I2C bus of the STM32L152ZDT6 through two transistors to support a wide voltage range from 1 65 V to 3 6 V on the I2C bus I2C address of temperature sensor is 0b100100 AO AO can be 0 or 1 according to 589 Table 20 Temperature sensor related solder bridge SB9 Solder bridge Description I2C address AO is 0 when SB3 is open Default setting I2C address 0 is 1 when SB3 is closed The LCD glass module has to be mounted on IO position for temperature sensor usage Refer to Section 2 6 LCD glass module for detail Doc ID 022868 Rev 2 UM1521 Hardware layout and configuration Note 2 19 Temperature result measured from STLM75M2E would be a little higher than ambient temperature due to board heat Display and input devices The display devices are 4 general purpose color LED s LD 1 2 3 4 a
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55. the right Default setting USART1_RX is connected to IrDA transceiver IrDA communication is 123 enabled when JP4 is set as shown to the right e ele The LCD glass module has to be mounted on IO position for USART1 usage Refer to Section 2 6 LCD glass module for detail 3 Doc ID 022868 Rev 2 UM1521 Hardware layout and configuration 2 10 Touch sensing slider The STM32L152D EVAL evaluation board supports a touch sensing slider based on either RC charging or charge transfer technology The charge transfer technology is enabled by default assembly PB6 and PB7 manage an active shield reducing sensitivity to other signals The active shield is placed on an internal layer immediately under the slider layer 2 to cover components related to the slider and the slider itself Table16 Touch sensing slider related solder bridges Solder bridge Description PF9 is connected to sampling capacitor when SB3 is open Default setting SB3 PF9 is connected to extension connector CN10 when 583 is closed In this case C54 must be removed to avoid disturbance due to the capacitor PF8 is connected to touch slider when SB4 is open Default setting SB4 PF8 is connected to extension connector CN10 when SB4 is closed In this case R69 must be removed to avoid disturbance due to the touch slider PF7 is connected to touch slider when SB5 is open Default setting SB5 is con
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