15-09-25T_Lab1_Lec2_ActivateLEDs-2
Contents
1. Blackfin BF533 EZ KIT Putting the O inte JITK Just In Time Kr Activating a FLASH memory out Part 2 The ROW and RAW ideas are th 1e gt sa me as in Lab Assignment 1 Lab 2 Lab 3 and Lab 4 Agenda e Processors need to send out conti processor chip 16 FLASH memory chip has additional o ports connected to Ez Lite KIT LED s e Making the FLASH memory I O port control the Ez KIT LED s e The new Blackfin assembly language instructions needed Blackfin 1 0 pins REVIEW A L ma He AND CONTROLLER eS Sora WATCHDOG TIMER EM ON CORE TIMER H wind UART PORT rH eration eH hia er H a TEE CORE SYSTEM BUS INTERFACE p oe gt Eme A SERIAL PORTS 2 k gt Boor ow ROM BED Figure 1 1 Processor Block Diagram EXTERNAL PORT FLASH SDRAM CONTROL Radio controlled car IN PRINCIPLE we could e Connect LED1 control signal to turn rigi signal line of radio transmitter signal line of radio transmitter e Connect LED3 control signal to left signal line of radio transmitter IN PRINCIPLE means we might start off this way wh k we initially explore ideas to control the car However we may or may not finish the project a different way In actually fact we will use both PF1 PF5 PF6 PF7 as output to control car during the labs IN ae During Lab 4 we could use SPI interface so we cani contr ol car2. 0000 Not supported not 15 0001 to 1111 1 to 15 cycles BiRAT 3 0 Bank 1 read access time number of cycles ARE is held asserted 0000 Not supported 0001 to 1111 1 to 15 cycles B1HT 1 0 Bank 1 hold time number of cycles between AWE or ARE deasserted and AOE deasserted 00 0 cycles 01 1 cycle 10 2 cycles 2 cycles 11 3 cycles BiST 1 0 11 not 15 B 1011 Bank 1 setup time number of cycles after AOE asserted ae AWE or ARE asserted 4 m arog hl aech 00 4 R 3 cycles 01 1 ale 10 2 cycles for bank transition 10 2 cycles cycles 11 3 cycles for bank transition 11 3 cycles 15 14 13 12 1110 9 8 7 6 54 73 210 BOWAT 3 0 Bank 0 write access time number of cycles AWE is held asserted 0000 Not supported 0001 ta 1111 1 ta 15 eveles Ignore ARDY for accesses to IG O E this memory bank Reset 0xFFC2 FFC2 BiRDYE Bank 1 ARDY enable 1 After access time countdown use state of ARDY to deter mine completion of access BiRDYPOL Bank 1 ARDY polarity 0 Transaction completes if ARDY sampled low 1 Transition completes if ARDY sampled high BiTT 1 0 Bank 1 memory transition time number of cycles inserted after a read access to this bank and before a write access to this bank or a read access to another bank BORDYEN Bank 0 ARDY enable 0 Ignore ARDY for accesses to this memory bank 14 Control access speed RE DATA LATCHED TRANSIT
3. There are six control registers and one status register in the EBIU They are Asynchronous Memory Global Control register EBIU_AMGCTL Asynchronous Memory Bank Control 0 register EBIU_AMBCTLO Asynchronous Memory Bank Control 1 register EBIU_AMBCTL1 e SDRAM Memory Global Control register EBIU_SDGCTL Bank control register RE Reset value will probably work as is BU not efficient slow reads Efficiency not normally a problem if op not doneo Asynchronous Memory Bank Control 0 Register EBIU_AMBCTLO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CA0 a Ee Adag BiRDYEN Bank 1 ARDY enable 0 Ignore ARDY for accesses to this memory bank 1 After access time countdown use state of ARDY to deter OxFFCO 0A04 Reset OxFFC2 FFC2 BiWAT 3 0 Bank 1 write access time number of cycles AWE is held asserted 0000 Not supported 0001 to 1111 1 to 15 cy BiRAT 3 0 Bank 1 read access time number of ed mine completion of access BiRDYPOL Bank 1 ARDY polarity 0 Transaction completes if ARDY sampled low 1 Transition completes if ARDY t 0001 to 1111 1 to 15 cycles B1HT 1 0 Bank 1 hold time number of cycles between AWE or ARE deasserted and AOE deasserted sampled high 00 0 cycles B1iTT 1 0 01 1 cycle Bank 1 memory transition time 10 2 cycles number of cycles inserted after a E gt 11 3 cycles read access to this bank and BiST
4. 1 0 before a write access to this bank Bank 1 setup time number of cycles after AOE or a read access to another bank AWE or ARE 00 4 cycles for bank transition gt asserted before AWE or ARE asserted 00 4 cycles 01 1 cycle for bank transition 01 1 cycle 10 2 cycles for bank transition 10 2 cycles 11 3 cycles for bank transition 11 3 cycles 15 14 13 12 11 10 9 8 76 543210 PA BOWAT 3 0 Bank 0 write access time number of cycles AWE is held asserted 0000 Not supported 0001 ta 1111 1 ta 15 eveles Bank 0 ARDY enable 0 Ignore ARDY for accesses to this memory bank General Control Register e Reset value leaves CLKOUT disabled is that important Asynchronous Memory Global Control Register EBIU_AMGCTL 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0 OxFFCO 0A00 o jo fo Jo o Jo Jo jo umg o Reset 0x00F2 CDPRIO MCKEN 0 Core has priority over DMA 0 Disable CLKOUT for for external accesses asynchronous memory 1 DMA has priority over core region accesses for external accesses 1 Enable CLKOUT for For more information please see asynchronous memory Chapter 7 Chip Bus Hierarchy region accesses AMBENT 2 0 Enable asynchronous memory banks 000 All banks disabled 001 Banko enabled 010 Banko and Bank1 enabled 011 Banko Bank1 and Bank2 enabled 1xx All banks Banko Bank1 Bank2 Bank3 enabled Figure 17 3 Asynchronous Memory Global Control
5. TOP2BITS MASKVALUE ledDataCopy ledDataCopy amp top2BitMask ledDataCopy_R1 LedDataCopy_R1 amp top2BitWack R2 R2 is now dead could re use Keep bottom 6 bits of in par 32 bit in_value define BOTTOMSBITS MASKVALUE Ox3F define BOTTOM6BITS_MASKVALUE 0x3F unsigned long bottom6BitMask BOTTOM6BITS MASKVALUE define bottom6BitMask_R3 R3 bottom6BitMask_R3 BOTTOM6BITS_MASKVALUE in_value invalue amp bottom2BT E in_value_RO in_value_RO amp bottom6BitMask_R3 Fixed typo R3 is now dead could reuse OR the two processor data registers ledDataCopy ledDataCopy in_value Still another ledDataCopy_R1 ledDataCopy_R1 in_value_RO syntax Write odified back into LED data re ter modified copy ck i Pe eb ye giste problem WriteFlashLEDASM END RTS 8 bit and 32 bit writes Chapter 6 of instruction user manual e P0 RO 32 bit write 4 bytes Places all 32 bits of processor data register into long word 32 bit address starting at memory location Be If PO 0x1000 then place 32 bit Va at memory location 0x1000 B P0 RO 8 bit write Places bottom 8 bits of 32 bit processor data register into byte 8 bit address starting at memory location pointed to by pointer register PO lw 8 bit and 32 bit reads e RO P0 32 bit read 4 bytes Places all 32 bits of long word 326 address st
6. ae i 2 the label AMA double clic Build was unsuccessful What to look for in the following Detailed look at the WriteLED and ReadLED code you will USE rather than write during the familiarization laboratory and Lab 1 e Look at how the Blackfin assembly language syntax is used KEY ELEMENT TO USE IN LABS AND QUIZZES Must do our coding without destroying the operation of existing code functionality When using hardware this normally means the extensive use of bitwise AND and OR operations Those RAW s and ROW s again oe z WriteFlashLEDASM long inV USER CASE STUDY TASK Write on or 0 off to the Port to activate LEDs connected to pins PB5 gt PBO leaving other pins unchanged Table 2 9 Flash A Port B Controls a QO eo DON WriteFlashLEDASM long in_ 1 Read 8 bit LED data register into 32 bit process register R1 makes a copy 4 OR the two processor data registers 5 Write modified copy back into 8 bit LED data register e PROBLEM byte read and writes how ag we those Table 2 6 Flash A Configuration Registers for port A B 0x2027 0007 26 The following way of writing assemb code is from my P S P find it speeds coding up as mak less mistakes 27 Standard ENUM36Y assembly problem but using different sym Start with the stub and pseudo code of user
7. ar ge LCD screen Sam 2S d duri ng TV flashing ship lab LEDS connected to memory f REVIEW ave eee es ta a a S 3 3 S 9 a yt a L7 u L r r E Lr rE rar z r a ji a ma m a o is r Fi 1 I 4 4 4 te 2 2 u N U U 2 amp 2 a ad wit 164 is i LH 8 mmm Raeaeaaaeas amp Da a a i ii gt aa ee a i a an at 2 ee nll eee Pia Tae Bee es PITH seas AN A 4 aasam o am ee rae Hi Toe i O PAEL TEE T e n r To G a r e A OO M I LL ws TH iTi Seep crepe O E S ge pe eee ELL ipo __ PUTO ZOL FADL BEN Oia eE Oe DEC a _ ee oe TSCA 7 i Tet Pate RIGHT Er FORWARD 2 LEFT BACK DONE POWER ON These pins might be connected to F other things THEIR aai EHAVIOUR 4 Activating LEDs REVIE e Get the FLASH to work correctly Performed by nitFlash_CPP function e Get the Port to work correctly as outputior pins PB5 gt PBO leaving other pins Z unchanged in behaviour Performed by nitFlashPort_CPP function e Write the value we want to LEDs WriteFlashLED_ASM int value or WriteFlashLED_CPP int value or both e Read back the value the LEDs show int ReadFlashLED_ASM void or int ReadFlashLED _CPP void or both o Er EBIU External Bus Intertac Unit REVIEW SDRAM memory Large arrays live there ASYNCHRONOUS MEMORY C
8. bits of in par 32 bit in_value problems define BOTTOMEBITS MASKVALUE 0x3F define BOTTOMGBITS__ MASKVALUE 0x3F ERRORS unsigned long bottom6BitMask BOTTOM6 define bottom6BitMask_R3 R3 bottom6BitMask_R3 BOTTOM6BITS _ MASKVALUE s in_value invalue amp bottom2BitMask Fix WriteASM in_value_RO in_value_RO amp bot tom6BitMask_ R3 z 7 R3 is now dead could reuse as exercise OR the two processor data registers Test by ledDataCopy ledDataCopy in_value replacing ledDataCopy_R1 ledDataCopy_R1 in_value_R0 Zz Write modified copy back into LED data register ic uTTCOS_Write BIPO a ledDataCopy_R1 LED in Lab WriteFlashLEDASM END RTS code i My_InitLEDASM to complet e Set direction to 1 on lower pins leaving other direction values unchanged Read direction byte register into processor data register makes a copy Set another processor data register to OxSF OR the two data registers HOW i Write modified copy back into direction byt register Agenda General purpose input output GPIO processor chip 16 FLASH memory chip has additiona ports connected to Ez Lite KIT LED Making the FLASH memory I O port control the Ez KIT LED s e The new Blackfin assembly language instructions needed p ss
9. EVIEW InitFlashCPP rne OOOO O pe o O ee SSO EBIU_AMBCTLO Ox7BBO7BB0 Timing control for Banks and 0 EBIU_AMBCTLI bits 15 0 Ox7BB0 Timing control for Bank 2 Bank 3 is not used EBIU_AMGCTL bits 3 0 Enable all banks Does not sound too big a deal IN PRINCIPLE 1 Set pointerto EBIU_AMBCTLO address 2 Then set value 0x7BB0O7BB0O 3 Then store value at EBIU_AMBCTLO pt value Real C code or ASM design comment 4 Then make sure write occurs NOW as this processor c delay doing writes until convenient This processor is DESIGNED to do writes when it is not busy giving highest priority to MANY read operations This priority scheme is useful when deve cM processing algorithms for video or audio LASH registers Build and Test Stub REV What we want to do paeudo code ve woid InitFlashaSM void CHANGED TO use uTTCOS _InitLED fe It FLASH menory already configured ae return without initializing ee Else Ae Order is inportant ee configure Memory Bank control register oe THEN configure Global control fe turna on the FLASH ee fe t wold InitFlashaAsSW void 4 S6ction progra global TnitF lachasi hASH FLASH memory already contietred return withe t initializing f Order 18 important coni igs fenor Bank control register Cont igisa Global control irna on the FLASH Else aa iow an i ten Thu are not actually going to c
10. ION SETUP READ ACCESS HOLD TIME lt p 2 CYCLES 2CYCLES 1 CYCLE 1 CYCLE ROE Figure 17 6 Asynchronous Read Bus Cycles 15 Set General Control Regi Documentation says set to Ox000F for this particular FLASH chip Asynchronous Memory Global Control Regi DRESS 15 141312 11 10 9 8 EBIU_AMGCTL 0000 00000000 1111 CDPRIO AMCKEN 0 Core has priority over DMA for external accesses 1 DMA has priority over core ENA LE for external accesses For more information please see Chapter 7 Chip Bus Hierarchy Note We don t access this memory location using an pointer register PO banks with value OxFFCO 0A00 Instead we include lt blackfin h gt in our code and use a pointer value EBIU_AMGTCL Software engineering abstraction concept Figure 17 3 Asynchronous Memory Global Control Register PERIPHERAL ie a VALUE XFFCO 0A00 ojo fo jo o Jo Jo jo Awan aana Reset 0x00F2 0 Disable CLKOUT for asynchronous memory region accesses 1 Enable CLKOUT for asynchronous memory region accesses AMBEN 2 0 Enable asynchronous memory 000 All banks disabled 001 Banko enabled 010 Banko and Bank1 enabled USE ALL 11 _ Bank1 and Bank2 bled ASK ME HOW DO YOU CODE 1XX WHILE X MEANS DON T CARE THE REQUIRES YOU MAKE A DECISION CODING BIT VALUE 001 IS EASY 0x01 PROCESSOR CARES WHICH Key issues R
11. In C code a similar error is coding unsigned int value 32 bits when you meant to use unsigned short value 16 bits More readable and reliable _ ASM code example include macros h Project Group 1 project void InitFlashASM void D FlashMemory section progr a Source Files global _Ini iF lachaSM InitFlashASh Pe FlashUtiltiesASM asm 77 If FLASH memory already configured fo C Linker Files ea return without initializing Seen al Header Files a4 Else Order is important configure Memory Bank control register PSP f Set PO to point to EBIU_AMBCTLO define EBIU_AMBCTLO OxFFCOOA04 rom carpentr PO EBIU_ANMBCTLO Then RO 0x7BB07BB0 define ONCE corte RO a aBn YOU FIX THIS CODE eadable code ee FLASH CONTROLO RESET_VALUE 0x7BB07BB0 lo Use twice DL lo FLASH_CONTROLO_RESET_VALUE RO H hi FLASH_CONTROLO_RESET_VALUE with no defects Then P0 RO P0 RO iL Self documenting _ Project FlashUtitiesas code ST Configuration FlashMemory Debug La FlashUtilitiesaASM asm cG 55 Error ea5003 FlashUtilitiesASM asm 26 Semantic Error in instruc I do define PO OxFFCOOA04 Operands don t fit instruction template REG ASSIGN expr and then use Check for an out of range immediate value or an illegal register double click Previous errors prevent assembly cut and paste A bl total I is d 0 s zer e Pear A BA
12. ONTROLLER AMC EAB DEB CONTROLLER EXTERNAL BUS CONTROLLER PAB e J I T K Just In Time Knowledge Need to W A I N rather than W A LL How does EBIU know whether to execute your Co by writing the data to FLASH LEDs live there or FLASH DATA 15 0 J ANSWER Blackfin Memory Map B e McVASH and COFFEE ADSP BF533 MEMORY MAP control logic ideas again oxFFE0 0000 C MMR on H OxFFCO 0000 LSVSTEM MMR LDF file controlled owen 1000 x RESERVED a E e i 0OxFFBO 0000 _ SCRATCHPAD SRAM lf agape i OxFFA1 1000 RARE yo register is set to OxFFA1 0000 D address 0x20001000 ce apap INSTRUCTIONSRAM then OxFFAO 0000 INTERNAL OxFF90 8000 RESERVED Memory Pae WIPO g reads a 32 bit value ariken from FLASH BANK 0 OxFF80 8000 eho OxFFB0 4000 e TATA BANK A SRAM e If RO is 6 and sehin PO is 0x0000 1000 DORN 0x2030 0000 then ANER EXTERNAL x2010 0000 __ ASYNCBANK1 BANK 1 MEMORY B PO RO places an 8 bit value in JRANV memo m ASYNC BANK 0 RESERVED FLASH registers REVIE How does Blackfin match itself Tor fastest FLASH operation e Depends on which FLASH is used in the EZ Lite KIT from a specific manufacture EBIU Programming Model This section describes the programming model of the EBIU This model is based on system memory mapped registers used to program the EBIU
13. Register InitFlashCPP REVIEV e Get the FLASH to work correctly e May be many processes running on the Blackfin All these processes may want to use InitFlashCPP InitFlashCPP Design ideas by pseudo code If FLASH memory is already configured return without re initializing to avoid destroying existing code Else configure Memory Bank control register THEN configure Global control turns on the FLASH looked in EZ Kit online docume Don t start from scratch Look for recommended settings e These settings are specific for FLA memory used on the EZ Kit Lite Table 2 4 Asynchronous Memory Control Registers Settings Example Rego ae enn EBIU_AMBCTLO Ox7BBO7BBO Timing Timing controlfxrBenkslandO for Banks and 0 EBIU_AMBCTL1 bits 15 0 0x7BB0 Timing control for Bank 2 Bank 3 is not used EBIU_AMGCTL bits 3 0 Enable all banks Turns on clock Each Flash chip is initially configured with the memory sectors mapped into the processor s address space as shown in able 2 5 13 Set the Bank control regi e Kit documentation recommends 0x7 P L1 Q What does this setting mez PERIPHERAL REGISTER ADDRESS PERIPHERAL REGISTER RESET VALUE Memory Bank Control 0 Regis r EBIU_AMBCTLO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 laa eases EERE CER BiWAT 3 0 Bank 1 write access time number of 7 cycles cycles AWE is held asserted
14. arting at memory location into processor data register If PO 0x1000 then place 32 bit Wait at memory location 0x1000 RO B P0 Z 98 bit read Places byte 8 bit address starting at memory location PO into bottom 8 bits of processor data register and puts 0 into the top 24 bits of register Must convert 8 bit read operation into a 32 bit store in register operation rw Add byte read and write ope section prog global _HriteF lashLEDASM ywoid a i ce a DO CODE ff define in_value_RO RO REVIEW WriteFlashLEDASH i 7 PROBLEM byte read and writes Is this correct for keeping top 2 bits of an 8 Read ae ri aa dk processor data register makes a copy 4 Convert b ned el so we can do the math bit value define LED DATA _ _ REGISTER ADDRESS 022027 0 PO L lo LED_DATA REGISTER ADDRESS PO H hif LED DATA REGISTER ADDRESS ledDataCopy_R1 B P0 Z DEFECT if unsigned long ledDataCopy define ledDataCopy_R1 R1 Keep t p 2 bits AND operation of cop tdef ine TOP2BITS_ MASKVALUE OxC not corrected define TOP2BITS MASKVALUE OxC signed long top2BitMask TOP2BITS_M xx AMW k k define top2BitMask_R2 R2 top2BitMask_R2 TOP2BITS MASKVALUE ledDataCopy ledDataCopy amp top2BitMas ledDataCopy_R1i LedDataCopy_R1l amp top2BitMask_R2 i R2 is now dead could re use Still syntax Keep bott 6
15. ashlUltiltiesAS Ubvious problem value nee EBIU_AMBCTLO e LOOK IN THE MANUAL CHAPTER Asynchronous Memory Bank Control 0 Register EBIU_ AMBCTLO 31 30 29 28 27 26 25 24 2 21 20 19 18 17 BiRDYEN moi a ammar Reset OxFFC2 FFC2 OxFFCO 0A04 able void InitFlashASM void for accesses to section program global _InitFlashaASn InitFlashaSH QUIZ it FLASH memory already configured return without initializing Else f Order configure Memory Bank control Set PO to point to EBIU_AMBCTLO define EBIU_AMBCTLO 0xFFCO OA04 PO BIU_AMBCTLO Then RO Ox 7BBO7BBO RO Ox BBO 7BB0 Is the following the equivalent define to use in C define pBIU_LAMBCTLO int OxFFCO 0A04 If use include Then P0 RO P0 0 FIND AN EXPLAIN THEM Then make sure write occurs NOW aa this processor can delay doing writes until convenient SSYNC SSYNC Programming manual page 16 8 Corrected code still fal Get equivalent errors in ETS void InitFlashaASM void No s in a define roject Group 1 project section program FlashMemory I j _InitFlashaSH statene nt nitFlas r a6 pom SAEN e If FLASH memory already configured Linker Files Header Files return without initializi PE Else fT r is ee configure Memory Bank c registi ag J5 a No spaces in Set PO
16. case study Use the real C as psuedo code when w know what to Use a description otherwise section progr global _firiteF lashLEDASM f void WriteFlashLEDASM long in_value 7 in RO WriteFlashLEDASH PROBLEM byte read and writes f unsigned long ledDataCopy Read LED data register into processor data register makes 4 copy f Convert byte into aoe rae so we can do the math Ree Keep top 2 bits AND cpereriani of copy define TOP2BITS_MASKVALUE OxC gt unsigned long top2BitMask TOP2BITS _MASKVALUE ledDataCopy ledDataCopy amp top2BitMask Keep bottom 6 bits of in par 32 bit in_value define BOTTOM6BITS_MASKVALUE 0x3F unsigned long bottom2BitMask BOTTOM6BITS MASKVALUE in_value invalue amp bottom2BitMask f OR the two processor data registers ledDataCopy ledDataCopy in_value 4 f Write modified copy back iy LED data register 4 222222222 Typo bottom6bitmask WriteFlashLEDASM END RTS 28 Now identify the registers t e Input value In_par come in RO e We can use R1 R2 and R3 without savii Follows C ASM coding convention section progra global iri teF LashLEDASH yoid WriteFlashLEDASM long in_value se in RO Fars define in_value_RO RO WriteFlashLEDASM PROBLEM byte read and writes f unsigned long ledDataCopy define ledDataCopy_R1 Ri Read LED
17. data register into processor data Pech ana a copy Convert byte into eeeigned va so we can do the m 5 Keep top 2 bits AND aparatin of Py Ta TOP2BITS_ MASKVALUE OxC J unsigned long top2BitMask TOP2BITS_MASKVALUE define top2BitMask_R2 R2 l edDataCopy ledDataCopy amp top2BitMask R2 is now dead could re use Keep bottom 6 bits of fe vol 32 bit in_value define ROTTOMGEITS _ MASKVALUE Ox3F p unsigned long bottom2BitMask BOTTOM6BITS MASKVALUE define bottom2BitMask_R3 R3 in_value invalue amp bottom2BitMask 7 R3 is ao dead could reuse OR the two processor data registers ledDataCopy ledDataCopy in_ value Write modified copy back mno LED data register 7 222777777 Typo bottom6bitmask Bi Ol MD aa defect if not spotted Add in the code we underst section progr global Wri teF LashLEDASM void WriteFlashLEDASM long in_value in RO Ved jakan Look for hidden defects where code does not match comments WriteFlashLEDASH PROBLEM byte read and writes unsigned long ledDataCopy define ledDataCopy_R1 Ri Read LED data register into processor data register makes a copy Convert byte into ben ya so we can do the math ae Keep top 2 bits AND aah of tdefias TOP2BITS_ MASKVALUE OxC define TOP2BITS MASKVALUE OxC Sf unsigned long top2BitMask TOP2BITS MASKVALUE define top2BitNask_R2 R2 top2BitMask_R2
18. ede this for Lab 1 Call uTTCOS utility instead uTTCOS_InitLED Asking you about the ideas or doing some of the code makes a good quiz or exam question al When stub is tested as a stub Li Run then add ASM code to learr The System Synchronize SSYNC instruction forces all speculative tran sient states in the core and system to complete before processing continues Until SSYNC completes no further instructions can be issued t the pipeline The SSYNC instruction performs the same function as Core Synchronize CSYNC In addition SSYNC flushes any write buffers between the L1 memory and the system interface and generates a Synch request signal t the external system The operation requires an acknowledgement Synch_Ack signal by the system before completing the instruction void InitFlashASM void f section program global _InitFlashaASH InitFlashASM ERROR WHEN WRITING A A If FLASH 1 d fi d i 7 m a a reer AVOID SAME PROBLEM II 7 Else Order is important eal configure Memory Bank control register Set PO to point to EBIU_AMBCTLO PO BIU_AMBCTLO NEW VIP BLACKFIN INSTRUCTION SSYNC Finish all pipelined operations as this alae me delay doing writes until convenient before continuing SSYNc SSYNC Programming manual page 16 q I a 1 Then RO 0x7BB07BB0 RO Ox BBO 7BBO Then P0 RO P0 RO Then make sure write occurs NOW Fl
19. to point to EBIU_AMBCTLO b define EBIU_AMBCTLO OxFFCOOA04 PO EBIU_AMBCTLO aad Then RO Ox BBO 7BBO0 RO Ox BBO 7BBO Th PO RO MBO RO Spell check Then make sure write occurs NOW 0 not O as this processor can delay doing writes until con SSYNC SSYNC Programming manual page 1 DEFECTS in code Project FlashUltilitiesAS process SA aeRO angie FlashMenory Debug j NFlashUtilities SH a Pair programming Error ea5003 FlashUtilitiesASM asm 25 Semantic Error in instruction i i cost if not caught Operands don t fit instruction template REG ASSIGN expr Check for an out of range immediate value or an illegal register by partner Error ea5003 FlashUtilitiesASM asm 28 Semantic Error in instruction 3 5 RO Ox BBO 7BBO0 Operands don t fit instruction template REG ASSIGN expr Check for an out of range immediate value or an illegal register Previous errors prevent assembly e a MIPS and Blackfin behave same putting 32 bit numbers into 32 b registers e You can t load a 32 bit register with a 32 bit immediate value using one instruction e WRONG RO 0x7BB07BBO0 F e Must load low 16 bit of data register i RO L 0x7BB0 e Then load high 16 bits of data register RO H 0x7BO00 e You must load addresses into pointer register PO the same way YOU write the code to replace PO OxFFCOOA04
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15 09 25T_Lab1_Lec2_ActivateLEDs 2