VPX4820 VPX XMC/PMC Carrier User Manual
Contents
1. 10 MPX COMME COS 12 PMECONNECTONS e en en ee u en an ne 14 XMIC Connector rennen cities 18 FIELD GROUNDING CONSIDERATIONS cssecececcceceenescececeeeaseeeesseeeececeaseaeeseeeeeeesaueaseseeeeeeeeags 21 3 VPXICONNECTIVITY se 22 VITA 65 PROFILES a e errata 22 dm dom O 22 4 SERVICE AND REPAIR eec 24 SERVICE AND REPAIR ASSISTANCE uueesessssensensenenennnnennennnnenennnnnennennnnen nenn nenennnennnnnnnnnensennen een 24 PRELIMINARY SERVICE PROCEDURE c cccsseseseseececceenesssseececesesueaeeeseseceesaueaceseeeseeeeauaaensss 24 WHERE TOGET HELP c a iia 24 5 SPECIFICATIONS cencechitveaszcs laica 25 PHYSICAL cuca aiii 25 Phiysical CoriflBUratl OD roe ee dassarenessehscsuessaceadeseuecgessacesuas sales 25 CONNECTOTS oosina nreno eene aee eaa E EE RAEE EAE E RE a A a Ea araa Ea aiea 25 JUMPEIS ii LTDA 25 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER POWER eSI Pd et entes e ite eie 25 XMC PMG POWOFE 1 eie d aee desit e eei e c di tees 26 Power Dissipation seizena DESERT e eut am Reid eee ris 26 PCIe BUS COMPLIANGE acti eerte g REC Eat 28 PEI BUS COMPLIANCE etie feptima tree eese ads erst d Rees E ta Pea Ea ASRS 29 XMC PMC Slot Selection eeesssseeeeeseeene en eene enne EEE r esee rnt esse rtr esee rtr esser esser sre s enn 29 Rear VORGE ee HET 29 ENVIRONMENT2. The PCie lane configuration determined the PCle switch port naming convention Use Table 2 2 as a reference when selecting the upstream and downstream port 22 Table 2 2 PCle Port Naming Convention PCle Lane Configuration Port Naming LO L3 L4 L7 L8 L11 L12 L15 Porto Porto Porto 8x 4x 4x Port O VPX CARRIER CARD SERIES PCie Upstream Port Select PCie Gen 1 Force PCie NT Port Enable PCie NT Port Select VPX4820 PCle XMC PMC CARRIER The PCle Upstream port is selected by the third and forth jumpers of J1 Please note that these strapping settings can be overwritten viaa 1 C write to the PLX8632 Table 2 3 PCle Upstream Port Jumper Selection PCIe Upsteam Port To Force all lanes of the PEX8632 to run at Gen 1 speeds set the fifth jumper of J2 Note only use this setting if the auto negotiate process fails Normally this only needs to be used for PCle devices are were released prior to the finalization of the PCle 1 0 specification This will effect all PCle connections on the board including to the processorand XMC modules To Enable the NT Port of the PCle switch SET the first jumper ofJ3 The PCle NT port is selected by the second and third jumpers of J3 Please note that these strapping settings can be overwritten via al C write to the PLX8632 Table 2 5 NT Enabled Jumper Settings Disabled OPEN Enabled The PCle NT port is selected by the second and third jumpers of J3 The NT Port mus
3. J gt Expansion Plane 32 pairs gt Key Diff S P3 J3 Diff P4 User Defined lt S j4 E _ gt Rear I O Diff P5 J5 Diff P6 J6 E gt Key The customeris responsible forchecking compatibility of the VPX4820 with their VPX backplane as well as managingthe interconnect between boards All the PCle lanes are connected to P2 the expansion plane Furtherinformation can be foundin VITA 65 REAR I O The Rear is mapped per VITA 46 9 method P64s X12d X8D This mappingis shown inthe diagram on the following page Note perthe errata attached to VITA 46 9 that the polarity of the XMC twisted pairs is reversed compared to the VITA 42 specification Please refer to VITA 46 9 for further information XMC Rear I O is routed differentially with 100 Ohm impedance and matched length 22 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER PMC Rear I O is routed differentially with 100 Ohm impedance and best effort to match length Match lengths will be done in groups of four Figure 5 3 1 6U Carrier P64s X12d X8d Mapping 23 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER 4 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test e
4. Pin A B c o E F fe 11 pmc1 RI021_N Jpmc RIO21 P ond pmci RIO20 n pci RIo20 P end 13 pci RIO25 N PMCi RIO25 P ond pmc1 RIO24 n pmc1 RIo24 P lena 14 ond rmcirio27 N pmci RIO27 P ond PMC1RIO26 N PMC1 RIO26 P 15 PMCi RIO29 N JPMC1i RIO29 P Gnd PMCiRIO28 N PMC1 RIO28 P ond 16 ond PMCciRO31N PMCi RiO31 P ond pmciRIO30_N PMC1_RIO30_P All blue colored cells are Not Used in this design Table 2 14 P4 XMC SLOT A Rear I O Pin A B c b tx Fr jG 1 kwcipPos N xici_ppos p end mcippos_N XMCiDPO4 P ens 2 ind xiica_ppo7_n Ixmc Po7 P and XMCi DPO6 N Ixmc DPOG P land 3 kmc1 ppo9 N kmc _Dpoo P nd XxwciprosN xMcipeosP end 4 jond JXMCLDPIS N XMCiDP1s P nd XMCiDP14 N XMCI DP14 P land 5 kmc1 DP17 N XMCLDPI7 ond XMCiDPle N XMCiDPl6 P fena 6 end xici_ppi9_N Ixmc pr s P Ina XMCiIO B19 XMC1 IO A19 land 7 kMcipPoi N XMCi DPo1 P ond kmc ppoo n XMCiDPO0P nd 8 ond jkmc _ppos n xmci_ppos p ond xmcibrozN xmciDPo2P Gnd 9 kwcipPii N mc pp1 P ond mcipr1o_N xmci_ppio p end 11 es cs UN 2 fend ond ml All blue colored cells are Not Usedin this design Table 2 15 P5 PMC SLOT B Rear I O 1 mc2 Rios n MC2ROl1P ena mcz Rioo n pmczrioop end 2 nd MczRO3 N Jpmc2 R3 P Gnd pmc2 RIO2 n JPMC2 RiO2P Gna 3 PMC2 ROS N PMC2RIOS P leni PMC2RO4N PMC2R
5. This provides maximum filtering and signal decoupling between the XMC modules and the carrier board However the boards are considered non isolated since thereis electrical continuity between the PCle bus and the XMC module power supply returns Therefore unless isolation is provided on the XMC module itself the field I O connections are not isolated fromthe PCle bus Care should be taken in designing installations without isolation to avoid ground loops and noise pickup Thisis particularly important for analog I O applications when a high level of accuracy resolution isneeded 12 bits ormore Contact your Acromag representative for information on our many isolated signal conditioning products that could be usedto interface tothe XMC input output modules All metalwork on this product will be connected to chassis ground whichis isolated from the board ground However this does not guarantee isolation as other components in yoursystem may interconnect these two grounds All system integrators should check all ground connections to prevent any current from running though the VPX4820 chassis ground 21 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER 3 VPX CONNECTIVITY VITA 65 PROFILES The VPX4820 and VPX4820CC match the following VITA 65 Module Profiles MOD6 PER 1Q 12 3 5 1 and MOD6 PER 1Q 12 3 5 2 The profile chart forthis board isas follows Utility Plane f P1 Not Used User Defined Utility Plane lt
6. or one x8 port and twox4 ports PCI and PC X Compliant Each slot supportsup to 133MHz 64 bit PCI X Upstream and NT Port Configuration Selectable via jumper 1 O Support both Front and Rear I O CC model is Rearl Oonly Single Power Supply The carrier only requires VPXto provide 12V to PS1 The carrier will generate and supply the PMC XMC modules with 5V and 3 3V The XMC VPWR pins are connected to 12V This board can also run off only the VPX PS3 5V supply Please contact the factory for details All VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER AUX supplies are optionaland are only required if used by the XMC PMC modules XMC PMC Power Dissipation 25W for eachslot JTAG Programming Header The VPX4820 carrier includes a programming connector that mates with a Xilinx programmer for programming Acromag FPGA products Acromag XMC FPGA boards can be configured to route the JTAG programming signals through the XMC P15 P25 connectors PCle REF CLKs Out PERICOM PI6C20800S21 PCle Clk Drvr PCIe Clk Demux PI3PCIE3422 Cle MUX IPISPCIE3422 Cle MUX PCle x4 PCle x4 PCle x4 PCle x4 PCle x4 PCle x4 TSi384 PCle PCT TSi384 PCle PCT PCI PCI Regulators DC DC Power PMC XMC SITE 1 LEPROM PCle Switch 32 lane O T ABORT OFT ART i PMC XMC SITE 1 V
7. AL 0 00 teeth i eee vete be te eee es 29 Certificate of Volatility z s it veda e aen ERE Peres 30 6 REVISION ISO Vii E 30 The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness fora particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall systemdesign It is agreed between the Buyer and Acromag that this is the Buyer s responsibility VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER 1 GENERAL INFORMATION KEY VPX4820 FEATURES The VPX4820 card is a 6U VPX non intelligent XMC PMC carrier board designed forPCle bus connectiontothe VPX Expansion Plane The board supports upto a 16x PCle connection that is selectable viajumpers The
8. Acromag kd THE LEADER IN INDUSTRIAL 1 0 Carrier Card Series VPX4820 VPX4820CC VPX XMC PMC Carrier USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 2014 Acromag Inc Printed inthe USA Data and specifications are subject to change without notice 8501 010A VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Contents 1 GENERAL INFORMATION 4 KEY VPX4820 FEATURES ER 4 2 PREPARATION FOR USE cccccccssssssseecececenecsseseececessenscsseseececesecaesseeeececessenseuseseseseesecagseetsessessens 6 UNPACKING AND INSPECTION 2 eine id 6 CARD CAGE CONSIDERATIONS sessseseeeeeeeeeee nennen nennen n nnne nensi i inen nensis E renes ness nnns 6 Board Conff g rati OD cur are ein Peg Ese amade Nor Eas Pe AA 6 UMPER c 7 CAMERA AS 7 PCie Upstream Port Selec A 8 PEE GON O Cia E 8 PCie NT Port Enable 5 u een a euere 8 PEIE NT Port Select nase eh ri iR Medshendd wee 8 FO AU POWER ee ee ee ee eier 9 JTAG Reference POWSr eite ee de Re 9 Clock Settings ERI eo HIER eie dee 9 PEPA MIMI eee eo ee ee are 9 hd o e 10 zb OCA Un 10 BACKPLANE KEY 10 CONNECTOR ce
9. C XMC modules within the voltage tolerances specified Adequate air circulation must be provided to prevent atemperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation isin an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering Power should be removed from the board when changing jumper configurations or when installing an XMC or PMC module cables and field wiring VPX CARRIER CARD SERIES JUMPERS PCle Lane Configuration VPX4820 PCle XMC PMC CARRIER There are three jumper blocks located on the board The jumper blocks are labeledJ1 J2 and J3 Within each jumper block are five jumpers Jumper one is marked as showninthe diagram above Referto Error Reference source not found above The description for each jumperis describedinthe tables below The jumper position is OPEN if no jumperis present The jumper position is SETif a jumperis present across the two pins For rugged designs all jumpers can be replaced withOOhm resistors Please contact the factory for details Figure 2 Jumper and Connector Locations Bold Selections are the factory defaults The VPX P2 PCie lane configuration is selectable via the first and second jumperofJ1 Please note that these strapping settings can be overwritten via a l C write to the PLX8632 Table 2 1 PCle Lane Jumper Configuration OPEN 8x 4x 4x
10. CIE L5 RXN Gnd PCIELS TXP Pcie L5 TxM Gnd 7 cie L6 RXP PCEL6 RXN Gnd Pcie LG TXP PCIE L6 TXN o Gn 9 cie 18 RXP Pcie 18 RXN Gnd PCiEL8TXP JPCIE L8 TXN 10 and PCIE L9 RXP_ PCIE Lo RXN Gnd PCIE to xp PCIE Lo Txn Gn Gna Peieu _rxp PCIE 111 RXN end PCIE tii TxP PCIE 111 TXN i i o Gn 8 ena pPciet7 RXP PCIE L7 RXN Gnd JPCIEIZ TxP PCIE L7 TXN PCIE L10 RXP PCIE L10 RXN Gnd Pce L10 TXP PCIE L10 TXN Gn O a Q PCIE L14 RXP PCIE 114 RXN Gnd PoE L14 TXP PCIE_L14_TXN Gnd PciEL1S RXP Pcie L5 RXN lena PCIE t15 TXP Pcie L15 TXN Gnd All blue colored cells are Not Usedin this design Table 2 13 P3 PMC SLOT A Rear I O Pin Loc D E F e 1 PMCLRIOLN PMCLROIP ond Pmca Rioo n emca Roop nd 2 na MCI Rios N pemci Rios P nd 2 PMCLRIO2 n pmciRio2 P ond 3 pwci mos EE 5 PMCi R09 6 PMC1 RIO7 N PMCi RIO7 P Gnd PMCi RIO6 n PMC1 RIO6 P nd P G PMCI Rios N PMCi RIOS P Ind PMCI RIO4N MCiRIO4P ond _ G P MCi RIO9 N PMCi RIO9 P Gnd PMCLRIOS N PMCLRIOSP Ind MC1_R1011_N PMC1 RIO11 Pond PMCI RIO10 N PMC1 RIO10 P 8 linda PMCLRIO15 N jPMC1 RIO15 P Gnd PMC1 RIO14 N PPMC1 RIO14 P 9 MCLRIO17 N PMCLRIO17 P cend Pmca RIO16 N PMCL RlO16 P nd 10 and PMCi RIO19 N PMCi RIO19 P Gna PMC1 RIO18 N PMC1 RIO18 P 12 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER
11. ECIFICATIONS PHYSICAL Physical Configuration Length naaa 9 187 inches 233 35 mm Maximum Heightoocccccocnnnccnnconnccnononnccnonannnnns 6 299 inches 159 99 mm Maximum Width essen VPX4820 0 8 inchair cooled 1 0 front panels available upon request PEIRHERE VPX4820CC 0 8 ConductionCooled Connectors Refertothe Connector Section located early in this manual for pin outs Jumpers JB1 JB2 and JB3 Control PCie strapping signals clk setup and JTAG powersettings Referto the Jumper section located earlierin this manual for more information POWER Board power requirements are a function of the installed XMC module and of the carrier card The carrier board supports upto four powersupplies from the VPX Backplane 12V 3 3V_AUX 12V_AUX 12V AUX The 5V and 3 3V supplies forthe XMC PMC modules are generated by on board DC DC converters from the 12V backplane supply Currents specified are for the carrier board only for Model VPX4820 add the XMC module currents for the total current required from each supply The major power components are listed belowto assist with power calculations Table 5 1 VPX4820 Internal Power usage typical Voltage PCle Switch PCle PCIBridge Watts Power from 12V Pio 284 28W zw sv osa os ow 4x om sw 2w Pav om ow 0672Ww 1 Assume 8096 from on board DC DC 2 Assume 16 la
12. ER CARD SERIES APCe8675 PCle XMC CARRIER Certificate of Volatility Certificate of Volatility Acromag Model Manufacturer VPX4820 L Acromag Inc VPX4820 LF 30765 Wixom Rd VPX4820 CC L Wixom MI 48393 VPX4820 CC LF Volatile Memory Does this product contain Volatile memory i e Memory of whose contents are lost when power is removed Yes m No Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed m Yes No Type EEPROM User Modifiable Function Process to Sanitize Flash etc m Yes Storage of Code IPMI Clear Memory by erasing EEPROM No information Note device is empty when firstshipped Type EEPROM Size User Modifiable Function Process to Sanitize Flash etc 4096x8 bit m Yes Storage forinitialization Clear Memory by erasing EEPROM No of PCle Switch PEX8632 Note device is empty when firstshipped Type EEPROM Size User Modifiable Function Process to Sanitize Flash etc 4096x8 bit Yes Storage of Code for Not Applicable EEPROM m No PCle PCI bridge TSI384 Device is not populated in default build 6 Revision History The following table shows the revision history for this document EGR DOC Description of Revision 14 MAY 2014 INITIALRELEASE 30
13. MC See derating information below While Acromag can test temperature with a given thermal dissipation we do not guarantee that the individual chips on the XMC PMC boards will not go into thermal shutdown Each XMC PMC module used must be fully rated at the temperature and power usage specified and MUST be connected to the midplane on conduction cooled frame for maximum effectiveness The two charts below give the maximum power dissipation per slot for both air cooled and conduction cooled boards Forair cooled boardsitis assume air flow of at least 200cfm is module across the module Conduction cooled conditions assume a 6U Conduction cooled chassis with the first 3adjacent slots populate with power board CPU and the VPX4820 Thetestboard was an XMC and PMC module modified with power resistors to induce specific 27 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER currents The Resistors are provided a direct cooling path to either the conduction cooled ring or the midplane Air Cooled Power Dissapation 2 2 SS o a put o o a CC Card Edge Temperature Maximum Power W per Slot PCle BUS COMPLIANCE Specification cccccccesssssseeees This device meets or exceeds all written PCI Express specifications per revision 2 0 Note PCle Gen 2 signal rates exceed the rated bandwidth of the XMC connectors While testing to Gen2 signals was completed Acromag cannot certify Gen2 compliance wi
14. O4P end 4 ond pmc2 rioz N PMC2RIO7P nd PMC2 Rios N PMC2 Rios P Jona 5 PMC2RIO9 n pmc2 Rioo P leni Ipmc2 rios n pmczriogp nd 6 nd pMcz R11 N PMC2 RiO11 P end PMC2 RIO10 N PMC2 RIO10 P Gnd 7 pmcz R13 N PMC2 R13 P ond PMC2 RIO12 N PMC2 RIO12 P Gnd f 8 ond pmczfio1sN pmczRIo1s P ond PMC2 RIO14 N PMC2 RIO14 P Gnd 9 pmc2 m1 N pPMC2 mO17P ond pmc2 RIO16 N PMC2 RIO16 P Gnd 11 pwc2 R21 N PMC2 RiO21 P ond PMC2 RIO20 N PMC2 RIO20 P Gnd 13 lpmc2 mo25 w eMc2 mo2s P ond pmca O24 N PMc2 rioza P end 13 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Fin A B c D E F jG 14 nd PMC2_RIO27 N PMC2_RIO27 P Gnd PMC2_RIO26_N PMC2 RIO26 P 15 PMC2 RIO29 N JPMC2 RIO29 P Gnd Pmc2 RIO22 N pmc2 RIO28 P and 16 and PMC2 RIO31 N JPMC2 RIO31 P Gnd PMC2 RIO30 N PPMC2 RIO30 P All blue colored cells are Not Usedin this design Table 2 16 P6 XMC SLOT B Rear I O Pin A B c bD j t r jG 1 kwc2 pPos N XMC2 DPOS P ond xmc2_ DPO4 N XMC2 DPO4 P nd 2 na men pov N kwca peor P ena lxmc2_ppos n Ixmc2 beoe P and 3 wc pro9_N wc posp nd mczpros_w mcz peos e end 4 jond kxmc2pp1sN XMC2 pPis P and XMC2 DPl4 N XMC2 DP14 P land 5 XMC2DP17 N XMC2 DP17 P nd xMC2DP16N XMC2DP16 P ond 6 Ind kmc2_pp19 N XxMC2 pPi9 P na 2 xmc210819 Ixmc2 10 A19 land 7 mcz pr
15. PX Backplane Figure 1 Block Diagram VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER 2 PREPARATION FOR USE UNPACKING AND INSPECTION iW CAUTION SENSITIVE ELECTRONIC DEVICES DO MOT Sit On STORE NEAR ETRONG DEA etn CARD CAGE CONSIDERATIONS Board Configuration Upon receipt of this product inspectthe shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the cartonis opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power The board utilizes static sensitive components and should onlybe handled at a static safe workstation Refer tothe specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed PM
16. ackplane Assume 8A used to generate 43 3 5 0V supplies 2 Deratingis required above this temperature due to DC DC See Power dissipation section below Note that extra allowance of 0 5A is available on the CC modules due to the addition of a heat sink Power dissipation isa complicated issue onthe carriercard The maximum allowable die temperature is 125 C for the critical components on the board Beyond this point the DC DC and the PCle switch will automatically be disabled to prevent overheating Furthermore thermal restrictions on the DC DC IC s for 3 3V and 5 0V supplies will limit supply current to the XMC PMC modules dependent on ambient temperature As such as you proceed to calculate maximum power dissipation you take into consideration how much 3 3V and 5 0V power you are using as well as the overall power usage The first two charts give the Amperage derating for 3 3V and 5 0V supplies For conduction cooled boards Acromag limits the maximum powerto0 5A above the 85C limit This will guarantee full functionality over the full power rating of the XMC PMC modules 26 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER 3 3V Derating uv c pan m 3 o 5 0V Derating O e N U A Ui DN OO OO Assuming that your XMC PMC current supply requirements are met then you can move to the total XMC PMC power dissipation calculation Power Dissipation 25W Maximum per XMC P
17. carrier enables the use of XMC and PMC mezzanine I O modules The carrier card acts as an adapter to route PCle bus signals between the PCle bus of your backplane and either P15 connector of an XMC module card or P11 and P12 of a PMC Card Access to rear I O is provided through connections to the backplane XMC and PCM modules with front I O can be accessed though the front mounting bracket The VPX4820 seriesis a 6U VPX Non Intelligent XMC PMC carrier board designed for 4x 8x 16x PCle bus connection The carrier card uses a PLX Technology PCle Switch Chip PEX 8632 and IDT Technology PCle to PCI Bridge Chip TSI384 to interface between the VPX PCle bus and one XMC PMC mezzanine I O module card Model VPX4820 is an air cooled product which can be used for front and rear 1 0 XMC PMC mezzanine modules Model VPX4820CC is an extended temperature conduction cooled product which supports all Acromag FPGA modules It only supports Rear I O Board Size Operating Temperature Length Range VPX4820 0 to 70 C VPX4820 CC 40 to 85 C 1 See Power Specifications for further information including power rating 2 Both boards are available in leaded L orlead free LF version PCI Express Interface Up to Sixteen PCI Express Gen 10r Gen 2 lanes are connected tothe VPXP2 connecter Thisisthe Expansion Plane Lane configuration isjumper selectable PCI Express Configuration Jumper selectable for one x16 port two x8 ports fourx4 ports
18. ed Table 2 20 Jx4 PMC PCI Rear I O Signals Pin Description Number Pin Description Number Ror 3 or 6 RO2N 7 ROBN 8 Rop o Rop w momN 39 NosN 1 In VPX Connector pinouts P3 P5 the name is preceded by PMC1 or PMC2 depending on Slot 17 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER XMC Connectors Table 2 21 Jx5 XMC PCle Signals Pin Description Number Pin Description Number A D4 4 A18 D18 REFCLGGO WAKE PETOnO MEM E E1 E2 B16 18 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Pin Description Number Pin Description Number Table 2 22 Jx6 XMC Rear I O Signals Pin Description Number Pin Description Number Gp ae om os ano A8 GNb os Dep A9 oor bs D10 GND au GND Dia oap as se bis GND Ato GND L srisp fa m Po DPi amp P Am oop Dm oon Bi ovan E ano amp GN e DN s won B 19 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Pin Description Number Pin Description Number GN e con Es pon so oon E Eis 1 In VPX Connector pinouts P4 P6 the name is preceded by XMC1 or XMC2 depending on Slot 20 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER FIELD GROUNDING CONSIDERATIONS Carrier boards are designed with passive filters on each supply line to each XMC PMC module
19. neoperation Typical 3 Per PMC SlotUsed Typical 12 Volts 4596 esses 900 mA typ 2A Maximum 12V AUX 12V AUX not used Supplied to PMC XMC modules only 3 2M AUX ana 25mA typical 50mA maximum Sequencing eocccccccnoccnnccnoncnnnnnnnos All powersupplies will ramp up with 400us of bus power Onboard supplies will ramp up together once VS1 12V has exceeded 2 5V Note that there is no onboard detection to determine if 12V is within specification 25 VPX CARRIER CARD SERIES XMC PMC Power Power Dissipation VPX4820 PCle XMC PMC CARRIER The maximum power provided to the XMC PMC modules is limited due to onboard DC DC converters Both the 3 3V and 5V supplies are generated on the carrier board The total limits forthe supplies are provided inthe table below Be sure to add up supplies for both XMC PMC and do not exceed the limits below Note that each DC DC can provide upto 12A inrush Exceeding these limits will cause the on board supplies to automatically shut down Furthermore never exceed using more then 1A per power pin on the PMC XMC modules Resistance losses can mount when more then 1A per powerpinis used and Acromag can nolonger guarantee that the voltage falls within specification Table 5 2 Total Power Available for PMC XMC modules Voltage Total Power On board usage Derating Available above A wv e 3 3V_AUX 1A 0 05A NA bay aux m oosa na gt 1 From b
20. o1_N mcz prosp ond mczproow kwczpeooP end 8 jond mc2_ppo3 N xMC2 pPo3 P end XMC2 DPO2 N XMc2 DPO2 P land 9 Xwc2 op N XMC2 Pli ani xMC2DP10_N mcz oprop nd ul ge med 12 feng fm o o ss ch i All blue colored cells are Not Used in this design PMC Connectors Table 2 17 Jx1 PMC PCI Signals Pin Description Number Pin Description Number wx 1 uw 2 INTAR NT 5 me e SUS MODERA 7 v s no 9 NC 1 VAR GNTE REO AD3I AD28 AD27 ADS C BESH AD22 ADA ADIS 14 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Pin Description Number Pin Description Number frames 35 GN 34 oo s ww x ows 37 38 pa m Nc 1 NC Not used Table 2 18 Jx2 PMC PCI Signals Pin Description Number Pin Description Number TRST TVs TDO SUSMODENS 15 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Pin Description Number Pin Description Number meN 47 Am 48 as e 9x 3 a ss o ss s Nc s GND s p oe aem ea 3334 gt a e e NC Not used Table 2 19 Jx3 PMC PCI Signals Pin E in Desfption Number ano gt Se ee NN cs s vas 6 ce 7 ND 8 33v o a o wc s Nc 6 16 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER Pin Description Number Pin Description Number 1 NC Not us
21. peed If you insert and XMC module it will automatically be detected via the MPRESENT signal and disable the PMC PCI interface Vice versaif no XMCis present the PCI Interface to the PMC module is enable If no PMC module is detected then the PCle to PCI bridge will go into low power mode since it is unused Rear I O is compliant to VITA 46 9 Slot A is mapped P3w1 P64s P4w1 X12d X8d SlotB is mapped P5w1 P64s P6w1 X12d X8d VPX4820 0 to 70 C VPX4820CC 40 C to 85 C Max card edge temp 85 C 5 95 non condensing 55 to 100 C IEC 60068 2 6 10 500 Hz 5G 1 Hours axis IEC 60068 2 64 10 500 Hz 5G rms 1 Hours axis IEC 60068 2 27 30g 11 ms half sine 18 shocks at 6 orientations The PCle bus and the XMC module commons have a direct electrical connection Assuch unlessthe XMC module provides isolation between the logicand user I O signals the user I O signals are not isolated fromthe PCle bus Chassis Ground is electrical isolated floating from all digital power grounds on the board All metal work is attached is chassis ground Designed to comply with IEC61000 4 3 class A Not required for signal I O per European Norm EN61000 6 1 Designed to comply with IEC61000 4 4 class A Designed to comply with CISPR 16 2 3 class A Designed to comply with IEC6100 4 2 Level 2 Conducted Radio Frequency Interference PB Content cocccccoccncnncncnninincnnano Designed to comply with IEC6100 4 6 class A 29 CARRI
22. quipment that thoroughly checks the performance of each board Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation for Use have been followed Also referto the documentation of your carrier board to verify that it is correctly configured Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate afaulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our website contains the most up to date product and software information Go to the Support tab to access Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 295 0310 Fax 248 624 9234 Email solutions acromag com 24 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER 5 SP
23. sers also have the option to use a clock fromthe VPX backplane Note that this must be a 100MHz clock for proper operation Refer tothe table below for jumper settings Table 2 9 ClockJumper Settings GlobalClockSource 121 322 23 On Board Crystal OPEN OPEN OPEN The PEX8632 PCI switch can alternately be programmed via a simple 1 C bus The lC is accessed via the System Bus pins on the VPX backplane VPX CARRIER CARD SERIES NVROM LED s BACKPLANE KEY CONNECTORS VPX4820 PCle XMC PMC CARRIER Furthermore the lC bus is connected to both XMC modules For further information on programming using the 1 C bus contact the factory The NVROM signal from the VPX Backplane is routed to the PCle Switch EEPROM as well as both XMC modules The VPX4820 has several status LEDS Referto Figure 2 for the location of the LED s These LED s are primarily used forinitial power up status The table below describes the functionality Table 2 10 LED LED Color 5 S s12 Green VPX PCIe Port 2 has successfully connected Sia Green A Connection has been made toXMC PMCSlotA rosie Red Fatal Error non recoverable 0517 Red Red Red 55 Red PMCA Only Ple Lane 4has connected Red Red Red Red The VPX4820 is not keyed and will pluginto any VPX backplane Priorto powerup verify that VS1is 12V Any other voltage on VS1 may damage the board Refer to Error Reference so
24. t be enabled viajumpers J3 1for these jumper to operate properly Please note that these strapping settings can be overwritten via al C write to the PLX8632 VPX CARRIER CARD SERIES 3 3 AUX Power JTAG Reference Power Clock Settings lC PROGRAMMING VPX4820 PCle XMC PMC CARRIER Table 2 6 PCle NT Port Jumper Selection PdeNTPot 332 193 0 OPEN OPEN SET The 3 3V_AUX poweris required for proper operation of this board For users without this power supply available on the VPX backplane you can alternatively use the onboard generated 3 3V Table 2 7 3 3V_AUX Power Select Jumper Settings Source of 3 3V AUX 14 185 Backplane OPEN SET WARNING The J3 4 and 5 jumpers should both never be set This could cause damageto either the board or chassis power supply The pull up voltage on the JTAG pins to XMC P15 and P25 can be selected as either 2 5V or 3 3V Referto the XMC User s Manual for propervoltage selection The forth jumperinJ2 is for slot A and the fifth jumperinJ1is for slot B Table 2 8 JTAG Power Select Jumper Settings JTAG Ref Voltage loc semg SET 3 3V OPEN 2 5V J1 5 SET 3 3V OPEN 2 5V There are several clock options availableforthe user These optionsare seton the first second and third jumpers of J2 The default selection is to use the on board crystal to generate the 100MHz PCle clock This frequency is propagated to all parts and XMC modules U
25. th non Acromag products SWItCh iced A PLX Tech PEX8632 Gen 2 0 PCle switch is used forthe routing of PCle signals The Maximum PCle trace length on XMC module 500mils Recommended for Gen2 compliance 28 VPX CARRIER CARD SERIES SYSCLK Requirements ifused PCI BUS COMPLIANCE Specification ooocccccononcnnconoo XMC PMC Slot Selection Auto negotiate ee Rear I O SpecificatiON ooocccccoonccnnconoo ENVIRONMENTAL Operating Temperature Storage Temperature Sinusoidal Vibration Random Vibration Operating Shock PCie Non Isolated Chassis Ground eee Radiated Field Immunity Surge Immunity ElectricFast Transient Immunity Radiated Emissions Electrostatic Discharge VPX4820 PCle XMC PMC CARRIER Jumper selectable between VPX POSYSCLK and an on board generated clock 100MHz 200ppm Jaws ur 3 1ps RMS Jams r 3 0ps RMS This device meets or exceeds all written PCI specifications per revision 3 0 and PCI X revision 2 0 PCI will operate at 33Mhz or 66HZ PCI X will operation at 66MHz or 133MHz at either 32 or 64 bits Other operational frequencies are available contact the factory for details PCle PCI X and PCI offer auto negotiation for bus width and s
26. urce not found for connector locations Connectors on the VPX4820 carrier consist of six VPX Backplane connectors then 2 XMC connectors and four PMC connectors foreach slot These interface connectors are discussed in the following sections 10 VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER J11 J12 J13 J21 122 J23 PMC PCI signals 1147125 eiae S PMC usersignals Rear 1 0 A ee e XMC PCIe signals 116 1265 A ina XMC usersignals Rear1 O PO iip VPXPowerand system signals Pc oen EE ERN E VPX Data Plane This connectoris not populated p VPX Expansion plane This connects to all PCle lanes A nie PMC XMC Slot A Rear I O PO Pitt PMC XMC Slot B Rear I O VPX CARRIER CARD SERIES VPX4820 PCle XMC PMC CARRIER VPX Connectors Table 2 11 PO VPX Utility Signals A B c D E F G 3 bv w Nc jev ev w wv 6 pao fa ono HavAUX eNo 6 amp 2 GS s fono aer BUS p rer BUS NoD PO RECI All blue colored cells are Not Usedin this design Table 2 12 P2 VPX Expansion Plane Pin c D E F 1 PciE Lo RXP PCIE LO RXN Gnd PCIE LO TXP PCIE LO TXN 2 ena PotEiiRXP PCIE Li RXN Gnd poea TXP PCIE Li TXN Gnd PCIE L5 3 cie ia exp PCEI2 RXN Gnd Pae 12 TXP PCIEL2 TXN Gnd Pc e ws RXP Pcie L3 RXN ond Paes TXP pcie 13 TXN Gn 5 pere La RXP CIE LA RXN od PCIE La TXP JPCIE L4 TXN O Q 6 end PciELs RXP P
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