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1. 395 800 OTHER PUBLICATIONS Intel 86 88 186 188 User s Manual Hardware Reference 1985 pp 1 63 1 65 and 1 110 to 1 112 Computer amp Software News vol 6 Issue 32 p 26 Aug 8 1988 Peck Robert A Expanding Your Apple s Applica tions Byte Dec 1984 pp A45 A47 A122 A126 Moskowitz Robert Appli card Enhancing Your Apple Interface Age Aug 1983 pp 107 111 Heck Mike Quadlink Running Apple Software on IBM PC Interface Age May 1984 pp 108 110 Morganstein David ALF s 8088 Coprocessor Byte Dec 1984 pp A38 A43 386SX 387SX Board Design with Neat Chips 250 Product Alert Chips and Technologies Inc Sep 1988 Update on Neat Plus SX Module Product Alert Chips and Technologies Inc 1989 Gal Q Data Book Lattice Semiconductor Corpora tion Spring 1988 pp 1 31 Y Shimazu et al LSI Research and Development Laboratory Mitsubishi Electroc Corporation 24 bit Floating Point Digital Signal Processor mSP2 Mar 25 1988 pp 49 54 Primary Examiner Parshotam S Lall Assistant Examiner Richard Lee Ellis Attorney Agent or Firm Mason Fenwick amp Lawrence 57 ABSTRACT A system and method for upgrading a computer is dis closed Certain essential chips present in the original computer system are functionally but not physically removed from the computer system The functions which would
2. OUT EO 6 Bier o gt 387 gt NPPRESZ A O 23 gt Sheet 5 of 7 5 297 272 Mar 22 1994 U S Patent 10 122 A vie 9 8 9 80 4 a Holes 22 V Old 7124 22 gg 2 7 U S Patent Amm 0 25 ND 9 Lx 85 a ees aa eA Naa 6 D 6 769 N a8 GND 71 uS I s Ww s EAT 3 Sareea Aj 78 Mm m 5 a Ses i meee L GND 8 AB s ss 20 86 8 vec vec 8 RB rN 825 901 GNB S ENT UE SINTR gt _ _ 191 2 Rr SEES HLDA 9 f OO Q READY 1021 92 B L SND 14 K20 OO C GND 107 O8 iex c Ene KOZME _ JENCLK2SMB 13 Y GND I n A Mar 22 1994 Q e z m e 4 2 Sheet 6 of 7 5 297 272 D LI SBHES gt 6 10 C MIO ATL iii T 2 RESETS Esra Es 26 QUITE T AUTOR Sr XSTINT Ent REPREQ EE EDS RINT ko m u i i 1222002 021020 i 20 _ D4 ig ni DLD D po 2r OO n T LDLo DEO 15J FIG 4 Sheet 7 of 7 5 297 272 Mar 22 1994 U S Patent VS 9 4 914 lt LSNIXS bOdbL JINGOW NI 9nd W
3. 202 20 90 D8 D8 DATA 5 GND GND GND 91 VCC 6 GAL 206 13 92 D7 D DATA 7 READY SXREADY GATE 221 3 OUTPUT 93 D6 D6 DATA 8 VCC 94 D5 D5 DATA 9 vcc 55 95 D4 D4 DATA 10 VCC VCC 96 D3 D3 DATA 11 GND GND GND 97 VCC vec 12 GND GND GND 98 GND GND GND 13 GND GND GND 99 D2 D2 DATA 14 GND GND GND 100 D1 15 CLK2 386CLK2 INVERTER 211 OUTPUT 60 16 ADS ADS PULLED UP 80386SX 47 ADS GAL 206 3 17 A0 AO ADDRESS 2 TABLE II 18 A1 1 ADDRESS 80387SX Pin Connections 19 BHE 386BHE PULLED GAL 8 206 9 80387SX ee 65 Pin Label Signal S urce Dest 22 GND GND GND 23 SXH IO PULLED UP GAL 206 5 2 D7 D7 DATA GAL 8 202 14 3 D6 D6 DATA 4 VCC 80387SX 44 NPS1 5 297 272 17 18 TABLE IlI continued TABLE II continued 80387SX Pin Connections 80387SX Pin Connections 803875 80387SX Pin Label Signal Source Dest Pin Label Signal Source Dest 5 GND GND gt FLIP FLOP 232 12 6 D5 Ds DATA INPUT 7 D 4 D4 DATA 37 VCC 8 D3 D3 DATA 38 GND GND GND 9 VCC VCC 39 TIE HIGH 11 DIS DIS DATA 40 STEN PULLED HIGH 12 D14 014 10 41 W R W R 80386SX 25 W R 13 VCC 42 GND GND GND 14 GND GND GND 43 VCC 15 DI3 013 DATA 44 NPSI SXM IO 803865X 23 M IO 1
4. A signal also input to the 80386SX indicating that a cycle is over The signal is generated by combinatorial logic in FIG 3 illustrated as logic elements 221 and 222 Briefly the purpose of logic elements 221 and 222 are to govern the state of the SXREADY ff signal This signal is governed by three inputs The two gates 221 and 222 function equiva lently to a 3 input active low OR gate The first input is the READY signal generated from the chip set on the system board The function of this READY is published and therefore readily available to those skilled in the art The second input is the 387RDY signal which is a signal output by the 80387SX chip at pin 57 signal READYO Its function similarly is published and is therefore available to those skilled in the art 20 25 30 35 40 45 50 55 65 6 A third input to the combinatorial logic is the signal output f rom pin 14 of the GAL 206 As be seen f rom the 206 logic equations Appendix A this signal is activated during a halt instruction or a shut down This signal is needed because the NEAT TM chip set would not provide a signal in these circumstances caus ing the system to hang indefinitely The system would hang were it not for the fact that the SXREADY signal can be activated by the signal from pin 14 of the 206 GAL In the preferred embodiment the function of a three input active low OR gate is implemented using two
5. Pin 5 OUTFO This signal is generated on the system board and is involved in the write cycle of the I O Port F0 Here it is used as a co processor status signal The INTEL Application Note B3 STEP 80387 0 _ 5 30 45 50 55 60 65 5 297 272 8 stepping information p 11 describes the use of this signal Pin 6 387BUSY This signal is generated by the 80387SX and functions in a manner known to those skilled in the art Pin 7 REFREQ This signal is generated on the system board and functions in a manner known to those skilled in the art Pin 8 387PEREQ This signal is generated by the 80387SX and functions in a manner known to those skilled in the art Pin 9 337ERROR This signal is generated by the 80387SX and functions in a manner known to those skilled in the art Pin 10 ERRLTCH This signal is a latched error signal which is generated at the data output of a second D type flip flop 232 to be described in greater detail below Pin 11 NPPRES This signal is normally pulled high by means of a 10K pull up resistor on a single in line package 201 FIG 3 The signal is also con nected to ground signal 66 on the 80387SX socket In the preferred embodiment this is used as a signal to inform the rest of the circuit of the presence of an 80387SX chip in the socket Pin 14 SXM IO This signal is one of the three signals defining the present cycle as belonging to one of eight categorie
6. 40 INTR 49 GND GND GND 94 NMI 80386SX 38 NMI 50 GND GND GND 95 GND GND 20 51 A2 A2 ADDRESS 96 52 A3 A3 ADDRESS 97 HLDA 80386SX 3 HLDA 53 A4 A4 ADDRESS 98 HOLD FLIP FLOP 231 2 54 5 5 ADDRESS D IN 55 A6 A6 ADDRESS 99 GND GND 56 7 A7 ADDRESS 100 25 57 VCC 101 58 A8 8 ADDRESS 102 READY GATE 221 2 QND 59 A9 A9 ADDRESS INPUT 60 AIO 10 ADDRESS 103 GND GND 61 11 All ADDRESS 104 62 A12 A12 ADDRESS 105 30 63 GND GND GND 106 CLK20UT 32MHz XTAL OSC 209 64 A13 A13 ADDRESS THRU RESISTOR 65 14 14 ADDRESS 107 GND GND 66 A15 A15 ADDRESS 108 67 GND GND GND 109 PROCCLK INVERTERS 211 212 68 GND GND GND INPUTS 35 69 VCC 70 16 16 ADDRESS 111 GND 71 VCC VCC 112 ENCLK32MB JUMPER 241 1 to 72 A17 A17 ADDRESS GND 73 A18 A18 ADDRESS 113 ENCLK25MB JUMPER 242 1 to 74 19 19 ADDRESS GND 75 A20 CPUA20 ADDRESS BIT 20 114 SXINST GND 40 76 21 21 ADDRESS 115 GND GND 77 GND GND GND 116 78 GND GND GND 79 A22 A22 ADDRESS 80 A23 A23 ADDRESS 81 D15 D15 DATA TABLE II 45 82 D14 D14 DATA 80386SX Pin Connections 83 D13 D13 DATA 803865 84 Pin Label Signal Source Dest 85 GND GND GND 86 D12 Di DATA 1 DO DO DATA 87 DH DATA 2 GND GND GND 50 88 10 D10 DATA 3 HLDA HLDA CONNECTOR PIN 97 89 D9 D9 DATA 4 HOLD HOLD386 GAL
7. Ultimately this prevents the chip set on the system board from responding when it should not re spond The outputs of GAL 206 will next be described Pin 13 NA This Next Address signal is impor tant to an understanding of an advantage of the present invention As a background to understanding the importance of the signal it should be appreciated that imple menting the plug in card for the 80386SX upgrade causes a problem to arise because of the difference in the definition of the status signals output by the 80386SX which start its cycles certain known system trans lates the 80386SX status signals to an 80286 format However this known implementation of the status sig nal translation causes time to be lost resulting in re duced system performance 803865 has an input signal named NA which be used to request the CPU place the Next Ad dress onto the bus to begin the next cycle before the current cycle has completed In the known translation scheme referred to immediately above the NA signal is either active all of the time or is never active When is always active it is necessary to employ four 74F373 latches with latch control logic so as to latch 7 address and status signals to maintain them in proper time relation for the system board chip set This known translation scheme does not utilize the NA signal to its fullest advantage As appreciated by the present inventio
8. sclk amp ready amp reset ireset amp Ireset amp g Ireset t Ireset g Ireset amp g ireset amp g Ireset g Ireset 2 Ireset t g Ireset g Ireset amp 9 Ireset 69 busstate idle active amp ads amp sclk amp Ireset 69 amp reset 2 GAL R Equations for Second GAL R 202 Figure Mf module MUS1SX FLAG R2 title 387sx 5 297 272 23 24 Engineer DT Date 5 5 89 LOCATION U81 PUB1SX device P20V8R inputs CLK PIN 1 32 MHZ CLOCK CHOLD PIN 2 RESET3 PIN 3 RESETS PIN 4 OUTFO PIN 5 N9BUSY 6 REFREQ PIN 7 N9PEREQ PIN 8 NOERROR_ PIN 9 ERRLTCH PIN 10 NPPRES PIN 11 NMIO 14 A23 PIN 23 OUTPUTS NBUSY_ PIN 15 PEREQ PIN 16 NPRESET PIN 17 SCLK 18 NRESET3 PIN 19 NHOLD PIN 20 RSTERR PIN 21 6 22 EQUATIONS SCLK SCLK NRESET3 15 amp RESET3 ISCLK amp RESETS SCLK t NRESET3 5 297 272 25 26 NPRESET SCLK amp RESETS SCLK t NPRESET NBUSY N9BUSY_ ERRLTCH 0000 NPPRES_ amp REFREQ NHOLD SCLK amp CHOLD SCLK amp NHOLD IRSTERR_ RESETS OUTFO PEREQ x N9PEREQ N9BUSY amp ERRLTCH IG NPPRES_ NMIO 1423 END MUSISX 25 Conclusion From the above it is apparent that many modifica tions and variations of the present invention are possible in light of the above teachings It is therefore to be understood that within the scope of th
9. two input 74FO8 NAND gates connected in series output of gate 222 is input to the first input of the second gate 221 The second input of gate 221 receives the READY signal Gate 222 receives the 387 READY f signal and the signal from pin 14 of the 206 GAL The output of gate 221 constitutes the SXREADY signal Pin 5 SXM IO Pin 6 D C and Pin 8 W R These three status signals generated by the 80386SX define which category of the eight cycle categories is presently being executed A definition of the cycle cate gories is published and therefore available to those skilled in the art Pin 7 SCLK A signal generated at pin 18 of the second GAL R 202 used to maintain the phase rela tionship for generating signals SO and 51 at pins 16 and 17 of the first GAL 206 The SCLK signal pro vides for a division by two of the clock signal from in the preferred embodiment 32 MHz to 16 MHz Pin 9 386 BHE A Byte High Enable signal gener ated by the 80386SX governing a choice of operating on only 8 of 16 bits for example on devices having only 8 bit data lines Pin 11 HLDA A Hold Acknowledge signal gener ated by the 80386SX causes the outputs of GAL R 206 to enter a high impedance state Pin 12 NPCS This input to the first GAL 206 is identified at pin 22 of the second GAL R 202 The signal described below is active only if the present cycle is a co processor cycle and a 387 processor is installed
10. 212 FIG 3 which signal is also driven through a 33 ohm series resistor This 387CLK2 signal is the inverted form of the PROCCLK clock signal generated on the system board The two signals 386CLK2 and 387CLK2 are advantageously filtered to remove noise from the clock signal Such filters are advantageously implemented using a series combination of an 82 picofarad capacitor and a 240 ohm resistor to ground Separate capacitor resistor filters should be used for the two clock signals 386CLK2 and CLK2 It is advantageous to pull up certain signals to insure that they are at required levels It is preferable to implement the pull up function using a single in line package SIP of 10K resistors with one common end tied to VCC The signals which are indi vidually tied to respective 10K resistors include the following W R output from the W R signal on pin 25 of the 80386S X processor The D C signal output f rom the D C signal on pin 24 of the 80386SX processor The SXM IO signal output from the M IO pin 23 of the 80386SX processor The ADS signal output from the ADS output pin 16 of the 80386SX processor 5 297 272 11 The 386BHE signal output from the BHE pin 19 of the 80386SX processor The 387RDY signal output from the READYO out put pin 57 of the 80387SX co processor The 387BUSY signal output from the BUSY output pin 36 of the 80387SX co processor The 387ERROR signal output from the PEREQ out put pin 56
11. a pre determined constant signal level and 2 a pathway to which the first input of the first processor is responsive 27 The upgraded computer system of claim 26 wherein the installation announcement circuit consists essentially of a short circuit pathway extending between 1 ground and 2 a pathway to which the first input of the first processor is responsive 28 The upgraded computer system of claim 23 wherein the first processor has associated therewith a first bus with first bus characteristics the second processor has associated therewith a sec ond bus with second bus characteristics and the module includes means to ensure full compatibil ity between the first bus characteristics and the second bus characteristics I 29 base computer system with modular upgrade capability in which installation of a module which is not originally part of the base computer system caused disablement of a first processor without its physical removal from the computer system while allowing a second processor on the module to assume functions which would otherwise be performed by the first pro cessor the base computer system having an expansion bus with a set of expansion bus signal paths the base 5 207272 31 computer system comprising a the first processor having a first input which when activated disables the first processor b means for providing a disabling signal to the first input of the first processor i
12. activated acknowledges disablement of the first processor the system further comprising c an acknowledgement isolation circuit including 1 an input responsive to the first output of the first processor 2 an output which may either be i responsive to the first output of the first pro cessor ii rendered inactive and 3 an enable input responsive to the installation announcement signal for controlling whether the output of the acknowledgement isolation circuit is responsive to the first output of the first pro cessor or whether it is rendered inactive 5 The system of claim 3 wherein the first processor is part of a first integrated circuit chip and the OR circuit is separate from the first integrated circuit chip 6 The system of claim 3 wherein the first processor is part of a first integrated circuit chip and the OR circuit is part of a second integrated circuit chip which is separate from the first integrated circuit chip 7 The system of claim 3 wherein the OR circuit employs a negative logic in which any input signal causes the output of the OR cir cuit to be active 8 The system of claim 3 wherein the first input of the first processor is an input which when activated does not disable the first processor until the end of a current instruction cycle 9 The system of claim 3 wherein the first input of the first processor is an input which when activated causes
13. an acknowledgement isolation circuit including 1 an input responsive to the first output of the first processor 2 an output which may either be i responsive to the first output of the first pro cessor or ii rendered inactive and 3 an enable input responsive to the installation announcement signal for controlling whether the output of the acknowledgement isolation circuit is responsive to the first output of the first pro cessor or whether it is rendered inactive 33 The system of claim 29 wherein the first processor is part of a first integrated circuit chip and the providing means is separate from the first inte grated circuit chip 34 The system of claim 29 wherein the first processor is part of a first integrated circuit chip and the providing means is part of a second integrated circuit chip which is separate from the first inte grated circuit chip 35 The system of claim 29 wherein the providing means employs a negative logic in which any O input signal causes the output of the providing means to be active 36 The system of claim 29 wherein the first input of the first processor is an input which when activated does not disable the first processor until the end of a current instruction cycle 37 The system of claim 29 wherein the first input of the first processor is an input which 32 when activated causes the first processor to acti vate a hold acknowledge output signal
14. disables the first processor b means for providing a disabling signal to the first input of the first processor in response to 1 a first signal generated from within the base computer system the first signal causing disablement of the first processor when the first signal is active and a module is not installed in the base computer sys tem or 2 an installation announcement signal output by the module when the module is installed into the base computer system the installation an nouncement signal thereby causing functional dis ablement of the first processor so as to allow the second processor to assume functions otherwise performed by the first processor wherein the means for providing the disabling signal constitutes means for providing the disabling signal only to the first processor and to portions of the base computer system other than the expansion bus which por tions if not disabled would interfere with the sec ond processor s assuming functions otherwise per formed by the first processor and C a path for carrying the installation announcement signal to the means for providing the path being electrically separate from the expansion bus signal paths 18 The system of claim 17 wherein the first processor is part of the first integrated circuit chip and 1 the providing means is separate form the first inte grated circuit chip 19 The system of claim 17 wherein the first processor is part of a first integra
15. is achieved using a tri state buffer 324 to whose 1 Sg vo input the 287INT signal from the 82C211 is fed The 40 D4 DATA SXINST signal generated on FIG B1 is high when 41 5 DATA the 80386SX plug in module is installed thereby dis 40 25 ve TATAN abling tristate buffer 324 Control of the NPINT net 44 D7 DATA connected to the output of the tristate buffer 324 is thus 45 D8 DATA surrendered to the inverter 214 FIG 3 described p T above 48 D10 DATA As described above the flip flops 231 and 232 and 409 Dil DATA gates 213 222 and 214 contribute to control the co a 22 processor interface handling error conditions and 52 DB DATA clocking the signals as needed for proper functioning 53 D14 DATA when the 80386SX plug in module is installed 50 2 VEG vend In addition to the systems described above the pres 56 D9 DATA ent invention also provides a method for upgrading a 57 computer system having a system board including a first E OND UND processor the first processor having a first input which 60 0 ADDRESS when activated causes the first processor to be dis 55 61 Al ADDRESS abled the method comprising retaining the first proces s am sor the system board retaining the system board 64 ADDRESS the computer system and installing a plug in module 65 A4 ADDRESS into the computer system the plug in module compris 66 A ADDRESS ing a second processor having at le
16. of the 80387SX co processor and The NPRES which is treated as effectively being an output from the normally grounded input pin 66 of the 80387SX co processor used as an input to pin 11 of second GAL 202 FIG 3 to report the pres ence of an 80387SX processor in the co processor socket 203 on the plug in module The 387PEREQ signal normally output from the PEREQ output pin 56 of the 80387SX co processor is tied low through a 10K resistor to ground so as to put the signal in a known low state when the 80387SX co processor chip is not inserted The default low state of this 387 signal is designed to insure compatibility The connections between the 80386SX processor and the 80387SX co processor will next be presented The W R output pin 25 of the 80386SX processor generates the W R signal which is input to the W R pin 41 of the 80387SX co processor The M IO output pin 23 generates the SXxM IO signal which is input to the NPS1 input pin 44 of the 80387SX co processor The ADS output pin 16 of the 80386SX processor generates the ADS signal which is input to the ADS input pin 47 of the 80387SX co processor Any other connections of the input or output pins of the 80386SX processor or the 80387SX co processor may be found through inspection of FIG 2 and or Tables II and Referring now to FIGS 5A and 5B the portions of the circuitry of the system board which are of special interest to the present
17. of the plug in module s connector 114 Preferably a 12 ohm resis tor is inserted in series to provide proper loading char acteristics connection of signals from the 80386SX plug in module and the system board is made through the con nector which is shown as 114 in FIG 4 Also Table I presents the connector pin connections in conjunction with the schematic signal names and source destination names of the signals as they are generated or received on the plug in and system boards Those skilled in the art upon inspection of the figures and associated tables are able to implement the preferred embodiment of the enhanced computer system according to the present invention 15 25 30 35 40 45 50 65 10 Pins 112 and 113 of connector 114 receive the ENCLK32MB and ENCLK25MB signals respec tively In the preferred embodiment each of these two signal lines are tied directly to ground during operation Jumpers 241 and 242 are not needed operationally but are used during the development phase for flexibility In the preferred embodiment when the signals are low tied to ground the corresponding clock either 32 MHz or 25 MHz is disabled These signals are used on the system board to enable a desired clock For exam ple the 80286 processor functions on a 12 5 MHz clock which is derived from the 25 MHz clock enabled by the ENCLK25MB signal Conversely when an 803865 processor from the plug in module is act
18. system As described more generally above the effective removal of the 80286 processor from the system board 20 25 30 35 40 45 65 12 by the simple insertion of a plug in module is a central feature of the present invention Using a very small number of logic gates as shown in FIG 5A the func tional removal of the 80286 processor without necessi tating its physical removal from the system board con stitutes a significant advance in the art placement into the hold state of the 80286 pro cessor causes the HL DA output signal on pin 65 to become active The activation of the HLDA signal should be masked to prevent any circuits receiving it from believing that no processor at all was in control of the system In f act according to the teachings of the present invention the functional disablement of the 80286 processor on the system board is accompanied by the simple insertion of another processor such as an 80386SX on a separate plug in module The presence of the 80386SX processor masks the activated HLDA signal from the 80286 processor on the system board in the following manner Referring again to FIG 5A the SXINST signal generated near the plug in board connector 114 as a result of the plug in module s insertion is fed to inverter 312 Inverter 312 produces an active high SXINST signal to indicate that the 80386SX plug in module is installed When the SXINST signal is active high it disables
19. 1 of second GAL 202 The second flip flop 232 generates a data output signa ERRLTCH which drives two inputs The first input has already been described above the pin 10 input to second CAL 202 second input of NAND gate 223 The first input of gate 223 is the 387ERROR Z signal which is generated by the output pins ERROR on the 80387SX The output of NAND gate 223 drives the input of inverter 214 The output of inverter 214 produces signal NPINT numeric processor interrupt which is sent to the system board tied to the output of a tri state buffer 324 FIG B2 Speaking conceptually the flip flop and logic ar rangement just described causes a numeric processor interrupt immediately if there is an error detected be cause of the direct connection of the 387ERROR signal to the input of NAND gate 223 Also an inter rupt is generated if the 387 BUSY signal is clocked into the flip flop 232 by the rising edge of the inverted 387ERROR signal as it becomes active As described above the latch 232 is pre set by the RSTERR signal generated at pin 21 of second GAL amp 202 Next the clock selection arrangement and the con nector for the preferred plug in module for the 80386SX upgrade These features are illustrated in FIG 4 Referring now to FIG 4 a commonly employed 32 MHz high frequency crystal oscillator is shown at loca tion 209 The 32 MHz clock oscillator at 209 produces the CLK2OUT signal which drives pin 106
20. 286 processor This allows the rest of the computer system to be spoofed into believing that an 80286 processor may still be present and operating in the computer system In particular the computer sys tem is still AT TM compatible The following is a description of the signals which are input and output to GAL 206 A brief description of the origin function and destination of certain signals is presented However most of the signals are used in a manner consonant with their use on the 80286 system board so that those skilled in the art would readily appreciate the implementation and use of the signals on the preferred plug in module according to the present invention Referring to FIG 3 the input and output signals of GAL amp 206 will first be described Pins 1 through 9 11 and 12 are input signals pins 13 through 19 are output signals Pin 1 386 CLK2 An inverted form of the signal PROCCLK from the system board In inverter 211 FIG 3 inverts PROCCLK to account for the fact that the 80286 processor triggers on the negative edge of its clock signal while the 80386SX triggers on its positive edge Pin 2 RESET 386 A clock reset signal originating directly from the second GAL R 202 described in greater detail below Pin 3 ADS An address strobe signal generated by the 80386SX used to indicate that a new cycle has begun or that a new address and status signals have been presented on the bus Pin 4 SXREADY
21. 38 An upgraded computer system having an expan sion bus with a set of expansion bus signal paths the 5 upgraded computer system comprising 20 25 35 40 50 55 60 1 a first processor having a first input which when activated disables the first processor 2 a module installed in the computer system the module including a second processor and an instal lation announcement circuit for generating an stallation announcement signal whenever the mod ule is installed in the computer system 3 a first path being electrically separate from the expansion bus signal paths for carrying to the first input a disabling signal determined by the installa tion announcement signal so that installation of the module causes disablement of the first processor without its physical removal from the computer system the first path carrying the disabling signal leading only to portions of the computer system which if not disabled would interfere with the second processor s assuming functions otherwise performed by the first processor and 4 a second path being electrically separate from the expansion bus signal paths for carrying the installa tion announcement signal from the module to acti vate the disabling signal wherein the installation announcement circuit gener ates the installation announ ent signal to cause disablement of 1 a disable acknowledge signal indicating disablement of the first processor to th
22. 6 D12 Di2 DATA 45 NPS2 A23 ADDRESS BIT 23 19 DO DO DATA 46 VCC vcc vcc 20 Di DI DATA 15 47 ADS ADS 80386SX 16 ADS 21 GND GND GND 48 CMD A2 ADDRESS BIT 2 22 VCC 49 READY SXREADY GATE 221 3 OUTPUT 23 D2 D2 DATA 50 HIGH VCC vec 24 D8 D8 DATA 51 RESET RESET387 GAL 202 17 25 GND GND GND 53 387CLK2 26 VCC 20 54 386CLK2 387CLK2 INVERTER 212 4 OUTPUT 27 GND GND GND 55 GND GND GND 28 D9 D9 DATA 56 387PEREQ TO GND THRU IK 29 DIO D10 DATA RESISTOR 30 D1 Dil DATA GAL 6 202 8 31 VCC vcc 57 READYO 387RDY PULLED UP GATE 222 13 32 GND GND GND 34 QND INPUT 33 VCC 58 vec vec 34 GND GND GND 59 PULLED HIGH 35 ERROR 387ERROR PULLED UP GAL 202 9 0 GND GND GND GATE 223 4 FIRST L GND GND GND INPUT GATE 213 5 62 VEC NCC VEC RR WE T e 36 BUSY 387BUSY PULLED UP GAL 6 202 6 66 GND NPRES PULLED UP GAL 202 11 APPENDIX A 3 Equations for First 206 Figure AM Name Partno XXXXXX Location 01 Revision Assembly XXXXXX gi vB FORMAT j 7 Date 06 23 89 Designer N HACK Company ALR Inputs pin 1 9 11 pin 12 Outputs elk reset lads ready mio dc sclk wr bhe oe Ig 5 297 272 19 20 19 16 pipecyc Ibuscyc mods1 mods0 15 13 Imodbhe hltrdy n
23. OU a HONGO TONI cle 4 Wx ZHW 2 90 6 Sszljit GOW NI SfT1d WOu4 HAWEA TINI JINGOW NI 9Nd 110212 V iNIdN 1 1341282 226 UCE vO S ZHW Q 0H SE GG 6 NI2W19 OLE 12528 5 297 272 1 APPARATUS FOR AUTOMATICALLY DISABLING AND ISOLATING A COMPUTER S ORIGINAL PROCESSOR UPON INSTALLATION OF A PROCESSOR UPGRADE CARD BACKGROUND OF THE INVENTION 1 Field Of The Invention The present invention relates to computer systems which are performance upgrades of other computer systems More specifically the invention relates to com puter systems in which one or more important elements such as the central processing unit of a known com puter system are replaced with elements having higher performance characteristics 2 Related Art It is known in the art that given computer systems may be upgraded in performance through substitution of elements The new elements have higher perfor mance capabilities than elements in the original system For example in the field of personal computers the TM computer available from International Business Machines Corporation Armonk N Y is known This known computer operates using an 80286 processor and an 80287 math co processor available from for example INTEL Inc of Santa Clara Calif Other manufacturers have since designed computer systems which although still compatible with
24. United States Patent Lu et al Ill US005297272A 11 Patent Number 4 Date of Patent 5 297 272 Mar 22 1994 54 APPARATUS FOR AUTOMATICALLY DISABLING AND ISOLATING A COMPUTER S ORIGINAL PROCESSOR UPON INSTALLATION OF A PROCESSOR UPGRADE CARD 75 Inventors Gene Y Lu San Clemente David L Kelly Mission Viejo Norman M Hack Tustin Scott R Rushford Huntington Beach all of Calif 73 Assignee Advanced Logic Research Inc Irvine Calif 21 Appl No 388 445 22 Filed Aug 2 1989 51 Int C5 eese GO6F 15 76 52 U S CI nee 395 500 395 800 364 DIG 2 364 929 2 364 929 5 364 929 71 58 Field of Search 364 200 MS File 900 MS File 395 800 500 56 References Cited U S PATENT DOCUMENTS 4 530 066 7 1985 Ohwaki et al 364 708 4 531 198 7 1985 Matsuda 395 575 4 562 535 12 1985 Vincent et al 395 325 4 680 674 7 1987 Moore 361 395 4 703 419 10 1987 Krause et al 364 200 4 716 526 12 1987 Mori et al 364 200 4 794 523 12 1988 Adan et al 364 200 4 882 702 11 1989 Struger et al 364 900 4 885 482 12 1989 Sharp et al 307 465 4 967 346 10 1990 Freidin 364 200 4 997 377 3 1991 Goto et al 439 68 5 040 990 8 1991 Suman et al wee 439 34 5 109 517 4 1992 Houda et al
25. al Sdefine idle b 00 define active b 10 define pipelined b 11 define notall 01 memr mem mio amp wr halt mio amp wr amp de mio amp wr H i ior imio amp H memory write or halt iow mio amp wr inta mio amp amp dc field busstate buscyc pipecyc sequence busstate present idle if g amp ads amp sclk amp Ireset next active default next idle e present active if reset next idle if 7 lads 6 sclk amp Ireset amp ready next idle if 9 ads amp sclk amp ireset amp Iready next pipelined default I next active present pipelined 2 a if ready 8 amp Ireset next active if reset next idle default next pipelined present notall DA next idle H mods0 d amp busstate idle ads amp sclk t ireset amp g t busstate active amp ads amp sclk amp ready amp Ireset amp g amp busstate pipelined amp sclk amp ready amp Ireset amp g halt amp busstate idle amp ads amp sclk amp Ireset amp g halt busstate active amp ads t amp ready amp Ireset amp g halt 4 busstate pipelined 5 297 272 21 inta busstatezidle amp ads t inta amp busstate active amp ads amp sclk amp ready amp Ireset inta iow amp busstate idle iow t busstate active iow t busstate pipel in
26. ast certain perfor 4 ADDRESS mance characteristics different than performance char 69 A7 ADDRESS acteristics of the first processor and an installation an b ER e S nouncement circuit for generating an installation an gt 9 ADDRESS nouncement signal when the plug in module is installed 65 73 A10 ADDRESS in the computer system in which method the installa z PEOPLE tion of the plug in module into the computer system 76 12 ADDRESS causes functional disablement of the first processor 77 A13 ADDRESS 15 TABLE I continued Concordance For Signals For 80386SX Plug In 5 297 272 16 TABLE II continued 80386SX Pin Connections Connector Signal Plug in Module 80386SX Pin Name Connection 5 Pin Label Signal Source Dest 78 Al4 ADDRESS 24 D C D C PULLED UP GAL 206 6 79 GND GND 25 W R W R PULLED UP GAL 206 8 80 15 ADDRESS 80387SX 41 W R 81 16 ADDRESS 26 LOCK 82 17 ADDRESS 32 VCC VCC 83 GND GND 10 33 RESET RESET386 GAL 202 19 84 18 ADDRESS 34 BUSY BUSY386 GAL 202 15 85 19 ADDRESS 35 GND GND GND 86 CPUA20 80386SX A20 36 ERROR VCC THRU RESISTOR ADDRESS 20 37 PEREQ PEREQ386 GAL amp 202 16 87 GND GND 38 NMI NMI CONNECTOR PIN 94 88 A21 ADDRESS 15 39 VCC vcc 89 A22 ADDRESS 40 INTR INTR CONNECTOR PIN 93 90 A23 ADDRESS 41 GND GND GND 91 GND GND 42 VCC 92 48 VCC VCC 93 INTR 803865
27. base computer system cause disablement of a first processor without its physical removal from the computer system so as to allow a second processor on the module to assume functions otherwise performed by the first processor the base computer system having an expansion bus with a set of expansion bus signal paths the base computer system comprising a the first processor having a first input which when activated disables the first processor b an OR circuit having an output signal which is input to the first input of the first processor the OR circuit having respective inputs responsive to 1 a first signal generated from within the base computer system the first signal for causing disablement of the first processor when the first signal is active and a module is not installed in the base computer system and 2 an installation announcement signal which is generated when the module is installed into the base computer system the installation announce ment signal being restricted to a path in the base computer system which is electrically separate from the expansion bus signal paths thereby causing functional disablement only of the first processor and of minimal portions of the base computer system to allow the second processor to assume functions otherwise performed by the first processor and c the path which carries the installation announce ment signal to the OR circuit 12 The system of claim 11 wherein the first
28. e remainder of the computer system as well as 2 a co processor interrupt which if not disabled would interfere with the operation of the second processor 39 The upgraded computer system of claim 38 wherein the first input is a HOLD input 40 The upgraded computer system of claim 38 wherein the installation announcement circuit is located out side an integrated circuit chip in which the second processor is located 41 The upgraded computer system of claim 38 wherein the installation announcement circuit includes a short circuit pathway extending between 1 a pre determined constant signal level and 2 a pathway in which the first input of the first processor is responsive 42 The upgraded computer system of claim 41 wherein the installation announcement circuit includes a short circuit pathway extending between 1 ground and 2 a pathway to which the first input of the first processor is responsive 43 The upgraded computer system of claim 38 wherein the first processor has associated therewith a first bus with first bus characteristics the second processor has associated therewith a sec ond bus with second bus characteristics and the module includes means to ensure full compatibil ity between the first bus characteristics and the second bus characteristics 44 A base computer system with modular upgrade capability in which installation of a module which is not originally part of the base co
29. e appended claims the invention may be practiced otherwise than as specifically described What is claimed is 1 An upgraded computer system comprising 1 a system board including at least a part of a first chip set the first chip set including 80286 processor chip having a HOLD input the 80286 processor chip having status and con trol signals of an 80286 timing and format b an 82C211 chip and C a numeric processor interrupt disable circuit receiving an interrupt signal from the 82C211 chip 2 an 80386SX plug in module including 80386SX processor socket in which is inserted an 80386SX processor chip the 80386SX proces sor chip having status and control signals of an 80386SX timing and format b an 80387SX co processor socket translation circuitry which translates status and control signals from the 80386SX timing and format to the 80286 timing and format the trans lation circuitry including programmable arrays of logic elements whose composite function is determined by programming a plurality of equa tions thereinto d a numeric processor interrupt circuit which generates a plug in numeric processor interrupt signal under certain conditions a first clock selection circuit which determines the characteristics of clock signal which is used by clock generation circuitry within the 82C211 chip and f an installation announcement circuit the installa tion announcement circuit inc
30. ed busstate pipelined t ads amp sclk 50 t Isclk amp lreset mods 1 8 hitrdy d modbhe d 22 amp sclk amp ready amp ireset amp amp ireset 6 5 amp ready amp ireset t amp ireset amp amp ads amp sclk amp ready t reset amp amp sclk amp ready amp reset amp memr amp busstatesidle amp ads amp sclk t memr amp busstate active amp ads amp 5 amp ready amp memr amp busstate pipelined T sclk amp ready halt amp busstate idle amp ads amp sclk 4 halt amp busstate active amp ads 6 sclk amp ready t halt amp busstate pipelined amp sclk amp ready amp inta amp busstate idle amp ads amp sclk amp X inta amp busstate active amp ads amp sclk amp ready amp inta amp busstate pipelined amp sclk amp ready amp ior amp busstate idle t ads t sclk ior amp busstate active amp ads amp sclk amp ready amp ior t busstate pipelined amp sclk amp ready amp modsi amp sclk amp ireset nat sclk amp Ireset hltrdy amp sclk amp ireset bhe amp busstate idle bhe t busstatesactive X bhe amp busstate pipelined modbhe t ready amp Ireset X modbhe amp tsclk amp ireset APPENDIX B 1 amp modsO t mio amp wr amp dc amp sclk t ireset amp ads amp sclk amp ads 4 sclk amp ready amp reset amp
31. em perfor mance will be enhanced in accordance with the perfor mance characteristics of the circuit elements on the plug in module 102 In one preferred embodiment for example the 80286 processor 106 on the existing system board 104 is func tionally replaced by an 80386SX processor 108 Also the 80287 co processor 110 may be functionally re placed by an 80387SX co processor 112 The connector 114 may be for example a connector available from Burndy Corporation of Norwalk Connecticut In this manner the simple addition of a plug in module 102 enhances system performance while not sacrificing the AT TM compatibility of the system as originally config ured with only system board 104 It is understood that partial functional replacement is encompassed by the present invention That is not every essential chip on the system board 104 need be replaced functionally by a corresponding enhanced circuit on the plug in module 102 Certain sub sets of the essential chips may be enhanced Also the simple insertion of the plug in module need not be the only means of communicating to the rest of the system that the function of certain elements of the system board 104 are being usurped It lies within the contemplation of the present invention that hybrid up grades involving combinations of the plug in module and or replacement or modification of the system board and or addition of a supplementary board with a cable leading to the origina
32. er the known solution yields a machine which is fully AT TM com patible Referring now to FIG 5B the 82 211 is shown with timing and logic elements to achieve the timing and interrupt functions described above The third input of the jumper 304 is driven by The CLK20UT signal is generated on the plug in module A middle conductor on the jumper 304 functions as the output of the jumper so that the jumper effectively functions as a selector choosing either the 32 MHz crystal locally generated for developmental testing not or operationally the CLK20UT clock generated on the plug in module by the 32 MHz crystal oscillator 209 FIG 4 The middle 5 297 272 13 14 output pin of jumper 304 connected during operation TABLEI to the clock from the plug in module drives the input of non inverting tristate buffer 322 preferably eU a ea RES Signal Plug in Module 74F 125 The output of buffer 322 is connected in com Pin Name Connection mon to the output of another tristate buffer 323 At any 1 BHE GAL 206 15 given time at most one of these two buffers is activated 2 50 GAL 206 16 so as to control their common output 3 Md DAL Runs crystal oscillator 306 with 25 MHz frequency 5 Te drives the input of second tristate buffer 323 preferably 10 6 M 10 80386SX 23 M IO through a 33 ohm series resistor An inverter 313 pref Ves Sa 9 206 5 erably a 74F04 receives the ENCLK25MB signal 8 Ma _ generated o
33. essor and portions of the computer system which if not disabled would interfere with the second processor s as suming functions otherwise performed by the first processor c translation circuitry making a bus of the first processor compatible with a bus of the second processor and d means for allowing the second processor instal lation announcement circuit and translation cir cuitry to operate properly 5 297 272 35 wherein the installation announcement circuit gener ates the installation announcement signal to cause disablement of 1 a disable acknowledge signal indicating disablement of the first processor to the remainder of the computer system as well as 2 a co processor interrupt which if not disabled would interfere with the operation of the second processor 57 The computer system of claim 56 wherein the module s second processor is an integrated circuit chip and the module has cache memory outside the inte grated circuit chip 58 The computer system of claim 56 wherein the translation circuit includes arrays of logic ele ments which are responsive to signals on the re spective busses of the first and second processors and which provide other signals to the respective busses of the first and second processors 59 The upgraded computer system of claim 24 wherein the installation announcement circuit is located out side an integrated circuit chip in which the second processor i
34. h the 80286 processor is not removed from the system board The system powers up with the 80286 as the CPU After powering up however system control is relinquished to the processor on the new board through what is commonly known as the master mode The master mode involves use of the DMA controller to request control of the external AT TM bus allowing the card to be master of the system This third method possesses the drawback that true AT TM system compatibility is sacrificed True com patibility cannot be maintained because the card is func tioning on an external bus and not directly on the CPUI bus Therefore there is a need in the computer industry for systems and methods for upgrading known com puter systems which do not involve unnecessary cost inconvenience for the user or customer or introduction of features which are incompatible with any industry standards adhered to by the original computer system Further it is desirable to provide a system and method whereby a given computer system may be upgraded without the necessity of physically removing or replac ing any portion of the original computer system so as to minimize inconvenience and possibility of electronic or physical damage It is further desirable to achieve these goals while maintaining compatibility with industry standards and maintaining system reliability SUMMARY OF THE INVENTION The present invention provides a system and method for overcoming t
35. he disadvantages of known computer upgrade systems The present invention provides a sys tem and method for upgrading a computer in which certain essential chips present in the original computer System are functionally but not physically removed from the computer system The functions which would otherwise be performed by the original chips are instead performed by higher performance chips on a plug in module which is plugged into the computer system Advantageously the mere insertion of the plug in module ensures that the original chips are disabled in favor of the enhanced chips present on the plug in mod ule Also advantageously no chips from the original computer system need be removed or replaced Of still further advantage is the full compatibility with industry standards which were adhered to by the original com puter system Another advantage is the ability to effect a change in clock speed through mere insertion of the plug in module 5 297 272 3 Thus the present invention envisions a computer system taken as a whole which is an upgrade of an earlier computer system The present invention also encompasses a plug in module which is capable of up grading a given computer system Furthermore the invention encompasses methods for upgrading a given computer system using a plug in module which easily and quickly replaces the functions of certain essential chips in the given computer system Other features and advantages of
36. he path being electrically separate from the expansion bus signal paths 45 The base computer system of claim 44 wherein the first input is a HOLD input 46 The base computer system of claim 44 wherein the means for disabling includes means for disabling 1 any disable acknowledge sig nal associated with the first processor as well as 2 any co processor interrupts which would other wise interfere with the operation of the second processor 47 The system of claim 44 wherein the first processor is part of a first integrated circuit chip and the providing means is separate from the first inte grated circuit chip 48 The system of claim 44 wherein the first processor is part of a first integrated circuit chip and the providing means is part of a second integrated circuit chip which is separate from the first inte grated circuit chip 49 The system of claim 44 wherein the providing means employs a negative logic in which any input signal causes the output of the providing means to be active 50 The system of claim 44 wherein the first input of the first processor is an input which when activated does not disable the first processor until the end of a current instruction cycle 51 The system of claim 44 wherein the first input of the first processor is an input which when activated causes the first processor to acti vate a hold acknowledge output signal 52 A base computer system with m
37. hysical removal from the computer system while allowing a second processor on the module to assume functions which would otherwise be performed by the first processor the base computer system having an expansion bus with a set of expansion bus signal paths the base computer system comprising the first processor having a first input which when activated disables the first processor b an OR circuit having an output signal which is input to the first input of the first processor the OR circuit having respective inputs responsive to 1 a first signal generated from within the base computer system the first signal for causing 5 297 272 27 functional disablement of the first processor when the first signal is active and a module is not installed in the base computer system and 2 an installation announcement signal output by the module when the module is installed the installation announcement signal being restricted to a path in the base computer system which is electrically separate from the expansion bus sig nals paths thereby causing functional disable ment only of the first processor and of minimal portions of the base computer system to allow the second processor to assume functions other wise performed by the first processor and c the path which carries the installation announce ment signal to the OR circuit 4 The base computer system of claim 3 wherein the first processor has a first output which when
38. in 15 BUS Y386 This signal is input to the BUSY input of the 80386SX Equations for generation of the above output signals from second GAL 202 are presented in the equations of Appendix B Those skilled in the art are readily able to understand and implement a GAL performing the 5 297 272 9 above functions given the present description and the accompanying equations Referring now to the logic components 213 223 and 214 which are connected to D type flip flops 231 and 232 entry listed above the control of the numeric processor interface for the 80387SX will now be de scribed The data input of flip flop 231 receives the HOLD signal from the system board The HOLD input is clocked into 231 by signal 386CLK2 which is an in verted version of the clock PROCCLK itself generated on the system board The active low clear input of the flip flop 231 is tied high Flip flop 231 produces the CHOLD signal which is input to pin 2 of second GAL 202 Second flip flop 232 receives its data input from the 387BUSY signal generated by the 803875 BUSY output The clock input of flip flop 232 is received from the output of inverter 213 The input of inverter 213 receives its input from the 387ERROR signal output from the ERROR output pin 35 of the 80387SX The clear input of the second flip flop 232 is tied high As described above the pre set input of second flip flop 232 is driven by the RSTERR signal generated by 2
39. invention will next be described FIG 5A illustrates a preferred mechanism in which the 80286 processor on the system board is placed in a hold state so as to allow the 80386SX processor on the plug in module to take control of the system FIG 5A illustrates the 80286 processor as element 358 Inverter 311 preferably a 74F04 NAND gate 331 preferably 74F00 inverter 312 preferably 74F04 and tristate buffer 321 preferably a 74F125 are illus trated in the following configuration The HOLD sig nal output from HOLD output pin 55 of the NEAT TM 82C211 FIG 5B is input to inverter 311 The inverted HOLD signal from inverter 311 is input to the active low input of gate 331 920 The other input of gate 331 is governed by the SXINST signal generated on the plug in module when inserted into connector 114 As shown in FIG 4 the SXINST indicates to gate 331 FIG 5A when the 80386SX plug in module is in stalled When the 80386SX plug in module is installed pin 114 of connector 114 is grounded so that the second input of gate 331 is driven low into its active state The output of gate 331 signal NHOLD drives the HOLD input pin 64 of the 80286 processor In this manner either an activated SXINST signal from the plugged in 80386SX module when installed or the HOLD signal from the 82C211 chip can force the 80286 processor into a hold state Placing the 80286 processor into the hold state effectively removes it from the
40. ive then a 16 MHz clock derived from a 32 MHz clock is enabled by the ENCLK32MBfF signal The preferred circuitry by which the proper clock signal is selected is described in this specification in detail in the section relating to the system board circuitry illustrated in FIG B2 Referring now to FIG 2 the 80386SX processor and the 80387SX co processor are illustrated in a preferred configuration Table and Table recite the pin connections which are shown in FIG A1 Generally the signals are used in a manner known to those skilled in the art The accompanying drawings Table II and Table and the accompanying text allow those skilled in the art to implement the plug in module and the enhanced computer system according to the present invention Referring more specifically to FIG 2 it is seen that the following connections are made The active low ERROR input signal on pin 36 of the 80386SX proces sor is tied to VCC through a 1K resistor Similarly the STEN and CKM inputs of the 80387SX co processor are also tied high to VCC also through the 1K resistor The CLK2 input of the 80386SX processor receives the 386CLK2 signal from the output of inverter 211 FIG 3 driven through a 33 ohm series resistor The 386 CLK2 signal is the inverted version of the PROCCLK signal generated on the system board Similarly the 386CLK2 input on pin 54 of the 80387SX co processor receives the 387CLK2 signal which was generated by inverter
41. l processor slot and so forth In this manner upgrades of upgrades are possible The invention is not to be limited to a system configuration containing only the elements shown in FIG 1 Addi tional elements may be present and still fall within the scope of the appended claims even if the additional elements are involved in other performance enhance ment schemes 3 297 212 5 The details of operation of the embodiments of the present invention will next be presented Shown in FIG 3 are two logic devices 206 and 202 These logic devices may be implemented using a variety of circuits but generic array logic GAL and pro grammable array logic PAL 8 chips are preferred In the exemplary illustrated embodiment GAL chips 206 and 202 are GAL 16V8 15 and GAL 20 8 15 respec tively available from Lattice Semiconductor Corpora tion P O Box 2500 Portland Ore 97208 555 N E Moore Court Hillsboro Ore 97124 See GAL DATA BOOK Lattice 1988 As is known in the art certain GAL chips such as the V series from Lattice Semiconductor Corporation advantageously allow the outputs to be either combinatorial or registered allow ing design flexibility and minimization of IC count Briefly GAL amp 206 converts signals such as status and control signals from the 80386SX format and tim ing into other e g status and control signals which are readily usable by circuits expecting format and timing from an 80
42. luding a connec tion from an SXINST pin on a plug in connec tor to ground the connection from the 30 35 40 45 SXINST to ground providing an installation announcement signal to which the 80286 proces sor is responsive whenever the plug in module is installed the installation announcement signal causing disablement of the 82086 processor with out its physical removal from the system board while allowing the 80386SX processor to assume functions in the computer system otherwise per formed by the 80286 processor the installation announcement signal also causing the numeric processor interrupt disable circuit to prevent the interrupt signal from the 82C211 from reaching any portion of the computer system and 3 a connector in electrical contact with both the system board and the installed plug in module for carrying the SXINST signal from the installation announcement circuit on the 80386SX plug in module to control the HOLD input of the 80286 processor and the numeric processor interrupt dis able circuit on the system board 2 The upgraded computer system of claim 1 wherein the installation announcement circuit includes a con ductive pathway and includes no active circuit elements 3 A base computer system with modular upgrade capability in which installation of a module which is not originally part of the base computer system causes 55 functional disablement of a first processor without its 65 p
43. mputer system causes disablement of a first processor without its physical removal from the computer system so as to allow a 5 297 212 33 second processor on the module to assume functions otherwise performed by the first processor the base computer system having an expansion bus with a set of expansion bus signal paths the base computer system comprising a the first processor having a first input which when activated disables the first processor b means for providing a disabling signal to the first input of the first processor in response to 1 a first signal generated from within the base computer system the first signal causing disable ment of the first processor when the first signal is active and a module is not installed in the base computer system or 2 an installation announcement signal generated by the module whenever the module is installed in the base computer system so as to cause dis ablement of the first processor and allow the second processor to assume functions otherwise performed by the first processor c means for disabling signals generated in the base computer system 1 which if not disabled would indicate disablement of the first processor to the remainder of the base computer system or 2 which if not disabled would interfere with control exerted by the module and d a path for carrying the installation announcement signal to the means for providing and to the means for disabling t
44. n the function of beginning the next cycle before the current cycle has completed can be used to save the time lost in translating 80386SX status signals to status signals having the 80286 format In designs according to the present invention the NA signal is controlled to allow the release of the next ad dress when the changing of the address will not ad versely effect the functioning of the system board chip set This selective control of the NA input here fed directly from the NA output of first GAL 206 is achieved by simulating the timing of the 80286 proces sor which only guarantees the address to be valid dur ing limited timing periods In this manner the present invention provides an implementation of the status sig nal translation circuit using fewer IC s while not sacri ficing the speed which would otherwise be lost due to the translation process Pin 14 As described above with respect to the SXREADY f input on pin 4 the output of pin 14 is fed back to a gate 222 for ultimate generation of the SXREADY signal The generation of the 206 GAL output on pin 14 is determined according to the GAL equations in Appendix A Pin 15 BHE The byte high enable signal is also generated according to the equations in Appendix A and is sent to the system bus for governing cycles where only one of the two bytes is to be transferred Pin 16 SO and Pin 17 51 These status bits are generated according to the GAL equatio
45. n response to 1 a first signal generated from within the base computer system the first signal for causing disablement of the first processor when the first signal is active and a module is not installed in the base computer system for 2 an installation announcement signal output by the module whenever it is installed in the base computer system c means for disabling signals generated in the base computer system b which if not disabled would indicate disablement of the first processor to the remainder of the base computer system or 2 which if not disabled would interfere with control exerted by the module and d a path for carrying the installation announcement signal to the means for providing and to the means for disabling the path being electrically separate from the expansion bus signal paths 30 The base computer system of claim 29 wherein the first input is a HOLD input 31 The base computer system of claim 29 wherein the installation announcement circuit generates the in stallation announcement signal to cause disablement of 1 any disable acknowledge signal associated with the first processor as well as 2 any co processor interrupts which would otherwise interfere with the operation of the second processor 32 The base computer system of claim 29 wherein the first processor has a first output which when acti vated acknowledges disablement of the first processor the system further comprising c
46. n the 80386SX plugged in module The 313 9 inverter enables the local 25 MHz signal to reach the 10 z 24 VCC output of tristate buffer 323 when the system is to 15 RESET3 GAL 202 3 ate with a 12 5 MHz clock 13 RESET4 GAL 2024 The output node of the two tristate buffers 322 and K Veg eem 323 drives the CLK2IN input pin 5 of the 82C211 pref 16 S 2 erably through a 33 ohm series resistor m 17 In the above described manner the preferred cir 18 19 vcc cuitry selectively chooses between 25 MHz oscillator 20 OUTFO GAL 202 5 306 local to the system board when no plug in mod 21 387INT INVERTER 214 NPINT ule is present a 32 MHz oscillator 305 also local to UC 202 7 the system board used e g during development or 25 24 us the 32 MHz clock signal generated on the plug in board 25 advantageously used during operation when the plug 5 ve in module is installed 28 7 Referring to FIG 5B the NPINT output pin 4 of the 29 82C211 generates the 287INT signal For reasons analo 30 30 31 gous to those discussed above with respect to the 32 bh v HLDA hold acknowledge signal generated by the 33 80286 processor it is desirable to remove the 2871 s UC T m signal from the system when the 80386SX plug in mod 36 DI DATA ule is installed The functional removal of the 287INT 37 D2 DATA signal
47. ns in Ap pendix A and are sent to the system board for control of the function of defining the status of new cycles Pins 18 and 19 These two signals are associated with the state machine and serve the function of maintaining time relationship throughout the cycle As can be seen on FIG A2 the two signals NA f rom pin 13 of GAL 206 and the signal from pin 14 of GAL 206 are connected to respective resistors of value 1K ohms to VCC The signals entering and leaving second GAL 202 will next be described Pins 1 through 11 13 14 and 23 are inputs and pins 15 through 22 are outputs The inputs will first be de scribed Pin 1 387 CLK2 This signal is an inverted form of the PROCCLK signal generated on the system board It is essentially the same signal as the corresponding pin on first GAL 206 Pin 2 CHOLD The CHOLD signal generated by the data output of a D type flip flop 231 allows mainte nance of the proper clock relationships As will be de scribed below the CHOLD signal is a delayed form of the HOLD signal generated on the system board This signal functions as a request to the 80386SX to give a hold acknowledge and relinquish the data bus for such functions as direct memory accesses and refresh cycles Pins 3 and 4 RESET3 and RESET4 These signals are generated on the system board and generally serve as software invoked reset signals to the 386 and as power up signals to the 386 and 387 respectively
48. ocessor unit socket on the system board In a second upgrade method a circuit board containing a higher performance CPU is inserted into the CPU socket Both these methods involve the physical re moval of the 80286 processor from its socket These known methods possess several disadvantages The removal of a chip from the original processor board is not convenient for the user or customer In fact physical removal of the 80286 and insertion of the intercardconnecting cable or second board into the 10 15 20 25 30 35 40 45 50 55 60 65 2 original processor s socket may even cause physical electronic damage if not performed properly Furthermore it is generally known that increased performance may be obtained through increasing CPU clock speed These two methods involving insertion of a cable or board into the CPU socket do not provide for changing the clock speed To change clock speeds using either of these two known methods the crystal itself must be replaced Replacement of a crystal is both inconvenient and dangerous to components Both of the above described methods may decrease reliability due to introduction of unwanted signal noise into signals entering and leaving the CPU socket Also boards or cables plugged directly into the CPU socket may vibrate loose causing intermittent connections A third upgrade method involves placement of an add in board into the AT TM slot but in whic
49. odular upgrade capability in which installation of a module which is not originally part of the base computer system causes disablement of a first processor without its physical removal from the computer system so as to allow a 5 20 25 30 35 45 50 55 65 34 second processor on the module to assume functions otherwise performed by the first processor the base computer system having an expansion bus with a set of expansion bus signal paths the base computer system comprising the first processor having a first input which when activated disables the first processor b a first path for carrying to the first input a disabling signal determined by an installation announcement signal which is generated whenever the module is installed in the base computer system the first path leading only to the first processor and portions of the computer system which if not disabled would interfere with the second processor s assuming functions otherwise performed by the first proces sor and C a second path electrically separate from the expan sion bus signal paths for carrying the installation announcement signal from the module to activate the disabling signal wherein the first path leads only to the first proces sor to disable acknowledge signal gating means associated with the first processor and to co processor interrupt gating means which if not disabled would interfere with the operation of the
50. or and replacement of their function ing with either an 80386SX based plug in module or a 80486 based plug in module processor chips and docu mentation available from INTEL order numbers 240187 002 and 240225 002 respectively However the teachings of the present invention should not be limited to these particular applications The breadth and import of the present invention should be ascertained only in accordance with the claims Referring now to FIG 1 a computer system 100 with certain components are illustrated schematically A system board 104 is illustrated as comprising a central processing unit or 106 operating in con junction with other essential chip elements 110 The essential chip elements 110 may include for example a math co processor Before the present invention a computer system would have comprised 2 processor chip such as an 80286 and a co processor such as an 80287 These two chips would have adhered to an industry standard such as the AT TM standard The present invention provides that the computer system comprising system board 104 may be upgraded without removal or replacement of any chips or boards or addition of any substitute boards to the system The present invention provides for the addition of an inven tive plug in module 102 into a connector 114 The pres ent invention provides that the mere fact that the plug in module 102 is installed insures that the syst
51. otherwise be performed by the original chips are instead performed by higher performance chips on a plug in module which is plugged into the computer system The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug in module No replacement or substitution of original chips or boards is necessary 63 Claims 7 Drawing Sheets U S Patent Mar 22 1994 Sheet 1 of 7 5 297 272 FIG FIG B2 74F04 FROM PLUG IN MODULE Sheet 2 of 7 5 297 272 Mar 22 1994 U S Patent az 99 colep se Yel aA s 2 SERES NI zc um zo OL S8 22 790 ET 22 3028 lt 9 10 ANNAN IX V 61V 8i V n dt Tiv DOA Lv 9 SV Iv V EZ OIDs ay 215 16177570 Ist 030 rpg eel w 42 9 4 i se 20 66 12 68 Sheet 3 of 7 5 297 272 Mar 22 1994 U S Patent d gt T Ei cT S OT v2 Old WOHJ U S Patent Mar 22 1994 Sheet 4 of 7 5 297 272 M7104 NAH lt BHE lt 508 lt 5 lt 386 _ 2 lt SXREADY H lt 387 1 2 TO FIG j T T EE N SN AN S ZN m FIG S s D C H gt FIG FIG 3B HLDA gt ADS OU WRR 386 HEP 2M bes PROCCLK gt RESET
52. processor is part of a first integrated circuit chip and the OR circuit is separate from the first integrated circuit chip 13 The system of claim 11 wherein the first processor is part of a first integrated circuit chip and the OR circuit is part of a second integrated circuit chip which is separate from the first integrated circuit chip 14 The system of claim 11 wherein the OR circuit employs a negative logic in which any signal causes the output of the OR circuit to be active 15 The system of claim 11 wherein the first input of the first processor is an input which when activated does not disable the first processor until the end of a current instruction cycle 16 The system of claim 11 wherein the first input of the first processor is an input which 5 291272 29 when activated causes the first processor to acti vate a hold acknowledge output signal 17 A base computer system with modular upgrade capability in which installation of a module which is not originally part of the base computer system causes disablement of a first processor without its physical removal from the computer system so as to allow a second processor on the module to assume functions otherwise performed by the first processor the base computer system having an expansion bus with a set of expansion bus signal paths the base computer system comprising 2 the first processor having a first input which when activated
53. s described above with respect to pin 5 of the first GAL 206 Pin 23 A23 This input is tied to A23 Pin 13 GND The output enable signal is always active low so that the output of the second GAL 202 are not forced to a high impedance state The outputs of second GAL 202 will now be de scribed Pin 22 NPCS This signal prevents improper control of the 80387SX co processor specifically preventing the system board chips at from controlling it The NPCS signal is directly input to pin 12 of the first GAL 206 The NPCS signal like all other signals output from the second GAL 202 are generated in accordance with GAL 8 equations reproduced Ap pendix B Pin 21 RSTERR This signal resets the second D type f lip f lop 232 and serves to reset a latched error signal relating to the co processor interface It is di rectly connected to the pre set input pin 1 of the flip flop 232 Pin 20 HOLD386 This signal is input to the HOLD input of the 80386SX Pin 19 RESET386 This signal is input to the RESET input of the 80386SX Pin 18 SLCK This clock signal is input to pin 7 of the first GAL R 206 As described above it serves to divide by two a clock signal ultimately involved in the generation of the SO and 61 signals output from first GAL 206 Pin 17 RESET387 This signal is input to the RESET input of the 80387SX Pin 16 PEREQ386 This signal is input to the PEREQ input of the 80386SX P
54. s located 60 The upgraded computer system of claim 24 wherein the installation announcement circuit includes a short circuit pathway extending between 1 a pre determined constant signal level and 2 a pathway 10 15 20 25 30 35 45 50 55 65 36 to which the first input of the first processor is responsive 61 The upgraded computer system of claim 60 wherein the installation announcement circuit consists essentially of a short circuit pathway extending between 1 ground and 2 a pathway to which the first input of the first processor is responsive 62 The upgraded computer system of claim 24 wherein the first processor has associated therewith a first bus with first bus characteristics the second processor has associated therewith a sec ond bus with second bus characteristics and the module includes means to ensure full compatibil ity between the first bus characteristics and the second bus characteristics 63 The upgraded computer system of claim 56 wherein the means for allowing includes power bus a ground bus a circuit board providing support for the foregoing elements a connector on an edge of the circuit board and conductive pathways interconnecting the foregoing elements
55. second processor 53 The base computer system of claim 52 wherein the first input is a HOLD input 54 The base computer system of claim 52 wherein the installation announcement signal is a predeter mined constant signal level provided to a first pin on a connector to the module the first pin being adjacent a pin which receives the installation an nouncement signal from the module 55 The base computer system of claim 54 wherein the predetermined constant signal level is ground the installation announcement signal constituting a short circuit to ground when the module is in stalled in the base computer system 56 An upgraded computer system comprising 1 a first processor having a first input which when activated disables the first processor and 2 a module consisting essentially of a a second processor and any related co processor having at least certain performance characteristics dif ferent than performance characteristics of the first pro cessor b an installation announcement circuit for generat ing an installation announcement signal when the module is installed in the computer system the first input of the first processor being responsive to the installation announcement signal to cause disablement of the first processor without its physical removal from the computer system the installation announcement signal not causing disablement of any portion of the computer sys tem other than the first proc
56. ssor without its physical removal from the computer system the installation announcement signal not causing disablement of any portion of the com puter system other than the first processor and portions of the computer system which if not disabled would interfere with the second proces sor s assuming functions otherwise performed by the first processor and 3 a path being electrically separate from the expan sion bus signal paths for carrying the installation announcement signal from the module only to the processor and to the portions which if not disabled would interfere with the second processor s assum ing functions otherwise performed by the first pro cessor wherein the installation announcement circuit gener ates the installation announcement signal to cause disablement of 1 a disable acknowledge signal indicating disablement of the first processor to the remainder of the computer system as well as 2 a co processor interrupt which if not disabled would interfere with the operation of the second processor 24 The computer system of claim 23 wherein the first input is a HOLD input 25 The upgraded computer system of claim 23 wherein the installation announcement circuit is located out side an integrated circuit chip in which the second processor is located 26 The upgraded computer system of claim 23 wherein the installation announcement circuit includes a short circuit pathway extending between 1
57. ted circuit chip and the providing means is part of a second integrated circuit chip which is separate from the first inte grated circuit chip 20 The system of claim 17 wherein the providing means employs a negative logic in which any O input signal causes the output of the providing means to be active 21 The system of claim 17 wherein the first input of the first processor is an input which when activated does not disable the first processor until the end of a current instruction cycle 22 The system of claim 17 wherein the first input of the first processor is an input which when activated causes the first processor to acti vate a hold acknowledge output signal 23 An upgraded computer system having an expan sion bus with a set of expansion bus signal paths the upgraded computer system comprising 1 a first processor having a first input which when activated disables the first processor 2 a module including a a second processor having at least certain per _ 5 20 35 40 45 50 55 65 30 formance characteristics different than perfor mance characteristics of the first processor and b an installation announcement circuit for generat ing an installation announcement signal when ever the module is installed in the computer system the first input of the first processor being responsive to the installation announcement sig to cause disablement of the first proce
58. the first processor to acti vate a hold acknowledge output signal 10 A base computer system with modular upgrade capability in which installation of a module which is not originally part of the base computer system causes functional disablement of at least a portion of the base computer system without its physical removal from the computer system while allowing the module to assume functions which would otherwise be performed by the disabled portions of the base computer system the mod ule generating an installation announcement signal when installed in the base computer system the base computer system comprising a a circuit which generates a local numeric processor interrupt signal Ww 10 15 20 25 30 35 45 50 55 65 28 b a numeric processor interrupt isolation circuit including 1 an input responsive to the local numeric proces sor interrupt signal 2 an output which may either be i responsive to the local numeric processor in terrupt signal or ii rendered inactive and 3 an enable input responsive to the installation announcement signal from the module the en able input controlling whether the output of the numeric processor interrupt isolation circuit i is responsive to the local numeric processor inter rupt signal or ii is rendered inactive 11 A base computer system with modular upgrade capability in which installation of a module which is not originally part of the
59. the origi nal 80286 based AT TM computer are considered in some respects to be enhancements of it One manufacturer Chips amp Technologies Inc C amp T 3050 Zanker Road San Jose Calif 95134 has developed a chip set known as the NEAT TM chip set The NEAT TM chip get is described in data sheets entitled CS 8221 New Enhanced AT TM NEAT TM Data Book part catalog no 2221 B 10M 3 88 Rev 2 which like all technical documents cited in this specifi cation is incorporated by reference as if reproduced in full below See also C amp T PRODUCT ALERT PA76 2 9 88 UPDATE Sep 21 1988 386SX 387SX BOARD DESIGN WITH NEAT AND CHIPS 250 and PA115 3 89 UPDATE ON NEAT PLUS SX MODULE The C amp T NEAT chip set has allowed develop ment of AT TM compatible computer systems Among the systems which are AT TM compatible is the 80286 based POWERFLEXTM system from Advanced Logic Research Inc ALR 9401 Jeronimo Irvine Calif 92718 As will be better appreciated by a reading of the Detailed Description of the Preferred Embodi ments of the present invention below this computer system may advantageously be used in conjunction with the present invention There are several known methods of upgrading an AT TM compatible 80286 based computer systems A first upgrade method involves an add in card which is inserted into the AT TM bus and in which a cable is extended form the add in card to the CPU cen tral pr
60. the output of a tristate buffer 321 whose input is the HLDA signal In this manner when the 803865 plug in module is installed the HLDA signal output from 321 is governed by the HLDA output pin 3 of the 80386SX processor FIG 2 By virtue of the bus con nection in which the HLDA signal from the 803865 and the HLDA signal which may be output from buffer 321 the disablement of buffer 321 relinquishes control of the hold acknowledge function to the new 80386S X module On the other hand when the 80386SX module is not installed the SXINST signal FIG 5A is low allowing the HLDA signal output from the 80286 processor on the system board to control the system wide HLDA signal shown at the far right of FIG 5A FIG 5B illustrates the preferred method of generat ing clocks for the system and the method for genera tion of the numeric processor interrupt signal NPINT In particular when the 80386SX plug in module is in stalled into connector 114 the numeric processor inter rupt signal NPINT is governed from that module as described above with respect to FIG A2 Generally the 80387SX co processor orn the plug in module is completely isolated from the chip set on the system board with the exception of the interrupt the interrupt is generated for numeric co processing er rors In known techniques to support an 80387SX co processor substantially more circuitry is required and there still remains a question as to wheth
61. the present inven tion will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Preferred Embodiments in conjunction with the accompanying drawings Tables and Appendices BRIEF DESCRIPTION OF THE DRAWINGS The invention is better understood while reading the following Detailed Description in conjunction with a review of the accompanying drawings in which like reference designators refer to like elements throughout and in which FIG 1 is a schematic diagram illustrating the advan tages of a preferred embodiment of the present inven tion in allowing a plug in module 102 to assume the function of certain chips such as 106 and 110 on the system board 104 of a computer system 100 FIG 2 shows the connection of FIGS 2A and 2B FIGS 2A and 2B collectively referred to hereinafter as FIG 2 are logical diagrams illustrating the 80386SX processor 204 and 80387SX co processor 203 as imple mented in a plug in module according to a first embodi ment of the invention FIG 3 shows the connection of FIGS 3A and 3B FIGS 3A and 3B collectively referred to hereinafter as FIG 3 illustrate the Generic Array Logic GAL chips and the numeric processor interrupt logic as used in the first embodiment of the plug in module according to the present invention FIG 4 illustrates a connector 114 and part of the clock selection logic from the first embodiment of the plug in module according
62. to the present invention FIG 5A illustrates a preferred implementation of a logic configuration on the 80286 system board for al lowing the 80286 processor to be functionally removed from the computer system when a plug in module ac cording to the present invention is installed FIG 5B illustrates a preferred implementation of another portion of the system board s clock selection logic and numeric processor interrupt control logic DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In describing the preferred embodiments of the in vention specific terminology will be used for the sake of clarity in describing the specific embodiments to those skilled in the art However the invention is not intended to be limited to the specific terms so selected and it is understood that each specific term includes all technical equivalents which operate in a similar manner to accomplish a similar purpose Also particular chips chip sets industry standards computer systems and other elements are presented and described in detail so as to describe the particular embodiments presented However the invention is not to be limited by the par ticular embodiments contained herein but should be defined only in accordance with the claims which fol low and their equivalents 25 40 45 50 55 60 65 4 Briefly the preferred embodiments involve the use of the C amp T NEAT TM chip set processor and possibly also a co process

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