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WildFire Users` Manual - Freescale Semiconductor

1. Alt 2 Alt 1 GPIO Signal Signal GPIO Alt 1 Alt 2 z 3V3 GND E U2TXD DTOOUT DTOIN DT1IN DTIOUT U2RXD U2RTS DT2OUT DT2IN DT3IN DT3OUT U2CTS DREQO IRQ4 QSPI_CLK 12C_SCL 12C_SDA QSPI_DOUT QSPI_DIN DREQO U2CTS QSPI CS0 DTOIN UOCTS U1CTS DTIIN QSPI CS1 U2RXD 120 SDA Pe scl U2TXD l 3V3 GND 2 Legend Special Function GPIO SIGNAL M5208EVBUM pdf 13 1 Sep 5 DMA Timers There are 4 32 bit DMA Timers on the MCF5208 Each timer is associated with a single input capture IC signal and a single output compare OC signal The two signals are multiplexed onto a single pin on the 196 MAPBGA package so only one function either DTnIN or DTnOUT can be enabled at a time The tic rate for each timer can be set through its prescalar to a frequency ranging from 20 26 KHz to 83 MHz The timers can operate in a free run mode where the timer counts up to OxFF FF FF FF then wraps to 0 or they can run in restart mode where the timer will reset to 0 once the compare value is reached Each DMA Timer module can be configured to fire an interrupt when an input event IC or a reference compare match is detected OC The DMA Timer pins are shown in blue on CNI in Figure 13 They can be independently configured as GPI O Configuring a pin for I O will disable any timer functionality associated with the pin but will not affec
2. RX Antenna 18pF EL 4 7 deg Z 1150hm EL 4 7 deg Z 1150hm i TX Antenna EL 8 0 deg Z 1150hm EL 8 0 deg Z 1150hm ZigBee Capable Transceiver TITLE M5208EUVB_Rev_B Document Number Date 8 30 2005 12 20 51p From ZigBe nee U MCF5208 IRQ from BDM Port hoa To ZigBee heet 10 To Configure hee U1_RESET co RSTOUT RESET RCON DRAMSEL TEST PLL_TEST IRQ4 DREQO IRO7 N14 Abort indicator LED D8 Z 7 Abort Switch w 0 30ms debounce cct MCP130 BOOT SELECT 10K JP1 is used to select the boot program If dBUG monitor sees a low signal here it will automatically run the program in flash 10K resistor prevents contention on U1 pin A10 out of reset JP6 is fitted to enable reset Reset and IRQ configuration default GET is Med to select DDR TITLE M5208EUB_Rev_B JP4 is fitted to disable Test mode default Document Number REV Date 8 30 2005 12 20 51p Sheet 11 13 3V3 2V5 3 3V Decoupling JP7 JP10 are fitted by default U1_PWR JP9 pa EVDD EVDD EVDD EVDD EVDD EVDD mimim aaa o G O Se pu pad elel le mE lo fared PS a M9 io Joo 77 Ko 2 5V Decoupling d gt K LC d MCF5208 Power lt lt SSSSE D0ODODODODODOO LR O DI VD IVDD IVDD IVDD 1 5V Decoupling VDD_A PLL VDD_D_PLL ii C25 N 10uF 6 3V su al Pye T z ol ES P nio MCU Power Rails T
3. Data Direction Register A register whose bits correspond to the function of a set of digital I O pins The convention on the M5208EVB is to use 0 for input 1 for output Direct Memory Access Ability to copy a block of data from one device to another without the intervention of the CPU Data Terminal Equipment The fraction of high time of a PWM signal versus the period of the signal A multi purpose extensible integrated development environment GNU Compiler Collection A public license GNU compiler GNU Debugger A public license GNU debugger General Purpose Input Output These are 3 3V level signals on the M5208EVB GNU General Public License Single or double row of pins on a circuit board to which connectors may be attached Integrated Development Environment An set of software tools that share a single interface used for writing compiling and debugging programs Interrupt Request The ability of a module or external pin to request servicing of the interrupt controller An IRQ stops the current execution of a program and jumps to a piece of code found in the interrupt vector table Least Significant Byte Most Significant Byte Periodic Interrupt Timer A timer that can generate interrupts at regular intervals Pulse Width Modulation A pseudo analog signal that is toggled at a high frequency The analog value between 0 and 3 3V is determined by the signal s duty cycle Watchdog Timer A timer that resets the MCF5208 if
4. PLL and Internal Core supply voltage 1 25V VREF DDR reference voltage Figure 3 Power Test Points Lo gt GND test loop gt freescale Power test points M5208EVBUM pdf UART1 AUX EXT CLK semiconductor A Intec Automation Inc www steroidmicros com Oscillator osc E EXT CLK JP11 x x F GND test point u5 VB BOM RITA Crystal DDR SDRAM gt ColdFire M5208E D AGREE GND test loop Capable XCVR x _ 0 E Mex E 20 E un So E TOUT3E TOUT2E RESET ABORT TOUTIE on IRQ7 wm TOUTOE 4 1 Sep 5 Each supply voltage can be measured at a labeled test point on the M5208EV Band Ground can be accessed at 2 test clips and one test point as shown in Figure 3 Power Jumpers Several jumpers make it possible to measure the current draw to the various MCF5208 processor power inputs or to isolate them from the power supplies These jumpers are listed in Table 3 Figure 4 Power Jumpers Power Jumpers Table 3 Power Jumper Descriptions JP7 JON Connect Core PLL filter to 1 5V OFF Disconnect Core PLL filter from 1 5V JP8 JON Connect Core to 1 5V w JP7 ON OFF Disconnect Core from 1 5V JP9 JON Connect MPU I O rail to 3 3V OFF Disconnect MPU I O rail from 3 3V JP10 JON Connect External Bus to 2 5V OFF Disconnect External Bus from 2 5V All the power jumpers are described in Appendix A and on Sheet 12 of the M5208EVB schematic Low V
5. TITLE M52068EUB_Rev_B Document Number REV Date 8 30 2005 12 20 51p Sheet 2 13 To ZigBee XCVR nee 0 U1_UART UORTS DTOOUT QSPI U1RTS DTTOUT QSPI_CS1 UORXD UIRXD UOCTS DTOIN QSPI_CSO U1CTS DTIIN QSPI_CS1 E lt MCF5208 CMOS Levels From I O Header TIN T2IN T3IN TAIN TSIN R10UT R20UT R3OUT y C2 073 TIOUT T2OUT T3OUT T4OUT T5OUT RUIN R2IN R3IN SP3249EY GND 232 Levels Pin 11 on U8 is internally pulled down Add pulldowns resistors to UOTXD and U1TXD to prevent these lines from floating during reset TITLE DCE Terminal Label as Terminal and UARTO DCE Serial I O Label as Auxiliary and UART1 Serial Communications M5208EUB_Rev_B Document Number Date 8 30 2005 12 20 51p CNS is a 2 1mm center positive power jack O ring supply voltage accepting 7VDC 14VDC Switching 3 3V Power Supply 1A max Overcurrent protection resettable fuse sw5 U12 H E Reverse bias protection diode T lt 1 E PTC Green LED indicates 3V3 0805FB2002 1a E nal ONOFF 101M2SXA i 0 4V 1a 30VmaX L 4TUH 1A OR2 5 c39 M2675 _ A U12 is ON when pin oy 100uF 10V OR15 N 5 is unconnected LED 0805 Green I U I I I l 4 7uF 50V 0R36 PGND PGND is connected to GND at one point only 0 4V 1a 30Vmax I I I I pe TP15 TP5 TPG TP16 I I I I I I DDR SDRAM and Flash supply voltage i 2V5 Regulator 500mA max GND testpoints
6. 4 Amber LED 0805 Lite On LTST C170KFKT D9 D10 D11 D12 2 Green LED 0805 Lite On LTST C170KGKT D2 D4 2 Red LED 0805 Lite On LTST C170KRKT D8 D15 5 0 4V 1a 30Vmax DIODE CRS05 MCC MBRX130 D1 D3 D5 D6 D13 1 16 000MHz MA 406 Citizen CM309S 16 000MABJTR Y3 1 16 000MHz TSX 4025 Toyocom TSX 4025 Y2 1 25 000MHz MA 406 Fox FPX 250F 20 Y1 1 16MHz CSX 750F Fox F4100 160 oscillator U5 1 1 5pF GOG 0 25pF CAP 0402 Rohm MCH155A1R5CK C19 2 10pF COG 5 CAP 0402 CalChip GMC04CG100K25NT C29 C30 2 18pF COG 5 CAP 0402 Murata GRM1555C1H180JZ01D C20 C24 2 22pF COG 5 CAP 0603 AVX 06035A220JAT2A C4 C5 2 39pF COG 5 CAP 0603 TDK C1608COG1H390J C12 C13 11 220pF COG 10 CAP 0402 Rohm MCH155A221JK C15 C18 C26 C40 C43 C45 C59 C63 C66 C72 C73 6 inF COG 10 CAP 0603 AVX 06035A102JAT2A C28 C42 C44 C58 C62 C65 35 0 1uF X7R CAP 0603 Rohm MCH182CN104KK C1 C2 C3 C7 C9 C10 C11 C14 C16 C17 C21 C27 C33 C34 C35 C36 C37 C38 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C60 C64 C70 C71 1 JO t1uF X7R 4XCAP603 NIG NCA1206X7R104K16TR C6 1 _ 4 7uF 50V 0R36 CAP_TANT D Vishay 293D475X9050D2T C41 6 10uF 6 3v 0 5R CAP_TANT_Y Kemet T491A106K006AS C8 C22 C23 C25 C31 C32 1 100uF 10V 0 15R CAP_TANT_D Vishay 593D107X9010D2T C39 M5208EVB RevB Bill of Materials BoM 30 Aug 05 Qty Value Device Manufacturer Pa
7. great detail in Freescale s MCF5208 Reference Manual Ch 14 Interrupt Controller Module and Ch 15 Edge Port Module M5208EVBUM pdf 15 1 Sep 5 Abort Button When this tactile switch is pressed the IRQ7 signal is asserted When the M5208EVB is running under control of the BUG monitor a level 7 interrupt will be triggered The dBug monitor will terminate the user program and the CPU context will be displayed on the host PC followed by the dBug prompt This assumes that the M5208EVB is connected serially to a host PC running a serial terminal program such as HyperTerminal uClinux does not implement the abort functionality However this button can be used as a general purpose input for user interaction with an application This signal is debounced and is held low for up to 700ms after the button is released M5208EVBUM pdf 16 1 Sep 5 QSPI The QSPI module allows high speed serial communication with SPI devices such as a serial flash real time clock AtoD and DtoA converters etc Two QSPI chip select signals and the QSPI bus signals are available on pins 8 12 on CNI See I O Header A third QSPI chip select is used on board to interact with the ZigBee capable transceiver The QSPI signals are shown in blue in Figure 15 Figure 15 QSPI Signals on CN1 BEEEEEEE i A 99999973 a z Q le MW TOUT3E UP16 9 x IITOUT2E JP15 ABORT NE IRQ7 L TOUTOE p13 In addition to the QSPI function these signals can be co
8. running This date will reset every time the board is rebooted If you would like to keep the time accurate you must use a battery backed RTC with the hwclock utility e date view the current system date e date MMDDhhmm YYYY set the system date time System proc file system The proc file system provides diagnostics for the entire system To view the diagnostics use the cat command in the proc directory e cat proc cpuinfo displays stats about the CPU brand and speed e cat proc interrupts statistics on interrupts e cat proc mounts information on mounted filesystems uClinuxCommands pdf C 2 5 Sep 05 e more browse through the proc directory and subdirectories to see more diagnostics ps The ps command shows information about the current running processes in the system e ps display information including the process id of each process in the system shutdown The shutdown command is the only way to correctly shutdown uClinux without causing potential file system damage The shutdown command will attempt to gracefully close all processes and eventually kill them synchronize the cached file system information to disk and terminate operation e shutdown h now Shutdown the system and hang in an endless loop requires hard reset to boot up again e shutdown r now Shutdown the system and perform a software reset if Autorun is on uClinux will boot up again e shutdown display usa
9. the processor I O voltage to 3 3V Also connects JP11 to 3 3V JP10 When fitted connects the processor external bus voltage to 2 5V JP11 This jumper selects between an external oscillator and an off board frequency source This jumper is only relevant is JP15 is in position 1 2 By default it is set to position 2 3 to JP12 This jumper selects between the on board crystal or an external oscillator It is in position 1 2 by default to select the on board crystal JP13 This jumper connects TOUTS to its LED It is normally fitted JP14 This jumper connects TOUT to its LED It is normally fitted JP15 This jumper connects TOUTI to its LED It is normally fitted JP16 This jumper connects TOUTO to its LED It is normally fitted M5208EV BUM pdf A 3 1 Sep 05 Switches Several switches on the M5208EVB are used to control the board s configuration and operation The switches are listed in Table A 2 Table A 2 Switch Functions Switches Function Power Switch Isolates M5208EVB from power supply Reset Button Asserts the RSTI signal forcing the MCF5208 and peripheral systems to reset Abort Button Asserts the IRQ7 signal causing an interrupt in the MCF5208 This interrupt is handled by ABUG monitor Configuration Switch Determines the out of reset configuration of the MCF5208 Reset Configuration Switches The DIP switch on the M5208EVB determines the MCF5208 s
10. the running program gets caught in an infinite loop or branches incorrectly M5208EVBUM pdf Vv 7 Sep 5 Nomenclature Periodically reference is made to entities in a generic manner using the italicized letter n to indicate that there are many numbered entities with the same name For example DATn applies to all bits in the DAT register The naming conventions used for signals are shown in Table 1 Table 1 Signal Nomenclature Name Type Logic Value Term SIGNAL Active High 0 Asserted 1 Negated SIGNAL Active Low 0 Negated 1 Asserted M5208EVBUM pdf vi 7 Sep 5 Introduction The M5208EVB is a convenient platform for evaluating many of the capabilities of the MCF5208 MPU It offers a head start in terms of hardware development around this MPU The software packages that accompany this evaluation board provide a head start in terms of software development The MC5208 is a highly configurable MPU While the M5208EVB does not make it possible to explore all the configuration possibilities of this MPU it does provide a fair amount of functionality This is further supplemented by the inclusion of a ZigBee capable transceiver as shown in Figure 1 With a 10 100 Ethernet controller and the ability to interface to up to 256MB not Mb of fast DDR SDRAM the MCF5208 can support large operating systems and open up new software opportunities To demonstrate this the M5208EVB is shipped with uClinux and sample web
11. to monitor the processor status at any time without interfering with the processor execution If JTAG is enabled the JTAG signals from the MCF5208 come out to the BDM header Figure 9 CN2 BDM Port E freescale EXT CLK semiconductor Intec Automation Inc www steroidmicros com Oscillator Direction Signal Pins Signal Direction 1 2 BKPT IN GND 3 4 DSCLK IN GND 5 16 TCLK IN IN RSTI 7 8 DSI IN 3V3 DSO OUT GND PST3 OUT OUT PST2 PST1 OUT OUT PSTO DDATA3 OUT OUT DDATA2 17 DDATA1 OUT OUT DDATAO 19 GND GND PSTCLK OUT 1V5 TA IN Pin 25 on the BDM header is connected to 1V5 through JP2 which is fitted by default This jumper is required for some of the legacy BDM pods that connect pins 9 amp 25 of the BDM interface internally More recent debug pods support both core amp I O voltages The BDM pod supplied with the M5208EVB supports both voltages and requires JP2 to be fitted JTAG_EN Jl is a 2 position shorting pad for a 0 ohm 0603 resistor Figure 10 By default pads 1 2 are shorted enabling BDM mode on the processor This configures all the signals on the BDM header CN2 with their BDM functions as described in Chapter 26 Debug Module of the MCF5208 Reference Manual In BDM M5208EVBUM pdf 11 1 Sep 5 mode JP1 should be fitted across pins 1 2 to connect TCLK PSTCLK configured as PSTCLK to pin 24 o
12. using the serial device driver under uClinux uClinuxDeviceDrivers pdf D 2 27 Jun 05
13. 1 mnt flash 3 To erase a device use the raw char driver gt eraseall dev mtd1 This will erase all data on the device and is in fact like formatting the device For the M5208EVB the partitions are as follows 1 mtd0 mtdblock0 256K dBUG partition 2 mtdl mtdblock1 640K JFFS2 partition 3 mtd2 mtdblock2 1152K compressed Kernel image Only the mtd1 partition should be used in most cases Altering the other partitions could cause problems booting the board and will require the board to be re flashed with the BDM pod Once mounted the directory can be used like any other and will retain its data between power cycles uClinuxDeviceDrivers pdf D 1 27 Jun 05 ram RAM The ram driver allows a file system to be mounted in RAM A special RAM disk is created by default on startup from the rc script when uClinux boots The var directory will boast fast access but will not retain its contents between system reboots It is not likely that a user application will need to use this driver directly but instead simply use the var directory for fast file access ttyS COM Ports The ttyS drivers provide access to the serial ports under uClinux The ttyS driver can be configured in many ways to allow ASSCII and binary communications The number after the ttyS represents which port to use e ttyS0 uart0 COMI used as console e ttyS1 uartl COM2 e ttyS2 uart2 COM3 See the uDemoSerial for a comprehensive example on
14. 30 2005 12 20 51p Sheet 7 13 U1_TIMERS JP13 JP16 are fitted by default DTOIN DTOOUT U2TXD DT1IN DTIOUT U2RXD DT2 T20U S DT3IN DT3OUT FU2CTS Timers MCF5208 4 x Amber LEDs IO Header To From ZigBee heet 10 U1_QSPI QSPI_CLK 2C QSPI_DOUTA20 QSPI_DINADREQO QSPI co O N LO LL E QSPI_ ACKO U2RTS vie an 1 0 Header an TEE MO CORE NE Rev TXDIPFECI2C1 120 MCF5208 Document Number REV Date 8 30 2005 12 20 51p Sheet 8 13 U1_MEM_CTRL U2 is not populated U gt ADDR A0 23 U gt To DDR Shee From Boot Selec hee El DATA D 0 31 K 4 x c E A Ag E MCF5208 Mem Control ME From BDM Header E DATA D 0 31 i i ADDR A 0 23 i IDT71T016SA12PH iw o 3 A pon 5 a o s D v o S E las GND C51 0 1uF C52 0 1uF PA AE O Decoupling caps for U13 PED O Place one capacitor on each side of U2 and route directly to SD_VDD 7 Place one capacitor on each side of U13 and route directly to SD_VDD EAT Reset OV a3 20 y S Wo roy ese Flash amp SRAM DO gt TITLE M52 8EVB_Rev_B lesa PEIN NEN Document Number REU sis Date 8 30 2005 12 20 51p Sheet 9 13 To From QSP Y2 1 3 16 000MHz 7 4 o e on 8 GND To Flash amp SRAM RFIN VDDA VDDLO1 VDDLO2 XTAL2 VDDD VDDVCO GND VBATT GND VDDINT GND GND MC13192
15. 8E VB Modules HE Power Sy Stein id alia aa tans 4 POWErJUMDOIS ra rasca 5 STUD Configuration eio ie Tadig A A ee EDR 6 BODA AN TIA A da a A 8 Cl APURO RE ni ne Re Out 9 Seral INS eines e Med a 10 Serial DEDUBENE iaia 10 A T rale dini Sl li i bieco 11 AG ENS poll 11 VO Head ici a E E E a pr 13 Interrupt Level and PILOT RR A AA astm a 15 Abort BUG ON enerne onda E E OO EAE E E RIT ee 16 M5208EVBUM pdf iii 7 Sep 5 Memory and Storage o OO RE ne e 19 Interna SRAM AAA un O le a 19 LS T lio bad 19 External DDR SDRAM leali 19 External Pla A da a a ii dto di 19 AR 20 Runtime Trom Elabora 20 Memory Is 21 WY AUCH T NO Ra 23 A n Aia 24 ANI iii 24 Pie Bee Capable K ini 25 FCC Certification A ae a 26 EXCESO se ceases Re RS nr ne RS 26 Calogero 26 Appendix A Jumpers Switches Pinouts amp Specifications oomoooomo A Appendix B M5208EVB Schematics BOM ooccconnccoonoccnnnnccnnnnccnnoncconocccnnocccnoccconocons B Appendix C ABUG Monitor Serres rara aio C Appendix D uClinux Commands ccoooccoonoccnonnccnonaccnnoncconocccnnncccnnoccconococonococnncccnnocons D Appendix E uClinux Divers iii E M5208EVBUM pdf iv 7 Sep 5 Glossary BDM DCE DDR DMA DTE Duty Cycle Eclipse GCC GDB GPIO GPL Header IDE IRQ LSB MSB PIT PWM WDT Background Debug Mode Mode A non intrusive method of taking control of the MCF5208 through a debug program running on a host PC Data Communication Equipment
16. EREERRERE 9 c30 FETE z i A T RETOUTIET yJpP16 i TOUT2E Jpis gt RESET ABORT TOUTE sp14 O IRQ7 RETOUTOEC JP13 Abort Button IRQ4 Interrupt Level and Priority An understanding of the interrupt level and priority scheme on the MCF5208 can be helpful The MCF5208 has sources of interrupts Each is assigned a number ranging from 1 for IRQI to 62 for buss error These are hard wired With the exception of the IRQ signals each interrupt source eg source 4 PITO PCSRO PIF PIT interrupt flag can be assigned an interrupt level 1 being the lowest level 7 being the highest serviced first Any number of interrupts can be set to the same level When multiple interrupts at the same level fire they are processed in reverse order of their source number That is the lowest source gets serviced last And the IRQ signals correspond to the lowest sources as shown in Table 9 Table 9 IRQ Pin Priority al Source Priority This interrupt scheme can have interesting side effects For instance in the absurd case where the Ethernet interrupts were set to level 7 the level 7 interrupt fired by pressing the Abort button would not be serviced until the CPU had finished servicing the Ethernet interrupts dBUG monitor sets the IRQ7 level to level 7 Internal interrupt sources should not be set to level 7 or the Abort functionality of BUG monitor will be compromised The MCF5208 s interrupt scheme is covered in
17. ITLE M52068EUB_Rev_B Document Number Date 8 30 2005 12 20 51p Sheet 12 13 aloleclollllilolololo follo lla ast Z External Clock Input SMA Connector Not populated CN7 JP11 is fitted on 1 2 by default Oscillator Clock Input U5 3V3 VDD OE OUT GND JP12 is fitted on 1 2 by default Crystal Clock Input 22pF 3 16 000MHz 2 Y 4 3 Clock Input Selection a A AA N N a mn MCF5208 PLL Clock TITLE M52068EUB_Rev_B Document Number REU Date 8 30 2005 12 20 51p Sheet 13 13 M5208EVB RevB Bill of Materials BoM 30 Aug 05 Qty Value Device Manufacturer Part Number Ref ID 1 MC13192 MC13192 Freescale MC13192FC U7 1 MCF5208 MCF5208 Freescale MCF5208CVM66 U1 1 DP83848 DP83848 National Semi DP83848VV U4 1 LM2675 LM2675 National Semi _ LM2675M 3 3 U12 1 MT46V16M16 MT46V16M16 Micron MT46V16M16 U6 1 AM29BDD160G IDT71T016SA12PH AMD AM29BDD160GT64DKI U13 1 SP3249EY SP3249EY Sipex SP3249EY U8 1 SPX1117M3 SPX1117M3 Sipex SPX1117M3 1 5 U9 1 LD29080DT25 LD29080 STElectronics LD29080DT25 U3 1 LVX573 74XX573T Fairchild Semi 74LVX573MTC U11 2 MCP130 MCP130 MicroChip MCP130T 3151 TT U10 U14 1 FUSE PTC FUSE PTC Raychem miniSMDC050 U15 1 FB1K0 100ma L SMT 0603 Murata BLM18AG102SN1D L6 1 0805FB200z 1a L SMT 0805 Murata BLM21P221SGPT L4 1 47uH 1A 0R2 IND_DN8155 Coev DN8155 470K L2
18. Interrupt Request Subsystem IRQ OSPI module LO module Memory 2MB external flash 32 MB external DDR SDRAM and a foot print for a 128KB external SRAM WatchDog Timer WDT module Ethernet PHY and RJ45 connector ZigBee capable transceiver Resident firmware dBUG monitor Operating System uClinux Some of these features are associated with connectors as shown Figure 1 This adds up to a rich assortment of features M5208EVBUM pdf 3 1 Sep 5 Power System The center positive 5 5 2 1mm power jack for the M5208EVB accepts inputs ranging from 7V to 14V DC capable of at least 3 watts A slider switch connects the power to the board When this switch is in the ON position power is connected to the board otherwise all circuits on the board are isolated from the input power A resettable Polyswitch fuse protects the power supply against a short on the board Two green LEDs between the power connector and power switch indicate when the board is powered The location of these indicators is shown in Figure 2 Power Connector Figure 2 M5208EVB Power m 5 m R dl gt au my Power Indicators RESET ABORT ON a IRQ7 Power Switch Table 2 M5208EVB Voltage Levels Voltage Max Current Signal Name Description 3 3V 1A EVDD External I O supply voltage 2 5V 500mA SDVDD External Bus supply voltage Used by DDR SDRAM flash and SRAM 1 5V 200mA PLLVDD IVDD
19. JP 7 9 US Ji BOM 1EJTAG COM1 TERMINAL UARTO Crystal 9 RSTOUT F x FLASH m gt LU 00 o N w o 7 IL 3 O O Ser No 32MB DDR ZIGBEE Capable XCVR 33332322223333233233227233332237 UART1 AUX OO 62 S 2 S TOUT3E RESET ABORT mE ou a fon RO TOUTOE JP13 COM1 is specifically used for serial debugging a user program with the dBUG monitor or for uClinux terminal COM2 is available for user I O and for redirecting console I O during a serial debugging session The female DB9 serial connectors have standard DCE pinouts and connect directly to a DTE device such as a PC There are no hardware handshaking signals on COM1 or COM2 COM3 UART signals are available on CN1 The Tx and Rx signals are multiplexed with TINO and TOUT respectively See I O Header and Chapter 24 UART Module of the MCF5208 Reference Manual for more details Serial Debugging Serial debugging requires the use of 2 COM ports if the user program contains any console I O i e printf or getc This is because the serial dBUG monitor ties up COM and console I O is typically redirected to COM2 M5208EVBUM pdf 10 1 Sep 5 BDM JTAG Port While serial debugging using the on board dBUG monitor is adequate for many applications Background Debug Mode BDM debugging makes it possible for a BDM debugger to have total control of the processor even after a program has crashed BDM debugging is able
20. M5208E VB RevB 32 bit Microcontroller User Manual Version 1 0 Intec Automation Inc 2751 Arbutus Road Victoria BC V8N5X7 Canada Warranty Intec Automation Inc warrants the hardware components of this product to be free from defects in material and workmanship This warranty extends for a period of 90 days from the date of purchase Any component under warranty will be repaired or replaced at the sole discretion of Intec Automation Inc without charge to the purchaser providing that the return of the component or board is preauthorized by Intec that shipping is prepaid by the purchaser and that Intec determines the defect is not a result of misuse The components of this product are provided as is without warranty The entire risk for the results and performance of these components is assumed by the purchaser Intec Automation Inc does not warrant guarantee or make any representation regarding the use of this product No other warranties are made expressly or implied including but not limited to the implied warranties of merchantability and suitability of products for a particular purpose In no event will Intec Automation Inc be held liable for additional damages including lost profits lost savings or other incidental or consequential damages arising from the use or inability to use Intec s products or the products resold by Intec Disclaimers Intec Automation Inc reserves the right to make changes without notice to
21. ON 8058 A test point Jumper ais EXT CLK semiconductor JP5 k Intec Automation Inc US www steroidmicros com Oscillator osc E EXT CLK 2 JP11 Z co gt lt LU 4 co Z lt RSTOUT Lo test point _DDR SDRAM v E E LL Gs D Og Z Moe x O Z O 3 NO E ZIGBEE H Capable E E XCVR lt Reset LED TO JT3E JP16 TO JT2E gt JP15 TO JT1E JP14 TO JTOE 4P13 Power switch RCON Switch Reset button SW1 Startup Configuration The MCF5208 configuration depends on 9 signals RCON D9 and D 7 1 which are sampled when the MPU comes out of reset When RCON is asserted the shunt on JP5 is on the MCF5208 reads its configuration options from the data signals which are driven high or low by the 8 rocker switches on SW1 Configuration options are shown in Table 4 If RCON is negated JP5 OFF the MCF5208 takes the default reset configuration values shown in Table 5 M5208EVBUM pdf 6 1 Sep 5 Table 4 RCON Mode Configuration Selection RCON 0 JP5 ON Selection Configuration SW1 1 PLL Mode OFF 166 67MHz Core bus 83 33MHz External Bus operation ON 88MHz Core bus 44MHz External Bus operation Note 1 SW1 2 Oscillator Mode OFF Crystal oscillator mode ON Oscillator bypass mode SW1 3 SW1 4 Boot Port Size OFF OFF 16 bit port OFF ON 32 bit port ON OFF __ 32 bit port ON ON 8 bit port SW1 5 Output Pad Drive Streng
22. Sep 05 Coordinates LO o E o D E OS o N 3 900 3 850 _ E90000000000 O Dn 20 3 800 2 Fa O 50000000000000 ti E 7 09 fis pp um SEEEEEEEE 00 o E a me GEH DOOODOLDO x Intec Automation Inc gt tue 200 ROSSO cbs E Ee Pi EORR TA YLE k ni scillator 3 gt g a FE oscl 9 Olext cK y d ae ma e 10 100 E E E ETHERNET 2 T os DaS rs EE On 7 SO pimin 2 n un z i LARE US D po gt ND OCLKOUTE E au 3 Crystal perm A daba x DDR SDRAM qe E CASH Q D 0 448 DO PET III 2 soil p a osno E RO ll EH TT eye Ds Este l of o s E culi O Ww go Y2 5 ui l y ZIGBEE z SEO n J CAPABLE ha gt 5 ORY BY YCUR Ce OxCSa Elan eas p e a di i LP m imin vie Ul4 00000000 y nn Ia O 0 750 el gt TCA ie d S PA a h0000000 EERIE Ebad Sui BCC GGG E rl EA E e 1g SIDOOOOO CNL O O Oal mml ro Cs ESS oo00070 0 325 RESET EE Ha TouTZ Bima 29955853 0 100 ta JP13 FFERS E O on O Ba TOUT3 OO 8 cast o a a D Y O N z E o b oO 1 Sep 05 M5208EV BUM pdf A 7 Appendix B M5208EVB Schematics amp BoM M5208EVBUM pdf B 1 Sep 5 Table of Contents DDR SDRAM Serial Communications Power Supply Reset Configuration 10 100 Ethernet BDM Connector 1 0 Header Flash amp SRAM ZigBee Transciever Reset amp IRQ MCU Power Rails Clock Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 She
23. YADO 1 internal PU Auto negotiation Enabled _EN 1 internal PU AN Advertise 10 100 Mbs H FD AN 1 0 11 MII mode of operation MII_MODE 0 internal PD SNI_MODE 0 internal PD Use Mode 2 LED configuration LED_LINK ON Good Link BLINK activity LED_SPEED ON 100Mb s OFF 10Mb s LED_ACT Unused 1 4 LED_CFG 0 25 000MHz MDIX enabled 2 3 N MDIX_EN 1 internal PU Eno Power Down disabled PWR_DWN 1 internal PU GND 0 1uF Place resistors and capacitors close to U4 HFJ11 2450E R20A gt R20C 10K R20D 10K Place close to CN6 AAA 1C56 0 1uF 1C55 0 1uF Place decoupling caps close to each power pin on U4 TITLE M5208EUVB_Rev_B Document Number Date 8 30 2005 12 20 51p MCF5208 JTAG BDM JP1 Fit 1 2 to enable PSTCLK on CN2 default Fit 2 3 to enable TCLK on CN2 DDATAO PSTCLK TCLK JTAG_EN To enable BDM short pads 1 2 w 0 ohm resistor default To enable JTAG short pads 2 3 w 0 ohm resistor BDM signal traces should not exceed 3 inches PST 3 0 and DDATA 3 0 trace lenghts should be equal BDM Header LI n INI JP2 is required for some of the legacy BDM cables that connect pins 9 amp 25 of the BDM interface internally More recent cables support both core amp I O voltages Please check with your BDM cable supplier JP5 is fitted by default BDM Connector TITLE M5208EUVB_Rev_B Document Number REV Date 8
24. able Transceiver Location LS A a 2 gt 32MB DDR SDRAM UART1 AUX meo E 33333322223333233233222233332227 a e Pe 2 freescale EXT CLK US osc E JP Crystal X Intec Automation Inc www steroidmicros com Oscillator EXT CLK m gt LU co N O 7 LL 3 O O 3V3 2V5 I le le TOUT3E gt JP16 T T RESET ABORT weTouriE Jos on amp IRQ7 TOUTOE JP13 semiconductor ZIGBEE Capable XCVR The MC13192 interfaces to the MCF5208 via the QSPI lines and some GPIO signals The additional GPIO are required to realize the full functionality of the MC13192 chip The signal connections are shown below Table 12 MC13192 Connections M5208EVBUM pdf MCF5208 Signal MC13192 Signal QSPI_CLK SPICLK QSPI_DIN MISO QSPI_DOUT MOSI UORTS QSPI_CSO RTXEN U1RTS QSPI_CS1 ATTN QSPI_CS2 CE RSTOUT RST IRQ1 IRQ TS GPIO1 OUT_OF_IDLE FB_CS3 GPIO2 CRC_VALID 1 Sep 5 For information on communicating with the MC13192 refer to the MC13192 Data Sheet and MC13192 Reference Manual The SMAC source code shows using the MC13192 transceiver in a simple application FCC Certification This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 3 This device may not cause harmful interference and 4 This device must accept any interference that may cause any undesired operation This e
25. ameter is set then dBUG monitor will run the program it has saved in flash By default this program is uClinux but can be replaced with any user program If BOOTSEL is negated JP3 is OFF then dBUG monitor will present the dBUG prompt at the console and await user input Figure 6 Boot Select Jumper BOOTSEL JP3 M5208EVBUM pdf 8 1 Sep 5 Clock Input There are 3 options for providing the clock input to the MCF5208 Table 6 shows valid combinations of settings for SW1 2 JP5 JP11 and JP12 to select the clock input Figure 7 as shown in Table 6 Figure 7 Clocking Selection Crystal FLASH TOUT3E TOUT2E TOUT1E TOUTOE Oscillator EXT CLK z gt Clock Select Jumpers PLL Disable Table 6 Clock Source Selection SW1 2 JP5 JP11 JP12 Clock Selection i OFF 1 2 16MHz Crystal OFF ON 1 2 16MHz Crystal ON ON 1 2 2 3 16MHz Oscillator ON ON 1 2 2 3 External Oscillator Warning Using any combination of settings not included in this table can damage the PLL circuit on the MCF5208 Ensure that only these combinations are used when power is applied to the board M5208EVBUM pdf 1 Sep 5 Serial Ports The M5208EVB has two COM ports with RS232 level signals They normally connect to a host PC Figure 8 M5208EVB Serial Ports o 2 freescale EXT CLK semiconductor X Intec Automation Inc www steroidmicros com Oscillator osc E EXTCLK o
26. any product to improve reliability performance capabilities design or ease of use or to reduce size or cost Intec Automation Inc products may not be used as components in life support devices of any description M5208EVBUM pdf 1 7 Sep 5 Safety Information FCC Certification This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference and 2 This device must accept any interference that may cause any undesired operation This equipment has been tested and found to comply with the requirements of ETSI EN301 489 1 V1 4 1 It bears the CE marking for sale and operation within Europe NOTE This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his her own expense IC Certification Operation is subject to the following two conditions 1 this device may not
27. are located in opposing corners of the board U3 Green LED indicates 2V5 Shottky diode feedback to prevent 2V5 from exceeding 3V3 during shutdown 2 VOUT lt 10uF 0 5R PES 10uF 0 5R 0 4V 1a 30Vmax Core and PLL supply voltage 1V5 Regulator 200mA max I U U l D6 ug i U U l l 0 4V 1a 30Vmax Q vour ro SPX1117M3 10uF 0 5R 10uF 0 5R Power Supply TITLE MS2Q8EVB_Rev_B Document Number REV Date 8 30 2005 12 20 51p Sheet 4 13 Reset Configuration 166 67 83 33 MHz operation 88 44 MHz operation Mode 1 Oscillator bypass mode U rystal oscillator mode 32 bit port 16 bit port O Normal P mode 1 16 67 MHz So tem A 23 22 CS 5 4 Arrows indicate default settings Setting D1 0 will run DDR out of spec LVX573 DATA D 0 31 To DDR in To Flash amp SRAM heat TITLE M5208EUVB_Rev_B Document Number Date 8 30 2005 12 20 51p Place U4 close to U1 to minimize trace lengths between Insert 22ohm damping resistors between MPU and PHY if signals are of significant length 10uF 6 3V 25MHZ_OUT MDIO MDC VDD33 IC CRS LED_CFG PFBOUT COL PHYADO TD TD TEN TXDO RD RD LED_ACT AN_EN LED_SPEED AN1 LED_LINK ANO FEC_TXER FEC_TXCLK RXDV MIL_ MODE RSV FEC_RX RXDO PHYAD1 FEC FEC FEC FEC_RXD3 FEC_RXER FEC_RXCLK MCF5208 FEC PWR_DWN INT RESET PHY Configuration PHY Address 0001 PHYADI 4 1 0000 internal PD PH
28. as directed by the program information block at the top of flash M5208EV BUM pdf 20 1 Sep 5 If Autorun has been set and the user wishes not to have the program run automatically remove the jumper from JP1 Under this configuration BUG will always boot to the BUG prompt Table 10 shows the possible settings and their actions out of reset Because the program is copied to DRAM and executed from there it must be linked for execution from DRAM Table 10 dBUG Boot Configuration Action JP3 Autorun Boot to dBUG gt OFF Boot to dBUG gt ON OFF Autorun user program typically uClinux ON ON As shipped the user program on the M5208EVB is uClinux When JP1 is fitted dBUG monitor will load uClinux into DDR SRAM and run it uClinux can be configured to load a user program saved in the flash file system etc rc is a script that is executed upon booting uClinux This script should contain the path and name of the program to be run automatically Initially etc rc contains usr interactive_demo which serves a number of web pages including an interactive page that allows the user to interact with the 4 timer LEDs on the M5208EVB Memory Mapping The M5208EVB memory map is shown below in Figure 19 Any memory access to a location not specified in Figure 19 is an undefined operation and may result in a bus access error and should be avoided This memory mapping is dependent on a user program being li
29. ax asm lt lt addr gt lt assembly gt gt bc addr1 addr2 length bf begin end data lt inc gt bm begin end dest br lt addr gt lt cit lt value gt gt lt r lt addr gt gt lt i gt bs begin end data dc data dis lt addr gt dl lt offset gt dn lt cieliis lt o offset gt gt lt filename gt fl lt operation gt go lt addr gt gt addr help lt cmd gt lr addr lw addr data md begin lt end gt addr lt data gt register reg data reset reset Press lt ENTER gt to continue Connected 0 01 13 Auto detect 115200 8 N 1 dBUGmonitor pdf C 1 5 Sep 05 dBUG and Autorun On startup dBUG checks if JP3 is installed and if it is then dBUG attempts to boot a program stored in external flash A program can be stored into external flash by using the dfl or dnfl commands detailed below and in the dBUG user manual The World as Seen by dBUG dBUG resides in the bottom 256K of the M5208EVB external flash On startup BUG maps the 16MB SDRAM and accesses it as follows e It sets up DDR SDRAM from 0x40000000 to 0x41 FFFFFF e It uses the lower 128K of SDRAM that is 0x40000000 to 0x4001FFFF for its vector table data and stack Consequently this memory space is out of bounds to the user program e It expects the user program to always start at 0x40020000 in SDRAM e A user program can use the MCF5208 s on chip SRAM for stack space since it is very fast and dBUG does not use this m
30. cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device L utilisation de ce dispositif est autoris e seulement aux conditions suivantes 1 il ne doit pas produire de brouillage et 2 2 l utilisateur du dispositif doit tre pr t accepter tout brouillage radio lectrique re u m me si ce brouillage est susceptible de compromettre le fonctionnement du dispositif NOTE The abbreviation IC before the registration number signifies that registration was performed based on a Declaration of Conformity indicating that Industry Canada technical specifications were met It does not imply that Industry Canada approved the equipment Caution CAUTION This device is susceptible to electrostatic discharge ESD and surge phenomenon Always use ESD precautions when handling this device CAUTION Changes or modifications to this equipment not expressly approved by the manufacturer could void the user s authority to operate the equipment M5208EVBUM pdf ii 7 Sep 5 Table of Contents i Warranty Glen OT DISClAmMErsi saint nine items 1 Safety Information sinon Mon Noire FO Certifications sister rente emilie in sn iaia iaia il IC CS rt CAI OM fetali han Dre re nee il LS ani Leni on an ND Lari leoni il Table of Contents iii MI CAOS aaa N l i Tae ELATI E SA tic A E T E EEEE A x TYS TTG T TTS MS20
31. emory Using dBUG Setting dBug Parameters dBUG stores several parameters on the SBC that determine dBUG s behaviour Resetting or repowering the board will not affect the values of these parameters e Base The numeral base used by dBUG for entry and display of all numbers 16 e Baud The baud rate shared by the SBC s Primary and Secondary serial connection 115200 Setting Board Parameters dBUG stores several parameters on the SBC that determine the SBC s behavior Resetting or repowering the board will not affect the values of these parameters Some of these parameters are e Watchdog When On the watchdog timer is left enabled on the MCF5208 and must be fed by the user program or the watchdog will reset the board after 5 seconds e Server The IP address of a PC running a TFTP server This setting is used for network downloads e Client The IP address of the board e Gateway The IP address of the gateway for the LAN that the board is connected to e Netmask The netmask of the LAN that the board is connected to e DNS The IP address of a DNS server used for resolving a URL to IP address e Ethaddr The MAC address dBUGmonitor pdf C 2 5 Sep 05 The values of these parameters can be displayed on the console screen with the show command Each value can be individually set using the set command The set command takes two parameters the name of the parameter and the new value of the parame
32. et 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Revision History 30 Aug 05 G Rouse Changed U3 to ST LD29080 Changed U9 VIN to 3V3 Removed unnecessary jumpers Renamed jumpers Added 10K pullup to ATTN Rationalized resistors into resistor packs Renamed MCF5208 signal names for consistency with MCF5208RM pdf M5208EUB Evaluation Board TITLE M52068EUB_Rev_B Document Number REV Date 8 30 2005 12 20 51p Sheet 1 13 Place these 22ohm resistors and 4x resistor packs Decoupling Caps as close to U1 as possible gt A 5 so CkE 592 so uk High and low data bytes are swapped to minimize routing Bits within high and low data byte are shuffled to minimize routing a Place these 4x22ohm resistor packs D_DQ U6 D_DQ centrally between U1 and U6 peles I upas LDAS V lt 7 U1_DATA Dats 1 21 CO gt HE DATA D 0 31 IW DQ10 bag DOS DQ7 U1_ADDR Da DQ4 DQ3 DQ2 DO DQO vb EE EE EO EO EO CO CO HE gt gt co ko C Place these 22ohm resistors and 4x resistor packs EF as close to U1 as possible _52 MCF5208 Data Lines MT46V16M16 GND GND Place these componets U6 is a 16MB DDR SDRAM chip as close to U6 as possible Equivalent DDR SDRAM chips are Micron MT46V16M16TG 6TF ICSI IC43R16160 6TG MCF5208 Addresses Traces between U1 and U6 should be as near equal length as possible Preferably within 2cm DDR SDRAM
33. f CN2 Figure 10 BDM JTAG Set Up for BDM freescale EXT CLK semiconductor u Intec Automation Inc i Ger PSTCLK oscE EXTCLK g To CN2 24 JP 11 L 1 5 Select BDM The BDM header also serves as a port for JTAG signals if the 0 ohm resistor on J1 is soldered across pads 2 3 Chapter 27 IEEE 1149 1 Test Access Port JTAG of the MCF5208 Reference Manual describes the functions of the JTAG signals In JTAG mode JP1 should be fitted across pins 2 3 to connect TCLK PSTCLK configured as TCLK to pin 6 of CN2 Figure 11 BDM JTAG Set Up for JTAG Lo freescale EXT CLK semiconductor Intec Automation Inc US 7 WWW Steror OM TCLK Oscillator osc E EXT CLK To CN2 24 JP 11 o zZ 5 L Ji BDM 1JTAG Select JTAG mo 2 Crystal D RSTOUT M5208EVBUM pdf 12 1 Sep 5 1 O Header One header provides access to a number of the MCF5208 s signals The location of CN1 is shown below in Figure 12 Figure 12 CN1 I O Header 32MB DDR SDRAM ZIGBEE Capable XCVR III UART1 AUX TOUT3E jP16 lt TOUT2E 615 E RESET TOUT1E J 4 ON J TOUTOE JP13 CN1 I O Header CNI is a 2x8 double row header that provides access to the DMA timer QSPI IRQ and I2C signals All these signals can also be configured as general purpose I O A mapping of these signals and their associated functions is shown in Table 8 Table 8 CN1 I O Header Pin Mapping
34. ge information for the shutdown command uClinuxCommands pdf C 3 5 Sep 05 Appendix E uClinux Drivers M5208EVBUM pdf E 1 Sep 5 uClinux Device Drivers The following sections describe the various device drivers in uClinux that are importance to user application development There are other drivers available in the dev directory that are not included in this list because they are exclusively used by the kernel ips IPS The ips driver has been developed by Intec to support the run time library under uClinux The internal peripheral system 1ps driver provides user applications with access to the hardware registers User applications should never use the ips driver directly but instead simply call functions from the run time library provided mtd x mtdblock x External Flash The memory technology device mtd driver is for accessing the external flash device On the Wildfire board this device provides access to the on board serial flash To make use of the mtd driver a file system should be mounted on top of it The Journaling Flash File System JFFS2 is designed for these type of flash devices which require sector erases before writes To use the mtd driver issue the following command at either the command line or from the rc file done by default with the M5208EVB as shipped in the etc rc file 1 Create a directory if not already created gt mkdir mnt flash 2 Mount the file system gt mount t jffs2 dev mtdblock
35. new soon to be released PHY chip from National Semiconductor the DP83848 It can auto negotiate connection speed and can switch its Tx and Rx lines to suit the polarity of the connection Auto MDIX feature Crossover Ethernet cables are never required The RJ45 connector has 2 LEDs which convey information as summarized in Table 11 Table 11 Ethernet Indicator LEDs LED State Significance Speed On 100Mbps Off 10Mbps Link Traffic On Good link Blink Traffic Off No link Figure 20 Ethernet Connector Speed LED National Semi DP83848 PHY Link Traffic LED Advanced Users The Ethernet PHY chip on board is configured to support Auto negotiation of 10 and 100 base T speeds full duplex and half duplex connections The MII interface to the PHY chip is connected to the MCF5208 MII serial management allowing the MPU complete control over the PHY The PHY has an address of 0x01 For further information about the PHY and its internal registers see the National Semiconductor DP83848 PHY Data Sheet The physical Ethernet interface PHY can be accessed under uClinux using a command line tool called mii tool M5208EVBUM pdf 24 1 Sep 5 ZigBee Capable Transceiver A MC13192 ZigBee Capable Transceiver chip and printed circuit board antenna have been integrated on the M5208EVB to demonstrate the ease of integration of this ZigBee capable transceiver with the MCF5208 Figure 21 ZigBee Cap
36. nfigured as GPIO through the GPIO module See the MCF5208 Reference Manual Ch 13 General Purpose I O Module for more information M5208EVBUM pdf 17 1 Sep 5 FC The LC module is 2 wire serial bus used for communication with I2C devices serial flash real time clock etc The IC signals SDA and SCL are brought out to pins 13 and 14 on CNI These signals are configured through the 12C module on the MCF5208 These signals are shown in blue in Figure 16 Figure 16 I2C Signals on CN1 SCHEELE RARES a le TOUT3E spre l TOUT2E p15 ABORT wetouTiE Jp14 Z TOUTO E JP13 M5208EVBUM pdf 18 1 Sep 5 Memory and Storage The M5208EVB has 4 types of memory available to the user e 16KB Internal on chip SRAM e 128KB External SRAM optional e 32MB External DDR SDRAM e 2MB External Flash Figure 19 shows the memory mapping of these memory blocks All the external memory devices run and interface at 2 5V This allows a single bus to interface all devices without the need for buffers Internal SRAM The MCF5208 s 16KB on chip SRAM is fast single cycle memory making it ideal for the user program stack BUG monitor initially maps the internal SRAM to 0x80 00 00 00 External SRAM Pads for a 2 5V 64K x 16 bit SRAM IDT IDT71T016SA12PH are located beneath the M5208EVB This part can be attached for benchmarking purposes It is driven by FB_CS1 External DDR SDRAM The M5208EVB has a fast 16M x 16 bit DDR SDRAM for both data st
37. nked with the Intec memory mapping and using the dBUG monitor M5208EVBUM pdf 21 1 Sep 5 Figure 19 dBUG M5208EVB Memory Map External Flash 2MB Vector Table 0x00000000 FB_CSO i 0x00003FFF Parameters 0x00004000 0x00005FFF 0x00006000 dBUG Code Data 0x0003FFFF Flash File System 0x00040000 and uClinux 0x001FFFFF 0x00200000 OxOFFFFFFF 0x10020000 Ox3FFFFFFF DDR SDRAM 32MB Vector Table dBUG Data Copied at boot 0x40000000 SD_CS 64K dBUG heap LLLLLLLL MM TEL D 3K dBUG Stack HEAP END 3k Unused 0x4001FFFF User Code 4444444 0x40020000 User Data 4444444 Unused Ox41FFFFFF 0x42000000 Ox7FFFFFFF Fast 0x80000000 Internal SRAM 16K TITTTTTA User Stack Typical 0x80003FFF 0x80004000 OxFBFFFFFF Peripheral Registers See Freescale MCF5208 Reference 0xFC000000 Manual for more information OxFFFFFFFF M5208EVBUM pdf 22 1 Sep 5 Watchdog Timer The MCF5208 has a Watchdog Timer WDT which can be used to reset the board in the event a program has entered an unexpected state When the watchdog timer is enabled it must be serviced periodically to ensure that it does not time out and reset the MPU Servicing consists of writing a 0x5555 and UX A A A A sequence to the Watchdog Service Register Once enabled the watchdog timer cannot be disabled without resetting the MPU M5208EVBUM pdf 23 1 Sep 5 Ethernet The M5208EVB supports 10 100 Ethernet through a brand
38. oltage Detection The ColdFire5208 processor does not have internal low voltage detection circuitry to detect intermittent power levels The voltage supervisor on the reset debounce circuit Sheet 11 of the schematic serves as a voltage supervisor that resets the processor if the external voltage 3 3V drops below 3 15V WARNING To avoid damage to the M5208EVB only attach a coaxial center positive 2 1 mm plug Draw from any power pin on a header to an external circuit in excess of 100ma may damage the board M5208EVBUM pdf 5 1 Sep 5 Reset There are 3 ways to reset the M5208EVB Power on reset accomplished by power cycling the board switch the power switch to the OFF position then back to the ON position or remove and reconnect the power cable The contents of all volatile memory RAM and SDRAM will be lost External reset asserted by pressing the Reset button or by issuing a reset command through the BDM pod using software on the PC The contents of volatile memory are preserved Software reset invoked with the reset command to dBUG monitor the reboot command in uClinux or by setting bit 7 in the RCR register see MCF5208 Reference Manual Chapter 10 Reset Controller Module The contents of volatile memory are preserved In all 3 cases when the board is reset all registers are reset to their default state Figure 5 Reset Signal and Switch Locations RSTI CA RC
39. or some of the legacy BDM cables that connect pins 9 amp 25 of the BDM interface internally More recent cables support both core amp I O voltages Please check with your BDM cable supplier The BDM cable supplied with the M5208EVB supports both core and I O voltages and requires JPS to be fitted M5208EVBUM pdf A 2 1 Sep 05 JP3 When fitted this jumper causes dBUG monitor to automatically load a program and run it Typically this program is uClinux as shipped See Appendix C and the SBCTools Programmer Reference for more information on the Autorun feature of dBUG monitor When this jumper is open BUG monitor will not run any user program and instead display the dBUG prompt on the terminal and wait for input JP4 When fitted this jumper disables the factory test mode of the MCF5208 This jumper is normally always fitted JPS When fitted this jumper asserts the RCON signal and causes the MCF5208 to load the CCR register based on the signals D9 D 7 1 These signals are conditioned out of reset by the DIP switch See the MCF5208 Reference Manual Ch 9 Chip Configuration Register for more information on the reset configuration JP6 This jumper selects between DDR and SDR mode for the SDRAM module Should always be fitted to support DDR mode JP7 When fitted connects 1 5V to the PLL filter and to JP8 JP8 When fitted connects the processor core voltage to 1 5V JP7 must also be fitted JP9 When fitted connects
40. orage and program execution Typically the user program is loaded from flash into SDRAM and run from SDRAM The program can also be loaded through a serial port or Ethernet External Flash External flash consists of a 2MB Am29BDD160G It is selected by FB_CSO This 2 5V flash is organized as 512K x 16 bits It is made up of 8 x 8KB sectors 30 x 64KB sectors and 8 x 8KB sectors A sector is the smallest block of memory that can be erased The M5208EVB s external flash is shipped pre loaded with the dBug monitor the uClinux kernel and uClinux services On start up the dBUG monitor is set up to check if there is an executable in flash If so it starts execution of this program which as shipped would be uClinux As shipped the flash memory map looks like Figure 17 uClinux is the default user program shipped with the M5208EVB A different user program may be saved into external flash using dBUG monitor at the expense of overwriting uClinux However uClinux may be restored painlessly into external flash at anytime by reprogramming the m5208evb s19 flash image with CFflasher Getting a program to run under uClinux is done through the RC file which is analogous to a DOS Autoexec bat file M5208EVBUM pdf 19 1 Sep 5 Programming Flash A user program can be programmed into flash using several techniques The dBUG monitor supports saving a program compiled to run from flash with the dl command See Appendix C dBUG Monitor for a descri
41. pages pre installed allowing it to serve web pages right out of the box M5208EVBUM pdf 1 1 Sep 5 Figure 1 M5208EVB Capabilities ETHERNET HUB Choice of Professional Development Tools BDM PORT DEVELOPER Background Debug Mode La freescale EXT CLK semiconductor Intec Automation Inc www steroidmicros com Oscillator EXT CLK B TERMINAL UARTO Crystal FLASH ColdFire M5208EV 32MB DDR SDRAM ZIGBEE Capable XCVR UART1 AUX fe al m TOUTSE u e TOUT2E Jpis x RESET ABORT mwrOUTiE 1914 POWER ON RA TOUTES JP13 7 14 VDC r CENTER LEVEL or EDGE INTERRUPT 3v3 a LE rm Nsg 3v3 Gnd o y II IL Ly Ta Tb Te Td COMPLEX I PULSE HA EN PATTERNS LS A o e E 14 f 1 I U UL LU COUNT PULSES MEASURE FREQUENCY M5208EVBUM pdf 2 1 Sep 5 M5208EVB Modules The M5208EVB is made up of modules Some modules correspond to on chip ColdFire peripherals Other modules correspond to on board peripherals and added features These modules are Power System 7 14VDC input regulated on board to provide necessary processor and peripheral voltages Reset Control circuitry and reset configuration switches Clock selection circuitry for on board crystal on board oscillator or external oscillator Serial module 2 level translated serial ports Background Debug Mode BDM port VO Header providing access to several MCF5208 signals for off board use DMA Timer module
42. per Settings Function JP1 1 2 Connect TCLK PSTCLK to pin 24 of BDM CN2 2 3 Connect TCLK PSTCLK to pin 6 of BDM CN2 JP2 ON _ Connect 1 5V to pin 25 of BDM CN2 OFF Disconnect 1 5V from pin 25 of BDM CN2 JP3 ON _ Boot uClinux or user program OFF Boot dBUG JP4 ON _ Disable TEST mode OFF Enable TEST mode JP5 ON _ Enable reset configuration OFF _ Disable reset configuration JP6 ON DDR mode OFF SDR mode JP7 ON Connect Core PLL filter to 1 5V OFF Disconnect Core PLL filter from 1 5V JP8 ON Connect Core to 1 5V w JP7 ON OFF Disconnect Core from 1 5V JP9 ON Connect MPU I O rail to 3 3V OFF Disconnect MPU I O rail from 3 3V JP10 ON Connect MPU External Bus to 2 5V OFF Disconnect MPU External Bus from 2 5V JP11 1 2 Clock source select Oscillator 2 3 Clock source select External oscillator CN7 JP12 1 2 Clock source select Crystal 2 3 Clock source select Oscillator JP13 ON Enable Disable TOUT3 LED OFF Disable TOUT3 LED JP14 ON Enable Disable TOUT2 LED OFF Disable TOUT2 LED JP15 ON Enable Disable TOUT1 LED OFF Disable TOUT1 LED JP16 ON _ Enable Disable TOUTO LED OFF Disable TOUTO LED JP1 Selects either pin 6 or pin 24 of the CN2 to be connected to the TCLK PSTCLK signal from the M5208EVB TCLK is used when JTAG mode is enabled PSTCLK is used when BDM mode is enabled see JTAG_EN JP2 This jumper is required f
43. personality out of reset when the RCON signal is held low JPS is fitted Table A 3 Reset Configuration Switch Functions SW1 1 PLL Mode OFF 166 67MHz Core bus 83 33MHz External Bus operation ON 88MHz Core bus 44MHz External Bus operation Note 1 SW1 2 Oscillator Mode OFF Crystal oscillator mode ON Oscillator bypass mode SW1 3 SW1 4 Boot Port Size OFF OFF 16 bit port OFF ON 32 bit port ON OFF 32 bit port ON ON 8 bit port SW1 5 Output Pad Drive Strength OFF High drive strength ON Low drive strength SW1 6 LIMP Mode OFF Normal operation PLL drives internal clocks ON LIMP mode low power clock divider drives internal clocks SW1 7 Oscillator Frequency Select OFF 16MHz is used as input to processor ON 16 67MHz is used as input to processor SW1 8 Chip Select Configuration OFF A 23 22 A 23 22 ONN A 23 22 FB_CS 5 4 M5208EVBUM pdf 1 Sep 05 LEDs The LEDs on the M5208EVB indicate the status of the board and can be used by user programs as indicators The LEDs colours and their functions are listed below Table A 4 LED Functions Signal LED Colour Description 2 5V Green External Bus power indicator 3 3V Green I O power indicator RSTOUT Red Reset indicator LED will light when the board is resetting IRQ7 Abort Button Red Abort indicator LED will light when IRQ7 is a
44. ption of this and other useful BUG commands Figure 17 2MB Flash with uClinux as Shipped dBUG monitor 0x00000000 0x0003FFFF uClinux JFFS2 File System 0x00040000 on EVB as shipped Ox000DFFFF Compressed uClinux kernel amp services 0x000E0000 linked for DDR SDRAM 0x001FFFFF dBUG monitor s dfl command allows the user to save an executable file to flash In order to execute this file dBUG first copies it to DRAM and then runs it from there Consequently the program must be linked to run out of DRAM With this command a flash program is stored at the top of flash just below a 32 byte program information block which allows dBUG to find the code come time to execute it The mapping of a user program in flash is shown in Figure 18 The total space consumed by any program is the size of the program 32 bytes rounded up to the nearest 64K sector boundary Figure 18 2MB Flash with User Program dBUG monitor 0x00000000 0x0003FFFF Data storage 0x00040000 0x000 X 1 FFFF User Program 0x000X0000 linked for DDR SDRAM 0x001FFFDF 0x001FFFEO 0x001FFFFF Running from Flash The gfl command will execute a program saved in external flash using the dfl command The program can also be run automatically when the board resets by setting the Autorun parameter to ON in dBUG If Autorun is set and JP1 is on dBUG monitor will attempt to run a program in flash
45. quipment has been tested and found to comply with the requirements of ETSI EN301 489 1 V1 4 1 It bears the CE marking for sale and operation within Europe NOTE This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his her own expense IC Certification Operation is subject to the following two conditions 3 this device may not cause interference and 4 this device must accept any interference including interference that may cause undesired operation of the device L utilisation de ce dispositif est autoris e seulement aux conditions suivantes 3 il ne doit pas produire de brouillage et 4 2 l utilisateur du dispositif doit tre pr t accepter tout brouillage radio lectrique re u m me si ce brouillage est susceptible de compromettre le fonctionnement du dispositif NOTE The abbreviation IC before the registration number signifies tha
46. racts serially with a console or debugger program on the PC It also interacts with the user program that runs on the SBC dBUG provides a mechanism for downloading running and debugging programs without a BDM pod It also stores board parameters such as the IP address handles user program boot up can handle user program interrupts and can act as an interface for the user program s console I O Basic concepts The dBUG Monitor is a versatile program that carries out a number of services and can be used in different ways dBUG and Serial Console Program A developer can interact directly with dBUG through any serial console program such as HyperTerminal using dBUG s command line interface That is a developer can load debug and run his program without the need of a specialized debug program dBUG offers a rich assortment of commands and in fact some commands can only be accessed through a console program The full list of BUG commands can be viewed by typing Help after the dBUG gt prompt when accessing the SBC through a serial console program e Com 1 115200 HyperTerminal File Edit View Cal Transfer Help De Description Assembly Block Compare Block Fill Block Move Breakpoint Block Search Data Convert Disassemble Download Console Download Network Flash Utilities Execute Execute To Help Loop Read Loop Urite Memory Display Memory Modify Register Display Register Modify Reset Ba Synt
47. rt Number Ref ID 1 ORO RES 0603 Rohm MCRO3EZPJ000 J1 9 22R0 4XRES603 CalChip CN34J220CT R22 R24 R30 R34 R35 R36 R37 R46 R48 6 22R0 RES 0603 Vishay CRCW0603 22ROFRT1 R26 R27 R28 R38 R39 R47 1 49 9 1 4XRES603 CTS 742C083510JTR R13 2 100 RES 0603 Rohm MCRO3EZHJ101 R2 R4 2 150 RES 0603 Rohm MCRO3EZHJ151 R8 R16 4 150 4XRES603 CalChip CN34J151CT R5 R7 R10 R11 1 11K5 RES 0603 CalChip RMO6F1501CT R51 1 4K87 1 RES 0603 CalChip RMO6F4871CT R1 1 10K RES 0603 Vishay CRCW0603 1002FRT1 R6 2 10K 1 RES 0603 Vishay CRCW0603 1002FRT1 R40 R41 7 10K 4XRES603 CalChip CN34J103CT R3 R9 R14 R20 R21 R32 R33 1 DIPSW DIPSW Amp Alco 435640 5 SWI 2 PBSWO5 PBSWO5 ITT Cannon KSC421G SW2 SW3 1 1101M2SXA 1101M2SXA ITC 1101M2S3AQE2 SW5 13 1x2 Header Mode 36 280G 0 2x40 straight double row jpo JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 JP13 JP14 JP15 JP16 3 11X3 Header Mode 36 140G 0 1x40 single strip JP1 JP11 JP12 1 2X8 Header Mode 36 280G 0 2x40 straight double row CN 1 1 2X13 Header Mode 36 280G 0 2x40 straight double row CN2 2 DB9F 90 DB9F 90 Mode 30 420 0 CN3 CN4 1 HFJ11 2450E RJ45MAG Tyco 5 1605473 7 CN6 1 PWR_J PWR_J Mode 31 155 0 2 1mm power jack CN5 1 ISMA SMA Amphenol 901 9894 RFX CN7 2 TEST LOOP TEST LOOP Keystone 5015 TP5 TP6 Appendix C dBUG Monitor M5208EVBUM pdf C 1 Sep 5 dBUG Monitor dBUG is a program that runs on the target SBC that inte
48. sserted TOUT3 Amber Timer GPIO LED LED off low LED on high TOUT2 Amber Timer GPIO LED LED off low LED on high TOUTI Amber Timer GPIO LED LED off low LED on high TOUTO Amber Timer GPIO LED LED off low LED on high Electrical Specifications The maximum source sink current on I O varies depending on the pin it is attached to Table A 5 shows the maximum source sink current on the I O header by pin M5208EVBUM pdf Table A 5 CN1 Drive Strength by Pin Drive Pin Drive Strength Strength 8 16mA 8 16mA 8 16mA 8 16mA 4mA 8 16mA 8 16mA 8 16mA 4mA 4mA 8 16mA 8 16mA A 5 1 Sep 05 Def Alt RTL Alt RTL Func Pin Function 3V3 GPIO DTOIN DMA Timer PIN GPIO DT2IN DMA Timer PIN GPIO IRQ F GPIO GPIO GPIO 3V3 Header Pinouts CN1 I O Header Alt RTL Function Alt RTL Pin Def Func DMA Timer 3 DMA Timer PIN1 PIN3 GND GPIO GPIO GPIO GPIO GPIO GPIO GND NOTE 1 To create the port name prepend EVB DIO PORT i e EVB DIO PORT TIMER is the constant used to access any of the DMA Timer pins as GPIO Alt Func Def Func GND GND GND GND M5208EVBUM pdf MCF Def Func Alt Func DSO PST3 PST DDATA3 DDATA1 GND CLKOUT TA 1
49. t registration was performed based on a Declaration of Conformity indicating that Industry Canada technical specifications were met It does not imply that Industry Canada approved the equipment Caution CAUTION This device is susceptible to electrostatic discharge ESD and surge phenomenon Always use ESD precautions when handling this device CAUTION Changes or modifications to this equipment not expressly approved by the manufacturer could void the user s authority to operate the equipment M5208EVBUM pdf 26 1 Sep 5 Tf this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Relocate the M5208EVB and reorient serial or Ethernet cables attached to it e Reorient or relocate the receiving antenna e Increase the separation between the M5208EVB and receiver e Power the M5208EVB from an outlet that is on a different circuit than the receiver M5208EVBUM pdf 27 1 Sep 5 Appendix A Jumpers Switches Pinouts amp Specifications M5208EVBUM pdf A 1 Sep 5 Jumpers Table A 1 lists each jumper and its function on the M5208EVB The default position of the jumper is shown in bold A quick reference of the jumper functions is silk screened onto the bottom side of the board Table A 1 Jumper Settings and Function Jum
50. t the timer itself Configuring a pin for its timer function will disable its GPI O function When timer signals are configured as digital outputs or as timer outputs they can be connected to LEDs through jumpers JP13 JP16 These jumpers are shown in Figure 13 As shown in Table 8 pins 3 6 on CNI are the DMA Timer pins A full description of the functions of these signals is in MCF5208 Reference Manual Ch 22 DMA Timers Figure 13 DMA Timer LED Locations ERREREREREEEEERE 9050 s HHE E i TOUT EX JP16 RE OUT2E 7 JP15 RESET ABORT mm OU11E spi4 ON gt RO Re OUT EF JP13 v mer GPIO Timef LEDs Timer Jumpers M5208EVBUM pdf 14 1 Sep 5 IRQ The MCF5208 EPORT module has 3 signals IRQ1 IRQ4 and IRQ7 that can be individually configured as digital inputs or outputs or they can be configured to be edge or level sensitive interrupt signals Ifa signal is configured for edge detection it can detect on a rising edge falling edge or both All IRQ pins are configured as digital input out of reset IRQ1 is used as in interrupt from the MC13192 ZigBee Capable Transceiver IRQ7 is connected to the Abort button on the M5208EVB When the board first starts up the dBUG monitor configures IRQ7 as a falling edge interrupt This leaves IRQ4 for user control The location of the Abort switch and IRQ4 pin is shown in Figure 14 Figure 14 Abort Switch and IRQ4 Locations E 5 L gt ORY BY e ES PES E E XCVR C
51. t to 0x40020000 in SDRAM and run it Killing Programs The kfl command will destroy a program stored in external flash If a valid program exists in the specified location then it is marked as dead and will not be run by either the Autorun feature or the gfl command dBUG Help More information can be found on dBUG by typing help at the command prompt The help command lists all the BUG commands and a description of the syntax of the command dBUG Updates To update dBUG use either the didbug command or the P amp E background debug module BDM with the CFFlasher program The M5208EVB is shipped with a combined dBUG and uClinux image The factory image can be found on this CD under Software Firmware directory m5208evb s19 dBUGmonitor pdf C 3 5 Sep 05 Appendix D uClinux Commands M5208EVBUM pdf D 1 Sep 5 Useful uClinux Commands The following commands are widely used on all Linux based systems including uClinux These are just a summary of useful commands more documentation can be found for each of these commands at http man linuxquestions org Also typing help at the uClinux prompt gt will provide a complete listing of the command available File System Manipulation ls list directory contents cd change directory mkdir make directory rm remove file rmdir remove directory cp copy a file mv move a file cat view a file on standard output mount mo
52. ter Downloading Programs User programs can be downloaded to the M5208EVB via the serial connection or a network connection A serial download is done using the dl command The dl command puts the dBUG monitor into a state where it waits for an s record download of the user program Using HyperTerminal click on Transfer gt Send Text File and select the s record to download dBUG stores the program starting at 0x40020000 A network download is done using the dn command Before the dn command can be issued the dBUG parameters must be set correctly The necessary parameters are Server Client Gateway Netmask Filename Filetype and Ethaddr Once these are set issuing the dn command will download the specified file from the specified server IP address Programming Flash The dfl command is used to program the permanent storage on the M5208EVB This command behaves exactly like the dl command but adds the feature of saving the downloaded program to external flash For example to save a program to the external flash a user types dfl presses return then transfer the s record as with the dl command Running Programs A program is run using the go command with a start address 0x40020000 or the gfl command Programs compiled for BUG should always start at address 0x40020000 The gfl command will determine if a program is present in external flash and then it will copy i
53. th OFF High drive strength ON Low drive strength SW1 6 LIMP Mode OFF Normal operation PLL drives internal clocks ON LIMP mode low power clock divider drives internal clocks SW1 7 Oscillator Frequency Select OFF 16MHz is used as input to processor ON 16 67MHz is used as input to processor SW1 8 Chip Select Configuration OFF A 23 22 A 23 22 ON A 23 22 FB_CS 5 4 NOTE Default setting for each switch is OFF Table 5 Default RCON Values RCON 1 JP5 OFF Selection Default Mode PLL Mode 88MHz Core bus 44MHz External Bus operation Note 1 Oscillator Mode Crystal oscillator mode Boot Port Size 32 bit port Output Pad Drive Strength Low drive strength LIMP Mode Normal operation PLL drives internal clocks Oscillator Frequency Select 16MHz is used as input to processor Chip Select Configuration A 23 22 A 23 22 Note 1 Caution Loss of Functionality Running the PLL at 88 44MHz will run the DDR out of spec The DDR will be inaccessible under this configuration M5208EVBUM pdf 7 1 Sep 5 Boot Select This jumper determines whether the dBUG monitor executes a program in flash or whether dBUG remains as the only active program When the M5208EVB powers on dBUG monitor immediately initializes the board Then it looks to the BOOTSEL signal to determine its behavior BOOTSEL is tied to JP3 If BOOTSEL is asserted JP3 is ON and the board s Autorun par
54. unt a file system on top of a device o e g gt mount t jffs2 dev mtdblock1 mnt flash smbmount mount a remote file share o e g gt smbmount 192 168 2 98 wokspace mnt workspace o username Mike password mike sync synchronize cached files in RAM to disk Network ifconfig The ifconfig command is used to view and edit network information such as IP address and subnet mask ifconfig eth0 display IP address and other network parameters ifconfig eth0 ip netmask netmask Set IP address to ip and netmask to netmask ifconfig h display help on the ifconfig command uClinuxCommands pdf C 1 5 Sep 05 route The route command is used to view or edit network routing information e route display network routing table e route add default gw gateway Add the default gateway to the routing table e route h diplay help for the route command mii tool The mii tool command is used to get and set low level physical information from the network interface such as speed and duplex e mii tool display the physical Ethernet properties e mii tool v display more information verbose e mii tool v v most verbose setting includes raw dump of PHY chip registers in Hex e mii tool restart reset the physical Ethernet interface chip e mii tool h help for the mii tool command Date Time date The date command will show or set the system date as kept by the kernel while

WildFire Users` Manual - Freescale Semiconductor

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